Texas Instruments DAC7741EVM Network Card User Manual
Contents
1. AERA 1 15V VCC VSS VDD CLD OUT 19 5 INSTRUMENTS 12500 TI Boulevard Dallas Texas 75243 Title Engineer J PARGUIAN DAC7741 DOCUMENTCONTROL Drawn By 6443168 REV A FILE DACT741 Sch DATE 27 Sep 2002 SIZE SHEET 1 OF 1 62. e eo e eo LANE GND P SPLIT DAC 741 2 3 Physical Description Figure 2 3 Layer 3 Power Plane O e Qe 4 PLANE R 5 LIT POW gt 3 LAY REU A 2 4 PCB Layout Figure 2 4 Layer 4 Bottom Plane 0000000100000008 is lt lt 1 s 000 nine m 8 MS 3 1000000101 LAYER 4 REV DAC 741 2 5 Physical Description PCB Layout Figure 2 5 Drill Drawing 2 6 224 1400 2200 3400 11 6017 1 112 2 2 Bill of Materials Table 2 1 Parts List Bill of Materials Item Qty Designator Manufacturer Part Number Description 1 1 C8 Panasonic ECJ3VB1C0105K 1 1206 multilayer ceramic capacitor 2 2 C9C10 Panasonic ECUV1H103KBM 0 01 uF 1206 multilayer ceramic capacitor 3 5 C1C2C3C7 Panasonic ECJ3VB10104K 0 1 uF 1206 multilayer ceramic C13 capacitor 4 1 C12 Panasonic ECUV1H102JCH 1 nF 1206 m
3. 1 3 EVM Basic Functions The DAC7741 EVM is a functional evaluation platform to test certain functional characteristics of the DAC7741 digital to analog converter Functional evaluation of the DAC device can be accomplished with the use of any microprocessor TMS320VC33 DSP or some sort of a waveform generator The headers J1 J2 and J3 are provided to channel in the necessary control signals and data needed to interface a microprocessor microcontroller 115 DSP starter kit or waveform generator to the DAC7741 EVM through a custom cable A specific adapter interface card is also available for most of 115 DSP starter kit DSK and the card model depend on the type of the DSP starter kit to be used The user must specify the DSP used as an interface to acquire the right adapter interface card Call or email TI for more information regarding the adapter interface card The output of the DAC can be monitored through two different access points which are as follows a BNC connector J5 if installed and also a header through pin 2 of J4 The 6 pin header W13 provides different options of the DAC output but requires the output op amp U2 to be configured correctly first for the desired waveform characteristic Shorting pins 1 and 2 of W13 allows the user to monitor the raw output of the DAC7741 EVM Overview 1 3 EVM Basic Functions Figure 1 1 EVM Block Diagram DAC Out W13 A block diagram of the EVM is shown below in
4. adios 3 1 3 1 Factory Default Setting 3 2 3 2 Host Processor Operation 3 3 3 244 Unity teens 3 3 3 22 Of efe 2 eee dade 3 4 3 2 3 Capacitive Load 914 3 4 3 3 Jumper Setting aba ened A ie 3 5 3 4 PSCHOMALUCS duse lesen act A ae e deme 3 7 EVM Block Diagram 1 1 1 4 1 4 Layer One Top 2 2 Layer Two Ground Plane 2 3 kayet 3 Power Plane siu 55 eee nrw 2 4 Layer 4 2 5 1141 1 EM MEER 2 6 Tables 2 1 3 1 3 2 3 3 3 4 3 5 vi Parts reds ire uen we at Peel deities Os Pre setas 2 7 Factory Default Jumper Setting 3 2 Unity Gain Output Jumper Settings 3 3 Gain of Two Output Ju
5. and J12 1 or through J7 6 and J7 8 terminals and is referenced to analog ground through J10 2 J12 2 and J7 1 terminals A dc source of 15 V supply is required to provide the rails for the external output op amp provided for output signal conditioning or boost capacitive load drive and for other output modes of application The 15 V supply connects through J10 1 or J7 2 terminal and the 15 V supply connects through J10 3 or J7 4 terminals The 15 V supply is referenced to ground through J10 2 or J7 3 terminals The supply source for Voc and Vgs can also be used as the supply source for 15 V and 15 V respectively To avoid potential damage to the EVM board make sure that the correct cables are connected to their respective terminals as labeled on the EVM board Stresses above the maximum listed voltage ratings may cause permanent damage to the device 1 2 2 Reference Voltage Although the DAC7741 has a built in 10 V voltage reference an external reference circuit is provided in the EVM board The external reference circuit can be isolated if the internal reference voltage is selected The 10 V precision voltage reference is provided to supply the external voltage reference for the DAC through REF102 U3 via jumper W4 by shorting pins 1 and 2 An adjustable 100 kQ potentiometer R11 is installed in series with 20 kO R10 to allow the user to adjust the reference voltage to its desired settings TP1 and TP2 are also provided as w
6. the Figure 1 1 1 4 15 V 15V 15 V GND 15 V GND VCC External VDD Reference VSS 14 Module Output Buffer Module LDAC REFIN RST Ext Ref RSTSEL REF REFS 2 DAC Module cs R W TP2 0 DB15 MSB DB1 LSB Chapter 2 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module Topic Page 2 1 Layout e E 2 2 2 2 Materials 2 7 2 1 21 Layout The EVM is constructed on a four layer printed circuit board using a copper clad FR 4 laminate material The printed circuit board has a dimension of 99 06 mm 3 90 inch x 104 14 mm 4 10 inch and the board thickness is 1 57 mm 0 062 inch Figures 2 1 through 2 6 show the individual artwork layers Figure 2 1 Layer One Top Silkscreen 2 2 4 _ 0111111010111101 w g oH N DAC7741_REU A 6443167 PCA 6443169 6443166 ntu 15U AGND 1 C7741 REU fi LAYER 1 SILKSCREEN PCB Layout Figure 2 2 Layer Two Ground Plane
7. 1 105 01 S D VS 3A Isolated power header see Note 26 10 W6 W7 W8 Samtec TSW 102 07 L S 2 Position jumper 0 1 spacing wg W10 W11 W14 W15 W16 W17 27 6 W1 W2 W3 Samtec TSW 103 07 L S 3 Position Jumper_ 0 1 spacing W4 W5 W12 28 1 R9 Bourns 3214W 203E 20 BOURNS_32X4W Series 5T pot Note P1 P2 P3 P4 P8 amp P9 parts are not shown in the schematic diagram All the P designated parts are installed in the bottom side of the PC Board opposite the J designated counterpart Example J1 is installed on the topside while P1 is installed in the bottom side opposite of J1 Physical Description 2 7 Bill of Materials This page has been left blank intentionally 2 8 Chapter 3 EVM Operation This chapter covers in detail the operation of the EVM to provide guidance to the user in evaluating the onboard DAC and how to interface the EVM to a specific host processor Refer to the DAC7741 data sheet SBAS248 for information about its parallel interface and other related topics The EVM board is factory tested and configured to operate in the bipolar output mode Topic Page 3 7 S Factory Default Setting 2222222 3 2 3 27 3 3 353 3 5 3 4 Schematic osse EET 3 7 3 1 Factory Default Setting 3 1 Factory Default Setting The EVM board is set to its default configuration from fa
8. 49 5 INSTRUMENTS DAC7741EVM User s Guide October 2002 DAP 5 SLAUO93 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to 115 terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with 5 standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intell
9. EMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the EVM User s Guide and specifically the EVM Warnings and Restrictions notice in the EVM User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For further safety concerns please contact the TI application engineer Persons handling the product must have electronics training and observe good laboratory practice standards No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 15 V and the output voltage range of 10 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input r
10. I is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use As such the goods being provided may not be complete in terms of required design marketing and or manufacturing related protective considerations including product safety measures typically found in the end product incorporating the goods As a prototype this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive Should this evaluation kit not meet the specifications indicated in the EVM User s Guide the kit may be returned within 30 days from the date of delivery for a full retund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE IND
11. S 24 23 Dis as DB14 RW 22 21 59 2813 LDAC 010 10 DE 20 19 DB12 zer p I 18 17 D8 Dii 31 pr 39 RST D7 210 30 43 __ RSTSEL 16 15 55 59 5g 0810 RSTSEL 3 5 14 13 DB9 VCC R13 CS D5 D8 28 R14 x1 2 SW 42 2 40 75 D4 D7 27 087 vss 2 10k 10k EN 4 d D3 D6 2257 RI WAC 5 610 5 6 2 5 21 46 10K 1 RST ae 7 28 22 25 01 D4 20 d RSTSEL 4 10 S 49 10 x DO D3 19 4 REF en 11 12 27 4 D 18 083 Vref 11 12 44 14 LE Di 082 1 13 14 KK 15 16 DB1 9 15 16 DO 1 Roffset 17 18 17 VDD 19 20 X 19 20 38 VDD R3 R7 REFout 45 0 5K 20K 100K 8 47 REFin RFB1 53 lt 0 1 CO CETT AB o VOUT 108 unc 7 ___ DAC_VOUT 26 test FEFEN 4 37 AND 7 AGND VDD 7741 DAC_VOUT 4 0 274 15V RS 14 5 lt exREFin 446 5 10K 5 12 EK 14 13 TRIM OUT S amp H 16 15 V TEMP i 18 17 _ 7110 162 Tantalum EE NC 3 REF102AU 8 0 EXTERNAL REFERENCE exREFin 2 R10 20K VDD 15V 15V VCC VSS J6 v 1 2 1 2 V 4L 4 5 6 5 6 E 011 D LU LLL ni 9 10 9 10 lt bad NI lt 1 1
12. ange please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than xxx C The EVM is designed to operate properly with certain components above xxx C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated Preface Read This First About This Manual This user s guide describes the characteristics operation and the use of the DA7741 evaluation module It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports The physical PCB layout schematic diagram and circuit descriptions ar
13. ctory as described on the table below to operate in bipolar 10V mode of operation using the internal reference Table 3 1 Factory Default Jumper Setting Reference Position Function OPEN External reference is disconnected from the negative input of U2 to configure U2 for unity gain OPEN Configure U2 op amp for unity gain OPEN RSTSEL pin is tied high to set DAC reset value to midscale OPEN RST pin is tied high by default 3 2 Host Processor Operation 3 2 Host Processor Operation The host processor basically drives the DAC so the DACs proper operation depends on the successful configuration between the host processor and the EVM board In addition a properly written code is also required to operate the DAC A custom cable can be made specific to the host interface platform The EVM allows interface to the host processor through J2 and J3 header connectors for the control signals and J1 header connector for the data input The output can be monitored through the J5 BNC connector if installed or J4 header connector An interface adapter card is also available for specific DSP starter kits as mentioned in Chapter 1 of this manual The EVM includes an optional signal conditioning circuit for the DAC output through an external operational amplifier U2 This is set to a unity gain configuration by default Regardless the raw output of the DAC can be probed through W13 pin 2 so that it can be compared with the
14. e included How to Use This Manual This document contains the following chapters Chapter 1 EVM Overview Chapter 2 Physical Description 3 Chapter 3 EVM Operation Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully Trademarks Related Documentation From Texas Instruments To obtain a copy of any of the following TI documents call the Texas Instru ments Literature Response Center at 800 477 8924 or the Product Informa tion Center PIC at 972 644 5580 When ordering identify this manual by its tile and literature number Updated documents can also be obtained through our website at www ti com Data Sheets Literature Number DAC7741 SBAS248 REF102 PDS 900E OPA627 PDS 998H Questions about this or other Data Converter EVM s FCC Warning Trademarks If you have questions about this or other Texas Instruments Data Converter evaluation modules please feel free to e mail the Data Converter Application Team at dataconvapps list ti com Please include in the subjec
15. ectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated EVM IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation kit being sold by T
16. either the onboard adjustable reference or user supplied reference to supply the DAC reference voltage Routes the onboard 10 V reference through the adjustable pot to W3 and W14 Routes the user supplied reference from TP1 or J4 20 through the adjustable pot to W3 and W14 Negative supply rail of op amp is powered by 15 V Negative supply rail of op amp is tied to AGND REFAD J pin is not connected pin is connected to R1 pot for gain adjustment input when internal reference is used RFB2 pin is not connected to the pin RFB2 pin is strapped to the Vout pin for feedback TEST pin not connected to DGND TEST pin connected to DGND default mode SJ summing junction pin of the DAC output amplifier is not connected SJ Summing junction pin of the DAC output amplifier is connected to R2 pot to allow small amount of current for offset adjustment RFB1 pin is not connected RFB1 pin is strapped to RFB2 for DAC Vout feedback EVM Operation 3 5 Jumper Setting Table 3 5 Jumper Setting Function Continued Reference Jumper Function Setting Disconnects AGND from DGND Connects AGND and DGND together 3 Positive supply rail of op amp is powered by 15V ele W12 33 Positive supply rail of op amp is powered by Voc Routes the raw output of the DAC7741 to J4 2 and J5 output terminals Routes the output of U2 to J4 2 and J5 output terminals Used for unipo
17. ell as J4 20 to allow the user to connect other external reference source if the onboard reference circuit is not desired The external voltage reference should not exceed 10 V dc EVM Basic Functions The REF102 precision reference derives its power of 15 V supply through J10 or J7 terminal The plus 15 V connects through J10 1 or J7 2 terminals while the minus 15 V connects through J10 3 or J7 4 terminals They are both referenced to analog ground through J10 2 and J7 1 The DAC7741 has a REFEN pin to enable the internal reference circuit or disable it and select an external reference source The REFEN pin can be hardware driven through W2 jumper Likewise it can also be software driven through 42 11 terminal W2 jumper by shorting pins 1 and 2 The REFout pin of the DAC7741 must be connected to the REFIN pin to use the internal voltage reference This can be done through jumper by shorting pins 1 and 2 Shorting pins 2 and 3 of W3 selects the external voltage reference source The on chip reference buffer output is channeled out through pin which is used to set up the DAC7741 output amplifier into one of three voltage output modes can also be used to drive other system components that require external voltage reference When applying an external voltage reference through TP1 or J4 20 make sure that it does not exceed 10 V maximum Otherwise this can permanently damage the DAC7741 U11 device under test
18. ifier When the DAC7741 is configured to operate in bipolar mode the DAC output must be within the range of 12 Vp p or less Anywhere above the range of 12 Vp p would clip the output of the op amp Likewise when operating the DAC in unipolar mode the DAC output must not exceed 6 Vp p Table 3 3 shows the proper jumper settings of the EVM for the 2x gain output of the DAC Table 3 3 Gain of Two Output Jumper Settings Jumper Setting W5 1 2 Bipolar Negative rail of the op amp tied to 15 V for bipolar operation or AGND 2 3 Unipolar for unipolar operation Positive rail supply of the op amp tied to 15 V Amplified output of DAC is channeled to the output terminals Opn Disconnect exREFin from negative input of op amp Configures op amp for a 2X gain output 3 2 3 Capacitive Load Drive Another output configuration option is to drive a wide range of capacitive load requirement However all op amps under certain conditions may become unstable depending on the op amp configuration gain and load value These are just few factors that can affect op amps stability performance and should be considered when implementing In unity gain the OPA627 U2 performs very well with very large capacitive loads Increasing the gain enhances the amplifier s ability to drive even more capacitance and by adding a load resistor would even improve the capacitive load drive capability Table 3 4 shows the jumper setting c
19. lar and bipolar modes of operation Routes the output of U2 to J4 2 and J5 output terminals Used for capacitive load driving Disconnects exREFin from the negative input terminal of U2 Allows exREFin to be routed to the negative input terminal of U2 used for experimentation purposes only Disconnect the negative terminal of U2 to AGND and disable 2x gain Configures U2 for a 2x gain output RSTSEL pin is pulled high and configures the DAC to midscale when POR or reset is initiated RSTSEL pin is pulled low and configures the DAC to minscale when POR or reset is initiated RST pin is pulled high and configures the DAC not to reset default state ST pin is pulled low and holds the DAC to reset state Legend ee Indicates the corresponding pins that are shorted or closed 3 6 Schematic 3 4 Schematic A schematic of the DAC7741 is found on the following page EVM Operation 3 7 1 2 3 4 5 6 Revision History REV ECN Number Approved n vss 32 31 015 30 29 C7 C5 D13 Ul 28 27 512 Dis 92 1 40 105 100 26 25 0815 C
20. mper 6 3 4 Capacitive Load Drive Output Jumper Settings 3 4 Jumper Setting Function 3 5 EVM Overview This chapter gives a general overview of the DAC7741 evaluation module EVM and describes some of the factors that must be considered in using this module Topic Page Features 1 2 1222 POWer Requirements m aa e a e 1 2 13 EVM Basic Functions 1 3 Features 1 4 Features This EVM features the DAC7741 digital to analog converter The DAC7741 EVM is a simple evaluation module designed for a quick and easy way to evaluate the functionality of the high resolution single channel and parallel input DAC This EVM features a parallel interface to communicate to any host processor base system 1 2 Power Requirements The following sections describe the power requirements of this EVM 1 2 1 Supply Voltage The dc power supply requirement for the digital section of this EVM is typically 5 V connected to the J11 2 or via J6 2 terminal when plugged in with another EVM board or interface card and is referenced to ground through the J11 1 and J6 1 terminal The dc power supply requirement for the analog section and Vss of this EVM range from 15 75 V to 15 75 V maximum and connects through J10 4
21. onfiguration for a capacitive load drive Table 3 4 Capacitive Load Drive Output Jumper Settings Jumper Setting W5 1 2 Bipolar Negative rail of the op amp tied to 15 V for bipolar operation or AGND 2 3 Unipolar for unipolar operation Positive rail supply of the op amp tied to 15 V Capacitive load drive output of DAC is channeled to the output terminals Disconnect exREFin from negative input of op amp Disconnect R12 see note Note If there is a need to incrementally adjust the capacitive load output replace R12 with a capacitor with the desired capaci tance value and CLOSE W15 3 4 Jumper Setting 3 3 Jumper Setting The figures in Table 3 5 will show the function of each jumper on the EVM Table 3 5 Jumper Setting Function Jumper Reference Setting 3 CD ee 2 W9 Ror rset is strapped to Vngr to set VsJ summing junction to 2 Refer to the data sheet for offset adjustment Rorrser is not connected to set summing junction to Refer to the data sheet for offset adjustment Rorrsrr is strapped to AGND to set Summing junction to VREF 6 Refer to the data sheet for osset adjustment Disables the internal reference voltage Enables the internal reference voltage of 10V REFIN is strapped to REFour to allow the internal 10 V to supply the DAC reference voltage REF is strapped to exREFin to allow
22. output of U2 if necessary The output terminals J5 and J4 are provided to monitor the desired output of the DAC by shorting the respective pins of W13 The following sections describe the different configurations of the output amplifier U2 3 2 1 Unity Gain Output The buffered output configuration is used to prevent loading the DAC7741 and should closely match the raw output of the DAC with maybe some slight distortion because of the feedback resistor and capacitor The user can tailor the feedback circuit to closely match their desired wave shape by simply desoldering R7 and C11 and replacing them with the desired values You can also simply get rid of R7 and C11 altogether and just solder a zero resistor in replacement of R7 if desired Table 3 2 shows the jumper setting for the unity gain configuration of the DAC external output buffer in unipolar or bipolar mode Table 3 2 Unity Gain Output Jumper Settings Jumper Jumper Setting Bipolar 23 12 Supplies the voltage for the negative rail of op amp Supplies the voltage for the positive rail of op amp DAC output is channeled to the output terminals exREFin is disconnected from the negative input of op amp Disconnect negative input of from GND EVM Operation 3 3 Host Processor Operation 3 2 2 Output Gain of Two This configuration allows the DAC output with a gain of two but is limited to the effective rails of the operational ampl
23. t heading the product you have questions or concerns with This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference TI Logo is a trademark of Texas Instruments Incorporated SPI and QSPI are trademarks of Motorola Inc 1 1 1 2 1 2 3 2 4 2 5 Contents EVM ET 1 4 1 4 1 2 1 2 Power Requirements 2 2 1 2 121 Supply Voltage 1 2 1 22 Reference Voltage 1 2 1 3 Basic Functions er us Lid bee ney Debita 1 3 Physical Description 2 1 234 PGB Layout tech EE 9 2 2 2 2 Bill or Materials eda WEE Pneu 2 7 EVM Operation viele seek e
24. ultilayer ceramic capacitor 5 5 84 5 6 C11 C1210C106K8PAC 10 uF 1210 multilayer ceramic X5R C14 capacitor 6 1 R8 Panasonic ERJ 8GEYOROOV 0 1 4W 1206 chip resistor 7 2 R7 R10 Panasonic ERJ 8ENF2002V 20 1 4W 1206 chip resistor 8 6 R4R5 6 R12 Panasonic ERJ 8ENF1002V 10 kQ 1 4W 1206 chip resistor R13 R14 9 2 R1R2 Bourns 3214W 103E 10 BOURNS_32X4W Series 5T pot 10 1 R11 Bourns 3214W 104E 100 BOURNS 32X4W Series 5T pot 11 1 R3 Panasonic ERJ 8ENF1003V 100 1 4W 1206 chip resistor 12 2 J6J7 Samtec IPT1 105 01 S D VS 5X2X0 1 10 pin 3A isolated power socket 13 3 4924344 Samtec TSM 1 10 01 S DV M 10X2X 1 20 pin 0 025 sq SMT socket 14 1 Samtec TSM 1 16 01 S DV M 16X2X 1 32 pin 0 025 sq SMT socket 15 2 Ji1J12 Lumberg KRMZ2 2 pin Terminal screw connector 16 1 J5 Not AMP TYCO 227699 2 PCB Mounted BNC Amphenol Installed 17 1 J10 Lumberg KRMZ4 4 pin Terminal screw connector 18 1 U1 Texas Instruments DAC7741 16 bit 48 LQFP DAC 19 1 02 Texas Instruments OPA627AU 8 SOP D Precision op amp 20 1 U3 Texas Instruments REF102AU 10 V 8 SOP D Precision voltage reference 21 2 TP1TP2 Cambion 180 7337 02 05 Turret terminal test point 22 1 W13 Samtec TSW 103 07 L D 3X2X 0 1 6 Pin IDC header 23 3 P2P3 P4 Samtec SSW 1 10 22 S D VS P 20 pin 0 025 sq SMT terminal strips see Note 24 1 P1 see Note Samtec SSW 1 16 22 S D VS P 32 pin 0 025 sq SMT Terminal Strips 25 2 P6P7 Samtec IPS
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