Texas Instruments CC2511 Network Card User Manual
Contents
1. savec FOR INFORMATION ON WHICH TERMINALS NEED PULLUP RESISTORS VCCP JO PAR SERR cio cH cm PERRE STOP uF tur aw DEUSELY t TRDY IRDY FRAME C BE 3 0 amp AD 31 0 IDSEL PCLK REQ GNT PRST PME a xoa ol of cd coc I va ASRS AA ely VOTO GG SE dec OO NoD s ceedoussonae a a 22990 565POORDT 209 AD10 1 o 0 amp 0 FrF ro 191 ADI7 AUS 2 AD10 a ADI7 190 ADT ADE 3 Abs AD18 gg ADT 4_ ADB AD19 188 ADZO AD7 5 C BEO AD20 187 AUZT AD AD21 D 6 186 A Ape 1 54 GND AD22 se ADS i ADs GND Haz AD23 ADI 5 ADS AD23 aps ADS 10 AD4 IDSEL agp ADZ 11 ADs PCLK at AD24 ADT 12 AD AD24 180 ADU 13 AD VCCP F179 AD26 ADO AD26 55 152 5 AD27 77 183 SPKROUT z GRST Hss AD28 184 LATCH x AD28 se ADOS 185 CLOCK P amp du D E AD29 i74 U 9569339835 ot br FERREE EEEE EPEAK EEE EIEEEEFEEERBEEBEEEIRI t4 EEE EE EREREEEEE RIS pons ec R4 PULL DOWN ON CLOCK REQUIRED WHEN USING INTERNAL OSC lt GRST NOTE GRST IS A POWER ON RESET IT SHOULD BE ASSERTED AT POWER UP WAIT AT R6 R7 RB Ro m2 ma LEAST 100US AFTER PCLK savec 43k ask 43k 43k 43K 43K IS STABLE THEN BE DEASSERTED FOR PROPER INITIALIZATION PCI12V NOTE IRQSER SHOULD BE o PCISV ROUTED TO AN i 9 INTERRUPT CONTROLLER C13 C14 U3 LL2. eeeeeeeeeeeeeeeeeee ee een eene nn snnt nuin snnt snnt asina natns sans natns st sn ane sn nananana ennnen 13 93 DS Wake Informatlon e nte ORE ERE RR T aaae aa RERO HUI CHOR ME ERES 13 9 1 1 GRST Only Registers eec one nece nee ee an eine tenets Dea ee ede ra ete ede E Edu ende 14 93 2 PME Context Beglisters ood de leet wheat cece er die Meere ire ee era ea esee see Spe x d 15 9 2 PME RI OUT Behavior diit iie a cre to dest needs d eta uide repre atte erp eee ra deer eens 15 9 3 GEIKKRBUNIEPIOIOCOL euim eb oeMe ame nate aua esate 15 9 4 SUSPEND 2 etie cce ene Cea tede io e nde P e ELS cite EE EE D CHEN URL este bie eee Ec eC eei ect 16 Pin Compatibility with Other Devices neeeeeeeeeeeeeeee enne nnne nnn nnns nnns ntnn annnm ssi nn sinn n ssi nn natns sten natn n nnt n nnn 16 Migration to the PCI1520 from the PCI1420 eeeeeeeeeseeeeeeeeeee enne nnn enne nnn nennen na nnnasnnn na tnn ss nnn nat nn nsns nennen nnne n n 17 11 1 Hardware and Pin Assignment Changes cceccceeseeceeeeeeneeceeeseaeeeeaeeeeaeeseaeeeeaeeecaeeseaeeseaeeseaaeeseeeesieeseeeseeeseneeeeaes 17 11 2 Configuration Register Gharges 5 2 tim ete ern o EE A ELI IO RO ERR EL 18 11 3 Other Functional Differences cnet esI dre euet tete e ce Dao eee deed Cae feoda era lis pe ek re eco Lens 19 Migration to the PCI1420 from the PCI1225 eeeees
3. sgvec Byoo AVCC 9 E TuF 4 d EE 8 d a j dd zl Bn E E Jaga dag ids EEEEEEGEEREEER ddd lt lt lt t t t es E me c2 ca c4 deis siio is sla adocidadnadadadddal d ue FAIS IIIA AIAG SAAS aS SAVINGS ANIA we Due pue 4 4 OND OROKO Ceo HS OE NOH OE TEWL OSOR TIVO gE E PEPIPES tA aBbBagaaBAOSIcLOD 2528 ors 383533383325 9 PELARE D pncxZU x Pe Occ cd py ce XB88 sre 2L AS Teaacscscsssss 1uF 2588 SNS SSNLZSNAA SAZA TALAN OTAS 8833 238 29O0sODaS8 Sag 33203202 ur 3258 338 bs238555 BOSS 363530323 xu xx x9 Bt Dax Q u JOE lt 5sac lt Eni 7 7 95 4 voc 239008 18 lt Sa a CIRDYHIA Ais HHZ ALAS 18 B CCD1 B_CD1 EPER owl A CTRDYP A A22 ATS au 17 B CADO B D3 Eis A CCLK A A16 LS AAG 18 B CAD2 B D11 8929 2 a voca His 18 B CAD1 B D4 Q A CDEVSEL amp A A21 HH AN ay 20 B CADA D12 A A_CGNT HIA_WE iT zd Ex 21 amp Capo amp Dis 2 ACSTOPRIA ED 8 y E Di4 23 B CADS B D6 A CPERRE A A14 Hos 24 B RSVDI DA CBLOCK A A19 H07 BD toe A CPAR A A13 BDT B B_CAD7 B_D7 ARSVDIIA_A1a LASS EVE 27 B CADB B D15 A CC BETI A AB um BATO 5g B_CCIBEO B_CE1 A_CAD16 A_A17 28 B_CAD9 B_A10 A CADIA A A9 VR_EN Di IF TO 30 amp CAD10 8_CE2 A CADTS A rons O R2 BAT 32 B_CAD11 B_OE A_CAD12 A_A11 100 E JOHDF 33 B CADI2 B A1 A_CAD11 A_OE BTOWRF 34 B_CAD13 B_IORD A CADIO A CE2 LSS 35 B_CAD15 B_IOWR CADO A A10 38 B CAD14 B A9 A CC BEOR A
4. The PCI1520 does not have a VCCI pin Signals clamped to VCCI on the PCI1420 are clamped to VCCP on the PCI1520 A new power switch has been introduced for dual socket CardBus controllers The TPS2226A is recommended for new designs although the TPS2216 and TPS2206 are still compatible with the PCI1520 All three power switches have very similar functionality and can be designed onto the same footprint The PCI1520 has integrated pullup resistors on the two CCLKRUN WP IOIS16 terminals All necessary pullup resistors on the PC Card interface have been integrated in the PCI1520 A switchable pullup pulldown resistor has been implemented on the two CSTSCHG BVD1 STSCHG RI terminals The pullup is active when the 16BITCARD bit bit 4 in the Socket Present State register is 1 otherwise the pulldown resistor is activated This prevents unexpected PME assertion PCI1520 Implementation Guide 17 EXAS SCPA033 INSTRUMENTS 11 2 Configuration Register Changes e The device ID for the PCI1520 is AC55 e Bit 23 in the System Control register PCI offset 80h is reserved on the PCI1520 On the PCI1420 this enabled PCI Bus power management specification revision 1 1 reporting The PCI1520 is compliant to revision 1 1 by default e The default value of the Multifunction Routing register PCI offset 8Ch has been changed from 00000000h on the PCI1420 to 00001000h in order to enable IRQSER on MFUNCS by default e Bit6inthe Diagnostic
5. A power management event PME is the process by which a PCI or CardBus function can request a change of its current power consumption state Typically a device uses PME to request a change from a power savings state to the fully operational state DO PME Context is defined as the functional state information and logic required to generate PMEs report PME status and enable PMEs PCI Function Context refers to the small amounts of information held internal to the function This includes not only the contents of the function s PCI registers but also information about the operation states of the function including state machine context and other internal mechanisms When global reset GRST is asserted the PCI1520 is completely non functional and is in a default state Output buffers are tristated and internal registers are reset The result of PCI reset PRST being asserted is dependent on whether PME is enabled or not When PRST is asserted with neither function enabled for PME it causes the PCI1520 to tristate all output buffers and reset all internal registers except for those considered GRST Only Registers If PMEZ is enabled for either socket the PCI1520 will maintain its PME Context Registers According to the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges a device returning to DO from D3hot is required to assert an internal reset The PCI reset may or may not be asserted by the system How
6. KIRGSER touF uF ae cis ctu bt 3 svin svin SG 10uF uF 5 SVIN NC Hig X t DATA Nc Hx I CLOCK NC X z LATCH NC sex E x Ne SHDN 25 X E 5 12VIN 12VIN 53 4 AVPP BVPP HS AVCC BVCC Ed IE AVCC BVCC Hil a uF 12 Avo BvCC ig uF 13 1 GND NC Ha X x NC oc H7 X 4 RESET 3 3VIN Hie i 7 3 3VIN 3 3VIN z TPS2226A AVCC PCI3 3V BVCC o fo o 4 C19 C20 cat C22 uF touF uF uF Figure 4 PCI1520 Implementation Guide Reference Schematics Page 1 X5 TEXAS INSTRUMENTS SCPA033
7. 8ch MFUNC Byte 1 MFUNC3 IRQSER FUNC2 GPI2 Of 0x00 78ch MFUNC Byte 2 MFUNC5 GPIA4 MFUNC4 SCL 10 0x00 8ch MFUNC Byte 3 MFUNC6 RSVD 11 OxcO 90h Retry Status bits 7 6 PCI Retry CardBus Retry 12 0x00 91h Card Control bits 7 5 Ring Indicate Enable ZV Port Select 13 0x44 92h Dev Cntr bits 6 3 0 3V Capa IRQ serialized and parallel PCI 14 0x00 93h Diagnostic bits 7 4 0 1 5 0x00 a2h Power Management Capabilities bit 15 PME _Supp from D3cold 0 16 0x84 00h ExCA ID and Revision bits 7 0 17 0x00 Och CB Socket Force Event Function 0 bit 27 ZVSUPPORT 0 18 0x00 Och CB Socket Force Event Function 1 bit 27 ZVSUPPORT 0 8 2 8 2 1 BIOS Considerations This section provides a high level overview of the registers which need to be programmed by the BIOS upon initialization In general the only registers which must be programmed for proper operation within a Windows operating system are those registers which are EEPROM loadable Other registers may need to be changed according to system implementation Microsoft provides the following reference documents concerning initialization of CardBus controllers in Windows http www microsoft com hwdev bus cardbus cardbus1 asp http www microsoft com hwdev bus pci pcibridge cardbus asp PCI Configuration Registers Standard Cache Line Size Register PCI offset OCh This register indicates the size in doublewords of a cache line This register is system architectur
8. BAS 123 T BAT 47 BAIS 122 LATS BA 46 B A13 121 T9 BECA 45 B A19 120 T4 BAD 44 B A14 119 0 ag B20 118 B_WE 22 GND_ R A WE BAZ 4i B WE 116 T B READY 40 B A21 e 115 READY 38 B READY IREQ READY T 3g 8 VCC 113 237 BANG MEN BAIS En Beale iH A A16 BATS 34 B A22 1S CAT 33 BAIS 108 B A23 T 32 GND 107 A A23 BAT 31 B Aes 106 T Emer 30 B A12 105 zi BAT 29 B_A24 104 B A25 28 B A7 103 BAG 27_ B A25 AA25 102 6 B VSZ 26 BAS AAS 101 VSF 25 B VS2 A VS2 Hoo B_AS T 24 GND GND 99 T ALAS B RESET 23 BAS ALAS 98 RESET wat 227 B RESET A RESET 97 A B WAITE B Ad AAS Bae 21 B WAT A WAIT E et BLINPACKF 19 8 AS AAS 94 INPACK ER 18 8 INPACK A INPACK 93 ACAD T7 B A2 ANE B_REG GND GND pa sies ABER Areas B BVD 14 B At AA BAT lt 3 B BVD2 SPKR A BVD2 SPKR Se na T2 B AO SEEE AA 87 CEVDT T 8 BVDISTSCHG A BVDI STSCHG Hgg DO 108 00 A DO Fae DE g 88 A D8 Taq T 8 GND GND 83 T ADI 548 01 ADI Pap DS g 8 09 A D9 8T D2 A_D2 3 8 I 4 B D10 A bio 9 D 4 B WP IOIS16 A WP IOIST6 Hg Wed 2 B CD2 A CD2 77 GND GND Fah end PEt C 1318619 R2 CB Connector Reference Schematics Page 2 PCI1520 Implementation Guide 23 SCPA033 EXAS INSTRUMENTS 14 References 24 1 Sito qu PCI1520 GHK PDV PC Card Controllers Data Manual SCPS065A PCI Local Bus Specification Revision 2 2 PC Card Standard Revision 7 1 PCI Bus Power Management I
9. SPKROUT is disabled and therefore tristated SUSPEND The assertion of SUSPEND gates PRST GRST and PCLK from the PCI1520 More information can be found in Section 9 Power Management Considerations A 43kQ pullup resistor is required on SUSPEND SUSPEND cannot be low during boot PCI1520 Implementation Guide 7 1 7 2 7 3 7 4 EXAS INSTRUMENTS SCPA033 Interrupt Configurations The PCI1520 provides system designers with great flexibility in configuring interrupts The PCI1520 allows four interrupt modes which are selected via bits 2 1 of the Device Control register at PCI offset 92h PCI interrupts are available on INTA and INTB These signals are available on MFUNCO and MFUNC1 respectively The Multifunction Routing register at PCI configuration offset 8Ch must be programmed correspondingly If MFUNC1 is not available i e EEPROM implementations which use MFUNC1 as SDA the INTRTIE bit can be set at bit 29 in the System Control register at PCI offset 80h This allows both INTA and INTB signaling to both be reported on INTA PCI interrupts can also be signaled through IRQSER ISA style IRQ interrupts are available on IRQ15 2 These signals are available on MFUNC6 0 These interrupts are necessary for some 16 bit PC Cards to function properly IRQ interrupts can also be signaled through IRQSER IRQSER is available on MFUNC3 and requires a 43k pullup resistor to VCC Parallel PCI Interrupts Only The parallel
10. X3 TEXAS Application Report INSTRUMENTS SCPA033 October 2002 OORO 10 11 12 13 14 PCI1520 Implementation Guide Computer Connectivity Solutions ABSTRACT This document is provided to assist platform designers using the PCI1520 dual socket PC Card controller Detailed information can be found in the PCI1520 data manual However this document provides design suggestions for the various options when designing in the PCI1520 Contents PCI1520 Typical System Implementation eeeeeeees esee esee esee eee n nennen nnn n nnnm nnn nn ns nnn natnra anna nsnm anat n ista natns antra 3 Power Considerations eie ceu iet ae lecce ete iet Lune ceece sini A EA AEA Aa ESE ineei 4 23 Internal Voltage Regulator eee HO tte T E 4 2 2 Clamping Ralls eR LC 4 213 Bypass Capacitors errezeta LC a 4 Power SwitcliImplementatlon 5 2 err leer nc ode cen eeenice decane es deniers tie abiere taie Exeter inde 5 PCI Bus LC Rel RETE 6 PC Card INtertaGe ns eR 7 Miscellaneous Pin ica c 8 6 1 Multifunction Terrminals 2 nett eem eerie dh alse ede ERO eset la it eee aden 8 6 2 SPKROU T uiro e tse dtu cde e seas dte act ice ei odes tie ert 8 6 37 SUSPEND GS
11. 6 02 PCI1520 Implementation Initial Draft Guide 1 00 doc DGB 8 8 02 PCI1520 Implementation Added information about switchable pullup pulldown on Guide 1 10 doc CSTSCHG to Section 5 Corrected explanation of single socket implementation in Section 5 Added PCLK to list of SUSPEND gated signals in Section 6 3 Corrected bit number for INTRTIE in Section 7 Changed description of Cache Line Size Reg in Section 8 2 1 Removed duplicate Dev Cntl Reg in Section 8 2 2 Corrected PC Card Standard rev number in Section 14 DGB 8 9 02 PCI1520 Implementation Fixed typo in Rev History Guide 1 11 doc 2 PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 1 PCI1520 Typical System Implementation The figure below represents a typical implementation of the PCI1520 PC Card Controller The device serves as a bridge between a PCI Bus and a PC Card interface The PCI1520 will operate only with the PCI Bus as a primary bus and the PC Card interface as the secondary bus The PC Card interface operates with both CardBus 32 bit and 16 bit PC Cards Vcc Vpp TPS2226A Power Switch P2C Bus Socket A PCI1520 CardBus Controller Socket B I2C Bus Serial EEPROM Optional i CardBus Controller Block System Side IRQSER l Interrupt l Controller Figure 1 Typical System Implementation A power switch is necessary in order to control power to the PC Card sockets The
12. PCI interrupts only mode is selected by programming bits 2 1 to a value of OOb This allows interrupts to be routed through INTA and INTB This is not a recommended interrupt configuration because many 16 bit PC Cards require legacy ISA interrupts and will not function properly Parallel IRQ and Parallel PCI Interrupts The parallel IRQ and parallel PCI interrupts mode is selected by programming bits 2 1 to a value of 01b This allows interrupts to be routed through IRQ15 2 INTA and INTB This is nota recommended interrupt configuration because this requires all the multifunction terminals to be used as interrupts which limits other functions on the PCI1520 Serial IRQ and Parallel PCI Interrupts The serial IRQ and parallel PCI interrupts mode is selected by programming bits 2 1 a value of 10b This allows interrupts to be routed through IRQSER INTA and INTB This is the recommended interrupt configuration for a PCI add in card implementation of the PCI1520 INTA and INTB can be routed through the PCI edge connector while IRQSER must be attached to a Serial IRQ input on the motherboard If no Serial IRQ input is available this mode still allows CardBus cards to function properly However many 16 bit cards will not Serial IRQ and Serial PCI Interrupts The serial IRQ and serial PCI interrupts mode is selected by programming bits 2 1 to a value of 11b This allows all interrupts to be routed through IRQSER This is the recommended int
13. SCL respectively In order for the PCI1520 to detect the EEPROM and load configuration information a pulldown resistor must be implemented on LATCH Pullups are needed on SDA and SCL The EEPROM slave address should be 1010000b If the Serial Bus Detect bit is cleared after the EEPROM data is loaded MFUNC1 and MFUNCA are returned to their functions as indicated by the Multifunction Routing Register PCI offset 8Ch PCI1520 Implementation Guide X5 TEXAS INSTRUMENTS SCPA033 The EEPROM loading map can be found in the data manual The following is an example data file which could be loaded into the EEPROM for use with the PCI1520 EEPROM Programming Data for the PCI1520 Customer Board Configured for IRQ serialized interrupts and parallel PCI interrupts Register Data Description 00 0x01 Reference 1 01 0x03 04h Command Register bit 8 mapped from EEPROM bit 7 6 5 2 0 02 0x78 40h Sub System Vendor ID Byte 0 03 0x56 40h Sub System Vendor ID Byte 1 04 0x34 742h Sub System ID Byte 0 05 0x12 42h Sub System ID Byte 1 06 Oxe0 44h Legacy Bar Byte 0 bits 7 1 07 0x03 44h Legacy Bar Byte 1 08 0x00 44h Legacy Bar Byte 2 09 0x00 44h Legacy Bar Byte 3 Oa 0x60 7 80h System Control Byte 0 default Ob OxdO 780h System Control Byte 1 MRBURSTU 1 all others default Oc 0x28 780h System Control Byte 3 INTRTIE 1 P2CCLK 1 Od 0x02 78ch MFUNC Byte 0 MFUNC1 SDA MFUNCO INTA Oe 0x10
14. TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated
15. eed ataueti auc LM iitcoten eS cit sec selet se 8 Interrupt COMPIQUIATIONS tse 9 Tel Parallel PG Interrupts Only oce eite t RR P RU RR CERRO IUe aloha leben edad bade At REDE pa aed ERE a 9 7 2 Parallel IRQ and Parallel PCI Interrupts sessseeseseseeeeeeenenennenennnen nennen nennen nne nnnnen nennen enne rnn enne 9 7 3 Serial IRQ and Parallel PCI Interrupts eseessseeseeeeneeeeeenneeenneennnee nennen nennen nnne nnnn sinn rennen senes etre n enne 9 7 4 Serial IRQ and Serial PCI Interrupts sesessssssseseeseeeeneenn nennen nennen ennt nn entrent nn senes nnne s enne nnns enne 9 Software Considerations aee c 10 9 4 EEPROM Configurations chil ech ee eee n Eee Me ERR Sok el RE iste ae aes 10 9 2 BIOS Gonsider tioOns ec ccei coi ve ets e mega tre nah aan deel ia e tempi ice base ce des 11 8 2 1 PCI Configuration Registers Standard sssssssssssssseseseeeeneenneeneee nennen nennen nens 11 8 2 2 PCI Configuration Registers TI Extension ssesssssseseeeneeeeeenenenneen nennen nennen nnne 12 8 23 ExGA Compatibility Registers nsns accede denis die elite tete dep eere teer Dep K E e deere 12 8 2 4 CardBus Socket Registers ein a detect den a eed Aa d ete dd edat obe ice tbe 12 Power Management Considerations
16. has been fixed SPKROUT signal behavior is changed The signal will stay low during socket power on an off A pulldown resistor is required to prevent oscillation Setting bit 15 of the Power Management Capabilities register is no longer required to preserve PME context for a D3hot to DO transition This was an erratum in the PCI1420 PCI1520 Implementation Guide 19 SCPA033 12 EXAS INSTRUMENTS Migration to the PCI1420 from the PCI1225 The major differences between the PCI1420 and PC1I1225 are the ability to wake from the D3 power state and the integration of the pullup resistors on the PC Card interface This is done using a global reset pin 12 1 Hardware and Pin Assignment Changes 20 The pinout changed slightly from the PCI1225 to the PCI1420 A VCC pin has been replaced by a global reset pin GRST This requires a PCB redesign This pin allows for wake from the D3 power state Certain configuration registers are reset only by GRST and not PRST This allows the device to save context since PCI Reset must be asserted on a D3 to DO transition For systems requiring wake from D3 GRST should be connected to a power on reset and PRST should be connected to the system PCI Reset When implementing GRST in this way it must be treated similar to PRST in that PCI Clock must be stable for 100ys before deassertion The sequence of events should be 1 Power on with GRST and PRST asserted 2 Clock becomes stable 3 100ys
17. later GRST can be deasserted 4 PRST can be deasserted at the same time or any time after GRST is deasserted For systems not requiring wake from D3 GRST can be tied to PRST which is connected to system PCI Reset For more information please refer to the datasheet and the Section 9 1 D3 Wake Information All necessary pullup resistors on the PC Card interface have been integrated on the PCI1420 with the exception of CCLKRUNZ WP IOIS1 62 PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 12 2 Configuration Register Changes The device ID for the PCI1420 is AC51 The PCI1420 is both Intel 82365SL DF and 82365SL register compatible The PCI1225 is only 82365SL DF register compatible Bit 2 in the System Control register PCI offset 80h is now ExCA Power instead of reserved to allow for SL compatibility The ExCA Power Control register ExCA offset 02h also changes in SL mode Bit 23 in the System Control register PCI offset 80h is now used to allow the PCI1420 to report as compliant to either revision 1 0 or 1 1 of the PCI Bus Power Management Specification In the PCI1225 this bit is reserved Some of the values of the Multifunction Routing register PCI offset 8Ch matrix have changed When MFUNC5 1001b it is now reserved instead of IRQ9 When MFUNC4 1111b itis now reserved instead of IRQ15 When MFUNC2 1011b it is now reserved instead of IRQ11 Bit 7 in the Device Control register PCI offset 92h is
18. powered This opens the possibility of potential card damage If a 3 3V card is inserted into the hot slot that was powered to 5V card damage will most likely occur It is therefore recommended that P2CCLK bit 27 at PCI offset 80h is set to a 1 so that the Internal Oscillator is enabled The CLOCK signal will then always be available as long as power is applied to the CB controller Pin Compatibility with Other Devices The PCI1520 is pin compatible with the PCI1620 PC Card Flash Media and Smart Card Controller This device has flash media and smart card terminals multiplexed on the PC Card interface to allow for convenient access to many different media types In order to design a PCB for an upgrade path to the PCI1620 one change must be made from a normal PCI1520 PCB A 48MHz clock is needed on the PCI1620 This clock input is located on pin 81 for the PDV package and pin W11 for the GHK package The PCI1520 can also be designed on to the same PCB as other Texas Instruments CardBus controllers such as the single socket PCI1510 controller even though the two devices are not pin compatible This can be done using a dual footprint for the devices on the PCB For example a designer may want the option of having a single or dual socket implementation on a single PCB In this instance a PCI1510 BGA GGU footprint can be placed inside a PCI1520 QFP PDV footprint The traces for the PC Card socket A on the PCI1520 footprint are then connected to
19. recommended power switch is the TPS2226A Other possibilities include the TPS2224A TPS2216A and the TPS2206 The TPS2223A is also available but does not provide 12V Vpp The EEPROM can be used to set various configuration registers but is not necessary if those registers are settable via software BIOS for the system IRQSER is used to pass both PCI interrupts and ISA style legacy interrupts to the system Only PCI interrupts are necessary in order for CardBus cards to operate correctly Some 16 bit PC Cards require ISA style legacy interrupts in order to function properly PCI1520 Implementation Guide 3 2 2 1 2 2 2 3 EXAS SCPA033 INSTRUMENTS Power Considerations Internal Voltage Regulator One of the major differences between the PCI1520 and previous Texas Instruments CardBus controllers is that the PCI1520 uses an internal voltage regulator to power the core logic at 2 5V This allows for a more than 50 reduction in power consumption over previous controllers The voltage regulator is enabled using the VR_EN pin If VR EN is high the voltage regulator is disabled and VRPORT serves as a 2 5V external input to power the core If VR EN is low the voltage regulator is enabled and VRPORT serves as a 2 5V output This 2 5V output cannot be used to power other devices and is only available externally in order to provide a 1uF bypass capacitor VRPORT must have a 1uF bypass capacitor to ground in order for proper operation if t
20. refer to Section 3 2 2 3 5 System Generation of IDSEL and Section 4 2 6 footnote 31 Pinout Recommendation of the PCI Local Bus Specification Revision 2 2 for more information PCI Interrupts can be routed through INTA and INTB through the Multifunction terminals More information can be found in Section 7 Interrupt Configurations PCI CLKRUN can be routed through Multifunction terminal 6 For more information please refer to Section 9 Power Management Considerations PME is used to signal Power Management Events This signal is important for waking the PCI1520 from low power states PME is an open drain signal Pullup resistors are needed on the following PCI terminals IRDY TRDY FRAME STOP DEVSEL PERR SERR LOCK PRST GRST INTA INTB CLKRUN and PME PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 5 PC Card Interface There are two different modes on the PC Card interface The first is 16 bit mode which is analogous to the legacy ISA bus The second is 32 bit CardBus mode which is very similar to a PCI Bus The terminal functions for these two modes are multiplexed and routed to the PC Card sockets The following suggestions apply to the PC Card interface e Pullup resistors for the PC Card interface have been integrated into the PCI1520 These include A14 CPERR A15 CIRDY A19 CBLOCK A20 CSTOP A21 CDEVSEL A22 CTRDY BVD2 SPKR CAUDIO CD1 CCD1 CD2 CCD2 INPACK CREQ RE
21. register PCI offset 93h is reserved on the PCI1520 instead of AOSPMEN The AOSPMEN feature of disabling oscillator power management is no longer necessary e Bit 0 in the Diagnostic register PCI offset 93h is no longer Asynchronous Interrupt Enable The functionality is no longer necessary It is now STDZVEN which enables the new ZV register model e Bits 2 0 in the Power Management Capabilities register PCI offset A2h are now 010b indicating that the PCI1520 is compliant to Revision 1 1 of the PCI Bus Power Management Specification e Bit 4 AUX PWR in the Power Management Capabilities register PCI offset A2h is now tied to bit 15 PME Support for D3Cold e D3_STAT functionality has been added to MFUNC5 MFUNCA and MFUNC2 D3_STAT is asserted when PME is enabled and both functions are placed in D3 power state e Bit 27 in the Socket Present State register Socket offset 08h now indicates Zoom Video Support in that socket for the PCI1520 It is reserved in the PCI1420 e Bit 27 in the Socket Force Event register Socket offset OCh now causes the ZNV SUPPORT bit mentioned above to be set in the PCI1520 It is reserved in the PCI1420 e Bits 11 9 in the Socket Control register Socket offset 10h were reserved and now are used for ZV control e Registers and bits previously referring to centralized or distributed DMA are now reserved bits 19 16 System Control register at PCI offset 80h DMA registers at PCI offsets 94
22. ADY CINT RESET CRST VS1 CVS1 VS2 CVS2 WAIT CSERR WP IOIS16 CCLKRUN e A switchable pullup pulldown resistor has been implemented on BVD1 STSCHG CSTSCHG The pulldown is implemented when a CardBus card is being used or when the socket is empty A pullup is implemented when a 16 bit PC card is being used e Adamping resistor is necessary on the CCLK terminals between the PCI1520 and the PC Card sockets The value is system dependent If line impedance is in the range of 60 900 a 470 resistor is recommended For more information please see the PC Card Standard Revision 7 1 Section 5 3 2 1 4 e CD line noise filtering is no longer required because the PCI1520 has an integrated digital noise filter e Three PC Card terminals on each socket are not necessary for CardBus mode but are necessary for 16 bit mode These terminals are CRSVD D14 CRSVD A18 and CRSVD D2 These terminals must be connected to the PC Card Socket according to their 16 bit designations By default when in CardBus mode these terminals are driven low They can be tristated by setting bit 22 CBRSVD in the System Control register at PCI configuration offset 80h e Texas Instruments provides single socket CardBus controllers such as the PCI1510 for systems requiring only one PC card socket However the PCI1520 can be used as a single socket controller simply by leaving the Socket B interface floating PCI1520 Implementation Guide 7 6 1 6 2 6 3 E
23. GE 2 38 B CAD16 B A17 euo H5 4 Sg B CC BE1 B_A8 A CADB A D15 es B RSVD B A18 j n a BR X A_CAD7 A_D7 32 B_CPAR B_A13 PERS C 31 42 B CBLOCK B A19 A CADS A D6 22 43 B CPERR amp B A14 A CADG A D13 E2 B A20 1 i GND 9 A CAD3 A D5 HS B WEF 45 B CSTOP B_A20 PI A GADA A D12 FE TOAMD je B_CGNT B_WE p A CADI A D4 HE R3 47 B CDEVSELW B A21 g oG A CAD2 A Dti VCCB T I9 A JIA B_A16 48 esi ciate z t B os E sane A CADO A D3 33 X goga b 3 8 E hes A_CCD1 A_CD1 47 lkaning ionns glg og Fag howa o 9 LITID LTE 2 2z200 j59 08858x 5 s xzcoojocoo osooc u 359590onony m Az2 csoCTssraqS s zcscs EOOESLESESS BSSZULTTqNENSO NHUAAN S CODYANNNSG n e9r255508538u 325888505 MIKANDA 8 EELOTILSLLLIE IOT 59558955955595925295959599995995994 6 mmommommomnononaonon noommomm mnmmmmmnmnnonzdm 4 4 adddad d FRPEER dyg dddddddddddddddd iilii Keds poneo canosus i H 9 4 a E gadda d Adad S SR E 43 2 saga q col celeb cbc e enl cde dedi col dddo of BVPP BVOCC AVCC AVPP Pt 75 150 GND fv 149 73 SND EX A CDI 72 B CD 147 Dg 71 B 03 146 Dit 70 B Da 145 Da 68 B D2 I p 67 B D5 142 E T 566 GND 141 T A D13 B Di3 65 B be 140 D6 4 B Dia 139 nur 138 82 8 D7 137 Dis or po 136 CETE 80 B cet 135 CE 134 1 58 vn 133 f A A10 ALO 132 VSTE 56 6X8 131 OEF ER ES a ORD HS a 3 sown al E nd BT B A9 126 gt B_AI7 50 GND 125 T AAT BAB 49 B A17 124 BATS 4g
24. T Only Registers Global reset places all registers in their default state regardless of the state of the PME enable bit The GRST signal is gated only by the SUSPEND signal This means that assertion of SUSPEND blocks the GRST signal internally thus preserving all register contents The registers cleared only by GRST are Status register PCI offset 06h bits 15 11 8 Secondary status register PCI offset 16h bits 15 11 8 Interrupt pin register PCI offset 3Dh bits 1 0 function 1 only Subsystem vendor ID register PCI offset 40h bits 15 0 Subsystem ID register PCI offset 42h bits 15 0 PC Card 16 bit legacy mode base address register PCI offset 44h bits 31 1 System control register PCI offset 80h bits 31 29 27 13 11 6 0 Multifunction routing register PCI offset 8Ch bits 27 0 Retry status register PCI offset 90h bits 7 5 3 1 Card control register PCI offset 91h bits 7 5 2 0 Device control register PCI offset 92h bits 7 5 3 0 Diagnostic register PCI offset 93h bits 7 0 Power management capabilities register PCI offset A2h bit 15 General purpose event status register PCI offset A8h bits 15 14 General purpose event enable register PCI offset AAh bits 15 14 11 8 4 0 General purpose output PCI offset AEh bits 4 0 Serial bus data PCI offset BOh bits 7 0 Serial bus index PCI offset B1h bits 7 0 Serial bus slave address register PCI offset B2h bits 7 0 Serial bus control and
25. XAS SCPA033 INSTRUMENTS Miscellaneous Pin Interface Multifunction Terminals The multifunction terminals MFUNC6 0 can be programmed to serve many different roles using the Multifunction Routing register at PCI configuration offset 8Ch The discrete ISA interrupts IRQ15 2 INTA INTB and IRQSER are explained in Section 7 Interrupt Configurations CLKRUN D3STAT and RI OUTZ are discussed in Section 9 Power Management Considerations ZVSTAT ZVSEL1 and ZVSELO are used for ZV control For more information please refer to the PCI1520 Data Manual LED SKT LEDA1 and LEDA2 can be used to indicate socket activity When a PC Card is being accessed these outputs will be driven high LED SKT will be driven high for access to either socket LEDA1 and LEDA will only be driven high during access to their respective socket GPE GPIx and GPOx can be used to signal general purpose events to the system CAUDPWM provides a PWM output for the CAUDIO terminals as opposed to the binary output SPKROUT PCI LOCK is an optional PCI signal as mentioned in Section 4 PCI Bus Interface All unused multifunction terminals require a 43kO pullup resistor SPKROUT SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1520 from the PC Card interface If SPKROUT is enabled for both sockets it is driven as an exclusive OR of the two inputs A 43k pulldown resistor is required to prevent oscillation when
26. e dependent PCI1520 Implementation Guide 11 EXAS SCPA033 INSTRUMENTS Latency Timer Register PCI offset ODh This register indicates the number of PCI clocks the PCI1520 will be allowed access to the PCI bus if another master has its REQ asserted The recommended value is 40h However the value should be dependent on the system implementation and which devices need priority CardBus Latency Timer Register PCI offset 1Bh This register indicates the number of CardBus clocks the PCI1520 will be allowed access on the CardBus interface Because the CardBus interface is a point to point interface the PCI1520 does not deassert CGNT until a transaction is finished Therefore this register has little effect on the system Subsystem Vendor ID and Subsystem ID Registers PCI offsets 40h and 42h These registers are used for subsystem and option card identification purposes Typically these registers contain the OEM vendor ID and an OEM identified designator These fields can be programmed using the EEPROM or BIOS If using BIOS the SUBSYSRW bit System Control register bit 5 must be cleared to 0 The SSVID and SSID registers can now be written The SUBSYSRW bit should be set to 1 after the registers are written 8 2 2 PCI Configuration Registers TI Extension System Control Register PCI offset 80h This register contains many important system dependent variables Please refer to the datasheet for more details Of possible
27. ed by the PCI CLKRUN protocol CLKCTRLEN Socket Power Management Register CB offset 20h bit 16 This bit enables the CB CLKRUN protocol CLKCTRL Socket Power Management Register CB offset 20h bit 0 This bit determines whether the CB CLKRUN protocol will either stop or slow CCLK SUSPEND The assertion of the SUSPEND signal gates PCLK GRST PRST from the PCI1520 The recommended implementation for SUSPEND is to not use it for power management and simply connect a 43kQ pullup resistor SUSPEND is an unstandardized method of power management and causes many implementation problems The following guidelines are provided to help reduce implementation issues The main purpose of the PCI1520 SUSPEND pin is to prevent PCI reset from clearing all register context which would require the reconfiguration of the PCI1520 by software Asserting the PCI1520 SUSPEND signal will also tri state the controllers PCI outputs and gate the PCLK internally to the controller if there isn t any PCI transaction currently in process Due to the tri stated PCI outputs it is important that the PCI bus not be parked on the PCI1520 when SUSPEND X is asserted Another major point to note is that powerdown of a card slot due to card removal requires the use of either the Internal Oscillator or an externally supplied clock to the power switch If an external clock is used and is removed during Suspend the card slot will not power down and will remain
28. eeeeeeeeseeeeeeeen nennen nenne tnnn nnn na nnn ss nnn na tnn nnne n natn n nsn nn nantes ntn nnn 20 12 1 Hardware and Pin Assignment Changes ssssssssssseseseeeeenee nennen nnne nneen nennen neret rennen ennt nnns 20 12 2 Configuration Register Glianges oreet eR tx HEAR EE Efe DL Ea aspra irai OARE 21 12 3 Other Functional Differences tein pene eee ite eter ete eo ever ein Pe eee euet eo ee rte e Eae os 21 Reference gyrum E w w GS 22 higiiuccpe m EE 24 EXAS SCPA033 INSTRUMENTS Figures Figure 1 Typical System Implementation cssecsseessseessseeeseeeenseeeseeesnseeeseeesneeessaeeseseesseesnseasseesaeeesseesaseeeseeeeaeeeeeas 3 Figure 2 Power Switch Implementation csccsseeeeseecsseeeeseeesseeesneeeneeeeeneesnseeeseeesaseasaseesaseasaeeesaeeaenseeseeeesseeeseeeesseneeseeeas 5 Figure 3 EEPROM Implementation cccsecceseesseeeseeesseeseseeenseeeeeeeeseeeeeeeesseesseeessaeesseeessaeeseeeeeseeeseeeeeseeesaseaseeeeseseeeees 10 Figure 4 Reference Schematics Page 4 wiccccccsciccscccecenceesetesnccacoccscetencestestactsseessstenseteesdecessteseantesssucectieatietsnceustacssnnested 22 Figure 5 Ref rence Schematics Page 2 e cccciscieccccdscdectedecececestentacec teste cteatputetecteceveceusdieyscusdendeivecstanestsesccdedenegfecseade 23 Document History Revised by Date Document Name Revision Comments DGB 8
29. errupt configuration for all designs other than PCI add in cards It is the simplest method of routing interrupts and allows the other multifunction terminals to be used for other purposes PCI1520 Implementation Guide 9 8 8 1 EXAS SCPA033 INSTRUMENTS Software Considerations The PCI1520 is natively supported by Windows XP The PCI1520 will be recognized natively as a Generic CardBus Controller under Windows 2000 Windows ME and Windows 98SE The device will function properly using this driver However it is recommended that new drivers provided by Texas Instruments be used for non XP systems These drivers have a few small tweaks and allow the device to be reported in Device Manager properly Other operating systems are not supported directly by Texas Instruments However many non Microsoft operating systems have generic CardBus device drivers which are compatible with the PCI1520 Any driver which was compatible with a previous Texas Instruments CardBus controller such as the PCI1225 or PCI1420 or the Intel 82365SL should also be compatible with the PCI1520 EEPROM Configuration The following diagram represents the implementation of an EEPROM for the PCI1520 for configuration Vcc TPS2226A Figure 3 EEPROM Implementation On the rising edge of GRST if LATCH is low the Serial Bus Detect bit bit 3 PCI offset B3h is set and the EEPROM contents are loaded into the PCI1520 MFUNC1 and MFUNC4 become SDA and
30. ever for a device returning to DO from D3cold however PRST must be asserted by the system For a wake from D3cold the device needs to save its PME context in order for software to determine the source of the wake up event This is accomplished using PME enable and saving the PME context registers However the device must also maintain certain registers that are normally configured by BIOS at boot time This is accomplished using GRST and the GRST Only Registers This allows a system to be in a low power state and resumed quickly without needing BIOS to reprogram the device The sequence of events at power up are that GRST and PRST should be asserted 100 us after PCLK is stable GRST can be deasserted PRST can be deasserted at the same time as GRST or any time there after At this point GRST will stay deasserted until the system completely cycles power and reboots Now the system can put the PCI1520 into a lower power state and may or may not assert PRST The PCI1520 does not require a PCI clock to generate a PME signal However it does require a voltage source such as Vaux to be supplied and the pullup on PME must also be connected to Vaux In addition the VCCP pins and power switch must also have power in order to wake from a card Vaux is limited to 200mA for each socket For systems not implementing wake from D3 GRST can be tied to PRST PCI1520 Implementation Guide 13 SCPA033 EXAS INSTRUMENTS 9 1 1 GRS
31. h and 98h see explanation about DMA below e The EEPROM loading map has changed significantly to provide more control for applications needing an EEPROM see datasheet for details e Two registers have been added to the PME context list EXCA Power Control register and ExCA Interrupt and General Control register 18 PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 11 3 Other Functional Differences The PCI1520 is natively supported by Windows XP The PCI1520 will be recognized natively as a Generic CardBus Controller under Windows 2000 Windows ME and Windows 98SE The device will function properly using this driver However it is recommended that new drivers provided by Texas Instruments be used for non XP systems These drivers have a few small tweaks and allow the device to be reported in Device Manager properly The latest version of the PC Card Standard Revision 8 0 no longer supports centralized or distributed DMA for PC Cards Therefore the PCI1520 no longer supports centralized or distributed DMA DMA was used by very few PC Cards most of which are obsolete DOS based sound cards DVD decoders A new standardized ZV register model has been implemented in the PCI1520 see datasheet for details The PCI1520 is backward compatible with the legacy ZV register model used in previous CardBus controllers The timing condition erratum which disabled the MFUNC1 and MFUNCA pins because a non existent EEPROM was detected
32. he voltage regulator is enabled Clamping Rails The PCI1520 has 3 clamping rails VOCP VCCA and VCCB VCCP is the PCI interface I O clamp rail and can be either 3 3V or 5V depending on the system implementation The PCI1520 will only signal on the PCI bus at 3 3V but is 5V tolerant VCCA and VCCB are connected to the PC Card power rails for Socket A and Socket B respectively These terminals serve as the clamping inputs for the PC Card interface to the PCI1520 Bypass Capacitors Standard design rules for power supply bypass should be followed A value of 0 1uF is recommended for each of the power pins VCC VCCP VCCA and VCCB PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 3 Power Switch Implementation The following figure shows the serial interface between the PCI1520 and the TPS2226A power switch Qe uds TPS2226A e VPPB LATCH Pull down for Pulldown if 12C interface using internal optional clock Figure 2 Power Switch Implementation A power switch is necessary in order to control power to the PC Card sockets When the PCI1520 receives a socket power request it sends the appropriate data across the P C interface CLOCK DATA and LATCH In turn the power switch turns on the appropriate levels for VCC and VPP for that socket A 2 7kO pulldown on LATCH is used to indicate to the PCI1520 that an EEPROM is being used to program the PCI1520 CLOCK can be provided either internally or externally depend
33. ing on bit 27 in System Control register in the PCI configuration space at offset 80h If an external clock is used the frequency should be between 32kHz and 100kHz If the internal clock is used a 43k pulldown resistor is necessary PCI1520 Implementation Guide 5 SCPA033 EXAS INSTRUMENTS 4 PCI Bus Interface The PCI1520 has a 33MHz 32 bit PCI Interface compliant with PCI Local Bus Specification Revision 2 2 PCLK AD31 0 C BE 3 0 PAR DEVSEL FRAME STOP TRDY IRDY GNT and REQ are required PCI signals All except PCLK GNT and REQ are bussed signals PCLK is a 33MHz point to point clock GNT and REQ are point to point signals form the PCI bus arbitrator PERR SERR and LOCK are optional PCI signals PERR and SERR are bussed signals and should be pulled up to VCC if unused LOCK is available on a Multifunction Terminal If LOCK is not needed for system implementation it should not be configured as such in the Multifunction Routing register PCI configuration offset 8Ch GRST Global reset and PRST PCI reset are both used to initialize the PCI1520 The assertion of GRST puts the PCI1520 in its default state The assertion of PRST does not initialize GRST only bits PRST also does not initialize PME context bits if PME in enabled More information can be found in Section 9 1 D3 Wake Information IDSEL should be resistively coupled 1000 to one of the address lines between AD31 and AD11 Please
34. interest to the BIOS programmer SER STEP INTRTIE P2CCLK MRBURSTDN MRBURSTUP and RIMUX Multifunction Routing Register PCI offset 8Ch This register controls the seven multifunction terminals of the PCI1520 This register must be set before the interrupt mode is programmed in the Device Control register PCI offset 92h Card Control Register PCI offset 91h This register contains enable bits for RI OUT and SPKROUT Device Control Register PCI offset 92h This register contains the interrupt mode bits Power Management Capabilities Register PCI offset A2h This register is important for systems needing to wake from the D3 power state Bit 15 reflects whether or not PME is supported from D3cold Bit 4 is tied to bit 15 indicating that if PME is supported from D3cold the system must be providing auxiliary power Power Management Control and Status Register PCI offset A4h This register contains the PME enable bit bit 8 8 2 3 ExCA Compatibility Registers ExCA Interrupt and General Control Register EXCA offset 03 43h This register is used to route CSTSCHG interrupts via PCI interrupts 8 2 4 CardBus Socket Registers Socket Control Register and Socket Power Management Register CB offsets 10h and 20h These registers can be used to characterize how CB CLKRUN functions 12 PCI1520 Implementation Guide 9 1 EXAS INSTRUMENTS SCPA033 Power Management Considerations D3 Wake Information
35. now SKTPWR LOCK instead of RSVD This bit when set to 1b stops software from powering down the PC Card socket while in the D3 power state This may be necessary for wake on LAN Bit 6 in the Diagnostic register PCI offset 93h is now AOSPMEN which disables the oscillator power management features This bit is reserved in the PCI1225 Bit 14 in the Power Management Capabilities register PCI offset A2h is now read write with a default of 1 indicating the PCI1420 supports PME from D3cold when Vaux is provided This bit is read only zero in the PCI1225 12 3 Other Functional Differences The PCI1420 and PCI1225 are both natively supported by Windows XP Windows 2000 Windows ME and Windows 98SE PCI1520 Implementation Guide 21 SCPA033 13 Reference Schematics X TEXAS INSTRUMENTS The following schematics show the most basic implementation of the PCI1520 possible These schematics provide minimum functionality All interrupts are routed using IRQSER 22 NOTE THESE ARE THE PCI TERMINALS PLEASE REFER TO SECTION 4
36. nterface Specification Revision 1 1 PCI Mobile Design Guide Revision 1 0 PCI1520 Implementation Guide IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other
37. status register PCI offset B3h bits 7 5 0 ExCA identification and revision register ExCA offset 00h bits 7 0 ExCA global control register ExCA offset 1Eh bits 2 0 Socket present state register CardBus offset 08h bit 29 Socket power management register CardBus offset 20h bits 25 24 PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 9 1 2 PME Context Registers 9 2 9 3 If the PME enable bit bit 8 of the power management control status register PCI offset A4h is asserted then the assertion of PRST will not clear the following PME context bits If the PME enable bit is not asserted then the PME context bits are cleared with PRST The PME context bits are e Bridge control register PCI offset 3Eh bit 6 e System control register PCI offset 80h bits 10 9 8 e Power management control status register PCI offset A4h bits 15 8 e ExCA power control register EXCA offset 802h bits 7 5t 4 3 1 0 T82365SL mode only e ExCA interrupt and general control register EXCA offset 803h bits 6 5 e ExCA card status change register EXCA offset 804h bits 11 8 3 0 e ExCA card status change interrupt configuration register EXCA offset 805h bits 3 0 e CardBus socket event register CardBus offset 00h bits 3 0 e CardBus socket mask register CardBus offset 04h bits 3 0 e CardBus socket present state register CardBus offset 08h bits 13 7 5 1 e CardBus socket control register CardBus offse
38. t 10h bits 6 4 2 0 PME RI_OUT Behavior PME and RI_OUT are very important for power management The PME signal is useful for PCI power management systems The RIl_OUT Ring Indicate Out signal is used for legacy power management systems PME and RI_OUT are multiplexed on the same pin The PCI1520 can also provide RI OUT on the Multifunction terminals To enable passage of Ring signals from the PC Card interface RINGEN bit 7 ExCA offset 803 must be set to 1 and RIENB bit 7 PCI offset 91h must be set to 1 This is a per socket function CLKRUN Protocol CLKRUNZ is a hardware method of clock control that can be used in parallel with other types of power management For the PCI1520 PCI CLKRUN can be programmed using the Multifunction Routing Register PCI offset 8Ch on MFUNC6 CardBus CLKRUNS is a required signal incorporated into the PC Card interface The following bits can be used to adjust the operation of how PCI and CB CLKRUN affect the PCI1520 Multifunction Routing register MFUNC6 PCI offset 8Ch bits 27 24 set to 0001b Requires a 43kQ pullup KEEPCLK System Control Register PCI offset 80h bit 1 Setting this bit to a 1 will never allow the PCI CLKRUN protocol to stop or slow the PCI clock PCI1520 Implementation Guide 15 9 4 10 EXAS SCPA033 INSTRUMENTS STOPCLK Socket Control Register CB offset 10h bit 7 This bit determines whether the CB CLKRUNE protocol is affect
39. the PC Card socket traces on the PCI1510 footprint For single socket implementations only one PC Card socket is populated along with the PCI1510 controller For dual socket implementation both PC Card sockets are populated along with the PCI1520 controller PCI1520 Implementation Guide EXAS INSTRUMENTS SCPA033 11 Migration to the PCI1520 from the PCI1420 The major differences between the PCI1520 and PCI1420 are pinout lower power consumption and lower cost The pinout is changed on the PCI1520 in order to incorporate an internal voltage regulator which allows the core to operate at 2 5V When moving from the PCI1225 to the PCI1520 please see Section 13 for the differences between the PCI1225 and PCI1420 in addition to the changes from this section 11 1 Hardware and Pin Assignment Changes The pinout on the PCI1520 is significantly changed from the PCI1420 This requires a PCB redesign A low dropout voltage regulator is integrated into the PCI1520 to supply 2 5V core voltage A voltage regulator enable pin VR_EN has been added in place of one of the VCCP pins A core voltage input output VRPORT pin has been added in place of the VCCI pin This pin is used to either input core voltage or allow for an external 1 0uF bypass capacitor depending on the value of VR EN A typical implementation would enable the regulator by grounding VR EN and adding the bypass capacitor from VRPORT to ground For further details see the datasheet
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