Renesas H8S Computer Monitor User Manual
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1. ECDIinteE if error 0 16 Direct Drive LCD Design Guide 4 1 4 LCDBacklight Direct Driver backlight control Format omo Ciel labo Ione as e Ye Parameters state Requested backlight state O off non 0 on Return Values None Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description This function is used to control the state of the LCD backlight Example LebBa coli do a back tone some Direct Drive LCD Design Guide 4 15 LCDSetFrameRate Configure the vertical refresh rate of the LCD panel Format STG ECD Sar rame Reese ee Parameters rate Requested refresh rate in Hz Return Values Negative value indicates rate was not able to be achieved with system configuration Positive value indicates success returned value will be the percent of MCU access time available Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description This function is used to control the vertical refresh rate of the LCD panel This function can be used to dynamically adapt the MCU access time based on system conditions For example prior to a full buffer refresh the rate can be dropped to increase access time than it can be restored to previous value for normal operation Example SI slices ss MODs ice rte E2. II LL Figure 5 H8SX SDRAM in Cluster Mode Note 1 To create the highest LCD Dot Clock frequency on the H8SX requires using cluster mode In this mode EDACK is not generated and an equivalent signal must be generated The above circuit creates the necessary timing 2 4 Driver Mode Configuration The driver characteristics are configured with the following macros 2 4 1 DOT CLOCK FREQUENCY_DATA This macro configures the dot clock frequency during the data transfer portion of the LCD update cycle This value must be achievable by the configured BCLK FREQUENCY and RAM configuration This value is checked against other system parameters and an error will be generated if the value is not achievable 2 4 2 DOT CLOCK FREQUENCY BLANK This macro configures the dot clock frequency during the blanking portion of the LCD update cycle This value must be achievable by the configured PCLK_ FREQUENCY as it generated by the TPU This value is checked against other system parameters and an error will be generated if the value is not achievable 2 4 3 DESIRED_FRAME_RATE This macro configures the initial selection of LCD frame rate The frame rate can also be modified at runtime via the LCDSetFrameRate API call To achieve the desired frame rate the vertical blanking time is extended beyond the values configured in the LCD panel configuration This value is checked against other system parameters and an error will be generated if the value is not achievable 2 4
3. 4 MINIMUM_MCU_ACCESS PCT This macro configures the user s minimum acceptable percentage of time that the MCU core has access to the frame RAM the MCU core only has access to the frame RAM during the vertical blanking time This value interacts with DESIRED_FRAME_RATE macro higher access percentage is achievable at lower frame rates as the bus is less consumed with frame updates This value is checked against other system parameters and an error will be generated if the value is not achievable 2 5 LCD Panel Configuration The LCD Direct Driver is configured to operate with a given LCD panel by setting macro definitions These values are readily available in the data sheet for the selected panel 2 5 1 DOT INVERT This macro is used to control whether the RGB data is latched on the rising or the falling edge of the dot clock If the macro is not defined the data is latched on the rising edge if it is defined the data will be latched on the falling edge Note that when using the multiplexed EDACK and TPU modes the EDACK signal will also need to be inverted in hardware for falling edge operation See section on dot clock hardware connections 2 5 2 V_LINES xx and H DOT xx Refer to the following diagram for definition of these values Direct Drive LCD Design Guide lklirizontal sm 5imal Figure 6 LCD Panel Macro Definitions 2 6 LCD Platform Configuration The LCD Direct Driver is configured to operate with a given hardware pla
4. Image V_LINES_INVERT Image Figure 3 Images from Various Display Settings Direct Drive LCD Design Guide 2 3 Driver Mode Selection There are several different modes of operation currently supported in the Direct Drive LCD driver The selection of operation mode depends on RAM type selection and LCD panel resolution 2 3 1 SRAM_DD Defining this macro selects a mode of operation that utilizes SRAM or PSRAM as the frame buffer In this operation mode the ExDMA ACK signal supplies the Dot Clock during data transfer and the TPU supplies the dot clock during blanking This is currently the only mode supported on the H8S family of MCUs 2 3 2 SRAM NOMUX DD Defining this macro selects a mode of operation that utilizes SRAM or PSRAM as the frame buffer In this operation mode the TPU supplies the dot clock during data transfer and blanking This operation mode can currently only be used on the H8SX on panels that do not require driving a data enable signal 2 3 3 SDRAM DD Defining this macro selects a mode of operation that utilizes SDRAM as the frame buffer In this operation mode the EXDMA ACK signal supplies the Dot Clock during data transfer and the TPU supplies the dot clock during blanking 2 3 4 SDRAM CLUSTER_DD Defining this macro selects a mode of operation that utilizes SDRAM as the frame buffer In this operation mode the Bus Clock signal supplies the Dot Clock during data transfer and the TPU supplies the dot clock
5. and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Renesas Technology Corp All rights reserved 25
6. being used enter 142 10 Direct Drive LCD Design Guide 2 6 10 Xxxx_TPU_CHANNEL Enter the channel number for the requested TPU signal For example if the H8SX DOTCLK is mapped to TPU TIOCBO enter 0 2 6 11 Xxxx_TPU_PIN Enter the pin letter for the requested TPU signal For example if the H8SX DOTCLK is mapped to TPU TIOCBO enter B Direct Drive LCD Design Guide 3 Typical LCD Panel Connections This section illustrates typical connections on an LCD panel and how they are interfaced to the MCU in a Direct Drive configuration 3 1 LCD panel interface Pin Number Symbol Description 1 Ground E Clock Signal 3 Honzontal Synchronous signal negative 4 Wertical Synchronous signal negative Ground E RED data signal LSB 7 RED data signal z RED data signal g RED data signal 10 RED data signal 11 E RED data signal MSB 12 Ground 13 GREEN data signal LSB 14 GREEN data signal 15 GREEN data signal 16 gt GREEN data signal 17 GREEN data signal 13 GREEN data signal Mob 13 Ground 20 BLUE data signal LSB 21 BLUE data signal e lt BLUE data signal 23 E BLUE data signal 24 BLUE data signal 25 E BLUE data signal MSB 26 Ground Ze signal to settle the horzontal display position posite 20 3 3v power supply EZ 3 3v power supply 30 Honzontal Display Mode 0 Normal 1 Left nght reversed 31 Vertical Display Mode 0 Normal 1 Up do
7. during blanking This mode is intended for LCD panels that have relatively high dot clock requirements VGA because the high speed Bus clock is used to drive the dot clock 2 3 0 Dot Clock Hardware Connections From the microcontroller the EDACK signal is fed into a mux with the Dot Clock to ensure the clock edge is sent at the time the valid data is on the bus Use inverter if DEN active high LCD DEN Use inverter if LCD CLK latches on falling edge LCD DOT CLK Figure 4 H8S SRAM and H8SX SDRAM Dot Clock Logic Note 1 When using the H8S devices or the H8SX devices with SDRAM it is also necessary to connect the EDREQ active low line to the mux This ensures that the clock remains synchronized in the time between blocks of data The H8SX running with SRAM uses a ExDMA mode which has a deterministic number of clocks between blocks and so can be relied on to give predictable timing the other modes have a latency which may take 4 or 5 clocks and so hardware synchronization is necessary Note 2 If the panel you are connecting to requires a Dot Clock inversion falling edge data transfers you must place an inverter gate between EDACK and the mux and define DOT_INVERT in the driver code Direct Drive LCD Design Guide Use inverter if DEN active high HDEN Use NOR gate if LCD CLK LCD DEN latches on rising edge LCD DOT CLK L DOTCLK_TPU 11 CLR Q
8. included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Re
9. logic drives the resistive endpoints with a known reference voltage and the level on the channel is read into an analog to digital converter ADC With calibration and scaling in the microcontroller driver code it is possible to pinpoint the area of the panel that was touched Action can be taken accordingly An example of interface circuitry between the MCU and touch screen is shown in Figure 6 below R2 TOUCH YU 1K Ct R1 Y DRIVE 1 10nF DNF UTA 3 XI R4 X DRIVE 4 TOUCH XL wie 1 gt iK C2 R3 HC126A i ane DNF IM Y R9 TOUCH YL MOLEX 52044 1K C4 R8 10nF DNF N R11 TOUCH XR 1K CR R10 10nF DNF NY Figure 8 Touch Screen Circuit 13 Direct Drive LCD Design Guide 3 2 Hardware Design Below is a block diagram of a LCD system which uses Flash and SRAM for respectively storing and buffering the images to be displayed The following table describes the TPU channels and pins used for direct drive Note that the TPU synchronization capability is used to create a common time base between the HDEN HSYNC and VSYNC pins Suggested TPU Channel Requirements Channel DOTCLK DOTPER HDEN HDEN2 same as HDEN HSYNC 0 or 3 VSYNC same as HSYNC HPER TGR to set horizontal period SERIAL Z Optional External Flash PORT e g SD Card Serial Flash Figure 9 Block Diagram Note 1 Dot Clock Logic Note 2 Touch Screen 14 Direct Drive LCD Design Guide 4 LCD API Definition 4 1 1 Standard Redefines The
10. regions of the active display window Note that LCDSetActiveRaster LCDSetRasterOffset and LCDSetLineSource are similar in function and interact Example pragma section LCD_Frames SRAM allocated for GUI display baler CUT O DUE a oO ADS AA e allocate panning buffer 4x panel LIS Stan Seno ner as E RDH ANETTE EREA E pragma section mota L DSe t Erne our om Uo Ur CUR DO ADELA GUIAR On VOud heCDSecr heme source 0 vol EINES PANEL OO SMMC uo ie oO iS e HAPOT DIES Ie ey Pan qu O 1 23 Direct Drive LCD Design Guide Website and Support Renesas Technology Website http www renesas com Inquiries http www renesas com inquiry csc renesas com Revision Record Description Rev Date Page 1 00 Jan 28 08 1 10 Apr 28 08 2 20 Jan 13 09 2 30 Mar 16 09 2 40 May 11 09 2 50 June 8 09 2 60 Sept 25 2009 Renamed H_DOT_RESOURCE to FRAME_WIDTH Summary First edition issued Updated Updated Updated Added LCDSetLineSource to the API Reformatted to new API style Renamed Y LINES RESOURCE to FRAME_HEIGHT 24 Direct Drive LCD Design Guide 10 11 12 13 2008 Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any l
11. Everywhere you imagine g E NJ ESAS H8S H8SX Series Direct Drive LCD Design Guide Version 2 6 User s Manual Direct Drive Solution Rev 2 60 Renesas Technology America September 2009 america renesas com Direct Drive LCD Design Guide Index E INTRODUC HON EEE HEHE HHEH 3 1 1 DIRECT DRIVE CD OVERVIEW esa 1 1 1 PR OS A A nat RE 3 LZ CAPTURAS ee Sa ok E OT eae eo 5 2 DRIVER CONFIGURATION ooo 4 Ded LCD DIRECT DRIVE CONFIGURATION MACROS sestasdsieitorssicsentstese cave iaoneondeteicarddeancorsdash dave thauverdeseivensdiaveons avs 22 ERAME BUEFER CONFIGURATION lt a e e e e o A 22d TRAME HEIGHT a a a aeai 6 222 ERAME WIDTH lo a aaa 6 Delo VANE Se INVERSA a lata 6 2 2 4 Tt TI E rO NY EIR Easiest ances ae li oie 6 2 2 5 PANT COTATI Sapp DAA AS Seer eae alts hen A NA A ibi 6 2 2 6 PE aE RAME een aT een ee AE PRO A A MERON AT ee eRe 6 22 MAX SP E L GLOW Si ii IA AA AS tn ats N ETO 6 2 3 DRIVER MODE gt ELECTION aos ETT 2 3 1 O A O N O E NEE 8 R Ps DRAM NOM OX PDD THT 8 2 3 3 RD 073101 TE css 8 2 3 4 SORAM CLUS LER PID TTT 8 EE DOF Clock Hardware TT T amp 2 4 DRIVER MODE TC ETB N N LOT 2 4 1 POF CLOCK RLOUENC Y DATA a E E ao 9 2 4 2 DOT CLOCK FREOU ENC Y BLAINE Nao 9 2 4 3 PESIRED ARAME TATE gt lt NS E A houston 9 2 4 4 MINT MMC ACCESS POT ta AAA A A EE 9 25 ECD PANEL CONFIGURA ION rt iaa Z9 POF INVER eai a AAA ES E EE E 9 202 VRINE HT 2 Cae BO 5 Aer Re ROE STE ASA AA 9 2 6 LEDPLATEORM CONFIGURATION ini a 2 6 1
12. NNEL Platform Configuration HDEN2_TPU_PIN_ Piala Configuration HDEN2_TPU_VECT_______ Platform Configuration DirectLCD_CNF platform h Direct Drive LCD Design Guide 2 2 Frame Buffer Configuration The frame buffer is the external memory area that is used to store the 16bpp image data that will be presented on the LCD screen The quantity of frame buffers is typically 2 or more This allows the MCU to be updating one frame wile the ExDMA is transferring the other frame to the LCD panel this behavior allows for fast transitions and the user does not see operations occurring in the non displayed buffers Typically the frame buffer is configured to the same dimensions as the LCD panel however the frame buffer can be larger to allow the LCD panel to act as a window into the frame buffer allowing for fast panning of large images The following macros control the sizing of the frame buffer 2 2 1 FRAME_HEIGHT Defines the number of lines in each of the frame buffers 2 2 2 FRAME _WIDTH Defines the number of dots columns in each of the frame buffer lines 2 2 3 V_LINES INVERT If defined flips the presentation of lines on the display 2 2 4 H DOT INVERT If defined flips the presentation of dots columns on the display 2 2 0 PANEL ROTATE Rotates the presentation of data rows columns on the LCD panel Only available on H8SX SRAM based modes 2 2 6 LCD FRAMES Defines the number of frame buffers allocated in the driver The
13. TV A A OR 10 2 6 2 FRAMI BUS COCTELES SEAN ESAS RE 10 2 6 3 NO A A O A 10 2 6 4 SDRAM TAOL TE AA NE 10 2 6 5 LOVAC DD ES o es io 10 2 6 6 A O ON 10 2 6 7 E O O EN 10 2 6 8 DON EO 0 O acetic 10 2 6 9 o RA A A IO 10 2 6 10 A T lI 2 6 11 E T ll 3 TYPICALCLCDPANELCONNECTIONS iea a a aa ices ees 3 1 CCDE AUNT TINT Fe Be se ae sc ee a a o e 3 1 1 POW CP SU GS A AE E aR 12 sA E1 E ETETA NE O A A O A AE AE et 12 3 1 3 A A a 12 3 1 4 SIMA iia 12 3 1 5 TT miann A AA RAS SA 13 3 1 6 RGD REG Green Blue DITA cnt fet te pacha aeRO Oe ola eae lata neh alk Reena 13 BAe TONCES COCCI A AS E E CEEA A NE 13 3 2 HARDWARE DESIGN oirin A E e edo Direct Drive LCD Design Guide de ECDAPLFDEFINITION eee ee rr arent cs 4 1 1 NANA TAR COCIIICS AAA AAN 15 4 1 2 LE PDAPT DOIG IPES ayi aaa 15 4 1 3 LED A E S 16 4 1 4 LEDBAR Ta T 17 4 1 5 ECDS a A I AAEE E E e eo al lel can ud dde Le 18 4 1 6 TCT GEE VIC zac ate o rl ba a od at e Eh Deleted la Le 19 Hals ECDSCACIVEN O rd e e bal lel Shan ed la cult ad 20 4 1 8 TEC DG ACI TM e ad Dd Te a 21 4 1 9 TES EA Sata 22 4 1 10 TCD SCLEIN GS OU A a da eo e as 23 WEBSITE AND SUPPORT ii iio REVISION RECORD Direct Drive LCD Design Guide 1 Introduction This document provides technical information of how to configure the LCD panel parameters required by Renesas LCD Direct Driver according to the LCD panel datasheet published by the manufacturers This document will also describe all the APIs Application Programmin
14. demonstration code value is two by default This value can be set to zero in which case the user code is responsible for the allocation of frame buffers 2 2 MAX FRAME REGIONS Defines the number of horizontal screen splits that can be used within the driver The demonstration code default value is 1 no splits This capability allows different source regions to be used with horizontal screen areas control GUI panning image view for example The default display sequence of a LCD panel is shown in Figure 1 The origin of the display is shown as the green dot in the picture By default the driver will send the raster image to the LCD panel in the same sequence If necessary there are two macros available to change the sequence of data presented to the panel V_LINES INVERT sends the top line first and sequences to the bottom and H_DOT_INVERT sends the right side of the line first and sequences to the left Either or both of these macros can be specified at the same time PANEL_ROTATE only available on H8SX is the macro to allow user image to be rotated in transfer to the panel as shown in the Figure 2 Direct Drive LCD Design Guide Wertical Lines Wertical Lines j TEE Aa ae K d X EE he a c M ly L hi F d 5 CV i F E 4 8 5 J a j ATT VT Et AE E E ra ner Andras K RS ae 7 7 s G L Horizontal Dots Left Right Figure 1 RAM Frame Raster Data TE Y a Default Imag H_DOT_INVERT amp V_LINES_INVERT
15. function and interact Example SiGe Op ey ae If LCDSetRasterOffset x y 0 IFSC TORS Sie Cree lal Nove taille iones 22 Direct Drive LCD Design Guide 4 110 LCDSetLineSource Defines the source regions of the active display window Format SILES hese E GRT STIG Region slo Crne Count Urlo SE T S Ie eliinescep Parameters Region Region of display horizontal strip Ranging from 0 to MAX_FRAME_REGIONS defined in DirectLCD_CNF h Normally region 0 starts at the bottom of the screen However when V_LINES_INVERT is defined to change line presentation on the screen region O will start at the top of the screen MAX_FRAME_ REGIONS should be set to 1 if multiple regions are not used this will eliminate any associated runtime overhead LineCount Is the number of lines associated with this region This value can vary from 1 to Y LINES PANEL pSource Address of the first pixel of the first line within the region The entire memory space of the region must be within the LCD_ Frames section or the request will not be accepted LineStep Distance in pixels ul16 s from first pixel of first line to first pixel of second line source regions can be wider than the panel Return Values 0 on success non 0 on failure Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description LCDSetLineSource defines the source
16. g Interface in the LCD Direct Driver and their usages An overview of the system hardware is also provided 1 1 Direct Drive LCD Overview The H8S and H8SX device families include several peripherals that enable the direct connection of RGB interface TFT panels directly to the MCU data bus These peripherals include the ExDMA external DMA controller unit and the TPU Timer Pulse Unit With these peripherals and an external RAM device for LCD frame buffer use the LCD panel can be refreshed using less than 5 of the MCU processing capacity 1 1 1 Philosophy The Direct Drive LCD solution was developed to provide a low cost long life solution for driving TFT panels for use in GUI applications with limited animation requirements This solution reduces the risk for products with relatively long life on volatile components such as stand alone LCD controllers TFT panels with integrated LCD controllers or application specific microprocessors 1 1 2 Capabilities The current features of the Direct Drive LCD solution are Ability to use standard PSRAM SRAM or SDRAM as frame buffer Ability to create multiple frame buffers within the available RAM Ability to dynamically modify frame rate to accommodate varying system update requirements Ability to drive RGB panels at 16bpp up to WVGA resolution at up to 60Hz frame rates Ability to pan larger display regions within a portion of the LCD panel area Very simple operation model user code man
17. hich synchronize these signals to the ExDMA request line This ensures that the clocks are generated when valid data is available on the bus 3 1 5 Data Enable Many panels require an additional signal to frame the valid data this enable signal is sent at the time the valid data is latched onto the bus the panel will then clock in the data on the next edge of Dot Clock It provides added synchronization for the timing of data but this signal can often be left in the active state if the Dot Clock synchronization to the data is predictable 3 1 6 RGB Red Green Blue Data The data is presented to the panel in parallel LCD panels have connections for 6 or 8bits of data for each color totaling 18 or 24bits of color resolution Our solution uses a 16bit data bus so the most significant bits of the data are presented to the panel RGB 5 6 5 is the most common 16 bit solution The least significant bits can be tied low or better still to the MSB which would give a slightly improved range over tying to ground Specifically with respect to Renesas H8S and H8SX devices we use the ExDMA module to control the data bus transfers 3 1 Touch Screen Our support is currently for popular resistive touch screen panels which have 4 connections endpoints of an X axis resistance and Y axis resistance These inputs provide resistances proportional to the touched location particular X and Y coordinates on the panel The host system microcontroller plus
18. icense to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information
19. ipulates images in the frame buffer The frame buffer is transparently transferred to the LCD panel The Direct Drive LCD solution is highly configurable and capable of producing many different timing configurations which drive the input signals of TFT LCD panels from various panel manufacturers The signal timing generated from the Direct Drive LCD solution depends on your choice panel resolution frame buffer memory and desired panel refresh and animation rates Although Renesas provides guidelines and examples for configuring the signal timing Renesas is not responsible for meeting the AC timing specifications of your specific choice of TFT LCD panel Please contact your TFT LCD panel manufacturer to ensure the Direct Drive LCD solution complies with the panel timing limitations Direct Drive LCD Design Guide 2 Driver Configuration The LCD Direct Driver is configured through the setting of macro definitions These macros are illustrated in the sample code The following table briefly describes the location of each of these macros and their location in LCD Direct Drive demonstration code For examples of each macro usage refer to the demonstration code 2 1 LCD Direct Drive Configuration Macros Macro Name Description Units Demo Location System Clock Configuration 2 1722323 3 AA IO A FRAME_HEIGHT Frame Buffer Configuration FRAME_WIDTH Frame Buffer Configuration V_LINES_INVERT__________ Frame Buffer Configu
20. mene ise wo 190 da MSM SS SIN Oe CS Mea Sy 18 Direct Drive LCD Design Guide 4 16 LCDGetFrameRate Request the vertical refresh rate of the LCD panel Format SIMA CS tame Re oa Parameters none Return Values Current frame rate in Hz Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description Request the current vertical refresh rate of the LCD panel Example s116 old_rate LCDGetFrameRate AGS E ame E preto o changes 77 i 19 Direct Drive LCD Design Guide 4 1 7 LCDSetActiveRaster Set memory frame to display Format PS LEDS Sernac el ad ise Parameters frame Requested frame buffer index Return Values Pointer to first pixel of frame raster Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description Request the current vertical refresh rate of the LCD panel Note that LCDSetActiveRaster LCDSetRasterOffset and LCDSetLineSource are similar in function and interact Example ull6 frame_request GA See le Ch tourer Pramembegue sien A S ETT H E L select_buffer LCDSetActiveRaster frame_request i Sige IE 20 Direct Drive LCD Design Guide 4 18 LCDGetActiveFrame Request which memory frame is currently displayed Format pS EOS T rae NVO Parameters none Retu
21. nesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware
22. ration H_DOT_INVERT_____________ Frame Buffer Configuration PANEL_ROTATE________ Frame Buffer Configuration LCD_FRAMES Frame Buffer Configuration MAX_FRAME_REGIONS Frame Buffer Configuration A eee E E SRAM_DD_ Driver Mode Selection _ SRAM_NOMUX_ DD Driver Mode Selection SDRAM_DD Diye Mode Selection _ SDRAM_CLUSTER_DD_ Driver Mode Selection A O O DOT_CLOCK_FREQUENCY_DATA Driver Mode Configuration DOT_CLOCK_FREQUENCY_BLANK Driver Mode Configuration DESIRED_FRAME_RATE______ Driver Mode Configuration MINIMUM_MCU_ACCESS_PCT Driver Mode Configuration O O A eee DOT_INVERT_____________ LCD Panel Configuration V_LINES_ PULSE LCD Panel Configuration V_LINES_BACK_PORCH LCD Panel Configuration V_LINES_DISPLAY LCD Panel Configuration V_LINES_FRONT_PORCH_______ LCD Panel Configuration DirectLCD_CNF panel h HL DOL Pulse LCD Panel Configuration H_DOT_BACK_PORCH LCD Panel Configuration H_DOT_DISPLAY LCD Panel Configuration H_DOT_FRONT_PORCH________ LCD Panel Configuration DirectLCD_CNF panel h Direct Drive LCD Design Guide Macro Name Description Units Demo Location FRAME CS Piala Configuration FRAME BUS CYCLES Platform Configuration CAS_LATENCY Platform Configuration SDRAM_PAGE_SIZE Platform Configuration VSYNC_PORT Piala Configuration VSYNC_PIN Platform Configuration HSYNC_PORT___________ Platform Configuration HSYNC_PIN Platform Configu
23. ration DOTCLK_PORT___________ Platform Configuration DOTCIK PIN Platform Configuration LCD_BACKLIGHT_PORT____ Platform Configuration LCD_BACKLIGHT_PIN__ Platform Configuration EXDMAC_DD_ Platform Configuration EXDMAC_DD_INTC______ Platform Configuration EXDMAC_DD_VECT______ Platform Configuration EXDMAC_DD_REQ_PORT____ Platform Configuration EXDMAC_DD_REQ PIN Platform Configuration DOTCLK_TPU_INTC_____ Platform Configuration DOTCLK_TPU_CHANNEL Platform Configuration DOTCLK_TPU_PIN__ _ Platform Configuration DOTCLK_TPU_VECT_____ Platform Configuration DOTPER_TPU CHANNEL Platform Configuration DOTPER_TPU_PIN_______ Platform Configuration DirectLCD_CNF platform h DOTPER_TPU_VECT________ Platform Configuration HPER_TPU_INTC Piala Configuration HPER_TPU_CHANNEL Platform Configuration HPER_TPULPIN Platform Configuration HPER_TPU_VECT_______ Platform Configuration HSYNC_TPU_INTC_______ Platform Configuration HSYNC_TPU_CHANNEL_ Platform Configuration DirectLCD_CNF platform h HSYNC_TPULPIN Platform Configuration HSYNC_TPU_LVECT Platform Configuration VSYNC_TPULINTC Platform Configuration VSYNG_TPU_CHANNEL Platform Configuration VSYNC_TPU_LPIN Platform Configuration VSYNC_TPU_VECT_______ Platform Configuration HDEN_TPU_INTC_______ Platform Configuration HDEN_TPU_ CHANNEL Platform Configuration HEN TEU PIN _ Platform Configuration HDEN TPU VECT Platform Configuration HDEN2_TPU CHA
24. rn Values Index of active frame raster Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description Request which memory frame is currently displayed Note that this function only returns valid information when LCDSetActiveRaster is used to control the display content as opposed to LCDSetLineSource Note that LCDSetActiveRaster LCDSetRasterOffset and LCDSetLineSource are similar in function and interact Example ull6 frame_request frame_request LCDGetActiveFrame So E E if frame_request 0 LCDSetActiveRaster 1 else LCDSetActiveRaster 0 21 Direct Drive LCD Design Guide 4 19 LCDSetRasterOffset Request display location within larger raster image Format srie DeDsStRaster Orsini S L ye Parameters x X offset in pixels within the raster Y offset in pixels within the raster Return Values 0 on success non 0 on failure Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description LCDSetRasterOffset changes the display position within the raster The offset is limited to be within area allocated by the FRAME_HEIGHT x FRAME_WIDTH space lf raster is the same size as the panel the offset cannot be changed fixed to 0 0 Note that LCDSetActiveRaster LCDSetRasterOffset and LCDSetLineSource are similar in
25. se following type have been redefined in order to make the code easier for formatting Eypeder Unsigned char wits Us o iso bss slo uds typedef signed char Sie ISA o NES ty ped r UNnSmgmned Shore iio joa Wievsaloiiech T T I TT oa sI16 cea Witheceis Ss OE Eypeder unsigned long uo jo ia Sato ies nte en E typedef signed long SiS IS a lUntecien EI 4 1 2 LCD API Data Types These data types are used within the API to support API calls typedef enum TODAS Rs or SEO ECDARIT TERR UNINITIALIZED e capitel nto Eon alka Zee on ESDALITERESUN SUBO TES LCDAPI_ERR_INVALID_PARAMETER IE CIDE IES OER INOUE IA SI G E ERRA ODDADDRE O I LT HT elle Ses R RE E A DEF 15 Direct Drive LCD Design Guide 4 1 3 LCDInit Direct Driver Initialization Format LCDET COC EITE gba Asoc Parameters none Return Values 0 if successful non zero if failure Properties Prototyped in file DirectLCD h Implemented in file DirectLCD_SBF c for H8S family or DirectLCD_XBCFT c for H8SX family Description This function is used to initialize the hardware necessary for the Direct Drive LCD to execute This function uses the configuration macros to set up the TPU and ExDMAC peripherals to transfer data from the frame RAM to the LCD panel After this function successfully executes the transfer of data to the panel by ExDMAC will start and interrupts will be generated on every line to service the ExDMAC Example LCDEErorlypc error
26. tform by setting macro definitions These values will have to be determined from the schematics on the hardware platform As an example the demonstration code can be compared the LCD direct drive hardware schematics 2 6 1 FRAME_CS This is the numeric value of the CS pin used for the frame buffer for example if CS2 is used a value of 2 would be entered 2 6 2 FRAME_BUS_CYCLES Enter the number of BCLK cycles that are required to access the frame RAM only used in SRAM configurations 2 6 3 CAS LATENCY Enter the configured CAS latency for the SDRAM only used in SDRAM configurations 2 6 4 SDRAM_PAGE_SIZE Enter the SDRAM page size in words only used in SDRAM configurations 2 6 5 EDMAC_DD Enter the name of the ExXDMAC being used for the LCD Direct Drive For example if EXDMAC channel 2 is being used set the value to EXDMAC2 2 6 6 Xxxx_PORT Enter the associated port for the requested signal mapping For example if the LCD BACKLIGHT is on port PM1 set the port value to M 2 6 7 Xxxx_PIN Enter the associated port for the requested signal mapping For example if the LCD BACKLIGHT is on port PM1 set the pin value to 1 2 6 8 Xxxx_INTC Enter the SFR field for the associated interrupt controller peripheral For example if the H8SX ExDMAC 2 is being used enter INTC IPRJ BIT _ EXDMAC2 2 6 9 Xxxx_VECT Enter the interrupt vector number for the associated peripheral For example if the H8SX ExDMAC 2 is
27. wn reversed 32 VGAQWGA select 33 Ground Figure 7 Example Connections for a Kyocera TFT LCD Panel 3 1 1 Power Supplies Many panels require multiple supplies Check your panel s specification to see how many ground and different voltage level connections it requires In the example case of a Kyocera 320x240 panel 6x Ov GND lines are required along with 2x 3 3v reference voltages In addition the backlight power supply is also required 3 1 2 Clock Often referred to as the Dot Clock the panel requires a synchronous clock signal to provide logic edges for clocking in data The Red Green Blue RGB parallel data should be present on the data bus at the time of each rising edge of the clock This provides the color setting for each individual pixel in turn Read more about our specific implementation of the Dot Clock and the associated hardware options in Section 4 3 1 3 HSync Each period of HSync contains the Dot Clocks and data for each horizontal line on the panel 3 1 4 VSync Vsync provides synchronization for each packet of valid data in each line of pixels The total time for the 12 Direct Drive LCD Design Guide entire panel to fill with valid pixels is the maximum refresh rate Displays in existing media systems usually have refresh rates between 48Hz and 120Hz to avoid visible flicker HSync VSync and Dot Clock are all generated using TPU channels of the H8S or H8SX microcontrollers The TPU allows timer compare actions w
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