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Motorola MVME1X7P Computer Hardware User Manual

1. OFFSET D31 D24 D23 D16 00 CHIP ID CHIP REVISION 04 TIC TIMER 1 08 TIC TIMER 1 oC TIC TIMER 2 10 TIC TIMER 2 14 PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST GPI GPI GPI GPI GPI GPI GPI GPOE GPO 18 PLTY E L INT IEN ICLR IRQ LEVEL Scc scc scc scc scc scc scc scc 1C RTRY PAR EXT LTO SCLR MDM MDM MDM pu ELEM ERR ERR ERR ERR ERR AVEC o 20 24 SCC TRANSMIT PIACK LAN LAN LAN LAN 28 PAR EXT LTO SCLR ERR ERR ERR scsi scsi scsi scsi 2C PAR EXT LTO SCLR ERR ERR ERR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR FAULT 30 ACK ACK ACK ACK ACK IRQ LEVEL FLT FLT FLT FLT FLT IRQ LEVEL PLTY E L INT IEN ICLR PLTY E L INT IEN ICLR PRTR PRTR PRTR PRTR PRTR 34 BSY BSY BSY BSY BSY EVE PLTY E L INT IEN ICLR 38 CHIP SPEED 3C SCC PROVIDES ITS OWN VECTORS This sheet continues on facing page 1 32 Computer Group Literature Center Web Site Memory Maps D15 D8 D7 DO CPU FAST DRO 040 n BRAM VECTOR BASE REGISTER COMPARE REGISTER COUNTER REGISTER COMPARE REGISTER COUNTER REGISTER OVERFLOW eye er OVERFLOW leer COUNTER 2 2 COUNTER 1 1 1 2 2 TIC TIMER 2 tict T
2. AC AB SYS MWP PE TIC2 VME DMA 963 962 961 5160 LMO 68 FAIL IRQ FAIL BERR IRQ IRQ IRQ IRQ IACK IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN 6C IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 70 CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR 74 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 78 AC FAIL ABORT SYS FAIL MST WP ERROR IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IACK DMA SIG 3 SIG 2 7C IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 80 sw7 SW6 SW5 sw4 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 84 IRQ 7 VME IRQ 6 VME IRQ 5 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL T VECTOR BASE VECTOR BASE d S D ABORT GPIOEN REGISTER 0 REGISTER 1 EN kieva il tevet 8C This sheet continues on facing page 2 24 Computer Group Literature Center Web Site LCSR Programming Model EGE eee D VME LOCAL W ACCESS BUS TIME OUT PRESCALER TIMER TIMER SELECT CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER
3. 4 8 MM T 4 9 Chip bon OPERAE HE RR POR VY EUR DUE IURE URS 4 9 rud a0 es 4 10 Chip ID Redite 4 13 Chip Revision ISEren 4 13 Memory Configuration eR 4 14 Registe PEE eneen o e 4 15 DRAM Control Register rere Rebate cde Pra Feet VUE HRS RYE RUE EU S FERE 4 15 Frequency Crac e neue 4 16 Data Control Register uui eere eres iE 4 17 ROG SIE Ser 4 19 Scr b Period Register Bits 3 8 cocer rtt edens e er Ives 4 20 Scrub Period Resister Bits 7 0 RU E 4 20 Chip Prescaler Counters EUER HEROS 4 21 Scrub Time On Time CHE Hoe porto ERR CELO Do APO ped pd 4 21 Prescaler Coumer orc etre eerie 4 23 Scrub Prescaler Counter Bits 1058 uo HIER URS 4 23 scrub Prescal er Counter f BIS 4 24 Scrub Tuner Counter Bits 13598 4 24 Somo Timer Counter Bis T4 uai cua ARR FERAE EN RES FIRE 4 25 Scrub Address Counter Bits 4 25 scrub Address Counter Bits 23 18 4 26 Scrub Address Counter Bris sou op ERN Id Np EM 4 26 ecru Address Counter BiS 4 26 Ber
4. Offsets Bit Numbers VM Loca E lBus 15 14 13 12 11 10 9 8 7 6 5 4 53 2110 bus 0 0 Chip Revision Chip ID 2 4 s st st st Rs Is B sco sysF XI X X 3 2 1 0 Gi G0 T F F N L 4 8 General Purpose Control and Status Register 0 6 C General Purpose Control and Status Register 1 8 10 General Purpose Control and Status Register 2 A 14 General Purpose Control and Status Register 3 C 18 General Purpose Control and Status Register 4 E General Purpose Control and Status Register 5 VMEchip2 Revision Register ADR SIZ Local Bus FFF40100 VMEbus XXYO 8 bits BIT 15 m 8 NAME VMEchip2 Revision Register OPER R RESET 01 PS This register is the VMEchip2 revision register The revision level for the VMEchip2 starts at 0 and is incremented if mask changes are required The VMEchip2 used on the 1 is revision 01 or greater http www motorola com computer literature 2 103 VMEchip2 VMEchip2 ID Register ADR SIZ Local Bus FFF40100 VMEbus XXYO 8 bits BIT 7 24 0 VMEchip2 ID Register OPER R RESET 10 PS This register is the VMEchip2 ID register The ID for the VMEchip2 is 10 VMEchip2 LM SIG Register ADR SIZ Local Bus FFF40104 VMEbus 2 8 bits BIT 15 14 13 12 11 10 9 8 NAME
5. Pt B 3 Figure B 2 MVME1X7P Serial Port 1 Configured as DCE http www motorola com computer literature Printer and Serial Port Connections 0v6 E E 1 1 ii 1 1 1 i 71 1 I d 1062 g ag SLO govs LOW T 1 1 02 ET 11 09 90rSP LOW 1 2 it 1 1 1 1 1 1 820 ge 90 9 LOW MEE 1 y 4 1 1 1 1 I 1 I 1 1 I T 1 1 1 1 I d ARA 9 usa 1 d T 1 Pu e E 4 he 5 x SLO 7622 65 90SP LOW I 8 gt 151 FEO 09 90S LOIN t axe uS NE LEE NE
6. COUNTER OVERFLOW eus LEE E OVERFLOW seek Ae COUNTER 2 A COUNTER 1 1 1 SCALER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sw swe sws sw4 sws sw2 Swi swo SPARE VME VME VME VME VME RQ Ra RQ RQ IRQ7 IRQS 1804 IRQ2 IRQI EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET SET set set SET SET SET IRQ IRQ IRQ 15 14 13 12 11 10 9 8 CLR CLR CLR IRQ IRQ IRQ 15 14 13 12 11 10 9 8 IRQ1E TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SIG 1 SIG 0 LM 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SW3 swe swi swo IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IRQ 4 VMEB IRQ 3 VME IRQ 2 VME IRQ 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL GPIOO GPIOI GPI REV DIS DIS My DIS EN DIS EN FROM SRAM MST gay BSYT INT BGN 1361 9403 lt _ This sheet begins on facing page http www motorola com computer literature 2 25 VMEchip2 Programming the VMEbus Slave Map Decoders This section includes programming information for the VMEbus to local bus map decoders The VMEbus to
7. Address Range Description Size Bytes FFFC1EF8 SFFFCIEFB Version 4 FFFCIEFC FFFCIF07 Serial Number 12 8 FFFC1F17 Board ID 16 FFFC1F18 FFFC1F27 PWA 16 FFFC1F28 FFFC1F2B Speed 4 FFFCIF2C FFFC1F31 Ethernet Address 6 FFFCIF32 FFFC1F33 Reserved 2 FFFCIF34 FFFC1F35 SCSI ID 2 FFFC1F36 FFFC1F3D System ID 8 FFFC1F3E FFFC1F45 Mezz Board 1 PWB 8 FFFC1F46 FFFC1F4D Mezz Board 1 Serial Number 8 1 42 Computer Group Literature Center Web Site Memory Maps Table 1 13 BBRAM Configuration Area Memory Map Address Range Description Size Bytes FFFCIFAE FFFC1F55 Mezz Board 2 PWB 8 56 FFFC1F5D Mezz Board 2 Serial Number 8 FFFCIFSE FFFC1FF6 Reserved 153 FFFCIFF7 Checksum 1 Table 1 14 TOD Clock Memory Map Address Data Bits Function 7116543210 FFFCIFF8 W 5 Calibration Control FFFCIFF9 ST Seconds 00 FFFCIFFA x sd Minutes 00 FFFCIFFB x x Hour 00 FFFC1FFC x FT x x x Day 01 FFFCIFFD x x Date 01 FFFCIFFE x x x Month 01 FFFCIFFF Year 00 Notes W Write Bit R Read Bit S Sign Bit ST Stop Bit FT Frequency Test x Must be set to 0 The
8. 3 7 e 3 9 Oyerall Memory D cc ee 3 10 ausis nn m 3 11 T 3 14 3 14 enera Conteol aet aper e Mos p MUS 3 15 PRIEST BISE iiri a DR 3 16 Programming the oec roter citer rere ipe S trt verti 3 18 Tick Timer 1 Compare Reglstet tpe 3 18 Tick Timer 1 COU e 3 19 Tick Timer 2 Compare Reglslet sone paper bb ERAI HIM DL ER Et do aia 3 19 Tick Timer 2 rore rp winners 3 20 Prescaler Count Register 3 20 Prescaler Clock Adjust 3 20 Tick Timer 2 Control Beplstet eese bre DENDUM 3 22 Tick Timer 1 Control 3 23 General Purpose Input Interrupt Control 22 3 24 General Purpose Input Output Pin Control 3 25 Tick Timer 2 Interr pt Control 3 25 Tick Timer 1 Interrupt Control Register rete 3 26 SCC Error Status and Interrupt Control Registers sees 3 27 SCC Eror Status Rag fele Ha DR ORI A UT Tab 3 27 SCC Modem Interrupt Control Register oc e erar tiens 3 28 SCC Transmit Interrupt Control Register oii treo eter reae
9. 1 47 Cache Coherence INDY WIE LG crupina iekea ike enni ii R RR ARM 1 49 Cache Cohereney I F AE 1 50 Tere Bis TREES a R 1 51 Iii BOSS 1 52 Supervisor Stack Pointer MCBBSODU anr n arara r ER 1 53 nottiess or 1 54 Bus Time OU a 1 54 INI DUS Access BUDE EU mI 1 54 252 1 54 VMESNI PHA 1 55 Bus Error Processing aae 1 55 Eror ds cna he eee eee E EM dai 1 55 MPU Parity qu 1 56 RN E ere MEDIE 1 56 MPU TEA Cause Umidentitied usos exe 1 56 MPU Local Bus uu npe 1 57 DMAC VME DUS RED EF 1 57 DMAC m 1 57 DMAC Offboard essen np a 1 58 DMAC LE 1 58 DMAC TEA Cause Unidentified ensconce 1 59 SCC lids qe 1 59 SCC Parity BITOt 1 60 VUE BANDI NNI A HH 1 60
10. ADR SIZ FFF42004 32 bits BIT 31 OR 0 NAME Tick Timer 1 Compare Register OPER R W RESET OP Computer Group Literature Center Web Site Programming Model Tick Timer 1 Counter The Tick Timer 1 Counter is a 32 bit read write register located at address FFF42008 When enabled it increments every microsecond Software may read or write the counter at any time ADR SIZ FFF42008 32 bits BIT 31 62 0 Tick Timer 1 Counter OPER R W RESET X Tick Timer 2 Compare Register The Tick Timer 2 Compare Register is a 32 bit register located at FFF4200C The count value of Tick Timer 2 is compared to this register When they are equal an interrupt is sent to the Local Bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to determine the compare register value for a specific period compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at zero the time to the first interrupt may be longer or shorter than expected The rollover time for the counter is 71 6 minutes ADR SIZ FFF4200C 32 bits BIT 31 ix 0 NAME Tick Timer 2 Compare Register OPER R W RESET OP http www mot
11. Data Control Register ADR SIZ 1st FFF43020 2nd FFF43120 16 bits BIT 31 30 29 28 27 26 25 24 NAME 10 0 DERC ZFILL RWCKB 0 0 0 R R W R W R W R R R RESET X X IPLS OPLS OPLS X X X RWCKB READ WRITE CHECKBITS when set enables the data from the seven checkbits in the Petra MCECC sector bits 30 24 to be written and read on the local MC680x0 data bus This bit should be cleared for normal system operation Note that if test software forces a single bit error to a location line using this function the scrubber may correct the location before the test software gets a chance to check for the single bit error at that location This can be avoided by disabling scrubbing and making sure that all previous scrubs have completed before performing the test Also note that writing bad checkbits can set the ERRLOG bit in the Error Logger register http www motorola com computer literature 4 17 MCECC Functions The writing of checkbits causes the MCECC sector to perform a read modify write to DRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered by the write checkbits operation To avoid this it is recommended that the DERC bit also be set while the RWCKB bit is set A suggested sequence for performing read write checkbits is as follows 1 Stop all scrub operations by c
12. 1 TOYLNOO gt viva viva 0314 SN 1 201 OL SNAIWA YALSVW sna 1 201 Sng83WA Ss3uaav Ssauaav 7031409 7031409 H31SVW 518 WOOT 7OHINOO 7031405 Ssquaav 55 55 7051405 7031405 7031405 S31A8 t A8 AHLN3 91 viva viva Kiva SNEAWA Odld4 SNEAWA OL SNE 1v201 7031405 ssayqqv 5 Ss3uadav 70519405 7051405 7031405 7OHL1NOO 44 gt S31A8 p A8 AHIN3 t YALSV SNESWA 0314 TOHLNOD ssayqqv OHINOO TOHLNOD viva viva SN W907 ssauaav TOHLNOD viva sng voo1 Figure 2 1 VMEchip2 Block Diagram 2 5 iterature www motorola com computer l http VMEchip2 Using the four programmable map decoders separate VMEbus maps can be created each with its own attributes For example one map can be configured as A32 D32 with write posting enabled while a second map can be A24 D16 with write posting disabled The first I O map decoder decodes local bus addresses FFFF0000 through FFFFFFFF as the short I O A16 D16 or A16 D32 area The other provides an A24 D16 space at F0000000 to FOFF
13. ADR SIZ 1st FFF43038 2nd FFF43138 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 SPS21 SPS20 SPS19 5 518 SPS17 SPS16 OPER R wW R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0PLS Scrub Prescaler Counter Bits 15 8 This register reflects the current value in the scrub prescaler bits 15 8 ADR SIZ 1st FFF4303C 2nd FFF4313C 8 bits BIT 31 30 29 28 27 26 25 24 NAME 5 515 SPS14 SPS13 SPS12 SPS11 SPS10 SPS9 SPS8 OPER R wW R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0PLS http www motorola com computer literature 4 23 MCECC Functions Scrub Prescaler Counter Bits 7 0 This register reflects the current value in the scrub prescaler bits 7 0 ADR SIZ 1st FFF43040 2nd FFF43140 8 bits BIT 31 30 29 28 27 26 25 24 NAME SPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPSI SPSO OPER R W R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS OPLS Scrub Timer Counter Bits 15 8 This read write register is the Scrub Timer counter If scrubbing is enabled and the Scrub Period register is non zero the Scrub Timer counter increments approximately once every two seconds until it matches the value programmed into the Scrub Period register at which time it clears and resumes incrementing Writes to this address update the
14. t VAN i T 2 1 i bres 1 1 1 1 1 1 1 i m vey NEN EE i bres 1 1 f 1 1 1 1 Ji i i i i 5 NS Nae bres 012 1 1 D E MF vies 1 1 1 1 1 1 1 612 1 bres 1 1 1 1 1 1 1 gu le T is T b T pod li ves 330 v83T 0 6 1 1 1 1 1 1 1 8 9 T T T T T T T 8 M 9 2 8 Y a M A 1 8 M 1 1 1 1 1 1 1 a v Nosan NId9 ped mavo QuvO8 anoo ga1avav WZLZSWAW V d dap oq dLLISWAW d29 SWAN e eC M Ere cce cetero ee epi Lu of Diet ee J PSA De eT aces NC I IC enu cam qu ap ce Lac Computer Group Literature Center Web Site Figure B 1 MVME1X7P Printer Port with MVME712M B 2 Conne
15. 90vSv LOIN Lorzao n 1 1 quvoa gvo quvoa NOLLISNVHLL QNOO Wald Vay Zd dLLI3IWAN 4 9 AWA LT nl DM AES ev RD IURE R ND ew ee sae aed Figure B 3 MVME1XTP Serial Port 2 Configured as DCE Computer Group Literature Center Web Site B 4 Connection Diagrams 5096 0681 Tt Ic EEUU I 1 i I I 1 I 1777 0 59 2819 90950 LOW I 4 1 H 1 i aoe 1277 ar 2 90 Sr LOW 1 1 pU se 90vSr LOW I f 1 I 1 I M 1 1 t 1 1 I l 1 1 1 1 1 I i M 1 1 I 1 I d zu Lev 79
16. I 1 1 4 E BREF jeune 90vSLON i T7 90vSLON I Simo eun 90rSPLOW 12109 1 1 auvoa guavo NOILISNVHL Wad VV ZLZ3WAN zd dLLISWAN 4 9 3INAW Figure B 5 MVME1XTP Serial Port 4 Configured as DCE Computer Group Literature Center Web Site B 6 i iagrams Connection Diagr l mM 0819 d vS 1 1 1 i 92 m ag ys 98 1 8 S19 vzo 90 LOIN 1 5 4 1 1 2 1 m 1 af ME S 2 1 m i 1520 90950 LOIN ua ET 2 1 gt S1H d 21 7 90 LOW T 0c i 1 2 som NC 2 1 2 zga gavo qNOO quvog E am NOLLISNVH L ZANAN OOOO EEA E O B 7 DTE figured as V
17. 9079 LOW t 1 1 h 281H eov 59 90vSv LOW 90vSt LOW lopzao gvo quvoa NOLLISNVHL QNOD Wad vay ZLZ3WAN 99001 za dLLISWAN d29 V3INAW Tei PUN wal lem JJ EM M B 5 Figure B 4 MVME1XTP Serial Port 3 Configured as DCE http www motorola com computer literature Printer and Serial Port Connections 0v6 ISEL E p 4 p 4 1 I ii 1 1 I 1 I DERI a 90vSv 1 Tm 90vSv LOW T I Hu 92v 90 LOW i 1 1 M SIX gt H o vOXLY i i 82 o c 90rSb ON 4 1 1 IOXH i 15 nt 9 VOXEL 12 5079710 sir 0 1 A 90tSvLON
18. ADR SIZ FFF42002 8 bits DIR 15 14 13 12 11 10 9 8 NAME DRO C040 MIEN FAST OPER R W R W R W R W RESET V PL 0 0 0 0 OP 0 PL OP FAST Note MIEN This control bit tailors the control circuit for BBRAM to the speed of BBRAM The PCCchip2 runs at half the MPU speed on the MVME177P For example an MVME177P with a 50 MHz MPU will run the PCCchip2 at 25 MHz When operating at 25 MHz the FAST bit should be cleared for devices with access times longer than 200 ns 5 CLK cycles The bit can be set for devices that have access times of 200 ns or faster It is not allowed to use devices slower than 360 ns 9 CLK cycles at 25 MHz When operating at 33 MHz the FAST bit should be cleared for devices with access times longer than 150 ns 5 CLK cycles The bit can be set for devices that have access times 150 ns or faster It is not allowed to use devices slower than 270 ns 9 CLK cycles at 33 MHz Master Interrupt Enable When this bit is high interrupts from and via the PCCchip2 are allowed to reach the MPU When it is low all interrupts from the PCCchip2 are disabled this includes both the EIPL pins and the INT pin Also when the bit is low all interrupt acknowledge cycles to the PCCchip2 are passed on via the ACKOUT pin This bit is cleared by a reset http www motorola com computer literature 3 15 PCCchip2 Vector Base Register C040 DRO Note
19. d zug F SLY v9 90rSPLOW t 1 9 gt 5 59 90rSrLOW gt 16 14 lt 90vSv LOW i 101299 EE 00 Po gvo quvoa NOLLISNVHLL QNOD Wad vay 29901 dLLI3WAN 4 9 wal lem JJ EM P Figure B 8 MVME1X7P Serial Port 3 Configured as DTE B 9 http www motorola com computer literature Printer and Serial Port Connections 0v6 SSEL E p E p 1 1 I ii 1 1 71 1 S H 6519 S19 62v 29 90 6 LOIN if 1 aod Hey e zu 90vSv LOW T I Hu fox 90 LOW I 1 Lo 1 M SIX 5 gt Du EV V 90vSvLOW E T gt oxi 90vSLON
20. by software see NOTE Computer Group Literature Center Web Site Supervisor Stack Pointer MC68060 Note Software emulation of CAS2 and misaligned CAS instructions is performed by the MC68060 Software Package which is included in all Motorola supplied operating systems for the MVME177P Contact your sales office for information about obtaining the MC68060 Software Package for use with other operating systems The single board computers do not fully support all RMW operations in all possible cases The modules make the following assumptions and support a limited subset of RMW instructions The single board computers support single address RMW cycles Multiple address RMW cycles are not guaranteed indivisible and may cause illegal VMEbus cycles Lock cycles caused by MMU table walks on the VMEbus do not cause illegal VMEbus cycles but they are not guaranteed do be indivisible On M68000 based systems aligned CAS and all TAS cycles are always single address RMW operations while misaligned CAS and CAS2 operations and operations in the MMU can be multiple address R MW cycles The VMEbus does not support multiple address RMW cycles and there is no defined protocol for supporting multiple address RMW cycles that start onboard and then access offboard resources Because it is not possible to tell if the processor is executing a single or multiple address read modify write cycle software should only execute
21. 2 54 DMAC Control Register 1 b08 Q T Luise teme mra tnrba horae ra 2 55 DMAC Control Register 2 bits 6 13 iussi emere etti been taie 2 57 DMAC Control Register 2 btg Q T bkn tines aces 2 58 DMAEC Local Bus Address Counter IEEE SE HIER ENDE Udo 2 59 DMAC VMEbus Address COUNTED 2 60 DMAE 2 60 2 60 VMEpus Interrupter Control Register i e rper 2 61 VMEbus Interrupter Vector Register 1 2 2 oret 2 62 MPU Status and DMA Interrupt Count Register 2 62 DNMAL REHISIBE nuin peritis ip itt 2 63 Programming the Tick and Watchdog cbe 2 64 VMEbus Arbiter Time Out Control Register eee 2 64 DMAC Ton Toff Timers and VMEbus Global Time out Control Register nitrate asta 2 65 VME Access Local Bus and Watchdog Time out Control Register 2 66 Piescaler Control 55 2 67 Tick Timer 1 Compare 2 2 68 Tiek Timer UOT Mem T 2 68 Tick Timer 2 Compare Register sosna 2 69 Tiek Timer C OUI recipi e S 2 69 Board Control Reglstat 2 70 Watchdog Tim
22. 32 bit Local Bus to VMEbus DMA Controller Programmable 16 bit 32 bit and 64 bit VMEbus data width Programmable short standard and extended VMEbus addressing Programmable AM code Programmable local bus snoop enable 16 four byte FIFO data buffer Up to 4 GB of data per DMA request Automatically adjustment of transfer size to optimize bus utilization DMA complete interrupt DMAC command chaining supported by a singly linked list of DMA commands VMEbus DMA controller requester with Software enabled fair request modes Software configured release modes Release On Request ROR and Release On End Of Data ROEOD Software configured BRO BR3 request levels and Software enabled bus tenure timer VMEbus Interrupter Software configured IRQ1 IRQ7 interrupt request level 8 bit software programmed status ID register Computer Group Literature Center Web Site Introduction Table 2 1 Features of the VMEchip2 ASIC Continued Function VMEbus System Controller Features Arbiter with software configured arbitration modes Priority Round Robin Select RRS Single level SGL Programmable arbitration timer IACK daisy chain driver Programmable bus timer SYSRESET logic Global Control Status Register Set Four location monitors Global control of locally detected failures Global
23. When this bit is high D16 data transfers are performed to the segment defined by map decoder 4 When this bit is low D32 data transfers are performed to the segment defined by map decoder 4 http www motorola com computer literature 2 43 VMEchip2 Local Bus Slave VMEbus Master Attribute Register 3 ADR SIZ FFF40028 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME D16 WP AM OPER R W R W R W RESET OPS OPS OPS This register is the attribute register for the third local bus to VMEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 3 Because the local bus to V MEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to the segment defined by map decoder 3 When this bit is low write posting is disabled to the segment defined by map decoder 3 When this bit is high D16 data transfers are performed to the segment defined by map decoder 3 When this bit is low D32 data transfers are performed to the segment defined by map decoder 3 2 44 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Slave VMEbus Master Attribute Register 2 ADR SIZ FFF40028 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME D16 WP AM OPER R W R W R W
24. 0 1 FFF43000 1 0 FFF43100 SELII and SELIO are initialized by hardware after a power up soft or local reset Their initialized state is determined by board level configuration resistors FSTRD The FSTRD control bit determines the speed at which SDRAM reads occur When itis 1 SDRAM reads happen at full speed When it is 0 SDRAM reads are slowed by one clock unless they are already slowed by NCEBEN http www motorola com computer literature MCECC Functions being set The state of FSTRD after a reset power up soft or local is determined by board level configuration resistors RWB6 Read Write Bit 6 is a general purpose read write bit RWB7 Read Write Bit 7 is a general purpose read write bit Defaults Register 2 ADR SIZ 1st FFF43078 2nd FFF43178 8 bits BIT 131 30 29 28 27 26 25 24 0 0 0 0 0 RESST2 RESSTI RESSTO OPER R W R W R W R W R W R W R W RESET 0 PLS 0 PLS 0 PLS VPLS 5 VPLS 5 It is not recommended that non test software write to this register RESST2 RESSTO These general purpose read write bits are initialized by a power up soft or local reset to match the RESST2 RESSTO bits from the reset serial bit stream 4 32 Computer Group Literature Center Web Site Programming Model SDRAM Configuration Register ADR SIZ 1st FFF4307c 2nd FFF4317c 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0
25. 3 48 Interrupt Mask Level Register 3 49 xiii CHAPTER 4 MCECC Functions Ios IS e 4 1 lor E 4 2 Lotion SIN 4 3 General Ha E Heap Sb os 4 3 e MED IM 4 3 CONTO ere 4 4 l6 4 5 Ar T O 4 5 Reporting DRE HE a UR EUER UE 4 5 Single Bit Error Cycle Type Burst Read or Non Burst Read 4 5 Double Bit Error Cycle Type Burst Read Non Burst Read 4 6 Triple or Greater Bit Error Cycle Type Burst Read or Non Burst Read 4 6 Cycle Type Burst EET 4 6 Single Bit Error Cycle Type Non Burst Write sess 4 6 Double Bit Error Cycle Type Non Burst 4 6 Triple or Greater Bit Error Cycle Type Non Burst Write 4 7 Single Bit Error Cycle Type SiD aues 4 7 Double Bit Error Cycle Type SCAU iis coe etre erret etr kae tren 4 7 Triple or Greater Bit Error Cycle Type Scrub iue intere 4 7 Logging T M 4 8 vi m X ET 4 8 DI m
26. SCC MIEII M 1 61 LAN rin daro 1 61 viii 1 61 1 62 SCSI Parity en RS EARS DI pean 1 62 EHE iet EN TP o E 1 62 SESTETO EN A EE 1 63 CHAPTER2 VMEchip2 2 1 Funenonal ece 2 4 Local Bus to V MEbus Interface tip ias eto 2 4 Local Bus to VMEbus Requester Joco eterno Rb de SEDE tO ARE RAS 2 7 YMEbus to Local Bus Infetface uicta reet teet 2 9 Local Bus ta V MEbus DMA Controller erae 2 10 Na Address Increment DMA Trausters 2 12 DMAC VMEbus 2 13 Tek and WRC HEE TITE S 2 14 SER 2 14 Tek TOE E 2 15 Ware Hoea TIOE rd 2 15 NME DIS eto EA A ert 2 16 VMEbus System CostPoller eisisto EREE Rb MED 2 17 E E E qos 2 17 LACK Daisy bain DIVE a apes 2 17 Tr csi anaes 2 17 RESETE m T M 2 18 Local Bus Interrupter and Interrupt net ie ien 2 18 Global antro and Status iuda e apre 2 20 LER Program
27. Segment ees Size Translation Size Translation Select Value Select Value 6KB FEO 128KB FFFE 64MB 00 256 128 800 512 FFF8 256MB F000 1MB FFFO 512MB E000 2MB FFEO 1GB C000 4MB FFCO 2GB 8000 8MB FF80 4GB 0000 16MB 00 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Address Translation Address Offset Register 2 ADR SIZ FFF4000C 16 bits of 32 BIT 31 s 16 NAME Address Translation Address Offset Register 2 OPER R W RESET 0 PS This register is the address translation address register for the second VMEbus to local bus map decoder It should be programmed to the local bus starting address When the adder is enabled this register is the offset value VMEbus Slave Address Translation Select Register 2 ADR SIZ FFF4000C 16 bits of 32 BIT 15 0 Address Translation Select Register 2 OPER R W RESET 0 PS This register is the address translation select register for the second VMEbus to local bus map decoder The address translation select register value is based on the segment size the difference between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size Segment Segment dde Size Translati
28. The DLPE bit is set in the DMAC Status register address FFF40048 bit 5 If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access http www motorola com computer literature 1 57 Programming Issues DMAC Offboard Error Description MPU Notification Status Comments DMAC LTO Error Description MPU Notification Status Comments Error encountered while the Local Bus side of the DMAC was attempting to go to the VMEbus DMAC interrupt when enabled The DLOB bit is set in the DMAC Status register address FFF40048 bit 4 This is normally caused by a programming error The Local Bus address of the DMAC should not be programmed with a Local Bus address that maps to the VMEbus If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access A Local Bus time out LTO occurred while the DMAC was Local Bus master DMAC interrupt when enabled The DLTO bit is set in the DMAC Status register address FFF40048 bit 3 This indicates the DMAC attempted to access a Local Bus address at which there was no resource If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access 1 58 Computer Group Literature Center Web Site
29. 4 11 IOXH E Dt h o JOPSPLON oxiu voxul s sir 09XL 9r 4 908v LO v a SLY f Lew 89 esiu 09 ua 9 69 5027 1 I 2 i e 4 v Lovzao 90 LOW auvoa guavo NOLLISNVHL jua1avav ZL3WAN v9 gd dLLISWAN 4 9 3INAW T DM AES ev RD ORDINE RUNE ee Sh ew ee esa ae Figure B 9 MVME1X7P Serial Port 4 Configured as DTE Computer Group Literature Center Web Site B 10 Related Documentation C MCG Documents The Motorola Computer Group publications listed below are referenced in this manual You can obtain paper or electronic copies of MCG publications by Contacting your local Motorola sales office Visiting MCG s World Wide Web literature site http www motorola com computer literature Table C 1 Motorola Computer Group Documents Motorola Documents Publication Number MVME167P Single Board Computer Installation and Use V167PA IH MVME 77P Single Board Computer Install
30. 6C IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 70 CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR 74 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 78 AC FAIL ABORT SYS FAIL MST WP ERROR IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IACK DMA SIG 3 SIG 2 7C IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 80 sw7 SW6 SW5 sw4 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 84 IRQ 7 VME IRQ 6 VME IRQ 5 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL T VECTOR BASE VECTOR BASE d S D ABORT GPIOEN REGISTER 0 REGISTER 1 EN kieva il tevet 8C This sheet continues on facing page 1 28 Computer Group Literature Center Web Site Memory Maps CE NU REC LOCAL WD ACCESS BUS TIME OUT PRESCALER TIMER TIMER SELECT CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW M e OVERFLOW ce COUNTER 2 5 5 COUNTER 1 i 1 1 SCALER 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 SW7 swe sw5 SW4 sw3 Swe swt Swo SPARE VME VME IRQ
31. Acknowledge TEA signal is sent to the Local Bus master The time out value is selectable by software for 8 usec 64 usec 256 usec or infinite The Local Bus timer does not operate during VMEbus bound cycles VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer Refer to Chapter 2 VMEchip2 for detailed programming information Functional Description This section highlights few specific features of MVMEIXTP single board computers For a complete functional description of the major blocks of the 1 refer to the Installation and Use manual http www motorola com computer literature 1 17 Programming Issues VMEbus Interface and VMEchip2 The local bus to V MEbus interface and the VMEbus to local bus interface are provided by the VMEchip2 ASIC The VMEchip2 can also provide the VMEbus system controller functions Refer to the VMEchip2 description in Chapter 2 for detailed programming information VMEchip2 General Purpose I O The single board computers both MVME167P and 77 follow the previous MVME177 in their routing of GPIO signals GPIOI controls Flash memory write protection GPIO3 selects between shared EPROM Flash mode or Flash only mode GPIO2 controls whether the upper or lower Flash addresses are used in shared EPROM Flash mode GPIOO s function as 12V power status signal is unchanged Petra VMEchip2 Redunda
32. CPU040 This bit should remain set to indicate that the MPU is from the M68000 family When the bit is set EIPL lt 2 0 gt are driven as outputs which carry the priority encoded interrupt request from the PCCchip2 interrupt sources When the bit is cleared EIPL lt 2 0 gt are not driven as outputs but are inputs only Download ROM at 0 not applicable to MVME1X7P This bit should remain cleared so that DROM appears only in its normal address range When DRO is set DROM also appears at 00000000 through 0001FFFF DRO is cleared by power up or local reset but if no other device responds within a certain amount of time to the first memory access after the reset then the PCCchip2 sets DRO This causes the DROM to respond to the memory access and all memory accesses thereafter until software clears DRO 1 if no other device responds to the first memory access after Power up or Local Reset Otherwise V 0 The Interrupt Vector Base Register is located at FFF42003 It is an 8 bit read write register that is used to supply the vector to the MPU during an interrupt acknowledge cycle for the two internal tick timers LAN interrupt LAN BERR interrupt SCSI interrupt GPIO interrupt and parallel port interrupts Only the most significant four bits are used The least significant four bits encode the interrupt source during the acknowledge cycle The exception to this is that after reset occurs the interrupt vector passed is 0F
33. DMA DMA DMA DMA DMA DMA TBL SNP MODE INC INC WRT 016 064 BLK AM AM AM AM AM AM INT 18 BLK 5 4 3 2 1 0 LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER cem MPU MPU MPU MPU MPU DMA DMA DMA DMA DMA DMA DMA CLR LBE LPE LOB LTO LBE LPE LOB LTO TBL VME DONE INTERRUPT COUNT STAT ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR 1360 9403 This sheet begins on facing page http www motorola com computer literature 1 27 Programming Issues Table 1 5 VMEchip2 Memory Map Sheet 2 of 3 VMEchip2 LCSR Base Address FFF40000 OFFSET 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 ARB VME DMA DMA BGTO 4C EN TIME OFF TIME ON 50 TICK TIMER 1 54 TICK TIMER 1 58 TICK TIMER 2 5C TICK TIMER 2 SCON sys BRD PURS CLR BRD RST sys WD WD WD TO WD WD WD 60 FAIL FAIL STAT PURS FAIL SW RST CLR CLR TO BF SRST RST STAT STAT OUT EN TO CNT STAT EN LRST EN EN 64 PRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AC AB SYS MWP PE TIC2 VME DMA 963 962 961 5160 LMO 68 FAIL IRQ FAIL BERR IRQ IRQ IRQ IRQ IACK IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN
34. Ei anena 4 27 Emor Address Bits 4 28 Emor Address Bie pr RETI ee Rage EN Mad dela pd pU 4 28 Emor Address Eiis L3 4 29 Error PO Brie Tea esser URP M Udo dE Vo uicta a att oe ea Sls 4 29 Error Syndrome 4 30 e Em 4 30 S 4 32 SDRAM Configuration Besser i err aces pnt beer o Re 4 33 DLL T 4 34 syndrome RICO OIG 4 36 APPENDIX A Summary of Changes oe cose conse strap ares Sane EE stan c A 1 APPENDIXB Printer and Serial Port Connections Erici DOE Er ES B 1 eap osi Bod ee erate ere ee cere ea B 1 APPENDIX C Related Documentation Das C 1 Maputactiiters DOMMENS ipe ap i irem EM DON Moi ap E C 2 d slg P up em e E C 3 xvi List of Figures M VMBISGTE Block 1 5 Figure 1 2 Block 1 6 Figure 1 3 MVME177 Flash and EPROM Memory Mapping Schemes 1 10 Figure 2 1 VMBchip2 Block Dia State 5er tret prit tige 2 5 Figure 3 L POX chap
35. OPER C R R W R W R W R W RESET 0 PS 0 OP OPSL OPSL 1 PSL OPSL WDEN WDRSE WDS L WDBFE WDTO WDCC When this bit is high the watchdog timer is enabled When this bit is low the watchdog timer is not enabled When this bit is high and a watchdog time out occurs a SYSRESET or LRESET is generated The WDS L bit in this register selects the reset When this bit is low a watchdog time out does not cause a reset When this bit is high and the watchdog timer has timed out and the watchdog reset enable WDRSE bit in this register is high a SYSRESET signal is generated on the VMEbus which in turn causes LRESET to be asserted When this bit is low and the watchdog timer has timed out and the watchdog reset enable WDRSE bit in this register is high an LRESET signal is generated on the local bus When this bit is high and the watchdog timer has timed out the VMEchip2 asserts the BRDFAIL signal pin When this bit is low the watchdog timer does not contribute to the BRDFAIL signal on the VMEchip2 When this status bit is high a watchdog time out has occurred When this status bit is low a watchdog time out has not occurred This bit is cleared by writing a 1 to the WDCS bit in this register When this bit is set high the watchdog counter is reset The counter must be reset within the time out period or a watchdog time out occurs http www motorola com computer lite
36. The following sections provide an overview of the functions provided by the Petra MCECC sector For a detailed programming model for the Petra MCECC control and status registers refer to the Programming Model section General Description The Petra MCECC sector is a single chip solution for memory control functions The memory architecture is a single bank of SDRAM 32 bits wide plus seven check bits The MCECC sector provides all the functions required to implement a memory system These include programmable map decoding memory control refresh and a memory scrubber The scrubber when enabled periodically scans memory for errors If the scrubber finds a single bit error in the memory array it corrects the error This prevents soft single bit errors from becoming double bit errors Performance The Petra MCECC sector maintains tags for each internal bank of SDRAM Each bank may be in an active or idle state SDRAM access time is a function of the state of the bank of memory being addressed If the bank addressed is active performance is additionally a function of the page of memory being referenced If the page referenced is open access time is the shortest possible Maximum access time will occur when the page referenced is not open since the open page must be first closed and the desired page then opened Page sizes are determined by the configuration of the SDRAM device Sizes range from 256 to 1024 memory locations per page Th
37. VMEchip2 ASIC 2 10 arbiter time out timer VMEbus 2 64 VMEbus 2 17 arbitration modes VMEbus 2 17 ASIC replaced by Petra 1 2 attribute register VMEchip2 2 28 snoop bits 2 28 auto vector mode PCCchip2 ASIC 3 7 IN 1 xXmoz Index B Back Off signal PCCchip2 ASIC 3 5 backward compatibility 1 2 base address VMEchip2 LCSR 2 20 battery backup 1 10 BBRAM configuration area memory map 1 42 interface PCCchip2 3 3 memory map 1 41 speed control 3 15 BBRAM battery backed up RAM 1 12 restoring lost Ethernet address 1 15 BBSY signal VMEbus 2 98 BERR signal VMEbus 2 17 BGIN filters VMEbus 2 98 binary number symbol for xxiii block D64 access cycles VMEbus 2 33 2 36 block access cycles VMEbus 2 33 2 36 block diagrams MVMEIX7P board 1 4 PCCchip2 ASIC 3 2 VMEchip2 ASIC 2 5 block transfer cycles VMEchip2 DMAC 2 11 mode 2 9 modes DMAC 2 59 board address GCSR 2 48 failure signal VMEchip2 ASIC 2 70 ID 1 44 serial number 1 44 speed 1 46 status control register VMEchip2 2 106 Board Control register VMEchip2 2 101 BRDFAIL signal pin VMEchip2 ASIC 2 70 2 71 broadcast interrupt function VMEchip2 timers 2 15 broadcast mode VMEbus 2 16 BSY signal and arbitration timer 2 17 burst read cycle type 4 5 burst write cycle type 4 6 bus error 3 4 processing 1 55 sources 1 54 status SCSI 3 37 bus map decoder LCSR 2 20 bus sizing VMEchip2 ASIC 2 6 bus timer local 1 17 bus timer enable disable VME
38. a DMA transfer to a 16 bit FIFO would start on a 16 bit boundary and would have an even number of 16 bit transfers If the starting address is not aligned or the byte count is odd the DMA controller will increment the lower address lines This is required because the lower order address lines are used to define the size of the transfer and the byte lanes The VMEbus uses VA lt 2 1 gt LWORD and DS lt 1 0 gt to define the transfer size and byte lanes If the VMEbus port size is D32 then VA 1 LWORD and DS lt 1 0 gt are used to define the transfer size and byte lanes During D16 transfers VMEbus address line VA lt 1 gt toggles If the VMEbus port size is D64 then VA lt 2 1 gt LWORD and 05 lt 1 0 gt are used to define the transfer size and byte lanes Local bus address LA lt 3 0 gt and SIZ lt 1 0 gt are used to define the transfer size and byte lanes on local bus During local bus transfers LA 3 2 count The DMA controller internally increments the VMEbus address counter and if the transfer mode is BLT the DMA controller generates a new address strobe AS when a block boundary is crossed DMAC VMEbus Requester The chip contains an independent VMEbus requester associated with the DMA Controller This allows flexibility in instituting different bus tenure policies for the single transfer oriented master and the block transfer oriented DMA controller The DMAC requester provides all the signals necessary to
39. interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a rising edge high level of the BUSY pin When this bit is high interrupt is activated by a falling edge low level of the BUSY pin Note that if this bitis changed while the E L bit is set or is being set a BUSY interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the bit http www motorola com computer literature 3 43 PCCchip2 Printer Input Status Register ADR SIZ FFF42036 8 bits BIT 15 14 13 12 11 10 9 8 NAME PINT ACK FLT SEL PE BSY OPER R R R R R R R R RESET X 0 0 X X X X X BSY This bit reflects the state of the Printer Busy input pin It is 1 when BSY is high and 0 when BSY is low PE This bit reflects the state of the Printer Paper Error input pin It is 1 when PE is high and 0 when PE is low SEL This bit reflects the state of the Printer Select input pin It is 1 when SELECT is high and 0 when SELECT is low FLT This bit reflects the state of the Printer Fault input pin It is 1 when FAULT is low and 0 when FAULT is high ACK This bit reflects the state of the Printer Acknowledge input pin Itis 1 when ACK is low and 0 when is high PINT Printer Interrupt Status When this bit is high an interrupt is being generated at the level programmed in one or more of the Printer Interrupt Con
40. remains asserted for at least 200 msec as required by the VMEbus specification Similarly the chip provides an input signal and a control bit to initiate a local reset operation The local reset driver is enabled even when the chip is not the system controller A local reset may be generated by the RESET switch a power up reset a watch dog time out a VMEbus signal or a control bit in the GCSR Local Bus Interrupter and Interrupt Handler There are 31 interrupt sources in the VMEchip2 ASIC VMEbus ACFAIL interrupter Tick timer 2 1 ABORT switch DMAC done VMEbus SYSFAIL interrupter GCSR SIG3 0 Write post bus error GCSR location monitor 1 0 External input Software interrupts 7 0 VMEbus IRQI edge sensitive interrupter VMEbus 7 1 interrupts VMEchip2 VMEbus interrupter acknowledge 2 18 Computer Group Literature Center Web Site Functional Blocks Each of the 31 interrupts can be enabled to generate a local bus interrupt at any level For example VMEbus 5 be programmed to generate level 2 local bus interrupt The VMEbus AC fail interrupter is an edge sensitive interrupter connected to the VMEbus ACFAIL signal line This interrupter is filtered to remove the ACFAIL glitch which is related to the BBSY glitch The SYS fail interrupter is an edge sensitive interrupter connected to the VMEbus SYSFAIL signal line The write post bus error interr
41. switches ABORT and RESET 1 4 syndrome decoding 4 36 SYSFAIL interrupter 2 19 SYSFAIL signal line 2 19 2 70 2 96 SYSRESET function VMEchip2 ASIC 2 15 SYSRESET signal 1 17 2 18 2 71 system controller function VMEchip2 ASIC 2 70 enable disable 2 17 systems serial ID 1 45 http www motorola com computer literature IN 11 lt moz xXmoz Index T TEA source 3 34 Tick Timer 1 Compare register 3 18 Tick Timer 1 Control register PCCchip2 ASIC 3 23 Tick Timer 1 counter PCCchip2 ASIC 3 19 Tick Timer 1 Interrupt Control register PCCchip2 ASIC 3 26 Tick Timer 2 Compare register PCCchip2 ASIC 3 19 Tick Timer 2 Control register PCCchip2 ASIC 3 22 Tick Timer 2 counter PCCchip2 ASIC 3 20 Tick Timer 2 Interrupt Control register PCCchip2 ASIC 3 25 tick timer interrupters 2 19 tick timers 1 3 1 16 PCCchip2 ASIC 3 9 3 18 VMEchip2 2 14 time of day clock 1 3 memory map 1 43 timeout local bus 1 17 1 54 VMEbus 1 54 timeout period VMEbus 2 17 watchdog 2 66 timer registers VMEchip2 ASIC Board Control register 2 70 DMAC time on off timers 2 65 Prescaler Control register 2 67 Prescaler counter 2 73 Tick Timer 1 Compare register 2 68 Tick Timer 1 Control register 2 73 Tick Timer 1 counter 2 68 Tick Timer 2 Compare register 2 69 Tick Timer 2 Control register 2 72 Tick Timer 2 counter 2 69 VME Access Local Bus and Watchdog Time Out Control register 2 66 VMEbus Arbiter Time Out Control register 2
42. 0 0 0 0 0 0 10 DUMMY 1 0 0 0 0 0 0 0 0 14 BASE BAD31 BAD30 BAD2 BAD2 BAD27 BAD26 BAD25 BAD24 ADDRESS 9 8 18 DRAM BAD23 BAD22 RWB5 SWAI RWB3 NCEIE NCEB RAMEN CONTROL T N EN 1C BCLK BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCKO FREQUENCY 20 DATA 0 0 DERC ZFILL RWCKB 0 0 0 CONTROL 24 SCRUB RACO RADA HITDI SCRB SCRBEN 0 SBEIE IDIS CONTROL DE TA S N 28 SCRUB SBPDI SBPDI SBPDI SBPD SBPDII SBPDI SBPD9 SBPD8 PERIOD 5 4 3 12 0 2C SCRUB SBPD7 SBPD6 SBPD5 SBPD SBPD3 SBPD2 SBPDI SBPDO PERIOD 4 30 CHIP CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPSO PRESCALE 34 SCRUB TIME SRDIS 0 STON STON STONO STOFF STOFF STOFFO ON OFF 2 1 2 1 38 SCRUB 0 0 SPS21 SPS20 SPS19 SPS18 SPS17 SPS16 PRESCALE 3C SCRUB 5 515 5 514 5 513 5 512 5 511 5 510 5 59 SPS8 PRESCALE 40 SCRUB SPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPS1 SPSO PRESCALE 44 SCRUB STI5 ST14 ST3 ST12 ST11 ST10 ST9 ST8 TIMER 1 34 Computer Group Literature Center Web Site Memory Maps Table 1 8 MCECC Internal Register Memory Map Continued MCECC Base Address FFF43000 1st 43100 2nd Register Register Register Bit Names Offset Name D31 D30 p29 D28 D27 D26 D25 D24 48 SCRUB ST7 ST6 STS STA ST3 ST2 STI STO TIMER 4C SCRUB 0 0 0 0 0 SAC26 SAC25 SAC24 ADDR CNTR 50 SCRUB SAC23 SAC22 SAC21 SAC20 5 19 8 SACIT7 SAC
43. 0 0 0 SDCFG2 SDCFGI SDCGFO OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS VPLS VPLS V PLS V PLS V PLS SDCFG2 SDCFG0 Define the physical SDRAM memory population on the printed circuit board SDCFG2 SDCFG1 SDCFG0 DRAM Array Size 0 0 0 SDRAM device is 64MBit x 16 data with one bank composed of 3 devices 0 0 1 SDRAM device is 64MBit x 8 data with one bank composed of 5 devices 0 1 0 SDRAM device is 64MBit x 8 data with two banks composed of 5 devices each 0 1 1 SDRAM device is 64MBit x 8 data with four banks composed of 5 devices each 1 0 0 SDRAM device is 128MBit x 8 data with one bank composed of 5 devices 1 0 1 SDRAM device is 128MBit x 8 data with two banks composed of 5 devices each 1 1 0 reserved 1 1 1 reserved http www motorola com computer literature 4 33 MCECC Functions Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational The MCECC does not perform this initialization automatically but depends on software to perform enough dummy accesses to DRAM to meet the requirement The number of cycles required is fewer than 10 If there are multiple blocks of DRAM software has to perform at least 10 accesses to each block The MCECC pair provides a fast zero fill capability The sequence shown below performs such a zero fill It zeroes all of the DRAM
44. 103 ID Register iuc etat ertt rr RE 2 104 YMEchip2 LM ASIO Register 2 104 VMEchip2 Board Status Control Register 2 106 General Purpose Register O 2 107 General Purpose Register erts 2 107 General Purpose 2 107 General Purpose Reglstet 3 eaa ep res ray HRS PNE HERE FERE 2 108 General Purpose Register 2 108 General Purpose 2 108 3 PCCchip2 DEI 3 1 Maor PORES EE 3 1 3 2 gon WS Cea NCR ET 3 2 BBRAM Ink ape 3 3 52590 LAN Controller 3 3 MPU Part and MPU Channel oec coniicere 3 3 MC68040 Bus Master Support for 82596CA 3 4 LANC DS A 3 4 3 5 Sa 20 SC SI Controller 3 6 Paralel Port ii gr 3 6 Pampos VO 3 7 uxo T E T
45. 2 016 WP MASTER AM 1 EN EN EN EN 102 102 102 102 101 101 101 101 ROM ROM BANK B ROM BANK A EN WP S U P D EN D16 WP S U SIZE SPEED SPEED EN EN EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARB MAST MAST MST MST MASTER DMA DMA DMA DMA DM DMA ROBN DHB DWB FAIR VMEBUS HALT EN TBL FAIR RELM VMEBUS DMA DMA LB DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA TBL SNP MODE INC INC WRT 016 064 BLK AM AM AM AM AM AM INT VME LB BLK 5 4 3 2 1 0 LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER DIA TABLE MPU MPU MPU MPU MPU DMA DMA DMA DMA DMA DMA DMA CLR LBE LPE LOB LTO LBE LPE LOB LTO TBL VME DONE INTERRUPT COUNT stat ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR 1360 9403 This sheet begins on facing page http www motorola com computer literature 2 23 VMEchip2 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 2 of 2 VMEchip2 LCSR Base Address FFF40000 OFFSET 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 ARB VME DMA DMA BGTO 4C EN TIME OFF TIME ON 50 TICK TIMER 1 54 TICK TIMER 1 58 TICK TIMER 2 5C TICK TIMER 2 SCON sys BRD PURS CLR BRD RST sys WD WD WD TO WD WD WD 60 FAIL FAIL STAT PURS FAIL SW RST CLR CLR TO BF SRST RST STAT STAT OUT EN TO CNT STAT EN LRST EN EN 64 PRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
46. 4 2 6 2 9 master interrupt enable MIEN bit 2 74 2 96 master interrupt enable PCCchip2 ASIC 3 15 MC68040 bus master support for 82596C 3 4 MPU 1 7 MC68060 MPU 1 7 MC680x0 indivisible RMW memory accesses 1 52 6 access 3 10 normal access 3 10 MCECC chip Memory Controller ASIC 1 3 MCECC internal register memory map 1 34 MCECC sector arbitration process 4 9 Base Address register 4 15 BCLK Frequency register 4 16 chip defaults 4 9 Chip Prescaler counter 4 21 Data Control register 4 17 Defaults register 1 4 30 http www motorola com computer literature IN 7 lt moz xXmoz Index Defaults register 2 4 32 DRAM Control register 4 15 Error Address bits 23 16 4 28 Error Address bits 31 24 4 28 Error Address bits 7 4 4 29 Error Address Bits 15 8 4 29 Error Logger register 4 27 Error Syndrome register 4 30 features 4 1 initialization 4 34 internal register memory map 4 11 Memory Configuration register 4 14 refresh control 4 8 Scrub Address counter bits 15 8 4 26 Scrub Address counter bits 23 16 4 26 Scrub Address counter bits 26 24 4 25 Scrub Address counter bits 7 4 4 26 Scrub Control register 4 19 Scrub Period register bits 15 8 4 20 Scrub Period Register bits 7 0 4 20 Scrub Prescaler counter Bits 15 8 4 23 Scrub Prescaler counter bits 21 16 4 23 Scrub Prescaler counter Bits 7 0 4 24 Scrub Time On Time Off register 4 21 Scrub Timer counter Bits 15 8 4 24 Scrub Timer co
47. 41 offboard error 1 62 parity error 1 62 terminator configuration 1 16 SDRAM implementation 1 2 4 1 4 5 map decoder 1 11 segment size address translation 2 31 segment size translating 2 30 SERCLK driver 2 17 serial interface description 1 13 port connection diagrams B 1 short I O area VMEchip2 ASIC 2 6 short I O map decoder VMEbus 2 50 short I O memory map 1 46 short I O segment VMEbus 2 50 short I O space VMEbus 2 37 2 100 signal interrupts SIGO SIG3 VMEchip2 ASIC 2 100 Single SGL arbitration mode VMEbus 2 17 single bit error 4 5 size VMEbus segment 2 30 2 31 slave map decoders VMEbus 2 26 snoop control 3 4 SCC receive 3 30 snoop control bits 2 53 snoop control register 2 32 snoop control LANC bus error 3 36 snoop function enabling 2 28 2 32 2 35 snoop signal lines DMAC 2 58 snooping definition of 1 49 2 10 software 7 0 interrupters VMEbus 2 19 software interrupts 1 3 specifications applicable industry standards 1 4 MCECC sector 4 4 related C 3 SRAM static RAM 1 10 specifications 1 3 standard access cycles VMEbus 2 33 2 36 starting address register V MEbus slave 2 38 starting address register slave map decoder 2 27 static RAM SRAM 1 10 status LEDs 1 4 status register DMAC 2 63 status register MPU DMAC 2 62 strobe timing 3 45 strobe printer 3 45 supervisor address modifier code VMEbus 2 50 Supervisor Stack pointer on MVME177 1 53 supervisory access cycles VMEbus 2 34 2 37
48. ADDRESS 2 8 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER SNP WP SUP USR A32 A24 e BLK PRGM DATA 2 s 2 2 2 T 14 MASTER ENDING ADDRESS 1 18 MASTER ENDING ADDRESS 2 1C MASTER ENDING ADDRESS 3 20 MASTER ENDING ADDRESS 4 24 MASTER ADDRESS TRANSLATION ADDRESS 4 MAST MAST MAST MAST 28 016 WP MASTER AM 4 016 WP MASTER AM 3 EN EN EN EN GCSR MAST MAST MAST MAST 2C GCSR GROUP SELECT BOARD SELECT a 2 a 31 30 29 25 24 23 22 21 20 19 18 17 16 WAIT ROM DMA TB SRAM 30 RMW ZERO SNP MODE SPEED 34 38 DMA CONTROLLER 3C DMA CONTROLLER 40 DMA CONTROLLER 44 DMA CONTROLLER TICK TICK CLR IRQ VMEBUS 48 EE ME INTERRUPT VMEBUS INTERRUPT VECTOR LEVEL This sheet continues on facing page 2 22 Computer Group Literature Center Web Site LCSR Programming Model 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER SNP WP SUP usr 2 aza DATA 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 F 6 5 4 3 2 1 0 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST MAST 016 WP MASTER AM
49. Applicable Industry Standards These boards conform to the requirements of the following documents VMEbus Specification IEEE 1014 87 EIA 232 D Serial Interface Specification EIA SCSI Specification ANSI Block Diagram Figure 1 1 and Figure 1 2 are general block diagrams of the MVME167P and MVME177P single board computers 1 4 Computer Group Literature Center Web Site Introduction VMEchip 2 VMEbus Interface 128KB SRAM Battery Option i82696CA Ethernet Controller 25 33MHZ MC68040 MPU 53C710 SCSI Compressor CD2401 Centronics Quad Serial Compatible Controller Parallel Port PCCCHIP 2 M48T58 Battery Backed 8KB RAM Clock Mezzanine Connectors 16 64MB ECC SDRAM Memory Array Up to 128MB ECC DRAM 2816 0800 iagram Figure 1 1 MVME167P Block D 1 5 http www motorola com computer literature Programming Issues VMEchip 2 EPROM i82696CA 53C710 CD2401 Centronics VMEbus 2 44 pin Ethernet SCSI Quad Serial Compatible Interface PLCC Controller Compressor Controller raaa vO PCCCHIP 2 128KB 50 60MHZ Mezzanine M48T58 SRAM 4MB FLASH MC68040 Connectors Battery Backed Battery Option MPU 8KB RAM Clock 16 128MB ECC SDRAM Up to 128MB ECC DRAM Memory Array 2816 0800 iagram Figure 1 2 MVME177P Block D Computer Group Literature Center Web Sit
50. Block Dia atai 3 2 Figure B 1 MVMEIXT7P Printer Port with MVMETI2M B 2 Figure B 2 MVMEIXT7P Serial Port 1 Configured as DCE B 3 Figure B 3 MVMEIXT7P Serial Port 2 Configured as DCE B 4 Figure B 4 MVMEIXT7P Serial Port 3 Configured as DCE B 5 Figure B 5 MVMEIXT7P Serial Port 4 Configured as DCE B 6 Figure B 6 MVMEIXT7P Serial Port 1 Configured as DTE B 7 Figure 7 MVMEIXT7P Serial Port 2 Configured as DTE B 8 Figure B 8 MVMEIXT7P Serial Port 3 Configured as DTE B 9 Figure B 9 MVMEIXT7P Serial Port 4 Configured as DTE B 10 xvii xviii List of Tables Table 1 1 MYMELXSTP Features seni 1 3 Table 1 2 Functions Duplicated in VMEchip2 and Petra ASICS 1 19 Table 1 3 Local Bus Memor 1 21 Table 1 4 Local UO Devices Memory oce rnt rentre verre cours 1 22 Table 1 5 VMEchip2 Memory Map Sheet 1 043 22 2 1 26 Table 1 6 Printer Memory Map 1 31 Table 1 7 PCCchipz Memory 1 32 Table 1 8 MCECC Internal Register Memory 1 34 Table 1 9 Cirrus Logic
51. CD2401 Serial Port Memory Map 1 36 Table 1 10 82596CA Ethernet LAN Memory eter ttes 1 40 Table 1 10 535 210 SC SE Memory Eee p 1 41 Table 1 12 M48T58 BBRAM TOD Clock Memory 1 42 Table 1 13 BBRAM Configuration Area Memory Map esee 1 42 Table t 14 TOD Clock obse cordi eed ah de 1 43 Table 1 15 Single Cycle Insteuctions uiis nre 1 52 Table 2 1 Features of the VMEBcbip2 ASIC ainen 2 1 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 2 22 Table 2 3 DMAC Command Packet Format eo 2 53 Table 2 4 Local Bus luterrupter Summary ges 2 75 Table 2 5 VMEchip2 Memory Map 2 103 Table 3 1 PCCcInp2 Deyices Memory Map i eios etin aeo 3 10 Table 3 2 PCCchip2 Memory Map Control and Status Registers 3 12 Table4 1 MCECC Punctiong on the Petra ASIC iiec ret tiere border 4 2 Table 4 2 Memory Systeme Lyole Timing acoso ep 4 4 Table 4 3 MCECC Sector Internal Register Memory Map 4 11 Table 4 4 Syndrome Bit Encoding iui esce er etse 4 36 Table 4 5 I
52. Compare Register OPER R W RESET OP The tick timer 2 counter is compared to this register When they are equal an interrupt is sent to the local bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to determine the compare register value for a specific period compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 2 Counter ADR SIZ FFF4005C 32 bits BIT 31 0 Tick timer 2 Counter OPER R W RESET OP This is the tick timer 2 counter When enabled it increments every microsecond Software may read or write the counter at any time http www motorola com computer literature 2 69 VMEchip2 Board Control Register ADR SIZ BIT 31 FFF40060 8 bits 7 used of 32 29 28 27 26 25 24 NAME SCON SFFL BRFLI PURS CPURS BDFLO RSWE OPER R R R C R W R W RESET X 1 PSL 1P OPS 1 PSL 1P RSWE BDFLO CPURS PURS BRFLI SFFL SCON The RESET switch enable bit is used with the no VM
53. DISMST NOELBBSY DISBSYT ENINT DISBGN OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL 0 PS 0 PS 0 PS 0 PS 0 PS DISBGN When this bit is high the VMEbus BGIN filters are disabled When this bit is low the VMEbus BGIN filters are enabled This bit should not be set ENINT When this bit is high the local bus interrupt filters are enabled When this bit is low the local bus in terrupt filters are disabled This bit should not be set DISBSYT When this bit is low the minimum VMEbus BBS Y time when the local bus master has been retried off the local bus is 32 local bus clocks When this bit is high the minimum VMEbus BBSY time when the local bus master has been retried off the local bus is 3 local bus clocks When a local bus master attempts to access the VMEbus and a VMEbus master attempts to access the local bus a deadlock is created The VMEchip2 detects this condition and requests the local bus master to give up the local bus and retry the cycle This allows the VMEbus master to complete the cycle to the local bus If the VMEchip2 receives VMEbus mastership the local master has not returned from the retry and this bit is high VMEchip2 drives VMEbus BBSY for the minimum time about 90 ns and then releases the VMEbus If the local master does not return from the retry within this 90 ns window the board loses its turn on the VMEbus If the VMEchip2 receives VMEbus mastership the local master has not returne
54. DMAC completes its cycle Tick and Watchdog Timers Prescaler The VMEchip2 has two 32 bit tick timers and a watchdog timer The tick timers run on a IMHz clock which is derived from the local bus clock by the prescaler The prescaler is used to derive the various clocks required by the tick timers VME access timers reset timer bus arbitration timer local bus timer and VMEbus timer The prescaler divides the local bus clock to produce the constant frequency clocks required Software is required to load the appropriate constant depending upon the local bus clock following reset to ensure proper operation of the prescaler 2 14 Computer Group Literature Center Web Site Functional Blocks Tick Timers The VMEchip2 includes two general purpose tick timers These timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing The timers have a resolution of 1 us When free running they roll over every 71 6 minutes Each tick timer has a 32 bit counter a 32 bit compare register a 4 bit overflow register an enable bit an overflow clear bit and a clear on compare enable bit The counter is readable and writable at any time When enabled in free run mode it increments every 15 When the counter is enabled clear on compare mode it increments every 1s until the counter value matches the value in the compare register When a match occurs the counter is cleare
55. FLASH FLASH FLASH MEMORY TOP 2MB BOTTOM 4MB 2MB p 4 000 pe FFA00000 1MB EPROM 1MB EPROM DUPLICATED DUPLICATED READABLE READABLE NOT WRITABLE NOT WRITABLE FF900000 1MB EPROM 1MB EPROM BUG FF800000 NO EPROM IN MAP 1534 9408 Figure 1 3 MVME177 Flash and EPROM Memory Mapping Schemes SRAM The MVME167P and MVME177P single board computers include 128KB of 32 bit wide 100ns static RAM SRAM that supports 8 16 and 32 bit wide accesses The SRAM allows the debugger to operate and limited diagnostics to execute without using the on board SDRAM or mezzanines The SRAM is under the control of the VMEchip2 ASIC and the access time is programmable Refer to Chapter 2 VMEchip2 for more detail The MVME177P provides for SRAM battery backup The battery backup function is supplied by a Dallas DS1210S nonvolatile controller chip and Panasonic 2032 or equivalent battery Computer Group Literature Center Web Site Programming Interfaces The MVME177P implements primary and secondary backup sources You can select from 5V standby power the onboard battery or both The jumpers and configuration switches for the MVME167P and MVME177P are described in Chapter 1 of the Installation and Use manual for the respective boards Onboard SDRAM MVME167P boards are built with 16MB 64MB synchronous DRAM SDRAM MVME177P boards are built with 16MB 128MB SDRAM The MVME1X7P may have the SDRAM confi
56. LM3 LM2 LMI LMO SIG3 SIG2 SIGI SIGO OPER R R R R S R S R S R S R RESET 1 PS 1 PS 1 PS 1 PS 0 PS 0 PS 0 PS 0 PS This register is the VMEchip2 location monitor register and the interrupt register SIGO The SIGO bit is set when a VMEbus master writes a 1 to it When the SIGO bit is set an interrupt is sent to the local bus interrupter The SIGO bit is cleared when the local processor writes a 1 to the SIGO bit in this register or the CSIGO bit in the local interrupt clear register SIG1 The SIGI bit is set when a VMEbus master writes a 1 to it When the SIGI bit is set an interrupt is sent to the local bus interrupter The SIGI bit is cleared when the local processor writes a 1 to the SIGI bit in this register or the CSIGI bit in the local interrupt clear register SIG2 The SIG2 bit is set when a VMEbus master writes a 1 to it When the SIG2 bit is set an interrupt is sent to the local bus interrupter The SIG2 bit is cleared when the local processor writes a 1 to the SIG2 bit in this register or the CSIG2 bit in the local interrupt clear register 2 104 Computer Group Literature Center Web Site GCSR Programming Model SIG3 0 LM1 LM2 LM3 The SIG3 bit is set when a VMEbus master writes a 1 to it When the SIG3 bit is set an interrupt is sent to the local bus interrupter The SIG3 bit is cleared when the local processor writes a 1 to the SIG3 bit in this register or the CSIG
57. Local I O Devices portion of the local bus Main Memory Map Table 1 4 Local I O Devices Memory Address Range Devices Accessed Port Size Size Notes FFFO0000 FFF3FFFF Reserved 256KB 5 FFF40000 FFF400FF VMEchip2 LCSR D32 256B 1 4 FFF40100 FFF401FF VMEchip2 GCSR D32 D8 256B 1 4 FFF40200 FFF40FFF Reserved 3 5 5 7 FFF41000 FFF41FFF Reserved 4 5 FFF42000 FFF42FFF PCCchip2 032 08 4 1 FFF43000 FFF430FF Petra MCECC 1 D8 256B 1 Computer Group Literature Center Web Site Memory Maps Table 1 4 Local I O Devices Memory Map Continued Address Range Devices Accessed Port Size Size Notes FFF43 100 FFF431FF Petra MCECC 2 D8 256B 1 FFF43200 FFF43FFF Petra MCECCs repeated 3 5 1 7 FFF44000 FFF44FFF Reserved 4KB 5 FFF45000 FFF451FF CD2401 Serial Comm Cont D16 D8 512B 1 9 FFF45200 FFF45DFF Reserved 3KB 7 9 FFF45E00 FFF45FFF Reserved 512B 1 9 FFF46000 FFF46FFF 82596CA LAN D32 4KB 1 8 FFF47000 FFF47FFF 53C710 SCSD D32 D8 4KB 1 FFF48000 FFF4FFFF Reserved 32KB 5 FFF50000 FFF6FFFF Reserved 128KB 5 FFF70000 FFF76FFF Reserved 28 6 SFFF77000 SFFF77FFF Reserved 4KB 2 FFF78000 FFF7EFFF Reserved 28KB 6 FFF7F000 FFF7FFFF Reserved 4KB 2 FFF80000 FFF9FFF
58. Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its Warning components To prevent serious injury or death from dangerous voltages use extreme Flammability All Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference EMI if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Caution Attention Vorsicht Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d
59. NAME SW7 SW6 SW5 SWA SW3 SW2 SWI SWO OPER R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter status register When an interrupt status bitis high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are Swo SWI1 SW2 SW3 Sw4 SWS SW6 SW7 Software 0 interrupt Software 1 interrupt Software 2 interrupt Software 3 interrupt Software 4 interrupt Software 5 interrupt Software 6 interrupt Software 7 interrupt http www motorola com computer literature 2 79 VMEchip2 Local Bus Interrupter Status Register bits 0 7 ADR SIZ FFF40068 8 bits of 32 BIT 7 6 5 4 3 2 1 0 SPARE VME7 VME6 5 VME4 VME3 VMEI OPER R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter status register When an interrupt status bit is high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are 1 VMEbus IRQI Interrupt VME2 VMEbus IRQ Interrupt VME3 VMEbus IRQ3 Interrupt VME4 VMEbus IRQ4 Interrupt VMES VMEbus IRQS Interrupt VME6 VMEbus IRQ6 Interrupt VME7 VMEbus IRQ7 Interrupt SPARE Not used 2
60. Programmable map decoders for the master and slave interfaces A VMEbus to from local bus DMA controller A VMEbus to from local bus non DMA programmed access interface A VMEbus interrupter a VMEbus system controller a VMEbus interrupt handler and a VMEbus requester Processor to V MEbus transfers can be D8 D16 or D32 VMEchip2 DMA transfers to the VMEbus however can be D16 D32 D16 BLT D32 BLT or D64 MBLT Refer to Chapter 2 VMEchip2 for detailed programming information Interfaces The MVME167P and MVME177P single board computers provide onboard I O for many system applications The I O functions include serial ports parallel printer port Ethernet transceiver interface and SCSI mass storage interface Computer Group Literature Center Web Site Programming Interfaces Serial Port Interface The CD2401 serial controller chip SCC is used to implement the four serial ports The serial ports support the standard baud rates 110 to 38 4K baud The four serial ports differ in function because of the limited number of pins on the P2 I O connector Serial port 1 is a minimum function asynchronous port It uses RXD CTS TXD and RTS Serial ports 2 and 3 are full function asynchronous ports They use RXD CTS DCD TXD RTS and DTR Serial port 4 is a full function asynchronous or synchronous port It can operate at synchronous bit rates up to 64 k bits per second It uses RXD CT
61. R W B Receive Buffer Address Lower BRBADRL 46 W R W B Receive Buffer Address Upper BRBADRU 44 W R W A Receive Buffer Byte Count ARBCNT 4A W R W Computer Group Literature Center Web Site Memory Maps Table 1 9 Cirrus Logic CD2401 Serial Port Memory Map Continued Base Address FFF45000 Register Description Register Offsets Size Access Name B Receive Buffer Byte Count BRBCNT 48 W R W A Receive Buffer Status ARBSTS 4 B R W B Receive Buffer Status BRBSTS 4E B R W Receive Current Buffer Address Lower RCBADRL 3E W R Receive Current Buffer Address Upper RCBADRU 3C W R DMA Transmit Registers A Transmit Buffer Address Lower ATBADRL 52 W R W A Transmit Buffer Address Upper ATBADRU 50 W R W B Transmit Buffer Address Lower BTBADRL 56 W R W B Transmit Buffer Address Upper BTBADRU 54 W R W A Transmit Buffer Byte Count ATBCNT 5A W R W B Transmit Buffer Byte Count BTBCNT 58 W R W A Transmit Buffer Status ATBSTS SF B R W B Transmit Buffer Status BTBSTS 5E B R W Transmit Current Buffer Address Lower TCBADRL 3A W R Transmit Current Buffer Address Upper TCBADRU 38 W R Timer Registers Timer Period Register TPR DA R W Receive Time out Period Register RTPR 24 W R W Async Receive Time out Period Regis low RTPRI 25 B R W Async Receive Time out Period Register high RTPRh 24 B R W Async General
62. RESET OPS OPS OPS This register is the attribute register for the second local bus to VMEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 2 Since the local bus to VMEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to the segment defined by map decoder 2 When this bit is low write posting is disabled to the segment defined by map decoder 2 When this bit is high D16 data transfers are performed to the segment defined by map decoder 2 When this bit is low D32 data transfers are performed to the segment defined by map decoder 2 http www motorola com computer literature 2 45 VMEchip2 Local Bus Slave VMEbus Master Attribute Register 1 ADR SIZ FFF40028 8 bits of 32 BIT 7 6 2 4 3 2 1 0 NAME D16 WP AM OPER R W R W R W RESET 0 PS 0 PS O PS This register is the attribute register for the first local bus to V MEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 1 Because the local bus to V MEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to
63. Registers GCSRs for interprocessor communications The following table summarizes the characteristics of the VMEchip2 ASIC Table 2 1 Features of the VMEchip2 ASIC Function Features Local Bus to Programmable local bus map decoder VMEbus Interface Programmable short standard and extended VMEbus addressing Programmable AM codes Programmable 16 bit and 32 bit VMEbus data width Software enabled write posting mode Write post buffer one cache line or one four byte Automatically performs dynamic bus sizing for VMEbus cycles Software configured VMEbus access timers Local bus to VMEbus Requester with Software enabled fair request mode Software configured release modes Release When Done RWD and Release On Request ROR Software configured BRO BR3 request levels VMEchip2 Table 2 1 Features of the VMEchip2 ASIC Continued Function VMEbus to Local Bus Interface Features Programmable VMEbus map decoder Programmable AM decoder Programmable local bus snoop enable Simple VMEbus to local bus address translation 8 bit 16 bit and 32 bit VMEbus data width 8 bit 16 bit and 32 bit block transfer Standard and extended VMEbus addressing Software enabled write posting mode Write post buffer 17 four bytes in BLT mode two four bytes in non BLT mode An eight four byte read ahead buffer BLT mode only
64. This allows a block of data to be transferred between VMEbus memory and local bus memory In some applications it may be desirable to transfer a block of data from local bus memory to a single VMEbus address This single VMEbus address may be a FIFO or similar type device which can accept a large amount of data but only appears at single VMEbus address The controller provides support for these devices by allowing transfers without incrementing the VMEbus address The DMA controller also allows DMA transfers without incrementing the local bus address although the MVMEIXx7P has no onboard devices that benefit from not incrementing the local bus address The transfer mode on the VMEbus may be D16 D16 BLT D32 D32 BLT or D64 BLT When the no increment address mode is selected some of the VMEbus address lines and local bus address lines continue to increment in some modes This is required to support the various port sizes 2 12 Computer Group Literature Center Web Site Functional Blocks and to allow transfers which are not an even byte count or which start at an odd address with respect to the port size A 16 bit device should respond with VA 1 high or low Devices on the local bus should respond to any combination of LA lt 3 2 gt This is required to support the burst mode on the MC680x0 bus Normally when the non increment mode is used the starting address and byte count would be aligned to the port size For example
65. This section provides addresses and bit level descriptions of the DMAC counters control registers and status registers Other control functions are also included in this section EPROM Decoder SRAM and DMA Control Register ADR SIZ FFF40030 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME WAITRMW ROMO TBLSC SRAMS OPER R W R W R W R W RESET OPSL 1PSL OPS OPS This register controls the snoop control bits used by the DMAC when it is accessing table entries SRAMS These VMEchip2 bits not used on the MVME1x7P http www motorola com computer literature 2 53 VMEchip2 TBLSC These bits control the snoop signal lines on the local bus when the DMAC is table walking The snooping functions differ according to processor type as shown TBLSC Requested Snoop Operation 19 18 MC68040 MC68060 0 0 Snoop disabled Snoop enabled 0 1 Source dirty sink byte word longword Snoop disabled 1 0 Source dirty invalidate line Snoop enabled 1 1 Snoop disabled Reserved Snoop disabled ROMO This bit is not used on the MVME1x 7P Its function is performed by the ROMO bit in the Petra MC2 PROM Access Time Control register Refer to Chapter 3 WAIT RMW This function is not used on the MVMEIx7P Local Bus to VMEbus Requester Control Register ADR SIZ FFF40030 8 bits 7 used OF 32 BIT 15 14 13 12 11 10 9 8 NAME ROBN DHB DWB L
66. Timer 1 GTI 2A W R Sync http www motorola com computer literature 1 39 Programming Issues Table 1 9 Cirrus Logic CD2401 Serial Port Memory Map Continued Base Address FFF45000 Register Description Register Offsets Size Access Name General Timer 1 low 2 R Sync General Timer 1 high 2 R Sync General Timer 2 GT2 29 B R Sync Transmit Timer Register TTR 29 B R Async Note This is a 16 bit register Table 1 10 82596CA Ethernet LAN Memory Map 82596CA Ethernet LAN Directly Accessible Registers Data Bits Address D31 D16 D15 DO FFF46000 Upper Command Word Lower Command Word FFF46004 MPU Channel Attention CA Notes 1 Refer to the MPU Port and MPU Channel Attention register entries 2 After resetting you must write the System Configuration Pointer to the command registers before writing to the MPU Channel Attention register Writes to the System Configuration Pointer must be upper word first lower word second 1 40 Computer Group Literature Center Web Site Memory Maps Table 1 11 53C710 SCSI Memory Map Base Address is F FF47000 Big Endian 53C710 Register Address Map SCRIPTs Mode and Mode Little Endian Mode 00 SIEN SDID SCNTL1 SCNTLO 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 55 SSTATO DSTAT 0C 10 DSA 10 14 CTES
67. W R W RESET 0 PSL PSL This register is used to define the level of the VMEbus level 3 IRQ3 interrupt and the VMEbus level 4 IRQ4 interrupt The IRQ3 and IRQ4 interrupts may be mapped to any local bus interrupt level VIRQ3 LEVEL These bits define the level of the VMEbus IRQ3 interrupt VIRQ4 LEVEL These bits define the level of the VMEbus IRQ4 interrupt Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 4 bits 0 7 ADR SIZ FFF40084 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME VIRQ2 VIRQI LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the VMEbus level 1 IRQ1 interrupt and the VMEbus level 2 IRQ2 interrupt The IRQ1 and IRQ2 interrupts may be mapped to any local bus interrupt level VIRQ1 LEVEL These bits define the level of the VMEbus IRQ interrupt VIRQ2 LEVEL These bits define the level of the VMEbus IRQ interrupt Vector Base Register ADR SIZ FFF40088 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME VBR 0 VBR 1 R W R W RESET 0 PSL 0 PSL This register is used to define the interrupt base vectors VBR 1 These bits define the interrupt base vector 1 VBR 0 These bits define the interrupt base vector 0 Note Refer to Table 2 4 Local Bus Interrupter Summary for further information A suggested setting for the VMEchip2 Vector Base reg
68. When this bit is low the VMEbus interrupt has been acknowledged This is a read only status bit This bitis the VMEbus interrupt clear bit When this bit is set high the VMEbus interrupt is removed This feature is only used when the IRQ1 broadcast mode is used Normal VMEbus interrupts should never be cleared This bit always reads 0 writing a 0 to it has no effect These bits control the function of the IRQI signal line on the VMEbus 0 The IRQI signal from the interrupter is connected to the VMEbus IRQI signal line 1 The output from tick timer 1 is connected to the VMEbus IRQ signal line 2 The IRQI signal from the interrupter is connected to the VMEbus signal line 3 The output from tick timer 2 is connected to the VMEbus IRQ signal line http www motorola com computer literature 2 61 VMEchip2 VMEbus Interrupter Vector Register ADR SIZ FFF40048 8 bits of 32 BIT 23 er 16 NAME Interrupter Vector OPER R W RESET 0F PS This register controls the VMEbus interrupter vector MPU Status and DMA Interrupt Count Register ADR SIZ FFF40048 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME DMAIC MCLR MLBE MLPE MLOB OPER R C R R R RESET 0 PS 0 PS 0 PS 0 PS 0 PS This is the MPU status register and DMAC interrupt counter MLOB MLPE MLBE MCLR When this bit is set the MPU received a TEA and the status indicated off board T
69. With the value of 00 a Transfer Modifiers TM2 TMO With the value of 101 Transfer Acknowledge TA if Transfer Error Acknowledge is detected LANC Bus Error The 82596CA does not provide a way to terminate a bus cycle with an error indication The interface to the 82596CA on the Single Board Computers provides several ways of processing bus errors that occur while the 82596CA is local bus master These options are controlled by registers in the VMEchip2 and the PCCchip2 The GPIO2 signal on the VMEchip2 LCSR address FFF40088 controls how the 82596CA interface logic responds to bus errors If the GPIO2 signal is programmed as an input reset state or programmed as an output and set high bus errors are processed in the following way The 82596CA interface logic monitors all bus cycles initiated by the 82596CA and if a bus error is indicated TEA 0 and TA 1 the Back Off signal BOFF to the 82596CA is asserted to keep the 82596CA off the local bus and prevent it from transmitting bad data or corrupting local 3 4 Computer Group Literature Center Web Site Functional Description memory The LANC Error Status Register in the PCCchip2 is updated and a LANC bus error interrupt is generated if it is enabled in the PCCchip2 The Back Off signal remains asserted until the 82596CA is reset via a port reset command After the 82596CA is reset pending operations must be restarted If the GPIO2 signa
70. allow the on chip DMA Controller to request and be granted use of the VMEbus Requiring no external jumpers the chip provides the means for software to program the DMAC requester to request the bus on any one of the four bus request levels automatically establishing the bus grant daisy chains for the three inactive levels http www motorola com computer literature 2 13 VMEchip2 The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer The requester implements a fair mode By setting the DFAIR bit the requester refrains from requesting the bus until it detects its assigned request line in its negated state The requester releases the bus when requested to by the DMA controller The DMAC always releases the VMEbus when the FIFO is full VMEbus to local bus or empty local bus to VMEbus The DMAC can also be programmed to release the VMEbus when another VMEbus master requests the bus when the time on timer has expired or when the time on timer has expired and another VMEbus master is requesting the bus To minimize the timing overhead of the arbitration process the DMAC requester executes an early release of the bus If it is about to release the bus and it is executing a VMEbus cycle the requester releases BBSY before its associated VMEbus master completes the cycle This allows the arbiter to arbitrate any pending requests and grant the bus to the next requester at the same time that the
71. bit in the LCSR The local bus to VMEbus requester in the VMEchip2 implements a fair mode By setting the LVFAIR bit the requester refrains from requesting the VMEbus until it detects its assigned request line in its negated state The local bus to V MEbus requester attempts to release the VMEbus when the requested data transfer operation is complete the DWB pin is negated the DWB bit in the LCSR is negated and the bus is not being held by a lock cycle The requester releases the bus as follows 1 When the chip is configured in release when done RWD mode the requester releases the bus when the above conditions are satisfied 2 When the chip is configured in release on request ROR mode the requester releases the bus when the above conditions are satisfied and there is a bus request pending on one of the VMEbus request lines To minimize the timing overhead of the arbitration process the local bus to VMEbus requester in the VMEchip2 executes an early release of the VMEbus If it is about to release the bus and it is executing a VMEbus cycle the requester releases BBSY before its associated master completes the cycle This allows the arbiter to arbitrate any pending requests and grant the bus to the next requester at the same time that the active master completes its cycle 2 8 Computer Group Literature Center Web Site Functional Blocks VMEbus to Local Bus Interface The VMEbus to local bus interface allows an o
72. control logic does not allow the value 255 SFF to be programmed http www motorola com computer literature 2 67 VMEchip2 Tick Timer 1 Compare Register ADR SIZ FFF40050 32 bits BIT 31 oes 0 NAME Tick timer 1 Compare Register OPER R W RESET OP The tick timer 1 counter is compared to this register When they are equal an interrupt is sent to the local bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to calculate the compare register value for a specific period T compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 1 Counter ADR SIZ FFF40054 32 bits BIT 31 iss 0 NAME Tick timer 1 Counter OPER R W RESET OP This is the tick timer 1 counter When enabled it increments every microsecond Software may read or write the counter at any time 2 68 Computer Group Literature Center Web Site LCSR Programming Model Tick Timer 2 Compare Register ADR SIZ FFF40058 32 bits BIT 31 0 Tick timer 2
73. data structure of the configuration bytes starts at SFFFCIEFS and is as follows http www motorola com computer literature 1 43 Programming Issues struct brdi_cnfg char version 4 char serial 12 char id 16 char 16 char speed 4 char ethernet adr 6 char char lscsiid 2 char sysid 8 char brdl pwb 8 char brdl serial 8 char brd2 pwb 8 char brd2 serial 8 char reserved 153 char cksum 1 The fields are defined as follows 1 Four bytes are reserved for the revision or version of this structure This revision is stored in ASCII format with the first two bytes being the major version numbers and the last two bytes being the minor version numbers For example if the version of this structure is 1 0 this field contains 0100 Twelve bytes are reserved for the serial number of the board in ASCII format For example this field could contain 000000470476 Sixteen bytes are reserved for the board ID in ASCII format For example for a 16 MB 25 MHz MVME167 board this field contains MVME167P 24SE The 13 characters are followed by three blanks Sixteen bytes are reserved for the printed wiring assembly PWA number assigned to this board in ASCII format This includes the 01 w prefix This is for the main logic board if more than one board is required for a set Additional boards in a set are defined by a 1 44 Computer Gr
74. devices appear at FF800000 FFBFFFFF and also appear at 00000000 003FFFFF if the ROMO bit in the VMEchip2 EPROM control register is high ROMO 1 The ROMO bit is located at address FFF40030 bit 20 ROMO is set to 1 after each reset The ROMO bit must be cleared before other resources DRAM or SRAM can be mapped in this range http www motorola com computer literature Programming Issues 00000000 003FFFFF The VMEchip2 and DRAM map decoders are disabled by a local bus reset On the MVMEITT7P the Flash EPROM memory is mapped at 00000000 003FFFFF by hardware default through the VMEchip2 This area is user programmable The suggested use is shown in the table The DRAM decoder is programmed in the MCECC chip and the local to VMEbus decoders are programmed in the VMEchip2 Size is approximate Cache inhibit depends on devices in area mapped This area is not decoded If these locations are accessed and the local bus timer is enabled the cycle times out and is terminated by a TEA signal The Flash and EEPROM configuration is jointly controlled by a configuration switch S4 as described in Chapters 1 and 4 of MVME177P Single Board Computer Installation and Use and by control bit GPIO2 in the VMEchip2 ASIC as described in Chapter 2 VM Echip2 Depending on the setting of S4 this address space may reference 2MB EPROM 1 EPROM and 2MB Flash or 4MB Flash Table 1 4 focuses on the
75. error correcting code 4 5 edge level sensitive interrupt GPIO 3 24 LANC 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer paper error 3 42 printer select 3 41 edge sensitive interrupters VMEbus 2 19 edge sensitive interrupts VMEchip2 ASIC 2 74 EIA 232 D drivers receivers 1 13 ending address register VMEbus slave 2 38 ending address register slave map decoder 2 27 EPROM 1 8 addresses 1 21 socket 1 3 errata sheets obtaining 1 25 error conditions description of 1 55 error logging MCECC sector 4 5 4 8 error status LANC error 3 34 SCC error PCCchip2 ASIC 3 27 error status register SCSI 3 37 errors LANC bus 3 4 Ethernet station address 1 15 1 45 restoring to BBRAM 1 15 examples setting up interrupt handler routine 1 49 setting up local bus interrupter 1 48 extended access cycles VMEbus 2 34 2 37 F fair mode VMEchip2 2 8 2 14 fast read bit status 4 14 features MCECC sector 4 1 MVMEIXT7P 1 3 PCCchip2 ASIC 3 1 VMEchip2 ASIC 2 1 Flash memory devices 1 8 1 9 functional description 1 17 VMEchip2 ASIC 2 4 G GCSR base address registers programming 2 37 board address 2 48 group address 2 47 map decoder 1 46 programming model 2 100 SIG3 0 interrupters VMEbus 2 19 GCSR global control status registers programming 2 102 VMEchip2 2 20 2 100 General Control register PCCchip2 ASIC 3 3 3 15 General Purpose Input Interrupt Control register PCCchip2 ASIC 3 24 General Purpose Inpu
76. falling edge low level of the LANC INT pin Note that if this bitis changed while the E L bit is set or is being set a LANC interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the bit http www motorola com computer literature 3 35 PCCchip2 LANC Bus Error Interrupt Control Register ADR SIZ FFF4202B 8 bits BIT 7 6 5 4 3 2 1 0 5 5 0 INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level Level 0 does not generate an interrupt ICLR Writing a logic 1 into this bit clears the INT status bit This bit is always read as zero Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low IRQ Interrupt Status When this bit is high a LANC Bus Error interrupt is being generated at the level programmed in IL2 ILO if nonzero SC1 SCO Snoop Control These control bits determine the value that the PCCchip2 drives onto the local MC68040 bus SC1 and SCO pins when the 82596CA LANC performs DMA accesses During LANC DMA if bit SCO is 0 Local Bus pin SCO is low and when bit SCO is 1 pin SCO is high The same relationship holds true for bit and pin SC1 See the M68040 user s manual for details on how it uses the Snoop Cont
77. feature similar to that of the 47 In auto strobe mode after a write to the Printer Data Register the PCCchip2 automatically asserts the STROBE pin for a selected time specified by the Printer Fast Strobe control bit In manual mode the Printer Strobe control bit directly controls the state of the STROBE pin 3 6 Computer Group Literature Center Web Site Functional Description General Purpose I O Pin The General Purpose I O pin can be used as an input pin as an output pin or as both The PCCchip2 has a status bit that reflects the state of the pin The PCCchip2 also has a control bit that allows it to drive the pin and another control bit that controls the level that is driven The input can be configured to generate an interrupt to the MPU in any of the following programmable conditions high level low level high to low transition or low to high transition CD2401 SCC Interface The PCCchip2 provides the required logic to interface the CL CD2401 SCC Intelligent MultiProtocol Peripheral to the MC68040 compatible Local Bus The interface logic consists of a local master interface a local slave interface a CD2401 Host interface a CD2401 DMA interface a CD2401 interrupt handler and a Local Bus requester The base address for the CL CD2401 is FFF45000 It has 8 and 16 bit registers only Consequently it does not respond when accessed with a size of 4 bytes SIZ1 0 9600 or with a size of 16 byt
78. interrupt Clear software 1 interrupt Clear software 2 interrupt Clear software 3 interrupt Clear software 4 interrupt Clear software 5 interrupt Clear software 6 interrupt Clear software 7 interrupt Interrupt Level Register 1 bits 24 31 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 31 30 29 28 27 26 25 24 NAME ACF LEVEL AB LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the abort interrupt and the ACFAIL interrupt AB LEVEL Not used on MVMEIx7P LEVEL These bits define the level of ACFAIL interrupt http www motorola com computer literature 2 87 VMEchip2 Interrupt Level Register 1 bits 16 23 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SYSF LEVEL WPE LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the SYSFAIL interrupt and the master write post bus error interrupt WPE LEVEL These bits define the level of the master write post bus error interrupt SYSF LEVEL These bits define the level of the SYSFAIL interrupt Interrupt Level Register 1 bits 8 15 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME PE LEVEL IRQIE LEVEL OPER R W R W RESET PSL 0 PSL This register is used to define the level of the VMEbus IRQ1 edge sensitive interrupt and
79. interrupt service routine causes a second bus error the status that indicates the source of the first bus error may be lost Application software must take this possibility into account Error Conditions This section lists the various error conditions that are reported by the single board computer hardware A subheading identifies each error condition a standard format provides the following information a Description of the error How notification of the error is made Status register s containing information about the error Comments pertaining to the error http www motorola com computer literature 1 55 Programming Issues MPU Parity Error Description MPU Notification Status Comments MPU Offboard Error Description MPU Notification Status Comments A DRAM parity error TEA is asserted during an MPU DRAM access Bit 9 of the MPU Status and DMA Interrupt Count register in the VMEchip2 at address FFF40048 After memory has been initialized this error normally indicates a hardware problem An error occurred while the MPU was attempting to access an offboard resource TEA is asserted during offboard access Bit 8 of the MPU Status and DMA Interrupt Count register Address FFF40048 This can be caused by a VMEbus timeout a VMEbus BERR or a single board computer VMEbus access timeout The latter is the time from when the VMEbus has been requested to when it is
80. local bus and the VMEbus and if the aborted cycle is bound for the VMEbus erratic operation may result Communications between the local processor and a VMEbus master should use interrupts or mailbox locations reset should not be used in normal communications Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort http www motorola com computer literature 2 101 VMEchip2 Programming the GCSR A complete description of the GCSR appears in the following tables Each register definition includes a table with five lines 1 The base address of the register and the number of bits defined in the table The bits defined by this table The name of the register or the name of the bits in the register The operations possible on the register bits defined as follows R This bit is a read only status bit R W This bit is readable and writable S R Writing a to this bit sets it Reading it returns its current status The state of the bit following a reset defined as follows This bit is affected by power up reset The bit is affected by SYSRESET The bit is affected by local bus reset The bit is not affected by reset 2 102 Computer Group Literature Center Web Site GCSR Programming Model Table 2 5 shows a summary of the GCSR Table 2 5 VMEchip2 Memory Map GCSR Summary VMEchip2 GCSR Base Address FFF40100
81. local bus masters may use the local bus while the DMAC is waiting for the VMEbus http www motorola com computer literature 2 11 VMEchip2 The DMAC also supports command chaining through the use of a singly linked list built in local memory Each entry in the list includes a VMEbus address a local bus address a byte count a control word and a pointer to the next entry When the command chaining mode is enabled the DMAC reads and executes commands from the list in local memory until all commands are executed The DMAC can be programmed to send an interrupt request to the local bus interrupter when any specific table entry has completed In addition the DMAC always sends an interrupt request at the normal completion of a request or when an error is detected If the DMAC interrupt is enabled in the DMAC the local bus is interrupted For increased flexibility in managing the bus tenure to optimize bus usage as required by the system configuration the chip contains control bits that allow the DMAC time on and off the bus to be programmed Using these control bits software can instruct the DMA controller to acquire the bus maintain mastership for a specific amount of time and then after relinquishing it refrain from requesting it for another specific amount of time No Address Increment DMA Transfers During normal memory to memory DMA transfers the DMA controller is programmed to increment the local bus and VMEbus address
82. n 1 12 Setia Port UMS MASS acce itte EDO RE PIER ES Roa e Rb 1 13 Parallel Printer ERE FER E peux UE 1 14 Ethernet Dite 308 au oo e E aie aM 1 15 SCSI gt me 1 16 esci EE esie spies span dp prie MERI REDIT ap iru AME 1 16 Programmable Tick ade Hei ba ui 1 16 Bir eng nee rece renter te erent ree Tt 1 17 Software Programmable Hardware Interrupts sees 1 17 Bus T HOSCE iier etian 1 17 vii Purictional nate 1 17 VMEbus Interface and V MIBGIIp2 iuis eire bre Irt bn x UR 1 18 2 General Purpose rettet tran 1 18 Petra VMEchip2 Redundant LOIC uiae e Fo Rb IE RP 1 18 Memory 8 M 1 20 Local Bis naui m 1 20 Normal Address 1 20 Detailed VO Memory Maps 1 25 BBRAM TOD Clock Memory Map err eite 1 41 Acknowledge 1 46 VMEbus Memory ER RUE 1 46 Accesses to the Local Bus 1 46 VMEbus Short YO Memory Map eoe ees 1 46 Lite 1 47 Example VMEchip2 Tick Timer 1 Periodic Interrupt
83. not safe Block transfer is not supported because the MC680x0 block transfer capability is not compatible with the VMEbus The VMEbus master supports dynamic bus sizing When a local device initiates a quad byte access to a VMEbus slave that only has the D16 data transfer capability the chip executes two double byte cycles on the VMEbus acknowledging the local device after all requested four bytes 2 6 Computer Group Literature Center Web Site Functional Blocks have been accessed This enhances the portability of software because it allows software to run on the system regardless of the physical organization of global memory Using the local bus map decoder attribute register the AM code that the master places on the VMEbus can be programmed under software control The VMEchip2 includes a software controlled VMEbus access timer It starts ticking when the chip is requested to do a VMEbus data transfer or an interrupt acknowledge cycle The timer stops ticking once the chip has started the data transfer on the VMEbus If the data transfer does not begin before the timer times out the timer drives the local bus error signal and sets the appropriate status bit in the Local Control and Status Register LCSR Using control bits in the LCSR the timer can be disabled or it can be enabled to drive the local bus error signal after 64 us 1 ms or 32 ms The VMEchip2 includes a software controlled VMEbus write post timer It st
84. of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Manual xxii Comments aid b T T xxii Conventions Used in This xxiii CHAPTER 1 Programming Issues WSCC OM T P E 1 1 The Petra ASIC and Second Generation MVME I X7 Boards 1 1 1 3 Applicable Industry Standards dnote 1 4 Block Dia BT 1 4 Programming rion UO UPC ERU 1 7 1 7 o irs ier M Ripe RC IH dies R 1 7 EEPROMs ott the MV MIB UX TP iai incerti tere Het xu pnr RD 1 8 eT POT A 1 8 T pec 1 9 Flash Memory on the MVYMEI I T erie ES nina PA IE i 1 9 SRAM C 1 10 dits cie SORAN 1 11 B ttery Backed Up RAM and Clock uei en ortae tea ceti 1 12 YME DUS Veit eG A EE 1 12 ings ar E
85. register 4 bits 0 7 2 95 Miscellaneous Control register 2 98 Status register bits 16 23 2 78 Status register bits 24 31 2 77 Vector Base register 2 95 local bus master 2 9 VMEbus and 2 10 local bus slave VMEbus master registers Address Translation Address Register 4 2 42 Address Translation Select Register 4 2 42 Attribute Register 1 2 46 Attribute Register 2 2 45 Attribute Register 3 2 44 Attribute Register 4 2 43 Ending Address Register 1 2 39 Ending Address Register 2 2 40 Ending Address Register 3 2 41 Ending Address Register 4 2 41 Starting Address Register 1 2 40 Starting Address Register 2 2 40 Starting Address Register 3 2 41 Starting Address Register 4 2 42 local bus slave composition of 2 4 local bus timer VMEchip2 ASIC 2 18 local control and status segisters LCSRs VMEbus 2 7 local I O devices memory map 1 22 local reset driver VMEbus 2 18 local reset VMEbus 2 18 local SCSI ID 1 45 local bus to VMEbus Enable Control register 2 49 I O Control register 2 50 interface 1 18 interface VMEchip2 2 4 map decoders programming 2 37 requester 2 7 requester register programming 2 51 location monitor interrupters VMEbus 2 19 status register VMEchip2 ASIC 2 101 location monitors LMO LM3 VMEchip2 ASIC 2 100 LVFAIR bit VMEchip2 ASIC 2 8 M M48T58 BBRAM TOD Clock memory map 1 42 manual strobe control 3 45 map decoders 2 37 GCSR 1 46 SDRAM 1 11 VMEbus interface 1 46 VMEchip2 ASIC 2
86. register is the ending address register for the second VMEbus to local bus map decoder VMEbus Slave Starting Address Register 2 ADR SIZ FFF40004 16 bits of 32 BIT 15 0 Starting Address Register 2 OPER R W RESET 0 PS This register is the starting address register for the second VMEbus to local bus map decoder VMEbus Slave Address Translation Address Offset Register 1 ADR SIZ FFF40008 16 bits of 32 BIT 31 re 16 NAME Address Translation Address Offset Register 1 OPER R W RESET 0 PS This register is the address translation address register for the first VMEbus to local bus map decoder It should be programmed to the local bus starting address When the adder is engaged this register is the offset value http www motorola com computer literature 2 29 VMEchip2 VMEbus Slave Address Translation Select Register 1 ADR SIZ FFF40008 16 bits of 32 BIT 15 2 0 Address Translation Select Register 1 OPER R W RESET 0 PS This register is the address translation select register for the first VMEbus to local bus map decoder The address translation select register value is based on the segment size the difference between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size Segment
87. starting address of the GCSR in the VMEbus short I O space 1 46 Computer Group Literature Center Web Site Interrupt Handling Interrupt Handling M68000 based systems use hardware vectored interrupts Board MPUs from the M68000 family require that the C040 bit in the PCCchip2 General Control register address FFFA2002 be set For more information refer to the General Control Register section in Chapter 3 PCCchip2 Most interrupt sources are level and base vector programmable Interrupt vectors from the PCCchip2 and VMEchip2 ASICs have two sections Base value Can be set by the processor usually the upper four bits Lower bits Set according to the particular interrupt source There is a hierarchy of interrupt sources prioritized as follows Highest priority Interrupts from the PCCchip2 Lowest priority Interrupt sources from the VMEchip2 The MC68040 and MC68060 processors employ a seven level prioritized hardware vectored interrupt scheme that is standard in the M68000 family The Local Bus distinguishes interrupt acknowledge cycles from other cycles by placing the binary value 11 on TT1 TTO It also specifies the level that is being acknowledged using TM2 TMO The interrupt handler selects which device within that level is being acknowledged Example VMEchip2 Tick Timer 1 Periodic Interrupt This section describes the use of interrupts on MVME167P and MVMEI177P single board computers The following example illustra
88. the DMAC when it loads the command word from the command packet Because this register is loaded from the command packet in command chaining mode the descriptions here also apply to the control word in the command packet D16 TVME LINC VINC When this bit is high the DMAC executes D16 cycles on the VMEbus When this bit is low the DMAC executes D32 D64 cycles on the VMEbus This bit defines the direction in which the DMAC transfers data When this bit is high data is transferred to the VMEbus When it is low data is transferred to the local bus When this bit is high the local bus address counter is incremented during DMA transfers When this bit is low the counter is not incremented This bit should normally be set high In special situations such as transferring data to or from a FIFO it may be desirable to not increment the counter When this bit is high the VMEbus address counter is incremented during DMA transfers When this bit is low the counter is not incremented This bit should normally be set high In special situations such as transferring data to or from a FIFO it may be desirable to not increment the counter http www motorola com computer literature 2 57 VMEchip2 SNP These bits control the snoop signal lines on the local bus when the DMAC is local bus master and itis not accessing the command table The snooping functions differ according to processor type as shown Requested Sn
89. the segment defined by map decoder 1 When this bit is low write posting is disabled to the segment defined by map decoder 1 When this bit is high D16 data transfers are performed to the segment defined by map decoder 1 When this bit is low D32 data transfers are performed to the segment defined by map decoder 1 2 46 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave GCSR Group Address Register ADR SIZ FFF4002C 8 bits of 32 BIT 31 24 GCSR Group Address Register 4 OPER R W RESET 00 PS This register defines the group address of the GCSR as viewed from the VMEbus The GCSR address is defined by the group address and the board address Once enabled the GCSR register should not be reprogrammed unless the VMEchip2 ASIC is VMEbus master GCSR Group These bits define the group portion of the GCSR address These bits are compared with VMEbus address lines A8 through A15 The recommended group address for the MVMEIx7P is 02 http www motorola com computer literature 2 47 VMEchip2 VMEbus Slave GCSR Board Address Register ADR SIZ FFF4002C 4 bits of 32 BIT 23 20 GCSR Board Address OPER R W RESET F PS This register defines the board address of the GCSR as viewed from the VMEbus The GCSR address is defined by the group address and the board address Once enabled the GCSR register shoul
90. the current value in the Scrub Address counter bits 7 4 ADR SIZ 1st FFF43058 2nd FFF43158 8 bits BIT 31 30 29 28 27 26 25 24 SAC7 SAC6 SAC5 SAC4 0 0 0 0 OPER R W R W R W R W R R R R RESET OPLS OPLS OPLS OPLS X X X X 4 26 Computer Group Literature Center Web Site Programming Model Error Logger Register ADR SIZ BIT 1st FFF4305C 2nd FFF4315C 8 bits 31 30 29 28 27 26 25 24 NAME ERRLOG ERD ESCRB ERA EALT 0 MBE SBE OPER R C R R R R R R R RESET 0 PLS 0 PLS 0 PLS OPLS OPLS X OPLS EALT ESCRB ERD SINGLE BIT ERROR is set when the last error logged was due to a single bit error It is cleared when a 1 is written to the ERRLOG bit The syndrome code reflects the bit in error Refer to the Syndrome Decoding section MULTIPLE BIT ERROR is set when the last error logged was due to a multiple bit error It is cleared when a 1 is written to the ERRLOG bit The syndrome code is meaningless if MBE is set This bit provides status for a function that is not currently used in the MCECC sector EALT indicates that the last logging of an error occurred on a DRAM access by an alternate MI not asserted local bus master ESCRB indicates the entity that was accessing DRAM at the last logging of a single or double bit error If ESCRB
91. the hardware specification 2 108 Computer Group Literature Center Web Site PCCchip2 Introduction This chapter defines the peripheral channel controller ASIC referred to hereafter as the PCCchip2 The PCCchip2 is designed to interface an MC68040 compatible local bus Local Bus to various peripheral devices Summary of Major Features This section lists the major features of the PCCchip2 BBRAM interface with dynamic sizing support 8 bit parallel I O port Master and slave interface for CD2401 Intelligent Multi Protocol Peripheral Host interface to Intel 82596CA LAN Coprocessor Host interface to NCR SCSI I O Processor Two 32 bit tick timers a Interrupt handler for tick timers and all peripherals All interrupts are level programmable All interrupts are maskable Allinterrupts provide a unique vector 3 1 PCCchip2 Functional Description The following sections provide an overview of the functions provided by the PCCchip2 A detailed programming model for the PCCchip2 control and status registers is provided in a later section General Description The PCCchip2 interfaces the MC68040 microprocessor bus to the local peripherals on the Single Board Computers including battery backed RAM Serial Communications Controller CL CD2401 LAN controller 82596CA and SCSI controller NCR53C710 The PCCchip2 also provides two 32 bit timers and a parallel I O p
92. the level programmed in IL2 ILO if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a rising edge high level of the PE pin When this bit is high interrupt is activated by a falling edge low level of the PE pin Note that if this bit is changed while the E L bit is set or is being set a PE interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the E L bit 3 42 Computer Group Literature Center Web Site Programming Model Printer BUSY Interrupt Control Register ADR SIZ FFF42034 8 bits BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the printer BUSY Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as zero IEN When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a printer BUSY interrupt is being generated at the level programmed in IL2 ILO if nonzero E L When this bit is high the interrupt is edge sensitive The
93. when it completes The sequence begins when the MPU asserts a request for the Local Bus The MPU must wait until the Local Bus is released by the current bus master before its cycle can begin When the MPU is granted the Local Bus it begins its cycle and the Local Bus timer starts counting It continues to count until an address decode of the VMEbus address space is detected and then the timer stops This is normally a very short period of time In fact all Local Bus non error bus accesses are normally very short such as the time to access onboard memory Therefore it is recommended this timer be set to a small value such as 8 usec The next timer to take over when one single board computer accesses another is the VMEbus access timer This measures the time from when the VMEbus has been address decoded and hence a VMEbus request has been made to when VMEbus mastership has been granted Because experience has shown that some VME systems can become very busy we recommend this time out be set to a large value such as 32 msec For debug purposes this value can also be set to infinity Once the VMEbus has been granted a third timer takes over This is the global VMEbus timer This timer starts when a transfer actually begins DSO or DS1 goes active and ends when that transfer completes DSO or http www motorola com computer literature 1 51 Programming Issues DS1 goes inactive This time should be longer than any expected legit
94. 1 buts 2 88 Interrupt Level Register 1 bits aiios xi bise EM labe air 2 89 Inierrupt Level Register gt bots 24 313 iuit user eer ttov deba 2 89 Interrupt Level Register 2 bits 16 23 Yee ERRARE 2 90 Interrupt Level Register 915 2 90 Interrupt Level Register 2 buts 0 7 repas et bebes 2 91 Interrupt Level Register 3 buts 24 31 2 91 Interrupt Level Register 3 bits 10 23 cpiscessessntassssscanceestascaptveupecs speso niv cane 2 92 Level Register 2 92 Interrupt Level Register 3 bits aang 2 903 Interrupt Level Register 4 bats 24 31 dont tete 2 93 Interrupt Level Register 4 bits 16 23 serre sesion 2 94 Interrupt Level Register 2 94 Interrupt Level Register 4 bits T Laici cade pier tr atrii Mrs ire 2 95 Vector Base or ec 2 95 DO Contool Reister oerte p REAR 2 96 xi VO Control 2 2 97 LO Comiol Register 3 oneni enea E E 2 97 Miscellaneous Conttol trenta p ee 2 98 GCSR Propr mmime Model EE ER HEUS HER ER 2 100 Programming 2 102 Revision HP Aei 2
95. 1807 IRQs IRQ5 1804 IRQ2 IRQ1 EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN IRQ IRQ IRQ RQ IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET SET SET SET SET SET SET SET IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 CLR CLR CLR CLR CLR IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 P ERROR IRQIE TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SIG 1 SIG 0 LM 1 LM 0 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL sws swe swi swo IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IRQ 4 VMEB IRQ 3 VME IRQ 2 VME IRQ 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL GPIOO GPIOI GPI Pa REV DIS DIS DIS EN DIS EN EROM SRAM MST ga BSYT INT BGN 1361 9403 lt _ This sheet begins on facing page http www motorola com computer literature 1 29 Programming Issues Table 1 5 VMEchip2 Memory Map Sheet 3 of 3 VMEchip2 GCSR Base Address FFF40100 Offsets Bit Numbers VME Lon 10 9 5 4 bus Bus 0 0 Chip Revision Chip ID 2 4 SYS X X X 1 1 1 1 s s C FL T 3 2 1 0 N 4 8 General Purpose Control and Status register 0 6 C General Purpose Control and Status register 1 8 10 Gener
96. 2401 This is required since the CD2401 has no other way of clearing its interrupt requests PIACK cycles happen as follows 1 The MPU waits for an IRQ bit to be set in one of the three SCC interrupt control registers The Local Bus master starts a normal read cycle to one of the three PIACK registers in the PCCchip2 The three PIACK registers correspond to modem transmit and receive interrupts respectively The PCCchip2 upon detecting the start of the read performs an interrupt acknowledge cycle to the CD2401 The PCCchip2 drives the CD2401 A7 through A0 pins with a value that corresponds to the PIACK register that is being read If the Modem PIACK Register is being read then A7 through AO 01 If the Transmit PIACK Register is being read then A7 through AO 02 If the Receive PIACK Register is being read then A7 through AO 03 Asthe interrupt acknowledge cycle completes the PCCchip2 places the vector being driven by the CD2401 onto the Local Bus DO through D8 and D16 through D23 signals From the MPU point of view the status read from the selected PCCchip2 PIACK register is the vector from the CD2401 The PCCchip2 signals to the local MPU via TA that the read cycle is complete 3 8 Computer Group Literature Center Web Site Functional Description Tick Timer The PCCchip2 includes two 32 bit general purpose tick timers The tick timers run on a IMHz clock which is derived from th
97. 3 29 SCC Receive Interrupt Control tete 3 30 Modern ADS 3 31 Transmit PISE Rr Rapp REM Mec 3 32 DIAC ee iei 3 33 LANC Error Status and Interrupt Control Registers 222 3 34 LANC Emor Stilus eic IS HEU IESU EM 3 34 92596 LANC Interrupt Control Register iere entire 3 33 LANC Bus Error Interrupt Control 3 36 Programming SCSI Error Status and Interrupt Registers 3 37 BC Emor SEU ROSISIBI iai Hale GS v Ed de rd 3 37 SCSI Control Rie ipe Ea prp eMe emacs 3 38 Erosramninig the Printer 3 39 Printer ACK Interrupt Control Register tenente ipee inar 3 39 Printer FAULT Intermpt Control Register iei eite ee rhet 3 40 Printer SEL Interrupt Control Register accen etre 3 41 Printer PE Control Restster ee 3 42 Printer BUSY Interrupt Control Register eese 3 43 Printer Diput Status Reate 3 44 Printer Port Control Reg tater Lon pesce Rape pete Un 3 45 C ID pep EUG eer eee 3 46 Printer Data copio 3 47 Interrupt Phony Level E Elek PER OR CUR ER
98. 3 bit in the local interrupt clear register This bit is cleared by an LMO cycle on the VMEbus When this bit is cleared an interrupt is set to the local bus interrupter This bit is set when the local processor or a VMEbus master writes a to the LMO bit in this register or the CLMO bit in local interrupt clear register This bit is cleared by an LMI cycle on the VMEbus When this bit is cleared an interrupt is set to the local bus interrupter This bit is set when the local processor or a VMEbus master writes a 1 to the LMI bit in this register or the CLMI bit in local interrupt clear register This bit is cleared by an LM2 cycle on the VMEbus This bit is set when the local processor or a VMEbus master writes a 1 to the LMO bit in this register This bit is cleared by an LM3 cycle on the VMEbus This bit is set when the local processor or a VMEbus master writes a 1 to the LM3 bit in this register http www motorola com computer literature 2 105 VMEchip2 VMEchip2 Board Status Control Register ADR SIZ Local Bus FFF40104 VMEbus XXY2 8 bits 5 used BIT 7 6 5 4 3 2 1 0 NAME RST ISF BF SCON SYSFL OPER S R R W R R R RESET OPSL OPSL PS X PSL This register is the VMEchip2 board status control register SYSFL SCON BF ISF RST This bit is set when the VMEchip2 is driving the SYSFAIL signal This bit is set if the VMEchip2 is system controller When t
99. 5 Bit numbering for the VMEchip2 and Petra ASICs has a one to one correspondence ABORT switch interrupt control Implemented also in the VMEchip2 but with different bit organization refer to the VMEchip2 description in Chapter 2 In the MVME1X7P the ABORT switch is wired to the Petra chip not the VMEchip2 The SRAM and EPROM decoder in the VMEchip2 version 2 must be disabled by software before any accesses are made to these address spaces http www motorola com computer literature 1 19 Programming Issues 8 32 bit prescaler The prescaler can also be accessed at FFF40064 when the optional VMEbus is not enabled Memory Maps There are two points of view for memory maps 1 The mapping of all resources as viewed by local bus masters local bus memory map 2 The mapping of onboard resources as viewed by VMEbus masters VMEbus memory map The memory maps and I O maps described in the following tables are correct for all local bus masters Some address translation capability exists in the VMEchip2 This capability makes it possible to have multiple MVME1X7P modules on the same VMEbus with different virtual local bus maps as viewed by different VMEbus masters Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The following ta
100. 5200 to FFF45FFF on the MVMEIXT7P If the local bus timer is enabled the access times out and is terminated by a TEA signal Computer Group Literature Center Web Site Memory Maps Detailed I O Memory Maps Tables 1 5 through 1 14 give the detailed memory maps for 7 VMEchip2 PCCchip 2 Printer MCECC Internal Register Cirrus Logic CD2401 Serial Port 82596CA Ethernet LAN chip 53C710 SCSI chip M48T58 BBRAM TOD Clock BBRAM Configuration Area TOD Clock Table 1 5 Table 1 7 Table 1 6 Table 1 8 Table 1 9 Table 1 10 Table 1 11 Table 1 12 Table 1 13 Table 1 14 You can obtain manufacturers errata sheets for the various chips listed above by contacting your local Motorola sales representative A non disclosure agreement may be necessary http www motorola com computer literature Programming Issues Table 1 5 VMEchip2 Memory Map Sheet 1 of 3 VMEchip2 LCSR Base Address FFF40000 OFFSET 0 SLAVE ENDING ADDRESS 1 4 SLAVE ENDING ADDRESS 2 8 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER SNP WP SUP usr 2 24 PRGM DATA 14 MASTER ENDING ADDRESS 1 18 MASTER ENDING ADDRESS 2 16 MASTER ENDING ADDRESS 3 20 MASTER ENDING ADDRESS 4 24 MASTER ADDRESS TRANSLATION ADDRESS 4 MAST MAST MAST MAST 28 D16 WP MASTER AM 4 D16 WP MA
101. 64 VMEbus global time out timer 2 65 Watchdog Timer Control register 2 71 timers 1 3 local bus 1 51 VMEbus 2 7 transfer mode VMEbus 2 12 Transfer Type TT signals 1 20 transfer types PCCchip2 ASIC 3 4 transition modules 1 13 connection diagrams B 1 transmit interrupt SCC 3 29 Transmit PIACK register PCCchip2 ASIC 3 32 triple bit error 4 6 U updates from previous boards A 1 user access cycles VMEbus 2 34 2 37 V Vector Base register VBR 3 17 vector base registers VMEchip2 ASIC 2 74 VME LED 2 99 VMEbus access timeout 1 54 access time out value DMAC 2 66 address counter DMAC 2 60 BBSY signal 2 98 BERR signal 1 54 capabilities 2 4 2 9 2 11 interface 1 4 1 12 interrupter function VMEchip2 ASIC 2 16 interrupter programming 2 51 IRQI IRQ2 interrupts 2 95 mapping 1 46 maps creating 2 6 master bus sizing and 2 6 request level DMAC 2 54 2 55 requester DMAC 2 13 segment size translating 2 30 IN 12 Computer Group Literature Center Web Site slave 2 9 slave map decoders 2 26 slave map decoders programming 2 26 system controller function 2 17 timer 2 18 VMEbus Slave registers Address Modifier Select Register 1 2 36 Address Modifier Select Register 2 2 33 Address Translation Address Offset Register 1 2 29 Address Translation Address Offset watchdog timer VMEchip2 1 17 2 14 2 15 write post buffer 2 9 buffer VMEchip2 ASIC 2 6 bus error interrupter VMEbus 2 19 en
102. 8 VMEbus interrupter 2 51 VMEbus slave map decoders 2 26 programming issues 1 2 programming model MCECC sector 4 10 PCCchip2 ASIC 3 11 VMEchip2 GCSR 2 100 VMEchip2 LCSR 2 20 PROM EPROM sockets 1 3 pseudo interrupt acknowledge PIACK cycles 3 8 3 32 3 33 R receive interrupt SCC 3 30 vector bits 3 33 Receive PIACK register PCCchip2 ASIC 3 33 register definitions LCSR 2 20 registers local bus map decoders 2 38 PCCchip2 ASIC 3 11 VMEbus slave map decoder 2 26 related specifications C 3 release on acknowledge ROAK mode VMEbus 2 16 release on request ROR mode VMEchip2 ASIC 2 8 reset drivers VMEbus 2 18 RESET switch enabling disabling 2 70 revision level PCCchip2 ASIC 3 14 revision register VMEchip2 2 103 ROM Control register VMEchip2 ASIC 2 51 Round Robin Select RRS arbitration mode VMEbus 2 17 S SCC interface 3 7 LTO error 1 61 offboard error 1 60 parity error 1 60 retry error 1 59 SCC Error Status register PCCchip2 ASIC 3 27 SCC Modem Interrupt Control register PCCchip2 ASIC 3 28 IN 10 Computer Group Literature Center Web Site SCC Receive Interrupt Control register PCCchip2 ASIC 3 30 SCC Transmit Interrupt Control register PCCchip2 ASIC 3 29 scrub cycle type 4 7 SCSI controller interface PCCchip2 ASIC 3 6 Error Status register PCCchip2 ASIC 3 37 ID see local SCSI ID 1 45 interface 1 16 Interrupt Control register PCCchip2 ASIC 3 38 LTO error 1 63 memory map 1
103. 80 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Enable Register bits 24 31 ADR SIZ FFF4006C 8 bits of 32 BIT 3l 30 29 28 27 26 25 24 NAME EACF EAB ESYSF EMWP EVIIE ETICI OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ETICI ETIC2 ESYSF EAB EACF Enable tick timer 1 interrupt Enable tick timer 2 interrupt Enable VMEbus IRQI edge sensitive interrupt Not used on MVMEIx7P Enable VMEbus master write post error interrupt Enable VMEbus SYSFAIL interrupt Not used on MVMEIx7P Enable VMEbus ACFAIL interrupt http www motorola com computer literature VMEchip2 Local Bus Interrupter Enable Register bits 16 23 ADR SIZ FFF4006C 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME EVIA EDMA ESIG3 ESIG2 ESIGI ESIGO ELMI ELMO OPER R W R W R W R W R W R W R W R W RESE
104. ASIC 2 52 data transfers VMEbus 2 43 2 44 DCE connections serial ports B 1 debugging packages C 1 decimal number symbol for xxiii decoders programmable 2 4 VMEchip2 2 26 devices normal address range 1 20 DFAIR bit 2 14 differences from previous boards A 1 direct mode DMAC 2 51 PCCchip2 ASIC 3 7 DMA and serial interface 1 14 transfers no address increment 2 12 DMA Controller DMAC VMEchip2 ASIC 2 10 2 51 DMAC command packets 2 52 interrupter VMEbus 2 19 LTO error 1 58 offboard error 1 58 parity error 1 57 TEA cause unidentified 1 59 VMEbus error 1 57 VMEbus requester 2 13 DMAC registers VMEchip2 ASIC MAC byte counter 2 60 MAC Control register 1 bits 0 7 2 55 MAC Control register 2 bits 0 7 2 58 MAC Control register 2 bits 8 15 2 57 DMAC local bus address counter 2 59 DMAC Status register 2 63 DMAC VMEbus address counter 2 60 Local Bus to V MEbus Requester Control register 2 54 MPU Status and DMA Interrupt Count register 2 62 PROM Decoder SRAM and DMA Control register 2 53 table address counter 2 60 VMEbus Interrupter Control register 2 61 VMEbus Interrupter Vector register 2 62 double bit error 4 6 DRAM map decoder 1 11 specifications 1 3 0512105 device 1 10 DTACK signal VMEchip2 ASIC 2 9 DTE connections serial ports B 1 dump performing 3 3 DWB bit VMEchip2 LCSR 2 8 D D D D http www motorola com computer literature IN 3 lt moz xXmoz Index E ECC
105. B CACF Clear VMEbus IRQI edge sensitive interrupt Not used on MVMEIx7P Clear VMEbus master write post error interrupt Clear VMEbus SYSFAIL interrupt Not used on MVMEIx7P Clear VMEbus ACFAIL interrupt Interrupt Clear Register bits 16 23 ADR SIZ FFF40074 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME CVIA CDMA CSIG3 CSIG2 CSIGI CSIGO CLMI CLMO OPER C C C C C C C C RESET X X X X X X X X This register is used to clear the edge sensitive interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are defined below CLMO0 CLMI CSIGO CSIG1 CSIG2 CSIG3 CDMA CVIA Clear GCSR interrupt Clear GCSR interrupt Clear GCSR SIGO interrupt Clear GCSR SIGI interrupt Clear GCSR SIG2 interrupt Clear GCSR SIG3 interrupt Clear DMA controller interrupt Clear VMEbus interrupter acknowledge interrupt 2 86 Computer Group Literature Center Web Site LCSR Programming Model Interrupt Clear Register bits 8 15 ADR SIZ FFF40074 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME CSW7 CSW6 CSW5 CSW4 CSW3 CSW2 CSWI CSWO OPER C C C C C C C C RESET X X X X X X X X This register is used to clear the edge software interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are CSWO0 CSWI CSW2 CSW3 CSW4 CSWS CSW6 CSW7 Clear software 0
106. C 3 Related Specifications Publication Document Title and Source Number VME64 Specification ANSI VITA 1 1994 VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale AZ 85260 Telephone 602 951 8866 Web http www vita com NOTE An earlier version of the VME specification is available as Versatile Backplane Bus VMEbus ANSI IEEE Institute of Electrical and Electronics Engineers Inc Standard 1014 1987 Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 http www motorola com computer literature C 3 Related Documentation Table C 3 Related Specifications Continued Bureau Central de la Commission Electrotechnique Internationale 3 rue de Varemb Geneva Switzerland Publication Document Title and Source Number OR Microprocessor system bus for 1 to 4 byte data IEC 821 BUS ANSI Small Computer System Interface 2 SCSI 2 Draft Document X3 131 198X Revision 10c Global Engineering Documents 15 Inverness Way East Englewood CO 80112 5704 X3 131 198X Rev 10c Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Global Engineering Documents Suite 400 1991 M Street NW Washington DC 20036 Telephone 1 800 854 7179 Telephone 303 397 7956 Web http global ihs com ANSI
107. Configuration Register ADR SIZ 1st FFF43008 2nd FFF43108 8 bits NAME 0 0 FSTRD 0 0 MSIZ2 MSIZ1 MSIZO OPER R R R R R R R RESET X X X X X X X X MSIZ2 MSIZ0 MSIZ2 MSIZO together define the size of the total memory to be controlled by the MCECC sector These bits reflect the RSIZ2 RSIZO bits in Defaults Register 1 MSIZ2 MSIZ1 MSIZO Memory Size MSIZ2 MSIZ1 MSIZO Memory Size 0 0 0 4MB 1 0 0 64MB 0 0 1 8MB 1 0 1 128MB 0 1 0 16MB 1 1 0 Reserved 0 1 1 32MB 1 1 1 Reserved Note Remember that the DRAM organization presented in the table above is relevant to the extent that it aids in emulating DRAM configurations from earlier programming models For the actual SDRAM device and size options now applicable to the MVME1x7P boards refer to Table 1 1 FSTRD FSTRD reflects the state of the FSTRD bit in Defaults Register 1 When 1 this bit indicates that DRAM reads are operating at full speed When 0 it indicates that DRAM read accesses are slowed by one clock cycle 4 14 Computer Group Literature Center Web Site Programming Model Base Address Register These eight bits are combined with the two most significant bits in Register 7 the next register to form BAD31 BAD22 which defines the base address of the memory For larger memory sizes the lower significant bits are ignored The bit assignments for the Base Address r
108. Counter This register reflects the current value in the prescaler counter The Prescaler counter is used with the BCLK Frequency register to produce a 1MHz clock signal for use by the refresher and by the scrubber The register is readable and writable for test purposes Programming of this register is not recommended ADR SIZ 1st FFF43030 2nd FFF43130 8 bits BIT 31 30 29 28 27 26 25 24 CPS7 CPS6 557 CPS4 CPS3 52 CPS1 CPSO OPER R wW R W R W R W R W R W R W R W RESET Scrub Time On Time Off Register ADR SIZ 1st FFF43034 2nd FFF43134 8 bits BIT 31 30 29 28 27 26 25 24 RWB7 0 STON2 STONI STONO STOFF2 STOFFI STOFFO OPER R R W R W R W R W R W R W RESET OPLS 0 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS STOFF2 STOFF0 STOFF2 STOFFO control the amount of time that the scrubber refrains from requesting use of the DRAM each time it gives it up during a scrub They control the off time as follows http www motorola com computer literature MCECC Functions STOFF2 STOFF1 STOFFO Scrubber Time Off 0 0 0 Request DRAM immediately 0 0 1 Request DRAM after 16 BCLK cycles 0 1 0 Request DRAM after 32 BCLK cycles 0 1 1 Request DRAM after 64 BCLK cycles 1 0 0 Request DRAM after 128 BCLK cycles 1 0 1 Request DRAM aft
109. EIA 232 D Standard C 4 Computer Group Literature Center Web Site Index Numerics 53C710 SCSI controller 1 15 3 6 82596CA LAN coprocessor 1 14 3 3 LAN coprocessor memory map 1 40 LANC Interrupt Control Register 3 35 A A16 D16 space VMEbus 2 37 A16 D16 space VMEchip2 ASIC 2 6 A16 D32 space VMEbus 2 37 A16 D32 space VMEchip2 ASIC 2 6 A24 D16 space VMEbus 2 37 2 51 A24 D16 space VMEchip2 ASIC 2 6 A32 D16 space VMEbus 2 37 2 51 A32 D16 space VMEchip2 ASIC 2 6 ABORT switch interrupt address 1 18 AC Fail interrupter VMEbus 2 19 access cycles VMEbus 2 33 access timer VMEbus 2 7 ACFAIL signal line 2 19 2 96 adder in address translation 2 31 2 32 2 35 adders VMEchip2 2 27 address GCSR VMEchip2 1 46 2 100 LCSR VMEchip2 2 20 VMEbus resources 2 37 address counter VMEbus 2 13 address modifier codes 2 43 2 44 codes DMAC 2 58 register VMEbus slave 2 38 select bits 2 33 2 36 address range devices 1 20 local bus 2 39 address translation address register 2 38 address register slave map decoder 2 27 registers 2 38 registers slave map decoder 2 27 select register 2 38 select register slave map decoder 2 27 address translation registers slave map decoder 2 27 addresses PCCchip2 ASIC 3 11 SCC status and control registers PCCchip2 ASIC 3 27 addressing capabilities local bus to VMEbus interface 2 4 VMEbus to local bus interface 2 9 VMEchip2 DMAC 2 11 alternate address register
110. EVEL MASK LEVEL 1362 9403 lt _ This sheet begins on facing page http www motorola com computer literature 3 13 PCCchip2 Chip ID Register The Chip ID Register is located at FFF42000 It is an 8 bit read only register that is hard wired to a hexadecimal value of 20 Writes to this register are ignored however the PCCchip2 always terminates the cycles properly with TA ADR SIZ FFF42000 8 bits BIT 31 30 29 28 27 26 25 24 NAME CID7 CID6 CID5 CID4 CID3 CID2 CID1 CIDO OPER R R R R R R R R RESET 0 0 1 0 0 0 0 0 Chip Revision Register The Chip Revision Register is located at FFF42001 It is an 8 bit read only register that is hard wired to reflect the revision level of the PCCchip2 ASIC The current value of this register is 00 Writes to this register are ignored however the PCCchip2 always terminates the cycles properly with TA ADR SIZ FFF42001 8 bits BIT 23 22 21 20 19 18 17 16 NAME REV7 REV6 REVS REV4 REV3 REV2 REVI REVO OPER R R R R R R R R RESET 0 0 0 0 0 0 0 0 Computer Group Literature Center Web Site Programming Model General Control Register The General Control Register is located at FFF42002 It is an 8 bit register that controls chip general functions The Master Interrupt Enable bit MIEN must be set high for any interrupts from the PCCchip2 to be asserted to the processor
111. Ebus interface option This bit is duplicated at the same bit position in the MC2 chip at location FFF42044 When this bit or the duplicate bit in the MC2 chip is high the RESET switch is enabled When both bits are low the RESET switch is disabled When this bit is high the VMEchip2 asserts the BRDFAIL signal pin When this bit is low this bit does not contribute to the BRDFAIL signal on the VMEchip2 When this bit is set high the powerup reset status bit is cleared This bit is always read 0 This bit is set by a powerup reset It is cleared by a write to the CPURS bit When this status bit is high the BRDFAIL signal pin on the VMEchip2 is asserted When this status bit is low the BRDFAIL signal on the VMEchip2 is not asserted The BRDFAIL pin may be asserted by an external device the BDFLO bit in this register or a watchdog time out When this status bit is high the SYSFAIL signal line on the VMEbus is asserted When this status bit is low the SYSFAIL signal line on the VMEbus is not asserted When this status bit is high the VMEchip2 is configured as system controller When this status bit is low the VMEchip2 is not configured as system controller 2 70 Computer Group Literature Center Web Site LCSR Programming Model Watchdog Timer Control Register ADR SIZ BIT 23 FFF40060 8 bits of 32 21 20 19 18 17 16 NAME SRST WDCS WDCC WDTO WDBFE WDS L WDRSE WDEN
112. Error Conditions DMAC TEA Cause Unidentified Description MPU Notification Status Comments SCC Retry Error Description MPU Notification Status Comments An error occurred while the DMAC was Local Bus master and additional status was not provided DMAC interrupt when enabled The DLBE bit is set in the DMAC Status register address FFF40048 bit 6 An 8 or 16 bit write to the LCSR in the VMEchip2 causes this error If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access Local Bus Retry occurred due to VMEbus Dual Port Lock or LAN wanted Bus while the SCC was Local Bus master SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2 SCC Error Status register 6FFF4201C The DMA controllers in the SCC should not be programmed to access the VMEbus Refer to the Serial Port Interface section in this chapter SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2 http www motorola com computer literature 1 59 Programming Issues SCC Parity Error Description MPU Notification Status Comments SCC Offboard Error Description MPU Notification Status Comments
113. F Reserved es 128KB 6 FFFA0000 SFFFBFFFF Reserved 128KB 5 FFFC0000 SFFFCFFFF 48 58 BBRAM TOD D32 D8 64KB 1 Clock FFFD0000 FFFDFFFF Reserved 64KB 5 FFFE0000 FFFEFFFF Reserved 64KB 2 http www motorola com computer literature 1 23 Programming Issues Notes 1 For a complete description of the register bits refer to the data sheet for the specific chip For a more detailed memory map refer to the following detailed peripheral device memory maps On the MVMEIXTP this area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal Byte reads should be used to read the interrupt vector These locations do not respond when an interrupt is not pending If the local bus timer is enabled the access times out and is terminated by a TEA signal Writes to the LCSR in the VMEchip2 must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal This area does return an acknowledge signal Size is approximate Port commands to the 82596CA must be written as two 16 bit writes upper word first and lower word second The CD2401 appears repeatedly from FFF4
114. F40088 8 of 32 bits Base register 0 by writing to bits 28 31 Refer to the Vector Base Register description and to Table 2 4 Local Bus Interrupter Summary in Chapter 2 6 Interrupt Level register 1 Write desired level of Tick Timer 1 interrupt to bits 0 2 bits 0 7 FFF40078 8 of 32 bits 7 Local Bus Interrupter Set bit 24 ETIC1 to 1 to enable Tick Timer 1 interrupts Enable register FFF4006C 8 of 32 bits 8 I O Control Register 1 Write a 1 to bit 23 to enable interrupts from the FFF40088 8 of 32 bits VMEchip2 A 0 masks all interrupts from the VMEchip2 1 48 Computer Group Literature Center Web Site Cache Coherency MVME167P Periodic Tick Timer 1 interrupts now occur so you need an interrupt handler Section 3 gives the details as follows 3 Set up an interrupt handler routine Step Your interrupt handler should include the following features Action and Reference 1 Be sure the MC680x0 Vector Base register is set up Set the proper MC680x0 exception vector location so the processor vectors to your interrupt handler location You can determine the proper exception vector location to set from the MC680x0 Vector Base register the VMEchip2 Base register and Table 2 4 Local Bus Interrupter Summary in Chapter 2 from which you can determine the actual interrupt vector given on a Tick Timer 1 interrupt Lower the MC680x0 mask so the interrupt level you programmed is accepted The interrupt handler itself s
115. FAULTS2 RWB7 REFDIS TVECT NOCACHE RESST2 RESST1 RESSTO 7C SDRAM SDCFG2 SDCFGI SDCFGO CONFIG 4 12 Computer Group Literature Center Web Site Programming Model Chip ID Register The Chip ID register is hard wired to a hexadecimal value of 87 The Petra MCECC sector can be given a software reset by writing a value of 0F to this register This write is terminated properly with TA and sets most internal registers to their default power up state Although writes of any value other than 0F to this register are ignored the MCECC sector always terminates the cycles properly with TA ADR SIZ 1st FFF43000 2nd FFF43100 8 bits BIT 31 30 29 28 27 26 25 24 NAME 7 CID6 CID5 CID4 CID3 CID2 CID1 CIDO OPER R R R R R R R RESET X X X X X X X X Chip Revision Register The Chip Revision register is hard wired to reflect the revision level of the Petra MCECC ASIC The current value of the register is 07 Although writes to this register are ignored the MCECC sector pair always terminates the cycles properly with TA ADR SIZ 1st FFF43004 2nd FFF43104 8 bits BIT 31 30 29 28 27 26 25 24 NAME REV7 REV6 REVS REV4 REV3 REV2 REVI REVO OPER R R R R R R R RESET X X X X X X X X http www motorola com computer literature 4 13 MCECC Functions Memory
116. FFFF and an A32 D16 space at F 1000000 to FF7FFFFF Supervisor non privileged and program data space is determined by attribute bits Write posting may be enabled or disabled for each decoder I O space and this map decoder may be enabled or disabled When write posting is enabled the VMEchip2 stores the local bus address and data and then acknowledges the local bus master The local bus is then free to perform other operations while the VMEbus master requests the VMEbus and performs the requested operation The write post buffer stores data in single byte double byte quad byte or one cache line four quad bytes form Write posting should only be enabled when bus errors are not expected If a bus error is returned on a write posted cycle and the interrupt is enabled the local processor is interrupted The address of the error is not saved Normal memory never returns a bus error on a write cycle However some VMEbus ECC memory cards perform a read modify write operation and therefore may return a bus error if there is an error on the read portion of a read modify write Write posting should not be enabled when this type of memory card is used Also memory should not be sized using write operations if write posting is enabled I O areas that have holes should not be write posted if software may access non existent memory Using the programmable map decoders write posting can be enabled for safe areas and disabled for areas which are
117. I6 ADDR CNTR 54 SCRUB SACI5 SAC14 SACI3 SACI2 SACII SACIO 9 SAC8 ADDR CNTR 58 SCRUB SAC7 SAC6 SACS SACA 0 0 0 0 ADDR CNTR 5C ERROR ERRLO ERD ESCR ERA EALT 0 MBE SBE LOGGER G B 60 ERROR EA31 EA30E EA29 EA28 EA27 EA26 EA25 EA24 ADDRESS 64 ERROR EA23 EA22 EA21 EA20 EAI9 EA18 EAI17 EA16 ADDRESS 68 ERROR 15 14 EA13 EA12 EA10 EA9 8 ADDRESS 6C ERROR EA7 EA6 EAS EA4 0 0 0 0 ADDRESS 70 ERROR S7 S6 S5 54 53 S2 SI SO SYNDROME 74 DEFAULTS1 WRHDI STATC FSTR SELII SELIO RSIZ2 RSIZI RSIZO S OL D 78 DEFAULTS2 FRCO XY FL REFDI TVEC NOCAC RESST RESST RESSTO PN IP S T HE 2 1 http www motorola com computer literature 1 35 Programming Issues Table 1 9 Cirrus Logic CD2401 Serial Port Memory Map Base Address FFF45000 Register Description Register Offsets Size Access Name Global Registers Global Firmware Revision Code Register GFRCR 81 B R Channel Access Register CAR EE B R W Option Registers Channel Mode Register CMR 1B B R W Channel Option Register 1 CORI 10 B R W Channel Option Register 2 COR2 17 B R W Channel Option Register 3 COR3 16 B R W Channel Option Register 4 COR4 15 B R W Channel Option Register 5 5 14 R W Channel Option Register 6 COR6 18 B R W Channel Option Register 7 COR7 07 B R W Special Character Register 1 SCHRI 1F B R W Async Special Character Register 2 SCHR2 1E B R W Async Special Character Regist
118. IC TIMER 1 INT IRQ LEVEL INT ICLR IRQ LEVEL E itd gt SCC TRANSMIT SCC SCC jn ied ud SCC RECEIVE IRQ IEN AVEC IRQ LEVEL 501 360 IEN avec IRQ LEVEL SCC MODEM PIACK SCC RECEIVE PIACK LAN LAN LAN LAN LAN LAN INT LAN LAN id LAN ERR BET ips INT IEN IRQ LEVEL sci sco NT EN AGL IRQ LEVEL SCSI SCSI SCSI INT IRQ IEN IRQ LEVEL PRTR PRTR PRTR PRTR PRTR PRTR SEL PRTR PRTR PRTR PRTR PRTR PRTR PE SEL SEL SEL SEL SEL IRQ LEVEL PE PE PE PE PE IRQ LEVEL PLTY INT IEN PLTY E L INT IEN ICLR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR ANY ACK FLT SEL PE BSY DAT INP FAST INT ENBL ASTB STB PRINTER DATA INTERRUPT INTERRUPT IPL LEVEL MASK LEVEL 1362 9403 lt _ This sheet begins on facing page http www motorola com computer literature 1 33 Programming Issues Table 1 8 MCECC Internal Register Memory Map MCECC Base Address FFF43000 1st F FF43100 2nd Register Register Register Bit Names Offset Name D31 030 D29 D28 D27 D26 D25 D24 00 CHIP ID CID7 CID5 CID5 CID4 CID3 CID2 CID1 CIDO 04 CHIP REV7 REV6 REV5 REV4 REV3 REV2 REVI REVO REVISION 08 MEMORY 0 0 FSTR 1 0 MSIZ2 MSIZI MSIZO CONFIG D 0C DUMMY 0 0 0
119. ME1X7P Serial Port 1 Config i B 6 M Figure r literature motorola com compute W http www Printer and Serial Port Connections 5056 5951 4 4 p 4 1 I ii 1 1 1 i i 71 1 I 2750 foo 9 8 819 90vS LOW T 8 1 1 x aoa 5 i 90PSPLOW i du gt a OXY 1820 se i 90 SP LOW TUNE 1 1 d i T i i i 1 I 1 I 1 1 i i i i I T 1 1 1 1 I ik 1 I 1 d 1 T 1 4 iui Siu i i 1620 65 907SPLON I 0 i d 159 09 90vSv LOW Te EET 0 sun Nga reo n 1 1 quvo
120. MEbus IRQ7 interrupt SPARE 2 84 Computer Group Literature Center Web Site LCSR Programming Model Software Interrupt Set Register bits 8 15 ADR SIZ FFF40070 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SSW7 SSW6 SSW5 SSW4 SSW3 SSW2 SSWI1 SSWO OPER 5 5 5 5 5 5 5 5 RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is used to set the software interrupts An interrupt is set by writing a 1 to it The software interrupt set bits are SSWO0 SSWI SSW2 SSW3 SSW4 SSWS SSW6 SSW7 Set software 0 interrupt Set software 1 interrupt Set software 2 interrupt Set software 3 interrupt Set software 4 interrupt Set software 5 interrupt Set software 6 interrupt Set software 7 interrupt Interrupt Clear Register bits 24 31 ADR SIZ FFF40074 8 bits of 32 BIT 3l 30 29 28 27 26 25 24 NAME CAB CSYSF CMWP CPE CTIC2 CTICI OPER C C C C C C C C RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is used to clear the edge sensitive interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are defined below CTIC2 Clear tick timer 1 interrupt Clear tick timer 2 interrupt http www motorola com computer literature 2 85 VMEchip2 CMWP CSYSF CA
121. MEchip2 includes an on chip map decoder that allows software to configure the global addressing range of onboard resources The decoder allows the local address range to be partitioned into two separate banks each with its own start and end address in increments of 64KB as well as setting each bank s address modifier codes write post enable and snoop enable http www motorola com computer literature 2 9 VMEchip2 Each map decoder includes an alternate address register and an alternate address select register These registers allow any or all of the upper 16 VMEbus address lines to be replaced by signals from the alternate address register This allows the address of local resources to differ from their VMEbus address The alternate address register also provides the upper eight bits of the local address when the VMEbus slave cycle is A24 The ocal bus master requests the local bus and executes cycles as required To reduce local bus loading and improve performance it always attempts to transfer data using a burst transfer as defined by the MC680x0 When snooping is enabled the local bus master requests the cache controller in the MC680x0 to monitor the local bus addresses Local Bus to VMEbus DMA Controller The DMA Controller DMAC operates in conjunction with the local bus master the VMEbus master and a 16 four byte FIFO buffer The DMA controller has a 32 bit local address counter 32 bit table address counter a 32
122. MVME167P and MVME177P single board computers include many resources for the local processor These include tick timers software programmable hardware interrupts a watchdog timer and a local bus timeout Programmable Tick Timers Four 32 bit programmable tick timers with lus resolution are available two in the VMEchip2 ASIC and two in the PCCchip2 ASIC The tick timers may be programmed to generate periodic interrupts to the processor Refer to Chapter 2 VMEchip2 and Chapter 3 PCCchip2 respectively for detailed programming information Computer Group Literature Center Web Site Functional Description Watchdog Timer The VMEchip2 ASIC supplies a watchdog timer function When enabled the watchdog timer must be reset by software within the programmed interval or it times out The watchdog timer can be programmed to generate a SYSRESET signal local reset signal or a board fail signal if it times out Refer to Chapter 2 VM Echip2 for detailed programming information Software Programmable Hardware Interrupts The VMEchip2 ASIC supplies eight software programmable hardware interrupts These interrupts allow software to create a hardware interrupt Refer to Chapter 2 VM Echip2 for detailed programming information Local Bus Timeout The MVME167P and MVME177P single board computers provide a timeout function in the VMEchip2 ASIC for the Local Bus When the timer is enabled and a Local Bus access times out a Transfer Error
123. MVME1X7P Single Board Computer Programmer s Reference Guide V1X7PA PG1 Edition of October 2000 Copyright 2000 Motorola Inc All rights reserved Printed in the United States of America Motorola and the Motorola logo are registered trademarks of Motorola Inc MC68040 M and MC68060 are trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cab
124. PS3 CPS2 CPS1 CPSO PRESCALE 34 SCRUB TIME SRDIS 0 STON2 STONI STONO STOFF2 STOFF1 SRDIS ON OFF 38 SCRUB 0 0 SPS21 SPS20 SPS19 SPS18 SPS17 SPS16 PRESCALE 3C SCRUB SPS15 SPS14 SPS13 SPS12 SPS11 SPS10 SPS9 SPS85 PRESCALE http www motorola com computer literature 4 11 MCECC Functions Table 4 3 MCECC Sector Internal Register Memory Map Continued MCECC Sector Base Address FFF43000 1st board SFFF43100 2nd board Register Register Bit Names Offset Name D31 D30 D29 D28 D27 D26 D25 D24 40 SCRUB SPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPS1 SPSO PRESCALE 44 SCRUB 115 114 ST13 ST12 STII STIO ST9 ST8 TIMER 48 SCRUB ST7 ST6 STS ST4 ST3 ST2 STI STO TIMER 4C SCRUB 0 0 0 0 0 SAC26 SAC25 SAC24 ADDR CNTR 50 SCRUB SAC23 SAC22 5 21 SAC20 5 19 SACI8 SACI7 SAC16 ADDR CNTR 54 SCRUB 15 14 5 SACI2 SACII SACIO 5 9 SAC8 ADDR CNTR 58 SCRUB SAC7 SAC6 SACS SAC4 07 0 0 0 ADDR CNTR 5C ERROR ERRLOG ERD 5 ERA EALT 0 MBE SBE LOGGER 60 ERROR EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 ADDRESS 64 ERROR EA23 EA22 EA21 EA20 19 18 17 16 ADDRESS 68 ERROR 15 14 13 12 11 10 9 EA8 ADDRESS 6C ERROR EA7 EA6 EAS EA4 07 0 0 0 ADDRESS 70 ERROR S7 S6 S5 S4 S3 S2 1 SO SYNDROME 74 DEFAULTS RWB7 RWB6 FSTRD SELII SELIO RSIZ2 RSIZ1 RSIZO 78 DE
125. Parity Error detected while the SCC was reading DRAM SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2 SCC Error Status register SFFFA201C SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2 Error encountered while the SCC was attempting to go to the VMEbus SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2 SCC Error Status register SFFFA201C SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2 1 60 Computer Group Literature Center Web Site Error Conditions SCC LTO Error Description MPU Notification Status Comments LAN Parity Error Description MPU Notification Status Comments LAN Offboard Error Description MPU Notification Status Comments Local Bus Time out occurred while the SCC was Local Bus master SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2 SCC Err
126. Processor The base address for the 53C710 is FFF47000 When the PCCchip2 detects low a level on the IRQ line from the 53C710 if such interrupts are enabled it generates an interrupt to the MPU If the C040 bit is set the interrupt request goes to the MPU via the EIPL pins at the level that is programmed for SCSI interrupts in the SCSI Interrupt Control Register If the C040 bit is cleared the interrupt goes to the MPU via the INT pin if the level that is programmed for SCSI interrupts in the SCSI Interrupt Control Register is higher than the level set in the Interrupt Mask Level Register Parallel Port Interface The PCCchip2 provides an 8 16 bit bidirectional parallel port All eight or sixteen bits of the port must be either inputs or outputs no individual selection In addition to the 8 16 bits of data there are two control pins and five status pins Each of the status pins can generate an interrupt to the MPU in any of the following programmable conditions high level low level high to low transition or low to high transition This port may be used as a parallel printer port or as a general parallel I O port When used as a parallel printer port the five status pins function as Printer Acknowledge ACK Printer Fault FAULT Printer Busy BSY Printer Select SELECT and Printer Paper Error PE while the control pins act as Printer Strobe STROBE and Input Prime INP The PCCchip2 provides an auto strobe
127. R R RESET 0 5 OPLS OPLS OPLS OPLS OPLS OPLS 5 56 50 Bits SYNDROME6 0 reflect the syndrome value at the last logging of an error The seven bit code indicates the position of the data error When all the bits are 0 there is no error Note that if the logged error was non correctable then these bits are meaningless refer to the Syndrome Decoding section ADR SIZ 1st FFF43074 2nd FFF43174 8 bits BIT 31 30 29 28 27 26 25 24 NAME RWB7 RWB6 FSTRD SELII SELIO RSIZ2 RSIZ1 RSIZO OPER R W R W R W R W 0 PL V PLS VPLS V PLS V PLS V PLS VPLS V PLS It is not recommended that non test software write to this register 5172 5170 Bits RSIZ2 RSIZO determine the size of the DRAM array that is assumed by the MCECC They control the size as follows 4 30 Computer Group Literature Center Web Site Programming Model RSIZ2 RSIZ1 RSIZO DRAM Array Size 0 0 0 4MB 0 0 1 8MB 0 1 0 16MB 0 1 1 32MB 1 0 0 64MB 1 0 1 128MB 1 1 0 Reserved 1 1 1 Reserved The states of RSIZ2 0 after reset power up soft or local match those of the RSIZ2 0 bits from the reset serial bit stream SELI1 SELIO The SELI1 SELIO control bits determine the base address at which the control and status registers respond as shown below SELI1 SELIO Register Base Address
128. S DCD TXD RTS and DTR It also interfaces to the synchronous clock signal lines Refer to Appendix C Related Documentation for drawings of the serial port interface connections All four serial ports use EIA 232 D drivers and receivers located on the main board and all the signal lines are routed to the I O connector The configuration headers are located on the main board and may be on some transition boards An external I O transition board is necessary to convert the I O connector pinout to industry standard connectors Note MVMEIXT7P board hardware ties the DTR signal from the CD2401 to the pin labeled RTS at connector P2 Likewise RTS from the CD2401 is tied to DTR on P2 Therefore when programming the CD2401 assert DTR when you want RTS and RTS when you want DTR both MVMEI67P and MVME177P boards the interface provided by the PCCchip2 allows the 16 bit CD2401 serial controller chip to appear at contiguous addresses Accesses to the CD2401 however must be 8 or 16 bits 32 bit accesses are not permitted Refer to the CD2401 data sheet and to Chapter 3 PCCchip2 for detailed programming information http www motorola com computer literature 1 13 Programming Issues The CD2401 supports DMA operations to local memory Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions the CD2401 DMA controllers should not be programmed to access the VMEbus The hardware does no
129. SDRAM SCSI and Ethernet MVME167PA 36SE MVME177PA 54SE 33MHz MC68040 64MB SDRAM SCSI and Ethernet 50MHz MC68060 16MB SDRAM SCSI and Ethernet MVMEI77PA 55SE 50MHz MC68060 32MB SDRAM SCSI and Ethernet MVME177PA 56SE 50MHz MC68060 64MB SDRAM SCSI and Ethernet MVME177PA 64SE 60MHz MC68060 16MB SDRAM SCSI and Ethernet MVME177PA 65SE 60MHz 68060 32MB SDRAM SCSI and Ethernet MVME177PA 66SE 60MHz MC68060 64MB SDRAM SCSI and Ethernet MVME177PA 67SE 60MHz MC68060 128MB SDRAM SCSI and Ethernet This manual is intended for anyone who designs OEM systems adds capability to an existing compatible system or works in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed To use this manual you may also wish to become familiar with the publications listed in Appendix C Related Documentation Overview of Contents Chapter 1 Programming Issues describes the board level hardware features of MVMEIXT7P single board computers It includes memory maps and a discussion of some general software considerations such as cache coherency interrupts and bus errors Chapter 2 VMEchip2 describes the VMEchip2 ASIC the local bus VMEbus interface chip on MVME1X7P boards Chapter 3 PCCchip2 describes the PCCchip2 ASIC The PCChip2 is a peripheral channel controller designed to interface an MC680x0 compatible local bus to var
130. STER AM 3 EN EN EN EN GCSR MAST MAST MAST MAST 1 2C GCSR GROUP SELECT BOARD SELECT E 2 di 31 30 29 25 24 23 22 21 20 19 18 17 16 WAIT ROM DMA TB SRAM 30 RMW ZERO SNP MODE SPEED 34 38 DMA CONTROLLER 3C DMA CONTROLLER 40 DMA CONTROLLER 44 DMA CONTROLLER TICK TICK CLR IRQ VMEBUS 48 p 2A n IRQ STAT INTERRUPT VMEBUS INTERRUPT VECTOR LEVEL This sheet continues on facing page gt 1 26 Computer Group Literature Center Web Site Memory Maps 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER SNP WP SUP USR A32 A24 Dod BLK PRGM DATA 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST MAST 016 MASTER 2 016 1 EN EN EN 02 102 01 101 lO1 107 ROM ROM BANK B ROM BANK A EN we su po EN 016 WP sw SIZE SPEED SPEED EN EN EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARB MAST MAST MST MST MASTER DMA DMA DMA DMA DM DMA ROBN DHB DWB FAIR RWD VMEBUS HALT EN TBL FAIR RELM VMEBUS DMA DMA LB DMA DMA DMA DMA DMA
131. Scrub Timer counter and reads to this address yield the counter s value The ability to read and write this register is provided for test purposes Programming this counter is not recommended This register reflects the current value in the Scrub Timer counter bits 15 8 ADR SIZ 1st FFF43044 2nd FFF43144 8 bits BIT 31 30 29 28 27 26 25 24 NAME 5 15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 OPER R W R W R W R W R W R W R W R W RESET OPLS 8 OPLS OPLS OPLS OPLS OPLS 0PLS 4 24 Computer Group Literature Center Web Site Programming Model Scrub Timer Counter Bits 7 0 This register reflects the current value in the Scrub Timer counter bits 7 0 ADR SIZ 1st FFF43048 2nd FFF431468 8 bits BIT 31 30 29 28 27 26 25 24 ST7 ST6 ST5 ST4 ST3 ST2 STI STO OPER R wW R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0PLS Scrub Address Counter Bits 26 24 This read write register is the Scrub Address counter Each time the scrubber performs a scrub memory cycle the Scrub Address counter increments For an entire scrub the Scrub Address counter starts at 0 and increments until it reaches the DRAM size that is indicated by the MEMSIZ pins Writes to this address update the Scrub Address counter reads to this address yield the value in the counter The ability to read and write this counter is
132. T OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ELMO ELMI ESIGO ESIG1 ESIG2 ESIG3 EDMA EVIA Enable GCSR interrupt Enable GCSR interrupt Enable GCSR SIGO interrupt Enable GCSR SIGI interrupt Enable GCSR SIG2 interrupt Enable GCSR SIG3 interrupt Enable DMAC interrupt VMEbus interrupter acknowledge interrupt 2 82 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Enable Register bits 8 15 ADR SIZ FFF4006C 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME ESW7 ESW6 ESW5 ESW4 ESW3 ESW2 ESWI ESWO OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary
133. T3 CTEST2 CTESTI CTESTO 14 18 CTEST7 CTEST6 CTEST5 CTEST4 18 20 LCRC 8 ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER 3C Note Accesses may be 8 bit or 32 bit but not 16 bit BBRAM TOD Clock Memory Map The M48T58 BBRAM also called Non Volatile RAM or NVRAM is divided into six areas as shown in Table 1 12 The first five areas are defined by software while the sixth area the time of day TOD clock is defined by the chip hardware The first area is reserved for user data The second area is used by Motorola networking software The third area may be used by an operating system The fourth area is http www motorola com computer literature 1 41 Programming Issues used by the MVME1X7P board debugger MVMEIX7Bug The fifth area detailed in Table 1 13 is the configuration area The sixth area the TOD clock detailed in Table 1 14 is defined by the chip hardware Table 1 12 M48T58 BBRAM TOD Clock Memory Map Address Range Description Size Bytes 0000 FFFCOFFF User Area 4096 FFFC1000 FFFC10FF Networking Area 256 FFFC1100 FFFC16F7 Operating System Area 1528 FFFC16F8 FFFC1EF7 Debugger Area 2048 FFFC1EF8 SFFFCIFF7 Configuration Area 256 FFFC1FF8 SFFFCIFFF TOD Clock 8 Table 1 13 BBRAM Configuration Area Memory Map
134. This segment may be enabled using the enable bit Write posting may be enabled using the write post enable bit The local bus map decoders should not be programmed such that more than one map decoder responds to the same local bus address or a map decoder conflicts with on board resources You may however program the map decoders to allow a VMEbus address to be accessed from more than one local bus address Local Bus Slave VMEbus Master Ending Address Register 1 ADR SIZ FFF40014 16 bits of 32 BIT 31 16 Ending Address Register 1 OPER R W RESET 0 PS This register is the ending address register for the first local bus to VMEbus map decoder http www motorola com computer literature 2 39 VMEchip2 Local Bus Slave VMEbus Master Starting Address Register 1 ADR SIZ FFF40014 16 bits of 32 BIT 15 0 NAME Starting Address Register 1 OPER R W RESET 0 PS This register is the starting address register for the first local bus to VMEbus map decoder Local Bus Slave VMEbus Master Ending Address Register 2 ADR SIZ FFF40018 16 bits of 32 BIT 31 Bn 16 NAME Ending Address Register 2 OPER R W RESET 0 PS This register is the ending address register for the second local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 2 ADR SIZ FFF40018 16 bits of 32 BIT 15 m 0 NAME St
135. VFAIR LVRWD LVREQL OPER R W R R W R W R W R W RESET OPS OPS 0 PSL OPS OPS 0 PS This register controls the VMEbus request level the request mode and release mode for the local bus to V MEbus interface LVREQL These bits define the VMEbus request level The request level can only change while the VMEchip2 is bus master The VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect If the VMEchip2 is bus master when the level is changed the new level does not take effect until the bus has been released and re requested at the old level The requester always requests the VMEbus at level 3 the first time following a SYSRESET 2 54 Computer Group Literature Center Web Site LCSR Programming Model LVRWD LVFAIR DWB DHB ROBN The request level is 0 The request level is 1 The request level is 2 The request level is 3 When this bit is high the requester operates in release when done mode When this bit is low the requester operates in release on request mode When this bit is high the requester operates in fair mode When this bit is low the requester does not operate in fair mode In fair mode the requester waits until the request signal line for the selected level is inactive before requesting the VMEbus When this bit is high the VMEchip2 requests the VMEbus and does not release it When this bit is low the VMEchip2 rel
136. Y BSY BSY BSY PLTY E L INT IEN ICLR 38 CHIP SPEED 3C SCC PROVIDES ITS OWN VECTORS This sheet continues on facing page 3 12 Computer Group Literature Center Web Site Programming Model D15 D8 D7 DO CPU FAST DRO 040 Nr BRAM VECTOR BASE REGISTER COMPARE REGISTER COUNTER REGISTER COMPARE REGISTER COUNTER REGISTER OVERFLOW Bae SEN OVERFLOW NE NEA COUNTER 2 A COUNTER 1 1 1 1 TIC2 TIC2 TIC2 TIC TIMER 2 TIC TIC TIMER 1 INT IEN IRQ LEVEL INT IRQ LEVEL id sco SCC TRANSMIT scc scc Sog 906 pos SCC RECEIVE IRQ AVEC 801 SCO IEN avec IRQLEVEL SCC MODEM PIACK SCC RECEIVE PIACK LAN LAN LAN LAN LAN LAN INT LAN LAN th ee EN LAN ERR INT INT Bury INT IEN ICLR IRQ LEVEL sci sco WT IRQ LEVEL SCSI SCSI SCSI INT IRQ IEN IRQ LEVEL PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR SEL SEL SEL SEL SEL IRQ LEVEL PE PE PE PE PE IRQ LEVEL PLTY E L INT IEN ICLR PLTY E L INT IEN ICLR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR ANY ACK FLT SEL PE BSY DAT INP FAST INT ENBL ASTB STB PRINTER DATA INTERRUPT INTERRUPT IPL L
137. Z FFF4201C 8 bits BIT 31 30 29 28 27 26 25 24 NAME RTRY PRTY EXT LTO SCLR OPER R R R R W R 0 RESET 0 0 0 0 PL 0 PL 0 PL 0 PL 0 SCLR Writing a 1 to this bit clears bits 25 through 28 LTO EXT PRTY and RTRY Reading this bit always yields 0 These bits indicate the status of the last Local Bus error condition encountered by the SCC while performing accesses to the Local Bus A Local Bus error condition is flagged by the assertion of TEA When the SCC receives TEA if the source of the error is local time out then LTO is set and EXT PRTY and RTRY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other three status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other three status bits are cleared If the source of the TEA is because a retry was needed then RTRY is set and the other three status bits are cleared If the source of the error is none of the above conditions then all four bits are cleared Writing a 1 to bit 24 SCLR also clears all four bits http www motorola com computer literature 3 27 PCCchip2 SCC Modem Interrupt Control Register ADR SIZ BIT FFF4201D 8 bits 21 20 19 18 17 16 NAME IRQ IEN AVEC IL2 IL1 ILO OPER R R W R W R W R W R W RESET X 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO AVEC IEN IRQ Interrupt Requ
138. a gvo quvog NOILISNVHL QNOO Had VOY ZANAN 10 99 i Zd dZZLV3WANW 4 9 E3INAW NC ROSCIUS HE et ee TEN nl DM AES ev RD pact Po derrotar rm pacer E eel Sen reel Figure B 7 MVME1X7P Serial Port 2 Configured as DTE Computer Group Literature Center Web Site B 8 Connection Diagrams 5096 PSEL C ee ea eee Tt ig IEEE EO EON I I 1 ik o vow 1 810 EZ a gg 910 90PSPLON 8 1 1 1 gt 42 dod E er 9 90 Sv LOIN d6 e gt gt lt 4 gt zaxa 102 9 i 90vSvLOW ET ano I M 1 1 1 1 l 1 1 af 1 1 1 I 1 i M 1 1 I 1 I
139. a level select register an enable bit a status bit a clear bit and a set bit for the software interrupts Each interrupter also provides a unique interrupt vector to the processor The upper four bits of the vector are programmable in the vector base registers The lower four bits are unique for each interrupter There are two base registers one for the first 16 interrupters and one for the next 8 interrupters The VMEbus interrupters provide their own vectors A summary of the interrupts appears in Table 2 4 The status bit of an interrupter is affected by the enable bit If the enable bit is low the status bit is also low Interrupts may be polled by setting the enable bit and programming the level to 0 This enables the status bit and prevents the local bus from being interrupted The enable bit does not clear edge sensitive interrupts If necessary edge sensitive interrupts should be cleared in order to remove any old interrupts and then re enabled The master interrupt enable MIEN bit must be set before the VMEchip2 can generate any interrupts The MIEN bit is in I O Control Register 1 Computer Group Literature Center Web Site LCSR Programming Model Table 2 4 Local Bus Interrupter Summary Vector UN VMEbus IRQI External Lowest VMEbus IRQ2 External A VMEbus IRQ3 External VMEbus IRQ4 External VMEbus 5 External VMEbus IRQ6 Ext
140. able bits 2 39 enabling 2 32 2 35 2 43 2 44 2 50 2 51 register 2 32 Register 2 2 31 Address Translation Select Register 1 2 30 Address Translation Select Register 2 2 31 Ending Address Register 1 2 28 Ending Address Register 2 2 29 GCSR Board Address Register 2 48 GCSR Group Address Register 2 47 Starting Address Register 1 2 28 Starting Address Register 2 2 29 Write Post and Snoop Control Register 1 2 35 Write Post and Snoop Control Register 2 2 32 VMEbus to local bus interface 1 18 2 9 VMEchip2 ASIC 1 12 BERR signal 1 55 block diagram 2 5 features 2 1 functional blocks 2 4 functional description 2 4 GCSR programming model 2 100 programming model 2 20 watchdog timer function 1 17 VMEchip2 Petra chip redundancies 1 18 timer VMEchip2 ASIC 2 7 write posting VMEchip2 ASIC 2 6 2 9 http www motorola com computer literature IN 13 lt moz Index IN 14 Computer Group Literature Center Web Site
141. ace 153 bytes is reserved This pads the structure to an even 256 bytes System specific items such as size of system side and systems side version may go here http www motorola com computer literature 1 45 Programming Issues 15 The final byte of the area is reserved for a checksum as defined in the Debugging Package User s Manual for MVME167Bug and MVME177Bug and the Debugging Package for Motorola 68K CISC CPUs User s Manual for security and data integrity of the configuration area of the NVRAM This data is stored in hexadecimal format Interrupt Acknowledge Map The local bus distinguishes interrupt acknowledge cycles from other cycles by placing the binary value 11 on TT1 TTO It also specifies the level that is being acknowledged using TM2 TMO The interrupt handler selects which device within that level is being acknowledged VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters Default addresses for the slave master and GCSR address decoders are provided by the ENV command VMEbus Accesses to the Local Bus The VMEchip2 includes a user programmable map decoder for the VMEbus to local bus interface The map decoder allows you to program the starting and ending address and the modifiers to which the MVMEIX7P responds VMEbus Short I O Memory Map The VMEchip2 includes a user programmable map decoder for the GCSR The GCSR map decoder allows you to program the
142. al Purpose Control and Status register 2 A 14 General Purpose Control and Status register 3 C 18 General Purpose Control and Status register 4 E General Purpose Control and Status register 5 1 30 Computer Group Literature Center Web Site Memory Maps Table 1 6 Printer Memory Map Printer ACK Interrupt Control Register FFF42030 BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO Printer FAULT Interrupt Control Register FFF42031 BIT 23 22 21 20 19 18 17 16 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO Printer SEL Interrupt Control Register FFF42032 BIT 15 14 13 12 11 10 9 8 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO Printer PE Interrupt Control Register FFF42033 BIT 7 6 5 4 3 2 1 0 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO Printer BUSY Interrupt Control Register FFF42034 BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO Printer Input Status Register FFF42036 BIT 15 14 13 12 11 10 9 8 NAME PLTY ACK FLT SEL PE BSY Printer Port Control Register FFF42037 BIT 7 6 5 4 3 2 1 0 NAME DOEN INP STB FAST MAN Printer Data Register 16 bits FFF4203A BIT 15 0 NAME PD15 PDO http www motorola com computer literature 1 31 Programming Issues Table 1 7 PCCchip2 Memory Map PCCchip2 Base Address FFF42000
143. ap decoder is disabled When this bit is high the fourth local bus to VMEbus map decoder is enabled When this bit is low the fourth local bus to VMEbus map decoder is disabled http www motorola com computer literature 2 49 VMEchip2 Local Bus to VMEbus I O Control Register ADR SIZ FFF4002C 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME I2WP 1259 I2PD I1D16 1150 R W R W R W R W R W R W R W R W RESET 0PSL 0 PS O PS 0 PS 0 PS O PS 0 PS O PS This register controls the VMEbus short I O map and the F page F0000000 through FF7FFFFF I O map TISU I1D16 I2PD DSU When this bit is high the VMEchip2 drives a supervisor address modifier code when the short I O space is accessed When this bit is low the VMEchip2 drives a user address modifier code when the short I O space is accessed When this bit is high write posting is enabled to the VMEbus short I O segment When this bit is low write posting is disabled to the VMEbus short I O segment When this bit is high D16 data transfers are performed to the VMEbus short I O segment When this bitis low D32 data transfers are performed to the VMEbus short I O segment When this bit is high the VMEbus short I O map decoder is enabled When this bit is low the VMEbus short I O map decoder is disabled When this bit is high the VMEchip2 drives a program addre
144. arting Address Register 2 OPER R W RESET 0 PS This register is the starting address register for the second local bus to VMEbus map decoder 2 40 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Slave VMEbus Master Ending Address Register 3 ADR SIZ FFF4001C 16 bits of 32 BIT 31 16 Ending Address Register 3 OPER R W RESET 0 PS This register is the ending address register for the third local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 3 ADR SIZ FFF4001C 16 bits of 32 BIT 15 0 Starting Address Register 3 OPER R W RESET 0 PS This register is the starting address register for the third local bus to VMEbus map decoder Local Bus Slave VMEbus Master Ending Address Register 4 ADR SIZ FFF40020 16 bits of 32 BIT 31 26 16 Ending Address Register 4 OPER R W RESET 0 PS This register is the ending address register for the fourth local bus to VMEbus map decoder http www motorola com computer literature 2 41 VMEchip2 Local Bus Slave VMEbus Master Starting Address Register 4 ADR SIZ FFF40020 16 bits of 32 BIT 15 es 0 NAME Starting Address Register 4 OPER R W RESET 0 PS This register is the starting address register for the fourth local bus to VMEbus map decoder Local Bus Sl
145. arts ticking when a data transfer to the VMEbus is write posted The timer stops ticking once the chip has started the data transfer on the VMEbus If this does not happen before the timer times out the chip aborts the write posted cycle and sends an interrupt to the local bus interrupter If the write post bus error interrupt is enabled in the local bus interrupter the local processor is interrupted to indicate a write post time out has occurred The write post timer has the same timing as the VMEbus access timer Local Bus to VMEbus Requester The requester provides all the signals necessary to allow the local bus to VMEbus master to request and be granted use of the VMEbus The chip connects to all signals that a VMEbus requester is required to drive and monitor Requiring no external jumpers the chip provides the means for software to program the requester to request the bus on any one of the four bus request levels automatically establishing the bus grant daisy chains for the three inactive levels http www motorola com computer literature 2 7 VMEchip2 The requester requests the bus if any of the following conditions occur 1 The local bus master initiates either a data transfer cycle or an interrupt acknowledge cycle to the VMEbus 2 The chip is requested to acquire control of the VMEbus as signaled by the DWB input signal pin 3 The chip is requested to acquire control of the VMEbus as signaled by the DWB control
146. at location FFF4203B or PD15 PDO can be accessed as a 16 bit register at location FFF4203A In auto mode writing these bits also generates the strobe for the printer Reading these bits causes the PCCchip2 to read the data from the printer data signal lines no strobe is generated When the DOEN bit is set the printer data signal lines are driven by the external printer data buffer When the DOEN bit is cleared they must be terminated to high or to low and or an external device must drive them http www motorola com computer literature 3 47 PCCchip2 Interrupt Priority Level Register ADR SIZ FFF4203E 8 bits BIT 15 14 13 12 11 10 9 8 NAME IPL2 IPL1 IPLO OPER R R R R R R R R RESET 0 0 0 0 0 X X X IPL2 IPLO Interrupt Priority Level These bits reflect the priority encoded interrupt request level This level is a combination of the PCCchip2 interrupt requests and the interrupt requests driven onto the EIPL2 EIPLO pins Note that when the C040 bit is cleared external devices can drive EIPL2 EIPLO with their interrupt requests When C040 is set the PCCchip2 drives EIPL2 EIPLO with its interrupt requests In this case C040 set IPL2 IPLO only reflect PCCchip2 interrupt requests The IPL bits are encoded as shown below IPL2 IPL1 IPLO Priority Level Comments 0 0 0 0 No Interrupt 0 0 1 1 Lowest Level 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 High
147. ate of the SCC IRQ3 pin of the CD2401 qualified by the IEN bit When this bit is high an SCC receive interrupt is being generated at the level programmed in IL2 ILO if nonzero This status bit does not need to be cleared because it is not edge sensitive Snoop Control These control bits determine the value that the PCCchip2 drives onto the local MC68040 bus SC1 and SCO pins when the CL CD2401 SCC performs DMA accesses During SCC DMA when bit SCO is 0 Local Bus pin SCO is low and when bit SCO is 1 pin SCO is high The same relationship holds true for bit and pin 1 See M68040 and MC68060 user s manuals for details on how it uses the Snoop Control signals Note the MVMEITT7P which uses SCI the SCO bit must be 0 Computer Group Literature Center Web Site Programming Model Modem PIACK Register ADR SIZ FFF42023 8 bits The Modem PIACK Register is used to execute modem pseudo interrupt acknowledge cycles to the CD2401 When the Local Bus master initiates a read cycle to this register the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with 7 01 Note that the PILRI register in the CD2401 should be set to the same value 01 for the interrupt acknowledge cycle to operate properly To finish the local read cycle the PCCchip2 drives the vector received from the CD2401 onto the local data bus and asserts TA Reads to th
148. ation and Use V177PA IH MVME167Bug Debugging Package User s Manual MVMEI67BUG MVME177Bug Debugging Package User s Manual MVME177BUG Debugging Package for Motorola 68K CISC CPUs User s 68KBUGI D Manual Parts 1 and 2 68KBUG2 D Single Board Computers SCSI Software User s Manual SBCSCSI D MVME712M Transition Module and P2 Adapter Board VME712MA IH Installation and Use MVME712 12 MVME712 13 MVME712A MVME712A D MVME712AM and MVME712B Transition Modules and LCP2 Adapter Board User s Manual To locate and view the most up to date product information in PDF or HTML format visit http www motorola com computer literature 1 Related Documentation Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As a further help sources for the listed documents are also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table C 2 Manufacturers Documents Publication Document Title and Source Number M68000 Family Reference Manual M68000FR MC68060 Microprocessor User s Manual M68060UM Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail Idcformotorola hibbertco com Web http www mot com SPS 82596CA Local Area Network Coprocessor Data Sheet 290218 82596CA Local A
149. ave VMEbus Master Address Translation Address Register 4 ADR SIZ FFF40024 16 bits of 32 BIT 31 n 16 NAME Address Translation Address Register 4 OPER R W RESET 0 PS This register is the address translation address register for the fourth local bus to VMEbus bus map decoder Local Bus Slave VMEbus Master Address Translation Select Register 4 ADR SIZ FFF40024 16 bits of 32 BIT 15 m 0 NAME Address Translation Select Register 4 OPER R W RESET 0 PS This register is the address translation select register for the fourth local bus to VMEbus bus map decoder 2 42 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Slave VMEbus Master Attribute Register 4 ADR SIZ FFF40028 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME D16 WP AM OPER R W R W R W RESET OPS OPS OPS This register is the attribute register for the fourth local bus to VMEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 4 Because the local bus to VMEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to the segment defined by map decoder 4 When this bit is low write posting is disabled to the segment defined by map decoder 4
150. ber percent specifies a binary number amp ampersand specifies a decimal number Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition xxiii bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts Enter Return or CR CR represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or
151. bit VMEbus address counter a 32 bit byte counter and control and status registers The Local Control and Status register LCSR provides software with the ability to control the operational modes of the DMAC Software can program the DMAC to transfer up to 4GB of data in the course of asingle DMA operation The DMAC supports transfers from any local bus address to any VMEbus address The transfers may be from 1 byte to 4GB in length To optimize local bus use the DMAC automatically adjusts the size of individual data transfers until 32 bit transfers can be executed Based on the address of the first byte the DMAC transfers a single byte a double byte or a mixture of both and then continues to execute quad byte block transfer cycles When the DMAC is set for 64 bit transfers the octal byte transfers takes place Based on the address of the last byte the DMAC transfers a single byte a double byte or a mixture of both to end the transfer 2 10 Computer Group Literature Center Web Site Functional Blocks Using control register bits in the LCSR the DMAC can be configured to provide the following VMEbus capabilities Addressing capabilities A16 A24 A32 Data transfer capabilities D16 D32 D16 BLT D32 BLT D64 BLT BLT block transfer Using the DMA AM Address Modifier control register the address modifier code that the VMEbus DMA controller places on the VMEbus can be programmed under software control In addition
152. bles show the memory maps of devices that respond to the normal address range The normal address range is defined by the Transfer Type TT signals on the local bus On the MVME1X7P Transfer Types 0 1 and 2 define the normal address range Table 1 3 is the entire map from 00000000 to FFFFFFFF Many areas of the map are user programmable and suggested uses are shown in the table The cache inhibit function is programmable in the MC680x0 MMU Computer Group Literature Center Web Site Memory Maps The onboard I O space must be marked cache inhibit and serialized in its page table Table 1 4 on page 1 22 further defines the map for the local I O devices on the MVMEIXT7P Table 1 3 Local Bus Memory Map Address Software Devices Accessed Port Size Size Cache Notes Range mm Inhibit 00000000 User Programmable D32 DRAMSIZE N 1 2 DRAMSIZE Onboard SDRAM DRAMSIZE User Programmable D32 D16 3GB 2 3 4 FF7FFFFF VMEbus FF800000 ROM 167P D32 4MB N 1 SFFBFFFFF EPROM Flash 177P 232 2MB N 1 6 EPROM 4MB Flash FFCO00000 Reserved 2MB 5 FFDFFFFF FFE00000 SRAM D32 128KB N FFEIFFFF FFE20000 SRAM repeated D32 896KB N FFEFFFFF FFF00000 Local I O Devices D32 D8 IMB Y 3 SFFFEFFFF Refer to next table 0000 User Programmable D32 D16 64KB 7 2 4 FFFFFFFF VMEbus A16 Notes 1 ROM on MVME167P ROM Flash on MVME177P Flash EPROM
153. bus 2 17 bus timers example of use 1 51 byte counter DMAC 2 60 C cache coherency MCECC sector 4 4 MVMEIx7P 1 49 cache inhibit function 1 20 cautions for use of reset VMEchip2 2 101 CD2401 serial controller chip 1 12 3 7 memory map 1 36 changes from previous boards 1 checksum byte 1 46 chip arbiter VMEbus 2 17 chip ID and revision registers VMEchip2 ASIC 2 100 Chip ID register MCECC sector 4 13 PCCchip2 ASIC 3 14 Chip Revision register MCECC sector 4 13 PCCchip2 ASIC 3 14 Chip Speed register PCCchip2 ASIC 3 46 clear bits LANC error 3 34 SCSI error 3 37 clear overflow counter tick timer 1 3 23 tick timer 2 3 22 clear on compare tick timer 1 3 23 tick timer 2 3 22 IN 2 Computer Group Literature Center Web Site clear on compare mode VMEchip2 counters 2 15 clocks for VMEchip2 counters and timers 2 67 command chaining mode VMEchip2 DMAC 2 12 2 52 command packets DMAC 2 52 compatibility backward 1 2 connection diagrams printer and serial port B 1 transition module B 1 Control and Status registers CSRs PCCchip2 ASIC 3 11 memory map 3 12 counter enable tick timer 1 3 23 tick timer 2 3 22 cycle types MCECC sector 4 5 D data access cycles VMEbus 2 33 2 36 data bus structure 1 7 data sheets sources of C 2 data transfer capabilities local bus to V MEbus interface 2 4 VMEbus to local bus interface 2 9 VMEchip2 DMAC 2 11 data transfer size VMEchip2 DMAC 2 11 data transfers DMA VMEchip2
154. chip2 General Purpose Input Interrupt Control Register ADR SIZ FFF42018 8 bits BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the general purpose input output GPIO pin Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as zero When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a general purpose input interrupt is being generated at the level programmed in IL2 ILO if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low the interrupt is activated by either a rising edge on the GPIO pin or a high level on the GPIO pin depending on the E L bit When this bit is high the interrupt is activated by either a falling edge on the GPIO pin or a low level of the GPIO pin depending on the E L bit Note that if this bit is changed while the E L bit is set or is being set a GPIO interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the E L bit Co
155. computer literature PCCchip2 INT Interrupt Status When this bit is high a Tick Timer 2 interrupt is being generated at the level programmed in IL2 ILO if nonzero This bit is edge sensitive and can be cleared by writing a logic 1 into the ICLR control bit Tick Timer 1 Interrupt Control Register ADR SIZ BIT FFF4201B 8 bits 5 4 3 2 1 0 NAME INT ICLR IL2 IL1 ILO OPER R R W C R W R W R W RESET 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO ICLR IEN INT Interrupt Request Level These three bits select the interrupt level for Tick Timer 1 Level 0 does not generate an interrupt Writing a logic 1 into this bit clears the INT status bit This bit is always read as zero Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low Interrupt Status When this bit is high a Tick Timer 1 interrupt is being generated at the level programmed in IL2 ILO if nonzero This bit is edge sensitive and can be cleared by writing a logic 1 into the ICLR control bit Computer Group Literature Center Web Site Programming Model SCC Error Status and Interrupt Control Registers This section provides addresses and bit level descriptions of the SCC interrupt control registers and status registers SCC Error Status Register LTO EXT PRTY RTRY ADR SI
156. configured These include DRAM size DRAM speed Control and Status register selection etc The configuration parameters are loaded into the Defaults 1 Defaults 2 and SDRAM Configuration registers on the first clock edge after reset negation Software can override this initial setting by writing to the Defaults registers However it is not recommended that non test software alter the contents of the Defaults registers The actual values loaded into the Defaults registers are determined by board level jumpers and configuration resistors http www motorola com computer literature 4 9 MCECC Functions Programming Model This section defines the programming model for the control and status registers CSRs in the MCECC sector The base address of the CSRs is hard coded to the address FFF43000 for the MCECC sector on the first mezzanine board and to FFF43100 for the MCECC sector on the second mezzanine board Note that several bits in the register map have changed in functionality from the MCECC ASIC pair In most cases these bits were defined to be nonoperational in the MCECC model but were also defined as to their original intent This specification entirely omits those bit definitions The possible operations for each bit in the CSR are as follows R The bit is a read only status bit R W Thebit is readable and writable R C This status bit is cleared by writing a 1 to it Writing a 0 to the bit clears it or another bit Th
157. control of local reset Four global attention interrupt bits A chip ID and revision register Four 16 bit dual ported general purpose registers Interrupt Handler All interrupts level programmable All interrupts maskable All interrupts providing a unique vector Software and external interrupts Watchdog timer Control and status bits 4 bit counter Two tick timers Control and status bits 32 bit counter http www motorola com computer literature 2 VMEchip2 Functional Blocks The following sections provide an overview of the functions implemented by the VMEchip2 ASIC See Figure 2 1 for a block diagram of the VMEchip2 Detailed programming models for the local control and status registers LCSRs and the global control and status registers GCSRs appear in subsequent sections Local Bus to VMEbus Interface The local bus to VMEbus interface allows local bus masters access to global resources on the VMEbus This interface includes a local bus slave a write post buffer and a VMEbus master Using programmable map decoders with programmable attribute bits the local bus to V MEbus interface can be configured to provide the following VMEbus capabilities Addressing capabilities A16 A24 A32 Data transfer capabilities D08 D16 D32 The ocal bus slave includes six local bus map decoders for accessing the VMEbus The first four map decoders are general purpose pr
158. controlled by this MCECC pair at the rate of 100MB second when the BCLK pin is operating at 25MHz This sequence may have to be altered to perform the scrub more slowly if the scrub causes the DRAM to consume too much power at full speed 1 Make sure that the scrubber is disabled by clearing the SCRBEN bit in the Scrub Control register Clear bit 27 of offset 24 2 Make sure that the scrubber is done with any old scrub cycles by waiting for the SCRB bit in the Scrub Control register to be cleared Wait for bit 28 of offset 24 0 3 Discontinue all accesses from the MC680x0 bus to the DRAM 4 Ensure that all accesses have stopped by clearing the RAMEN bit in the DRAM Control register Clear bit 0 of offset 18 5 Set the ZFILL bit in the MCECC pair Set Bit 28 of offset 20 6 Setthe Scrub Time On Time Off register for the maximum rate and to do write cycles by setting the SRDIS bit setting all of the STON bits and clearing all of the STOFF bits Write B8 to offset 34 7 Enable scrubbing by setting the SCRBEN bit in the Scrub Control register Set bit 27 of offset 24 8 Ensure that the zero fill has started by waiting for the SCRB bit in the Scrub Control register to be set Wait for bit 28 of offset 24 1 4 34 Computer Group Literature Center Web Site Programming Model 9 Ensure that the zero fill stops after one pass by clearing the SCRBEN bit in the Scrub Control register Clear bit 27 o
159. ction Diagrams 06 BPEL en ee nae ee ae mee eee Tt I I 1 ik i I 1 MEE ism 1920 93 90 LOIN 009 98 ET ee rom 90vSt LOW 1 d 1 1 OND M 1 1 I M 1 1 i 1 1 1 1 l 1 1 i 1 1 1 I 1 d 1 1 1 1 i i 884 ws Dp UI qe 4 p 90 LOW 1 1 954 Du ox ME per nS EN sej 94 90997 LOW torpedo ZEE 4 anavo NOLLISNVH L QNO9 Haldvav ZLI3WAW 49 gd dLLISWAW d293IANN na P n wal eee earns 4d
160. d When a match occurs in either mode an interrupt is sent to the local bus interrupter and the overflow counter is incremented An interrupt to the local bus is only generated if the tick timer interrupt is enabled by the local bus interrupter The overflow counter can be cleared by writing a 1 to the overflow clear bit Tick timer 1 or 2 can be programmed to generate a pulse on the VMEbus IRQI interrupt line at the tick timer period This provides a broadcast interrupt function which allows several VME boards to receive an interrupt at the same time In certain applications this interrupt can be used to synchronize multiple processors This interrupt is not acknowledged on the VMEbus This mode is intended for specific applications and is not defined in the VMEbus specification Watchdog Timer The watchdog timer has a 4 bit counter four clock select bits an enable bit a local reset enable bit a SYSRESET enable bit a board fail enable bit counter reset bit WDTO status bit and WDTO status reset bit When enabled the counter increments at a rate determined by the clock select bits If the counter is not reset by software the counter reaches its terminal count When this occurs the WDTO status bit is set and if the local or SYSRESET function is enabled the selected reset is generated if the board fail function is enabled the board fail signal is generated http www motorola com computer literature 2 15 VMEchip2 VMEb
161. d SCC Receive Interrupt Control Register If this mode is disabled by setting the AVEC bits to 0 then the PCCchip2 obtains the vector from the SCC and passes it to the MPU Using the auto vector mode is NOT recommended http www motorola com computer literature 3 17 PCCchip2 A suggested setting of the Local Interrupt Vector Register in the SCC chip is 5C This produces the following vectors 5C Serial RX Exception IRQ 5D Serial Modem IRQ 5E Serial TX IRQ 5F Serial RX IRQ Programming the Tick Timers This section provides addresses and bit level descriptions of the prescaler tick timers and various other timer registers Tick Timer 1 Compare Register The Tick Timer 1 Compare Register is a 32 bit register located at FFF42004 The count value of Tick Timer 1 is compared to this register When they are equal an interrupt is sent to the Local Bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to determine the compare register value for a specific period compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at zero the time to the first interrupt may be longer or shorter than expected The rollover time for the counter is 71 6 minutes
162. d from the retry and this bit is low VMEchip2 drives VMEbus BBSY for a minimum of 32 local bus clocks which allows the local bus master time to return 2 08 Computer Group Literature Center Web Site LCSR Programming Model from the retry and the board does not lose its turn on the VMEbus For this reason it is recommended that this bit remain low NOELBBSY When this bit is high the early release feature of bus busy feature on the VMEbus is disabled The VMEchip2 drives BBSY low whenever VMEbus AS is low When this bit is low the early release feature of bus busy feature on the VMEbus is not disabled DISMST When this bit is high the VME LED on the MVMEIx7P illuminates on assertion of Local Bus Reset or when the VMEchip2 ASIC is driving Local Bus Busy When this bit is low the VME LED on the MVMEIx7P illuminates on assertion of Local Bus Reset when the VMEchip2 is driving Local Bus Busy or when the VMEchip2 is driving the VMEbus address strobe The signal is also available at J2 the Remote Reset connector behind the front panel This connector allows the Reset Abort and LED functions to be extended to the exterior of the enclosure containing the board DISSRAM When this bit is high the SRAM decoder in the VMEchip2 is disabled When this bit is low the SRAM decoder in the VMEchip2 is enabled Because the SRAM decoder in the VMEchip2 is not used on the MVMEIx7P this bit must be set REVEROM This function i
163. d mode operation with the CD2401 Note If this register is read when an interrupt is not present the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled RIV7 RIVO Receive Interrupt vector bits 7 0 reflect the transmit interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle http www motorola com computer literature 3 33 PCCchip2 LANC Error Status and Interrupt Control Registers This section provides addresses and bit level descriptions of the LANC interrupt control registers and status register LANC Error Status Register ADR SIZ FFF42028 8 bits BIT 31 30 29 28 27 26 25 24 NAME PRTY EXT LTO SCLR OPER R R R R W R 0 RESET 0 0 0 0 0 PL 0 PL 0 PL 0 SCLR Writing a 1 to this bit clears bits 25 through 27 LTO EXT and PRTY Reading this bit always yields 0 LTO EXT PRTY These bits indicate the status of the last Local Bus error condition encountered by the LANC while performing accesses to the Local Bus A Local Bus error condition is flagged by the assertion of TEA When the LANC receives TEA If the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is s
164. d not be reprogrammed unless the VMEchip2 is VMEbus master The value F in the GCSR board address register disables the map decoder The map decoder is enabled when the board address is not F GCSR Board These bits define the board number portion of the GCSR address These bits are compared with VMEbus address lines A4 through A7 The GCSR is enabled by values 0 through SE The address XXFY in the VMEbus A16 space is reserved for the location monitors LMO through LM3 Note that XX is the group address and Y is the location monitor 1 LMO 3 LM1 5 LM2 7 LM3 2 48 Computer Group Literature Center Web Site LCSR Programming Model Local Bus to VMEbus Enable Control Register ADR SIZ FFF4002C 4 bits of 32 BIT 19 18 17 16 NAME EN4 EN3 EN2 ENI OPER R W R W R W R W RESET OPSL OPSL OPSL OPSL This register is the map decoder enable register for the four programmable local bus to V MEbus map decoders EN2 EN3 ENA When this bit is high the first local bus to VMEbus map decoder is enabled When this bit is low the first local bus to VMEbus map decoder is disabled When this bit is high the second local bus to VMEbus map decoder is enabled When this bit is low the second local bus to VMEbus map decoder is disabled When this bit is high the third local bus to VMEbus map decoder is enabled When this bit is low the third local bus to VMEbus m
165. dentifying SDRAM Bank in Error Laisser tme rebates 4 37 Table A 1 List Of Changes 1 Table C 1 Motorola Computer Group Documents C 1 Table C 2 Manufacturers 2 Table 1 3 Related Speci BSBIODS C 3 xix XX About This Manual This manual provides board level information and detailed ASIC information including register bit descriptions for the MVME167PA xxSE and MVME177PA xxSE series of VME single board computers known collectively as the MVME1X7P The Petra chip that distinguishes MVME167P and MVME177P single board computers is an application specific integrated circuit ASIC used on various Motorola VME boards which combines a variety of functions previously implemented in other ASICs among them the MC2 chip the IP2 chip and the MCECC chip in a single ASIC On the MVME1X7P the Petra chip replaces the MCECC As of the publication date the information presented in this manual applies to the following MVMEIX7P models Model Number Characteristics MVME167PA 24SE 25MHz MC68040 16MB SDRAM SCSI and Ethernet MVMEI67PA 25SE 25MHz MC68040 32MB SDRAM SCSI and Ethernet MVME167PA 34SE 33MHz MC68040 16MB SDRAM SCSI and Ethernet MVME167PA 35SE 33MHz MC68040 32MB
166. e 1 6 Programming Interfaces Programming Interfaces The following sections describe the programming interface to devices on the MVME167P and MVME177P single board computers Unless the section specifies a particular board type the discussion applies to both models MC680X0 MPU The MVME167P is based on the MC68040 microprocessor The MVMEIT77P is based on the MC68060 microprocessor Both processors have on chip instruction and data caches and a floating point processor refer to the MC68040 and MC68060 user s manuals for more information Both models are available in various versions with the features listed in Table 1 1 on page 1 3 Data Bus Structure The local bus for all single board computers described in this manual is a 32 bit synchronous bus which is based on an MC68040 compatible bus and which supports burst transfers Throughout this manual this bus is referred to as the Local Bus The various Local Bus master and slave devices use the Local Bus to communicate The Local Bus is arbitrated by priority type arbiter The priority of the Local Bus masters from highest to lowest is Highest priority 82596CA LAN CD2401 serial through the PCCchip2 53C710 SCSI VMEbus Lowest priority MPU http www motorola com computer literature 1 7 Programming Issues As a general rule any master can access any slave not all combinations pass the common sense test however Refer to the device specific sections of th
167. e Petra MCECC sector design is targeted for SDRAM devices of the PC100 type Memory access time are not influenced by the settings of mode bits or SDRAM speed selections The basic performance specifications for the MCECC sector are listed in Table 4 2 http www motorola com computer literature 4 3 MCECC Functions Note The table is not complete because it cannot account for the effects of a write posting operation If the Petra MCECC sector is idle and a write cycle is initiated on the local bus the cycle is write posted and the local bus is acknowleged in two clock ticks If another bus cycle is initiated while the write post operation is in progress the new cycle is stalled until the write posting is complete The Read cycles are extended by one clock cycle if the the NCEBEN bit is set in the SDRAM Control register Since the bandwidth between the SDRAM and the processor local bus is generally higher than that of the logic it replaces the MCECC pair and EDO DRAMs software will take less time to execute This could change the behavior of certain applications Table 4 2 Memory System Cycle Timing Access Memory States Description Idle Active Hit Active Miss Read Single 4 clock cycles 3 clock cycles 5 clock cycles Read Burst 4 1 1 1 clock cycles 3 1 1 1 clock cycles 5 1 1 1 clock cycles Write Burst 2 1 1 1 clock cycles 2 1 1 1 clock cycles 2 1 1 1 clock cycles Write Longword 2 clock c
168. e processor clock by a prescaler Each tick timer has a 32 bit counter a 32 bit compare register and a clear on compare enable bit The counter is readable and writable at any time These timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing There are two modes of operation for these timers free running and clear on compare In free running mode the timers have a resolution of 1 us and roll over after the count reaches the maximum value FFFFFFFF The rollover period for the timers is 71 6 minutes When the counter is enabled in the clear on compare mode it increments every 1 us until the counter value matches the value in the compare register When a match occurs the counter is cleared When a match occurs in either mode an interrupt is sent to the Local Bus interrupter and the overflow counter is incremented An interrupt to the Local Bus is only generated if the tick timer interrupt is enabled by the Local Bus interrupter The overflow counter can be cleared by writing a one to the overflow clear bit http www motorola com computer literature 3 9 PCCchip2 Overall Memory Map The following memory map includes all devices selected by the PCCchip2 map decoders including those internal to the chip and those external These devices respond only when the Transfer Type signals carry the values of 00 or 01 which correspond to Normal and 16 acces
169. e programmed and the DMAC is enabled The DMAC transfers data as programmed until the byte count is zero or an error is detected When the DMAC stops the status bits in the DMAC status register are set and an interrupt is sent to the local bus interrupter If the DMAC interrupt is enabled in the local bus interrupter the local bus is interrupted The time on and time off timers should be programmed to control the VMEbus bandwidth used by the DMAC http www motorola com computer literature 2 51 VMEchip2 A maximum of 4GB of data may be transferred with one DMAC command Larger transfers can be accomplished using the command chaining mode In command chaining mode a singly linked list of commandis is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands The DMAC control register is programmed and the DMAC is enabled The DMAC executes commands from the list until all commands are executed or an error is detected When the DMAC stops the status bits are set in the DMAC status register and an interrupt is sent to the local bus interrupter If the DMAC interrupt is enabled in the local bus interrupter the local bus is interrupted When the DMAC finishes processing a command in the list and interrupts are enabled for that command the DMAC sends an interrupt to the local bus interrupter If the DMAC interrupt is enabled in the local bus interrupter the local bus
170. eases the VMEbus according to the release mode programmed in the LVRWD bit When the VMEbus has been acquired the DHB bit is set When this bit is high the VMEbus has been acquired in response to the DWB bit being set When the DWB bit is cleared this bit is cleared When this bit is high the VMEbus arbiter operates in round robin mode When this bit is low the arbiter operates in priority mode DMAC Control Register 1 bits 0 7 ADR SIZ FFF40030 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME DHAIT DEN DTBL DFAIR DRELM DREQL OPER 5 5 R W R W R W R W RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS This control register is loaded by the processor it is not modified when the DMAC loads new values from the command packet DREQL These bits define the VMEbus request level for the DMAC requester The request level can only change while the VMEchip2 is bus master The VMEchip2 http www motorola com computer literature 2 55 VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect If the VMEchip2 is bus master when the level is changed the new level does not take effect until the bus has been released and re requested at the old level The requester always requests the VMEbus at level 3 the first time following a SYSRESET 0 VMEbus request level 0 1 VMEbus request level 1 2 VMEbus request level 2 3 VMEbus request level 3 DRELM These bits defi
171. ed The interrupt is disabled when this bit is low INT When this bit is high a printer SEL interrupt is being generated at the level programmed in IL2 ILO if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a rising edge high level of the SEL pin When this bit is high interrupt is activated by a falling edge low level of the SEL pin Note that if this bit is changed while the E L bit is set or is being set a SEL interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the E L bit http www motorola com computer literature 3 41 PCCchip2 Printer PE Interrupt Control Register ADR SIZ FFF42033 8 bits BIT 7 6 5 4 3 2 1 0 PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the printer PE Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as zero When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a printer PE interrupt is being generated at
172. edge map 1 46 base vectors VMEbus 2 95 control register VMEchip2 2 101 counter DMAC 2 62 handler routine how to set up 1 49 mask level 3 49 interrupt enable GPIO 3 24 LANC bus error 3 36 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer paper error 3 42 printer select 3 41 SCC modem 3 28 SCC receive 3 30 SCC transmit 3 29 SCSI processor 3 38 tick timer 1 3 26 tick timer 2 3 25 interrupt handler SCSI I O 3 6 VMEbus 2 16 VMEchip2 2 18 interrupt handling 1 47 interrupt level GPIO 3 24 LANC bus error 3 36 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer paper error 3 42 printer select 3 41 SCC modem 3 28 SCC receive 3 30 SCC receive interrupt 3 30 SCC transmit PCCchip2 ASIC 3 29 SCSI processor 3 38 tick timer 1 3 26 tick timer 2 PCCchip2 ASIC 3 25 Interrupt Mask Level register PCCchip2 ASIC 3 49 interrupt priority level 3 48 http www motorola com computer literature IN 5 lt moz xXmoz Index Interrupt Priority Level register PCCchip2 ASIC 3 48 interrupt sources PCCchip2 VBR 3 17 VMEchip2 ASIC 2 18 interrupt status GPIO 3 24 LANC bus error 3 36 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer input 3 44 printer paper error 3 42 printer select 3 41 SCC modem 3 28 SCC receive 3 30 SCC transmit 3 29 SCSI processor 3 38 tick timer 1 3 26 tick timer 2 3 26
173. edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ESWO0 ESWI1 ESW2 ESW3 ESW4 ESWS ESW6 ESW7 Enable software 0 interrupt Enable software 1 interrupt Enable software 2 interrupt Enable software 3 interrupt Enable software 4 interrupt Enable software 5 interrupt Enable software 6 interrupt Enable software 7 interrupt http www motorola com computer literature 2 83 VMEchip2 Local Bus Interrupter Enable Register bits 0 7 ADR SIZ FFF4006C 8 bits of 32 BIT 9 6 5 4 3 2 1 0 NAME SPARE EIRQ7 EIRQ6 EIRQS EIRIQ4 EIRQ3 EIRQ2 EIRQI OPER gw RW RW RW RW RW RW RESET oPsL OPSL OPSL OPSL OPSL OPSL OPSL This is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled EIRQI EIRQ2 EIRQ3 EIRQ4 5 EIRQ6 EIRQ7 SPARE Enable VMEbus IRQI interrupt Enable VMEbus IRQ2 interrupt Enable VMEbus IRQ3 interrupt Enable VMEbus IRQA interrupt Enable VMEbus IRQS interrupt Enable VMEbus IRQ6 interrupt Enable V
174. efined by the first VMEbus slave map decoder These bits control the snoop enable lines to the local bus for the address range defined by the first VMEbus slave map decoder The snooping functions differ according to processor type as shown SNP1 Requested Snoop Operation MC68040 Snoop disabled MC68060 Snoop enabled Source dirty sink byte word longword Snoop disabled Source dirty invalidate line Snoop enabled oj OF Snoop disabled Reserved Snoop disabled When this bit is high the adder is used for address translation When this bit is low the adder is not used for address translation http www motorola com computer literature 2 35 VMEchip2 VMEbus Slave Address Modifier Select Register 1 ADR SIZ FFF40010 8 bits of 32 BIT 7 6 5 4 3 2 1 0 SUP USR A32 A24 D64 BLK PGM DAT OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the address modifier select register for the first VMEbus to local bus map decoder There are three groups of address modifier select bits DAT PGM BLK and D64 A24 and A32 and USR and SUP At least one bit must be set from each group to enable the first map decoder DAT When this bit is high the first map decoder responds to VMEbus data access cycles When this bit is low
175. egister 2 ADR SIZ Local Bus FFF40110 VMEbus XXY8 16 bits BIT 15 SA 0 NAME General Purpose Register 2 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification http www motorola com computer literature 2 107 VMEchip2 General Purpose Register 3 ADR SIZ Local Bus FFF40114 VMEbus XXYA 16 bits BIT 15 us 0 NAME General Purpose Register 3 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose Register 4 ADR SIZ Local Bus FFF40118 VMEbus XXYC 16 bits BIT 15 um 0 NAME General Purpose Register 4 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose Register 5 ADR SIZ Local Bus FFF4011C VMEbus XXYE 16 bits BIT 15 1 0 General Purpose Register 5 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by
176. egister are ADR SIZ 1st FFF43014 2nd FFF43114 8 bits BIT 31 30 29 28 27 26 25 24 NAME BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 OPER R W R W R W R W R W R W R W RESET O0PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS DRAM Control Register The bit assignments for the DRAM Control register are ADR SIZ 1st FFF43018 2nd FFF43118 8 bits BIT 31 30 29 28 27 26 25 24 BAD23 BAD22 RWB5 RWB4 RWB3 NCEIEN NCEBEN RAMEN OPER R W R W R W R W R W R W R R W RESET JOPLS OPLS OPLS OPLS OPLS 5 0 PLS 0 PLS RAMEN RAM Enable This control bit is used to enable the local bus to perform read write accesses to the memory Accesses are enabled when this bit is set and are disabled when this bit is cleared This bit should only be set after BAD31 BAD22 have been initialized http www motorola com computer literature 4 15 MCECC Functions NCEBEN Setting the NCEBEN control bit enables the MCECC pair to assert TEA when a non correctable error occurs during a local bus access to memory In some cases setting NCEBEN causes DRAM accesses to be delayed by one clock This delay is incurred when the access is a local bus or scrub read and the FSTRD bit is set NCEIEN When NCEIEN is set the logging of a non correctable error causes the INT signal pin to pulse true Note that NCEIEN has no effect o
177. er 256 BCLK cycles 1 1 0 Request DRAM after 512 BCLK cycles 1 1 1 Request DRAM never STON2 STONO STON2 STONO control the amount of time that the scrubber occupies the DRAM before providing a window during which the local bus and refresher might use it They control the on time as follows STON2 STON1 STONO Scrubber Time On 0 0 0 Keep DRAM for 1 memory cycle 0 0 1 Keep DRAM for 16 BCLK cycles 0 1 0 Keep DRAM for 32 BCLK cycles 0 1 1 Keep DRAM for 64 BCLK cycles 1 0 0 Keep DRAM for 128 BCLK cycles 1 0 1 Keep DRAM for 256 BCLK cycles 1 1 0 Keep DRAM for 512 BCLK cycles Keep DRAM for TOTAL SCRUB TIME 4 22 Computer Group Literature Center Web Site Programming Model RWB7 Note that if STON2 0 is zero the scrubber always releases the DRAM after one memory cycle even if neither the local bus nor refresher need it Read Write Bit 7 is a general purpose read write bit Scrub Prescaler Counter Bits 21 16 The Scrub Prescaler counter uses IMHz clock as an input to create the 0 5 Hz clock that is used for the scrub period Writes to this address update the scrub prescaler Reads to this address yield the value in the scrub prescaler The ability to read and write to the scrub prescaler is provided for test purposes Programming this counter is not recommended This register reflects the current value in the scrub prescaler bits 21 16
178. er 3 SCHR3 1D B R W Async Special Character Register 4 SCHR4 1C B R W Async Special Character Range low SCRI 23 B R W Async Special Character Range high SCRh 22 B R W Async LNext Character LNXT 2E B R W Async 1 36 Computer Group Literature Center Web Site Memory Maps Table 1 9 Cirrus Logic CD2401 Serial Port Memory Map Continued Base Address FFF45000 Register Description Register Offsets Size Access Name Bit Rate and Clock Option Registers Receive Frame Address Register RFARI 1F B R W Sync Receive Frame Address Register2 RFAR2 1E B R W Sync Receive Frame Address Register3 RFAR3 1D B R W Sync Receive Frame Address Register4 RFAR4 R W Sync CRC Polynomial Select Register CPSR D6 B R W Sync Receive Baud Rate Period Register RBPR CB B R W Receive Clock Option Register RCOR C8 B R W Transmit Baud Rate Period Register TBPR C3 B R W Transmit Clock Option Register TCOR CO B R W Channel Command and Status Registers Channel Command Register CCR 13 B R W Special Transmit Command Register STCR 12 B R W Channel Status Register CSR 1A B R Modem Signal Value Registers MSVR DE B R W RTS MSVR DF B R W DTR Interrupt Registers Local Interrupt Vector Register LIVR 09 B R W Interrupt Enable Register IER 11 B R W Local Interrupting Channel Register LICR 26 B R W Stack Register STK E2 B R Receive Inter
179. er Control Register ten Eos PEL nasos 2 71 Tick Timer 2 Control Register 4 cessent err era edes 2 72 Tick Timer 1 Control 2 73 Prescaler COUPE uui crop tt ten te eR LEUR FRUI ORR 2 73 Programming the Local Bus Inteiruptet onerare otio nirso 2 74 Local Bus Interrupter Status Register bits 24 31 2 77 Local Bus Interrupter Status Register bits 16 23 2 78 Local Bus Interrupter Status Register bits 8 15 seen 2 79 Local Bus Interrupter Status Register bits 0 7 sss 2 80 Local Bus Interrupter Enable Register bits 24 31 2 81 Local Bus Interrupter Enable Register bits 16 23 2 82 Local Bus Interrupter Enable Register bits 8 15 2 83 Local Bus Interrupter Enable Register bits 0 7 2 84 Software Interrupt Set Register buts 8 15 Lncret ein 2 85 Interrupt Clear Register bits 24 31 ss usse tinae npe bsc indue 2 85 Interrapt Clear Register bits 16 23 2 86 Interrupt Clear Register bits 8 15 iue ence do esee e thee nca 2 87 Interrupt Level Register 1 buts 2431 2 87 Interrupt Level Register 1 bits 16 23 cpiscesscsancassscssenceestancensssunsocsnsnannis cane 2 88 Interrupt Level Register
180. ernal VMEbus IRQ7 External Spare Y7 Software 0 Y8 Software 1 Y9 Software 2 YA Software 3 YB Software 4 YC Software 5 YD Software 6 YE Software 7 YF LMO X0 GCSR LM1 X1 GCSR SIGO 2 SIGI 3 5162 4 SIG3 5 http www motorola com computer literature 2 75 VMEchip2 Table 2 4 Local Bus Interrupter Summary Continued interrupt Vector DMAC X6 VMEbus Interrupter Acknowledge X7 Tick Timer 1 X8 Tick Timer 2 X9 VMEbus 1 Edge Sensitive XA Not used on MVME1x7P XB VMEbus Master Write Post Error XC VMEbus SYSFAIL XD Not used on MVMEIx7P XE Y VMEbus ACFAIL XF Highest Notes 1 X The contents of vector base register 0 2 The contents of vector base register 1 3 Referto the Vector Base register description later in this chapter for recommended Vector Base register values 2 76 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Status Register bits 24 31 ADR SIZ FFF40068 8 bits of 32 BIT 3l 30 29 28 27 26 25 24 NAME ACF AB SYSF MWP PE TIC2 TICI OPER R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter status register When an interrupt status bitis high a local bus interrupt is being generated When an interr
181. ership has been acquired The map decoder registers can then be modified and the VMEbus released by clearing the DWB bit in the LCSR Because the VMEbus is held during this programming operation the registers should be programmed quickly with interrupts disabled The VMEbus slave map decoders can be programmed without obtaining VMEbus mastership if they are disabled and the following procedure is followed The address translation registers and starting and ending address registers should be programmed first and then the map decoders should be enabled by programming the address modifier select registers 2 26 Computer Group Literature Center Web Site LCSR Programming Model You program a VMEbus slave map decoder by loading the starting address of the segment into the starting address register and the ending address of the segment into the ending address register If the VMEbus address modifier codes indicate an A24 VMEbus address cycle then the upper eight bits of the VMEbus address are forced to 0 before the compare The address modifier select register should be programmed for the required address modifier codes A VMEbus slave map decoder is disabled when the address modifier select register is cleared The address translation registers allow local resources to have different VMEbus and local bus addresses Only address bits A31 through A16 may be modified The address translation registers also provide the upper eight local b
182. es SIZ1 0 11 There are three interrupts sources from the SCC receive interrupt transmit interrupt and modem interrupt The PCCchip2 provides the ability to individually program the priority level of each of these interrupt sources When the C040 bit is set these interrupts are sent to the MPU via the EIPL pins at the programmed level When the C040 bit is cleared they are sent to the MPU via the INT pin The INT pin is only asserted if the programmed level of the interrupt source is higher than the level programmed into the Interrupt Mask Level Register There are two interrupt acknowledge modes supported by the PCCchip2 for the SCC auto vector and direct In auto vector mode the PCCchip2 supplies the interrupt vector to the MPU No interrupt acknowledge cycle is seen by the CD2401 In direct mode the SCC supplies the vector to the MPU The PCCchip2 passes the interrupt acknowledge cycle on through http www motorola com computer literature 3 7 PCCchip2 to the CD2401 Note that the PCCchip2 drives CD2401 A7 A0 pins with 01 for modem interrupt acknowledges 02 for transmit interrupt acknowledges and 03 for receive interrupt acknowledges The use of the auto vector mode is not recommended because the CD2401 can supply the vector and the CD2401 requires an interrupt acknowledge cycle In order to support polling with the CD2401 the PCCchip2 supports pseudo interrupt acknowledge PIACK cycles to the CD
183. est Level 3 48 Computer Group Literature Center Web Site Programming Model Interrupt Mask Level Register ADR SIZ FFF4203F 8 bits BIT 7 6 5 4 2 1 0 NAME MSK2 5 MSKO OPER R R R R R W R W R W RESET 0 0 0 0 5 2 8 0 Interrupt Mask Level The interrupt mask level bits determine the level which must be exceeded by IPL2 IPLO in order for the PCCchip2 to assert its INT pin The MSK bits are encoded as follows MSK2 MSK1 MSKO Priority Level Comments 0 0 0 0 Lowest Level 0 0 1 1 A 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 Y 1 1 1 7 Highest Level http www motorola com computer literature 3 49 PCCchip2 3 50 Computer Group Literature Center Web Site MCECC Functions Introduction The ECC DRAM Controller ASIC MCECC is a device used on earlier MVMEI167 177 models whose functions are now incorporated into the Petra chip on the MVME1x7 The two memory controllers modeled in Petra duplicate the functionality of the parity memory controller found in MC ASICs as well as that of the single bit error correcting double bit error detecting memory controller found in MCECC ASICs For ease of use in conjunction with processes programming models and documentation developed for earlier boards the structure of this manual preserves the functional distinctions that formerly characterized the MCECC ASIC This chap
184. est Level These three bits select the interrupt level for SCC modem Interrupt Level 0 does not generate an interrupt When this bit is high the PCCchip2 supplies the interrupt vector to the MPU during an IACK for SCC modem interrupt When this bit is low the PCCchip2 obtains the vector from the SCC and passes it to the MPU The use of the AVEC mode is not recommended Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low Interrupt Status This status bit reflects the state of the 5 pin of the CD2401 qualified by the bit When this bit is high an SCC modem interrupt is being generated at the level programmed in IL2 ILO if nonzero This status bit does not need to be cleared because it is not edge sensitive Computer Group Literature Center Web Site Programming Model SCC Transmit Interrupt Control Register ADR SIZ FFF4201E 8 bits BIT 15 14 13 12 11 10 9 8 NAME IRQ IEN AVEC IL2 IL1 ILO OPER R R R R W R W R W R W R W RESET 0 0 X 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level for SCC Transmit Interrupt Level 0 does not generate an interrupt AVEC When this bit is high the PCCchip2 supplies the interrupt vector to the MPU during an IACK for SCC transmit interrupt When this bit is low the PCCchip2 obtains the vector from the SCC and pas
185. et and the other two status bits are cleared If the source of the error is none of the above conditions then all three bits are cleared Writing a 1 to bit 24 SCLR also clears all three bits Computer Group Literature Center Web Site Programming Model 82596CA LANC Interrupt Control Register ADR SIZ FFF4202A 8 bits BIT 15 14 13 12 11 10 9 8 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level for the 82596CA LANC Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as zero IEN Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT This status bit reflects the state of the INT pin from the LANC qualified by the IEN bit When this bit is high a LANC INT interrupt is being generated at the level programmed in IL2 ILO if nonzero E L Edge or Level When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY Polarity When this bit is low interrupt is activated by a rising edge high level of the LANC INT pin When this bit is high interrupt is activated by a
186. f offset 24 10 Wait for the zero fill to complete by waiting for the SCRB bit in the Scrub Control register to be cleared Wait for bit 28 of offset 24 0 11 Clear the ZFILL bit in the MCECC pair Clear Bit 28 of offset 20 12 The entire DRAM that is controlled by this MCECC is now zero filled The software can now program the appropriate scrubbing mode and other desired initialization and enable DRAM for operation http www motorola com computer literature 4 35 MCECC Functions Syndrome Decoding The following table defines the syndrome bit encoding for the Petra MCECC ASIC A syndrome code value of 00 indicates no error found All other syndrome code values denote an error The bit in error is decoded as shown in the table Table 4 4 Syndrome Bit Encoding Bit in Error Syndrome Code Bit in Error Syndrome Code Bit 0 4F Bit 16 0E Bit 1 4A Bit 17 0B Bit 2 52 Bit 18 13 Bit 3 54 Bit 19 15 Bit 4 57 Bit 20 16 Bit 5 58 Bit 21 19 Bit 6 5B Bit 22 1A Bit 7 5D Bit 23 1C 8 23 Bit 24 62 Bit 9 25 Bit 25 64 Bit 10 26 Bit 26 67 Bit 11 29 Bit 27 68 Bit 12 2A Bit 28 6B Bit 13 2C Bit 29 6D Bit 14 31 Bit 30 70 Bit 15 34 Bit 31 77 Check Bit 0 01 Check Bit 4 10 Check Bit 1 02 Check Bit 5 20 Check Bit 2 04 Check Bit 6 40 Check Bit 3 08 4 36 Computer Group Literature Center Web Site S
187. ff board VMEbus master access to onboard resources The VMEbus to local bus interface includes the VMEbus slave write post buffer and local bus master Adhering to the IEEE 1014 87 VMEbus standard the s ave can withstand address only cycles as well as address pipelining and respond to unaligned transfers Using programmable map decoders it can be configured to provide the following VMEbus capabilities Addressing capabilities A24 A32 Data transfer capabilities DOS EO D16 D32 D8 BLT D16 BLT D32 BLT D64 BLT BLT block transfer The slave can be programmed to perform write posting operations When in this mode the chip latches incoming data and addressing information into a staging FIFO and then acknowledges the VMEbus write transfer by asserting DTACK The chip then requests control of the local bus and independently accesses the local resource after it has been granted the local bus The write posting pipeline is two deep in non block transfer mode and 16 deep in block transfer mode To significantly improve the access time of the slave when it responds to a VMEbus block read cycle the VMEchip2 contains a 16 four byte deep read ahead pipeline When responding to a block read cycle the chip performs block read cycles on the local bus to keep the FIFO buffer full Data for subsequent transfers is then retrieved from the on chip buffer significantly improving the response time of the slave in block transfer mode The V
188. gramming Interfaces Ethernet Interface The MVMEIXT7P uses the Intel 82596CA LAN coprocessor to implement the Ethernet transceiver interface The 82596CA accesses local RAM using DMA operations to perform its normal functions Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period buffer overrun may occur if the DMA is programmed to access the VMEbus Therefore the 82596CA should not be programmed to access the VMEbus Every MVMEIXT7P that is built with an Ethernet interface is assigned Ethernet Station Address The address is 0001 where xxxxxx is the unique 6 nibble number assigned to the board i e every MVME1X7P has a different value for xxxxxx Each board has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector In addition the six bytes including the Ethernet address are stored in the configuration area of the BBRAM That is 1 AExxxxxx is stored in the BBRAM At an address of FFFC1F2C the upper four bytes 0001 can be read At an address of FFFCIF30 the lower two bytes xxxx can be read Refer to the BBRAM TOD Clock memory map description in this chapter under Battery Backed Up RAM and Clock for specifics The MVME1X7P debugger firmware has the capability to retrieve or set the Ethernet address If the data in the BBRAM is lost use the number on the VMEbus P2 connector label to restore it The Ethernet transcei
189. granted MPU TEA Cause Unidentified Description MPU Notification Status Comments An error occurred while the MPU was attempting an access TEA is asserted during an MPU access Bit 10 of the MPU Status and DMA Interrupt Count register Address FFF40048 No status was given as to the cause of the TEA assertion 1 56 Computer Group Literature Center Web Site Error Conditions MPU Local Bus Time out Description MPU Notification Status Comments An error occurred while the MPU was attempting to access a local resource TEA is asserted during the MPU access Bit 7 of the MPU Status and DMA Interrupt Count register actually in the DMAC Status register Address FFF40048 The Local Bus timer timed out This usually indicates the MPU tried to read or write an address at which there was no resource Otherwise it indicates a hardware problem DMAC VMEbus Error Description MPU Notification Status Comments DMAC Parity Error Description MPU Notification Status Comments The DMAC experienced a VMEbus error during an attempted transfer DMAC interrupt when enabled The VME bit is set in the DMAC Status register address FFF40048 bit 1 This indicates the DMAC attempted to access a VMEbus address at which there was no resource or the VMEbus slave returned a BERR signal Parity error while the DMAC was reading DRAM DMAC interrupt when enabled
190. gured to model 4MB 8MB 16MB 32MB 64MB or 128MB of ECC protected DRAM In addition to the onboard SDRAM an additional mezzanine of the type used on previous MVME1X7 boards can be plugged in to provide up to 128MB of additional DRAM All DRAM has ECC protection The SDRAM map decoder can be programmed to accommodate different base address es and sizes of mezzanine boards The onboard SDRAM is disabled by a Local Bus reset it must be programmed in order for you to access it Most DRAM devices require some number of access cycles before the DRAMSs are fully operational Normally this requirement is met by the onboard refresh circuitry and normal DRAM initialization However software should insure a minimum of 10 initialization cycles are performed to each bank of RAM Detailed programming information is available in the chapters on the memory options http www motorola com computer literature 1 11 Programming Issues Battery Backed Up RAM and Clock Although the M48T58 70 RAM and clock chip is an 8 bit device the interface provided by the PCCchip2 supports 8 16 and 32 bit accesses to the 48758 No interrupts are generated by the clock Refer to Chapter 3 PCCchip2 and to the M48T58 data sheet for detailed programming guidance and battery life information VMEbus Interface The VMEbus interface is implemented with an ASIC called the VMEchip2 The VMEchip2 includes Two tick timers A watchdog timer
191. hapter discusses those topics in addition to interrupt handling the use of bus timers and the programming interface to each device on the board Programmable registers that reside in ASICs Application Specific Integrated Circuits on the MVME1X7P boards are covered in the chapters devoted to those devices Note The MVMEIXTP s new Petra ASIC performs the functions previously implemented in the MCECC chip For ease of use in conjunction with programming models and documentation developed for earlier boards however the structure of this manual preserves the functional distinctions that formerly characterized the MCECC ASIC The Petra ASIC and Second Generation MVME1X7 Boards Due to rapid changes in technology the production of certain ASICs used on various Motorola first and second generation VME embedded controllers and single board computers has ended The Petra chip was developed to replace these discontinued ASICSs In the case of MVME 1067 177 series boards the discontinued ASIC is the MCECC chip The Petra chip now supplies the functions formerly implemented in the MCECC chip 1 1 Programming Issues The Petra ASIC is functionally compatible with each of the components that it replaces In cases where functionality between ASICs is exclusive configuration switches or jumpers are provided to let you select the desired functionality In several areas of functionality the configuration switches provide backward compatib
192. he addition The adders are enabled by setting bit 11 for map decoder 1 and bit 27 for map decoder 2 in register http www motorola com computer literature 2 27 VMEchip2 FFF40010 The adders allow any size board to be mapped on any 64KB boundary The adders are disabled and the address replacement method is used following reset Write posting is enabled for the segment by setting the write post enable bit in the attribute register Local bus snooping for the segment is enabled by setting the snoop bits in the attribute register The snoop bits in the attribute register are driven on to the local bus when the VMEbus to local bus interface is local bus master VMEbus Slave Ending Address Register 1 ADR SIZ FFF40000 16 bits of 32 BIT 31 iis 16 NAME Ending Address Register 1 OPER R W RESET 0 PS This register is the ending address register for the first VMEbus to local bus map decoder VMEbus Slave Starting Address Register 1 ADR SIZ FFF40000 16 bits of 32 BIT 15 iss 0 NAME Starting Address Register 1 OPER R W RESET 0 PS This register is the starting address register for the first VMEbus to local bus map decoder 2 28 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Ending Address Register 2 ADR SIZ FFF40004 16 bits of 32 BIT 31 A 16 NAME Ending Address Register 2 OPER R W RESET 0 PS This
193. hem is requesting local bus mastership The scrubber then refrains from using the DRAM again for a programmable amount of time Each scrub cycle is made up of a full 39 bit read of DRAM a correction of any single bit errors and a write of the full 39 corrected bits back to the same location If a single or double bit error occurs and if such interrupts are enabled in the control register the local bus master is notified A software bit is available to disable the read portion of the scrub cycle The MCECC sector provides refresh control for the DRAM It performs a single CAS before RAS refresh cycle to the two DRAM blocks approximately once every 15 6 us 4 8 Computer Group Literature Center Web Site Functional Description Arbitration The MCECC sector has three different entities that can request use of the DRAM cycle controller 1 the local bus master 2 the refresher and 3 the scrubber The MCECC pair arbiter accepts requests and provides grants to the requesting entities as follows Priority is highest to lowest refresher local bus and scrubber When no requests are pending the arbiter defaults to providing a local bus grant for fast response to local bus cycles Although the arbiter operates on a priority basis it also performs a pseudo round robin algorithm in order to prevent starving any of the requesting entities Chip Defaults Certain parameters in the Petra MCECC sector have to be
194. high the ACFAIL signal line is active When this bit is low the ACFAIL signal line is not active This bit indicates the status of the SYSFAIL signal line on the VMEbus When this bit is high the SYSFAIL signal line is active When this bit is low the SYSFAIL signal line is not active When this bit is low all interrupts controlled by the VMEchip2 are masked When this bit is high all interrupts controlled by the VMEchip2 are not masked 2 96 Computer Group Literature Center Web Site LCSR Programming Model Control Register 2 ADR SIZ FFF40088 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME GPIOO3 GPIOO2 GPIOOI GPIOOO GPIOI3 GPIOI2 GPIOII GPIOIO OPER R W R W R W R W R R R R RESET OPSL 0 PS 0 PS 0 PS X X X X GPIOO1 Connects to pin 16 of the Remote Status and Control register GPIOO2 Connects to pin 17 of the Remote Status and Control register GPIOO3 Connects to pin 18 of the Remote Status and Control register Not used GPIOI2 Not used GPIOI3 Not used Control Register ADR SIZ FFF40088 8 bits of 32 This function is not used on the MVMEIx7P http www motorola com computer literature 2 97 VMEchip2 Miscellaneous Control Register ADR SIZ FFF4008C 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME MPIRQEN DISSRAM
195. high the second map decoder responds to VMEbus A24 standard access cycles When this bit is low the second map decoder does not respond to VMEbus A24 access cycles http www motorola com computer literature 2 33 VMEchip2 A32 USR SUP When this bit is high the second map decoder responds to VMEbus A32 extended access cycles When this bit is low the second map decoder does not respond to VMEbus A32 access cycles When this bit is high the second map decoder responds to VMEbus user non privileged access cycles When this bit is low the second map decoder does not responded to VMEbus user access cycles When this bit is high the second map decoder responds to VMEbus supervisory access cycles When this bit is low the second map decoder does not respond to VMEbus supervisory access cycles 2 34 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Write Post and Snoop Control Register 1 ADR SIZ FFF40010 8 bits 4 used of 32 BIT 15 14 13 12 11 10 8 NAME ADDER SNP1 WPI 1 OPER R W R W R W RESET OPS OPS OPS This register is the slave write post and snoop control register for the first VMEbus to local bus map decoder 1 SNP1 When this bit is high write posting is enabled for the address range defined by the first VMEbus slave map decoder When this bit is low write posting is disabled for the address range d
196. hip2 ASIC 2 14 printer acknowledge status ACK 3 44 busy status 3 44 data 3 47 data output enable 3 46 fault status 3 44 input prime 3 46 interface 1 14 memory map 1 31 paper error status 3 44 port 1 14 select status 3 44 Printer ACK Interrupt Control register PCCchip2 ASIC 3 39 Printer BUSY Interrupt Control register PCCchip2 ASIC 3 43 Printer Data register PCCchip2 ASIC 3 47 Printer Fault Interrupt Control register PCCchip2 ASIC 3 40 http www motorola com computer literature IN 9 lt moz xXmoz Index Printer Input Status register PCCchip2 ASIC 3 44 Printer PE Interrupt Control register PCCchip2 ASIC 3 42 printer port connection MVME1X7P MVME712M B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 printer port connection diagrams B 1 Printer Port Control register PCCchip2 ASIC 3 45 Printer SEL Interrupt Control register 3 41 Priority PRI arbitration mode VMEbus 2 17 processor to V MEbus transfers 1 12 program access cycles VMEbus 2 33 2 36 program address modifier code VMEbus 2 50 programmable map decoders 2 37 programming DMA controller VMEchip2 ASIC 2 51 GCSR global control status registers VMEchip2 2 102 GCSR base address registers 2 37 LCSR VMEchip2 2 20 local bus interrupter 2 74 local bus to VMEbus map decoders VMEchip2 2 37 local bus to VMEbus requester register 2 51 MPU Status register 2 51 tick and watchdog timers VMEchip2 2 64 tick timers PCCchip2 ASIC 3 1
197. his bit is cleared by writing a 1 to the MCLR bit in this register When this bit is set the MPU received a TEA and the status indicated a parity error during a DRAM data transfer This bitis cleared by writing a 1 to the MCLR bit in this register When this bit is set the MPU received a TEA and no additional status was provided This bit is cleared by writing a 1 to the MCLR bit in this register Writing a 1 to this bit clears the MPU status bits 7 8 9 and 10 MLTO MLOB MLPE and MLBE in this register Computer Group Literature Center Web Site LCSR Programming Model DMAIC The DMAC interrupt counter is incremented when an interrupt is sent to the local bus interrupter The value in this counter indicates the number of commands processed when the DMAC is operated in command chaining mode If the interrupt count exceeds 15 the counter rolls over This counter operates regardless of whether the DMAC interrupts are enabled This counter is cleared when the DMAC is enabled DMAC Status Register ADR SIZ FFF40048 8 bits of 32 BIT 7 6 5 4 3 2 1 0 MLTO DLBE DLOB TBL VME DONE OPER R R R R R R R R RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS This is the DMAC status register DONE VME TBL DLTO DLOB This bit is set when the DMAC has finished executing commands either without errors or because the halt bit was set Thi
198. his bit is high the Board Fail signal is active When this bit is low the Board Fail signal is inactive When this bit is set the VMEchip2 drives SYSFAIL if the inhibit SYSFAIL bit is not set When this bit is set the VMEchip2 is prevented from driving the VMEbus SYSFAIL signal line When this bit is cleared the VMEchip2 is allowed to drive the VMEbus SYSFAIL signal line This bit allows a VMEbus master to reset the local bus Referto the note on local reset in the GCSR Programming Model section earlier in this chapter When this bit is set a local bus reset is generated This bit is cleared by the local bus reset 2 106 Computer Group Literature Center Web Site GCSR Programming Model General Purpose Register 0 ADR SIZ Local Bus FFF40108 VMEbus XXYA 16 bits BIT 15 0 General Purpose Register 0 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose Register 1 ADR SIZ Local Bus FFF4010C VMEbus XXY6 16 bits BIT 15 is 0 NAME General Purpose Register 1 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose R
199. hould include the following steps 2 through 5 Confirm that the Tick Timer 1 interrupt occurred by reading the status of bit 24 in the Interrupter Status register at FFF40068 high indicates an interrupt present Clear the Tick Timer 1 interrupt by writing a 1 to bit 24 of the Interrupt Clear register at FFF40074 Increment a software counter to keep track of the number of interrupts if desired Output a character or some other action such as toggling the FAIL LED on an appropriate count such as 1000 Return from exception Cache Coherency MVME167P The MVME167P s MC68040 processor has the ability to watch Local Bus cycles executed by other Local Bus masters such as the SCSI DMA controller the LAN controller the VMEchip2 DMA controller and the VMEbus to Local Bus controller This bus snooping capability is described in the M68040 Microprocessors User s Manual sections on Cache Coherency and Bus Snooping Operation When snooping is enabled the MC68040 MPU can source data and invalidate cache entries as required by the current cycle The MPU cannot watch VMEbus cycles that do not access the Local Bus Software must http www motorola com computer literature 1 49 Programming Issues ensure that data shared by multiple processors is kept in un cached memory The software must also mark all onboard I O areas as cache inhibited and serialized Cache Coherency MVME177P The MVME177P
200. ility with earlier MVMEI67 177 implementations but you can override their settings in software if you wish A R W by the corresponding register table entry in this manual denotes instances where this override capability is present Where the older technology supported fast page or EDO DRAM chips the Petra memory controllers support SDRAM devices The two memory controllers modeled in Petra duplicate the functionality of the parity memory controller found in the MC ASICs used on certain other boards as well as that of the single bit error correcting double bit error detecting memory controller found in the MCECC ASICs used on the MVME167 177 This Programmer s Reference Guide describes the MCECC model in Chapter 4 In the MVME167 177 application there is logic on the Petra chip to prevent you from inadvertently enabling the MC memory controller model The same SDRAM memory array serves both controller models The SDRAM array is 32 data bits wide with 7 checkbits The array architecture is non interleaved single bank for sizes below 32MB For array sizes above 32MB additional physical memory banks are added but the architecture remains non interleaved A final note on the SDRAM implementation The bandwidth between the SDRAM and local bus is greater than it was with the earlier DRAM array As a result software takes less time to execute Applications that incorporate elapsed time functions which are dependent on code execu
201. imate transfer time on the bus We normally set it to 256 usec This timer can also be disabled for debug purposes Before a single board computer access to another single board computer can complete however the VMEchip2 on the accessed board must decode a slave access and request the Local Bus of the second board When the Local Bus is granted any in process onboard transfers have completed then the Local Bus timer ofthe accessed board starts Normally this is also set to 8 usec When the memory has the data available a transfer acknowledge signal TA is given This translates into a DTACK signal on the VMEbus which is then translated into a TA signal to the first requesting processor and the transfer is complete If the VMEbus global timer expires on a legitimate transfer the VMEbus to Local Bus controller in the VMEchip2 may become confused and the VMEchip2 may misbehave Therefore the bus timer values must be set correctly The correct settings may depend on the system configuration Indivisible Cycles The MVME167P and MVME177P single board computers perform operations that require indivisible read modify write RMW memory accesses These RMW sequences occur when the MMU modifies table entries or when the MPU executes one of the single cycle instructions listed in Table 1 15 Table 1 15 Single Cycle Instructions MPU Instructions MC68040 CAS CAS2 TAS MC68060 CAS CAS2 and misaligned CAS instructions are emulated
202. ingle and double byte write operations return a TEA signal to the local bus Read modify write operations should be used to modify a byte or a two byte of a register Each register definition includes a table with five lines 1 The base address of the register and the number of bits defined in the table 2 The bits defined by this table 3 The name of the register or the name of the bits in the register 2 20 Computer Group Literature Center Web Site LCSR Programming Model 4 The operations possible on the register bits defined as follows R This bit is a read only status bit This bit is readable and writable W AC This bit can be set and it is automatically cleared This bit can also be read Writing a 1 to this bit clears this bit or another bit This bit reads 0 5 Writing a 1 to this bit sets this bit or another bit This bit reads 0 5 The state of the bit following a reset defined as follows The bit is affected by powerup reset The bit is affected by SYSRESET The bit is affected by local reset A rns The bit is not affected by reset Table 2 2 shows a summary of the LCSRs http www motorola com computer literature 2 21 VMEchip2 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 VMEchip2 LCSR Base Address FFF40000 OFFSET T 0 SLAVE ENDING ADDRESS 1 4 SLAVE ENDING
203. interrupt status bit 2 77 Interrupt Vector Base register PCCchip2 ASIC 3 16 interrupt vectors 1 47 SCC modem 3 28 SCC transmit 3 29 interrupter acknowledge interrupter VMEbus 2 19 interrupter control VMEbus 2 61 interrupts broadcast 2 15 2 16 edge sensitive VMEchip2 ASIC 2 74 hardware 1 17 how to use 1 47 LANC 3 5 masked 2 96 tick timer example 1 47 IRQI interrupter VMEbus 2 19 IRQ7 1 interrupters VMEbus 2 19 LAN controller interface 3 3 interface 1 14 LTO error 1 62 offboard error 1 61 parity error 1 61 LANC bus error 3 4 Bus Error Interrupt Control register PCCchip2 ASIC 3 36 Error Status register PCCchip2 ASIC 3 34 interrupts 3 5 LCSR base address 2 20 memory map 2 22 programming model 2 20 LCSR Local Control and Status Registers VMEchip2 2 20 LEDs 2 99 LM SIG register VMEchip2 2 104 local bus accesses from VMEbus 1 46 address counter DMAC 2 59 address range 2 39 base address GCSR 2 100 error sources 1 54 interrupt filters VMEchip2 ASIC 2 98 interrupter summary 2 75 interrupter how to set up 1 48 map decoder registers 2 38 memory map 1 20 1 21 reset 2 106 timeout function 1 17 1 54 timeout value 2 66 Transfer Type TT signals 1 20 local bus interrupter DMAC and 2 12 programming 2 74 VMEchip2 2 18 IN 6 Computer Group Literature Center Web Site local bus interrupter registers I O Control register 1 2 96 I O Control register 2 2 97 I O Control register 3 2 97 Interrupt Level
204. ious on board peripheral devices such as SCSI and LAN controllers Chapter 4 MCECC Functions describes the ECC DRAM controller ASIC MCECC On the MVMEIX7P boards it supplies the interface to a 144 bit wide DRAM memory system Appendix A Summary of Changes lists the modifications that accompanied the introduction of the Petra ASIC on the MVMEI67P and MVME T77P Appendix B Printer and Serial Port Connections contains drawings of the printer and serial port interface connections available with the MVME167P MVME177P and MVME712 series transition board Appendix C Related Documentation lists all documentation related to the MVMEI67P and MVME177P Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 xxii You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document dollar specifies a hexadecimal num
205. ire no read cycle Error Reporting The Petra MCECC sector generates ECC check bits for write cycles It also checks read data from the DRAM and corrects the data if it contains a single bit error If a non correctable error occurs within the read data the Petra MCECC sector so indicates by asserting its non correctable error NCE pin The following paragraphs describe the actions that the MCECC sector will take in different error situations Single Bit Error Cycle Type Burst Read or Non Burst Read 1 Correct the data that is driven to the local MC680x0 bus 2 Do not correct the data in DRAM The DRAM is not corrected until the next scrub of that address which happens only if scrubbing is enabled 3 Terminate the cycle normally Assert to the local bus 4 Log the error if not already logged 5 Notify the local MPU via interrupt if so enabled http www motorola com computer literature 4 5 MCECC Functions Double Bit Error Cycle Type z Burst Read or Non Burst Read You cannot correct the data that is driven to the local MC680x0 bus 1 Leave the error in DRAM Note that the error 1s not corrected in DRAM during the next scrub of that address 2 Terminate the cycle with Bus Error assert TEA to the local bus if so enabled 3 Log the error if not already logged 4 Notify the local MPU via interrupt if so enabled Triple or Greater Bit Error Cycle Type Burst Read or Non Burst Read S
206. is register are termed pseudo interrupt acknowledge cycles because they are normal read cycles on the Local Bus side but they are interrupt acknowledge cycles on the CD2401 side of the PCCchip2 They are necessary to support polled mode operation with the CD2401 Note If this register is read when an interrupt is not present the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled MIV7 MIVO Modem interrupt vector bits 7 0 reflect the modem interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle http www motorola com computer literature 3 31 PCCchip2 Transmit PIACK Register ADR SIZ FFF42025 8 bits BIT 23 22 21 20 19 18 17 16 NAME TIV7 TIV6 TIV5 TIVA TIV3 TIV2 TIVI TIVO OPER R R R R R R R R RESET X X X X X X X X The Transmit PIACK Register is used to execute transmit pseudo interrupt acknowledge cycles to the CD2401 When the Local Bus master initiates a read cycle to this register the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with 7 0 02 Note that the PILRI register in the CD2401 should be set to the same value 02 for the interrupt acknowledge cycle to operate properly To finish the local read cycle the PCCchip2 drives the vector received from the CD2401 onto the local data bus and asserts TA Reads to this register are termed pseudo interrupt acknowledge cycle
207. is 1 it indicates that the scrubber was accessing DRAM If ESCRB is 0 it indicates that the local MC680x0 bus master was accessing DRAM ERD reflects the state of the local bus READ signal pin at the last logging of a single or double bit error ERD 1 corresponds to READ high and ERD 0 to READ low ERD is meaningless if ESCRB is set http www motorola com computer literature 4 27 MCECC Functions ERRLOG When set ERRLOG indicates that a single or a double bit error has been logged by this MCECC and that no more will be logged until the error is cleared The bit can only be set by logging an error and cleared by writing a 1 to it When ERRLOG is cleared the MCECC is ready to log a new error Note that because hardware duplicates control register writes to both MCECCs clearing ERRLOG in MCECC sector clears it in the other Any available error information in either MCECC should be recovered before clearing ERRLOG Error Address Bits 31 24 This register reflects the value that was on bits 31 24 of the local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43060 2nd FFF43160 8 bits BIT 31 30 29 28 27 26 25 24 NAME EA31 EA30 29 EA28 EA27 26 25 EA24 OPER R R R R R R R R RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS OPLS Error Address Bits 23 16 This register reflects the value that was on bits 23 16 of the
208. is accomplished by jumpers on the transition module For more information refer to the user s manual for the MVME712M Connection Diagrams The following figures illustrate the connection diagrams for the MVMETI2M transition module Figure Number Figure MVMEI67P 177P Printer Port with MVME7I2M Figure B 2 MVME167P 177P Serial Port 1 Configured as DCE Figure B 3 MVME167P 177P Serial Port 2 Configured as DCE Figure B 4 MVME167P 177P Serial Port 3 Configured as DCE Figure B 5 MVME167P 177P Serial Port 4 Configured as DCE Figure B 6 MVME167P 177P Serial Port 1 Configured as DTE Figure B 7 MVME167P 177P Serial Port 2 Configured as DTE Figure B 8 MVME167P 177P Serial Port 3 Configured as DTE Figure B 9 MVME167P 177P Serial Port 4 Configured as DTE Name B 1 Printer and Serial Port Connections AS8Hd dNiHd 91534 N3dd lt 2 gt 0 5 lt 9 gt 9 5 lt s gt avs lt gt 995 lt 5 gt 0 5 lt z gt YS lt 1 gt 9 5 lt 0 gt YS 0v6 ZvEl a AA AE er ot hye ap ae Ig E tare es li gee PROMIT erre
209. is bit reads zero Writing a 1 to the bit sets it or another bit This bit reads 0 The possible states of the bits after local software and power up reset are as defined below P The bit is affected by power up reset L The bit is affected by local reset 5 The bit is affected by software reset Writing 0F to the Chip ID register X The bit is not affected by reset V The effect of reset on this bit is variable 4 10 Computer Group Literature Center Web Site Programming Model Table 4 3 MCECC Sector Internal Register Memory Map MCECC Sector Base Address FFF43000 1st board FFF43100 2nd board Register Register Bit Names Offset Name D31 D30 D29 D28 D27 D26 D25 D24 00 CHIP ID CID7 CID6 CID5 CID4 CID3 CID2 CID1 CIDO 04 CHIP REV7 REV6 REV5 REV47 REV3 REV2 REVI REVO REVISION 08 MEMORY 0 0 FSTRD 1 0 MSIZ2 MSIZI MSIZO CONFIG 0C 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 14 BASE BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 ADDRESS 18 DRAM BAD23 BAD22 RWB5 RWB4 RWB3 NCEIEN NCEBEN RAMEN CONTROL 1C BCLK BCK7 BCK6 BCK5 BCK47 BCK3 BCK2 BCKO FREQUENCY 20 DATA 0 0 DERC ZFILL RWCKB 0 0 0 CONTROL 24 SCRUB 0 0 0 SCRB SCRBEN 0 SBEIEN RWBO CONTROL 28 SCRUB SBPDI5 SBPD14 SBPD13 SBPDI2 SBPDII SBPDIO SBPD9 SBPD8 PERIOD 2C SCRUB SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBPD1 SBPDO7 PERIOD 30 CHIP CPS7 CPS6 CPS5 CPS4 C
210. is counter is programmed with the starting address of the data in VMEbus memory DMAC Byte Counter ADR SIZ FFF40040 32 bits BIT 31 0 DMAC Byte Counter OPER R W RESET 0 PS In direct mode this counter is programmed with the number of bytes of data to be transferred Table Address Counter ADR SIZ FFF40044 32 bits BIT 31 ur 0 NAME Table Address Counter OPER R W RESET OPS In command chaining mode this counter should be loaded by the processor with the starting address of the list of commands This register gets reloaded by the DMAC with the starting address of the current command The last command in a list should have bits 0 and 1 set in the next command pointer 2 60 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Interrupter Control Register ADR SIZ FFF40048 8 bits 7 used of 32 BIT 3 30 29 28 27 26 25 24 18015 IRQC IRQS IRQL OPER R W S R S RESET 0 PS OPS OPS 0 PS This register controls the VMEbus interrupter IRQL IRQS IRQC IRQIS These bits define the level of the VMEbus interrupt generated by the VMEchip2 A VMEbus interrupt is generated by writing the desired level to these bits These bits always read 0 and writing 0 to these bits has no effect This bit is the IRQ status bit When this bit is high the VMEbus interrupt has not been acknowledged
211. is interrupted The DMAC control is divided into two registers The first register is only accessible by the processor The second register can be loaded by the processor in direct mode and by the DMAC in command chaining mode Once the DMAC is enabled the counter and control registers should not be modified by software When you use the command chaining mode the list of commands must be in local 32 bit memory and the entries must be quad byte aligned A DMAC command list includes one or more DMAC command packets A DMAC command packet includes a control word that defines the VMEbus AM code the VMEbus transfer size the VMEbus transfer method the DMA transfer direction the VMEbus and local bus address counter operation and the local bus snoop operation The format of the control word is the same as the lower 16 bits of the control register The command packet also includes a local bus address a VMEbus address a byte count and a pointer to the next command packet in the list The end of a command is indicated by setting bit 0 or 1 of the next command address Table 2 3 shows the command packet format Computer Group Literature Center Web Site LCSR Programming Model Table 2 3 DMAC Command Packet Format Entry Function 0 bits 0 15 Control Word 1 bits 0 31 Local Bus Address 2 bits 0 31 VMEbus Address 3 bits 0 31 Byte Count 4 bits 0 31 Address of Next Command Packet DMAC Registers
212. is manual and to the user s guide for each device to determine its port size data bus connection and any restrictions that apply when accessing the device EEPROMs on the MVME1X7P MVME167 Both boards include 44 pin PLCC CLCC sockets for EEPROMs organized as follows Model Sockets Banks MVMEI167 4 2 MVME177 2 1 The MVME167P boards use 27C102JK or 27C202JK type EEPROMs The MVME177 boards use SGS Thompson M27C4002 256K x 16 or AMD 27C4096 type EEPROMs The EEPROMs are organized as 32 bit wide banks that support 8 16 and 32 bit read accesses The MVME177 has Flash memory in addition to EEPROM The EEPROMs are mapped to Local Bus address 0 following a Local Bus reset This allows the MC68040 to access the stack pointer and execution address following a reset The EEPROMs are controlled by the VMEchip2 ASIC The map decoder the access time and the time they appear at address 0 are programmable parameters Refer to Chapter 2 VM Echip2 for more detail 1 8 Computer Group Literature Center Web Site Programming Interfaces MVME177 The EEPROMs on the MVME177 share 2MB of memory with the first 2MB of Flash memory The EEPROM can co exist with 2MB of Flash or you may wish to program all 4MB as Flash memory The Flash and EEPROM configuration is jointly controlled by a configuration switch S4 as described in Chapters 1 and 4 of MVME177P Single Board Computer Installation and Use and by contr
213. ister is 6 VBRI 7 i e setting the Vector Base register at address FFF40088 to 67xxxxxx This produces a Vector Base0 of 60 corresponding to the X in Table 2 4 and a Vector Basel of 70 corresponding to the in Table 2 4 http www motorola com computer literature 2 95 VMEchip2 Control Register 1 ADR SIZ FFF40088 8 bits of 32 BIT 23 21 20 19 18 17 16 NAME MIEN SYSFL ACFL ABRTL GPOEN3 GPOEN2 GPOENI GPOENO OPER R W R R R W R W R W R W RESET OPSL X X 0 PS 0 PS 0 PS 0 PS This register is a general purpose I O control register Bits 16 19 control the direction of the four General Purpose I O pins GPIOO 3 GPOENO 1 GPOEN2 GPOEN3 ABRTL ACFL SYSFL MIEN When this bit is low the GPIOO pin is an input When this bit is high the GPIOO pin is an output When this bit is low GPIO1 pin is an input When this bit is high the GPIOI pin is an output When this bit is low the GPIO2 pin is an input When this bit is high the GPIO2 pin is an output When this bit is low the GPIO3 pin is an input When this bit is high the GPIO3 pin is an output This bit indicates the status of the ABORT switch When this bit is high the ABORT switch is depressed When this bit is low the ABORT switch is not depressed This bit indicates the status of the ACFAIL signal line on the VMEbus When this bit is
214. it Error Cycle Type Scrub 1 Do not perform the write portion of the cycle This causes the location to continue to indicate a non correctable error when accessed 2 Log the error if not already logged 3 Notify the local MPU via interrupt if so enabled Triple or Greater Bit Error Cycle Type Scrub Some of these errors are detected correctly and are treated the same as a double bit error The rest may show up as no error or single bit error both of which are incorrect http www motorola com computer literature 4 7 MCECC Functions Error Logging Scrub Refresh ECC error logging is facilitated by the Petra MCECC sector because of its internal latches When an error single or double bit occurs in the to which the MCECC sector is connected it freezes the address of the error and the syndrome bits associated with the data that is in error Each MCECC sector segment performs this logging function independently of the other Once the MCECC sector has logged an error it does not log any new errors that occur until the ERRLOG control status bit has been cleared by software The MCECC sector contains programmable registers and circuitry to implement the memory scrubbing function Programmable registers determine how often the entire DRAM is scrubbed During a scrub the scrubber holds the memory for a programmable amount of time and then releases it for the local bus or for a refresher if one of t
215. iterature 3 37 PCCchip2 SCSI Interrupt Control Register ADR SIZ FFF4202F 8 bits BIT 7 6 2 4 3 2 1 0 NAME IRQ IEN IL2 IL1 ILO OPER R W R W R R W R W R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level for the SCSI Processor Level 0 does not generate an interrupt Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low IRQ Interrupt Status This status bit reflects the state of the IRQ pin of the SCSI Processor qualified by the IEN bit When this bit is high a SCSI processor interrupt is being generated at the level programmed in IL2 ILO if nonzero This status bit does not need to be cleared because it is not edge sensitive Computer Group Literature Center Web Site Programming Model Programming the Printer Port This section provides addresses and bit level descriptions of the printer port control status and data registers Printer ACK Interrupt Control Register ADR SIZ FFF42030 8 bits BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the printer ACK Level 0 does not generate an interrupt ICLR In edge sen
216. itive mode This bit is always read as zero When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a printer FAULT interrupt is being generated at the level programmed in IL2 ILO if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a falling edge low level of the PRFAULTI pin When this bit is high interrupt is activated by a rising edge high level of the PRFAULTI pin Note that if this bit is changed while the E L bit is set or is being set a FAULT interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the E L bit 3 40 Computer Group Literature Center Web Site Programming Model Printer SEL Interrupt Control Register ADR SIZ FFF42032 8 bits BIT 15 14 13 12 11 10 9 8 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the printer SEL Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as zero IEN When this bit is high the interrupt is enabl
217. l is programmed as an output and set low bus errors are processed in the following way The 82596CA interface logic monitors all bus cycles initiated by the 82596CA and if a bus error is indicated TEA 0 and 1 the interface logic asserts the TA signal to terminate the bus cycle The LANC Error Status Register in the PCCchip2 is updated and a LANC bus error interrupt is generated if it is enabled in the PCCchip2 In this case the 82596CA continues to operate and because the cycle was terminated with an error the 82596CA may transmit bad data or corrupt memory LANC Interrupt When the PCCchip2 detects a high level on the INT signal from the 82596CA if such interrupts are enabled it generates an interrupt to the MPU If the C040 bit is set the interrupt request goes to the MPU via the EIPL pins at the level that is programmed for LANC interrupts in the LANC Interrupt Control Register If the C040 bit is cleared the interrupt goes to the MPU via the INT pin if the level that is programmed for LANC interrupts in the LANC Interrupt Control Register is higher than the level set in the Interrupt Mask Level Register When the MPU acknowledges the LANC interrupt the PCCchip2 responds with the vector that corresponds to LANC interrupts http www motorola com computer literature 3 5 PCCchip2 53C710 SCSI Controller Interface The PCCchip2 provides a map decoder and an interrupt handler for the NCR 53C710 SCSI I O
218. le meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do not handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local
219. learing all of the STON bits and setting all of the STOFF bits in the Scrub Time On Time Off register A v N Set the DERC and RWCKB bits in the Data Control register Perform the desired read and or write checkbit operations Clear the DERC and RWCKB bits in the Data Control register Perform the desired testing related to the location locations that have had their checkbits altered 6 Allow the scrubber to proceed by restoring the STON and STOFF bits to their original state ZFILL DERC ZERO FILL memory when set forces all zeros to be written to the DRAM during any kind of write cycle or scrub cycle It is intended for use with the zero fill function refer to the section on nitialization at the end of this chapter This bit should be cleared for normal system operation When ZFILL is set the read portion of a scrub cycle is suppressed and writes of all zeros are executed DISABLE ERROR CORRECTION when set to 1 disables single bit error correction by the Petra MCECC sector Specifically data read from the DRAM array is presented to the local MC680x0 data bus unaltered Less than line write data performs a read modify write without correcting single bit errors that may occur on the read portion of the read modify write Note that DERC does not affect the generation of check bits DERC should be 4 18 Computer Group Literature Center Web Site Programming Model cleared during normal system opera
220. local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43064 2nd FFF43164 8 bits BIT 31 30 29 28 27 26 25 24 NAME 23 EA22 EA21 EA20 19 18 EA17 EAI6 OPER R R R R R R R R RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0PLS 4 28 Computer Group Literature Center Web Site Programming Model Error Address Bits 15 8 This register reflects the value that was on bits 15 8 of the local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43068 2nd FFF43168 8 bits BIT 31 30 29 28 27 26 25 24 NAME 15 14 EAI3 EA12 10 EA9 EA8 OPER R R R R R R R RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS OPLS Error Address Bits 7 4 This register reflects the value that was on bits 7 4 of the local MC680x0 bus at the last logging of an error ADR SIZ 1st FFF4306C 2nd FFF4316C 8 bits BIT 31 30 29 28 27 26 25 24 NAME EA7 EA6 5 4 0 0 0 0 OPER R R R R R R R OPLS OPLS OPLS OPLS X X X X http www motorola com computer literature 4 29 MCECC Functions Error Syndrome Register Defaults Register 1 ADR SIZ 1st FFF43070 2nd FFF43170 16 bits BIT 31 30 29 28 27 26 25 24 NAME 0 S6 55 54 53 52 51 50 OPER R R R R R R
221. local bus interface allows off board VMEbus masters access to local on board resources The address of the local resources as viewed from the VMEbus is controlled by the VMEbus slave map decoders which are part of the V MEbus to local bus interface Two VMEbus slave map decoders in the VMEchip2 allow two segments of the VMEbus to be mapped to the local bus A segment may vary in size from 64KB to 4GB in increments of 64KB Address translation is provided by the address translation registers The upper 16 bits of the local bus address come from the address translation address register rather than from the upper 16 bits of the VMEbus address Each VMEbus slave map decoder has the following registers address translation address register address translation select register starting address register ending address register address modifier select register and attribute register The tables on the following pages list the addresses and bit definitions of these registers The VMEbus slave map decoders described in this section are disabled by local reset SYSRESET or power up reset Use caution when enabling the map decoders or when modifying their registers after they are enabled The safest time to enable or modify the map decoder registers is when the VMEchip2 is VMEbus master To modify the map decoder registers follow this procedure Set the DWB bit in the LCSR and then wait for the DHB bit in the LCSR to be set indicating that VMEbus mast
222. low that they represent Data and address sizes are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant A word is 16 bits numbered 0 through 15 with bit 0 being the least significant A longword is 32 bits numbered 0 through 31 with bit 0 being the least significant xxiv The terms control bit status bit true and false are used extensively in this document The term control bit is used to describe a bit in a register that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions XXV xxvi Programming Issues Introduction The MVME167P and MVME177P single board computers are complex boards that interface both to the VMEbus and the SCSI bus From a programming standpoint their multiple bus interfaces raise issues of cache coherency and support of indivisible cycles There are also various potential sources of bus error This c
223. made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and
224. me 2 20 Programming the VMEbus Slave Map 2 26 VMEbus Slave Ending Address Register 1 cec 2 28 VMEbus Slave Starting Address Register 22 2 2 2 28 VMEbus Slave Ending Address Register 2 recettes 2 29 VMEbus Slave Starting Address Register 2 2 2 222 2 29 VMEbus Slave Address Translation Address Offset Register 1 2 29 VMEbus Slave Address Translation Select Register 1 2 30 VMEbus Slave Address Translation Address Offset Register 2 2 31 VMEbus Slave Address Translation Select Register 2 2 31 VMEbus Slave Write Post and Snoop Control Register 2 2 32 VMEbus Slave Address Modifier Select Register 2 2 33 VMEbus Slave Write Post and Snoop Control Register 1 2 35 VMEbus Slave Address Modifier Select Register 1 2 36 Programming the Local Bus to VMEbus Map 2 37 Local Bus Slave VMEbus Master Ending Address Register 1 2 39 Local Bus Slave VMEbus Master Starting Address Register 1 2 40 Local Bus Slave VMEbus Master Ending Address Register 2 2 40 Local Bus Slave VMEbus Master Starting Addres
225. mputer Group Literature Center Web Site Programming Model General Purpose Input Output Pin Control Register ADR SIZ FFF42019 8 bits BIT 23 22 21 20 19 18 17 16 NAME GPI GPOE GPO OPER R R R R R R R W R W RESET 0 0 0 0 0 X 0 PL 0 PL GPO When GPO is set and GPOE is set the GPIO pin is at a logic high level When GPO is cleared and GPOE is set the GPIO pin is at a logic low level GPOE This bit controls whether or not the PCCchip2 drives the GPIO pin When GPOE is set the PCCchip2 drives the GPIO pin When GPOE is cleared the PCCchip2 does not drive the GPIO pin GPI This bit reflects the state of the GPIO pin It is set when GPIO is high and cleared when GPIO is low On the Single Board Computers the PCCGPIO1 pin is connected to the remote reset connector pin 19 Tick Timer 2 Interrupt Control Register ADR SIZ FFF4201A 8 bits BIT 15 14 13 12 11 10 9 8 NAME INT IEN ICLR IL2 IL1 ILO OPER R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level for Tick Timer 2 Level 0 does not generate an interrupt ICLR Writing a logic 1 into this bit clears the INT status bit This bit is always read as zero IEN Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low http www motorola com
226. mputer literature 2 19 VMEchip2 The interrupt handler provides all logic necessary to identify and handle all local interrupts as well as VMEbus interrupts When a local interrupt is acknowledged a unique vector is provided by the chip Edge sensitive interrupters are not cleared during the interrupt acknowledge cycle and must by reset by software as required If the interrupt source is the VMEbus the interrupt handler instructs the VMEbus master to execute a VMEbus IACK cycle to obtain the vector from the VMEbus interrupter The chip connects to all signals that a VMEbus handler is required to drive and monitor On the local bus the interrupt handler is designed to comply with the interrupt handling signaling protocol of the MC680x0 microprocessor Global Control and Status Registers The VMEchip2 ASIC includes a set of registers that are accessible from both the VMEbus and the local bus These registers are provided to aid in interprocessor communications over the VMEbus These registers are fully described in a later section LCSR Programming Model This section defines the programming model for the Local Control and Status registers LCSR in the VMEchip2 ASIC The local bus map decoder for the LCSR is included in the VMEchip2 The base address of the LCSR is FFF40000 and the registers are 32 bits wide Single byte double byte and quad byte read operations are permitted but single byte and double byte write operations are not S
227. n DRAM access time RWB3 Read Write Bit 3 is a general purpose read write bit RWB4 Read Write Bit 4 is a general purpose read write bit RWB5 Read Write Bit 5 is a general purpose read write bit BAD22 BAD23 These are the lower two bits of the DRAM base address described in the previous register BCLK Frequency Register The Bus Clock BCLK Frequency register should be programmed with the hexadecimal value of the operating clock frequency in MHz i e 19 for 25MHz and 21 for 33MHz The MCECC sector pair uses the value programmed in this register to control the Prescaler counter The Prescaler counter increments to FF and then it is loaded with the two s complement of the value in the BCLK Frequency register This produces a 1MHz clock that is used by the refresh timer and the scrubber When the BCLK Frequency register is correctly programmed with the BCLK frequency the DRAMs are refreshed approximately once every 15 6 microseconds After power up this register is initialized to 19 for 25MHz 4 16 Computer Group Literature Center Web Site Programming Model Note This register is configured only during power up reset and is unchanged by software or local reset ADR SIZ 1st FFF4301C 2nd FFF4311C 8 bits BIT 31 30 29 28 27 26 25 24 NAME BCK7 BCK6 BCKS BCK4 BCK3 BCK2 BCKO OPER R W R W R W R W R W R W R W 1 1 1
228. n done or no data These bits define the minimum time the DMAC spends 0 8 us 1 64 us 2 256 Us 3 The timer is disabled on the VMEbus 0 16 us 4 1 32 us 5 2 64 us 6 3 128 us 7 off the VMEbus 0 0 us 4 1 16 us 5 2 32 us 6 3 64 us 7 128 us 256 Us 512 us 1024 us http www motorola com computer literature 2 65 VMEchip2 VME Access Local Bus and Watchdog Time out Control Register ADR SIZ FFF4004C 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME VATO LBTO WDTO OPER R W R W R W RESET 0 PS 0 PS 0 PS WDTO These bits define the watchdog time out period Bit Encoding Time out Bit Encoding Time out 0 512 us 8 128 ms 1 1 028 9 256 ms 2 2 10 512 105 3 4 ms 11 11 4 8 ms 12 4 s 5 16 ms 13 16 6 32 ms 14 32 5 7 64 ms 15 64 5 These bits define the local bus time out value The timer begins timing when TS is asserted on the local bus If TA or TAE is not asserted before the timer times out a TEA signal is sent to the local bus The timer is disabled if the transfer is bound for the VMEbus 0 86 2 256 1 64 3 The timer is disabled VATO These bits define the VMEbus access time out value When a transaction is headed to the VMEbus and the VMEchip2 is not the current VMEbus master the access timer begins timing If the VMEchip2 has not received bus mastership before
229. n monitor bits are set by writing a 1 to the corresponding bit in the location monitor register LMO and LM1 can also be set by writing a 1 to the corresponding clear bits in the local interrupt clear register The Interrupt Control register provides four bits that allow the VMEbus to interrupt the local bus An interrupt is sent to the local bus interrupter when one of the bits is set If the interrupt is enabled in the local bus interrupter then a local bus interrupt is generated The interrupt bits are cleared by writing a 1 to the corresponding bit in the interrupt clear register The Board Control register allows a VMEbus master to reset the local bus prevent the VMEchip2 from driving the SYSFAIL signal line and detect if the VMEchip2 wants to drive the SYSFAIL signal line The six General Purpose registers can be read and written from both the local bus and the VMEbus These registers are provided to allow local bus masters to communicate with VMEbus masters The function of these registers is not defined by this specification The GCSR supports read modify write cycles such as TAS The GCSR allows a VMEbus master to reset the local bus This feature is very dangerous and should be used with caution Caution The local reset feature is a partial system reset not a complete system reset such as powerup reset or SYSRESET When the local bus reset signal is asserted a local bus cycle may be aborted The VMEchip2 is connected to both the
230. ne the VMEbus release mode for the DMAC requester The DMAC always releases the bus when the FIFO is full VMEbus to local bus or empty local bus to VMEbus 0 Release when the time on timer has expired and a BRx signal is active on the VMEbus 1 Release when the time on timer has expired 2 Release when a BRx signal is active on the VMEbus 3 Release when a BRx signal is active on the VMEbus or the time on timer has expired DFAIR When this bit is high the DMAC requester operates in fair mode It waits until its request level is inactive before requesting the VMEbus When this bit is low the DMAC requester does not operate in fair mode DTBL The DMAC operates in direct mode when this bit is low and it operates in command chaining mode when this bit is high DEN The DMAC is enabled when this bit is set high This bit always reads 0 DHALT When this bit is high the DMAC halts at the end of a command when the DMAC is operating in command chaining mode When this bit is low the DMAC executes the next command in the list 2 56 Computer Group Literature Center Web Site LCSR Programming Model DMAC Control Register 2 bits 8 15 ADR SIZ FFF40034 8 bits 7 USED of 32 BIT 15 14 13 12 11 10 9 8 NAME INTE SNP VINC LINC TVME D16 OPER R W R W R W R W R W R W RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS This portion of the control register is loaded by the processor or by
231. ng the interrupt clear bit in the control register because the interrupt is never acknowledged on the VMEbus The VMEchip2 allows the output of one of the tick timers to be connected to the IRQI interrupt signal line on the VMEbus When this function is enabled a pulse appears on the IRQI signal line at the programmed interrupt rate of the tick timer 2 16 Computer Group Literature Center Web Site Functional Blocks VMEbus System Controller With the exception of the optional SERCLK driver and the Power Monitor the chip includes all the functions that a VMEbus system controller must provide The system controller is enabled disabled with the aid of an external jumper J1 the only jumper required in a VMEchip2 based VMEbus interface Arbiter The arbitration algorithm used by the chip arbiter is selected by software All three arbitration modes defined in the VMEbus Specification are supported Priority PRI Round Robin Select RRS as well as Single SGL When operating in the PRI mode the arbiter asserts the BCLR line whenever it detects a request for the bus whose level is higher that the one being serviced The chip includes an arbitration timer preventing a bus lockup when no requester assumes control of the bus after the arbiter has issued a grant Using a control bit this timer can be enabled or disabled When enabled it assumes control of the bus by driving the BBSY signal after 256 usecs releasing it after sati
232. nt Logic In support of possible future configurations in which the MVME1X7P might be offered as a single board computer without the VMEbus interface certain logic in the VMEchip2 has been duplicated in the Petra chip Table 1 2 shows the location of the overlapping logic As long as the VMEchip2 ASIC is present the redundant logic is inhibited in the Petra chip Note that the ABORT switch logic in the VMEchip2 is not used Likewise unused are the GPI inputs to the VMEchip2 which are located at FFF40088 bits 7 0 Instead the ABORT switch interrupt is integrated into the Petra ASIC at location FFF42043 The GPI inputs are integrated into the Petra ASIC at location FFF4202C bits 23 16 Computer Group Literature Center Web Site Functional Description Table 1 2 Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Notes Address Bit Address Bit FFF40060 28 24 FFF42044 28 24 1 5 FFF40060 22 19 FFF42044 22 19 2 5 17 16 17 16 FFF4004C 13 8 FFF42044 13 8 3 5 FFF40048 7 FFF42048 8 4 FFF40048 9 FFF42048 9 4 5 FFF40048 10 FFF42048 10 4 5 FFF40048 11 FFF42048 11 4 5 FFF40064 31 0 FFF4204C 3 0 8 FFF42040 6 0 6 FF800000 FFBFFFFF 31 0 FF800000 FFBFFFFF 31 0 7 FFE00000 FFEFFFFF 31 0 Programmable 31 0 7 Notes 1 RESET switch control 2 Watchdog timer control 3 Access and watchdog timer parameters 4 MPU TEA bus error status
233. ntrols the strobe timing When this bit is high the printer strobe is activated When this bit is low the printer strobe is not activated This bit has no function in auto mode http www motorola com computer literature 3 45 PCCchip2 INP DOEN Chip Speed Register Printer Input Prime This bit controls the input prime signal When this bit is high the input prime signal is activated When this bit is low the input prime signal is not activated Software must control the timing of the printer input prime signal Printer Data Output Enable This bit controls the external data buffer for the printer port When this bit is high the external printer data buffer is enabled When this bit is low the external printer data buffer is disabled For normal connection to a printer DOEN should be set to 1 ADR SIZ FFF42038 16 bits BIT 31 16 NAME CS31 C816 OPER R RESET X CS31 CS16 This read only register is for factory test purposes only 3 46 Computer Group Literature Center Web Site Programming Model Printer Data Register ADR SIZ FFF4203A 16 bits BIT 15 0 NAME PD15 PDO OPER R W RESET X PD15 PD0 Writing to these bits causes the PCCchip2 to latch data into the external printer data buffer Generally the printer data buffer only connects to PD7 PDO because most printer data paths are 8 bits wide PD7 PDO can be accessed as an 8 bit register
234. ogrammable decoders while the other two are fixed and are dedicated for I O decoding The first four map decoders compare local bus address lines A31 through A16 with a 16 bit start address and a 16 bit end address When an address in the selected range is detected a VMEbus select is generated to the VMEbus master Each map decoder also has eight attribute bits and an enable bit The attribute bits are for VMEbus AM address modifier codes D16 enable and write post WP enable The fourth map decoder also includes a 16 bit alternate address register and a 16 bit alternate address select register This allows any or all of the upper 16 address bits from the local bus to be replaced by bits from the alternate address register The feature allows the local bus master to access any VMEbus address 24 Computer Group Literature Center Web Site Functional Blocks 0v6 vvEL uarsio3H SNLVLS 1V8019 ssayqqv TOYXLNOD viva Ss3uaav Ss3uaav 7051405 7TOH1INOO viva uso5 H3T10HINOO 55 7031409 7051405 gt Ss3udav 7031405 7051405 viva viva viva gt H31S VW SNEAWA S31A8 t A8 AHIN3 91 lt 5 7051409 lt viva 7031405 1OH LNOO 5 7051409 4
235. ol bit GPIO2 in the VMEchip2 ASIC as described in Chapter 2 VMEchip2 The EPROMs are mapped to Local Bus address 0 following a Local Bus reset This allows the MC68060 processor to access the reset vector and execution address following a reset Flash Memory on the MVME177 The MVME177 includes four 28F008SA Flash memory devices The 32 bit wide Flash can support 8 16 and 32 bit accesses The Flash can be used for the onboard debugger firmware which can be downloaded from T O resources such as Ethernet SCSI serial port or VMEbus Flash write protection is programmable by setting a control bit GPIO bit 1 in the VMEchip2 GPIO register after downloading When the Flash memory is used with EEPROM only the top or bottom 2MB of Flash memory is visible at any one time For access to the shadowed area of Flash the 177Bug firmware provides the SFLASH command The MVME177 is shipped with the top 2MB of Flash memory and EEPROM mapped as illustrated by Map 2 in Figure 1 3 The 177Bug is shipped in EEPROM To map all 4MB of Flash and retain access to the 177Bug perform the following steps 1 Map Flash and EEPROM as shown in Map 3 in Figure 1 3 2 Copy the 177Bug into the bottom 2MB of Flash memory 3 Remap Flash memory as shown in Map 1 in Figure 1 3 http www motorola com computer literature 1 9 Programming Issues FFBFFFFF FF800000 MAP 2 MAP 1 as shipped MAP 3 FFBFFFFF
236. ome of these errors are detected correctly and are handled the same as a double bit error The rest may show up as no error or single bit error both of which are incorrect Cycle Type Burst Write Because all of the bits are written during a burst write no checking is done Single Bit Error Cycle Type Non Burst Write 1 Correct the data read from the DRAM merge with the write data and write the correct merged data to the DRAM 2 Terminate the cycle normally Assert to the local bus 3 Log the error if not already logged 4 Notify the local MPU via interrupt if so enabled Double Bit Error Cycle Type Non Burst Write 1 Do not perform the write portion of the cycle This causes the location to continue to indicate a non correctable error when accessed 2 Terminate the cycle normally Assert TA to the local bus 3 Log the error if not already logged 4 6 Computer Group Literature Center Web Site Functional Description 4 Notify the local MPU via interrupt if so enabled Triple or Greater Bit Error Cycle Type Non Burst Write Some of these errors are detected correctly and are handled the same as a double bit error The rest may show up as no error or single bit error both of which are incorrect Single Bit Error Cycle Type Scrub 1 Write corrected data to the DRAM 2 Log the error if not already logged 3 Notify the local MPU via interrupt if so enabled Double B
237. on Size Translation Select Value Select Value 64KB FFFF 32MB FE00 128KB FFFE 64MB 00 256 FFFC 128MB F800 512KB FFF8 256MB F000 FFFO 512MB E000 2MB FFEO 1GB C000 4MB FFCO 2GB 8000 8MB FF80 4GB 0000 16MB FF00 http www motorola com computer literature 2 31 VMEchip2 VMEbus Slave Write Post and Snoop Control Register 2 ADR SIZ FFF40010 8 bits 4 used of 32 BIT 31 30 29 28 27 26 25 24 NAME ADDER SNP2 WP2 2 OPER R W R W R W RESET 0 PS 0 PS 0 PS This register is the slave write post and snoop control register for the second VMEbus to local bus map decoder WP2 When this bit is high write posting is enabled for the address range defined by the second VMEbus slave map decoder When this bit is low write posting is disabled for the address range defined by the second VMEbus slave map decoder SNP2 These bits control the snoop enable lines to the local bus for the address range defined by the second VMEbus slave map decoder The snooping functions differ according to processor type as shown SNP2 Requested Snoop Operation 26 25 MC68040 MC68060 0 0 Snoop disabled Snoop enabled 0 1 Source dirty sink byte word longword Snoop disabled 1 0 Source dirty invalidate line Snoop enabled 1 1 Snoop disabled Reserved Snoop disabled ADDER2 When this bit is high the adder is used for address translation When this bit is low the adde
238. oop Operation MC68040 MC68060 Snoop disabled Snoop enabled Source dirty sink byte word longword Snoop disabled Source dirty invalidate line Snoop enabled o Snoop disabled Reserved Snoop disabled INTE This bitis used only in command chaining mode It is only modified when the DMAC loads the control register from the control word in the command packet When this bit in the command packet is set an interrupt is sent to the local bus interrupter when the command in the packet has been executed The local bus is interrupted if the DMAC interrupt is enabled DMAC Control Register 2 bits 0 7 ADR SIZ FFF40034 8 bits of 32 BIT 7 5 4 3 2 1 0 NAME BLK VME AM OPER R W R W RESET OPS OPS This portion of the control register is loaded by the processor or the DMAC when it loads the command word from the command packet Because this byte is loaded from the command packet in command chaining mode the descriptions here also apply to the control word in the command packet VME AM These bits define the address modifier codes the DMAC drives on the VMEbus when it is bus master During non block transfer cycles bits 0 5 define the VMEbus address modifiers During block transfers bits 2 5 define 2 58 Computer Group Literature Center Web Site LCSR Programming Model VMEbus address modifier bits 2 5 and address modifier bits 0 and 1 are pr
239. or Status register SFFFA201C SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2 Parity error while the LANCE was reading DRAM PCCchip2 Interrupt LAN ERROR IRQ PCCchip2 LAN Error Status register SFFF42028 The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2 Control for the interrupt is in the PCCchip2 LAN Error Interrupt Control register SFFFA202B Error encountered while the LANCE was attempting to go to the VMEbus PCCchip2 Interrupt LAN ERROR IRQ PCCchip2 LAN Error Status register SFFF42028 The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2 Control for the interrupt is in the PCCchip2 LAN Error Interrupt Control register SFFFA202B http www motorola com computer literature Programming Issues LAN LTO Error Description MPU Notification Status Comments SCSI Parity Error SCSI Offboard Error Description MPU Notification Status Comments Description MPU Notification Status Comments Local Bus Time out occurred while the LANCE was Local Bus master PCCchip2 Interrupt LAN ERROR IRQ PCCchip2 LAN Error Status register 42028 The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2 Control for the interrupt is in the PCCchip2 LAN Error Interrupt Control regi
240. orola com computer literature PCCchip2 Tick Timer 2 Counter The Tick Timer 2 Counter is a 32 bit read write register located at address FFF42010 When enabled it increments every microsecond Software may read or write the counter at any time ADR SIZ BIT 31 FFF42010 32 bits NAME Tick Timer 2 Counter OPER R W RESET x Prescaler Count Register The Prescaler Count Register is an 8 bit counter used to generate the 1 MHz clock for the two tick timers This register is a read only register located at address FFF42014 It increments to FF at the BCLK frequency then it is loaded from the Prescaler Clock Adjust Register ADR SIZ FFF42014 8 bits BIT 31 24 NAME Prescaler Count OPER R W RESET X Prescaler Clock Adjust Register Note PCCchip2 runs at half the MPU speed on the MVME177P For example an MVMEI77P with a 50 MHz MPU will run the PCCchip2 at 25 MHz The Prescaler Clock Adjust Register is an 8 bit read write register located at address FFF42015 It is required to adjust the prescaler so that it maintains a 1 MHz clock source for the tick timers regardless of what 3 20 Computer Group Literature Center Web Site Programming Model frequency is used for BCLK To provide a 1 MHz clock to the tick timers the prescaler adjust register should be programmed based on the following equation prescaler clock adjust register 256 BCLK MHz Fo
241. ort The block diagram of the PCCchip2 is shown as Figure 3 1 TICK 4 1 TIMER 1 VF PARALLEL 5 PORT VF e E MC68040 CD2401 Im 3 BUS SERIAL e VF VE o SCSI LANC MAE 040 DECODER TICK INTERRUPT TIMER 2 HANDLER bd065 9209 Figure 3 1 PCCchip2 Block Diagram 3 2 Computer Group Literature Center Web Site Functional Description BBRAM Interface The PCCchip2 provides a read write interface to the BBRAM by any bus master on the MC68040 bus The PCCchip2 performs dynamic sizing for accesses to the 8 bit BBRAM to make it appear contiguous This feature allows code to be executable from the BBRAM The BBRAM device access time must be no greater than 5 BCLK periods in fast mode or 9 BCLK periods in slow mode The BBRAM speed option is controlled by a control bit in the General Control Register 82596CA LAN Controller Interface The LAN controller interface is described in the following sections MPU Port and MPU Channel Attention The PCCchip2 allows the MC68040 compatible Local Bus master to communicate directly with the Intel 82596CA LAN Coprocessor by providing a map decoder and required control and timing logic Two types of direct access are feasible with the 82596CA MPU Port and MPU Attention MPU P
242. ort access enables the MPU to write to an internal 32 bit 82596CA command register This allows the MPU to do four things 1 Write an alternate System Configuration Pointer address 2 Write an alternative dump area pointer and perform a dump 3 Execute a software reset 4 Execute a self test Each Port access must consist of two 16 bit writes Upper Command Word two bytes and Lower Command Word two bytes The Upper Command Word two bytes is mapped at FFF46000 and the Lower Command Word two bytes is mapped at FFF46002 The PCCchip2 only supports decodes MPU Port writes It does not decode MPU Port reads Nor does the 82596CA support MPU Port reads http www motorola com computer literature 3 3 PCCchip2 MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Command blocks To execute an MPU Channel Attention the Local Bus bus master performs a simple read or write to address FFF46004 MC68040 Bus Master Support for 82596CA The 82596CA has DMA capability with an Intel 1486 bus interface When it is the local bus master external hardware is needed to convert its bus cycles into MC68040 bus cycles When the 82596CA has local bus mastership the PCCchip2 drives the following Local Bus MC68040 bus signal lines Snoop Control SC1 SCO With the value programmed into the LAN Interrupt Control Register Only SC1 is used on the MVME177 Transfer Types TT1 TTO
243. oup Literature Center Web Site Memory Maps 10 11 12 13 14 structure for that set For example for a 64MB 33MHz MVME 107P board at revision C the PWA field contains 01 W3620F35C The 13 characters are followed by three blanks Four bytes contain the speed of the board in MHz The first two bytes are the whole number of MHz and the second two bytes are fractions of MHz For example for a 25 00 MHz board this field contains 2500 Six bytes are reserved for the Ethernet address The address is stored in hexadecimal format Refer to the detailed description earlier in this chapter These two bytes are reserved Two bytes are reserved for the local SCSI ID The SCSI ID is stored in ASCII format Eight bytes are reserved for the systems serial ID for boards used in a system Eight bytes are reserved for the printed wiring board PWB number assigned to the first mezzanine board in ASCII format This does not include the 01 w prefix For example for a 16MB parity mezzanine at revision E the PWB field contains 3690B03E Eight bytes are reserved for the serial number assigned to the first mezzanine board in ASCII format Eight bytes are reserved for the printed wiring board PWB number assigned to the optional second mezzanine board in ASCII format Eight bytes are reserved for the serial number assigned to the optional second mezzanine board in ASCII format Growth sp
244. ovided by the DMAC to indicate a block transfer Block transfer mode should not be set in the address modifier codes The special block transfer bits should be set to enable block transfers If non block cycles are required to reach a 32 or 64 bit boundary bits 0 and are used during these cycles BLK These bits control the block transfer modes of the DMAC 0 Block transfers disabled 1 The DMAC executes D32 block transfer cycles on the VMEbus In block transfer mode the DMAC may execute byte and two byte cycles at the beginning and ending of a transfer in non block transfer mode If the D16 bit is set the DMAC executes D16 block transfers 2 Block transfers disabled 3 The DMAC executes D64 block transfer cycles on the VMEbus In block transfer mode the DMAC may execute byte two byte and four byte cycles at the beginning and ending of a transfer in non block transfer mode If the D16 bit is set the DMAC executes D16 block transfers DMAC Local Bus Address Counter ADR SIZ FFF400368 32 bits BIT 31 2 0 DMAC Local Bus Address Counter OPER R W RESET 0 PS In direct mode this counter is programmed with the starting address of the data in local bus memory http www motorola com computer literature 2 59 VMEchip2 DMAC VMEbus Address Counter ADR SIZ FFF4003C 32 bits BIT 31 0 NAME DMAC VMEbus Address Counter OPER R W RESET OPS In direct mode th
245. ow Counter The overflow counter is cleared when a one is written to this bit OVF3 OVF0 These four bits are the outputs of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the Local Bus interrupter The overflow counter can be cleared by writing a one to the COVF control bit Computer Group Literature Center Web Site Programming Model Tick Timer 1 Control Register This is an 8 bitr ead write register that controls Tick Timer 1 It is located COC COVF OVF3 OVF0 at address FFF42017 ADR SIZ FFF42017 8 bits BIT 7 6 5 4 3 2 1 0 NAME OVF3 OVF2 OVFI OVFO COVF COC CEN OPER R R R R R C R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 0 PL 0 PL 0 PL CEN Counter Enable When this bit is high the counter increments When this bit is low the counter does not increment Clear On Compare When this bit is high the counter is reset to zero when it compares with the compare register When this bit is low the counter is not reset Clear Overflow Counter The overflow counter is cleared when a one is written to this bit These four bits are the outputs of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the Local Bus interrupter The overflow counter can be cleared by writing a one to the COVF control bit http www motorola com computer literature 3 23 PCC
246. provided for test purposes Note that if scrubbing is in process the Scrub Time On Time Off register should be set for the minimum time on and the maximum time off during any writes to this register This register reflects the current value in the Scrub Address counter bits 26 24 ADR SIZ 1st FFF4304C 2nd FFF4314C 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 0 0 0 SAC26 SAC25 SAC24 OPER R wW R W R W R W R W R W R W R W RESET X X X X X OPLS OPLS 5 http www motorola com computer literature 4 25 MCECC Functions Scrub Address Counter Bits 23 16 This register reflects the current value in the Scrub Address counter bits 23 16 ADR SIZ 1st FFF43050 2nd FFF43150 8 bits BIT 31 30 29 28 27 26 25 24 5 23 SAC22 SAC21 SAC20 SACI9 SACI8 SACI7 5 6 OPER R W R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS OPLS Scrub Address Counter Bits 15 8 This register reflects the current value in the Scrub Address counter bits 15 8 ADR SIZ 1st FFF43054 2nd FFF43154 8 bits BIT 31 30 29 28 27 26 25 24 SACI5 SACIA SACI3 SACI2 SACII SACIO SACO SAC8 OPER R W R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS OPLS Scrub Address Counter Bits 7 4 This register reflects
247. r example for operation at 20 MHz the prescaler value is SEC at 25 MHz it is E7 and at 33 MHz it is DF Non integer Local Bus clocks introduce an error into the specified times for the tick timers The tick timer clock can be derived by the following equation tick timer clock BCLK 256 prescaler value The maximum clock frequency for the tick timers is the BCLK frequency divided by two The value 255 SFF is not allowed to be programmed into this register If a write with the value of SFF occurs to this register the PCCchip2 terminates the cycle properly with TA but the register remains unchanged ADR SIZ FFF42015 8 bits BIT 23 16 Prescaler Clock Adjust OPER R W RESET DFP http www motorola com computer literature 3 21 PCCchip2 Tick Timer 2 Control Register This is an 8 bit read write register that controls Tick Timer 2 It is located at address FFF42016 ADR SIZ FFF42016 8 bits BIT 15 14 13 12 11 10 9 8 NAME OVF3 OVF2 OVFI OVFO COVF COC CEN OPER R R R R R C R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 0 PL 0 PL 0 PL CEN Counter Enable When this bit is high the counter increments When this bit is low the counter does not increment COC Clear On Compare When this bit is high the counter is reset to zero when it compares with the compare register When this bit is low the counter is not reset COVF Clear Overfl
248. r is not used for address translation Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Address Modifier Select Register 2 ADR SIZ FFF40010 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME SUP USR A32 A24 D64 BLK PGM DAT OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the address modifier select register for the second VMEbus to local bus map decoder There are three groups of address modifier select bits DAT PGM BLK and D64 A24 and A32 and USR and SUP At least one bit must be set from each group to enable the map decoder DAT When this bit is high the second map decoder responds to VMEbus data access cycles When this bit is low the second map decoder does not respond to VMEbus data access cycles PGM When this bit is high the second map decoder responds to VMEbus program access cycles When this bit is low the second map decoder does not respond to VMEbus program access cycles BLK When this bit is high the second map decoder responds to VMEbus block access cycles When this bit is low the second map decoder does not respond to VMEbus block access cycles D64 When this bit is high the second map decoder responds to VMEbus D64 block access cycles When this bit is low the second map decoder does not respond to VMEbus 064 block access cycles A2A When this bit is
249. rature 2 71 VMEchip2 WDCS SRST When this bit is set high the watchdog time out status bit WDTO bit in this register is cleared When this bitis set high a SYSRESET signal is generated on the VMEbus SYSRESET resets the VMEchip2 and clears this bit Tick Timer 2 Control Register ADR SIZ FFF40060 8 bits 7 used of 32 BIT 15 14 13 12 11 10 9 8 NAME OVF COVF COC EN OPER R C R W R W RESET 0 PS 0 PS 0 PS 0 PS EN When this bit is high the counter increments When this bit is low the counter does not increment COC When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when a 1 is written to this bit OVF These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to the COVE bit Computer Group Literature Center Web Site LCSR Programming Model Tick Timer 1 Control Register Prescaler Counter ADR SIZ FFF40060 8 bits of 32 BIT 7 5 4 3 2 1 0 NAME OVF COVF COC EN OPER R C R W R W RESET 0 PS 0 PS 0 PS 0 PS EN When this bit is high the counter increments When this bit is low the counter does not increment COC When this bit is high the counter is re
250. rea Network Coprocessor User s Manual 296853 28F016SA Flash Memory Data Sheet 209435 Intel Corporation Web http developer intel com design SYM 53C710 was NCR 53C710 SCSI I O Processor Data Manual NCR53C710DM SYM 53C710 was NCR 53C710 SCSI I O Processor Programmer s Guide NCR53C710PG Symbios Logic Inc 1731 Technology Drive Suite 600 San Jose CA 95110 NCR Managed Services Center Telephone 1 800 262 7782 Web http www lsilogic com products symbios M48T58 B TIMEKEEPER and 8K x 8 Zeropower RAM Data Sheet M48T58 SGS Thomson Microelectronics Group Marketing Headquarters or nearest Sales Office 1000 East Bell Road Phoenix Arizona 85022 Telephone 602 867 6100 Web http www st com stonline books C 2 Computer Group Literature Center Web Site Related Specifications Table C 2 Manufacturers Documents Continued Publication Document Title and Source Number 785230 Serial Communications Controller Product Brief Z85230pb pdf Zilog Inc 210 Hacienda Avenue Campbell CA 95008 6609 Web http www zilog com products Related Specifications For additional information refer to the following table for manufacturers data sheets or user s manuals As a further help sources for the listed documents are also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table
251. register is used to define the level of the GCSR SIG2 interrupt and the GCSR SIG3 interrupt SIG2 LEVEL These bits define the level of the GCSR SIG2 interrupt SIG3 LEVEL These bits define the level of the GCSR SIG3 interrupt Interrupt Level Register 2 bits 8 15 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME SIG1 LEVEL SIGO LEVEL OPER R W R W RESET 0 PSL PSL This register is used to define the level of the GCSR SIGO interrupt and the SIGI1 interrupt SIGO LEVEL These bits define the level of GCSR SIGO interrupt SIG1 LEVEL These bits define the level of the GCSR SIGI interrupt Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 2 bits 0 7 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME LM1 LEVEL LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the GCSR LMO interrupt and the interrupt LEVEL These bits define the level of interrupt LM1 LEVEL These bits define the level of GCSR interrupt Interrupt Level Register 3 bits 24 31 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 31 30 29 28 27 26 25 24 NAME SW7 LEVEL SW6 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 6 inter
252. resses XXF1 XXF3 XXF5 and XXF7 respectively A location monitor cycle on the VMEbus is generated by a read or write to VMEbus short I O address XXFN where XX is the group address and is the specific location monitor address When the VMEchip2 generates a location monitor cycle to the VMEbus within its own group the VMEchip2 DTACKs itself A VMEchip2 cannot DTACK location monitor cycles to other groups The GCSR section of the VMEchip2 contains the following registers a Chip ID register a Chip Revision register a Location Monitor Status register an Interrupt Control register a Board Control register and six General Purpose registers The Chip ID and Revision registers are provided to allow software to determine the ID of the chip and its revision level The VMEchip2 has a chip ID of ten ID codes 0 and 1 are used by the old VMEchip The initial revision of the VMEchip2 is 0 If mask changes are required the revision level is incremented 2 100 Computer Group Literature Center Web Site GCSR Programming Model The Location Monitor Status register provides the status of the location monitors A location monitor bit is cleared when the VMEchip2 detects a VMEbus cycle to the corresponding location monitor address When the or LMI bits are cleared an interrupt is set to the local bus interrupter If the LMO or LMI interrupt is enabled in the local bus interrupter then a local bus interrupt is generated The locatio
253. resses and bit definitions for these registers are in the tables below A local bus slave map decoder is programmed by loading the starting address of the segment into the starting address register and the ending address of the segment into the ending address register The address modifier code is programmed into the address modifier register Because the local bus to V MEbus interface does not support VMEbus block transfers block transfer address modifier codes should not be programmed The address translation register allows a local bus master to view a portion of the VMEbus that may be hidden by onboard resources or an area of the VMEbus may be mapped to two local address For example some devices in the I O map may support write posting while others do not The VMEbus area in question may be mapped to two local bus addresses one with write posting enabled and one with write posting disabled The address translation registers allow local bus address bits A31 through A16 to be modified The address translation register should be programmed with the translated address and the address translation select register should be programmed to enable the translated address If address translation is not desired then the address translation registers should be programmed to 0 The address translation address register and the address translation select register operate in the following way If you set a bit in the address translation select register
254. rol signals Note 77 which uses SCI the SCO bit must be 0 Computer Group Literature Center Web Site Programming Model Programming the SCSI Error Status and Interrupt Registers This section provides address and bit level description of the SCSI interrupt control register and status register SCSI Error Status Register ADR SIZ FFF4202C 8 bits BIT 31 30 29 28 27 26 25 24 NAME PRTY EXT LTO SCLR OPER R R R W R 0 RESET 0 0 0 0 0 PL 0 PL 0 PL 0 SCLR Writing a 1 to this bit clears bits 25 through 27 LTO EXT and PRTY Reading this bit always yields 0 LTO EXT PRTY These bits indicate the status of the last Local Bus error condition encountered by the SCSI processor while performing DMA accesses to the Local Bus A Local Bus error condition is flagged by the assertion of TEA When the SCSI processor receives TEA If the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other two status bits are cleared If the source of the error is none of the above conditions then all three bits are cleared Writing a 1 to bit 24 SCLR also clears all three bits http www motorola com computer l
255. rupt Registers Receive Priority Interrupt Level Register RPILR El B R W Receive Interrupt Register RIR ED B R Receive Interrupt Status Register RISR 88 W R W NOTE http www motorola com computer literature 1 37 Programming Issues Table 1 9 Cirrus Logic CD2401 Serial Port Memory Map Continued Base Address FFF45000 Register Description Register Offsets Size Access Name Receive Interrupt Status Register low RISRI 89 B R Receive Interrupt Status Register high RISRh 88 B R Receive FIFO Output Count RFOC 30 B R Receive Data Register RDR F8 B R Receive End Of Interrupt Register REOIR 84 B W Transmit Interrupt Registers Transmit Priority Interrupt Level Register TPILR EO B R W Transmit Interrupt Register TIR EC B R Transmit Interrupt Status Register TISR 8A B R Transmit FIFO Transfer Count TFTC 80 B R Transmit Data Register TDR F8 B W Transmit End Of Interrupt Register TEOIR 85 B W Modem Interrupt Registers Modem Priority Interrupt Level Register MPILR E3 B R W Modem Interrupt Register MIR EF B R Modem Timer Interrupt Status Register MISR 8B B R Modem End Of Interrupt Register MEOIR 86 B W DMA Registers DMA Mode Register write only DMR F6 B W Bus Error Retry Count BERCNT 8E B R W DMA Buffer Status DMABSTS 19 B R DMA Receive Registers A Receive Buffer Address Lower ARBADRL 42 W R W A Receive Buffer Address Upper ARBADRU 40 W
256. rupt and the software 7 interrupt SW6 LEVEL These bits define the level of the software 6 interrupt SW7 LEVEL These bits define the level of the software 7 interrupt http www motorola com computer literature VMEchip2 Interrupt Level Register 3 bits 16 23 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SW5 LEVEL SW4 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 4 interrupt and the software 5 interrupt SW4 LEVEL These bits define the level of the software 4 interrupt SWS LEVEL These bits define the level of the software 5 interrupt Interrupt Level Register 3 bits 8 15 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME SW3 LEVEL SW2 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 2 interrupt and the software 3 interrupt SW2 LEVEL These bits define the level of the software 2 interrupt SW3 LEVEL These bits define the level of the software 3 interrupt Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 3 bits 0 7 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME SW1 LEVEL SWO LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 0 interrupt and
257. s usually caused by another bus master holding the bus for an excessive period of time VMEbus BERR A VMEbus BERR occurs when the signal line is asserted on the VMEbus while a Local Bus master is accessing the VMEbus VMEbus BERR should occur only if one of the following events is detected a An initialization routine samples to see if a device is present on the VMEbus and it is not Software accesses a nonexistent device within the VMEbus range Erroneous configuration data causes the VMEchip2 to incorrectly access a device on the VMEbus such as driving LWORD low to a 16 bit board Computer Group Literature Center Web Site Error Conditions Q A hardware error occurs on the VMEbus A VMEbus slave reports an access error such as parity error VMEchip2 An 8 or 16 bit write to the LCSR in the VMEchip2 ASIC causes a local BERR Bus Error Processing Because different conditions can cause bus error exceptions the software must be able to distinguish the source To aid in this status registers are provided for every Local Bus master The next section describes the various causes of bus error and the associated status registers Generally the bus error handler can interrogate the status bits and proceed with the result However an interrupt may occur during the execution of the bus error handler before an instruction can write to the status register to raise the interrupt mask If the
258. s MC68060 processor has the ability to watch the external bus during accesses by other bus masters maintaining coherency between the MC68060 s caches and external memory systems To maintain cache coherency the MC68060 provides automatic snoop invalidation when it is not the bus master When an external cycle is marked as snoopable the bus snooper checks the caches and invalidates the matching data Unlike the MC68040 the MC68060 cannot source or sink cache data during alternate bus master accesses Therefore the MVMEIT77 uses a single snoop control line SC1 Snoop control bits for SCO must be set to 0 MC68060 cache coherency and bus snooping capabilities are described in the M68060 Microprocessors User s Manual in the sections on Cache Coherency and Bus Snooping Operation Computer Group Literature Center Web Site Using Bus Timers Using Bus Timers This section illustrates the use of bus timers by describing the sequence of events when the MPU on one single board computer accesses the Local Bus memory on another single board computer using the VMEbus This scenario involves three bus timers which normally should be set to quite different values Local bus timer Measures the time an access to an onboard resource takes VMEbus access Measures the time from when the VMEbus request has timer been initiated to when a VMEbus grant has been obtained Global VMEbus Measures the time from when a VMEbus cycle begins to timer
259. s Register 2 2 40 Local Bus Slave VMEbus Master Ending Address Register 3 2 41 Local Bus Slave VMEbus Master Starting Address Register 3 2 41 Local Bus Slave VMEbus Master Ending Address Register 4 2 41 Local Bus Slave VMEbus Master Starting Address Register 4 2 42 Local Bus Slave VMEbus Master Address Translation Address Register 4 24 4 2 42 Local Bus Slave VMEbus Master Address Translation Select Register 4 2 42 Local Bus Slave VMEbus Master Attribute Register 4 2 43 Local Bus Slave VMEbus Master Attribute Register 3 2 44 Local Bus Slave VMEbus Master Attribute Register 2 2 45 Local Bus Slave VMEbus Master Attribute Register 1 2 46 VMEbus Slave GCSR Group Address Register 2 47 VMEbus Slave GCSR Board Address Register 2 48 Local Bus to VMEbus Enable Control Register 2 2 49 Local Bus to VMEbus Control Register 2 222 2 50 ROM Control Segun PT 2 51 Programming the VMEchip2 DMA Controller eese 2 51 TR 2 53 EPROM Decoder SRAM and DMA Control Register 2 53 Local Bus to VMEbus Requester Control Register
260. s because they are normal read cycles on the Local Bus side but they are interrupt acknowledge cycles on the CD2401 side of the PCCchip2 They are necessary to support polled mode operation with the CD2401 Note If this register is read when an interrupt is not present the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled TIV7 TIVO Transmit Interrupt vector bits 7 0 reflect the transmit interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle Computer Group Literature Center Web Site Programming Model Receive PIACK Register ADR SIZ FFF42027 8 bits The Receive PIACK Register is used to execute receive pseudo interrupt acknowledge cycles to the CD2401 When the Local Bus master initiates a read cycle to this register the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with 7 0 03 Note that the PILR1 register in the CD2401 should be set to the same value 03 for the interrupt acknowledge cycle to operate properly To finish the local read cycle the PCCchip2 drives the vector received from the CD2401 onto the local data bus and asserts TA Reads to this register are termed pseudo interrupt acknowledge cycles because they are normal read cycles on the Local Bus side but they are interrupt acknowledge cycles on the CD2401 side of the PCCchip2 They are necessary to support polle
261. s bit is cleared when the DMAC is enabled If this bit is set the DMAC has received a VMEbus BERR during a data transfer This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received an error on the local bus while it was reading commands from the command packet Additional information is provided in bits 3 6 DLTO DLOB DLPE This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received a TEA and the status indicated a local bus time out This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received a TEA and the status indicated off board This bit is cleared when the DMAC is enabled http www motorola com computer literature 2 63 VMEchip2 DLPE If this bit is set the DMAC has received a TEA and the status indicated a parity error during a DRAM data transfer This bit is cleared when the DMAC is enabled DLBE If this bit is set the DMAC has received a TEA and no additional status was provided This bit is cleared when the DMAC is enabled MLTO If this bit is set the MPU has received a TEA and the status indicated a local bus time out This bit is cleared by writing a 1 to the MCLR bit in this register Programming the Tick and Watchdog Timers The VMEchip2 has two 32 bit tick timers and one watchdog timer This section provides addresses and bit level descriptions of the prescaler tick timer watchdog timer regis
262. s not used on the MVMEIx7P This bit must not be set MPIRQEN This function is not used on MVME1x7P This bit must not be set http www motorola com computer literature 2 99 VMEchip2 GCSR Programming Model This section describes the programming model for the Global Control and Status Registers GCSR in the VMEchip2 The local bus map decoder for the GCSR registers is included in the VMEchip2 The local bus base address for the GCSR is FFF40100 The registers in the GCSR are 16 bits wide and they are byte accessible from both the VMEbus and the local bus The GCSR is located in the 16 bit VMEbus short I O space and it responds to address modifier codes 29 or 2D The address of the GCSR as viewed from the VMEbus depends upon the GCSR group select value XX and GCSR board select value Y programmed in the LCSR The board value Y may be 0 through E allowing 15 boards in one group The value F is reserved for the location monitors The VMEchip2 includes four location monitors LMO LM3 The location monitors provide a broadcast signaling capability on the VMEbus When a location monitor address is generated on the VMEbus all location monitors in the group are cleared The signal interrupts SIGO SIG3 should be used to signal individual boards The location monitors are located in the VMEbus short I O space and the specific address is determined by the VMEchip2 group address The location monitors LMO LM3 are located at add
263. s of the bits after local and power up reset are as defined below The bit is affected by power up reset The bit is affected by local reset The bit is not affected by reset The effect of reset on this bit is variable The bit is always 0 The bit is always 1 A summary of the PCCchip2 CSR is shown in Table 6 2 http www motorola com computer literature 3 11 PCCchip2 Table 3 2 PCCchip2 Memory Map Control and Status Registers PCCchip2 Base Address FFF42000 OFFSET D31 D24 D23 D16 00 CHIP ID CHIP REVISION 04 TIC TIMER 1 08 TIC TIMER 1 0c TIC TIMER 2 10 TIC TIMER 2 14 PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST GPI GPI GPI GPOE GPO 18 PLTY INT IEN ICLR IRQ LEVEL Scc scc scc scc scc Scc scc scc 1 RTRY PAR EXT LTO SCLR MDM MDM MDM Mond ERR ERR ERR ERR ERR IEN AVEC e 20 24 SCC TRANSMIT PIACK LAN LAN LAN LAN 28 PAR EXT LTO SCLR ERR ERR ERR SCSI scsi scsi SCSI 2C PAR EXT LTO SCLR ERR ERR ERR PRTR PRTR PRTR PRTR PRTR PRIA ACK PRTR PRTR PRTR FAULT 30 ACK ACK ACK ACK ACK IRQ LEVEL FLT FLT FLT FLT FLT IRQ LEVEL PLTY E L INT IEN PLTY EA INT IEN PRTR PRTR PRTR PRTR PRTR 34 BSY BS
264. s the modifications that accompanied the introduction of the Petra ASIC on the MVME167P and MVME177P single board computers Differences in function and implementation between previous MVME167 and MVME177 models and the new MVMEIx7P boards are listed in the following table Table A 1 List of Changes Function Previous Implementation MVMEIx2P2 Implementation MCECC memory control MCECC ASIC revision 00 Petra ASIC revision 02 page 3 12 DRAM DRAM with parity or ECC protection SDRAM with ECC protection page MVME167 DRAM with ECC protection MVME177 1 2 Ethernet interface N82C501AD device LXT901 device software transparent EEPROM sockets Through hole 44 pin PLCC Surface mount 44 pin PLCC Serial interface MC 14506 device 2 device Real time clock MASTO68 device M48T58 device LEDs Through hole wave soldered Surface mount with light pipes SRAM battery Through hole dual battery Surface mount holder 1 Summary of Changes A A 2 Computer Group Literature Center Web Site Printer and Serial Port Connections Introduction This appendix has connection diagrams for the printer port and the four serial ports on the MVMEIXT7P These ports are connected to external devices through an MVME712M transition module The configuration of the serial ports as Data Terminal Equipment DTE or Data Circuit terminating Equipment DCE
265. ses on the Local Bus Table 3 1 PCCchip2 Devices Memory Map Address Range Selected Device Comments FFF42000 FFF4203F PCCchip2 Registers See Programming Model FFF42040 FFF42FFF PCCchip2 Registers Repeated FFF43000 FFF43 FFF MCECC Memory Controller External Device FFF45000 FFF450FF CD2401 SCC External Device FFF45 100 FFF45FFF CD2401 SCC Repeated FFF46000 FFF46FFF 82596CA LANC External Device FFF47000 FFF47FFF 53C710 SCSI External Device FFF80000 FFFBFFFF Reserved External Device FFFC0000 FFFCFFFF DS1643 M48T58 BBRAM External Device TOD Clock Computer Group Literature Center Web Site Programming Model Programming Model This section defines the programming model for the control and status registers CSR in the PCCchip2 The base address of the CSR is FFF42000 The PCCchip2 control and status registers can be accessed as bytes 8 bits two bytes 16 bits or four bytes 32 bits The possible operations for each bit in the CSR are as follows R R W W AC 0 This bit is a read only status bit This bit is readable and writable This bit can be set and it is automatically cleared This bit can also be read Writing a one to this bit clears this bit or another bit This bit reads zero Writing a one to this bit sets this bit or another bit This bit reads zero This bit is read only It always reads as 0 The possible state
266. ses it to the MPU The use of the AVEC mode is not recommended IEN Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low IRQ Interrupt Status This status bit reflects the state of the SCC IRQ 2 pin of the CD2401 qualified by the bit When this bit is high an SCC Transmit interrupt is being generated at the level programmed in IL2 ILO if nonzero This status bit does not need to be cleared because it is not edge sensitive http www motorola com computer literature 3 29 PCCchip2 SCC Receive Interrupt Control Register ADR SIZ BIT 7 FFF4201F 8 bits 5 4 3 2 1 0 NAME SCI SCO IRQ IEN AVEC IL2 IL1 ILO OPER R W R W R R W R W R W R W R W RESET 0 PL 0 PL X 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO AVEC IEN IRQ SC1 SCO Interrupt Request Level These three bits select the interrupt level for SCC Receive Interrupt Level 0 does not generate an interrupt When this bit is high the PCCchip2 supplies the interrupt vector to the MPU during an IACK for SCC receive interrupt When this bit is low the PCCchip2 obtains the vector from the SCC and passes it to the MPU The use of the AVEC mode is not recommended Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low Interrupt Status This status bit reflects the st
267. set to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when a 1 is written to this bit OVF These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to the COVE bit ADR SIZ FFF40064 32 bits BIT 31 0 NAME Prescaler Counter OPER R W RESET OP The VMEchip2 has a 32 bit prescaler that provides the clocks required by the various timers in the chip Access to the prescaler is provided for test purposes The counter is described here because it may be useful in other applications The lower 8 bits of the prescaler counter increment to FF at the local bus clock rate and then they are loaded from the prescaler adjust register When the load occurs the upper 24 bits are incremented When the prescaler adjust register is correctly programmed the lower 8 bits increment at the local bus clock rate and the upper 24 bits increment every microsecond The counter may be read at any time http www motorola com computer literature 2 73 VMEchip2 Programming the Local Bus Interrupter The local bus interrupter is used by devices that need to interrupt the local bus There are 31 devices that can interrupt the local bus through the VMEchip2 In the general case each interrupter has
268. sfying the requirements of the VMEbus specification and then re arbitrating any pending bus requests IACK Daisy Chain Driver Complying with the latest revision of the VMEbus specification the System Controller includes an IACK Daisy Chain Driver ensuring that the timing requirements of the IACK daisy chain are satisfied Bus Timer The Bus Timer is enabled disabled by software to terminate a VMEbus cycle by asserting BERR if any of the VMEbus data strobes is maintained in its asserted state for longer than the programmed time out period The timeout period can be set to 8 64 or 256 secs The bus timer terminates an unresponded VMEbus cycle only if both it and the system controller are enabled http www motorola com computer literature 2 17 VMEchip2 Reset Driver In addition to the VMEbus timer the chip contains a local bus timer This timer asserts the local TEA when the local bus cycle maintained in its asserted state for longer that the programmed time out period This timer can be enabled or disabled under software control The time out period can be programmed for 8 64 or 256 seconds The chip includes both a global and a local reset driver When the chip operates as the VMEbus system controller the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET may be generated by the RESET switch a power up reset a watch dog timeout or by a control bit in LCSR SYSRESET
269. single address RMW instructions For efficiency all CAS instructions should be aligned Supervisor Stack Pointer MC68060 On the MC68060 use of the supervisor stack pointer is reserved for system programming functions All application software must be written to run in user mode Such software will migrate to any M68000 platform without modification Programs written for platforms like the MC68040 which do use the supervisor stack pointer must be recompiled before you can run them on a MC68060 based single board computer such as MVME177 http www motorola com computer literature 1 53 Programming Issues Sources of Local Bus Errors A TEA signal indicating a bus error is returned to the Local Bus master when a Local Bus time out occurs a DRAM parity error occurs and parity checking is enabled or a VME bus error occurs during a VMEbus access The sources of Local Bus errors on the Single Board Computers are described in the next subsections Local Bus Timeout A Local Bus Timeout occurs whenever a Local Bus cycle does not complete within the programmed time VMEbus bound cycles are not timed by the Local Bus timer If the system is configured properly this should only happen if software accesses a non existent location within the onboard address range VMEbus Access Timeout A VMEbus Access Timeout occurs whenever a VMEbus bound transfer does not receive a VMEbus bus grant within the programmed time This i
270. sitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as zero IEN When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a printer ACK interrupt is being generated at the level programmed in IL2 ILO if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a falling edge low level on the PRACKI pin When this bit is high interrupt is activated by a rising edge high level on the PRACKI pin Note that if this bit is changed while the E L bit is set or is being set an ACK interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the E L bit http www motorola com computer literature 3 39 PCCchip2 Printer FAULT Interrupt Control Register ADR SIZ FFF42031 8 bits BIT 23 22 21 20 19 18 17 16 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the printer FAULT Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sens
271. sory access cycles Programming the Local Bus to VMEbus Map Decoders This section includes programming information on the local bus to VMEbus map decoders and the GCSR base address registers The local bus to VMEbus interface allows onboard local bus masters access to off board VMEbus resources The address of the VMEbus resources as viewed from the local bus is controlled by the local bus slave map decoders which are part of the local bus to VMEbus interface Four of the six local bus to VMEbus map decoders are programmable while the two I O map decoders are fixed The first I O map decoder provides an A16 D16 or A16 D32 space at SFFFF0000 to FFFFFFFF which is the VMEbus short I O space The second I O map decoder provides an 24 16 space at F000000 to FOFFFFFF an A32 D16 space at F1000000 to FF7FFFFF A programmable segment may vary in size from 64KB to 4GB in increments of 64KB Address translation for the fourth segment is provided by the address translation registers which allow the upper 16 bits of the VMEbus address to be provided by the address translation address register rather than the upper 16 bits of the local bus http www motorola com computer literature 2 37 VMEchip2 Each of the four programmable local bus map decoders has a starting address an ending address an address modifier register with attribute bits and an enable bit The fourth decoder also has address translation registers The add
272. ss modifier code when the F page is accessed When this bit is low the VMEchip2 drives a data address modifier code when the F page is accessed When this bit is high VMEchip2 drives a supervisor address modifier code when the F page is accessed When this bit is low the VMEchip2 drives a user address modifier code when the F page is accessed 2 50 Computer Group Literature Center Web Site LCSR Programming Model DWP When this bit is high write posting is enabled to the local bus F page When this bit is low write posting is disabled to the local bus F page IZEN When this bit is high the F page F0000000 through FF7FFFFF map decoder is enabled The FO page is defined as A24 D16 on the VMEbus while the F1 FE pages are defined as A32 D16 When this bit is low the F page is disabled ROM Control Register ADR SIZ FFF4002C BIT 7 6 5 4 3 2 1 0 NAME SIZE BSSPD ASPD OPER R W R W R W RESET OPS OPS OPS This function is not used on the MVMEIx7P Programming the VMEchip2 DMA Controller This section includes programming information on the DMA controller VMEbus interrupter MPU status register and local bus to VMEbus requester register The VMEchip2 features a local bus to VMEbus DMA controller DMAC The DMAC has two modes of operation command chaining and direct In direct mode the local bus address the VMEbus address the byte count and the control register of the DMAC ar
273. ster SFFFA202B Parity error detected while the 53C710 was reading DRAM 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register SFFF4202C 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2 Error encountered while the 53C710 was attempting to go to the VMEbus 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register FFF4202C 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2 1 62 Computer Group Literature Center Web Site Error Conditions SCSI LTO Error Description MPU Notification Status Comments Local Bus Time out occurred while the 53C710 was Local Bus master 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register SFFFA202C 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2 http www motorola com computer literature 1 63 Programming Issues 1 64 Computer Group Literature Center Web Site VMEchip2 Introduction This chapter describes the VMEchip2 ASIC the local bus VMEbus interface chip The VMEchip2 interfaces the local bus to the VMEbus In addition to its VMEbus defined functions the VMEchip2 includes a local bus to VMEbus DMA controller VME board support features and Global Control and Status
274. t Output Pin Control register PCCchip2 ASIC 3 25 General Purpose Register 1 2 107 general purpose I O GPIO pins PCCchip2 ASIC 3 7 general purpose I O pins 2 96 general purpose registers VMEchip2 2 101 global control status registers GCSRs 2 100 reset driver VMEbus 2 18 reset VMEbus 2 18 global control status registers General Purpose Register 0 2 107 General Purpose Register 2 2 107 General Purpose Register 3 2 108 General Purpose Register 4 2 108 General Purpose Register 5 2 108 IN 4 Computer Group Literature Center Web Site ID register VMEchip2 2 104 VMEchip2 Board Status Control register 2 106 VMEchip2 ID register 2 104 VMEchip2 LM SIG register 2 104 VMEchip2 Revision register 2 103 GPI inputs addresses 1 18 GPIO pin PCCchip2 ASIC 3 25 GPIO pin drive PCCchip2 ASIC 3 25 GPIO pin logic PCCchip2 ASIC 3 25 group address GCSR 2 47 H hexadecimal number symbol for xxiii I O interfaces 1 3 T O map decoders 2 6 2 37 2 39 I O memory maps 1 25 1486 bus interface 3 4 IACK cycle VMEbus 2 20 IACK daisy chain driver VMEbus and 2 17 IACK daisy chain VMEbus 2 16 indivisible cycles MC68040 and MC68060 1 52 indivisible memory accesses 1 52 initialization MCECC sector 4 34 INT clear GPIO 3 24 LANC bus error 3 36 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer paper error 3 42 printer select 3 41 tick timer 1 3 26 tick timer 2 3 25 interrupt acknowl
275. t restrict the CD2401 to onboard DRAM Parallel Printer Interface The PCCchip2 ASIC provides an 8 bit bidirectional parallel port All eight bits of the port must be either inputs or outputs no individual selection In addition to the 8 bits of data there are two control pins and five status pins Each of the status pins can generate an interrupt to the MPU in any of the following programmable conditions high level low level high to low transition or low to high transition This port may be used as a Centronics compatible parallel printer port or as a general parallel I O port When used as a parallel printer port the five status pins function as Printer Acknowledge ACK Printer Fault FAULT Printer Busy BSY Printer Select SELECT and Printer Paper Error PE while the control pins act as Printer Strobe STROBE and Input Prime INP The PCCchip2 provides an auto strobe feature similar to that of the 47 In auto strobe mode after a write to the Printer Data Register the PCCchip2 automatically asserts the STROBE pin for a selected time specified by the Printer Fast Strobe control bit In manual mode the Printer Strobe control bit directly controls the state of the STROBE pin Refer to Chapter 3 PCCchip2 for detailed programming information Refer to Appendix C Related Documentation for drawings of the printer port interface connections 1 14 Computer Group Literature Center Web Site Pro
276. ter describes the Petra chip as used in the MVME1x7 MCECC implementation The MCECC ASICs used in a set of two provided the interface to a 144 bit wide DRAM memory array The Petra implementation provides an interface to a 40 bit SDRAM memory array There are 32 bits for data 7 for check bits and one bit that is not used SDRAM configurations that allow array sizes of 16MB to 128MB are supported For a complete description of the memory configurations that are supported refer to the definition of the SDCFG2 SDCFGO0 bits in the SDRAM Configuration register 4 1 MCECC Functions Features MCECC functions now implemented on the Petra chip include Table 4 1 MCECC Functions on the Petra ASIC Function Memory Control Features 2 1 1 1 memory accesses sustained for burst writes 4 1 1 1 memory accesses sustained for burst reads 5 1 1 1 with BERR on or when FSTRD is cleared Support for byte two byte four byte and cache line read or write transfers Programmable base address for DRAM Built in refresh timer and refresh controller Programmable period automatic scrub operation Error Handling ECC Single Bit Error Detect and Correct Software enabled Interrupt on Single Bit Error Double Bit Error Detect Software programmable Bus Error and or Interrupt on double bit error 4 2 Computer Group Literature Center Web Site Functional Description Functional Description
277. ters and various other timer registers VMEbus Arbiter Time Out Control Register ADR SIZ FFF4004C 8 bits 1 used of 32 BIT 31 30 29 28 27 26 25 24 NAME ARBTO OPER R W RESET 0 PS This register controls the VMEbus arbiter time out timer ARBTO When this bit is high the VMEbus grant time out timer is enabled When this bit is low the VMEbus grant timer is disabled When the timer is enabled and the arbiter does not receive a BBSY signal within 256 us after a grant is issued the arbiter asserts BBSY and removes the grant The arbiter then rearbitrates any pending requests 2 64 Computer Group Literature Center Web Site LCSR Programming Model DMAC Ton Toff Timers and VMEbus Global Time out Control Register ADR SIZ FFF4004C 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME TIME OFF TIME ON VGTO OPER R W R W R W RESET OPS OPS OPS This register controls the DMAC time off timer the DMAC time on timer and the VMEbus global time out timer VGTO TIME ON TIME OFF These bits define the VMEbus global time out value When DSO or 051 is asserted on the VMEbus the timer begins timing If the timer times out before the data strobes are removed a BERR signal is sent to the VMEbus The global time out timer is disabled when the VMEchip 2 is not system controller These bits define the maximum time the DMAC spends 256 Us 512 us 1024 us Whe
278. tes how to generate and handle a VMEchip2 Tick Timer 1 interrupt on M68000 based single board computers such as the MVME1X7P Specific values are given for the register writes It is advisable to read this entire section before you perform any of these procedures http www motorola com computer literature 1 47 Programming Issues 1 Set up Tick Timer Step Register and Address Action and Reference 1 Prescaler Control register If not already initialized by the debugger initialize as FFF4004C follows Prescaler register 256 Bclock MHz This gives a 1 MHz clock to the tick timers Bclock is the bus clock rate such as 25MHz 256 25 SET 2 Tick Timer 1 For periodic interrupts set the Compare Register value Compare register Period s For example if you want an interrupt every FFF40050 millisecond set the register value to 1000 3E8 Refer to the Tick Timer 1 Compare Register description in Chapter 2 3 Tick Timer 1 Write a zero to clear the register Counter register FFF40054 4 Tick Timer 1 Write 07 to this register set bits 0 1 and 2 This Control register enables the Tick Timer 1 counter to increment resets the FFF40060 8 bits count to zero on compare and clears the overflow counter 2 Set up local bus interrupter Step Register and Address Action and Reference 5 Vector Base register If not already initialized by the debugger set Interrupt FF
279. the software 1 interrupt SWO0 LEVEL These bits define the level of the software 0 interrupt SWILEVEL These bits define the level of the software 1 interrupt Interrupt Level Register 4 bits 24 31 ADR SIZ FFF40084 8 bits 6 used of 32 BIT 3l 30 29 28 27 26 25 24 NAME SPARE LEVEL VIRQ7 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the VMEbus IRQ7 interrupt and the spare interrupt The VMEbus level 7 IRQ7 interrupt may be mapped to any local bus interrupt level VIRQ7 LEVEL These bits define the level of the VMEbus IRQ7 interrupt SPARE LEVEL Not used on the MVMEIx7P http www motorola com computer literature 2 93 VMEchip2 Interrupt Level Register 4 bits 16 23 ADR SIZ FFF40084 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME VIRQ6 5 LEVEL OPER R W R W RESET 0 PSL 0 PSL Interrupt Level Register 4 bits 8 15 This register is used to define the level of the VMEbus level 5 IRQ5 interrupt and the VMEbus level 6 IRQ6 interrupt The 5 and interrupts may be mapped to any local bus interrupt level VIRQ5 LEVEL These bits define the level of the VMEbus IRQ 5 interrupt VIRQ6 LEVEL These bits define the level of the VMEbus IRQ6 interrupt ADR SIZ FFF40084 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME VIRQ4 VIRQ3 LEVEL OPER R
280. the DMAC can be programmed to execute block transfer cycles over the VMEbus Complying with the VMEbus specification the DMAC automatically terminates block transfer cycles whenever a 256 byte D32 BLT or 2 KB D64 BLT boundary is crossed It does so by momentarily releasing AS Address Strobe and then in accordance with its bus release bus request configuration initiating a new block transfer cycle To optimize VMEbus use the DMAC automatically adjusts the size of individual data transfers until 64 bit transfers D64 BLT mode 32 bit transfers D32 mode or 16 bit transfers D16 mode can be executed Based on the address of the first byte the DMAC transfers single bytes double bytes or a mixture of both and then continues to execute transfer cycles based on the programmed data width Based on the address of the last byte the DMAC transfers single bytes double bytes or a mixture of both to end the transfer To optimize local bus use when the VMEbus is operating in D16 mode the data FIFO converts D16 VMEbus transfers to D32 local bus transfers The FIFO also aligns data if the source and destination addresses are not aligned so the local bus and VMEbus can operate at their maximum data transfer sizes To allow other boards access to the VMEbus the DMAC has bus tenure timers to limit the time the DMAC spends on the VMEbus and to ensure a minimum time off the VMEbus Since the local bus is generally faster than the VMEbus other
281. the first map decoder does not responded to VMEbus data access cycles PGM When this bit is high the first map decoder responds to VMEbus program access cycles When this bit is low the first map decoder does not respond to VMEbus program access cycles BLK When this bit is high the first map decoder responds to VMEbus block access cycles When this bit is low the first map decoder does not respond to VMEbus block access cycles D64 When this bit is high the first map decoder responds to VMEbus D64 block access cycles When this bit is low the first map decoder does not respond to VMEbus D64 block access cycles A2A When this bit is high the first map decoder responds to VMEbus A24 standard access cycles When this bit is low the first map decoder does not respond to VMEbus A24 access cycles 2 36 Computer Group Literature Center Web Site LCSR Programming Model A32 When this bit is high the first map decoder responds to VMEbus A32 extended access cycles When this bit is low the first map decoder does not respond to VMEbus A32 access cycles USR When this bit is high the first map decoder responds to VMEbus user non privileged access cycles When this bit is low the first map decoder does not respond to VMEbus user access cycles SUP When this bit is high the first map decoder responds to VMEbus supervisory access cycles When this bit is low the first map decoder does not respond to VMEbus supervi
282. the level of the external interrupt IRQIE LEVEL These bits define the level of the VMEbus IRQ1 edge sensitive interrupt PE LEVEL Not used on MVMEIx7P 2 88 Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 1 bits 0 7 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME TICK2 LEVEL TICK1 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the tick timer 1 interrupt and the tick timer 2 interrupt TICK1 LEVEL These bits define the level of the tick timer 1 interrupt TICK2 LEVEL These bits define the level of the tick timer 2 interrupt Interrupt Level Register 2 bits 24 31 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 31 30 29 28 27 26 25 24 NAME VIA LEVEL DMA LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the DMA controller interrupt and the VMEbus acknowledge interrupt DMA LEVEL These bits define the level of the DMA controller interrupt VIA LEVEL These bits define the level of the VMEbus interrupter acknowledge interrupt http www motorola com computer literature 2 89 VMEchip2 Interrupt Level Register 2 bits 16 23 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SIG3 LEVEL SIG2 LEVEL OPER R W R W RESET 0 PSL 0 PSL This
283. the timer times out and the transaction is not write posted a TEA signal is sent to the local bus If the transaction is write posted a write post error interrupt is sent to the local bus interrupter 0 64 5 2 32ms 1 lms 3 The timer is disabled 2 66 Computer Group Literature Center Web Site LCSR Programming Model Prescaler Control Register ADR SIZ FFF4004C 8 bits of 32 BIT 1 0 Prescaler Adjust OPER R W RESET DFP The prescaler provides the various clocks required by the counters and timers in the VMEchip2 In order to specify absolute times from these counters and timers the prescaler must be adjusted for different local bus clocks The prescaler register should be programmed based on the following equation This provides a IMHz clock to the Tick timers prescaler register 256 Bclock MHz For example for operation at 25MHz the prescaler value is E7 and at 32MHz it is 0 Non integer local bus clocks introduce an error into the specified times for the various counters and timers This is most notable in the tick timers The tick timer clock can be derived by the following equation tick timer clock Bclock 256 prescaler value Ifthe prescaler is not correctly programmed the bus timers do not generate their specified values and the VMEbus reset time may be violated The maximum clock frequency for the tick timers is the B clock divided by two The prescaler register
284. then the corresponding bit in the address translation address register drives the appropriate VMEbus address line If you clear the bit in the address translation select register then the corresponding local bus address line drives the appropriate VMEbus address line The most significant bit of the address translation select register corresponds to the most significant bit of the address translation address register and to A32 of the local bus and A32 of the VMEbus 2 38 Computer Group Literature Center Web Site LCSR Programming Model Write posting is enabled for the segment by setting the write post enable bit in the address modifier register D16 transfers are forced by setting the D16 bit in the address modifier register A segment is enabled by setting the enable bit Segments should not be programmed to overlap The first I O map decoder maps the local bus address range FFFF0000 to FFFFFFFF to the A16 short I O map of the VMEbus This segment may be enabled using the enable bit Write posting may be enabled for this segment using the write post enable bit The transfer size may be D16 or D32 as defined by the D16 bit in the control register The second I O map decoder provides support for the other I O map of the VMEbus This decoder maps the local bus address range F0000000 to FOFFFFFF to the A24 map of the VMEbus and the address range 1000000 to SFF7FFFFF to the A32 map of the VMEbus The transfer size is always D16
285. tile RAM NVRAM 1 3 memory map 1 41 see BBRAM 1 41 overflow counter output tick timer 1 3 23 tick timer 2 3 22 overflow counter VMEchip2 ASIC 2 72 2 73 P P2 connector and Ethernet station address 1 15 parallel port interface PCCchip2 ASIC 3 6 parallel printer port 1 14 PCCchip2 ASIC 82596CA LAN controller interface 3 3 BBRAM interface 3 3 block diagram 3 2 CD2401 SCC interface 3 7 Chip ID register 3 15 Chip Revision register 3 14 features 3 1 functional description 3 2 General Control register 3 15 general purpose I O pin 3 7 LANC Error Status and Interrupt Control registers 3 34 memory map 1 32 3 10 parallel port interface 3 6 programming model 3 11 programming printer port 3 39 programming SCSI Error Status and Interrupt registers 3 37 programming tick timers 3 18 SCC Error Status register and Interrupt Control registers 3 27 SCSI controller interface 3 6 tick timer support 1 16 3 9 Vector Base register 3 16 periodic interrupt example 1 47 periodic interrupts PCCchip2 ASIC 3 18 Petra ASIC functionality of 1 2 redundancies with VMEchip2 1 18 PIACK register modem 3 31 polarity GPIO 3 24 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer paper error 3 42 printer select 3 41 power monitor function VMEbus 2 17 powerup reset VMEchip2 ASIC 2 70 prescaler clock PCCchip2 ASIC 3 21 Clock Adjust register PCCchip2 ASIC 3 20 Count register PCCchip2 ASIC 3 20 VMEc
286. tion DERC also allows the write portion of a read modify write to complete regardless of whether or not there was a multiple bit error during the read portion of the read modify write DERC also affects scrub cycles Scrub Control Register ADR SIZ 1st FFF43024 2nd FFF43124 8 bits BIT 31 30 29 28 27 26 25 24 0 0 0 5 0 SBEIEN RWBO OPER R R R R R W R R W R W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS X 0 PLS 0 PLS 0 RWBO is general purpose read write bit SBEIEN Setting SBEIEN causes the logging of a single bit error to create a true pulse on the INT signal pin SCRBEN This control bit enables the scrubber to operate When SCRBEN is set the MCECC sector immediately performs a scrub of the entire DRAM array When the scrub is complete if software has cleared SCRBEN then scrubbing is not done again until software sets the SCRBEN bit If software has not cleared the SCRBEN bit then when the amount of time indicated in the Scrub Period SBPD register expires the MCECC sector scrubs the DRAM array again It continues to perform scrubs of the entire DRAM array at the frequency indicated in the SBPD register The scrubber does not start a new scrub once the SCRBEN bit is cleared The time between scrubs is approximately two seconds times the value stored in the SBPD register Note that a power up local or software reset stops the scrubber http
287. tion may have problems For readers who need to know the ASIC specific differences between the previous MCECC and Petra MCECC programming models in detail certain areas of the text in this manual are printed in italics and marked with change bars as is done here Readers should compare those sections to the corresponding sections of the first and second generation manuals Computer Group Literature Center Web Site Introduction Features The Petra ASIC supplants the MCECC memory controller ASIC on MVMEIX7P boards performing the memory control functions previously carried out by the MCECC chip It supplies the programmable interface for the ECC protected 16 32 64 128MB DRAM emulation The following table summarizes the features of the MVME167P and MVME 77P single board computers Table 1 1 MVME1X7P Features Summary Feature MVME167P MVME177P Processor 25 33MHz 32 bit MC68040 50 60MHz 32 bit MC68060 microprocessor microprocessor DRAM 16 32 64 128MB synchronous DRAM SDRAM Configurable to emulate 4 8 16 32 64 128MB ECC protected DRAM MVME1X7P boards use SDRAM Synchronous DRAM in place of DRAM Up to 64MB SDRAM is available on MVME167P boards up to 128MB is available on MVME177P boards SRAM 128KB SRAM with battery backup EPROM Four 44 pin standard PLCC Two 44 pin standard PLCC EPROM sockets EPROM sockets Flash Not available Four Intel 28F008SA Flash memory devices
288. trol Registers The interrupt may come from one or more printer status pins 3 44 Computer Group Literature Center Web Site Programming Model Printer Port Control Register ADR SIZ FFF42037 8 bits BIT T 6 5 4 3 2 1 0 NAME DOEN INP STB FAST MAN OPER R R R R W R W R W R W R W RESET 0 0 0 0 PL 0 PL 0 PL 0 PL 0 PL MAN Manual Strobe Control This bit selects the auto or manual mode for the printer strobe When this bit is low the printer strobe is generated automatically by a write to the Printer Data Register auto mode When this bit is high the strobe pin is directly controlled by the STB control bit manual mode FAST Strobe Timing In auto mode this bit controls the printer strobe timing When this bit is low the strobe time is 212 BCLK periods 10 6 us at 20MHz 8 5 us at 25MHz and 6 4 us at 33MHz When this bit is high the strobe time is 50 BCLK periods 2 5 us at 20M Hz 2 us at 25MHz and 1 5 us at 33MHz Note that the strobe time is the width of the low going pulse generated on the STB pin Also note that after a write to the Printer Data Register the PCCchip2 delays about one strobe time before issuing the STB pulse This bit is not used in manual mode Note The PCCchip2 runs at half the MPU speed on the MVMEIT77P For example MVME177P with 50 MHz MPU will run the PCCchip2 at 25 MHz STB Manual Strobe Control In the manual mode the software co
289. un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem Dem Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class B EN50082 1 1997 Electromagnetic Compatibility Generic Immunity Standard Part 1 Residential Commercial and Light Industry System products also fulfill EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC safety performance In accordance with European Community directives a Declaration of Conformity has been made and is on file within the European Union The Declaration of Conformity is available on request Please contact your sales representative Notice While reasonable efforts have been
290. unter bits 7 0 4 25 scrubbing function 4 8 SDRAM Configuration register 4 33 specifications 4 4 memory accesses indivisible 1 52 memory devices used on board 1 3 memory maps 82596CA Ethernet LAN coprocessor 1 40 BBRAM configuration area 1 42 BBRAM TOD clock 1 41 Cirrus Logic CD2401 serial controller chip 1 36 interrupt acknowledge 1 46 local bus 1 20 local I O devices 1 22 M48T58 BBRAM TOD Clock 1 42 MCECC internal register 1 34 MCECC sector internal registers 4 11 PCCchip2 1 32 PCCchip2 ASIC 3 10 printer 1 31 SCSI 1 41 time of day clock 1 43 VMEbus 1 46 VMEchip2 GCSR 1 30 2 103 VMEchip2 LCSR 1 26 VMEchip2 LCSR summary 2 22 microprocessors used on board 1 3 MIEN master interrupt enable bit 2 74 2 96 modem interrupt control register SCC 3 28 Modem PIACK register PCCchip2 ASIC 3 31 MPU channel attention 3 3 channel attention access 3 4 local bus timeout 1 57 offboard error 1 56 parity error 1 56 port 3 3 port access 3 3 TEA cause unidentified 1 56 MPU Status register programming 2 51 MVME167Bug 177Bug debugging packages C 1 MVME1X7P example of VMEchip2 Tick Timer 1 periodic interrupt 1 47 features 1 3 functional description 1 17 microprocessors 1 3 MVME712M MVME1X7P printer port B 2 N no address increment DMA transfers 2 12 non burst read cycle type 4 5 non burst write cycle type 4 6 IN 8 Computer Group Literature Center Web Site non privileged access cycles VMEbus 2 34 2 37 Non Vola
291. upt status bit is low a local interrupt is not being generated The interrupt status bits are TIC1 TIC2 VILE PE MWP SYSF AB ACF Tick timer 1 interrupt Tick timer 2 interrupt VMEbus IRQI edge sensitive interrupt Not used on MVME1x7P VMEbus master write post error interrupt VMEbus SYSFAIL interrupt Not used on MVMEIx7P VMEbus ACFAIL interrupt http www motorola com computer literature 2 77 VMEchip2 Local Bus Interrupter Status Register bits 16 23 ADR SIZ FFF40068 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME VIA DMA SIG3 SIG2 SIGI SIGO LMI LMO OPER R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter status register When an interrupt status bit is high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are LMO0 SIGO SIG1 SIG2 SIG3 DMA VIA GCSR LMO interrupt GCSR LM1 interrupt GCSR SIGO interrupt interrupt GCSR SIG2 interrupt GCSR SIG3 interrupt DMAC interrupt VMEbus interrupter acknowledge interrupt 2 78 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Status Register bits 8 15 ADR SIZ FFF40068 8 bits of 32 BIT 15 14 13 12 11 10 9 8
292. upter is an edge sensitive interrupter connected to the local bus to VMEbus write post bus error signal line The VMEbus IRQI edge sensitive interrupter is an edge sensitive interrupter connected to the VMEbus IRQI signal line This interrupter is used when one of the tick timers is connected to the IRQ1 signal line When this interrupt is acknowledged the vector is provided by the VMEchip2 and a VMEbus interrupt acknowledge is not generated When this interrupt is enabled the VMEbus IRQ level sensitive interrupter should be disabled The VMEchip2 VMEbus interrupter acknowledge interrupter is an edge sensitive interrupter connected to the acknowledge output of the VMEbus interrupter An interrupt is generated when an interrupt on the VMEbus from VMEchip2 is acknowledged by a VMEbus interrupt handler The tick timer interrupters are edge sensitive interrupters connected to the output of the tick timers The DMAC interrupter is an edge sensitive interrupter connected to the DMAC The GCSR SIG3 0 interrupters are edge sensitive interrupters connected to the output of the signal bits in the GCSR The location monitor interrupters are edge sensitive interrupters connected to the location monitor bits in the GCSR The software 7 0 interrupters can be set by software to generate interrupts The VMEbus 7 1 interrupters are level sensitive interrupters connected to the VMEbus IRQ7 IRQ1 signal lines http www motorola com co
293. us address lines when an A24 VMEbus cycle is used to access a local resource The address translation register should be programmed with the translated address and the address translation select register should be programmed to enable the translated address If address translation is not desired then the address translation registers should be programmed to 0 The address translation address register and the address translation select register operate in the following way If you set a bit in the address translation select register then the corresponding bit in the address translation address register drives the appropriate local bus address line If you clear the bit in the address translation select register then the corresponding VMEbus address line drives the appropriate local bus address line The most significant bit of the address translation select register corresponds to the most significant bit of address translation register and to A32 of the local bus and A32 of the VMEbus In addition to the address translation method previously described the VMEchip2 as used on the MVME1X7P includes an adder which can be used for address translation When the adder is enabled the local bus address is generated by adding the offset value to the VMEbus address lines VA lt 31 16 gt The offset is the value in the address translation offset register If the VMEbus transfer is A24 then the VMEbus address lines VA lt 31 24 gt are forced to 0 before t
294. us Interrupter The interrupter provides all the signals necessary to allow software to request interrupt service from a VMEbus interrupt handler The chip connects to all signals that a VMEbus interrupter is required to drive and monitor Requiring no external jumpers the chip provides the means for software to program the interrupter to request an interrupt on any one of the seven interrupt request lines In addition the chip controls the propagation of the acknowledge on the IACK daisy chain The interrupter operates in release on acknowledge ROAK mode An 8 bit control register provides software with the means to dynamically program the status ID information Upon reset this register is initialized to a status ID of 0F the uninitialized vector in the 68K based environment The VMEbus interrupter has an additional feature not defined in the VMEbus specification The VMEchip2 supports a broadcast mode on the IRQI signal line When this feature is used the normal IRQI interrupt to the local bus interrupter should be disabled and the edge sensitive IRQ1 interrupt to the local bus interrupter should be enabled All boards in the system which are not participating in the broadcast interrupt function should not drive or respond to any signals on the IRQ signal line There are two ways to broadcast an IRQI interrupt The VMEbus interrupter in the VMEchip2 may be programmed to generate a level 1 interrupt This interrupt must be cleared usi
295. ver interface is located on the MVME1X7P main board and the industry standard DB15 connector is located on the MVME712B transition board Support functions for the 82596CA LAN coprocessor are provided by the PCCchip2 ASIC Refer to the 82596CA user s guide and to Chapter 3 PCCchip2 for detailed programming information http www motorola com computer literature 1 15 Programming Issues SCSI Interface The MVME167P and MVME177P single board computers provide for mass storage subsystems through the industry standard SCSI bus These subsystems may include hard and floppy disk drives streaming tape drives and other mass storage devices The SCSI interface is implemented using the NCR 53C710 SCSI I O controller Support functions for the 53C710 are provided by the PCCchip2 ASIC Refer to the 53C710 user s guide and to Chapter 3 PCCchip2 for detailed programming information SCSI Termination It is important that the SCSI bus be properly terminated at both ends Sockets for terminators are provided on the P2 or LCP2 adapter board If the SCSI bus ends at the adapter board termination resistors must be installed on the adapter board 5V power to the SCSI bus TERM power line and termination resistors is supplied through a fuse located on the adapter board in the case of the MVME167P or through a fuse on the MVME712 series transition module and a diode on the adapter board the case of the MVMEI77P Local Resources The
296. which remains in effect until a write is generated to the Vector Base Register Computer Group Literature Center Web Site Programming Model A normal read access to the Vector Base Register yields the value 0F if the read happens before it has been initialized A normal read access yields all Os on bits 0 3 and the value that was last written on bits 4 7 if the read happens after the Vector Base Register has been initialized A suggested setting of the Vector Base Register is 50 ADR SIZ FFF42003 8 bits BIT 7 6 5 4 3 2 1 0 NAME IV7 IV6 IV5 IVA IV3 IV2 IVO OPER R W R W R W R W R R R R RESET 0 PL 0 PL 0 PL 0 PL The encoding for the interrupt sources is shown below where IV3 IVO refer to bits 3 0 of the vector passed during the IACK cycle Interrupt Source IV3 IVO Priority Printer Port BSY 0 Lowest Printer Port PE 1 A Printer Port SELECT 2 Printer Port FAULT 3 Printer Port ACK 4 SCSIIRQ 5 LANC ERR 6 LANC IRQ 7 Tick Timer 2 IRQ 8 Tick Timer 1 IRQ 9 GPIO IRQ A Serial Modem IRQ auto vector mode only B Serial RX IRQ auto vector mode only C M Serial TX IRQ auto vector mode only D Highest The PCCchip2 supports an auto vector mode for the Cirrus Logic CD2401 SCC serial port Refer to the AVEC bit in the following registers SCC Modem Interrupt Control Register SCC Transmit Interrupt Control Register an
297. with optional write protection NVRAM and 8K by 8 Non Volatile RAM NVRAM and Real Time Clock RTC with RTC battery backup and watchdog function SGS Thomson M48T58 Timers Four 32 bit tick timers and watchdog timer in Petra ASIC Two 32 bit tick timers and watchdog timer in VMEchip2 ASIC Software Eight software interrupts including those in the VMEchip2 ASIC Interrupts IO Four EIA 232 D configurable serial ports via P2 and transition module Parallel printer interface via P2 and transition module SCSI interface with DMA via P2 or LCP2 adapter board Ethernet transceiver interface via DB15 connector on transition module http www motorola com computer literature 1 3 Programming Issues Table 1 1 MVME1X7P Features Summary Continued Feature MVME167P MVME177P VMEbus VMEbus system controller functions interface VMEbus to local bus interface A32 A24 D32 D16 D8 Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 Programmable interrupter and interrupt handler Global Control Status register for interprocessor communications DMA capability for fast local memory V MEbus transfers A16 A24 A32 D16 D32 D16 D32 D64 BLT Switches Two pushbutton switches ABORT and RESET Status Indicators Eight LEDs Board Fail FAIL CPU Status STAT CPU Activity RUN System Controller SCON LAN Activity LAN LAN Power 12V SCSI Activity SCSI VME Activity VME
298. www motorola com computer literature 4 19 MCECC Functions SCRB This status bit reflects the state of the scrubber When the scrubber is in the process of doing a scrub this bit is set When the scrubber is between scrubs this bit is cleared Scrub Period Register Bits 15 8 The Scrub Period Control register controls how often a scrub of the entire memory is performed if the SCRBEN bit is set in the Scrub Control register The time between scrubs is approximately two seconds times the value programmed into the Scrub Period register The scrub period can be programmed from once every four seconds to once every 36 hours This register contains bits 15 8 of the Scrub Period register ADR SIZ 1st FFF43028 2nd FFF43128 8 bits BIT 31 30 29 28 27 26 25 24 NAME SBPD15 SBPD14 SBPD13 SBPDI2 SBPD11 SBPDIO SBPD9 SBPD8 OPER R W R W R W R W R W R W R W RESET 1 PLS 1 PLS 1 PLS 1 PLS 1 PLS 1 PLS IPLS 1PLS Scrub Period Register Bits 7 0 This register contains bits 7 0 of the Scrub Period register ADR SIZ 1st FFF4302C 2nd FFF4312C 8 bits BIT 31 30 29 28 27 26 25 24 SBPD7 SBPD67 SBPD5 SBPD4 SBPD3 SBPD2 SBPDI SBPDO OPER R W R W R W R W R W R W R W R W RESET IPLS 5 IPLS 1PLS 1PLS 5 1PLS 1PLS 4 20 Computer Group Literature Center Web Site Programming Model Chip Prescaler
299. ycles 2 clock cycles 2 clock cycles Write 1 or 2 Bytes 9 clock cycles 8 clock cycles 10 clock cycles Cache Coherency The MCECC sector supports the MC680x0 caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle It also supports cache coherency by monitoring the memory inhibit MI signal For a write or read cycle the MCECC sector always waits for MI to be negated before it begins a read or write cycle to the DRAM If another local bus slave asserts or TEA before MI is negated then the MCECC sector never begins the DRAM write cycle Computer Group Literature Center Web Site Functional Description ECC The Petra MCECC sector pair performs single bit error correction and double bit error detection SECDED Since the SDRAM device can deliver data from incremental addresses with each clock tick subject to boundary limitations the Petra MCECC sector does not implement an interleaved memory architecture The SDRAM array is 32 data bits plus seven checkbits wide The depth is dependent on the number and type of SDRAM devices Cycle Types The Petra MCECC sector always initiates burst read write accesses to the SDRAM device If the bus access is not a burst the cycle is terminated early Single and double byte write cycles are read modify write accesses but longword write accesses requ
300. yndrome Decoding Since the memory architecture is 32 data bits plus seven syndrome bits with a non interleaved architecture there is no corresponding entry for Bank in Error The selection of the physical SDRAM bank is decoded from the address bus Consequently the Error Address register must be examined to determine which bank contains the error Given a specific SDRAM configuration the following table relates bits in the Error Address register to the physical bank where the error originated Table 4 5 Identifying SDRAM Bank in Error SDCFG2 SDCFG1 SDCFG0 DRAM Array Size and Bank with the Error Device is 64Mbit x 16 data with one bank composed of 3 devices Device is 64Mbit x 8 data with one bank composed of 5 devices Device is 64Mbit x 8 data with two banks composed of 5 devices each If EA24 0 Bank 0 If EA24 1 Bank 1 Device is 64Mbit x 8 data with four banks composed of 5 devices each If EA 25 24 00 Bank 0 If EA 25 24 01 Bank 1 If EA 25 24 10 Bank 2 If EA 25 24 11 Bank 3 Device is 128Mbit x 8 data with one bank composed of 5 devices Device is 128Mbit x 8 data with two banks composed of 5 devices each If EA25 0 Bank 0 If EA25 1 Bank 1 http www motorola com computer literature 4 37 MCECC Functions 4 38 Computer Group Literature Center Web Site Summary of Changes Introduction This appendix summarize

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