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Motorola MB100 Stereo Amplifier User Manual

1. 12 BITS 4 p 0 MBUFF 4 5 4 fosc CLOCK CONTROL 13 BIT DOWN COUNTER CARRIER OUT P ev 5 LOAD MBUFF SBUFF MODULATOR GATE NBI pers co OUT g DS SYSTEM CONTROL PRIMARY SECONDARY SELECT lt SREG MODULATOR W we CARRIER GENERATOR ENABLE SBUFF gt FLAG a gt MODULATOR 12 BITS CONTROLISTATUS REGISTER EOC INTERRUPT ENABLE MODE BASE DENOTES HIDDEN REGISTER W 0112 Figure 9 7 Modulator Block Diagram MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 75 Camer Modulator Transmitter 9 5 1 Time Mode When the modulator operates in time mode the modulation mark and space periods consist of zero or an integer number of fose 8 clocks 250 kHz 2 MHz osc This provides a modulator resolution of 4 us and a maximum mark and space periods of about 16 ms each However to prevent carrier glitches which could affect carrier spectral purity the modulator control gate and carrier clock are synchronized The carrier signal is activated when the modulator gate opens The modulator gate can only close when the carrier signal is low the output logic level during space periods is low If the carrier generator is in baseband mode BASE bit in MCSR is high the modulator output will be at a logic
2. Figure 4 2 IRQ Function Block Diagram MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Interrupts 41 Interrupts When edge sensitivity is selected for the IRQ interrupt it is sensitive to these cases 1 Falling edge on the IRQ pin 2 Falling edge on any port B pin with pullup enabled When edge and level sensitivity is selected for the IRQ interrupt it is sensitive to these cases 1 Low level on the IRQ pin 2 Falling edge on the IRQ pin 3 Falling edge or low level on any port B pin with pullup enabled External interrupts also can be masked by setting the EIMSK bit in the MSCR register of the IR remote timer See 9 5 4 Modulator Period Data Registers MDR1 MDR2 and MDR3 for details 4 8 Extemal Interrupt Timing If the interrupt mask bit I bit of the CCR is set all maskable interrupts internal and external are disabled Clearing the bit enables interrupts The interrupt request is latched immediately following the falling edge of the IRQ source It is then synchronized internally and serviced as specified by the contents of 3FFA and 3FFB Either a level sensitive and edge sensitive trigger or an edge sensitive only trigger is available via the mask programmable option for the IRQ pin 4 9 Camer Modulator Transmitter Intermupt C MT A CMT interrupt occurs when the end of cycle flag EOC and the end of cycle interrupt enable EOCIE bits are set in the modulator con
3. del aod 49 5 5 2 3 COP During Stop ModE da 49 5 5 2 4 COP Watchdog Timer Considerations 50 EUN AT 51 5 5 3 legal AUI 22 soko xS EG de uu uice goce e we 51 The MCU can be reset from five sources two external inputs and three internal restart conditions The RESET and LPRST pins are inputs as shown in Figure 5 1 All the internal peripheral modules will be reset by the internal reset signal RST Refer to Figure 5 2 for reset timing detail MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Resets 45 Resets 5 3 Extemal Reset RESET The RESET pin is one of the two external sources of a reset This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold This active low input will generate the RST signal and reset the CPU and peripherals Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU NOTE Activation of the RST signal is generally referred to as reset o
4. ee 74 9 5 1 ie MOJE 76 9 5 2 FSK 47 2 5 3 Extended Space 78 9 5 3 1 End Or Cycle EOC Inlem pt 48 28526 0 4 Modulator Control and Status Register MCSR 80 9 5 4 Modulator Period Data Registers MDAZ ard MDAS cis ird RR R 83 The carrier modulator transmitter CMT module provides a means to generate the protocol timing and carrier signals for a wide variety of encoding schemes It incorporates hardware to off load the critical and or lengthy timing requirements associated with code generation from the CPU releasing much of its bandwidth to handle other tasks such as code data generation data decompression or keyboard scanning The CMT does not include dedicated hardware configurations for specific protocols but is intended to be sufficiently programmable in its function to handle the timing requirements of most protocols with minimal CPU intervention When disabled certain CMT registers can be MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 67 Camer Modulator Transmitter 9 3 Overview used to change the state of the infrared out pin IRO directly This feature allows for the generation of future protocols not readily producible by the current architecture The module consists of carrier generator
5. secs Osc Where the subscripts 1 2 n refer to the modulation periods that elapsed while the EXSPC bit was set Similarly to calculate the length of an extended space in FSK mode use the equation SBUFF4 MBUFF2 1 SBUFF2 4 MBUFF 1 SBUFF 665 lexspace m General Release Specification MC68HCO05RC16 Rev 3 0 Carrier Modulator Transmitter CMT MOTOROLA Carrier Modulator Transmitter CMT Modulator Where feg is the frequency output from the carrier generator For an example of extended space operation see Figure 9 9 NOTE The EXSPC feature can be used to emulate a zero mark event SET EXSPC CLEAR EXSPC Figure 9 9 Extended Space Operation 9 5 3 1 End Of Cycle EOC Interrupt At the end of each cycle when the counter is reloaded from MBUFF the end of cycle EOC flag is set If the interrupt enable bit was previously set an interrupt also will be issued to the CPU The EOC interrupt provides a means for the user to reload new mark space values into the MBUFF and SBUFF registers As the EOC interrupt is coincident with reloading the counter MBUFF does not require additional buffering and may be updated with a new value for the next period from within the EOC interrupt service routine ISR To allow both mark and space period values to be updated from within the same ISR SREG is buffered by SBUFF The contents written to SBUFF are transferred to the active register SR
6. amp DIRECTION amp REGISTER BIT INTERNAL LATCHED io 5 gt UE OUTPUT gt oon CONNECTIONS INPUT REG BIT 9 INPUT 1 0 Figure 7 2 I O Circuitry General Release Specification MC68HCO5RC16 Rev 3 0 60 Parallel Input Output I O MOTOROLA General Release Spec ification MC 68HCO5RC 16 8 1 Contents 8 2 Introduction Section 8 Core Timer EE 0 cO 61 8 3 Core Timer Control and Status Register 63 8 4 Core Timer Counter 65 8 5 Computer Operating Properly COP Reset 66 86 Timer During Wat MOd6 mr 66 The core timer for this device is a 14 stage multifunctional ripple counter Features include timer overflow power on reset POR real time interrupt RTI and COP watchdog timer As seen in Figure 8 1 the internal peripheral clock is divided by four and then drives an 8 bit ripple counter The value of this 8 bit ripple counter can be read by the CPU at any time by accessing the core timer counter register CTCR at address 09 A timer overflow function is implemented on the last stage of this counter giving a possible interrupt rate of the internal peripheral clock E 1024 This point is then followed by three more stages with the resulting clock E 4096 driving the real time interrupt circuit RTI The RTI circuit consists of three di
7. 16 Mask OPIO RT PETER 19 Signal Deson Df c ou eed p EGER 21 Vss Reh Ria hE a a 23 IRQ Maskable Interrupt Request 23 eRe ewes 24 0450000084008 25 ere ee CU EORR eR 25 Re Gis oe cet eae ee heb abs couse U 25 tag Vite eee eee ee ee eee ee ee ee eee es ee ee ee 26 PEPE eee ee es ae ee REM 25 4 7 26 Mene 27 GION ock eden 27 MEMO PD dos p a9 OK 27 FON 30 ROM ee eee ee ee aes 30 TT TS 31 Iu OUS Programi ad ud r e C REC es a General Release Specification MOTOROLA Table of Contents 5 Table of Contents 3 1 3 2 3 3 3 4 3 5 3 6 3 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 5 1 D 5 3 5 4 General Release Specification Section 3 Central Processor Unit 99 ll qe 0 Mese rA 33 PCNA obec E we WS S E T 34 mader Regio as oe eee ra a 34 Condition Code 35 Stack Pointer 36 Progam 36 Section 4 Interrupts 22 1 gt adco E EE d 37 SO de doe E Ih Da
8. RESTORE REGISTERS EXECUTE FROM STACK CCR A X PC INSTRUCTION Figure 4 1 Interrupt Processing Flowchart General Release Specification MC68HCO05RC16 Rev 3 0 40 Interrupts MOTOROLA Interrupts Hardware Interrupts 4 6 Hardware Interrupts All hardware interrupts except RESET are maskable by the bit in the CCR If the I bit is set all hardware interrupts internal and external are disabled Clearing the bit enables the hardware interrupts The three types of hardware interrupts are explained in the following sections 4 7 Extemal Intermupt IRQ Port B Keyscan The IRQ pin provides an asynchronous interrupt to the CPU A block diagram of the IRQ function is shown in Figure 4 2 NOTE and BIL instructions will apply to the level on the IRQ pin itself and to the output of the logic OR function with the port B IRQ interrupts The states of the individual port B pins can be checked by reading the appropriate port B pins as inputs The IRQ pin is one source of an external interrupt All port B pins PBO PB7 act as other external interrupt sources if the pullup feature is enabled as specified by the user TO BIH amp BIL gt INSTRUCTION EIMSK 4 DD SENSING PORT B KEYSCAN LATCH TO IRQ INTERRUPT gt PROCESSING IRQ VECTOR FETCH 4 R IN CPU Jo LEVEL MASK OPTION
9. 54 Slop ak PT T 56 2 4 2555 gt 5 58 TT CET 60 Core Timer Block BIagram 62 Core Timer Control and Status Register CTCSR 63 Core Timer Counter Register 65 General Release Specification MOTOROLA List of Figures 11 List of Figures Figure 9 10 9 11 9 12 9 13 A 1 General Release Specification Title Page Carrier Modulator Transmitter Module Block Diagram 69 Carrier Generator Block 70 Carrier Generator Data Register CHR1 72 Carrier Generator Data Register CLR1 72 Carrier Generator Data Register CHR2 72 Carrier Generator Data Register 2 Zu Modulator Block 75 CMT Operation in Time Mode 77 Extended Space Operation 2 ct cece dauacccendawaas 79 Modulator Control and Status Register MCSR 80 Modulator Period Data Register MDR1 83 Modulator Period Data Register MDR2 83 Modulator Period Data Register MDR3 83 Maximum Supply Current versus Internal Losada de 108 MC68HCO5RC8 Memory Map 120 MC68HCO5RC16 Rev 3 0 12 List of Figures MOTOROLA General Release Spec ification
10. lt 00 DIR 3F 99 5 CLRA lt 00 INH 4F 3 CLRX Clear Byte X 00 0 1 INH 5F 3 CLR opr X M lt 00 IX1 eF ff 6 CLR X lt 00 7 5 1 ii 2 CMP opr DIR B1 dd 3 CMP opr EXT Cij hhll 4 CMP oprX Compare Accumulator with Memory Byte A M 1X2 lee ff 5 opr X X1 E1 ff 4 CMP X IX F1 3 COM opr M lt FF M DIR 33 99 5 lt FF INH 43 3 COMX Complement Byte One s Complement Xe X FF X ti1 53 3 COM M lt FF 63 6 COM X M lt FF M IX 73 5 CPX opr i 2 CPX opr DIR B3 dd 3 CPX opr n EXT Cca hhll 4 CPX oprX Compare Index Register with Memory Byte X M 2 2 2 D3 lee ff 5 CPX opr X I1 ff 4 CPX IX 3 DEC opr M lt M 1 DIR 3A 99 5 DECA A lt A 1 INH 4A 3 DECX Decrement Byte X lt X 1 j t t 5A 3 DEC opr X M lt M 1 IX1 6A ft 6 DEC X M lt M 1 IX 7 5 EOR opr IMM A8 ii 2 EOR opr DIR B8 dd 3 EOR opr EXCLUSIVE OR Accumulator with Memory X EXT Cc8 hhll 4 EOR Byte im sig IX2 5 EOR opr X IX1 E8 ff 4 EOR X IX F8 3 INC opr M lt M 1 DIR 3 9d 5 INCA lt A 1 INH 4C 3 INCX Increment Byte X lt X 1 1 INH 5 3 INC M lt M 1 6C 6 INC M l
11. 2 MOTOROLA General Release Spec ification MC 68HCO5RC 16 List of Sections Section 1 General Description 15 Section 2 Memory ssssaosaakuhsaakasuesaes 27 Section 3 Central Processor Unit 33 Section 4 Intemupts 37 Section 5 Resets 2 vekaskauxaddwexkaweus 45 Section 6 Low Power Modes 53 Section 7 Parallel Input Output I O 57 Section 8 Core 61 Section 9 Camer Modulator Transmitter CMT 67 Section 10 Instruction Set 85 Section 11 Specifications 103 Section 12 Mechanical Specifications 111 Section 13 Ordering Information 115 Appendix A MC68HCOBRC8 119 MC68HCO05RC16 Rev 3 0 General Release Specification MOTOROLA List of Sections 3 List of Sections General Release Specification MC68HCO5RC16 Rev 3 0 4 List of Sections MOTOROLA General Release Spec ification MC 68HCO5RC 16 1 1 lz 1 3 1 4 3 5 1 5 1 1 8 8 1 5 4 1 5 6 1 5 7 1 5 8 15 9 2 1 2 3 2 3 1 dd 2 3 3 2 4 MC68HCO05RC16 Rev 3 0 Table of Contents Section 1 General Description iig a ee ee 15 NOU D Eos d id PEE 3A chew ea he EP SEA ROC ER 16 Features
12. 94 10 4 5 Control NSIUCHONS Lu iae oe cee ee GER ACA CER 95 10 5 Instruction Sel SJUmmaly ark ha 96 Section 11 Electric al Specific ations Th GS u3 247265 103 TES 103 TLS Maximum Fete rriei ded dE Ee EXC UE Se d eid 104 Operaing Range idu 6555 690 056s ICE 105 11 5 Thermal Gharacteristice 105 11 6 DC Electrical Characteristics 5 0 106 11 7 DC Electrical Characteristics 2 2 107 11 8 Control Timing 5 0 and 2 2 Vaeseasasaaeret acaks 109 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Table of Contents 9 Table of Contents 12 1 12 3 12 4 185 13 1 13 2 13 3 13 4 13 5 13 6 13 7 2 General Release Specification Section 12 Mechanical Specifications d bh ne ER Edid ad acides d 111 dade en pra URN TUN NE 111 28 Pin Plastic Dual In Line Package GaSe NAI COMPETIT 112 28 Pin Small Outline Integrated Circuit Package Gase TRIP La oak D oes 112 44 Pin Plastic Leaded Chip Carrier Package rcc 113 Section 13 Ordering Information rjr PCI IRL 115 115 MEU LEURS PONS sree od CE ORG e deed AG JOE PR ACRES 115 Application Program 116
13. M68HC05 CPU PA2 CPU REGISTERS ACCUMULATOR PA3 INDEX REGISTER PORTA PA4 010101111 STACK POINTER 0 0 PROGRAM COUNTER c 2 D g lt PA6 CONDITION CODE REGISTER 1 1 1 H 0 SRAM 352 BYTES PB2 PB3 ROM 15 936 BYTES PB4 PORT B KEYSCAN PULLUPS PB5 DATA DIRECTION REGISTER PB6 BURN IN ROM 64 BYTES PB7 Marked pins are available only 44 lead PLCC package Figure 1 1 MC68HCO5RC16 Block Diagram General Release Specification MC68HCO05RC16 Rev 3 0 18 General Description MOTOROLA General Description Mask Options 1 4 Mask Options There are 11 total mask options on the MC68HCO5RC16 including Eight port B pullups e IRQ sensitivity COP enable disable STOP enable disable These are nonprogrammable options in that they are selected at the time of code submission when masks are made These options are as follows PB7PU Port B7 Pullup Interrupt This bit enables or disables the pullup interrupt on port B bit 7 1 Enables the pullup interrupt 0 Disables the pullup interrupt PB6PU Port B6 Pullup Interrupt This option enables or disables the pullup interrupt on port B bit 6 1 Enables pullup interrupt 0 Disables pullup interrupt PB5PU Port B5 Pullup Interrupt This option enab
14. Hd LI E Dy L A 1 A LL h LL 1 e UOO eee Y N Fs eL D xi Les 5 44 1 VIEWBI 0 010 0 25 OlT O N gt 0 007 0 180 MIT 1 R 0 007 0 180 D T Y py E Y CU AUI A 0 004 0 10 SEATING PLANE m G1 gt 1 je f VIEW S 00100 25 Olr m Oh 0 00710 180 1 VIEW S NOTES 1 DATUMS L M AND N ARE DETERMINED INCHES MILLIMETERS WHERE TOP OF LEAD SHOLDERS EXITS DIM MIN MAX MIN MAX PLASTIC BODY AT MOLD PARTING LINE A oss 0605 1740 17 65 2 DIMENSION G1 TRUE POSITION TO BE S T osm ces MEASURED AT DATUM T SEATING PLANE 5 3 DIMENSION AND U DO NOT INCLUDE MOLD C 0165 0 180 420 4 57 FLASH ALLOWABLE MOLD FLASH IS 0 010 E 0090 0110 229 279 0 25 PER SIDE 0013 0 019 033 048 4 DIMENSIONING AND TOLERANCING PER ANSI G 0 050 BSC 1 27 BSC Y14 5M 1982 0 026 0 032 06 081 5 CONTROLLING DIMENSION INCH aT a 6 THE PACKAGE TOP MAY BE SMALLER THAN PACKAGE BOTTOM BY UP TO 0 012 K 0 025 0 64 0 300 DIMENSIONS R AND U ARE DETERMINED R_ 0 650 0 656 16 51 16 66 AT THE OUTERMOST EXTREMES OF THE 0650 0656 1651 16 66 PLASTIC BODY EXCLUSIVE OF THE MOLD v 0 042 0048 107 12 FLASH TIE BAR BURRS GATE BURRS AND w 0042 0048 107 121 NTERLEAD FLASH BUT INCLUDING ANY MISMATCH
15. MC 68HCO5RC 16 List of Tables Table Title Page 4 1 Vector Address for Interrupts and Reset 38 5 1 COP Watchdog Timer Recommendations 50 7 1 FOPIN FUNCIONS NE 59 8 1 RTI and COP Rates at 4 096 MHz Oscillator 64 10 1 Register Memory Instructior s 90 10 2 Read Modify Write Instructions 2 22 2 91 10 3 Jump and Branch INSTUCHONS cuu apa tapa 93 10 4 ButMampulalon Inst cligflic oes pis pre 94 10S acccpit de dH ERU nd ERE ne 95 106 Set SUImITIBE V ausus iino tni tata x aii admissus 96 er 102 13 1 MO Order 118 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA List of Tables 13 List of Tables General Release Specification MC68HCO5RC16 Rev 3 0 14 List of Tables MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 1 General Description 1 1 Contents eoa reor EFE EA B 2232243 14 Mask 15 Signal Description 1 5 1 Vss eer ee 152 IRQ Maskable Interrupt Request 1 5 and DOSUE rsrs sod ab 1 5 4 xo dons dde 1 5 5 LPIBSE cua edidi iR e 1 5 6 sao ss xau 1 5 47 PAUSPAZ
16. EX 53 53 54 NERIS kd Vio apa ada 54 66 LUNTUONM 55 This section describes the low power modes The STOP instruction places the MCU in its lowest power consumption mode In stop mode the internal oscillator is turned off halting all internal processing including timer operation During stop mode the CTCSR 08 bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts The timer prescaler is cleared The bit in the CCR is cleared to enable external interrupts All other registers and memory remain unaltered All input output lines remain unchanged The EIMSK bit is not cleared automatically by the execution of a STOP instruction Care should be taken to clear this bit before entering stop mode MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Low Power Modes 53 Low Power Modes 05 1 N t RL RESET i ON IRQ N IS LCH 7 5 4064 t c 7 9 P O Uu VA INTERNAL N ADDRESS 3FFE X 3FFE J 3FFE X 3FFE i 3FFF BUS N NOTES 1 Represents the internal gating of the OSC1 pin RESET OR INTERRUPT 2 TRQ pin edge sensitive mask option VECTOR FETCH 3 IRQ pin level and edge sensitive mask option Figure 6 1 Stop Recovery Timing Diagram 6 4 Stop Recovery The processor can be brought out of stop m
17. FEM BRCLR opr rel Branch if Bit n Clear PC lt 2 rel 0 1 DIR b4 09 dd rr 5 DIR 65 OB dd 5 DIR 66 OD dd rr 5 DIR 67 OF dd rr 5 BRN rel Branch Never lt 2 rel 1 0 REL 21 rr 3 DIR 60 00 dd rr 5 DIR 61 02 ddrr 5 DIR 62 04 dd rr 5 WES DIR 63 06 dd 5 ee BRSET n opr rel Branch if Bit n Set lt 2 rel 1 1 DIR 04 08 dd rr 5 DIR 65 OA dd rr 5 DIR 66 OC dd rr 5 DIR b7 OE dd 5 DIR D0 10 dd 5 DIR b1 12 dd 5 DIR 62 14 5 63 16 5 BSET n opr Set Bit n Mn lt 1 11 18 5 65 1 5 DIR 66 1 5 DIR 67 1 5 lt PC 2 push PCL SP lt SP 1 push PCH 221421210 BSR rel Branch to Subroutine SP SP 1 REL AD rr 6 lt PC rel CLC Clear Carry Bit C lt 0 0 INH 98 2 CLI Clear Interrupt Mask 1 0 0 INH 9 2 MC68HCO05RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 97 Instruction Set Table 10 6 Instruction Set Summary Continued Effect on o ly DDIS 9 Operation Description CCR 5885 S 5 amp o
18. Program Verlllcallolt ianuae dura RR exa 117 HOM Verification Units HVUS sorry rr 118 MO Order TUBIS cad dudo eae CIRCO CR ede CC 118 Appendix A MC68HC O5RC8 22 lt dom k AR REOR ROSE 119 Leones ate sees oe eee ee ee ie acte Sent Sex 119 Memory 119 MC68HC05RC16 Rev 3 0 10 Table of Contents MOTOROLA General Release Spec ification MC 68HCO5RC 16 Figure 4151 1 2 1 3 159 2 1 2 2 3 1 3 2 4 2 8 1 5 2 5 3 6 1 6 2 7 1 7 2 8 1 8 2 8 3 MC68HCO05RC16 Rev 3 0 List of Figures Title Page MC68HC05RC16 Block 18 quia E ar pax dan 21 ccv qr kee eee E aie ee Rn 22 MFin PLOC PINOUT E OOMNECUONG iddei EE DA EA d 24 MC68HCO5RC16 Memory 28 VO REJSO C E 29 33 acea c kadewedczcbE eedd 34 Interrupt Processing 40 IRGO Function Block Diagrami su cicecxsduavisensous ce 41 Reset Block DIAGIAM i cues saca ddr dor ee 46 Reset and POR Timing Diagram i a 47 COP Watchdog limer LOCATON 2 55 2 gt 51 Stop Recovery Timing
19. Pullups are designed to be capable of pulling to Vi within 25 us for a 100 pF 4 kQ load MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Electrical Specifications 107 Hlec tical Specifications 1 0 15 2 0 INTERNAL CLOCK FREQUENCY MHz XT 25 o 70 C 5 r4 g U a a 5 0 0 5 1 0 Vpp 24V Ta 7 0 to 70 C 0 8 06 4 5 0 4 amp 03 0 2 0 0 5 1 0 LE 90 E 15 2 0 2 1 INTERNAL CLOCK FREQUENCY MHz XTAL 2 2 5 Figure 11 1 Maximum Supply Current versus Internal Clock Frequency General Release Specification MC68HCO05RC16 Rev 3 0 108 Electrical Specifications MOTOROLA Electrical Specifications Control Timing 5 0 Vdc and 2 2 Vdc 118 Control Timing 5 0 Vdc and 2 2 Vdc Characteristic Symbol Min Max Unit Frequency of Operation Crystal fose 42 2 External Clock dc 4 2 Internal Operating Frequency Crystal fosc 2 fop 2 1 MHz External Clock fosc 2 dc 2 1 Cycle Time 480 ns Crystal Oscillator Startup Time toxov 100 ms Stop Recovery Startup Time Crystal Oscillator tii cu 100 ms RESET Pulse Width tn 1 5 Interrupt Pulse Width Low Edge Triggered 125 ns Interrupt Pulse Period ru Note 2 OSC1 Pulse Width tou
20. RESET VECTOR HIGH BYTE RESET VECTOR LOW BYTE Figure 2 1 MC68HC05RC16 Memory 0A 3FF5 3FF6 3FF7 3FF8 3FF9 3FFA 3FFB 3FFC 3FFD 3FFE 3FFF MC68HCO5RC16 Rev 3 0 28 Memory MOTOROLA Addr 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 Register Port A Data Register Port B Data Register Port C Data Register Reserved Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Reserved Timer Control and Status Reg Timer Counter Register Reserved Reserved Reserved Reserved Reserved Reserved IR Timer CHR1 IR Timer CLR1 IR Timer CHR2 IR Timer CLR2 IR Timer MCSR IR Timer MDR1 IR Timer MDR2 IR Timer MDR3 Reserved Reserved MC68HCO05RC16 Rev 3 0 Memory Memory Map Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R R R R R R R R R CTOF RTIF TOFE RTIE TOFC RTFC RT1 RTO R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R IROLN 0 PH5 PH4 PH3 PH2 PH1 PHO IROLP 0 PL5 PL4 PL3 PL2 PL1 PLO 0 0 SH5 SH4 SH3 SH2 SH1 SHO 0 0 SL5 SL4 513 512 511 510 EOC 0 EIMSK EXMRK BASE MODE EOCIE MCGEN MB11 MB10 MB9 MB8 5811 5810 589 588 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MBO SB7
21. toL 90 ns NOTES 1 Vbo 2 0 to 5 5 Vss 0 0 C to 70 C unless otherwise noted 2 The minimum period t should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tcc MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Electrical Specifications 109 Hlec trical Specifications General Release Specification MC68HCO5RC16 Rev 3 0 110 Electrical Specifications MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 12 Mechanical Specific ations 12 1 Contents 12 2 Introducti ll is sous rrr 85824 exa 111 12 3 28 Pin Plastic Dual In Line Package n wa id PPP TTE 12 4 28 Pin Small Outline Integrated Circuit Package S IP DD uuu ui aet cu eh OP OS E aUo EERE ate 112 12 5 44 Plastic Leaded Chip Carrier Package Ge TIT UA C IT 113 12 2 Introduction This section describes the dimensions of the dual in line package DIP small outline integrated circuit SOIC and plastic leaded chip carrier PLCC MCU packages The following figures show the latest packages at the time of this publication To make sure that you have the latest package specifications contact one of the following Local Motorola Sales Office Motorola Mfax Phone 602 244 6609 EMAIL rmfax0 email sps mot com e Worldwide Web wwweb at http design net com Follow Mfax or wwweb on line instr
22. 10 6 Instruction Set Summary Continued o E Pee on g Fonn Operation Description 5885 oz BIH Branch if IRQ Pin High lt 2 rel IRQ 1 REL 2F r 3 BIL rel Branch if IRQ Pin Low lt 2 rel IRQ 0 REL 2 r 3 BIT opr A5 ii 2 BIT opr DIR 5 dd 3 BIT opr EXT C5 hhll 4 BIT opr X Bit Test Accumulator with Memory Byte A M 2 2 gt X2 D5 ee ff 5 BIT opr X IX1 E5 ff 4 BIT X IX F5 3 BLO rel Branch if Lower Same as BCS lt 2 rel C 1 REL 25 rr 3 BLS rel Branch if Lower or Same lt 2 CvZ 1 REL 23 rr 3 BMC rel Branch if Interrupt Mask Clear lt 2 rel 120 REL 2 m 3 BMI Branch if Minus lt 2 rel N 1 REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC lt 2 1 1 REL 2D rr 3 BNE rel Branch if Not Equal lt 2 rel Z 0 REL 26 rr 3 BPL rel Branch if Plus lt 2 rel N 20 REL 2 rr 3 BRA rel Branch Always lt 2 1 1 REL 20 rr 3 DIR 60 01 dd 5 DIR 61 03 dd rr 5 DIR 62 05 dd rr 5 m DIR 63 07 dd r 5
23. 16 Kbyte memory map consisting of user ROM RAM burn in ROM and input output I O Figure 2 1 shows the MC68HCO05RC16 memory map in user mode MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Memory 27 0000 0000 10 001F 32 5 0031 0020 0032 RAM 160 BYTES 00BF 0191 00C0 STACK 0192 00FF 64 BYTES 0255 0100 0256 RAM 128 BYTES 50180 0384 USER ROM 15 920 BYTES 3FAF 16303 3F BO 16304 BURN IN ROM amp VECTORS 64 BYTES 3FEF 16367 16368 USER VECTORS 3FFF 19 BYTES 16383 General Release Specification PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER RESERVED CORE TIMER CONTROL amp STATUS REG CORE TIMER COUNTER REGISTER RESERVED RESERVED IR TIMER CHR1 IR TIMER CLR1 IR TIMER CHR2 IR TIMER CLR2 IR TIMER MCSR IR TIMER MDR1 IR TIMER MDR2 IR TIMER MDR3 RESERVED RESERVED RESERVED UNUSED UNUSED CORE TIMER VECTOR HIGH BYTE CORE TIMER VECTOR LOW BYTE IR TIMER VECTOR HIGH BYTE IR TIMER VECTOR LOW BYTE IRQ PTB KEYSCAN PULLUPS VECTOR HIGH BYTE IRQ PTB KEYSCAN PULLUPS VECTOR LOW BYTE SWI VECTOR HIGH BYTE SWI VECTOR LOW BYTE
24. 3 4 9 4 p a ded 74 9 5 1 Time Mode 76 9 5 2 Por MOOS 2i422 24 Ric B 77 9 5 3 Extended Space 78 9 5 9 1 End Of Cycle Interrupt 79 9 5 3 2 Modulator Control and Status Register 80 9 5 4 Modulator Period Data Registers General Release Specification MDR1 MDR2 and 83 MC68HCO5RC16 Rev 3 0 8 Table of Contents MOTOROLA Table of Contents Section 10 Instruction Set one UE oS eae dps rab b 85 Js di eed 86 10 3 Addressing MONS eec Yd e Ge Ria o eee 86 10 3 1 87 Mig 87 Wee ONGC TTE 87 10 3 4 87 10 3 5 Indexed No 5 88 10 3 6 indexed Le sa ek ERE 88 10 3 7 Indexed 16 Bit 88 pont A 0 00 cec 89 10 4 Instruction 22222 22 22252 2 1 42 2 2 1 4 89 10 4 1 Register Memory 90 10 4 2 Read Modify Write 91 10 4 3 Jump Branch 51 5 92 10 44 Manipulation
25. A M 2 04 5 AND opr X 1 1 E4 ff 4 AND X IX F4 3 ASL opr DIR 38 99 5 ASLA 48 3 ASLX Arithmetic Shift Left Same as LSL C 0 11111 INH 58 3 ASL opr X b7 50 68 ff 6 ASL X IX 78 5 ASR opr DIR 37 dd 5 ASRA INH 47 3 ASRX Arithmetic Shift Right gt tit INH 57 3 ASR opr X b7 50 67 ff 6 ASR X IX 77 5 BCC rel Branch if Carry Bit Clear lt 2 rel C 0 REL 24 rr 3 DIR D0 11 dd 5 DIR 61 13 dd 5 DIR 62 15 5 63 17 dd 5 BCLR n opr Clear Bit n Mn 0 DIR 64 19 dd 5 DIR b5 1B dd 5 DIR b6 1D dd 5 b7 1F dd 5 BCS rel Branch if Carry Bit Set Same as BLO lt 2 1 REL 25 m 3 BEQ Branch if Equal lt 2 rel Z 1 REL 27 rr 3 BHCC rel Branch if Half Carry Bit Clear lt 2 rel H 0 REL 28 3 BHCS rel Branch if Half Carry Bit Set lt 2 rel H 1 REL 29 rr 3 BHI Branch if Higher lt 2 2 0 REL 22 rr 3 BHS rel Branch if Higher or Same lt 2 20 REL 24 rr 3 MC68HCO05RC16 Rev 3 0 96 Instruction Set MOTOROLA Instruction Set Instruction Set Summary Table
26. BETWEEN THE TOP AND BOTTOM x 0 042 0458 10 142 OF THE PLASTIC BODY we 7 DIMINSION H DOES NOT INCLUDE DAMBAR 2 2 10 2 10 PROTRUSION OR INTRUSION THE DAMBAR G1 0610 0630 1550 16 00 PROTUSION S SHALL NOT CAUSE THE H 0 040 102 DIMINSION TO BE GREATER THAN 0 037 0 940114 THE DAMBAR INTRUSION S SHALL NOT CAUSE THE DIMINISION TO SMALLER HAN 0 025 0 635 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Mechanical Specifications 113 Mechanical Specific ations General Release Specification MC68HCO05RC16 Rev 3 0 114 Mechanical Specifications MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 13 Ordering Information 13 1 Contents Jeu MPOC ode pep bio Sse de dee EY 115 13 3 MULT Ordering PONE iis s XR XC dae ieda CR SCR 115 13 4 Application Program Media 116 13 5 Program VenfiballD Lua eaa 117 13 6 ROM Verification Units 5 118 13 7 MU Order MUGS ius p DECR E EORR d RI a CP RD 118 13 2 Introduction This section contains ordering instructions for the MC68HC705RC16 13 3 MCU Ordering Forms To initiate an order for a ROM based MCU first obtain the current ordering form for the MCU from a Motorola representative Submit the following items when ordering MCUs e MCU ordering form that is completely filled out Contact
27. Description MOTOROLA 1 5 4 RESET 1 5 5 LPRST 1 5 6 IRO 1 5 7 PAO PA7 General Description Signal Description This active low pin is used to reset the MCU to a known startup state by pulling RESET low The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity See Section 5 Resets The LPRST pin is an active low pin and is used to put the MCU into low power reset mode In low power reset mode the MCU is held in reset with all processor clocks halted See Section 5 Resets The IRO pin is the high current source and sink output of the carrier modulator transmitter subsystem which is suitable for driving infrared IR LED biasing logic See Section 9 Carrier Modulator Transmitter CMT These eight I O lines comprise port A The state of any pin is software programmable and all port A lines are configured as inputs during power on or reset For detailed information on I O programming see 2 4 Input Output Programming 1 5 8 PBO PB7 These eight lines comprise port B The state of any pin is software programmable and all port B lines are configured as inputs during power on or reset Each port B I O line has a mask optionable pullup interrupt for keyscan For detailed information on I O programming see 2 4 Input Output Programming MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA General Description 25 General Description 1 5 9 PCO PC3 4 7 N
28. Operating Range 11 5 Themal Characteristics Characteristic Symbol Value Unit Operating Temperature Range T Tj to Ty MC68HCO5RC16 Standard 0 to 70 Characteristic Symbol Value Unit Thermal Resistance Plastic Dual In Line Package 60 C W Small Outline Intergrated Circuit Package JA 60 Plastic Leaded Chip Carrier Package 60 MC68HCO05RC16 Rev 3 0 General Release Specification MOTOROLA Electrical Specifications 105 Hlec tical Specifications 11 6 DC Electrical Characteristics 5 0 Vdc Output High Voltage l oap 2 0 mA Port A Port B Port C 1 7 Characteristic Max Unit Output Voltage 10 0 pA 0 1 V 10 0 uA LPRST OSC1 Input Low Voltage l 20 mA IRO l oan 4 0 mA Port C Bit 0 Output Low Voltage l 3 0 mA Port A Port B Port 1 7 V 25 0 mA IRO 1 20 0 mA Port C Bit 0 Input High Voltage aw Port A Port B Port C IRQ RESET V Port A Port B Port C Input Current RESET LPRST IRQ OSC1 PBO PB7 with Pullups Enabled Port A Port B Port C IRQ RESET V LPRST OSC1 Supply Current see Notes Run 4 0 mA Wait 1 0 mA Stop 25 10 0 0 to 70 C 20 0 Ports Hi Z Leakage Current 10 Vy 0 2 x Vapi 700 ps PBO PB7 with Pullups Enable
29. Stack pointer ff Offset byte in indexed 8 bit offset addressing X Index register H Half carry flag 2 Zero flag hh Il High and low bytes of operand address in extended addressing Immediate value Interrupt mask Logical AND ii Immediate operand byte v Logical OR IMM Immediate addressing mode e Logical EXCLUSIVE OR INH Inherent addressing mode Contents of IX Indexed no offset addressing mode Negation two s complement IX1 Indexed 8 bit offset addressing mode Loaded with IX2 Indexed 16 bit offset addressing mode If M Memory location 2 Concatenated with N Negative flag 1 Set or cleared n Any bit Not affected MC68HCO05RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 101 01 19 uononuisu VIOYOLOW jeeuec 06 ABH 9L0HS00H8990IN Table 10 7 Opcode Map Bit Manipulation Branch Read Modify Write Control Register Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX MSB MSB LSB 0 1 2 3 4 5 6 7 8 9 A B D E F LSB 5 5 3 3 0 BRSETO BSETO BRA SUB 0 3 DIR D REL X 5 5 3 3 1 BRCLRO BCLRO BRN CMP 1 3 DIR 2 D REL 5 5 3 2 BRSET1 BSET1 BHI SBC 2 3 DIR 2 D REL X 5 5 3 3 BRCLR1 BCLR1 BLS CPX 3 3 DIR 2 D REL X 5 5 3 4 BRSET2 BSET2 BCC AND 4 3 DIR 2 DIR 2 REL 5 5 3 3 5 BRCLR2 BCLR2
30. When the stop enable mask option is selected stop mode disables the oscillator circuit and thereby turns the clock off for the entire device When stop is executed the COP counter will hold its current state If a reset is used to exit stop mode the COP counter is reset and held until 4064 POR cycles are completed at this time counting will begin If an external IRQ is used to exit stop mode the COP counter does not wait for the completion of the 4064 POR cycles but does count these cycles It is therefore recommended that the COP is fed before executing the STOP instruction MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Resets 49 Resets 5 5 2 4 COP Watchdog Timer Considerations The COP watchdog timer is active in all modes of operation if enabled by a mask option If the COP watchdog timer is selected by a mask option any execution of the STOP instruction either intentionally or inadvertently due to the CPU being disturbed causes the oscillator to halt and prevents the COP watchdog timer from timing out If the COP watchdog timer is selected by a mask option the COP resets the MCU when it times out Therefore it is recommended that the COP watchdog be disabled for a system that must have intentional uses of the wait mode for periods longer than the COP time out period The recommended interactions and considerations for the COP watchdog timer STOP instruction and WAIT instruction are summarized in Tab
31. carrier generator data registers CHR1 and CLR1 The IRO latch can be written to on either edge of the internal bus clock 2 allowing for IR waveforms which a resolution of twice the bus clock frequency fosc See 9 4 2 Carrier Generator Data Registers CHR1 CLR1 CHR2 and CLR2 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 69 Modulator Transmitter 9 4 Camer Generator The carrier signal is generated by counting a predetermined number of input clocks 500 ns for a 2 MHz oscillator for both the carrier high time and the carrier low time The period is determined by the total number of clocks counted The duty cycle is determined by the ratio of high time clocks to total clocks counted The high and low time values are user programmable and are held in two registers An alternate set of high low count values is held in another set of registers to allow the generation of dual frequency FSK frequency shift keying protocols without CPU intervention The MCGEN bit in the MCSR must be set and the BASE bit in the MCSR must be cleared to enable carrier generator clocks The block diagram is shown in Figure 9 2 SECONDARY HIGH COUNT REGISTER P PRIMARY HIGH COUNT REGISTER 2 6 MODE U BASE 5 CLK UP COUNTER 2 gt PRIMARY CARRIER GENE
32. dpdut d deb opo Print bie seen 37 CPU Inonr pt PTOGOSSITD suoni aura amica hh xo 38 Reset Interrupt 5 39 dca de 39 Fargware InIGtrUpls uas eue RR ee Gare ICE mE md f 41 External Interrupt IRQ Port 41 External Interrupt Timing 42 Carrier Modulator Transmitter Interrupt 42 Gore imer NUE 43 Section 5 Resets DON BR e edi ee ee ee ree d ed oae edes eT 45 ie dra n Rd eee E S Ha 45 External Reset 5 46 Low Power External Reset LPRST 48 MC68HCO05RC16 Rev 3 0 6 Table of Contents MOTOROLA Table of Contents 5 5 Internal 48 5 5 1 Power On Reset POR asas uncta RR ERR siss 48 5 5 2 Computer Operating Properly Reset COPR 49 9 9 2 1 Resetting the 49 5 5 2 2 COP D ring Wal sux gu 49 5 5 2 3 GOP D ring Stop MONE 49 5 5 2 4 COP Watchdog Timer Considerations 50 5 5 2 5 OOP POG 51 5 5 3 Ilegal 51 Section 6 Low Power Modes DI 223 Koo Xd ado dr es SCREAM AS 53 62 introd
33. its input to improve noise immunity Refer to Section 4 Interrupts for more detail MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA General Description 23 General Description 1 5 3 OSC1and OSC2 These pins provide control input for an on chip clock oscillator circuit A crystal a ceramic resonator or an external signal connects to these pins to provide a system clock The oscillator frequency is two times the internal bus rate Figure 1 5 shows the recommended circuit when using a crystal The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time A ceramic resonator may be used in place of the crystal in cost sensitive applications Figure 1 5 a shows the recommended circuit for using a ceramic resonator The manufacturer of the particular ceramic resonator being considered should be consulted for specific information An external clock should be applied to the OSC1 input with the OSC2 pin not connected see Figure 1 5 b This setup can be used if the user does not want to run the CPU with a crystal OSCI 0SC2 10 MQ UNCONNECTED I EXTERNAL CLOCK 30 30pF a Crystal Ceramic Resonator b External Clock Source Oscillator Connections Connections Figure 1 5 Oscillator Connections General Release Specification MC68HCO05RC16 Rev 3 0 24 General
34. of On Chip RAM e 14 Stage Core Timer with Real Time Interrupt RTI and Computer Operating Properly COP Watchdog Circuits Carrier Modulator Transmitter Supporting Baseband Pulse Length Modulator PLM and Frequency Shift Keying FSK Protocols General Release Specification MC68HCO05RC16 Rev 3 0 16 General Description MOTOROLA General Description Features Low Power Reset Pin e 20 Bidirectional I O Lines Four Additional I O Lines Available for Bond Out in 44 Lead PLCC Package Mask Programmable Pullups and Interrupts on Eight Port Pins PBO PB7 e High Current Infrared IR Drive Pin e High Current Port Pin PCO e Power Saving Stop and Wait Modes e Mask Selectable Options Watchdog Timer STOP Instruction Disable Edge Sensitive or Edge and Level Sensitive Interrupt Trigger Port B Pullups for Keyscan e Illegal Address Reset e ROM Security Feature NOTE Aline over a signal name indicates an active low signal For example RESET is active low MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA General Description 17 General Description 05 2 CARRIER 05 1 OSCILLATOR MODULATOR IRO IRQEN TRANSMITTER V i UD 2 DD INTERNAL Vss PROCESSOR CLOCK COP RTI SYSTEM SYSTEM PCO 1 2 CORE TIMER SYSTEM PC3 PORTC PC4 PC5 DATA DIRECTION REGISTER PC6 PC7 CPU CONTROL PAD PAL
35. one for the duration of the mark period and at a logic zero for the duration of a space period See Figure 9 8 The mark and space time equations are MBUFF 1 8 tmark secs osc SBUFF x8 Setting the DIV2 bit in the MCSR will double mark and space times General Release Specification MC68HCO5RC16 Rev 3 0 76 Carrier Modulator Transmitter CMT MOTOROLA fosc 8 CARRIER FREQUENCY MODULATOR GATE TIME MODE OUTPUT BASEBAND OUTPUT 9 5 2 FSK Mode Carrier Modulator Transmitter CMT Modulator MARK SPACE MARK SPACE MARK Figure 9 8 CMT Operation in Time Mode When the modulator operates in FSK mode the modulation mark and space periods consist of an integer number of carrier clocks space period can be zero When the mark period expires the space period is transparently started as in time mode however in FSK mode the carrier switches between data registers in preparation for the next mark period The carrier generator toggles between primary and secondary data register values whenever the modulator mark period expires The space period provides an interpulse gap no carrier but if SBUFF 0 then th
36. or outputs under software control of the data direction registers To avoid a glitch on the output pins write data to the I O port data register before writing a one to the corresponding data direction register Port A is an 8 bit bidirectional port which does not share any of its pins with other subsystems The port A data register is at 0000 and the data direction register DDR is at 0004 Reset does not affect the data register but clears the data direction register thereby returning the ports to inputs Writing a one to a DDR bit sets the corresponding port bit to output mode MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Parallel Input Output I O 57 Parallel Input Output I O 7 4 Port B 7 5 Port C NOTE Port B is an 8 bit bidirectional port which does not share any of its pins with other subsystems The address of the port B data register is 0001 and the data direction register DDR is at address 0005 Reset does not affect the data register but clears the data direction register thereby returning the ports to inputs Writing a one to a DDR bit sets the corresponding port bit to output mode Each of the port B pins has a mask programmable pullup device that can be enabled When the pullup device is enabled this pin will become an interrupt pin also The edge or edge and level sensitivity of the IRQ pin also will pertain to the enabled port B pins Care needs to be taken when using port B
37. pins that have the pullup enabled Before switching from an output to an input the data should be preconditioned to a logic one or the bit should be set in the condition code register to prevent an interrupt from occurring The EIMSK bit in the CMT MCSR register can be used to mask port B keyscan and external interrupts IRQ When a port B pin is configured as an output it s corresponding keyscan interrupt is disabled regardless of it s mask option Von DISABLE DI MASK OPTION PB7PU o DDR BIT ENABLED PB7 e NORMAL PORT CIRCUITRY AS SHOWN IN FIGURE 7 2 IRQEN TO INTERRUPT LOGIC FROM ALL OTHER PORT B PINS Figure 7 1 Port B Pullup Option Port C is 8 bit bidirectional port PCO PC7 which does not share any of its pins with other subsystems The port C data register is at 0003 and the data direction register DDR is at 0006 Reset does not affect the data register but clears the data direction register thereby returning General Release Specification MC68HCO05RC16 Rev 3 0 58 Parallel Input Output I O MOTOROLA Parallel Input Output I O Input Output Programming the ports to inputs Writing a one to a DDR bit sets the corresponding port bit to output mode Port C pins PC4 PC7 are available only with the 44 lead PLCC package NOTE Only four bits of port C are bonded out in 28 pin packages for the MC68HCO5RC16 although port C is truly a
38. power turn on conditions and is not able to detect a drop in the power supply voltage brown out There is an oscillator stabilization delay of 4064 internal processor bus clock cycles PH2 after the oscillator becomes active The POR generates the RST signal that resets the CPU If any other reset function is active at the end of this 4064 cycle delay the RST signal remains in the reset condition until the other reset condition s ends General Release Specification MC68HCO05RC16 Rev 3 0 48 Resets MOTOROLA Resets Internal Resets 5 5 2 Computer Operating Properly Reset COPR The MCU contains a watchdog timer that automatically times out if not reset cleared within a specific time by a program reset sequence If the COP watchdog timer is allowed to time out an internal reset is generated to reset the MCU The COP reset function is enabled or disabled by a mask option and is verified during production testing 5 5 2 1 Resetting the COP Writing a zero to the COPF bit prevents a COP reset This action resets the counter and begins the time out period again The COPF bit is bit 0 of address 3FFO A read of address 3FFO returns user data programmed at that location 5 5 2 2 COP During Wait Mode The COP continues to operate normally during wait mode The software should pull the device out of wait mode periodically and reset the COP by writing to the COPF bit to prevent a COP reset 5 5 2 8 COP During Stop Mode
39. spurious operation This bit is cleared by reset 1 Modulator and carrier generator enabled 0 Modulator and carrier generator disabled General Release Specification MC68HCO05RC16 Rev 3 0 82 Carrier Modulator Transmitter CMT MOTOROLA Carrier Modulator Transmitter CMT 9 5 4 Modulator Period Data Registers MDRI MDR2 and MDR3 Modulator The 12 bit MBUFF and SBUFF registers are accessed through three 8 bit registers MDR1 MDR2 and MDR3 MDR2 and MDRS contain the least significant eight bits of MBUFF and SBUFF respectively MDR1 contains the two most significant nibbles of MBUFF and SBUFF In many applications periods greater than those obtained by eight bits will not be required Dividing the registers in this manner allows the user to clear MDR1 and generate 8 bit periods with just two data writes Address Read Write Reset Address Read Write Reset Address Read Write Reset MC68HCO05RC16 Rev 3 0 0015 Bit7 6 5 4 3 2 1 Bit 0 11 MB10 MB9 MB8 5811 5810 589 588 Unaffected by Reset Figure 9 11 Modulator Period Data Register MDR1 0016 Bit7 6 5 4 3 2 1 Bit 0 7 MB6 MB5 MB4 MB3 MB2 MB1 MBO Unaffected by Reset Figure 9 12 Modulator Period Data Register MDR2 0017 Bit 7 6 5 4 3 2 1 Bit 0 5 7 SB6 SB5 5 4 SB3 SB2 5 1 580 Unaffected by Reset Figure 9 1
40. these bits contain the number of input clocks required to generate the carrier high and low time periods When operating in time mode see 9 5 1 Time Mode this register pair is never selected When operating in FSK mode see 9 5 2 FSK Mode this register pair and the secondary register pair are alternately selected under control General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 73 Modulator Transmitter NOTE 9 5 Modulator of the modulator The secondary carrier high and low time values are undefined out of reset These bits must be written to nonzero values before the carrier generator is enabled when operating in FSK mode IROLN and IROLP IRO Latch Control Reading IROLN or IROLP reads the state of the IRO latch Writing IROLN updates the IRO latch with the data being written on the negative edge of the internal processor clock fosc 2 Writing IROLP updates the IRO latch on the positive edge of the internal processor clock for example fosc period later The IRO latch is clear out of reset Writing to CHR1 to update IROLN or to CLH1 to update IROLP will also update the primary carrier high and low data values Care should be taken that bits 5 0 of the data to be written to CHR1 or CHL1 should contain the desired values for the primary carrier high or low data The modulator consists of a 12 bit down counter with underflow detection which is loaded from the mod
41. to location 00FF The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack When accessing memory the seven most significant bits are permanently set to 0000011 These seven bits are appended to the six least significant register bits to produce an address within the range of 00FF to 00 0 Subroutines and interrupts may use up to 64 decimal locations If 64 locations are exceeded the stack pointer wraps around and loses the previously stored information A subroutine call occupies two locations on the stack an interrupt uses five locations 3 7 Program Counter The program counter PC is a 13 bit register that contains the address of the next byte to be fetched PC NOTE TheHCO05 CPU core is capable of addressing a 64 Kbyte memory For this implementation however the addressing registers are limited to an 16 Kbyte memory map General Release Specification MC68HCO05RC16 Rev 3 0 36 Central Processor Unit MOTOROLA General Release Spec ification MC 68HCO5RC 16 4 1 Contents 4 2 Introduction 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 Section 4 Intemupts EON Lada oe PEE edad OPE rd GPU Interrupt Processing ur ice aca dard eda qne CR CR Reset Interrupt Software Interrupt SW u einen eres ea Ehe RC ee Hardware Inter Ups RR a da cca Rr e
42. your Motorola sales office for assistance Acopy of the customer specification if the customer specification deviates from the Motorola specification for the MCU e Customer s application program on one of the media listed 13 4 Application Program Media MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Ordering Information 115 Ordering Information The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service BBS The telephone number is 512 891 FREE After making the connection type bbs in lower case letters Then press the return key to start the BBS software 13 4 Application Program Media Please deliver the application program to Motorola in one of the following media Macintosh 3 1 2 inch diskette double sided 800K or double sided high density 1 4 M 5 005 2 or PC DOS 3 1 2 inch diskette double sided 720 K or double sided high density 1 44 M MS DOS or PC DOS 5 1 4 inch diskette double sided double density 360 K or double sided high density 1 2 M Use positive logic for data and addresses When submitting the application program on a diskette clearly label the diskette with the following information Customer name Customer part number Project or product name File name of object code Date Name of operating system that formatted diskette Formatted capacity of diskette On diskettes the application program must be in Motor
43. 1 Push PCH SP lt SP 1 Push X SPc SP t Push A SWI Software Interrupt SP SP 1 Push 1 INH 83 10 SP lt SP 1 1 1 PCH lt Interrupt Vector High Byte PCL lt Interrupt Vector Low Byte TAX Transfer Accumulator to Index Register X A INH 97 2 General Release Specification MC68HCO5RC16 Rev 3 0 100 Instruction Set MOTOROLA Instruction Set Instruction Set Summary Table 10 6 Instruction Set Summary Continued Effect on 2 151 ue Operation Description CCR 53 S 5 El 2 3215 2 6 TST DIR 3D 94 4 TSTA 140 3 TSTX Test Memory Byte for Negative or Zero M 00 2 214 INH 150 3 TST opr X IX1 eD ff 5 TST X IX 70 4 TXA Transfer Index Register to Accumulator A lt X INH 9F 2 WAIT Stop CPU Clock and Enable Interrupts 0 INH 8 2 A Accumulator Operand one or two bytes C Carry borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed 16 bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP
44. 3 Modulator Period Data Register MDR3 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 83 Camer Modulator Transmitter General Release Specification MC68HCO5RC16 Rev 3 0 84 Carrier Modulator Transmitter CMT MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 10 Instruction Set 10 1 Contents TEE E HER HER Aron 86 10 3 Addressing Modes Ra terr ROC RN 86 10 3 1 87 10 3 2 87 Meee Eso er 87 10 3 4 E 54555 ee ee 87 10 3 5 Indexed No 88 103 6 indexed 88 10 37 Indexed 16 Bi 88 10 38 o 89 pL NE C i 89 10 4 1 Register Memory 1 5 5 90 10 4 2 Read Modify Write 91 104 3 4mpBrancn Inelicllols RET 92 10 4 4 Manipulation 94 1045 QGontrol ss sca deca RACER rE EEEREN 95 10 5 Instruction Set SHPDITIBIV 5 4404 og E ws 4490 nO RR 96 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 85 Instruction Set 10 2 Introduction The MCU instruction set has 62 instructions and uses e
45. 3 2 7 0 ACCUMULATOR 7 0 X INDEX REGISTER 13 0 PC PROGRAM COUNTER 13 7 0 0 0 0 0 0 0 111 SP STACK POINTER CCR H N 7 CONDITION CODE REGISTER Figure 3 1 Programming Model MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Central Processor Unit 33 Cental Processor Unit 7 0 STACK 1 1 1 CONDITIONCODE REGISTER N ACCUMULATOR T INCREASING T E DECREASING MEMORY U INDEX REGISTER R MEMORY ADDRESSES R R ADDRESSES U N PCH PCL UNSTACK NOTE Since the stack pointer decrements during pushes the PCL is stacked first followed by PCH etc Pulling from the stack is in the reverse order Figure 3 2 Stacking Order 3 3 Accumulator The accumulator A is a general purpose 8 bit register used to hold operands and results of arithmetic calculations or data manipulations 7 0 3 4 Index Register The index register X is an 8 bit register used for the indexed addressing value to create an effective address The index register also may be used as a temporary storage area 7 0 General Release Specification MC68HCO05RC16 Rev 3 0 34 Central Processor Unit MOTOROLA Central Processor Unit Condition Code Register 3 5 Condition Code Register The condition code register CCR is a 5 bit register in which four bits are used t
46. 9 E qae 1 58 8 7 1 5 9 PC4 PC7 6 5 16 Rev 3 0 General Release Specification MOTOROLA General Description 15 General Description L2 Introduction MC68HCO5RC16 is a low cost addition to the M68HC05 Family of microcontrollers MCUs and is suitable for remote control applications This device contains the HCO05 central processing unit CPU core including the 14 stage core timer with real time interrupt RTI and computer operating properly COP watchdog systems On chip peripherals include a carrier modulator transmitter The 16 kbyte memory map has 15 936 bytes of user ROM and 352 bytes of RAM There 20 input output I O lines eight having keyscan pullups interrupts and a low power reset pin This device is available in 28 pin small outline integrated circuit SOIC 28 pin dual in line DIP and 44 pin plastic leaded chip carrier PLCC packages Four additional I O lines are available for bond out on the higher pin count package 1 3 Features Features for the MC68HCO5RC16 include Low Cost e HC05 Core e 28 Pin Plastic Dual In Line PDIP Small Outline Integrated Circuit SOIC or Plastic Leaded Chip Carrier PLCC Packages On Chip Oscillator with Crystal Ceramic Resonator e 4 MHz Maximum Oscillator Frequency at 5 V and 2 2 V Supply Fully Static Operation e 15 936 Bytes of User ROM 64 Bytes of Burn In ROM 352 Bytes
47. Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB MC68HCO05RC16 Rev 3 0 90 Instruction Set MOTOROLA Instruction Set Instruction Types 10 4 2 Read Modify White Instructions These instructions read a memory location or a register modify its contents and write the modified value back to the memory location or to the register NOTE use read modify write operations on write only registers Table 10 2 Read Modify Write Instructions Instruction Mnemonic Arithmetic Shift Left Same as LSL ASL Arithmetic Shift Right ASR Bit Clear BCLR Bit Set BSET Clear Register CLR Complement One s Complement COM Decrement DEC Increment INC Logical Shift Left Same as ASL LSL Logical Shift Right LSR Negate Two s Complement NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TsT 1 Unlike other read modify write instructions BCLR and BSET use only direct addressing 2 TST is an exception to the read modify write sequence bec
48. BCS BLO BIT 5 3 DIR 2 DIR 2 REL 5 5 3 6 BRSET3 BSET3 ROR LDA 6 3 DIR 2 D DIR X 5 5 5 4 7 BRCLR3 BCLR3 ASR STA 7 3 DIR 2 D 2 DIR X 5 3 5 3 6 3 8 BRSET4 BSET4 ASL LSL ASL LSL EOR 8 3 DIR 2 D DIR 2 1 1 x 5 5 5 6 3 9 BRCLR4 BCLR4 ROL ROL ADC 9 3 DIR 2 D 2 DIR 2 1 1 5 5 5 6 3 A BRSET5 BSET5 DEC ORA A 3 DIR 2 DIR DIR X 5 5 3 B BRCLR5 BCLR5 ADD B 3 DIR 2 DIR X 5 5 2 BRSET6 BSET6 JMP J JMP 3 DIR 2 DIR EXT 2 2 5 5 5 D BRCLR6 BCLR6 JSR JSR JSR D 3 DIR 2 DIR REL EXT 2 2 x 5 5 3 2 2 3 4 5 4 3 E BRSET7 BSET7 BIL STOP LDX LDX LDX LDX DX LDX E 3 DIR 2 DIR 2 REL 1 INH 2 2 DIR 3 EXT 3 Ix2 2 IX11 X 5 5 3 3 3 6 2 4 6 5 4 F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX STX STX STX F 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH INH 2 DIR 3 EXT 3 Ix2 2 IX11 X i MSB INH Inherent REL Relative S 0 MSB of Opcode in Hexadecimal IMM Immediate IX Indexed No Offset LSB DIR Direct IX1 Indexed 8 Bit Offset 5 Number of Cycles LSB of n Hex mal BRSETO Opcode M EXT Extended IX2 Indexed 16 Bit Offset SB orOpedde im Hexadecimal 0 3 DIR Naber of Bytes addressing Mode TIT ET General Release Spec ification MC 68HCO5RC 16 Section 11 Electrical Specifications 11 1 Contents 112 INOOHODOR roprERRR4 Xd 11 3 Maximum 5 11 4 Operating Range 11 5 Thermal Characteristics 11 6 DC Electri
49. E MOLD ROTRUSION UM MOLD PROTRUSION 0 15 PER SIDE MENSION D DOES NOT INCLUDE AMBAR PROTRUSION ALLOWABLE AMBAR PROTRUSION SHALL BE 0 13 TOTAL IN EXCESS OF D MENSION AT MAXIMUM MATERIAL ON g MILLIMETERS INCHES MIN MAX MIN MAX 17 80 18 05 0 701 0 711 7 40 7 60 0 292 0 299 2 35 2 65 0 093 0 104 0 35 049 0 014 0 019 0 41 0 90 0 016 0 035 1 27 BSC 0 050 BSC 0 23 0 32 0 009 0 013 0 18 0 29 0 005 0 011 0 8 0 8 10 05 10 55 0 395 0 415 v Zz L om o o w gt 0 25 0 75 0 010 0 029 MC68HC05RC16 Rev 3 0 112 Mechanical Specifications MOTOROLA Mechanical Specifications 44 Pin Plastic Leaded Chip Carrier Package Case 777 02 12 5 44 Pin Plastic Leaded Chip Carrier Package Case 777 02 00070 180 1 P U 0 007 0 180 0 T gt 1 m Ly A E 7
50. EG at the end of every cycle regardless of the state of the EOC flag The EOC flag is cleared by a read of the modulator control and status register MCSR followed by an access of MDR2 or MDR3 The EOC flag must be cleared within the ISR to prevent another interrupt being generated after exiting the ISR If the EOC interrupt is not being used IE 0 the EOC flag need not be cleared MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 79 Camer Modulator Transmitter 9 5 3 2 Modulator Control and Status Register The modulator control and status register MCSR contains the modulator and carrier generator enable MCGEN interrupt enable IE mode select MODE baseband enable BASE extended space EXSPC and external interrupt mask EIMSK control bits divide by two prescaler DIV2 bit and the end of cycle EOC status bit Address 0014 Bit7 6 5 4 3 2 1 Bit 0 Read DIV2 EIMSK EXSPC BASE MODE IE MCGEN Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 9 10 Modulator Control and Status Register MCSR EOC End Of Cycle Status Flag EOC is set when a match occurs between the contents of the space period register SREG and the down counter This is recognized as the end of the modulation cycle At this time the counter is initialized with the possibly new contents of the mark period buffer MBUFF and th
51. F MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Low Power Modes 55 STOP Low Power Modes C WAIT 2 STOP OSCILLATOR AND ALL CLOCKS IR TIMER CLOCK ACTIVE CORE TIMER CLOCK ACTIVE CLEAR I BIT PROCESSOR CLOCKS OSCILLATOR ACTIVE STOPPED v INTE v TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE RESTART PROCESSOR CLOCK RRUPT PTB KEYSCAN PULLUPS 1 FETCH RESET VECTOR OR VECTOR OR 2 SERVICE 2 SERVICE INTERRUPT INTERRUPT A STACK A STACK SET BIT B SET I BIT C VECTOR TO C VECTOR TO INTERRUPT INTERRUPT ROUTINE ROUTINE 1 FETCH RESET CORE TIMER INTERNAL INTERRUPT Figure 6 2 Stop Wait Flowchart General Release Specification MC68HCO5RC16 Rev 3 0 56 Low Power Modes MOTOROLA General Release Spec ification MC 68HCO5RC 16 7 1 Contents 7 2 Introduction 7 3 PortA NOTE Section 7 Parallel Input Output I O 57 PE Wer oe oe he ee eee eee 57 DA aes oto eee eer 58 nS 5 1 eee eee yee eee eee ee ee ee 58 78 InpuvOutiut Programming va 59 In user mode 20 lines in 28 pin PDIP or SOIC or 24 lines in 44 lead PLCC are arranged as three 8 bit I O ports These ports are programmable as either inputs
52. HCO5RC16GRS D REV 3 0 MC 68HC 5 8 MC 68HC O5RC 16 General Release Specification October 24 1996 CSIC MCU Design Center Austin Texas Mj MOTOROLA General Release Spec ification Motorola Inc 1996 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MC68HCO05RC16 Rev 3 0
53. Low Voltage l 1 0 mA Port A Port B Port C 1 7 V 0 1 0 3 V 8 0 mA IRO OF 0 1 0 3 7 0 mA Port C Bit 0 0 1 0 3 Input High Voltage V 0 7 x u V V Port A Port B Port C IRQ RESET LPRST OSC1 n Vpp Input Low Voltage ET Port A Port B Port C IRQ RESET LPRST OSC1 Yi Vss ki Supply Current see Notes Run EL 0 3 1 0 mA Wait 0 15 0 3 mA Stop DR 25 C 0 1 1 0 0 to 70 C 0 1 4 0 Ports Hi Z Leakage Current Port A Port B Port C loz B u Input Current RESET LPRST IRQ OSC1 0 4 0 4 PBO PB7 with Pullups Enabled Vin 0 4 x Vpp 2 IN 25 50 105 PBO PB7 with Pullups Enabled ViN 0 7 Vpp 15 34 65 Ports as Input or Output Cour 12 pF RESET LPRST IRQ 8 NOTES 1 Vpn 2 2 10 Vas 0 0 C to 70 C unless otherwise noted 2 Typical values at midpoint of voltage range 25 only represent average measurements 3 Wait Ipp only core timer active 4 Run Operating Ipp wait Ipp Measured using external square wave clock source fose 4 2 MHz all inputs 0 2 V from rail no dc loads less than 50 pF on all outputs C 20 pF on OSC2 5 Wait Stop Ipp Port A and port C configured as inputs port B configured as outputs 0 2 V Vpp 0 2 V 6 Stop Ipp is measured with OSC1 Vas 7 Wait Ipp is affected linearly by the OSC2 capacitance 8
54. O5RC16 have 16 Kbyte memory maps consisting of user ROM RAM burn in ROM and input output I O However the user ROM for the MC68HCO5RC8 consists of only 8112 bytes of ROM Figure A 1 shows the MC68HCO5RC8 memory map in user mode MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA MC68HCO5RC8 119 MC 68HC O5RC 8 0000 001F 0020 00BF 00C0 00FF 0100 017F 0180 1FFF 2000 3FAF 3FBO 3FEF 3FF0 3FFF 10 32 5 RAM 160 BYTES STACK 64 BYTES RAM 128 BYTES UNUSED USER ROM 8112 BYTES BURN IN ROM amp VECTORS 64 BYTES USER VECTORS 16 BYTES 0000 0031 0032 0191 0192 0255 0256 0383 0384 16303 16304 16367 16368 16383 PORT A DATA REGISTER 00 PORT B DATA REGISTER 01 PORT C DATA REGISTER 02 RESERVED 03 PORT A DATA DIRECTION REGISTER 04 PORT B DATA DIRECTION REGISTER 05 PORT C DATA DIRECTION REGISTER 06 RESERVED CORE TIMER CONTROL amp STATUS REG 08 CORE TIMER COUNTER REGISTER 09 RESERVED 0A RESERVED 0F IR TIMER CHR1 10 IR TIMER CLR1 51 IR TIMER CHR2 12 IR TIMER CLR2 13 IR TIMER MCSR 14 IR TIMER MDR1 15 IR TIMER MDR2 16 IR TIMER MDR3 17 RESERVED 18 RESERVED 1E RESERVED 1F UNUSED ais UNUSED 3FF5 CORE TIMER VECTOR HIGH BYTE 3FF6 C
55. ORE TIMER VECTOR LOW BYTE 3FF7 IR TIMER VECTOR HIG H BYTE 3FF8 IR TIMER VECTOR LOW BYTE 3FF9 IRQ PTB KEYSCAN PULLUPS 3FFA VECTOR HIGH BY TE IRQIPTBKEYSCAN PULLUPS VECTOR LOW BY SWI VECTOR HIGH BYTE 3FFC SWI VECTOR LOW B RESET VECTOR HIGH RESET VECTOR LOW TE YTE 3FFD BYTE 3FFE BYTE 3FFF Figure 1 MC68HCO5RC8 Memory Map General Release Specification MC68HCO5RC16 Rev 3 0 120 MC68HCO5RC8 MOTOROLA Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical im
56. OTE NOTE These eight I O lines comprise port C PCO is a high current pin PC4 PC7 are available only in the 44 lead PLCC package The state of any pin is software programmable and all port C lines are configured as input during power on or reset For detailed information on programming see 2 4 Input Output Programming Only four bits of port C are bonded out in 28 pin packages for the MC68HCO5RC16 although port C is truly an 8 bit port Since pins 4 are unbonded software should include the code to set their respective data direction register locations to outputs to avoid floating inputs Any unused inputs I O ports and no connects should be tied to an appropriate logic level either Vpp Vss Although the I O ports of the do not require termination termination is recommended to reduce the possibility of static damage General Release Specification MC68HCO05RC16 Rev 3 0 26 General Description MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 2 Memory 2 1 Contents Bo OGIO S atre 27 Ed MEMON MAD wee ER 27 218 1 RON E eee ee d o oa 30 2 3 2 ROM Security rt 30 23 9 RAM addas Add 21 2 4 41 2 2 Introduction This section describes the organization of the on chip memory 2 3 Memory Map The MC68HCO5RC16 has
57. RATOR M SECONDARY ENABLE 5 SELECT 0 5 a CARRIER OUT E SECONDARY LOW COUNT REGISTER PRIMARY LOW COUNT REGISTER Figure 9 2 Carrier Generator Block Diagram General Release Specification MC68HCO05RC16 Rev 3 0 70 Carrier Modulator Transmitter CMT MOTOROLA 9 4 1 Time Counter NOTE Carrier Modulator Transmitter CMT Carrier Generator The high low time counter is a 6 bit up counter After each increment the contents of the counter are compared with the appropriate high or low count value register When this value is reached the counter is reset and the compare is redirected to the other count value register Assuming that the high time count compare register is currently active a valid compare will cause the carrier output to be driven low The counter will continue to increment and when reaching the value stored in the selected low count value register it will be cleared and will cause the carrier output to be driven high The cycle repeats automatically generating a periodic signal which is directed to the modulator The lowest frequency maximum period and highest frequency minimum period which can be generated are defined below fmin fosc 2 x 28 1 Hz fmax fosc 2 X T Hz In the general case the carrier generator output frequency is fout fose Highcount Lowcount Hz Where 0 lt Highcount lt 64 and 0 lt Lowcount lt 64 These equations assume the DIV2 bit
58. Register CHR2 General Release Specification MC68HCO05RC16 Rev 3 0 72 Carrier Modulator Transmitter CMT MOTOROLA Carrier Modulator Transmitter CMT Carrier Generator Address 0013 Bit7 6 5 4 3 2 1 Bit 0 Read 0 0 SL5 SL4 SL3 SL2 511 510 Write Reset 0 0 U U U U U U U Unaffected Figure 9 6 Carrier Generator Data Register CLR2 5 and PLO PL5 Primary Carrier High and Low Time Data Values When selected these bits contain the number of input clocks required to generate the carrier high and low time periods When operating in time mode see 9 5 1 Time Mode this register pair is always selected When operating in FSK mode see 9 5 2 FSK Mode this register pair and the secondary register pair are alternately selected under control of the modulator The primary carrier high and low time values are undefined out of reset These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results NOTE Writing to CHR1 to update 5 or to CLR1 to update PLO PL5 will also update the IRO latch When MCGEN bit 0 in the MCSR is clear the IRO latch value appears on the IRO output pin Care should be taken that bit 7 of the data to be written to 1 or CHL1 should contain the desired state of the IRO latch SH0 SH5 and 510 515 Secondary Carrier High and Low Time Data Values MC68HCO05RC16 Rev 3 0 When selected
59. SB6 SB5 SB4 SB3 SB2 5 1 580 R R R R R R R R R R R R R R R R Reserved Figure 2 2 I O Registers General Release Specification MOTOROLA Memory 29 Addr Register Bit 7 6 5 4 3 2 1 Bit 0 001A Reserved R R R R R R R R 001B Reserved R R R R R R R R 001C Reserved R R R R R R R R 001D Reserved R R R R R R R R 001E Reserved R R R R R R R R 001F Reserved R R R R R R R R R Reserved Figure 2 2 I O Registers Continued 2 3 1 ROM 2 3 2 ROM Security The user ROM consists of 15 920 bytes of ROM located from 0180 to 3FAF and 16 bytes of user vectors located from 3FFO to 3FFF The burn in ROM is located from 3FBO to 3FEF Ten of the user vectors 3FF6 3FFF are dedicated to reset and interrupt vectors The six remaining locations 3FFO 3FF1 3FF2 3FF3 3FF4 and 3FF5 are general purpose user ROM locations Security has been incorporated into the MC68HCO5RC16 to prevent external viewing of the ROM contents This feature ensures that customer developed software remains proprietary 1 No security feature is absolutely secure However Motorola s strategy is to make reading or copying the ROM difficult for unauthorized users General Release Specification MC68HCO5RC16 Rev 3 0 30 Memory MOTOROLA Memory Input Output Programming 2 3 3 RAM The user RAM consists of 352 bytes of a shared stack area The RAM star
60. ared If the COP watchdog timer is allowed to time out an internal reset is generated to reset the MCU The COP remains enabled after execution of the WAIT instruction and all associated operations apply If the STOP instruction is disabled execution of STOP instruction causes the CPU to execute a WAIT instruction In addition the COP is prohibited from being held in reset This prevents a device lock up condition This COP s objective is to make it impossible for this device to become stuck or locked up and to be sure the COP is able to rescue the part from any situation where it might entrap itself in abnormal or unintended behavior This function is a mask option 8 6 Timer During Wait Mode The CPU clock halts during wait mode but the timer remains active If interrupts are enabled a timer interrupt will cause the processor to exit wait mode The COP is always enabled while in user mode General Release Specification MC68HCO05RC16 Rev 3 0 66 Core Timer MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 9 Modulator Transmitter C MT 9 1 Contents 9 2 Introduction 92 Se eae dn ae deb de bo ane ees eens 67 ye Oe ee eee 68 9 4 _ 70 9 4 1 T PTPN 71 9 4 2 Carrier Generator Data Registers CHR1 CLR1 CHR2 and 72 Ho NANOBIO sce
61. ariable addresses within the first 511 memory locations The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode The sum is the effective address of the operand These instructions can access locations 0000 01 Indexed 8 bit offset instructions are useful for selecting the kth element in an n element table The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 01FE The k value is typically in the index register and the address of the beginning of the table is in the byte following the opcode 10 3 7 Indexed 16 Bit Offset Indexed 16 bit offset instructions are 3 byte instructions that can access data with variable addresses at any location in memory The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode The sum is the effective address of the operand The first byte after the opcode is the high byte of the 16 bit offset the second byte is the low byte of the offset Indexed 16 bit offset instructions are useful for selecting the kth element in an n element table anywhere in memory As with direct and extended addressing the Motorola assembler determines the shortest form of indexed addressing General Release Specification MC68HCO05RC16 Rev 3 0 88 Instruction Set MOTOROLA Instruction Set Instruction Types 10 3 8 Relative Relative addressing is only for branch instruction
62. ause it does not write a replacement value MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 91 Instruction Set 10 4 3 Jump Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter The unconditional jump instruction JMP and the jump to subroutine instruction JSR have no register operand Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met If the test condition is not met the branch is not performed The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations These 3 byte instructions use a combination of direct addressing and relative addressing The direct address of the byte to be tested is in the byte following the opcode The third byte is the signed offset byte The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true The bit to be tested and its condition set or clear is part of the opcode The span of branching is from 128 to 127 from the address of the next location after the branch instruction The CPU also transfers the tested bit to the carry borrow bit of the condition code register General Release Specification MC68HCO05RC16 Rev 3 0 92 Instruction Set MOTOROLA Instruction Set Instruction Types Table 10 3 Jum
63. bit 6 of the MCSR is clear When the DIV2 bit is set the carrier generator frequency will be half of what is shown in these equations The duty cycle of the carrier signal is controlled by varying the ratio of high time to low high time As the input clock period is fixed the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period Highcount Duty Cycle Fighcount Lowcount MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 71 Modulator Transmitter 9 4 2 Camier Generator Data Registers CHR1 CLR1 CHR2 and CLR2 The carrier generator contains two 7 bit data registers primary high time CHR1 primary low time CLR1 and two 6 bit data registers secondary high time CHR2 and secondary low time CLR2 Bit 7 of CHR1 and CHR2 is used to read and write the IRO latch Address 0010 Bit7 6 5 4 3 2 1 Bit 0 Read IROLN 0 PH5 PHA PH3 PH2 PHI PHO Write Reset 0 0 U U U U U U U Unaffected Figure 9 3 Carrier Generator Data Register CHR1 Address 0011 Bit 7 6 5 4 3 2 1 Bit 0 Read IROLP 0 PL5 PL4 PL3 PL2 PL1 PLO Write Reset 0 0 U U U U U U U Unaffected Figure 9 4 Carrier Generator Data Register CLR1 Address 0012 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 SH5 SH4 SH3 SH2 SH1 SHO Write Reset 0 0 U U U U U U U Unaffected Figure 9 5 Carrier Generator Data
64. cal Characteristics 5 0 Vdc 11 7 DC Electrical Characteristics 2 2 Vdc 11 8 Control Timing 5 0 and 2 2 Vdc 11 2 Introduction This section contains the electrical and timing specifications MC68HCO05RC16 Rev 3 0 General Release Specification MOTOROLA Electrical Specifications 103 Hlec trical Specifications 11 3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it The MCU contains circuitry to protect the inputs against damage from high static voltages however do not apply voltages higher than those shown in the table below Keep Vn and Voy within the range Vss Vin Vpp Connect unused inputs to the appropriate voltage level either Vss or Rating Symbol Value Unit Supply Voltage Vpp 0 3 to 7 0 V mu Vss 0 3 Burn In Mode IRQ Pin Only to V 2x Vpp 0 3 Current Drain Per Pin Excluding Vpp and Vss 25 mA Operating Junction Temperature Ty 150 C Storage Temperature Range 65 to 4150 C NOTE This device is not guaranteed to operate properly at the maximum ratings Refer to 11 6 DC Electrical Characteristics 5 0 Vdc and 11 7 DC Electrical Characteristics 2 2 Vdc for guaranteed operating conditions General Release Specification MC68HCO05RC16 Rev 3 0 104 Electrical Specifications MOTOROLA 11 4 Operating Range Electrical Specifications
65. cts should be tied to an appropriate logic level either Vpp or Vss Figure 1 4 44 Pin PLCC Pinout General Release Specification MC68HCO05RC16 Rev 3 0 22 General Description MOTOROLA General Description Signal Description 1 5 1 Vpp and Vss Power is supplied to the microcontroller s digital circuits using these two pins Vpp is the positive supply and Vss is ground 1 5 2 IRQ Maskable Interrupt Request In addition to suppling the EPROM with the required programming voltage this pin has a mask option as specified by the user that provides one of two different choices of interrupt triggering sensitivity The options are 1 Negative edge sensitive triggering only 2 Both negative edge sensitive and level sensitive triggering The MCU completes the current instruction before it responds to the interrupt request When IRQ goes low for at least one ti jj see 11 8 Control Timing 5 0 Vdc and 2 2 Vdc a logic 1 is latched internally to signify that an interrupt has been requested When the MCU completes its current instruction the interrupt latch is tested If the interrupt latch contains a logic 1 and the interrupt mask bit 1 bit in the condition code register is clear the MCU then begins the interrupt sequence If the option is selected to include level sensitive triggering the IRQ input requires an external resistor to Vpp for wired OR operation The IRQ pin contains an internal Schmitt trigger as part of
66. d ViN 0 7 Vpp 300 Capacitance Ports as Input or Output 12 pF RESET LPRST IRQ 8 NOTES 1 Vpp 5 0 Vdc 10 Vss 0 T4 0 to 70 C unless otherwise noted Typical values at midpoint of voltage range 25 only represent average measurements Wait Ipp only core timer active Bom Stop Ipp is measured with OSC1 Vgg Wait Ipp is affected linearly by the OSC2 capacitance coco om Run Operating Ipp wait Ipp Measured using external square wave clock source fos 4 2 MHz all inputs 0 2 V from rail dc loads less than 50 pF on all outputs C 20 pF on OSC2 Wait Stop Ipp Port A and port C configured as inputs port B configured as outputs 0 2 V Vpp 0 2 V Pullups are designed to be capable of pulling to within 1 us for a 100 pF 4 kQ load General Release Specification MC68HCO05RC16 Rev 3 0 106 Electrical Specifications MOTOROLA Electrical Specifications DC Electrical Characteristics 2 2 Vdc 11 7 DC Electrical Characteristic s 2 2 Vdc Characteristic Symbol Min Typ Max Unit Output Voltage 10 0 LA VoL 0 1 V 10 0 uA Vpp 0 1 Output High Voltage l 0 6 mA Port A Port Port C 1 7 V Vbo 0 3 Vbo 0 1 V l oan 9 0 mA IRO on Vpp 0 3 Vbo 0 1 l oap 1 2 mA Port C Bit 0 Vbo 0 3 Vbo 0 1 Output
67. d Writing a zero has no effect on the CTOF bit This bit always reads as zero RTFC Real Time Interrupt Flag Clear When a one is written to this bit RTIF is cleared Writing a zero has no effect on the RTIF bit This bit always reads as zero RT1 RTO Real Time Interrupt Rate Select These two bits select one of four taps from the real time interrupt circuit Refer to Table 8 1 Reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary Care should be taken when altering RTO and RT1 if the timeout period is imminent or uncertain If the selected tap is modified during a cycle in which the counter is switching an RTIF could be missed or an additional one could be generated To avoid problems the COP should be cleared before changing RTI taps Table 8 1 RTI and COP Rates at 4 096 MHz Oscillator 2 046 MHz Bus RTURTO MTM Bus 2 ms 212 00 215_212 14 ms 4 ms 213 E 01 216_213 28 ms 8 ms 214 E 10 56 ms 16 ms 215 11 218 215 112 ms General Release Specification MC68HCO05RC16 Rev 3 0 64 Core Timer MOTOROLA Core Timer Core Timer Counter Register 8 4 Core Timer Counter Register The timer counter register is a read only register that contains the current value of the 8 bit ripple counter at the beginning of the timer chain This counter is clocked by the CPU clock E 4 and can be used fo
68. d when the interrupt took place Figure 4 1 shows the sequence of events that occurs during interrupt processing 4 4 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt however it is acted upon in a similar manner as shown in Figure 4 1 A low level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations 3FFE and 3FFF The I bit in the condition code register is also set The MCU is configured to a known state during this type of reset 4 5 Software Interupt SM The SWl is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the bit in the If the bit is zero interrupts enabled the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched The interrupt service routine address is specified by the contents of memory locations 3FFC and 3FFD MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Interrupts 39 CLEAR IRQ REQUEST LATCH gt CORE TI gt INTERR N gt lt STACK PC X A CCR FETCH NEXT Y INSTRUCTION SET I BIT IN CC REGISTER v LOAD PC FROM APPROPRIATE VECTOR RTI INSTRUCTION
69. duces 10 MCUS called RVUs and sends the RVUs to the customer RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer s user ROM pattern was properly implemented The 10 RVUs are free of charge with the minimum order quantity These units are not to be used for qualification or production RVUs are not guaranteed by Motorola Quality Assurance 13 7 MC Order Numbers Table 13 1 provides information in determing order numbers Table 13 1 MC Order Numbers Operating Package Type Temperature MC Order Number Range 28 Pin Plastic Dual In Line 0 to 70 MC68HCO5RC8P Package DIP MC68HCO5RC16P 28 Pin Small Outline Integrated Circuit 0 to 70 MC68HCO5RC8DW Package SOIC MC68HCO5RC16DW 44 Pin Plastic Leaded Chip 0 to 70 C MC68HCO5RC8FN Carrier PLCC MC68HCO5RC16FN General Release Specification MC68HCO05RC16 Rev 3 0 118 Ordering Information MOTOROLA General Release Spec ification MC 68HCO5RC 16 Appendix A MC68HCOSRC8 A 1 Contents Introduction 141 P MOMON ED 141 A 2 Introduction Appendix A introduces the MC68HCO5RC8 The technical data applying to the MC68HCO05RC16 applies to the MC68HCO5RC8 with the exceptions given in this appendix A 3 Memory Map Both the MC68HCO5RC8 and the MC68HC
70. during program execution MC68HCO05RC16 Rev 3 0 Table 10 5 Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and Enable IRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable Interrupts WAIT General Release Specification MOTOROLA Instruction Set 95 Instruction Set 10 5 Instruction Set Summary Table 10 6 Instruction Set Summary General Release Specification Effect on o lot EE o 2 Operation Description CCR 56 98 5 oz 2 HiIilNZzic 29 5 amp o ADC opr IMM 9 ii 2 ADC opr DIR B9 dd 3 ADC opr EXT C9 hhll 4 ADC opr X Add with Carry A lt A M C 1131414 2 D9 lee ff 5 ADC opr X 9 ff 4 ADC IX F9 3 ADD opr AB ii 2 ADD opr DIR BB dd 3 ADD opr EXT CB hhll 4 ADD opr X Add without Carry A lt M tI pBleeff 5 ADD opr X 1 1 EB ff 4 ADD X IX FB 3 AND A4 2 AND opr DIR 4 dd 3 AND opr 1 EXT C4 hhll 4 AND opr X Logical AND A lt
71. e modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches zero space Using timing data for carrier burst and interpulse gap length calculated by the CPU FSK mode can automatically generate a phase coherent dual frequency FSK signal with programmable burst and interburst gaps MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 77 Modulator Transmitter The mark and space time equations for FSK mode are MBUFF 1 SBUFF Secs Where fg is the frequency output from the carrier generator setting the DIV2 bit in the MCSR will double mark and space times 9 5 3 Extended Space Operation In either time or FSK mode the space period can be made longer than the maximum possible value of SBUFF Setting the EXSPC bit in the MCSR will force the modulator to treat the next modulation period beginning with the next load of MBUFF SBUFF as a space period equal in length to the mark and space counts combined Subsequent modulation periods will consist entirely of these extended space periods with no mark periods Clearing EXSPC will return the modulator to standard operation at the beginning of the next modulation period To calculate the length of an extended space in time mode use the equation SBUFF MBUFF2 1 SBUFF MBUFF 1 SBUFF x 8 lexspace
72. e space period register SREG is loaded with the possibly new contents of the space period buffer SBUFF This flag is cleared by a read of the MCSR followed by an access of MDR2 or MDR3 The EOC flag is cleared by reset 1 End of modulator cycle counter SBUFF has occurred 0 Current modulation cycle in progress DIV2 Divide by two prescaler The divide by two prescaler causes the CMT to be clocked at the bus rate when enabled 2 x the bus rate when disabled fosc This bit is not double buffered and so should not be set during a transmission 1 Divide by two prescaler enabled 0 Divide by two prescaler disabled General Release Specification MC68HCO05RC16 Rev 3 0 80 Carrier Modulator Transmitter CMT MOTOROLA Carrier Modulator Transmitter CMT Modulator EIMSK External Interrupt Mask The external interrupt mask bit is used to mask IRQ and keyscan interrupts This bit is cleared by reset 1 IRQ and keyscan interrupts masked 0 IRQ and keyscan interrupts enabled EXSPC Extended Space Enable For a description of the extended space enable bit see 9 5 3 Extended Space Operation This bit is cleared by reset 1 Extended space enabled 0 Extended space disabled BASE Baseband Enable When set the BASE bit disables the carrier generator and forces the carrier output high for generation of baseband protocols When BASE is clear the carrier generator is enabled and the carrier output
73. ent to a WAIT instruction IRQ IRQ sensitivity When the IRQ option is selected IRQ 1 edge and level sensitive IRQ is enabled When the IRQ option is deselected IRQ 0 edge only sensitive IRQ is enabled NOTE The port B keyscan interrupt sensitivity will match that of the IRQ sensitivity See 4 7 External Interrupt IRQ Port B Keyscan for more information General Release Specification MC68HCO05RC16 Rev 3 0 20 General Description MOTOROLA General Description Signal Description 1 5 Signal Description The MC68HCO05RC10 is available 1 28 pin dual in line package DIP see Figure 1 2 2 28 pin small outline integrated circuit SOIC package see Figure 1 3 3 44 pin plastic leaded chip carrier PLCC package see Figure 1 4 The signals are described in the following subsections A W rn Figure 1 2 28 Pin DIP Pinout MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA General Description 21 General Description PBO 10 05 1 1 2 05 2 PB2 3 Voy PB3 4 RG PB4 5 RESET PB5 6 IRO PB6 7 Vss PB7 8 LPRST PAO 9 PC3 PAL 10 PC2 PA2 11 1 12 PCO PAL 13 7 5 14 PAG NC PB4 PB5 PB6 PB7 NC PC6 PC7 PAO PAL NC NOTE NC No Connect All no conne
74. f 6 LSL X IX 78 5 LSR opr DIR 34 99 5 LSRA INH 44 3 LSRX Logical Shift Right 07x INH 54 3 LSR oprX b7 bo x1 64 6 LSR X IX 74 5 MUL Unsigned Multiply lt X x A 0 INH 42 11 NEG opr M lt M 00 M DIR 30 99 5 NEGA lt A 00 A INH 40 3 NEGX Negate Byte Two s Complement X lt X 00 X 50 3 NEG M lt 00 M I1 leol 6 NEG X M lt M 00 M IX 70 5 NOP No Operation INH 9D 2 ORA opr IMM AA ii 2 ORA opr DIR dd 3 ORA opr EXT CA hhll 4 ORA opr X Logical OR Accumulator with Memory lt v x2 DA lee ff 5 ORA opr X IX1 EA ff 4 ORA X IX FA 3 ROL opr DIR 39 dd 5 ROLA INH 49 3 ROLX Rotate Byte Left through Carry Bit te j t t INH 59 3 ROL opr X b7 1 1 69 ff 6 ROL X IX 79 5 MC68HCO05RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 99 Instruction Set Table 10 6 Instruction Set Summary Continued Effect on o DIS 9 ene Operation Description CCR 5885 oz 2 DIR 36 44 5 RORA INH 46 3 RORX Rotate Byte Right thr
75. f the device unless otherwise specified RO TO IRQ 1 ps 4 LOGIC D LATCH ELECT RESET Ir i gt gt gt R CLOCKED OSC _ gt DATA gt COP WATCHDOG ADDRESS COPR t PRST o eee S D TO OTHER POWER ON RESET Voo gt POR LATCH us PERIPHERALS PH2 gt ILLEGAL ADDRESS ADDRESS Figure 5 1 Reset Block Diagram General Release Specification MC68HCO05RC16 Rev 3 0 46 Resets MOTOROLA VIOYOLOW sjesey 47 0 E ASH 910HS800H899IN aseajay e1euec osci A poppe are Y re HeH H H H Hem HH HOY 9 Vey Ve e Festa Rus ey RR F T NOTES 1 RON Internal timing signal and bus information are not available externally OSC 1 line is not meant to represent frequency It is only used to represent time The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence Vpp must fall to a level lower than Vpop to be recognized as a power on reset The LPRST pin resets the CPU like RESET However 4064 POR cycles are executed first before the reset vector address appears on the internal address bus See 5 4 Low Power External Reset LPRST Figure 5 2 Reset and POR Timing Diagra
76. g out of reset Address 08 Read CTOF RTIF 0 0 TOFE RTIE RTO Write TOFC RTFC Reset 0 0 0 0 0 0 1 1 Unimplemented Figure 8 2 Core Timer Control and Status Register CTCSR CTOF Core Timer Overflow CTOF is a read only status bit set when the 8 bit ripple counter rolls over from FF to 00 Clearing the CTOF is done by writing a one to TOFC Writing to this bit has no effect Reset clears CTOF RTIF Real Time Interrupt Flag The real time interrupt circuit consists of a 3 stage divider and a one of four selector The clock frequency that drives the RTI circuit is 212 or E 4096 with three additional divider stages giving a maximum interrupt period of 16 milliseconds at a bus rate of 2 024 MHz RTIF is a clearable read only status bit and is set when the output of the chosen one of four selection stage goes active Clearing the RTIF is done by writing a one to RTFC Writing has no effect on this bit Reset clears RTIF TOFE Timer Overflow Enable When this bit is set a CPU interrupt request is generated when the CTOF bit is set Reset clears this bit RTIE Real Time Interrupt Enable When this bit is set a CPU interrupt request is generated when the RTIF bit is set Reset clears this bit MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Core Timer 63 TOFC Timer Overflow Flag Clear When a one is written to this bit CTOF is cleare
77. h External Interrupt IRQ Port Exteel Interrupt IMNO ra nen Carrier Modulator Transmitter Interrupt CMT Dore Timer MUG rn csc dado ER de Reo ceeded ewes The MCU can be interrupted four different ways 59 dg MC68HCO05RC16 Rev 3 0 Nonmaskable software interrupt instruction SWI External asynchronous interrupt IRQ port B keyscan Internal carrier modulator transmitter interrupt Internal core timer interrupt General Release Specification MOTOROLA Interrupts 37 Interrupts 4 3 CPU Intenupt Processing Interrupts cause the processor to save register contents on the stack and to the interrupt mask I bit to prevent additional interrupts Unlike reset hardware interrupts do not cause the current instruction execution to be halted but are considered pending until the current instruction is complete If interrupts are not masked I bit in the CCR is clear and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing Otherwise the next instruction is fetched and executed If an interrupt occurs the processor completes the current instruction stacks the current CPU register state sets the bit to inhibit further interrupts and finally checks the pending hardware interrupts If more than one interrupt is pending after the stacking operation the interrupt with the highest vector locat
78. held high continuously to allow for the generation of baseband protocols See 9 4 Carrier Generator General Release Specification MC68HCO05RC16 Rev 3 0 68 Carrier Modulator Transmitter CMT MOTOROLA Carrier Modulator Transmitter CMT Overview PRIMARY SECONDARY SELECT MODE MODULATOR OUT CARRIER CARRIER OUT GENERATOR IRO TRANSMITTER gt OUTPUT PIN MODULATOR MODULATOR CARRIER ENABLE fosc fosc 2 CPU INTERFACE DB AB EOC INTERRUPT Figure 9 1 Carrier Modulator Transmitter Module Block Diagram The modulator provides a simple method to control protocol timing The modulator has a resolution of 4 us with a 2 MHz oscillator It can count system clocks to provide real time control or it can count carrier clocks for self clocked protocols It can either gate the carrier onto the modulator output TIME control the logic level of the modulator output baseband or directly route the carrier to the modulator output while providing a signal to switch the carrier generator between high low time register buffers FSK See 9 5 Modulator The transmitter output block controls the state of the infrared out pin IRO The modulator output is gated on to the IRO pin when the modulator carrier generator is enabled Otherwise the IRO pin is controlled by the state of the IRO latch which is directly accessible to the CPU by means of bit 7 of the
79. ight addressing modes The instructions include all those of the M146805 CMOS Family plus one more the unsigned multiply MUL instruction The MUL instruction allows unsigned multiplication of the contents of the accumulator A and the index register X The high order product is stored in the index register and the low order product is stored in the accumulator 10 3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction The eight addressing modes are Inherent e Immediate Direct e Extended Indexed no offset Indexed 8 bit offset Indexed 16 bit offset Relative General Release Specification MC68HCO05RC16 Rev 3 0 86 Instruction Set MOTOROLA 10 3 1 Inherent 10 3 2 Immediate 10 3 3 Direct 10 3 4 Extended Instruction Set Addressing Modes Inherent instructions are those that have no operand such as return from interrupt RTI and stop STOP Some of the inherent instructions act on data in the CPU registers such as set carry flag SEC and increment accumulator INCA Inherent instructions require no operand address and are one byte long Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register Immediate instructions require no operand address and are two bytes
80. ion shown in Table 4 1 will be serviced first The SWI is executed the same as any other instruction regardless of the I bit state When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations 3FF6 3FFF as defined in Table 4 1 Table 4 1 Vector Address for Interrupts and Reset Register Flag Name Interrupt Interrupt Vector Address N A N A Reset RESET 3FFE 3FFF N A N A Software Interrupt SWI 3FFC 3FFD N A N A External Interrupts IRQ 3FFA 3FFB MCSR poe O CMT 3FF8 3FF9 Interrupt Real Time Interrupt CTOF CORE CTCSR Core Timer TIMER 3FF6 3FF7 Overflow External interrupts include IRQ and port B keyscan sources General Release Specification MC68HCO05RC16 Rev 3 0 38 Interrupts MOTOROLA Interrupts Reset Interrupt Sequence The M68HC05 CPU does not support interruptible instructions The maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead Latency Longest instruction execution time 10 x to seconds An RTI instruction is used to signify when the interrupt software service routine is completed The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be execute
81. le 5 1 Table 5 1 COP Watchdog Timer Recommendations IF the Following Conditions Exist Wait Time THEN the COP Watchdog Timer Should Be as Follows Wait Time Less than COP Time Out Enable or Disable COP by Mask Option Wait Time More than COP Time Out Disable COP by Mask Option Any Length Wait Time Disable COP by Mask Option MC68HCO5RC16 Rev 3 0 General Release Specification 50 Resets MOTOROLA Resets Internal Resets 5 5 2 5 COP Register The COP register is shared with the LSB of an unimplemented user interrupt vector as shown in Figure 5 3 Reading this location returns whatever user data has been programmed at this location Writing a zero to the COPR bit in this location clears the COP watchdog timer Address 3FF0 7 6 5 4 3 2 1 Read X X X X X X X X Write COPR Reset 0 Unimplemented Figure 5 3 COP Watchdog Timer Location 5 5 3 Illegal Address An illegal address reset is generated when the CPU attempts to fetch an instruction from I O address space 0000 to 001F MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Resets 51 Resets General Release Specification MC68HCO05RC16 Rev 3 0 52 Resets MOTOROLA General Release Spec ification MC 68HCO5RC 16 6 1 Contents 6 2 Introduction 6 3 Stop Mode NOTE Section 6 Low Power Modes
82. les or disables the pullup interrupt on port B bit 5 1 Enables pullup interrupt 0 Disables pullup interrupt PB4PU Port B4 Pullup Interrupt This option enables or disables the pullup interrupt on port B bit 4 1 Enables pullup interrupt 0 Disables pullup interrupt PB3PU Port B3 Pullup Interrupt This option enables or disables the pullup interrupt on port B bit 3 1 Enables pullup interrupt 0 Disables pullup interrupt MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA General Description 19 General Description PB2PU Port B2 Pullup Interrupt This option enables or disables the pullup interrupt on port B bit 2 1 Enables pullup interrupt 0 Disables pullup interrupt PB1PU Port B1 Pullup Interrupt This option enables or disables the pullup interrupt on port B bit 1 1 Enables pullup interrupt 0 Disables pullup interrupt PBOPU Port BO Pullup Interrupt This option enables or disables the pullup interrupt on port B bit 0 1 Enables pullup interrupt 0 Disables pullup interrupt COPEN COP Enable When the COP option is selected COPEN 1 the COP watchdog timer is enabled When the COP option is deselected COPEN 0 the COP watchdog timer is disabled STOPEN STOP Instruction Enable When the STOP option is selected STOPEN 1 the STOP instruction is enabled When the STOP option is deselected STOPEN 0 the STOP instruction is equival
83. long The opcode is the first byte and the immediate data value is the second byte Direct instructions can access any of the first 256 memory locations with two bytes The first byte is the opcode and the second is the low byte of the operand address In direct addressing the CPU automatically uses 00 as the high byte of the operand address Extended instructions use three bytes and can access any address in memory The first byte is the opcode the second and third bytes are the high and low bytes of the operand address When using the Motorola assembler the programmer does not need to specify whether an instruction is direct or extended The assembler automatically selects the shortest form of the instruction MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 87 Instruction Set 10 3 5 Indexed No Offset Indexed instructions with no offset are 1 byte instructions that can access data with variable addresses within the first 256 memory locations The index register contains the low byte of the effective address of the operand The CPU automatically uses 00 as the high byte so these instructions can address locations 0000 00FF Indexed no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I O location 10 3 6 Indexed 8 Bit Offset Indexed 8 bit offset instructions are 2 byte instructions that can access data with v
84. m 19599 1 sjesey Resets 5 4 Low Power Extemal Reset LPRST The LPRST pin is one of the two external sources of a reset This external reset occurs whenever the LPRST pin is pulled below the lower threshold and remains in reset until the LPRST pin rises This active low input will in addition to generating the RST signal and resetting the CPU and peripherals halt all internal processor clocks The MCU will remain in this low power reset condition as long as a logic 0 remains on LPRST When a logic 1 is applied to LPRST processor clocks will be re enabled with the MCU remaining in reset until the 4064 internal processor clock cycle oscillator stabilization delay is completed If any other reset function is active at the end of this 4064 cycle delay the RST signal remains in the reset condition until the other reset condition s end 5 5 Intemal Resets The three internally generated resets are the initial power on reset function the COP watchdog timer reset and the illegal address detector Termination of the external reset input external LPRST input or the internal COP watchdog timer are the only reset sources that can alter the operating mode of the MCU The other internal resets do not have any effect on the mode of operation when their reset state ends 5 5 1 Power On Reset POR The internal POR is generated on power up to allow the clock oscillator to stabilize The POR is strictly for
85. modulator and transmitter output blocks The block diagram is shown in Figure 9 1 The carrier generator has a resolution of 500 ns with a 2 MHz oscillator The user may independently define the high and low times of the carrier signal to determine both period and duty cycle The carrier generator can generate signals with periods between 1 us 1 MHz and 64 us 15 6 kHz in steps of 500 ns The possible duty cycle options will depend upon the number of counts required to complete the carrier period For example a 400 kHz signal has a period of 2 5 us and will therefore require 5 x 500 ns counts to generate These counts may be split between high and low times so the duty cycles available will be 2096 one high four low 4096 two high three low 6096 three high two low and 80 four high one low For lower frequency signals with larger periods higher resolution as a percentage of the total period duty cycles are possible The carrier generator may select between two sets of high and low times When operating in normal mode subsequently referred to as time mode just one set will be used When operating in FSK frequency shift key mode the generator will toggle between the two sets when instructed to do so by the modulator allowing the user to dynamically switch between two carrier frequencies without CPU intervention When the BASE bit in the modulator control and status register MCSR is set the carrier output to the modulator is
86. n 8 bit port Since pins 4 are unbonded software should include the code to set their respective data direction register locations to outputs to avoid floating inputs 7 6 Input Output Programming Port pins may be programmed as inputs or outputs under software control The direction of the pins is determined by the state of the corresponding bit in the port data direction register DDR Each I O port has an associated DDR Any port pin is configured as an output if its corresponding DDR bit is set to a logic 1 A pin is configured as an input if its corresponding DDR bit is cleared to a logic O At power on or reset all DDRs are cleared which configures all pins as inputs The data direction registers are capable of being written to or read by the processor During the programmed output state a read of the data register actually reads the value of the output data latch and not the I O pin Table 7 1 I O Pin Functions Access DDR Pin Functions The I O pin is in input mode Data is written into the output Write 0 data latch Data is written into the output data latch and output to the Write 1 pin Read 0 The state of the I O pin is read Read 1 The I O pin is in an output mode The output data latch is read MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Parallel Input Output I O 59 Parallel Input Output I O
87. o indicate the results of the instruction just executed and the fifth bit indicates whether interrupts are masked These bits can be tested individually by a program and specific actions can be taken as a result of their state Each bit is explained in the following paragraphs H Half Carry This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4 Interrupt When this bit is set timer and external interrupts are masked disabled If an interrupt occurs while this bit is set the interrupt is latched and processed as soon as the interrupt bit is cleared N Negative When set this bit indicates that the result of the last arithmetic logical or data manipulation was negative Z Zero When set this bit indicates that the result of the last arithmetic logical or data manipulation was zero C Carry Borrow When set this bit indicates that a carry or borrow out of the arithmetic logical unit ALU occurred during the last arithmetic operation This bit is also affected during bit test and branch instructions and during shifts and rotates MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Central Processor Unit 35 Cental Processor Unit 3 6 Stack Pointer The stack pointer SP contains the address of the next free location on the stack During an MCU reset or the reset stack pointer RSP instruction the stack pointer is set
88. ode only by an external interrupt LPRST or RESET Refer to Figure 6 1 NOTE Ifan external interrupt is pending when stop mode is entered then stop mode will be exited immediately 6 5 Wait Mode The WAIT instruction places the MCU in a low power consumption mode but wait mode consumes more power than stop mode All CPU action is suspended but the core timer the oscillator and any enabled module remain active Any interrupt or reset will cause the MCU to exit wait mode The user must shut off subsystems to reduce power General Release Specification MC68HCO5RC16 Rev 3 0 54 Low Power Modes MOTOROLA Low Power Modes Low Power Reset consumption Wait current specifications assume CPU operation only and do not include current consumption by any other subsystems During wait mode the bit in the CCR is cleared to enable interrupts All other registers memory and input output lines remain in their previous states The timer may be enabled to allow a periodic exit from wait mode 6 6 Low Power Reset Low power reset mode is entered when a logic 0 is detected on the LPRST pin When in this mode as long as LPRST is held low the MCU is held in reset and all internal clocks are halted Applying a logic 1 to LPRST will cause the part to exit low power reset mode and begin counting out the 4064 cycle oscillator stabilization period Once this time has elapsed the MCU will begin operation from the reset vectors 3FFE 3FF
89. ola s S record format S1 and S9 records a character based object file format generated by M6805 cross assemblers and linkers 1 Macintosh is a registered trademark of Apple Computer Inc 2 MS DOS is a registered trademark of Microsoft Corporation 3 PC DOS is a trademark of International Business Machines Corporation General Release Specification MC68HCO05RC16 Rev 3 0 116 Ordering Information MOTOROLA Ordering Information ROM Program Verification NOTE Begin the application program at the first user ROM location Program addresses must correspond exactly to the available on chip user ROM addresses as shown in the memory map Write 00 in all nonuser ROM locations or leave all nonuser ROM locations blank Refer to the current MCU ordering form for additional requirements Motorola may request pattern re submission if nonuser areas contain any nonzero code If the memory map has two user ROM areas with the same address then write the two areas in separate files on the diskette Label the diskette with both file names In addition to the object code a file containing the source code can be included Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code Label the diskette with the file name of the source code 13 5 ROM Program Verffication The primary use for the on chip ROM is to hold the customer s application program The c
90. ough Carry Bit Et mic iit 56 3 ROR opr X b7 50 1 1 66 ff 6 ROR X IX 76 5 RSP Reset Stack Pointer SP 00FF INH 9 2 SP lt SP 1 Pull CCR SP lt SP 1 Pull A RTI Return from Interrupt SP lt SP 1 Pull X 212122121 INH 80 9 SP lt SP 1 Pull PCH SP lt SP 1 Pull PCL SP lt SP 1 Pull PCH RTS Return from Subroutine SP SP 1 Pull PCL INH 81 6 SBC opr IMM 2 ii 2 SBC opr DIR B2 dd 3 SBC opr Subtract Memory Byte and Carry Bit from EXT C2 hhll 4 SBC opr X Accumulator m kaka 2 02 5 SBC opr X E2 ff 4 SBC X IX F2 3 SEC Set Carry Bit 1 1 99 2 SEI Set Interrupt Mask 16 1 1 INH 9 2 STA opr DIR B7 dd 4 STA opr EXT C7 hhll 5 STA opr X Store Accumulator in Memory M lt A 1 1 2 07 6 STA opr X IX1 E7 ff 5 STA X IX F7 4 STOP Stop Oscillator and Enable IRQ Pin 0 INH 8E 2 STX opr DIR dd 4 STX opr EXT CF hhll 5 STX opr X Store Index Register In Memory M lt X ti xe DF eeff 6 STX opr X IX1 EF ff 5 STX X IX FF 4 SUB opr IMM ii 2 SUB opr DIR 0 dd 3 SUB opr n EXT CO hhll 4 SUB oprX Subtract Memory Byte from Accumulator lt A M 1 1111 2 poleeff 5 SUB I1 ff 4 SUB X IX FO 3 PC lt 1 Push PCL SP lt SP
91. p and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear Branch if Carry Bit Set BCC Branch if Equal Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR MC68HCO05RC16 Rev 3 0 General Release Specification Instruction Set 93 Instruction Set 10 4 4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory which includes I O registers and on chip RAM locations The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations Table 10 4 Bit Manipulation Instructions Instruction Mnemonic Bit Clear BCLR Branch if Bit Clear Branch if Bit Set Bit Set General Release Specification MC68HCO05RC16 Rev 3 0 94 Instruction Set MOTOROLA 10 4 5 Control Instructions Instruction Set Instruction Types These instructions act on CPU registers and control CPU operation
92. plant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a Situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer How to reach us USA EUROPE Locations Not Listed Motorola Literature Distribution Box 20912 Phoenix Arizona 85036 1 800 441 2447 or 602 303 5454 RMFAX0 email sps mot com TOUCHTONE 602 244 6609 INTERNET http Design NET com JAPAN Nippon Motorola Ltd Tatsumi SPD JLDC 6F Seibu Butsuryu Center 3 14 2 Tatsumi Koto Ku Tokyo 135 Japan 03 81 3521 8315 ASIA PACIFIC Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 M MOTOROLA HCO5RC16GRS D
93. r various functions including a software input capture Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16 bit or more counter Address 09 Read D7 D6 D5 D4 D3 D2 01 00 Write Reset 0 0 0 0 0 0 1 1 Unimplemented Figure 8 3 Core Timer Counter Register CTCR The power on cycle clears the entire counter chain and begins clocking the counter After 4064 cycles the power on reset circuit is released which again clears the counter chain and allows the device to come out of reset At this point if RESET is not asserted the timer starts counting up from zero and normal device operation begins When RESET is asserted any time during operation other than POR and low power reset the counter chain is cleared MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Core Timer 65 8 5 Computer Operating Properly COP Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight The minimum COP reset rates are listed in Table 8 1 If the COP circuit times out an internal reset is generated and the normal reset vector is fetched Preventing a COP timeout or clearing the COP is accomplished by writing a zero to bit 0 of address 3FFO When the COP is cleared only the final divide by eight stage output of the RTI is cle
94. s If the branch condition is true the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter If the branch condition is not true the CPU goes to the next instruction The offset is a signed two s complement byte that gives a branching range of 128 to 127 bytes from the address of the next location after the branch instruction When using the Motorola assembler the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch 10 4 Instruction Types The MCU instructions fall into the following five categories e Register Memory Instructions e Read Modify Write Instructions e Jump Branch Instructions Bit Manipulation Instructions e Control Instructions MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Instruction Set 89 Instruction Set 10 4 1 Register Memory Instructions These instructions operate on CPU registers and memory locations Most of them use two operands One operand is in either the accumulator or the index register The CPU finds the other operand in memory General Release Specification Table 10 1 Register Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test
95. t M 1 IX 7 5 JMP opr DIR BC dd 2 JMP opr EXT CcCc hhll 3 JMP opr X Unconditional Jump PC Jump Address 1 2 DC 4 JMP opr X IX1 EC ff 3 JMP X IX FC 2 General Release Specification MC68HC05RC16 Rev 3 0 98 Instruction Set MOTOROLA Instruction Set Instruction Set Summary Table 10 6 Instruction Set Summary Continued Effect on o o0 9 c 9 Operation Description CCR 5885 oz 2 PC lt PC n n 1 2 or 3 DIR JSR EXT CcD hhll 6 Push PCL SP lt SP 1 JSR opr X Jump to Subroutine 1 2 DDjeeff 7 Push PCH SP lt SP 1 lt Effective Address 1 ED ff 6 JSR X IX FD 5 LDA opr IMM 6 ii 2 LDA opr DIR 6 dd 3 LDA opr P EXT Cce hhll 4 LDA oprX Load Accumulator with Memory Byte lt 1 11 1 2 D6 lee ff 5 LDA opr X IX1 E6 ff 4 LDA X IX F6 3 LDX opr IMM ii 2 LDX opr DIR BE dd 3 LDX opr be EXT CcEhhll 4 LDX opr X Load Index Register with Memory Byte X lt t t X2 pEleeft 5 LDX opr X IX1 EE ff 4 LDX IX FE 3 LSL opr DIR 38 99 5 LSLA INH 48 3 LSLX Logical Shift Left Same as ASL 0 11 INH 58 3 LSL opr X b7 50 I1 68 f
96. toggles at the frequency determined by values stored in the carrier data registers See 9 5 1 Time Mode This bit is cleared by reset This bit is not double buffered and should not be written to during a transmission 1 Baseband enabled 0 Baseband disabled MODE Mode Select For a description of CMT operation in time mode see 9 5 1 Time Mode For a description of CMT operation in FSK mode see 9 5 2 FSK Mode This bit is cleared by reset This bit is not double buffered and should not be written to during a transmission 1 CMT operates in FSK mode 0 CMT operates in time mode IE Interrupt Enable A CPU interrupt will be requested when EOC is set if IE was previously set If IE is clear EOC will not request a CPU interrupt 1 CPU interrupt enabled 0 CPU interrupt disabled MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Carrier Modulator Transmitter CMT 81 Camer Modulator Transmitter MCGEN Modulator and Carrier Generator Enable Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks Once enabled the carrier generator and modulator will function continuously When MCGEN is cleared the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled to save power and the modulator output is forced low The user should initialize all data and control registers before enabling the system to prevent
97. trol and status register MCSR This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations 3FF8 and 3FF9 General Release Specification MC68HCO05RC16 Rev 3 0 42 Interrupts MOTOROLA Interrupts Core Timer Interrupt 4 10 Core Timer Intemupt This timer can create two types of interrupts A timer overflow interrupt occurs whenever the 8 bit timer rolls over from FF to 00 and the enable bit TOFE is set A real time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set Either of these interrupts vectors to the same interrupt service routine located at the address specified by the contents of memory locations 3FF6 and 3FF7 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Interrupts 43 Interrupts General Release Specification MC68HCO5RC16 Rev 3 0 44 Interrupts MOTOROLA General Release Spec ification MC 68HCO5RC 16 5 1 Contents 5 2 Introduction Section 5 Resets Se ITI 45 53 External Reset RESET d aor ge ch xs 46 5 4 Low Power External Reset LPRST 48 55 femal POENIS d ode toed 39 eee eRe Qo ded Ra Ow 48 5 5 1 Power On Reset POR Leda eia 48 2220 Computer Operating Properly Reset COPR 49 5 5 2 1 de COM di 49 5 5 2 2 During VENE OCS
98. ts at address 0020 and ends at address 017F The stack begins at address 00FF The stack pointer can access 64 bytes of RAM in the range 00FF to 00CO NOTE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call 2 4 Input Output Programming In user mode 20 lines 28 pin PDIP or 28 pin SOIC or 24 lines 44 lead PLCC are arranged as three 8 bit I O ports These ports are programmable as either inputs or outputs under software control of the data direction registers For detailed information refer to Section 7 Parallel Input Output I O MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Memory 31 General Release Specification MC68HCO05RC16 Rev 3 0 32 Memory MOTOROLA General Release Spec ification MC 68HCO5RC 16 Section 3 Central Processor Unit 3 1 Contents me 4 eo oe has add ede Eran 99 mu ACCUNUIRO food dodge de dod x oae 34 34 Index Register riss dx X x aie X eda eo ere rre 34 3 5 Condition Code 5 35 WB POME 43 edo 36 B PROS OU Pd sede 36 3 2 Introduction This section describes the registers of the MC68HCO5RC16 central processor unit CPU The MCU contains five registers as shown in Figure 3 1 The interrupt stacking order is shown in Figure
99. uctio loea sess amaba e eee ha 53 OS QOMO 1oon ieu ER es on beh abe ERES quU eee dae 53 64 ee E EP d x E A 54 Wisi MOOR risata E EERS 54 Low Power 22222222422 222 2222 2222 2 2 2242 55 Section 7 Parallel Input Output I O 22 CODE aanaesaed aee dd eoa cd 024450 abd addi 57 T2 oh oo b tare eas one eee nee eh ee ee eT eee ee 57 POD hes 58 DB 58 7 6 1 59 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Table of Contents 7 Table of Contents Section 8 Core Timer Os iris iriri rer ESIS oko ke TITRES 61 EE 7 i o sd d ee EER 61 8 3 Core Timer Control and Status Register 63 8 4 Core Timer Counter 65 8 5 Computer Operating Properly COP Reset 66 8 6 Timer During Wait Mode 66 Section 9 Modulator Transmitter C MT 9 1 _ 67 g2 ata cohen kos eh eee eb daa es ceed ee 67 NAE Ee 68 Cur SSI cd hes ken wAqbE quiauxAsas d eub 70 9 4 1 NG 9 4 2 Carrier Generator Data Registers CLIST ad csc tai 72 HB Ce ol iie d
100. uctions to retrieve the current mechanical specifications MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Mechanical Specifications 111 Mechanical Specifications 12 3 28 Pin Plastic Dual In Line Package Case 710 02 SEATING PLANE NOTES POSITIONAL TOLERANCE OF LEADS 0 SHALL BE WITHIN 0 25mm 0 010 AT MAXIMUM MATERIAL CONDITION IN RELATION TO SEATING PLANE AND EACH OTHER DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL DIMENSION B DOES NOT INCLUDE MOLD FLASH MILLIMETERS INCHES DIM MIN MAX MIN MAX 3645 3721 1435 1 465 B 1372 1422 0 540 0 560 394 5 08 0155 0 200 D 036 056 0 014 0 022 F 102 152 0 040 0 060 G 2 54 BSC 0 100 BSC H 165 216 0 065 0 085 J 0 20 0 38 0 008 0 015 K 292 343 0 115 0 135 L 15 24 BSC 0 600 BSC M 0 15 0 15 051 102 0 020 0 040 12 4 28 Pin Small Outline Integrated Circuit Package Case 751F 04 14x P 0 010 0 25 PES SEATING PLANE y General Release Specification NOTES 1 2 3 4 gt AXIMI 006 S ogg 005 os CONDI MENSIONING AND TOLERANCING PER NSI Y14 5M 1982 ONTROLLING DIMENSION MILLIMETER MENSION A AND B DO NOT INCLUD
101. ulation mark period from the mark buffer register MBUFF When this counter underflows the modulator gate is closed and a 12 bit comparator is enabled which continually compares the logical complement of the contents of the still decrementing counter with the contents of the modulation space period register SREG When a match is obtained the modulator control gate is opened again Should SREG 0 the match will be immediate and no space period will be generated for instance for FSK protocols which require successive bursts of different frequencies When the match occurs the counter is reloaded with the contents of MBUFF SREG is reloaded with the contents of its buffer SBUFF and the cycle repeats The MCGEN bit in the MCSR must be set to enable the modulator timer The 12 bit MBUFF and SBUFF registers are accessed through three 8 bit modulator period registers MDR1 MDR2 and MDR3 General Release Specification MC68HCO05RC16 Rev 3 0 74 Carrier Modulator Transmitter CMT MOTOROLA Carrier Modulator Transmitter CMT Modulator The modulator can operate in two modes time or FSK In time mode the modulator counts clocks derived from the system oscillator and modulates a single carrier frequency or no carrier baseband In FSK mode the modulator counts carrier periods and instructs the carrier generator to alternate between two carrier frequencies whenever a modulation period mark space counts expires
102. ustomer develops and debugs the application program and then submits the MCU order along with the application program Motorola inputs the customer s application program code into a computer program that generates a listing verify file The listing verify file represents the memory map of the MCU The listing verify file contains the user ROM code and may also contain nonuser ROM code such as self check code Motorola sends the customer a computer printout of the listing verify file along with a listing verify form To aid the customer in checking the listing verify file Motorola will program the listing verify file into customer supplied blank preformatted Macintosh or DOS disks All original pattern media are filed for contractual purposes and are not returned Check the listing verify file thoroughly then complete and sign the listing verify form and return the listing verify form to Motorola The signed listing verify form constitutes the contractual agreement for the creation of the custom mask MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Ordering Information 117 Ordering Information 13 6 ROM Verification Units RVUs After receiving the signed listing verify form Motorola manufactures a custom photographic mask The mask contains the customer s application program and is used to process silicon wafers The application program cannot be changed after the manufacture of the mask begins Motorola then pro
103. vider stages with a one of four selector The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the timer control and status register at location 08 MC68HCO5RC16 Rev 3 0 General Release Specification MOTOROLA Core Timer 61 CTOF RTIF RTIE TOFC RTFC RTI RTO INTERNAL BUS 8 18 INTERNAL PERIPHERAL CLOCK E CTCR 09 CORE TIMER COUNTER REGISTER CTCR 22 210 p 2E e 4 POR 5 BIT COUNTER 2215 2214 23 2212 RTI SELECT CIRCUIT OVERFLOW DETECT CIRCUIT RTlour CTCSR TIMER CONTROL amp 08 STATUS REGISTER INTERRUPT CIRCUIT TO INTERRUPT LOGIC COP WATCHDOG 23 p TO RESET LOGIC Figure 8 1 Core Timer Block Diagram General Release Specification TIMER 8 COP CLEAR MC68HCO05RC16 Rev 3 0 62 Core Timer MOTOROLA Core Timer Core Timer Control and Status Register 8 3 Core Timer Control and Status Register The CTCSR contains the timer interrupt flag the timer interrupt enable bits and the real time interrupt rate select bits Figure 8 2 shows the value of each bit in the CTCSR when comin

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