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Maxim DS33R11 Switch User Manual

1. ADD NAME Bir 7 6 Bir 5 4 3 2 1 Bir 0 R h 01A LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA h TR SR3 01B LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA h TR IMR3 01C RAIS CI RSA1 RSAO TMF TAF RMF RCMF RAF h TR SR4 01D RAIS Cl RSA1 RSAO TMF TAF RMF RCMF RAF h TR IMR4 01E TESF TESEM TSLIP RESF RESEM RSLIP h TR SR5 01 TESF TESEM TSLIP RESF RESEM RSLIP h TR IMR5 020 TMEND RPE RPS RHWM RNE TLWM TNF h TR SR6 021 TMEND RPE RPS RHWM RNE TLWM TNF h TR IMR6 022 TMEND RPE RPS RHWM RNE TLWM TNF h TR SR7 023 TMEND RPE RPS RHWM RNE TLWM TNF h TR IMR7 024 Z BOCC RFDLAD RFDLF TFDLE RMTCH RBOC h TR SR8 025 BOCC RFDLAD RFDLF TFDLE RMTCH RBOC h TR IMR8 026 BBED BBCO BECO BRA1 BRAO BRLOS BSYNC h TR SR9 027 BBCO BECO BRA1 BRAO BRLOS BSYNC h TR IMR9 028 RSAOICS RSRCS RFCS BRCS THSCS PEICS TFCS BTCS h TR PCPR 029 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR PCDR1 02A CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR PCDR2 02B CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR PCDR3 02C CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 h TR PCDR4 02D H2UDR 2 H1UDR H1OBT h TR INFO4 02 TFULL REMPTY PS2 PS1 PSO h TR INFO5 02F TEMPTY TFULL REMPTY PS2 PS1 PSO h TR INFO6 030 CSC5 CSC4 CSC3 CSC2 CSCO FASSA CASSA CRC4SA h TR INFO7 031 RHR RHMS
2. 16 APPEICATIONS itio 17 ACRONYMS AND GLOSSARY 18 MAJOR OPERATING 5 19 BLOCKA DINGIRAMS 20 PIN 65 ess ansa nean nena 25 is PIN FUNCTONALDESCRIP TON a Eee Oe dat PESE 25 FUNG TIONAL DESCRIPT VR ER RR REP 41 8 1 PROCESSOR INTERFACE 42 07 7 Read WHE Dale 29 pa HM MR MD 42 Bm OMM BI PSU Lui LI I S d MM LP C EM 42 SLI Manuo oco aui oc eem 42 ETHERNET MAPPER Aaa YO ME 43 9 1 ETHERNET MAPPER CLOCKS kE Eabb aaa ERR aa aan ERR 43 g1 uo dois e iiic IT T EE 45 9 1 2
3. 303 TMG m P 303 Figure 12 12 Receive Side Boundary Timing Elastic Store Disabled sse 304 Figure 12 1 3 Receive Side 1 544MHz Boundary Timing Elastic Store 304 Figure 12 14 Receive Side 2 048MHz Boundary Timing Elastic Store 305 Figure 12 1 Figure 12 1 Figure 12 1 Figure 12 1 HMM ede EL 305 Suec die 306 7 Transmit Side Boundary Timing with Elastic Store 306 8 Transmit Side 1 544MHz Boundary Timing Elastic Store 307 6 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 19 Figure 12 20 Figure 12 21 Figure 12 22 Figure 12 23 Figure 12 24 Figure 12 25 Figure 12 26 Figure 12 27 Figure 12 28 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 13 9 Figure 13 10 Figure 13 11 Figure 13 12 Figure 13 13 Figure 13 14 Figure 13 15 Figure 13 16 Figure 13 17 Figure 13 18 Figure 13 19 Figure 13 20 Figure 14 1 Figure 14 2 Figure 14 3 Transmit Side 2 048MHz
4. B8ZS Bipolar with 8 Zero Substitution BOC Bit Oriented Code CRC Cyclical Redundancy Check D4 Superframe 12 frames per multiframe Multiframe Structure ESF Extended Superframe 24 frames per multiframe Multiframe Structure FDL Facility Data Link FPS Framing Pattern Sequence in ESF Fs Signaling Framing Pattern in D4 Ft Terminal Framing Pattern in D4 HDLC High Level Data Link Control MF Multiframe SLC 96 Subscriber Loop Carrier 96 Channels 18 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8 bit parallel control port and provides configuration for all the features of the device The Ethernet Link Transport Engine in the device can be configured for HDLC or X 86 encapsulation The integrated transceiver can be software configured for T1 E1 or J1 operation It is composed of a line interface unit LIU framer two additional HDLC controllers and a TDM backplane interface and is controlled via an 8 bit parallel port configured for Intel or Motorola bus operations The LIUs are composed of a transmit interface receive interface and a jitter attenuator The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used T1 waveform generation includes DSX 1 line build outs as
5. Register Address 0100h indirect 0100h Bit 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0101h Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0102h Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved MXFRM10 MXFRM9 MXFRM8 MXFRM7 MXFRM6 MXFRM5 Default 0 0 1 0 1 1 1 1 0103h Bit 07 06 05 04 03 02 01 00 Name MXFRM4 MXFRM3 MXFRM2 MXFRM1 MXFRMO Reserved Reserved Reserved Default 0 1 1 1 0 0 1 0 Bits 3 13 Maximum Frame Size MXFRM 0 10 These bits indicate the maximum packet size value All transmitted frames larger than this value are counted as long frames Bit 1 Reserved Note that this bit must be written to 1 for proper operation 191 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description Reserved MAC Reserved Control Register Register Address 010Ch indirect 010Ch Bit 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 010Dh Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved
6. 53 Table 9 5 Registers Related to Setting the iusserat riga den ER AY aes vied en KR samen ieee ERK 57 P Uu Ls oco 60 Table 7 ILE UN Cor M 60 Table T VE TT 3 Table 102 mmm 75 Table 1023 ET Sy vico pq D 76 Tabe PN m UT mU 77 Table 10 5 T3 Line Code Violation Counting sae AO HA dI einn 78 Table 10 6 ET Line Code Violation Counting 78 Table 10 7 T1 Path Code Violation Counting AITBOOTiBeHIeeuaaucasaeeseaaerka tator ria d mera da deir ka tac art 79 Table 10 8 T1 Frames Qut or Sync Counting Arrangements 80 Table 10 9 Time Slot Numbering SCHORROG RARO FELAVEDVEPOLRYER DU RID EEIAF OU RU ERANT SEXE 85 Table 10 10 Idle Code Array Address e E RR EDO AE ROLEDUEROLRIV CERRO RD ERI OA E 86 Table 10 11 Elastic Store Delay After IUS cis sire ERE VON E OLERITERO ER FEL A FERIA EE EROR Kart ER e tci 89 Table 10 12 HDLC Controler RROL EL ROT ERILERUEEREIAR E
7. Bits 0 7 MAC Read Data 2 MACRD16 23 One of four bytes of data read from the MAC Valid after a read command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACRD3 Register Description MAC Read Data byte 3 Register Address 145h Bit 7 6 5 4 3 2 1 0 Name MACRD31 MACRD30 MACRD29 MACRD28 MACRD27 MACRD26 MACRD25 MACRD24 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Read Data 3 MACRD24 31 One of four bytes of data read from the MAC Valid after a read command has been issued and the SU MACRWC MCS bit is zero Register Name Register Description SU MACWDO MAC Write Data 0 Register Address 146h Bit 7 6 5 4 3 2 1 0 Name MACWD7 MACWD6 MACWD5 MACWD4 MACWD3 MACWD2 MACWD1 MACWDO Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Write Data 0 MACWDO 7 One of four bytes of data to be written to the MAC Data has been written after a write command has been issued and the SU MACRWZC MCS bit is zero 175 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU MACWD1 Register Description MAC Write Data 1 Register Address 147h Bit 7 6 5 4 3 2 1 0 Name MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWDO9 MACWDO8 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Write Data 1 MACWD8 15 One of four bytes of data to be wr
8. Bit 3 Performance Monitoring Update Status PMS This bit indicates the status of the receive performance monitoring register counters update This bit will transition from low to high when the update is completed PMS is asynchronously forced low when the PMU bit goes low TCLKE and RCLKI must be present Bit 1 Bit Error Count BEC When 0 the bit error count is zero When 1 the bit error count is one or more Bit 0 Out Of Synchronization OOS When 0 the receive pattern generator is synchronized to the incoming pattern When 1 the receive pattern generator is not synchronized to the incoming pattern 147 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name BSRL Register Description BERT Status Register Latched Register Address 8Eh Bit 7 6 5 4 3 2 1 0 Name PMSL BEL BECL OOSL Default Bit 3 Performance Monitor Update Status Latched PMSL This bit is set when the PMS bit transitions from 0 to 1 Bit 2 Bit Error Detected Latched BEL This bit is set when a bit error is detected Bit 1 Bit Error Count Latched BECL This bit is set when the BEC bit transitions from O to 1 Bit 0 Out Of Synchronization Latched OOSL This bit is set when the OOS bit changes state Register Name BSRIE Register Description BERT Status Register Interrupt Enable Register Address 90h Bit 7 6 5 4 3 2 1 0 Nam
9. Bit 7 Runt Frame RF This bit is set to 1 if the received frame was altered by a collision or terminated within the collision window Bit 6 Watchdog Timeout WT This bit is set to 1 if a packet receive time exceeds 2048 byte times After 2048 byte times the receiver is disabled and the received frame will fail CRC check Bits 0 5 Frame Length FL 8 13 These 6 bits are the upper bits of the length in bytes of the received frame with FCS and Padding If Automatic Pad Stripping is enabled this value is the length of the received packet without PCS or Pad bytes SU RFSB2 Receive Frame Status Byte 2 Register Name Register Description Register Address 156h Bit 7 6 5 4 3 2 1 0 Name CRCE DB MIIE FT CS FTL Default 0 0 0 0 0 0 0 0 Bit 5 CRC Error CRCE This bit is set to 1 if the received frame does not contain a valid CRC value Bit 4 Dribbling Bit DB This bit is set to 1 if the received frame contains a noninteger multiple of 8 bits It does not indicate that the frame is invalid This bit is not valid for runt or collided frames Bit 3 MII Error MIIE This bit is set to 1 if an error was found on the MII bus Bit 2 Frame Type FT This bit is set to 1 if the received frame exceeds 1536 bytes It is equal to zero if the received frame is an 802 3 frame This bit is not valid for runt frames Bit 1 Collision Seen CS This bit is set to 1 if a late col
10. 138 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description GL BIS Global BERT Interrupt Status Register Address 0Dh Bit 7 6 5 4 2 0 Name BIS Default 0 0 0 0 0 0 Bit 0 BERT Interrupt Status BIS This bit is set to 1 if the BERT has an enabled interrupt generating event Register Name Register Description GL CON1 Connection Register for Ethernet Interface 1 Register Address OEh Bit 7 5 4 0 Name LINE1 0 Default 0 0 0 1 Bit 0 LINE1 0 This bit is preserved to provide software compatibility with multiport devices The LINE1 0 bit selects the Ethernet port that is to be connected to the Serial Interface Note that bidirectional connection is assumed between the Serial and Ethernet Interfaces The connection register and corresponding queue size must be defined for proper operation Writing a O to this register will disconnect the connection When a connection is disconnected 1 5 are sourced to the Serial Interface transmit and to the HDLC receiver and the clocks to the HDLC transmitter receiver are disabled 139 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver GL C1QPR Connection 1 Queue Pointer Reset Register Name Register Description Register Address 12h Bit 7 4 3 2 1 0 Name C1MRPR C1HWPR C1MH
11. DS33R11 5 DALLAS Ethernet Mapper with Integrated T1 E1 J1 Transceiver Iwww maxim icC COm GENERAL DESCRIPTION FEATURES The DS33R11 extends a 10 100 Ethernet LAN 10 100 IEEE 802 3 Ethernet MAC and segment by encapsulating MAC frames in HDLC or RMII Half Full Duplex with Automatic Flow X 86 LAPS for transmission over a T1 E1 J1 data Control stream Integrated T1 E1 J1 Framer and LIU The device performs store and forward of packets HDLC LAPS Encapsulation with with full wire speed transport capability The built in Programmable FCS and Interf Fill Committed Information Rate CIR Controller 3 eds provides fractional bandwidth allocation up to the line Committed Information Rate Controller rate in increments of 512kbps The DS33R11 can Provides Fractional Allocations in 512kbps operate with an inexpensive external processor Increments Programmable BERT for Serial TDM APPLICATIONS Interface Transparent LAN Service External 16MB 100MHz SDRAM Buffering LAN Extension A Ethernet Delivery Over T1 E1 J1 Parallel Microprocessor Interface 1 8V 3 3V Supplies FUNCTIONAL DIAGRAM Reference Design Routes Two Signal Layers IEEE 1149 1 JTAG Support Features continued on page 11 ORDERING INFORMATION PART TEMP RANGE PIN PACKAGE DS33R11 40 C to 85 C 256 BGA MI RMI DS33R11 Note Some revisions of this device may incorporate deviations from publ
12. E PARE 94 Table 10 13 Transtorimer SPC AOS E 104 Table 10 14 Transmit Error Insertion Setup 114 Table 10 15 Error Ineerticonm Example AA 111 Table Regit Addross I 117 Table 11 2 Global Ethernet Mapper Register Bit Map 001 enne 118 Table 11 3 Arbiter Register BIE ascdelapecenip ta pi EOD AED RU 119 Table 11 4 BERT Register Bit Map 119 Table 11 5 Serial Interlace Register Bit A 120 Table 11 6 Ethernet Interface Register DORIA 122 Table 11 7 Indirect Register BAT Map 122 Table 11 8 T1 E1 J1 Transceiver Register Bit Map Active when CST 0 125 Table 13 1 Recommended DO Operating X Mt ERE Iu EF ED SUE 313 Table 12 2 DC Elecirical GharscterielicB eo Seo ea 313 Table 12 3 Thetinal EPOR RR FIBER EE DEI EM NP RO aoa 314 Table 134 314 Table 1543 Trams iis MII IRONICE EEN 315 Table 12 5 Receive MI 316 Table
13. 11 2 1 e 40 C to 85 C Junction Operating Temperature 2 Ie 40 C to 125 C Storage Temperature 55 C to 125 C Soldering a erede e IRR See IPC JEDEC J STD 020 Specification These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods of time can affect reliability Ambient Operating Temperature Range is assuming the device is mounted on a JEDEC standard test board in a convection cooled JEDEC test enclosure Note The typ values listed below are not production tested Table 13 1 Recommended DC Operating Conditions VDD3 3 3 3V 5 VDD1 8 1 8V 595 T 40 C to 85 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 1 Vin 2 35 3 465 V Logic 0 Viu 0 3 0 75 V Supply VDD3 3 5 VDD3 3 3 135 3 300 3 465 V Supply VDD1 8 5 VDD1 8 1 71 1 8 1 89 V Table 13 2 DC Electrical Characteristics VDD3 3 3 3V 596 VDD1 8 1 8V 5 T 40 C to 85 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current VDD3 3 3 465V Ippio Notes 1 2
14. T 107 2 107 Figure 10 14 Optional Crystal CORO OTI sanati sat sanat t DANE 108 Figure 10 1 Figure 10 1 Figure 10 1 Figure 10 1 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 12 9 Figure 12 1 Figure 12 1 5 Simplified Diagram of BERT Network 109 6 Simplified Diagram of BERT in Backplane Direction nn 109 TUJI Troanemit Flow m 113 SET TAON DT mm 115 TX Serial Interlace Puncture ME 300 Rx Serial Interlace Functional e 300 Transmit Byte Syne d expl YE EU PR i er eR mae Posen e UR 301 Receive Byte Syne Functional TITIO 301 MID Transmit Functional TIMI 301 MII Transmit Half Duplex with a Collision Functional 302 IL Funcional ME T 302 RMII Transmit interface 302 RMI Receive Interface Functional M 303 0 Roceive Side MN e
15. and TT1 of LIC4 register must be set to 0 in this configuration T1 Mode L2 L1 LO Application N 1 Return Loss Rt 1 0 0 0 DSX 1 Oft to 133ft OdB CSU 1 2 NM 0 0 0 1 DSX 1 133ft to 266ft 1 2 NM 0 0 1 0 DSX 1 266ft to 399ft 1 2 NM 0 0 1 1 DSX 1 399ft to 533ft 1 2 NM 0 1 0 0 DSX 1 533ft to 655ft 1 2 NM 0 1 0 1 7 5dB CSU 1 2 NM 0 1 1 0 15dB CSU 1 2 NM 0 1 1 1 22 5dB CSU 1 2 NM 0 Bit 4 Receive Equalizer Gain Limit EGL This bit controls the sensitivity of the receive equalizer T1 Mode E1 Mode 0 368B long haul 0 12dB short haul 1 15dB limited long haul 1 43dB long haul Bit 3 Jitter Attenuator Select JAS 0 7 place the jitter attenuator on the receive side 1 7 place the jitter attenuator on the transmit side Bit 2 Jitter Attenuator Buffer Depth Select JABDS 0 128 bits 1 32 bits use for delay sensitive applications Bit 1 Disable Jitter Attenuator DJA 0 jitter attenuator enabled 1 jitter attenuator disabled Bit 0 Transmit Power Down TPD 0 powers down the transmitter and tri states the TTIP and TRING pins 1 normal transmitter operation 255 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TLBC Register Description Transmit Line Build Out Control Register Address 7Dh Bit 7 6 5 4 3 2 1 0 Name AGCE GC5 GC4 GC3 GC2 GC1 GCO coc 0 0 0 0 0 0 Bi
16. 6 5 4 TPEN3 TPEN2 TPEN1 TPENO OC7h LI TEPHC MEIMS TPER6 5 TPER4 TPER3 TPER2 TPER1 TPERO OC8h LI TPPSR 2 OC9h LI TPPSRL E TEPFL OCAh LI TPPSRIE 7 4 TEPFIE OCBh Reserved z M OCCh LI TPCRO TPC7 TPC6 IPCS 4 TPC3 TPC2 TPC1 TPCO OCDh LI TPCR1 IPC15 14 TPC13 TPC12 11 10 9 TPC8 OCEh LI TPCR2 TPC23 TPC22 TPC21 TPC20 TPC19 TPC18 TPC17 TPC16 OCFh Reserved ODOh LI TBCRO TBC7 TBC6 5 4 TBCS3 TBC2 TBC1 TBCO OD1h LLTBCR1 15 TBC14 TBC13 TBC12 11 10 9 TBC8 OD2h LI TBCR2 TBC23 TBC22 TBC21 TBC20 TBC19 TBC18 TBC17 TBC16 OD3h LI TBCR3 TBC31 TBC30 TBC29 TBC28 TBC27 TBC26 TBC25 TBC24 OD4h LITMEI TMEI OD5h Reserved z gt 2 5 OD6h Li THPMUU 3 TPMUU OD7h Li THPMUS TPMUS OD8h LI TX86EDE 8 z 2 X86ED OD9h LI TRX86A X86TRA7 X86TRA6 X86TRA5 X86TRA4 X86TRA3 X86TRA2 X86TRA1 X86TRAO ODAh LI TRX8C X86TRC7 X86TRC6 X86TRC5 X86TRC4 X86TRC3 X86TRC2 X86TRC1 X86TRCO ODBh LI TRX86SAPIH TRSAPIH7 TRSAPIH6 TRSAPIH5 TRSAPIH4 TRSAPIH3 TRSAPIH2 TRSAPIH1 TRSAPIHO ODCh LLTRX86SAPIL TRSAPIL7 TRSAPIL6 TRSAPIL5 TRSAPIL4 TRSAPIL3 TRSAPIL2 TRSAPIL1 TRSAPILO ODDh LI CIR CIRE CIR6 CIR5 CIR4 CIR3 CIR2 CIR1 CIRO 100h LI RSLCR gt d RDENPLT 101h RFPD RF16 RFED RDD
17. 7 6 5 Bit 4 3 Bit 2 Bit 1 Bit 0 140h SU MACRADL MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRAO 141h SU MACRADH MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 MACRAO9 MACRAO8 142h SU MACRDO MACRD7 MACRD6 MACRD5 MACRD4 MACRD3 MACRD2 MACRD1 MACRDO 143h SU MACRD1 MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 MACRD8 144h SU MACRD2 MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16 145h SU MACRD3 MACRD31 MACRD30 MACRD29 MACRD28 MACRD27 MACRD26 MACRD25 MACRD24 146h SU MACWDO MACWD7 MACWD6 MACWD5 MACWD4 MACWD3 MACWD2 MACWD1 MACWDO 147h SU MACWD1 MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWDO9 MACWDO08 148h SU MACWD2 MACWD23 MACWD22 MACWD21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16 149h SU MACWD3 MACD31 MACD30 MACD29 MACD28 MACD27 MACD26 MACD25 MACD24 14Ah SU MACAWL MACAW 7 MACAW 6 MACAW 5 MACAW4 MACAW3 MACAW2 MACAW1 MACAWO 14Bh SU MACAWH MACAW 15 MACAW 14 MACAW 13 MACAW12 MACAW11 MACAW10 MACAW9 8 14Ch SU MACRWC MCRW MCS 14Eh RESERVED gt 14Fh SU LPBK z 2 QLP 150h SU GCR CRCS H10S ATFLOW JAME 151h SU TFRC NCFQ TPDFCB TPRHBC TPRCB 152h SU TFSL UR EC LC ED LOC NOC 153h SU TFSH PR HBF CC3 CC2 CC1 CCo LCO DEF 154h SU RFSBO FL7
18. RMSYNC RSYNC CHANNEL 23 CHANNEL 24 CHANNEL 1 RSIG A B CIA D B A B C A DIB RCHBLK 3 NOTE 1 RSYNC IS IN THE OUTPUT MODE TR IOCR1 4 0 NOTE 2 RSYNC IS IN THE INPUT MODE TR IOCR1 4 1 NOTE RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 304 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 14 Receive Side 2 048MHz Boundary Timing Elastic Store Enabled RSYSCLK 31 _ CHANNEL 32 CHANNEL 1 RSERO X A X X Ass wss X X X X X RSYNC RMSYNC RSYNC CHANNEL 31 CHANNEL 32 CHANNEL 1 RSIG A X B IC A D IB X B JC AI DIB RCHCLK RCHBLK NOTE 1 RSERO DATA IN CHANNELS 1 5 9 13 17 21 25 AND 29 ARE FORCEDTO 1 NOTE 2 RSYNC IS IN THE OUTPUT MODE TR IOCR1 4 0 NOTE 3 RSYNC IS INTHE INPUT MODE TR IOCR14 1 NOTE 4 RCHBLK IS FORCED TO 1IN THE SAME CHANNELS AS RSERO SEE NOTE 1 NOTE amp THE F BIT POSITION IS PASSED THROUGH THE RECEIVE SIDE ELASTIC STORE Figure 12 15 Transmit Side D4 Timing FRAME TSYNC TSSYNC 2 TSYNC 3 TSYNC NOTE 1 TSYNC IN THE FRAME MODE
19. TCHBLK RCLKO RSYSCLK TCLKT TSYSCLK NOTE RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15 17 THROUGH 25 AND BIT 1 TIME SLOT 26 RSERO TSE RCHCLK TCHCLK RCHBLK TCHBLK Figure 12 25 Transmit Side Timing CHANNEL 25 CHANNEL 26 LSB MSB FRAME 14 15 16 1 2 3 4 5 6 11 12 13 14 15 146 1 2 3 4 5 6 7 8 9 10 TSYNC TSSYNC TSYNC NOTE 1 TSYNC IN FRAME MODE TR IOCR1 2 0 NOTE 2 TSYNC IN MULTIFRAME MODE TR IOCR1L2 1 NOTE 3 THIS DIAGRAM ASSUMES BOTH THE CAS MF ANDTHE MF BEGIN WTH THE TAF FRAME 310 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 26 Transmit Side Boundary Timing Elastic Store Disabled TCLKT CHANNEL 1 CHANNEL 2 TSERI LSB 1 A 5 4 5 5 5 6 5 7 5 8 5 LSB MSB TSYNC TSYNC CHANNEL 1 CHANNEL 2 TSIG y y y y Y y A B D TCHCLK TCHBLK NOTE 1 TSYNC IS IN THE OUTPUT MODE TR IOCR11 1 NOTE 2 TSYNC IS IN THE INPUT MODE 1 1 0 NOTE 3 TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2 NOTE 5 THE SIGNALING DATA AT DURING CHANNEL 115 NORMALL
20. 55 9 14 ETHERNET INTERFACE 56 2 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 58 AS ETHERNET IE ME UU LE IM MEL 59 TUE T 61 MENO 61 9 15 3 PHY Management Block MDIO Interface 2 22 0000 000000000 9 62 9 16 BERT IN THE ETHERNET e rii e asi ese eines senis 62 Recevre Dala n RENT UL I UU TN 63 g e Paier So er ied ro MNT 64 PIE a italiens 64 BID Faten COO oh cts tty ce sacs auc ks Beck nd DR Re Lun de Dn bend Gabun 64 BAY IRANSMITPASKET PROCESSOR 65 9 18 RECEIVE PACKET 1 20 1 1 4 sese sanae 66 9 19 X 86 ENCODING AND 0 21 0 110 m nn emen nnn nnnnn n 68 9 20 COMMITTED INFORMATION RATE 71 10 TRANSCEIVER cannon nhat 72 RS MAL LL E MEME 7
21. 7 0 Data Valid CS CST Figure 13 12 Motorola Bus Write Timing MODEC 01 ADDR 12 0 Address Valid DATA 7 0 CS CST 326 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 9 AC Characteristics Receive Side Table 13 14 AC Characteristics Receive Side Vpp 3 3V 5 T4 40 C to 85 C Note 1 Figure 13 3 Figure 13 14 and Figure 13 15 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 488 E1 RDCLKO Period tp ns 648 T1 Note 2 200 0 5 tip RDCLKO Pulse Width ns tue Note 2 200 0 5 tip t Note 3 150 0 5t RDCLKO Pulse Width ns tie Note 3 150 0 5 tip 488 E1 RDCLKI Period tcp 648 T1 ns tcu 20 0 5 tcp RDCLKI Pulse Width add toL 20 in Note 4 648 RSYSCLK Period tsp Note 5 488 ns tsu 20 0 5 tsp ns RSYSCLK Pulse Width ts 20 05 ns RSYNC Setup to RSYSCLK Falling tsu 20 ns RSYNC Pulse Width tew 50 ns RPOSI RNEGI Setup to RDCLKI Falling tsu 20 ns RPOSI RNEGI Hold from RDCLKI Falling tup 20 ns RSYSCLK RDCLKI Rise and Fall Times tr te 22 ns Delay RDCLKO to RPOSO RNEGO top 50 ns Valid Delay RCLKO to RSERO RDATA RSIG 50 ns Valid Delay RCLKO to RCHCLK RSYNC t 50 RCHBLK RFSYNC i Delay RSYSCLK to RSERO RSIG Valid tps 22 ns Delay RSYSCLK to RCHCLK RCHBLK t 22 s RMSYNC RSYNC Note 1
22. Bits 0 7 Per Channel Loopback Enable for Channels 17 to 24 CH17 to CH24 0 loopback disabled 1 enable loopback source data from the corresponding receive channel Register Name TR PCLR4 Register Description Per Channel Loopback Enable Register 4 Register Address 4Eh Bit 7 6 5 4 3 2 1 0 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 Default 0 0 0 0 0 0 0 0 Bits 0 7 Per Channel Loopback Enable for Channels 25 to 32 CH25 to CH32 0 loopback disabled 1 enable loopback source data from the corresponding receive channel 243 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR ESCR Register Description Elastic Store Control Register Register Address 4Fh Bit 7 6 5 4 3 2 1 0 TESALGN TESR TESMDM TESE RESALGN RESR RESMDM RESE Bit 7 Transmit Elastic Store Align TESALGN Setting this bit from a 0 to a 1 forces the transmit elastic store s write read pointers to a minimum separation of half a frame No action is taken if the pointer separation is already greater or equal to half a frame If pointer separation is less than half a frame the command is executed and the data is disrupted It should be toggled after TSYSCLK has been applied and is stable It must be cleared and set again for a subsequent align See Section 10 12 3 for details Bit 6 Transmit Elastic Store Reset TESR Setting this b
23. Bits 0 7 Receive Aborted Packet Count RAPC 7 0 Eight bits of a 24 bit value Register description below Register Name LI RAPCB1 Register Description Receive Aborted Packet Count Byte 1 Register Register Address 111h Bit 7 6 5 4 3 2 1 0 Name RAPC15 RAPC14 RAPC13 RAPC12 RAPC11 RAPC10 9 RAPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Packet Count RAPC 15 8 Eight bits of a 24 bit value Register description below Register Name LI RAPCB2 Register Description Receive Aborted Packet Count Byte 2 Register Register Address 112h Bit 7 6 5 4 3 2 1 0 Name RAPC23 RAPC22 RAPC21 RAPC20 RAPC19 RAPC18 RAPC17 RAPC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Packet Count RAPC 23 16 The twenty four bit value from these three registers indicates the number of packets received with a packet abort indication The byte count for these packets is included in the receive aborted byte count register REBCR 167 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RSPCBO Register Description Receive Size Violation Packet Count Byte 0 Register Register Address 114h Bit 7 6 5 4 3 2 1 0 Name RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Size Violation Packet Count RSPC 7 0 Eight bits of a 24 bit value Register des
24. HDLCD RSFD h TR H1RC 032 RHR RHMS HDLCD RSFD h TR H2RC 033 RSERC RSIGM RHDB3 RG802 RCRC4 FRC SYNCE RESYNC h TR E1RCR1 034 TR E1RCR2 RCLA 126 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADD NAME Bit 7 BIT 6 5 4 Bir 3 2 1 R h 035 TFPT T16S TUA1 TSiS TSA1 THDB3 TG802 TCRC4 h TR E1TCR1 036 Reserved Reserved Reserved Reserved Reserved AEBE AAIS ARA h TR E1TCR2 037 RBOCE RBR RBF1 RBFO SBOC h TR BOCC 038 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR RSINFO1 039 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR RSINFO2 03A CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR RSINFO3 03 CH30 CH29 CH28 CH27 CH26 CH25 h TR RSINFO4 03C CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR RSCSE1 03D CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR RSCSE2 24 23 22 21 CH20 CH19 CH18 CH17 h TR RSCSE3 CH30 CH29 CH28 CH27 CH26 CH25 h TR RSCSE4 040 GRSRE RFE RFF RCCS TCCS FRSAO h TR SIGCR 041 MECU ECUS EAMS VCRFS FSBE MOSCRF LCVCRF h TR ERCNT 042 LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCCV8 h TR LCVCR1 043 LCVC7 LCVC6 LCVC5 LCVC4 LCVC3 LCVC2 LCVC1 LCVCO h TR LCVCR2 044 PCVC15 PCVC14 PCVC13 PCVC12 PCVC11 PCVC10 PCVC9 PCVC8 h TR PCVCR1 045 PCVC7 PCVC6 PCVC5 PCVC4 PCVC3 PC
25. LOOPBACK SEE TR LIC1 i REGISTER FRAMER PAYLOAD LOOPBACK LOOPBACK i SEE NOTES gt BPCLK FLB 0 RECEIVE FRAMER j gt RCLK 1 1 TRANSMIT FORMATTER The TCLKT MUX is dependent on the state of the 550 and 551 bits in the TR CCR1 register and the state of the TCLKT pin 72 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 10 1 T1 E1 J1 Transmit Clock Source TCSS1 TCSSO TRANSMIT CLOCK SOURCE 0 0 The TCLKT pin C is always the source of transmit clock Switch to the recovered clock B when the signal at the TCLKT pin 0 1 A fails to transition after one channel time 1 0 Use the scaled signal A derived from MCLK as the transmit clock The TCLKT pin is ignored 4 1 Use the recovered clock B as the transmit clock The TCLKT pin is ignored 10 2 Per Channel Operation Some of the features described in the data sheet that operate on a per channel basis use a special method for channel selection There are five registers involved per channel pointer register TR PCPR and per channel data registers 1 4 TR PCDR1 4 The user selects which function or functions are to be applied on a per channel basis by setting the app
26. Bits 3 to 5 Transmit Error Insertion Rate TEIR 2 0 These three bits indicate the rate at which errors are inserted in the output data stream One out of every 10 bits is inverted TEIR 2 0 is the value n A TEIR 2 0 value of 0 disables error insertion at a specific rate A TEIR 2 0 value of 1 result in every 10 bit being inverted A TEIR 2 0 value of 2 results in every 100 bit being inverted Error insertion starts when this register is written to with a TEIR 2 0 value that is nonzero If this register is written to during the middle of an error insertion process the new error rate is started after the next error is inserted Bit 2 Bit Error Insertion Enable BEI When 0 single bit error insertion is disabled When 1 single bit error insertion is enabled Bit 1 Transmit Single Error Insert TSEI This bit causes a bit error to be inserted in the transmit data stream if and single bit error insertion is enabled A 0 to 1 transition causes a single bit error to be inserted For a second bit error to be inserted this bit must be set to 0 and back to 1 Note If this bit transitions more than once between error insertion opportunities only one error is inserted All other bits in this register besides BEI and TSEI and TIER must be reset to 0 for proper operation Register Name BSR Register Description BERT Status Register Register Address 8Ch Bit 7 6 5 4 3 2 1 0 Name PMS BEC OOS Default 0 0 0 0 0 0 0 0
27. REGISTER FUNCTION GL CON1 Enables connection between the Ethernet Interface and the Serial Interface Note that once connection is set up then the queues and thresholds can be setup for that connection AR TQSC1 Size for the Transmit Queue in Number of 32 2K packets AR RQSC1 Size for the Receive Queue in Number of 32 2K packets GL TRQIE Interrupt enable for items related to the connections at the global level GL TRQIS Interrupt enable status for items related to the connections at the global level LI TQTIE Enables for the Transmit queue crossing high and low thresholds LI TQCTLS Latched status bits for connection high and low thresholds for the transmit queue SU QRIE Enables for the receive queue crossing high and low thresholds SU QCRLS Latched status bits for receive queue high and low thresholds GL C1QPR Resets the connection pointer 9 12 Arbiter The Arbiter manages the transport between the Ethernet port and the Serial port It is responsible for queuing and dequeuing packets to a single external SDRAM The arbiter handles requests from the HDLC and MAC to transfer data to and from the SDRAM 52 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 13 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost The DS33R11 allows for optional flow control based on the queue high watermark or throu
28. te TDCLKI TPOSI TNEGI 334 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 12 JTAG Interface Timing Table 13 17 JTAG Interface Timing VDD3 3 3 3V 5 VDD1 8 1 8V 5 T 40 C to 85 C Note 1 Figure 13 20 PARAMETER SYMBOL MIN TYP MAX UNITS JTCLK Clock Period 11 1000 ns JTCLK Clock High Low Time Note 2 t2 t3 50 500 ns JTCLK to JTDI JTMS Setup Time t4 2 ns JTCLK to JTDI JTMS Hold Time t5 2 ns JTCLK to JTDO Delay t6 2 50 ns JTCLK to JTDO HIZ Delay t7 2 50 ns JTRST Width Low Time t8 100 ns Note 1 Timing parameters in this table are guaranteed by design GBD Note 2 Clock can be stopped high or low Figure 13 20 JTAG Interface Timing Diagram JTDI JTMS 335 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 14 JTAG INFORMATION The DS33R11 contains two JTAG ports Port 1 is for the Ethernet Mapper and Port 2 is for the T1 E1 J1 Transceiver Because of this this device requires special consideration during JTAG test design For more information on performing JTAG testing using this device go to www maxim ic com support The device supports the standard instruction codes SAMPLE PRELOAD BYPASS and EXTEST Optional public instructions included are HIGHZ CLAMP and IDCODE See Table 14 1 The DS33R11 contains the following as required by IEEE 1149 1 Standard Test Access Port and Boundary Scan Architec
29. 10 25 2 BERT Mapping The BERT function can be assigned to the network direction or backplane direction through the direction control bit in the BIC register TR BIC 1 See Figure 10 15 and Figure 10 16 The BERT also can be assigned on a per channel basis The BERT transmit control selector BTCS and BERT receive control selector BRCS bits of the per channel pointer register TR PCPR are used to map the BERT function into time slots of the transmit and receive data streams In T1 mode the user can enable mapping into the F bit position for the transmit and receive directions through the RFUS and TFUS bits in the BERT interface control TR BIC register 108 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 15 Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER CHANNEL AND F BIT T1 MODE MAPPING TO TRANSMIT FRAMER Figure 10 16 Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER CHANNEL AND F BIT T1 MODE MAPPING TO TRANSMIT FRAMER BERT RECEIVER BERT TRANSMITTER gt 0 1 BERT RECEIVER BERT TRANSMITTER 109 of 344 TO RECEIVE SYSTEM BACKPLANE INTERFACE FROM TRANSMIT SYSTEM BACKPLANE INTERFACE TO RECEIVE gt SYSTEM BACKPLANE INTERFACE FROM TRANSMIT SYSTEM BACKPLANE INTERFACE DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 25 3 BERT Repetitive Pattern
30. 182 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description SU RMFSRL Receiver Maximum Frame Low Register Register Address 158h Bit 7 6 5 4 3 2 1 0 Name RMPS7 RMPS6 RMPS5 RMPS4 RMPS3 RMPS2 RMPS1 RMPSO Default 1 1 1 0 0 0 0 0 Bits 7 0 Receiver Maximum Frame RMPS 0 7 Eight bits of sixteen bit value Register description below Register Name Register Description SU RMFSRH Receiver Maximum Frame High Register Register Address 159h Bit 4 7 6 5 4 3 2 1 0 Name RMPS15 RMPS14 RMPS13 RMPS12 RMPS11 RMPS10 RMPS9 RMPS8 Default 0 0 0 0 0 1 1 1 Bits 7 0 Receiver Maximum Frame RMPS 8 15 This value is the receiver s maximum frame size in bytes up to a maximum of 2016 bytes Any frame received greater than this value is rejected The frame size includes destination address source address type length data and crc 32 The frame size is not the same as the frame length encoded within the IEEE 802 3 frame Any values programmed that are greater than 2016 will have unpredictable behavior and should be avoided Register Name SU RQLT Register Description Receive Queue Low Threshold Watermark Register Address 15Ah Bit 7 6 5 4 3 2 1 0 Name RQLT7 RQLT6 RQLT5 RQLT4 RQLT3 RQLT2 RQLT1 RQLTO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Queue Low Thr
31. Clock MOUNBS eese tei eret e ete eret EE e ee Ep Ps eI Eee ER e EE EE 45 9 2 RESETS AND LOW POWER 0 1 he nn nne hern erre rr ne ese ese esses ens 46 9 3 INITIALIZATION AND CONFIGURATION cient en hr baa E ER ER CE re a 47 94 GLOBAL RESOURCES TT 47 98 5 PER PORT RESOURCES 47 48 9 7 INTERRUPT INFORMATION REGISTERS 50 BB MM 50 9 9 INFORMATION REGISTERS 0 50 9 10 c rar E RD RD BY RACHEL VERD CELER ERR 50 9 11 CONNECTIONS AND QUEUES ERR RE RR yRREEEME 51 uu m c ua LM ME 52 AIT A 53 quu Ric PE 54 TE EN FOW CONGO TER 55 yi
32. RCHCLK gt RCHBLK ELASTIC STORE SIGNALING BUFFER TSERI amp TSIG amp TSSYNC TSYSCLK gt TSYNC gt TESO TDATA gt TLINK v CHANNEL TCHCLK TIMING TCHBLK n 24 of 344 CLK MUX TCLKT DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 7 PIN DESCRIPTIONS 7 1 Pin Functional Description Note that all digital pins IO pins in JTAG mode This feature increases the effectiveness of board level ATPG patterns LEGEND I input output input with pullup Oz output with tri state IO bidirectional lOz bidirectional pin with tri state Table 7 1 Detailed Pin Descriptions NAME PIN TYPE FUNCTION MICROPROCESSOR PORT Address Bit 0 Address bit 0 of the microprocessor interface AO A18 Va ein Least Significant Bit A1 B18 Address Bit 1 Address bit 1 of the microprocessor interface A2 C18 Address Bit 2 Address bit 2 of the microprocessor interface A3 A17 Address Bit 3 Address bit 3 of the microprocessor interface A4 B17 Address Bit 4 Address bit 4 of the microprocessor interface A5 C17 Address Bit 5 Address bit 5 of the microprocessor interface A6 A16 Address Bit 6 Address bit 6 of the
33. Register Name TR RDSOM Register Description Receive DSO Monitor Register Register Address 77h Bit 7 6 5 4 3 2 1 0 1 B2 B3 B4 B5 B6 B7 B8 Defaut 0 0 0 0 oO 0 o 0 Bits 0 7 Receive DSO Channel Bits B1 to B8 Receive channel data that has been selected by the receive channel monitor select register B8 is the LSB of the 050 channel last bit to be received 254 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR LIC1 Register Description Line Interface Control 1 Register Address 78h Bit 7 6 5 4 3 2 1 0 Name EGL JAS JABDS DJA TPD L2 L1 LO Bits 5 7 Line Build Out Select LO to 12 When using the internal termination the user needs only to select 000 for 75Q operation or 001 for 1200 operation below This selects the proper voltage levels for 75Q or 1200 operation Using TTO and TT1 of the TR LICR4 register the user can then select the proper internal source termination Line build outs 100 and 101 are for backwards compatibility with older products only E1 Mode L2 L1 LO Application N 1 Return Loss Rt 1 0 0 0 750 normal 1 2 NM 0 0 1 1200 normal 1 2 NM 0 1 0 0 750 with high return loss 1 2 21dB 6 2 1 0 1 1200 with high return loss 1 2 21dB 11 6
34. SET TO 600 EACH IF THE INTERNAL RECEIVE SIDE TERMINATION FEATURE IS ENABLED WHEN THIS FEATURE IS DISABLED 37 50 FOR 750 COAXIAL E1 LINES 602 FOR 1200 TWISTED PAIR E1 LINES OR 500 FOR 1000 TWSTED PAIR T1 LINES NOTE 3 CERAMIC Refer to Application Note 324 T1 E1 Network Interface Design for more information on protected interfaces Table 10 13 Transformer Specifications SPECIFICATION RECOMMENDED VALUE 1 1 receive and 1 2 transmit 2 Transmit Transformer DC Resistance Primary Device Side 1 Secondary 2 Receive Transformer DC Resistance Primary Device Side Secondary ax ax 00 m 00 m 104 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 8 E1 Transmit Pulse Template 2 37VPEAK 3 00VPEAK G 703 TEMPLATE a A a lt a ul lt o a IN 750 SYSTEMS 1 0 ON THE SCALE IN 1200 SYSTEMS 1 0 ON THE SCALE 250 200 150 100 50 0 50 100 TIME ns Figure 10 9 T1 Transmit Pulse Template MAXIMUM CURVE MINIMUM CURVE Ul Time Amp Ul Time Amp 0 77 500 0 05 0 77 500 0 05 0 39 255 0 05 0 23 150 0 05 0 27 175 0 80 0 23 150 0 50 0 27 175 1 15 0 15 100 0 95 0 12 75 1 15 0 00 0 0 95 0 00 0 1 05 0 15 100 0 90 0 27 175 1 05 0 23 150 0 50 0 35 225 0 07 0 23 150 0 45 0 93 600 0 05 0 46 300 0 45 1 16 750 0 05 0 66 430 0 20 0 93 600 0 05 1 16 750 0 05 NORMALIZED AMPLI
35. 0 Bits 0 7 Receive Up Code Definition Bits 0 7 C0 C7 A don t care if a 1 bit to 7 bit length is selected 274 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RDNCD1 Register Description Receive Down Code Definition Register 1 Register Address BBh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Default Note Writing this register resets the detector s integration period Bit 7 Receive Down Code Definition Bit 7 C7 First bit of the repeating pattern Bit 6 Receive Down Code Definition Bit 6 C6 A don t care if a 1 bit length is selected Bit 5 Receive Down Code Definition Bit 5 C5 A don t care if a 1 bit or 2 bit length is selected Bit 4 Receive Down Code Definition Bit 4 C4 A don t care if a 1 bit to 3 bit length is selected Bit 3 Receive Down Code Definition Bit 3 C3 A don t care if a 1 bit to 4 bit length is selected Bit 2 Receive Down Code Definition Bit 2 C2 A don t care if a 1 bit to 5 bit length is selected Bit 1 Receive Down Code Definition Bit 1 C1 A don t care if a 1 bit to 6 bit length is selected Bit 0 Receive Down Code Definition Bit 0 CO A don t care if a 1 bit to 7 bit length is selected Register Name TR RDNCD2 Register Description Receive Down Code Definition Register 2 Register Address BCh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Defaut 9 4 50 3911 70 1
36. 117 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 1 Register Bit Maps Bits that are reserved are noted with a single dash All registers not listed are reserved and should be initialized with a value of OOh for proper operation unless otherwise noted 11 1 1 Global Ethernet Mapper Register Bit Map Table 11 2 Global Ethernet Mapper Register Bit Map ADDR Name Bir 7 Bir 6 5 Bir 4 Bir 3 BIT 2 1 Bir 0 O0h 1207 1206 1205 1204 1203 1002 1001 1000 O1h X GLIDRH ID15 ID14 ID13 ID12 1011 1010 1009 1008 02h 1 REF CLKO RST 03h GL BLR GL BLC1 04h GL RTCAL RLCALS1 TLCALS1 05h GL SRCALS REFCLKS SYSCLS 06h GL LIE LIN1TIE LIN1RIE 07h GL LIS LIN1TIS LIN1RIS 08h GL SIE SUB1IE 09h GL SIS SUB1IS OAh GL TRQIE OBh GL TRQIS TQ1IS 1 5 OCh GL BIE BIE ODh GL BIS z BIS OEh GL CON1 7 LINEO OFh Reserved 10h Reserved z 11h Reserved E n _ 12 GL C1QPR C1MRPR C1HWPR C1MHPR C1HRPR 13h Reserved i 14h Reserved 2 i 15h Reserved _ 20h 5 z s 2 BISTE 21h GL BISTPF BISTDN BI
37. 5 1 TESTO T1 E1 SFTRST Default 0 0 0 0 0 0 0 0 Bits 2 3 Test Mode Bits TESTO TEST1 Test modes are used to force the output pins of the transceiver into known states This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses TEST1 TESTO Effect On Output Pins Operate normally Force all output pins into tri state including all I O pins and parallel port pins 0 Force all output pins low including all I O pins except parallel port pins Force all output pins high including all I O pins except parallel port pins Bit 1 Transceiver Operating Mode T1 E1 Used to select the operating mode of the framer formatter digital portion of the Transceiver The operating mode of the LIU must also be programmed 0 T1 operation 1 E1 operation Bit 0 Software Issued Reset SFTRST A 0 to 1 transition causes the register space in the T1 E1 J1 transceiver to be cleared A reset clears all configuration and status registers The bit automatically clears itself when the reset has completed 201 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IOCR1 Register Description Configuration Register 1 Register Address 01h Bit 7 6 5 4 3 2 1 0 RSMS RSMS2 RSMS1 RSIO TSDW TSM TSIO ODF Default 0 0 0 0 0 0 0 0 Bit 7 RSYNC Multiframe Skip Control RSMS Useful in framing for
38. 7 6 5 4 3 2 1 0 Name RSa6F 1 RSa6F3 RSa6F5 RSa6F7 RSa6F9 RSa6F11 RSa6F13 RSa6F15 Defaut 0 Bit 7 Bit of Frame 3 RSa6F3 Bit 6 Bit of Frame 4 RSa6F4 Bit 5 Bit of Frame 5 RSa6F5 Bit 4 Bit of Frame 7 RSa6F7 Bit 3 Sa6 Bit of Frame 9 RSa6F9 Bit 2 Bit of Frame 11 RSa6F11 Bit 1 Sa6 Bit of Frame 13 RSa6F13 Bit 0 Sa6 Bit of Frame 15 RSa6F15 283 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RSa7 Register Description Received Sa7 Bits Register Address CEh Bit 7 6 5 4 3 2 1 0 RSa7F1 Rsa7F3 RSa7F5 RSa7F 7 RSa7F9 RSa7F11 RSa7F13 RSa7F15 050 qn 4 9 9 us Bit 7 Sa7 Bit of Frame 1 RSa4F1 Bit 6 Sa7 Bit of Frame 3 RSa7F3 Bit 5 Sa7 Bit of Frame 5 RSa7F5 Bit 4 Sa7 Bit of Frame 7 RSa7F7 Bit 3 Sa7 Bit of Frame 9 RSa7F9 Bit 2 Sa7 Bit of Frame 11 RSa7F11 Bit 1 Sa7 Bit of Frame 13 RSa7F13 Bit 0 Sa7 Bit of Frame 15 RSa7F15 Register Name TR RSa8 Register Description Received Sa8 Bits Register Address CFh Bit 7 6 5 4 3 2 1 0 Name RSa8F1 RSa8F3 RSa8F5 RSa8F7 RSa8F9 RSa8F11 RSa8F13 RSa8F15 Default 0 Bit 7 Sa8 Bit of Frame 1 RSa8F 1 Bit 6 Sa8 Bit of Frame 3 RSa8F3 Bit 5 Sa8 Bit of Frame 5 RSa8F5 Bit 4 Sa8 Bit of Frame 7 RSa8F7 Bit 3 Sa8 Bit of Frame 9 RSa8F9 Bit 2 Sa8 Bit of Frame 11 RSa8F11 Bit 1 Sa8 Bit of Frame 13
39. HDLC X 86 LAPS Mapper SDRAM interface control ports Bit Error Rate Tester BERT and integrated T1 E1 J1 Transceiver The packet interface consists of a MII RMII Ethernet PHY interface The Ethernet interface can be configured for 10Mbit s or 100Mbit s service The DS33R11 encapsulates Ethernet traffic with HDLC or X 86 LAPS encoding to be transmitted over a T1 E1 or J1 line The T1 E1 J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the Ethernet ports Access is provided to the signals between the Serial port and the integrated T1 E1 J1 Transceiver The device includes a software selectable T1 E1 or J1 single chip transceiver SCT for short haul and long haul applications The transceiver is composed of an LIU framer and two additional HDLC controllers The transceiver is software compatible with the 052155 and DS2156 The LIU is composed of transmit and receive interfaces and a jitter attenuator The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used T1 waveform generation includes DSX 1 line build outs as well as CSU line build outs of 7 5dB 15dB and 22 5dB E1 waveform generation includes G 703 waveshapes for both 75Q coax and 1200 twisted cables The receive interface provides network termination and recovers clock and data from the network The receive sens
40. Reserved LI TPPSRL Reserved Transmit Errored Packet Insertion Finished Reserved Reserved gt Reserved gt Reserved SAPI High is not equal to LI TRX86SAPIH SAPI Low is not equal to LI TRX86SAPIL Control is not equal to LI TRX8C Address is not equal to LI TRX86A Reserved LI RX86S GL TRQIS lt Reserved gt lt Reserved gt lt Reserved gt Transmit Queue FIFO Overflowed Transmit Queue Overflow Transmit Queue for Connection Exceeded Low Threshold Transmit Queue for Connection Exceeded High Threshold lt Reserved gt LI TQCTLS lt Reserved gt Interrupt Pin lt Reserved gt lt Reserved gt Receive Queue FIFO Overflowed Receive Queue Overflow Receive Queue for Connection Exceeded Low Threshold Receive Queue for Connection Exceeded High Threshold SU QCRLS lt Reserved gt lt Reserved gt lt Reserved gt lt Reserved gt Performance Monitor Update Bit Error Detected Bit Error Count Out Of Synchronization gt lt INTO J IN GL BIS GL SIS GL LIS Interrupts from T1 E1 J1 Transceiver OoO 2 mNm o 5 o o o 2 mjo 5 o0 o A o1 o O m o o1o 49 of 344 DS33R11 Ethernet Mapper with Integrat
41. Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 010Eh Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 010Fh Bit 07 06 05 04 03 02 01 00 Name Reserved Reserve Reserved Reserved Reserved Reserved Reserved Reserved d Default 0 0 0 0 0 0 0 0 Note Addresses 10Ch through 10Fh must each be initialized with all 175 FFh for proper software mode operation 192 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description Reserved MAC Reserved Control Register Register Address 0110h indirect 0110h Bit 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0111h Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0112h Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0113h Bit 07 06 05 04 03 02 01 00 Name Reserved Reserve Reserved Reserved Reserved Reserved Reserved Reserved d Default 0 0 0 0 0 0 0 0 No
42. The Run Test Idle is used between scan operations or during specific tests The Instruction register and test registers will remain idle Select DR Scan All test registers retain their previous state With JTMS LOW a rising edge of JTCLK moves the controller into the Capture DR state and will initiate a scan sequence JTMS HIGH during a rising edge on JTCLK moves the controller to the Select IR Scan state Capture DR Data may be parallel loaded into the test data registers selected by the current instruction If the instruction does not call for a parallel load or the selected register does not allow parallel loads the test register will remain at its current value On the rising edge of JTCLK the controller will go to the Shift DR state if JTMS is LOW or it will go to the Exit1 DR state if JTMS is HIGH Shift DR The test data register selected by the current instruction is connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK If a test register selected by the current instruction is not placed in the serial path it will maintain its previous state Exit1 DR While in this state a rising edge on JTCLK will put the controller in the Update DR state which terminates the scanning process if JTMS is HIGH A rising edge on JTCLK with JTMS LOW will put the controller in the Pause DR state Pause DR Shifting of the test registers is halted while in this state All test regist
43. interrupts on rising and falling edges 220 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR4 Register Description Status Register 4 Register Address 1Ch Bit 7 6 5 4 3 2 1 0 Name RAIS CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7 Receive AIS CI Event RAIS CI T1 Only Set when the receiver detects the AIS CI pattern as defined in ANSI T1 403 Bit 6 Receive Signaling All Ones Event RSAO E1 Only Set when the contents of time slot 16 contains fewer than three Os over 16 consecutive frames This alarm is not disabled in the CCS signaling mode Bit 5 Receive Signaling All Zeros Event RSAZ E1 Only Set when over a full MF time slot 16 contains all Os Bit 4 Transmit Multiframe Event TMF E1 Mode Set every 2ms regardless if CRC4 is enabled on transmit multiframe boundaries Used to alert the host that signaling data needs to be updated T1 Mode Set every 1 5ms on D4 MF boundaries or every 3ms on ESF MF boundaries Bit 3 Transmit Align Frame Event TAF E1 Only Set every 250us at the beginning of align frames Used to alert the host that the TR TAF and TR TNAF registers need to be updated Bit 2 Receive Multiframe Event RMF E1 Mode Set every 2ms regardless if CAS signaling is enabled or not on receive multiframe boundaries Used to alert the host that signaling data is available T1 Mode Set every 1 5ms on D4 MF boundaries or eve
44. t2 RCLKI t3 t4 5 RSERI m RDEN E RBSYNC 321 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 7 SDRAM Timing Table 13 12 SDRAM Interface Timing Note 1 Figure 13 8 100 MHz PARAMETER SYMBOL MIN TYP MAX UNITS SDCLKO Period t1 9 7 10 10 3 ns SDCLKO Duty Cycle t2 4 6 ns SDCLKO to SDATA Valid 3 7 ns Write to SDRAM SDCLKO to SDATA Drive On 4 4 ns Write to SDRAM SDCLKO to SDATA Invalid 5 3 T Write to SDRAM SDCLKO to SDATA Drive Off 6 4 ae Write to SDRAM SDATA to SDCLKO Setup Time 7 2 n Read from SDRAM SDCLKO to SDATA Hold Time 8 2 Read from SDRAM SDCLKO to SRAS SCAS SWE SDCS Active 9 5 Read or Write to SDRAM SDCLKO TO SRAS SCAS SWE SDCS Inactive 2 ns Read or Write to SDRAM SDCLKO to SDA SBA Valid t11 7 is Read or Write to SDRAM SDCLKO TO SDA SBA Invalid H2 2 Read or write to SDRAM SDCLKO to SDMASK Valid 13 5 ns Read or write to SDRAM SDCLKO TO SDMASK Invalid 14 2 Read or write to SDRAM Note 1 Timing parameters in this table are guaranteed by design GBD 322 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 8 SDRAM Interface Timing SDCLKO output t5 lt gt SDATA OX 7y output AN Ao NU SDATA input SRAS SCAS SWE SDCS output SDA SBA output SDMASK output 323 of 344 DS33
45. udWwvHa 9 LINSNVUL 2 a X X 2 3IAISO3H nr LINSNVYL nr JAIHO3H X19dS MIOSASY ON T19Q NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED TYE 1 TANSCEIVER ARE DISCUSSED IN SECTION 10 1 44 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 1 4 Ethernet Interface Clock Modes The Ethernet PHY interface has several different clocking requirements depending on the mode of operation Table 9 1 outlines the possible clocking modes for the Ethernet Interface The buffered REF CLKO output is generated by division of the 100MHz system clock input by the user on SYSCLKI The frequency of the REF CLKO pin is automatically determined by the DS33R11 based on the state of the RMIIMIIS The REF CLKO function can be turned off with the GL CR1 RFOO bit Note that in DCE and RMII operating modes the REF CLKO signal should not be used to provide an input to REF due to the reset requirements in these operating modes In mode receive and transmit timing is always synchronous to 50 MHz clock input the REF CLK pin The source of REF is expected to be the external PHY The user has the option of using the 50MHz REF CLKO output as the timing source for the PHY More information RMII mode can be found in Section 9 15 2 While
46. 1 2 1 EIBO SBE RPL3 RPL2 RPL1 RPLO h TR BC2 OE2 E fo ie m u h Reserved 0 BBC7 BBC6 BBC5 BBC4 BBC3 BBC2 BBC1 BBCO h TR BBC1 0 4 BBC15 BBC14 BBC13 BBC12 BBC11 BBC10 BBC9 BBC8 h TR BBC2 0 5 BBC23 BBC22 BBC21 BBC20 BBC19 BBC18 BBC17 BBC16 h TR BBC3 0 6 BBC31 BBC30 BBC29 BBC28 BBC27 BBC26 BBC25 BBC24 h TR BBC4 0 7 EC6 EC5 EC4 EC3 EC2 EC1 ECO h TR BEC1 OE8 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 h TR BEC2 0 9 EC23 EC22 EC21 EC20 EC19 EC18 EC17 EC16 h TR BEC3 OEA RFUS TBAT TFUS BERTDIR BERTEN h TR BIC WNOE CE 2 ER1 ERO h TR ERC 0 C7 C6 C5 C4 C3 C2 C1 CO h TR NOE1 OED _ _ a ix C9 C8 h TR NOE2 OEE C7 C6 C5 C4 C3 C2 C1 CO h TR NOEL1 Es m C9 C8 h TR NOEL2 133 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 2 Global Register Definitions for Ethernet Mapper Functions contained in the global registers include framer reset LIU reset device ID and BERT interrupt status These registers are preserved to provide code compatibility with the multiport devices in this product family The global registers bit descriptions are presented below Register Name GL IDRL Register Description Global ID Low Register Register Address 00h Bit 7 6 5 4 3 2 1 0 Name 1207 1206 1005 1004 1203 1002 1001 1000 Default 0 0 1 1 0 0 0 0 Bit 7 ID07 Reserved
47. 100 mA Core Supply Current VDD1 8 1 89V IppcoRE Notes 1 2 30 mA Lead Capacitance Cio Note 3 7 pF li 10 10 Input Leakage A i 3 50 10 i Output Leakage when High Z lio 10 10 lou 4 0mA Vou All outputs 2 35 lo 4 VoL All outputs 0 75 tput Volt V 05 Vo REF CLKO 2 85 lo 12 0mA VoL TSERO 0 75 Vit 0 75 Input Volt V nput Voltage Vis 2 35 Note 1 Typical power consumption is approximately 400mW Note 2 All outputs loaded with rated capacitance all inputs between Vpp and Vss inputs with pullups connected to Vpp Note 3 Value guaranteed by design GBD 313 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 1 Thermal Characteristics Table 13 3 Thermal Characteristics PARAMETER MIN TYP MAX Ambient Temperature Note 1 40 C 85 C Junction Temperature Note 2 125 Theta JA 0 4 in Still Air for 256 Pin 5 27mm BGA Notes 2 3 nd Note 1 The package is mounted on a four layer JEDEC standard test board Note 2 Value guaranteed by design GBD Note 3 Theta JA 0 4 is the junction to ambient thermal resistance when the package is mounted on a four layer JEDEC standard test board Table 13 4 Theta JA vs Airflow THETA JA AIESEEQW 256 PIN 27mm BGA Om s Note 1 20 3 C W 1m s Note 1 17 9 C W 2 5m s Note 1 16 9 C W Note 1 Value guaranteed by design GBD 314 of 344 DS33R11 Et
48. 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 7 Software Signaling Insertion Enable for Channels 9 to 16 CH9 to CH16 These bits determine which channels are to have signaling inserted from the transmit signaling registers 0 7 do not source signaling data from the TR TSx registers for this channel 1 source signaling data from the TR TSx registers for this channel Register Name TR SSIE2 E1 Mode Register Description Software Signaling Insertion Enable 2 Register Address 09h Bit 7 6 5 4 3 2 1 0 Name CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Software Signaling Insertion Enable for Channels 8 to 15 CH8 to CH15 These bits determine which channels are to have signaling inserted from the transmit signaling registers 0 do not source signaling data from the TR TSx registers for this channel 1 source signaling data from the TR TSx registers for this channel 209 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SSIE3 T1 Mode Register Description Software Signaling Insertion Enable 3 Register Address 0Ah Bit 7 6 5 4 3 2 1 0 24 23 22 21 20 19 18 17 Default 0 0 0 0 0 0 0 0 Bits 0 7 Software Signaling Insertion Enable for Channels 17 to 24 CH17 to CH24 These bits determine which channels are to have signaling inse
49. ASTP When set to 1 all incoming frames with less than 46 byte length are automatically stripped of the pad characters and FCS Bits 6 7 Back Off Limit BOLMT 0 1 These two bits allow the user to set the back off limit used for the maximum retransmission delay for collided packets Default operation limits the maximum delay for retransmission to a countdown of 10 bits from a random number generator The user can reduce the maximum number of counter bits as described in the table below See IEEE 802 3 for details of the back off algorithm Bit 7 Bit6 Random Number Generator Bits Used 0 0 10 0 1 8 1 0 4 1 1 1 Bit 5 Deferral Check DC When set to 1 the MAC will abort packet transmission if it has deferred for more than 24 288 bit times The deferral counter starts when the transmitter is ready to transmit a packet but is prevented from transmission because CRS is active If the MAC begins transmission but a collision occurs after the beginning of transmission the deferral counter is reset again If this bit is equal to zero then the MAC will defer indefinitely Bit 3 Transmitter Enable TE When set to 1 packet transmission is enabled When equal to zero transmission is disabled Bit 2 Receiver Enable RE When set to 1 packet reception is enabled When equal to zero packets are not received 187 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register
50. Bit 7 6 5 4 3 2 1 0 Name TSa4F1 TSa4F3 TSa4F5 TSa4F7 TSa4F9 TSa4F11 TSa4F13 TSa4F15 Defaut 02 Ue c up qe Sp o Bit 7 Sa4 Bit of Frame 1 TSa4F1 Bit 6 Sa4 Bit of Frame 3 TSa4F3 Bit 5 Sa4 Bit of Frame 5 TSa4F5 Bit 4 Sa4 Bit of Frame 7 TSa4F7 Bit 3 Sa4 Bit of Frame 9 TSa4F9 Bit 2 Sa4 Bit of Frame 11 TSa4F11 Bit 1 Sa4 Bit of Frame 13 TSa4F13 Bit 0 Sa4 Bit of Frame 15 TSa4F15 287 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TSa5 Register Description Transmitted Sa5 Bits Register Address D6h Bit 7 6 5 4 3 2 1 0 TSa5F1 TSa5F3 TSa5F5 TSa5F7 TSa5F9 TSa5F11 TSa5F13 TSa5F15 Befaub 30 22 9r 4 07 90 0 pe i Bit 7 Sa5 Bit of Frame 1 TSa5F1 Bit 6 Sa5 Bit of Frame 3 TSa5F3 Bit 5 Sa5 Bit of Frame 5 TSa5F5 Bit 4 Sa5 Bit of Frame 7 TSa5F7 Bit 3 Sa5 Bit of Frame 9 TSa5F9 Bit 2 Sa5 Bit of Frame 11 TSa5F11 Bit 1 Sa5 Bit of Frame 13 TSa5F13 Bit 0 Sa5 Bit of Frame 15 TSa5F15 Register Name TR TSa6 Register Description Transmit Sa6 Bits Register Address D7h Bit 7 6 5 4 3 2 1 0 Name TSa6F1 TSa6F3 TSa6F5 TSa6F7 TSa6F9 TSa6F11 TSa6F13 TSa6F15 Defaults 02 gp sor c s 1 Bit 7 Bit of Frame 1 TSa6F1 Bit 6 Sa6 Bit of Frame 3 TSa6F3 Bit 5 Sa6 Bit of Frame 5 TSa6F5 Bit 4 Bit of
51. Bit 1 Transmit Open Circuit Detect Condition TOCD Set when the device detects that the TTIP and TRING outputs are open circuited This is a double interrupt bit Section 9 7 Bit 0 Loss of Line Interface Transmit Clock Condition LOLITC Set when TDCLKI has not transitioned for one channel time This is a double interrupt bit Section 9 7 215 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR1 Register Description Interrupt Mask Register 1 Register Address 17h Bit 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Defaut 0 0 0 0 0 O 0 0 Bit 7 Input Level Under Threshold 0 interrupt masked 1 interrupt enabled Bit 6 Timer Event TIMER 0 interrupt masked 1 interrupt enabled Bit 5 Receive Signaling Change of State Event RSCOS 0 interrupt masked 1 7 interrupt enabled Bit 4 Jitter Attenuator Limit Trip Event JALT 0 interrupt masked 1 interrupt enabled Bit 3 Line Interface Receive Carrier Loss Condition LRCL 0 interrupt masked 1 interrupt enabled generates interrupts on rising and falling edges Bit 2 Transmit Current Limit Exceeded Condition TCLE 0 interrupt masked 1 interrupt enabled generates interrupts on rising and falling edges Bit 1 Transmit Open Circuit Detect Condition TOCD 0 interrupt masked 1 7 interrupt enabled generates interrupts on rising and falling edges Bit 0
52. JTAG Reset 2 for the T1 E1 J1 Transceiver 5 2 is used to asynchronously reset the test access port controller After power JIRSI2 B8 Ipu up JTRST2 must be toggled from low to high This action will set the device into the JTAG DEVICE ID mode Normal device operation is restored by pulling JTRST2 low JTRST2 is pulled HIGH internally via a 10kO resistor operation 38 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION POWER SUPPLIES RVDD K3 L1 Receive Analog Positive Supply Connect to 3 3V power supply RVSS J1 J2 K2 L2 M2 Receive Analog Signal Ground Connect to the common supply ground TVDD U1 Transmit Analog Positive Supply Connect to 3 3V power supply TVSS P1 R3 T3 U2 Transmit Analog Signal Ground Connect to the common supply ground DVDD D1 D17 E17 Digital Positive Supply Connect to 3 3V power supply DVSS N4 P4 R4 T4 Digital Signal Ground Connect to the common supply ground VDD1 8 B10 B15 C12 F3 J18 J20 P18 P19 R19 R20 V9 Y9 Y13 VDD1 8 Connect to 1 8V power supply VDD3 D20 F17 G17 G18 H17 J17 K17 L17 M17 N17 VDD3 3 Connect to 3 3V power supply VSS VSS Connect to the common supply ground N C 9 D6 No Connection Do not connect these pins Leave these pins open 39
53. RSa8F13 Bit 0 Sa8 Bit of Frame 15 RSa8F15 284 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TAF Register Description Transmit Align Frame Register Register Address DOh Bit 7 6 5 4 3 2 Name Si 0 0 1 1 0 Default Bit 7 International Bit Si Bit 6 Frame Alignment Signal Bit 0 Bit 5 Frame Alignment Signal Bit 0 Bit 4 Frame Alignment Signal Bit 1 Bit 3 Frame Alignment Signal Bit 1 Bit 2 Frame Alignment Signal Bit 0 Bit 1 Frame Alignment Signal Bit 1 Bit 0 Frame Alignment Signal Bit 1 Register Name TR TNAF Register Description Transmit Nonalign Frame Register Register Address D1h Bit 7 6 5 4 3 2 1 0 Si 1 A Sa4 Sa5 Sa6 Sa Sa8 Default Bit 7 International Bit Si Bit 6 Frame Nonalignment Signal Bit 1 Bit 5 Remote Alarm used to transmit the alarm A Bit 4 Additional Bit 4 Sa4 Bit 3 Additional Bit 5 Sa5 Bit 2 Additional Bit 6 Sa6 Bit 1 Additional Bit 7 Sa7 Bit 0 Additional Bit 8 Sa8 285 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TSiAF Register Description Transmit Si Bits of the Align Frame Register Address D2h Bit 7 6 5 4 3 2 1 0 Name TSiFO TSiF2 TSiF4 TSiF6G TSiF8 TSiF10 TSiF12 TSiF14 Befau 0 ege 40 0 Bit 7 Si Bit of Frame 0 TSiFO Bit 6 Si Bit of Frame 2 TSiF2 Bit 5
54. TR IOCR1 2 0 AND DOUBLE WIDE FRAME SYNC IS NOT ENABLED TR IOCR1 1 0 NOTE 2 TSYNC IN THE FRAME MODE TR IOCR1 2 0 AND DOUBLE MDE FRAME SYNC IS ENABLED TR IOCR1 1 1 NOTE 3 TSYNC IN THE MULTIFRAME MODE TR IOCR1 2 1 305 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 16 Transmit Side ESF Timing FRAME TSYNC TSSYNC TSYNC TSYNC NOTE 1 TSYNC IN FRAME MODE TR IOCR1 2 0 AND DOUBLE WIDE FRAME SYNC IS NOT ENABLED TR IOCRL3 0 NOTE 2 TSYNC IN FRAME MODE TR IOCR1 2 0 AND DOUBLE WDE FRAME SYNC IS ENABLED TR IOCR1 3 1 NOTE 3 TSYNC IN MULTIFRAME MODE 12 1 Figure 12 17 Transmit Side Boundary Timing with Elastic Store Disabled TCLKT CHANNEL 1 CHANNEL 2 TSERI LSBX J 1 JSBMSB JLSB MSB D TSYNC TSYNC CHANNEL 1 CHANNEL 2 Tsic K K YaB c vs y TCHCLK TCHBLK NOTE 1 TSYNC IS IN THE OUTPUT MODE TR IOCR1 1 1 NOTE 2 TSYNC IS IN THE INPUT MODE TR JOCR1 1 0 NOTE 3 TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2 306 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 18 Transmit Side 1 544MHz Boundary Timing Elastic Store
55. TXBYTEOK12 TXBYTEOK11 TXBYTEOK10 TXBYTEOK9 TXBYTEOK8 Default 0 0 0 0 0 0 0 0 030Fh Bit 07 06 05 04 03 02 01 00 Name TXBYTEOK7 TXBYTEOK6 TXBYTEOK4 TXBYTEOK3 TXBYTEOK2 TXBYTEOK1 TXBYTEOKO Default 0 0 0 0 0 0 0 0 Bits 0 31 Bytes Transmitted OK Counter TXBYTEOK 0 31 32 bit value indicating the number of bytes transmitted and determined to be valid Each time a valid byte is transmitted this counter is incremented by 1 This counter resets only upon device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2 32 1 times at the maximum frame rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 198 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description SU TxFrmUndr MAC Transmit Frame Under Run Counter Register Address 0334h indirect 0334h Bit 31 30 29 28 27 26 25 24 Name TXFRMUS1 TXFRMU30 TXFRMU29 TXFRMU28 TXFRMU27 TXFRMU26 TXFRMU25 TXFRMU24 Default 0 0 0 0 0 0 0 0 0335h Bit 23 22 21 20 19 18 17 16 Name TXFRMU23 TXFRMU22 TXFRMU21 TXFRMU
56. Timing parameters in this table are guaranteed by design GBD Note 2 Jitter attenuator enabled in the receive path Note 3 Jitter attenuator disabled or enabled in the transmit path Note 4 RSYSCLK 1 544MHz Note 5 RSYSCLK 2 048MHz 327 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 13 Receive Side Timing RCLKO 4 RSERO RDATA RSIG X X 1ST FRAME BIT tpo gt RSYNC ibo lt RFSYNC RMSYNC gt 402 RCHCLK 2 RCHBLK NOTE 1 RSYNC IS IN THE OUTPUT MODE NOTE 2 NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED 328 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 14 Receive Side Timing Elastic Store Enabled tR gt RSYSCLK gt RSERO RSIG SEE NOTE 3 gt RCHCLK gt RCHBLK 4 4 tp4 gt gt tsu 4 RMSYNC RSYNC 2 RSYNC NOTE 1 RSYNC IS IN THE OUTPUT MODE NOTE 2 RSYNC IS IN THE INPUT MODE NOTE F BIT WHEN MSTRREG 1 0 MSB OF TSO WHEN MSTREG 1 1 329 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 15 Receive Line Interface Timing RDCLKO j RPOSO RNEGO Ir gt tp RDCLKI RPOSI RNEGI 330 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 10 AC Characteristics Backplane Clock Timing Table 13 15 AC Charact
57. When this bit is set to a 1 and TR LIC1 5 TR LIC1 6 TR LIC1 7 0 the device generates a square wave at the TTIP and TRING outputs instead of a normal waveform When this bit is set to a 1 and TR LIC1 5 TR LIC1 6 TR LIC1 7 z 0 the device forces TTIP and TRING outputs to become open drain drivers instead of their normal push pull operation This bit should be set to 0 for normal operation of the device 257 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR LIC3 Register Description Line Interface Control 3 Register Address 7Ah Bit 7 6 5 4 3 2 1 0 Name TCES RCES MM1 MMO RSCLKE TSCLKE TAOZ Defaut 0o 0 o o o j o 0 j 0 Bit 6 Transmit Clock Edge Select TCES Selects which TDCLKI edge to sample TPOSI and TNEGI 0 sample TPOSI and on falling edge of TDCLKI 1 sample TPOSI and on rising edge of TDCLKI Bit 5 Receive Clock Edge Select RCES Selects which RDCLKO edge to update RPOSO and RNEGO 0 update RPOSO and RNEGO on rising edge of RDCLKO 1 update RPOSO and RNEGO on falling edge of RDCLKO Bits 3 4 Monitor Mode 0 to MM1 MM1 MMO Internal Linear Gain Boost dB 0 0 Normal operation no boost 0 1 20 1 0 26 1 1 32 Bit 2 Receive Synchronization G 703 Clock Enable RSCLKE 0 disable 1 544MHz T1 2 048MHz E1 synchronization receive mode 1 enable 1 544MHz T1 2 048MHz E1 synchronizat
58. generate an interrupt Register Name LI TQLT Register Description Serial Interface Transmit Queue Low Threshold Watermark Register Address 124h Bit 7 6 5 4 3 2 1 0 Name TQLT7 TQLT6 TQLT5 TQLT4 TQLT3 TQLT2 TQLT1 TQLTO Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Queue Low Threshold TQLT 0 7 The transmit queue low threshold for the connection in increments of 32 packets of 2048 bytes each The value of this register is multiplied by 32 2048 bytes to determine the byte location of the threshold Note that the transmit queue is for data that was received from the Serial Interface to be sent to the Ethernet Interface Register Name LI TQHT Register Description Serial Interface Transmit Queue High Threshold Watermark Register Address 125h Bit 7 6 5 4 3 2 1 0 TQHT6 TQHTS TQHT4 TQHT3 TQHT2 1 TQHTO Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Queue High Threshold TQHT 0 7 The transmit queue high threshold for the connection in increments of 32 packets of 2048 bytes each The value of this register is multiplied by 32 2048 bytes to determine the byte location of the threshold Note that the transmit queue is for data that was received from the Serial Interface to be sent to the Ethernet Interface 172 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description LI TQ
59. nr LIINSNVS L JAI3O3H nr Ov Ll ous v olisviNas ce olv1vas L 0 vas 3MS SVOS SYYS IS 1 TRANSCEIVER z n ce 5 a O 5 3 g 2 3 E a gt 5 z E a 2 ftg 556 bat 20 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 6 2 Block Diagram of T1 E1 J1 Transceiver EXTERNAL ACCESS TO RECEIVE SIGNALS A tl HDB3 B8ZS BACKPLANE T CLOCK SYNTH SINGALING ALARM DET HDLCs Y Y Y BACKPLANE INTERFACE CIRCUIT FRAMER SINGALING ALARM GEN HDLCs CRC GEN 1 HDB3 875 BACKPLANE INTERFACE NETWORK 72 lt JITTER ATTENUATOR BACKPLANE LOCALLOOPBACK PAYLOAD LOOPBACK REMOTE LOOPBACK FRAMER LOOPBACK 4 HOST INTERFACE 21 0 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 6 3 Receive and Transmit T1 E1 J1 LIU ONIOQW VCO PLL 32 768MHz 3 1 ANIM gt TNEG gt gt TPOS HlVd 3AIHO3H HO 2 fm m lt m 2 2 LINSNVYL
60. te pvss VDD3 VDD3 001 8 T TRING TRING TVSS DVSS vop3 voos SDATA U RMSYNC vss vss vss vss vss vss vss vss vss vss vss vss vss voos vss DATA y sData spaa spata SDATA SDATA SATA SDMASK ssi vanta SBA SDA spa spa SDMASK suai spata SDATA vss w SDATA SDATA SDATA SDATA SDATA SDATA oves Cane SDA SDA SpA SpA SDA SDATA SDATA vss SDATA SDATA y vss soata d SEEN etre SpA SDA soa SDA SDATA sData SDATA SDATA 40 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 8 FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet packet LANs and T1 E1 J1 WAN Time Division Multiplexed TDM systems The device is composed of a 10 100 Ethernet MAC packet arbiter committed information rate controller CIR HDLC X 86 LAPS mapper SDRAM interface control ports bit error rate tester BERT and integrated T1 E1 J1 transceiver The packet interface consists of a MII RMII Ethernet PHY interface The Ethernet interface can be configured for 10Mbit s or 100Mbit s service The DS33R11 encapsulates Ethernet traffic with HDLC or X 86 LAPS encoding to be transmitted over a T1 E1 or J1 line The T1 E1 J1 interface also receives encapsulated Ethernet packets and transmits the extracted pac
61. 0 0 0 0 Bits 0 7 Transmit Byte Count TBC 31 24 These thirty two bits indicate the number of packet bytes inserted in the outgoing data stream Register Name Register Description LI TMEI Transmit Manual Error Insertion Register Address 0D4h Bit 7 6 5 4 3 2 1 0 Name TMEI Default 0 0 0 0 0 0 0 0 Bit 0 Transmit Manual Error Insertion TMEI A zero to one transition will insert a single error in the Transmit direction 157 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver LI THPMUU Serial Interface Transmit HDLC PMU Update Register Register Name Register Description Register Address 0D6h Bit 7 6 5 4 3 2 0 Name TPMUU Default 0 0 0 0 0 0 0 Bit 0 Transmit PMU Update TPMUU This signal causes the transmit cell packet processor block performance monitoring registers counters to be updated A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data and the counters reset 0 or 1 This update updates performance monitoring counters for the Serial Interface LI THPMUS Serial Interface Transmit HDLC PMU Update Status Register Register Name Register Description Register Address 0D7h Bit 7 6 5 4 3 2 0 TPMUS Default 0 0 0 0 0 0 0 Bit 0
62. 1 TCM1 0 RCM1 1 TCMO 1 RCMO 0 81 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 9 Signaling Operation There are two methods to access receive signaling data and provide transmit signaling data processor based software based or hardware based Processor based refers to access through the transmit and receive signaling registers R81 RS16 and 51 516 Hardware based refers to the TSIG and RSIG pins Both methods can be used simultaneously Figure 10 2 Simplified Diagram of Receive Signaling Path PER CHANNEL CONTROL T1 E1 DATA STREAM Y e gt Y SIGNALING EXTRACTION ALL ONES gt Ei RECEIVE SIGNALING REINSERTION REGISTERS CONTROL gt SIGNALING CHANGE OF STATE BUFFERS INDICATION REGISTERS 10 9 1 Processor Based Receive Signaling The robbed bit signaling T1 or TS16 CAS signaling E1 is sampled in the receive data stream and copied into the receive signaling registers RS1 RS16 In T1 mode only RS1 RS12 are used The signaling information in these registers is always updated on multiframe boundaries This function is always enabled 10 9 1 1 Change of State To avoid constant monitoring of the receive signaling registers the transceiver can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state TR RSCSE1 TR RSCSE4 for E1 and TR RSCSE1 TR RSCSES3 for T1 are used to sele
63. 1 0 Name REPC7 REPC6 REPC5 REPC4 REPC3 REPC2 REPC1 REPCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive FCS Errored Packet Count RFPC 7 0 Eight bits of a 24 bit value Register description below Register Name Register Description LI RFPCB1 Receive FCS Errored Packet Count Byte 1 Register Register Address 10Dh Bit 7 6 5 4 3 2 1 0 Name 15 RFPC14 RFPC13 RFPC12 RFPC11 RFPC10 RFPC9 RFPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive FCS Errored Packet Count RFPC 15 8 Eight bits of a 24 bit value Register description below Register Name Register Description LI RFPCB2 Receive FCS Errored Packet Count Byte 2 Register Register Address 10Eh Bit 7 6 5 4 3 2 1 0 Name REPC23 REPC22 REPC21 REPC20 REPC19 REPC18 REPC17 REPC16 Default 0 0 0 0 0 0 0 0 Receive FCS Errored Packet Count RFPC 23 16 These twenty four bits indicate the number of packets received with an FCS error The byte count for these packets is included in the receive aborted byte count register REBCR 166 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RAPCBO Register Description Receive Aborted Packet Count Byte 0 Register Register Address 110h Bit 7 6 5 4 3 2 1 0 Name RAPC7 RAPC6 5 4 2 RAPC1 RAPCO Default 0 0 0 0 0 0 0 0
64. 13 7 317 Table 12 5 Receive oe nae a M es 318 Table 12 9 IDI ieee ac eoe Ir RETRO PEE ERE HR 319 Table 12 10 Transmit 320 Table 12 1 Receive WAN 321 Table SUR AM i eee eq DI PRA EERRE RO EE EX Rat up er pe URP Qr SH T 322 Table 13 13 AC Characteristics Microprocessor Bus TImilld u 324 Table 13 14 AC Characteristics Receive Side 327 Table 13 15 AC Characteristics Backplane Clock Synthesis 331 Table 12 16 AG Characteristics Transmit Side 332 s ad Rc URP 335 Table 14 1 Instruction Codes for IEEE 1149 1 recien art e env noo Rp ene eot 340 Table T42 IB Code Smc Mem 341 8 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 1 DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1 E1 J1 WAN Time Division Multiplexed TDM systems The device is composed of a 10 100 Ethernet MAC Packet Arbiter Committed Information Rate Controller CIR
65. 2 9 5 Per Port Resources Multiport devices in this product family share a common set of global registers BERT and arbiter All other resources are per port 47 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 6 Device Interrupts Figure 9 2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin When an interrupt occurs the host can read the Global Latched Status registers GL LIS GL SIS GL BIS and GL TROIS to initially determine the source of the interrupt further identify the source of the interrupt s In order to maintain software compatibility with the multiport devices in the product family the global interrupt status and interrupt enable registers have been preserved but do not need to be used If GL TRQIS is determined to be the interrupt source the host will then read the LI TPPSRL and LI RPPSRL registers for the cause of the interrupt If GL LIS is determined to be the interrupt source the host will then read the LI TQCTLS LI TPPSRL LI RPPSRL and LI RX86S registers for the source of the interrupt If GL SIS is the source the host will then read the SU QCRLS register for the source of the interrupt If GL BIS is the source the host will then read the BSRL register for the source of the interrupt All Global Interrupt Status Register bits are real time bits that will clear once the app
66. 217 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR2 Register Description Interrupt Mask Register 2 Register Address 19h Bit 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7 Receive Yellow Alarm Clear Event RYELC 0 interrupt masked 1 interrupt enabled Bit 6 Receive Unframed All Ones Condition Clear Event RUA1C 0 interrupt masked 1 interrupt enabled Bit 5 Framer Receive Carrier Loss Condition Clear FRCLC 0 interrupt masked 1 interrupt enabled Bit 4 Receive Loss of Sync Clear Event RLOSC 0 interrupt masked 1 interrupt enabled Bit 3 Receive Yellow Alarm Condition RYEL 0 interrupt masked 1 interrupt enabled interrupts on rising edge only Bit 2 Receive Unframed All Ones Blue Alarm Condition RUA1 0 interrupt masked 1 interrupt enabled interrupts on rising edge only Bit 1 Framer Receive Carrier Loss Condition FRCL 0 interrupt masked 1 interrupt enabled interrupts on rising edge only Bit 0 Receive Loss of Sync Condition RLOS 0 interrupt masked 1 interrupt enabled interrupts on rising edge only 218 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR3 Register Description Status Register 3 Register Address 1Ah Bit 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0
67. 4 2 and 4 3 2 Valid MF alignment word found and previous time slot Two consecutive MF alignment 16 contains code other than words received in error all 05 76 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 5 1 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm When automatic AIS generation is enabled TR E1TCR2 1 1 the device monitors the receive side framer to determine if any of the following conditions are present loss of receive frame synchronization AIS alarm all ones reception or loss of receive carrier or signal The framer forces either an AIS or remote alarm if any one or more of these conditions is present When automatic RAI generation is enabled TR E1TCR2 0 1 the framer monitors the receive side to determine if any of the following conditions are present loss of receive frame synchronization AIS alarm all ones reception loss of receive carrier or signal or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization if CRC4 is enabled If any one or more of these conditions is present then the framer transmits an RAI alarm RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted if the device cannot find CRC4 multiframe synchronization within 400ms as per G 706 Note It is an invalid state to have both automatic AIS generation and automatic remote alarm gene
68. 5 e6 7 l8 9 10 t1 12 13 14 15 16 RFSYNC RSYNC 1 RSYNC NOTE 1 RSYNC IN FRAME MODE TR IOCRL5 0 NOTE 2 RSYNC IN MULTIFRAME MODE TR IOCR1L5 1 NOTE THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME Figure 12 21 Receive Side Boundary Timing with Elastic Store Disabled RCLKO CHANNEL 32 CHANNEL 1 CHANNEL 2 RSERO 158 Si 1 A Sa4 5 5 5 7 5 8 RSYNC RFSYNC CHANNEL 32 E CHANNEL 2 RSIG A BX CAD AB RCHCLK RCHBLK NOTE 1 RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1 NOTE 2 SHOWN IS A RNAF FRAME BOUNDARY NOTE 3 RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE 0000 IN CHANNEL 1 308 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 22 Receive Side Boundary Timing RSYSCLK 1 544MHz E Store Enabled rsyselk LT LT LE LT CHANNEL 23 31 CHANNEL 24 32 CHANNEL 1 2 LSB MSB A A LSB MSB RCHCLK RCHBLK NOTE 1 DATA FROMTHE E1 CHANNELS 1 5 9 13 17 21 25 AND 2915 DROPPED CHANNEL 2 FROM THE E1 LINK IS MAPPEDTO CHANNEL 1
69. 9 7 Bit 0 Receive Remote Alarm Condition RRA E1 Only Set when a remote alarm is received at RPOSI and RNEGI This is a double interrupt bit See Section 9 7 219 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR3 Register Description Interrupt Mask Register 3 Register Address 1Bh Bit 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 7 Spare Code Detected Condition LSPARE 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 6 Loop Down Code Detected Condition LDN 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 5 Loop Up Code Detected Condition LUP 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 4 Loss of Transmit Clock Condition LOTC 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 3 Loss of Receive Clock Condition LORC 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 2 V5 2 Link Detected Condition V52LNK 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 1 Receive Distant MF Alarm Condition RDMA 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 0 Receive Remote Alarm Condition RRA 0 interrupt masked 1 interrupt enabled
70. Bits 0 7 Receive Down Code Definition Bits 0 7 C0 C7 A don t care if a 1 bit to 7 bit length is selected 275 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RSCC Register Description In Band Receive Spare Control Register Register Address BDh Bit 7 6 5 4 3 2 1 0 Name RSC2 RSC1 RSCO Defau i 82 0 Bits 3 7 Unused must be set to 0 for proper operation Bits 0 2 Receive Spare Code Length Definition Bits RSCO to RSC2 RSC2 RSC1 RSCO Length Selected bits gt On BR o h gt lt lt 276 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RSCD1 Register Description Receive Spare Code Definition Register 1 Register Address BEh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Default Note Writing this register resets the detector s integration period Bit 7 Receive Spare Code Definition Bit 7 C7 First bit of the repeating pattern Bit 6 Receive Spare Code Definition Bit 6 C6 A don t care if a 1 bit length is selected Bit 5 Receive Spare Code Definition Bit 5 C5 A don t care if a 1 bit or 2 bit length is selected Bit 4 Receive Spare Code Definition Bit 4 C4 A don t care if a 1 bit to 3 bit length is selected Bit 3 Receive Spare Code Definition Bit 3 C
71. Boundary Timing Elastic Store 307 era UNV Mec CT 308 Receive Side Boundary Timing with Elastic Store 308 Receive Side Boundary Timing RSYSCLK 1 544MHz E Store 309 Receive Side Boundary Timing RSYSCLK 2 048MHz E Store 309 E1 Mode OMY c 310 use 310 Transmit Side Boundary Timing Elastic Store Disabled sse 311 Transmit Side Boundary Timing TSYSCLK 1 544MHz Elastic Store Enabled 311 Transmit Side Boundary Timing TSYSCLK 2 048MHz Elastic Store Enabled 312 Hc ons usi MISC TS TET 315 Receive MII interlace TIMING SO 316 Transmit RMI Interface m 317 Receive RMII Interiace ME QUT 318 ESPERTO SUUS UT 319 Transmit 320 Receive WAN Interface UTE SS 321 SDRAN Menace TNO T E 323 intel Bus Read Timing MODEC Q 0 oin ptt pie rh erbe tiu ibas aa inada 325 Write Timing MODEC QO 325 Motorola Bus Read Timing DT Y e
72. C1 CO h TR RUPCD1 C7 C6 C5 C4 C3 C2 C1 CO h TR RUPCD2 0 C7 C6 C5 C4 C3 C2 C1 CO h TR RDNCD1 OBC C7 C6 C5 C4 C3 C2 C1 CO h TR RDNCD2 0BD RSC2 RSC1 RSCO h TR RSCC OBE C7 C6 C5 C4 C3 C2 C1 CO h TR RSCD1 OBF C7 C6 C5 C4 C3 C2 C1 CO h TR RSCD2 0CO Bit Definitions Change With BOCC Setting See Register Definition h TR RFDL 131 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADD NAME Bit 7 BIT 6 5 4 3 2 Bit 1 0 R 0 1 TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDLO h TR TFDL 0 2 RFDLM7 RFDLM6 RFDLM5 RFDLM4 RFDLM3 RFDLM2 RFDLM1 RFDLMO h TR RFDLM1 0 3 RFDLM7 RFDLM6 RFDLM5 RFDLMA RFDLM3 RFDLM2 RFDLM1 RFDLMO h TR RFDLM2 0C3 5i _ n m p h Reserved 0C5 _ _ Nu u _ h Reserved 0 6 0 0 1 1 0 1 1 TR RAF 0 7 1 Sa4 5 Sa7 Sa8 h TR RNAF 0C8 SiFO SiF2 SiF4 SiF6 SiF8 SiF10 SiF12 SiF14 h TR RSiAF 0C9 p SiF1 SiF3 SiF5 SiF7 SiF9 SiF11 SiF13 SiF15 h TR RSiNAF 0CA RRAF1 RRAF3 RRAF5 RRAF7 RRAF9 RRAF11 RRAF13 RRAF15 h TR RRA 0 RSa4F1 RSa4F3 RSa4F5 RSa4F7 RSa4F9 RSa4F11 RSa4F 13 RSa4F 15 h TR RSa4 0 RSa5F1 RSa5F3 RSa5F5 RSa5F7 RSa5F9 RSa5F11 RSa5F13 RSa5F 15 h TR RSa5 0CD RSa6F1 RSa6F3 RSa6F5 RSa6F7 RSa6F9 RSa6F 11 RSa6F 13 RSa6F 15 h TR RSa6 0 RSa7F1 RSa
73. Description E1 Receive Control Register 1 Register Address 33h Bit 7 6 5 4 3 2 1 0 Name RSERC RSIGM RHDB3 RG802 RCRC4 FRC SYNCE RESYNC Default 0 0 0 0 0 0 0 0 Bit 7 RSERO Control RSERC 0 allow RSERO to output data as received under all conditions 1 force RSERO to 1 under loss of frame alignment conditions Bit 6 Receive Signaling Mode Select RSIGM 0 CAS signaling mode 1 CCS signaling mode Bit 5 Receive HDB3 Enable RHDB3 0 HDB3 disabled 1 HDB3 enabled Bit 4 Receive G 802 Enable RG802 See Section 10 10 for details 0 do not force RCHBLK high during bit 1 of time slot 26 1 force RCHBLK high during bit 1 of time slot 26 Bit 3 Receive CRC4 Enable RCRC4 0 CRCA disabled 1 CRC4 enabled Bit 2 Frame Resync Criteria FRC 0 resync if FAS received in error three consecutive times 1 resync if FAS or bit 2 of non FAS is received in error three consecutive times Bit 1 Sync Enable SYNCE 0 auto resync enabled 1 auto resync disabled Bit 0 Resync RESYNC When toggled from low to high a resync is initiated Must be cleared and set again for a subsequent resync Register Name TR E1RCR2 Register Description E1 Receive Control Register 2 Register Address 34h Bit 7 6 5 4 3 2 1 0 Name RCLA Default 0 0 0 0 0 0 0 0 Bit 0 Receive Carrier Loss RCL Alternate Criteria RCLA Defines the criteria for a receive carrier loss conditi
74. FL6 FL5 FLA FL3 FL2 FL1 FIO 155h SU RFSB1 RF WT FL13 FL12 FL11 FL10 FL9 FI8 156h SU RFSB2 a CRCE DB MIIE FT cs FTL 157h SU RFSB3 MF UF CF LE 158h SU RMFSRL RMPS7 RMPS6 RMPS5 RMPS4 RMPS3 RMPS2 RMPS1 RMPSO 159h SU RMFSRH RMPS15 RMPS14 RMPS13 RMPS12 RMPS11 RMPS10 RMPS09 RMPSO08 15Ah SU RQLT RQLT7 RQLT6 RQLT5 RQLT4 RQLT3 RQLT2 RQLT1 RQLTO 15Bh SU RQHT RQHT7 RQHT6 RQHT5 RQHT4 RQHT3 RQHT2 RQHT1 RQHTO 15Ch SU QRIE gt RFOVFIE RQVFIE RQLTIE RQHTIE 15Dh SU QCRLS E RFOVFLS RQOVFLS RQHTLS RQLTLS 15Eh SU RFRC UCFR CFRR LERR CRCERR DBR MIIER BFR Note 15Fh 17Fh are reserved 122 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 1 6 MAC Register Bit Map Table 11 7 MAC Indirect Register Bit Map ADDR NAME Bir 7 Bir 6 5 Bit 4 3 2 1 0000h et Reserved Reserved Reserved HDB PS Reserved Reserved Reserved 0001h 23 16 DRO OML1 OMLO F PM PAM Reserved Reserved 0002h 15 8 Reserved Reserved Reserved LCC Reserved DRTY Reserved ASTP 0003h 7 0 BOLMT1 BOLMTO DC Reserved TE RE Reserved Reserved 0004h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0005h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0006h Reserved Reserved Reserved Reserv
75. Frame 7 TSa6F7 Bit 3 Sa6 Bit of Frame 9 TSa6F9 Bit 2 Bit of Frame 11 TSa6F11 Bit 1 Sa6 Bit of Frame 13 TSa6F13 Bit 0 Sa6 Bit of Frame 15 TSa6F15 288 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TSa7 Register Description Transmit Sa7 Bits Register Address D8h Bit 7 6 5 4 3 2 1 0 TSa7F1 TSa7F3 TSa7F5 TSa7F7 TSa7F9 TSa7F11 TSa7F13 TSa7F15 Beraut 0 gr Bit 7 Sa7 Bit of Frame 1 TSa4F1 Bit 6 Sa7 Bit of Frame 3 TSa7F3 Bit 5 Sa7 Bit of Frame 5 TSa7F5 Bit 4 Sa7 Bit of Frame 7 TSa7F7 Bit 3 Sa7 Bit of Frame 9 TSa7F9 Bit 2 Sa7 Bit of Frame 11 TSa7F11 Bit 1 Sa7 Bit of Frame 13 TSa7F13 Bit 0 Sa7 Bit of Frame 15 TSa7F15 Register Name TR TSa8 Register Description Transmit Sa8 Bits Register Address D9h Bit 7 6 5 4 3 2 1 0 Name TSa8F1 TSa8F3 TSa8F5 TSa8F7 TSa8F9 TSa8F11 TSa8F13 5 8 15 Defaut 0 0 0 0 0 O 0 0 Bit 7 Sa8 Bit of Frame 1 TSa8F1 Bit 6 Sa8 Bit of Frame 3 TSa8F3 Bit 5 Sa8 Bit of Frame 5 TSa8F5 Bit 4 Sa8 Bit of Frame 7 TSa8F7 Bit 3 Sa8 Bit of Frame 9 TSa8F9 Bit 2 Sa8 Bit of Frame 11 TSa8F11 Bit 1 Sa8 Bit of Frame 13 TSa8F13 Bit 0 Sa8 Bit of Frame 15 TSa8F15 289 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TSACR Register Description Transmit Sa Bit Control Register Regis
76. H2RCS4 Register Description HDLC 1 Receive Channel Select HDLC 2 Receive Channel Select Register Address 92h 93h 94h 95h A2h A3h A4h A5h Bit 7 6 5 4 3 2 1 0 Name RHCS7 RHCS6 RHCS5 RHCS4 RHCS3 RHCS2 RHCS1 RHCSO Default 0 Bit 7 Receive HDLC Channel Select Bit 7 RHCS7 Select Channel 8 16 24 or 32 Bit 6 Receive HDLC Channel Select Bit 6 RHCS6 Select Channel 7 15 23 or 31 Bit 5 Receive HDLC Channel Select Bit 5 RHCS5 Select Channel 6 14 22 or 30 Bit 4 Receive HDLC Channel Select Bit 4 RHCS4 Select Channel 5 13 21 or 29 Bit 3 Receive HDLC Channel Select Bit 3 RHCS3 Select Channel 4 12 20 or 28 Bit 2 Receive HDLC Channel Select Bit 2 RHCS2 Select Channel 3 11 19 or 27 Bit 1 Receive HDLC Channel Select Bit 1 RHCS1 Select Channel 2 10 18 or 26 Bit 0 Receive HDLC Channel Select Bit 0 RHCSO Select Channel 1 9 17 or 25 267 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1RTSBS TR H2RTSBS Register Description HDLC 1 Receive Time Slot Bits Sa Bits Select HDLC 2 Receive Time Slot Bits Sa Bits Select Register Address 96h A6h Bit 4 7 6 5 4 3 2 1 0 Name RCB8SE RCB7SE RCB6SE 55 45 RCB3SE RCB2SE RCB1SE Default O0 Bit 7 Receive Channel Bit 8 Suppress Enable RCB8SE MSB of the channel Set to 1 to stop this bit from being used Bit 6 Receive Chan
77. H3LLIP MOV8dOO13 LONW3MH ANIM MOVEdOO7 W901 INTERNAL SIGNALS TO FRAMER OM1900L 22 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 6 4 Receive and Transmit T1 E1 J1 Framer REC REC HDLC 1 HDLC 2 128 Byte 128 Byte FIFO FIFO DATA gt MAPPER MAPPER gt DATA RECEIVE FRAMER CLOCK gt CLOCK SYNC SYNC SYNC SYNC TPOS lt TNEG TCLK TRANSMIT ERAMER CLOCK 2 m 2 Q O U 0 gt MOV8dOO QVO lAVd DATA MAPPER MAPPER DATA INTERNAL T INTERNAL XMIT XMIT SIGNALS Pus HDLC 1 HDLC 2 TO 128 Byte 128 Byte BACKPLANE FIFO FIFO INTERFACE A 23 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 6 5 T1 E1 J1 Backplane Interface DATA CLOCK SYNC INTERNAL Sa BIT FDL EXTRACTION gt gt RLCLK SIGNALING BUFFER gt RSIG ELASTIC STORE WM RSYSCLK gt RSERO gt RCLKO lt gt RSYNC RMSYNC RFSYNC Sa FDL INSERT lt v v RDATA CHANNEL TIMING
78. Loopback RLB When this bit is set to 1 data input by the RPOSI and RNEGI pins is transmitted back to the TPOSO and TNEGO pins Data continues to pass through the receive side framer of the transceiver as it would normally Data from the transmit side formatter is ignored See Figure 6 2 for more details Bit 1 Payload Loopback PLB When set to 1 payload loopback is enabled and the following occurs 1 Data is transmitted from the TPOSO and TNEGO pins synchronous with RCLKO instead of TCLKT 2 All the receive side signals continue to operate normally 3 Data at the TSERI TDATA and TSIG pins is ignored T1 Mode Normally this loopback is only enabled when ESF framing is being performed but can also be enabled in D4 framing applications The transceiver loops the 192 bits of payload data with BPVs corrected from the receive section back to the transmit section The FPS framing pattern CRC6 calculation and the FDL bits are not looped back they are reinserted by the transceiver E1 Mode The transceiver loops the 248 bits of payload data with BPVs corrected from the receive section back to the transmit section The transmit section modifies the payload as if it was input at TSERI The FAS word Si Sa and E bits and CRCA are not looped back they are reinserted by the transceiver Bit 0 Framer Loopback FLB When this bit is set to 1 the transceiver loops data from the transmit side back to the receive side When FLB is enabled t
79. MDC TX EN TX CLK TX ERR RX CRS RXD 3 0 RX CLK RXDV MDIO MDC A 9 15 Ethernet MAC Indirect addressing is required to access the MAC register settings Writing to the MAC registers requires the SU MACWDO 3 registers to be written with 4 bytes of data The address for the write operation must be written to SU MACAWL and SU MACAWH A write command is issued by writing a zero to SU MACRWC MCRW and a one to SU MACRWC MCS MAC command status MCS is cleared by the DS33R11 when the operation is complete Reading from the MAC registers requires the SU MACRADH and SU MACRADL registers to be written with the address for the read operation A read command is issued by writing a one to SUL MACRWC MCRW and a zero to SU MACRWC MCS SU MACRWC MCS is cleared by the DS33R11 when the operation is complete After MCS is clear valid data is available in SU MACRDO SU MACRDS3 Note that only one operation can be initiated read or write at one time Data cannot be written or read from the MAC registers until the MCS bit has been cleared by the device The MAC registers are detailed in the following table 59 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 9 6 MAC Control Registers ADDRESS REGISTER DESCRIPTION MAC Control Register This register is used for programming full duplex half duplex promiscuous mod
80. MSG SITS arp e 62 PRBS State e 63 Repetitive Pattern Synchronization State 64 HDLC Encapsulaton Of MAG Frae 67 LAPS Encoding or MAC Frames bir nr 68 Ne Encapsulation of the MACO PTTTT 69 WE WT a aaea 72 Simplified Diagram of Receive Signaling 2 lt 82 Simplified Diagram of Transmit Signaling nincsen 84 CRG 4 Recaldulale rud T 90 Typical Monitor telo or pier PE 101 COP COGN 103 Basio CITA CE eee M nM 104 Transit Pulse Template ce M 105 Pule 4 T ULT 105 ARS e c 106 EET ris E1 MOUE M 106 2 Jier
81. Ma Data CRC32 7 pod 4 6 6 2 46 1500 Low d Max Frame Length 4 gt Encapsulated Frame The distant end will normally reject the sent frames if jabber timeout Loss of carrier excessive deferral late collisions excessive collisions under run deferred or collision errors occur Transmission of a frame under any of theses errors will generate a status bit in SU TFSL SU TFSH The DS33R11 provides user the option to automatically retransmit the frame if any of the errors have occurred through the bit settings in SU TFRC Deferred frames and heartbeat fail have separate resend control bits SU TFRC TFBFCB and SU TFRC TPRHBC If there is no carrier indicated by the MAC Transmit Packet Status the transmit queue data from the Serial Interface to the SDRAM to Ethernet Interface can be selectively flushed This is controlled by SU TFRC NCFQ 56 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver The MAC circuitry generates a frame status for every frame that is received This real time status can be read by SU RFSBO to SU RFSB3 Note the frame status is the real time status and hence the value will change as new frames are received Hence the real time status reflects the status in time and may not correspond to the current received frame being processed This is also true for the transmitted frames Frames with errors are usually rejected by the DS33R11 The user has the option of accepting frames by se
82. Mode In DCE Mode the 0533811 MAC port can be directly connected to another MAC In DCE DCEDTES G20 Mode the Transmit clock TX CLK and Receive clock RX CLK are output by the DS33R11 Note that there is no software bit selection of DCEDTES Note that DCE Mode is only relevant when the MAC interface is in mode RMII or MII Selection Set high to configure the MAC for RMII en interfacing Set low for MII interfacing 28 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION PHY MANAGEMENT BUS MDC C19 Management Data Clock MII Clocks management data between the PHY and DS33R11 The clock is derived from theSYSCLKI with a maximum frequency is 1 67MHz The user must leave this pin unconnected in the DCE Mode MDIO C20 MII Management data IO MII Data path for control information between the PHY and DS33R11 When not used pull to logic high externally through a 10kQ resistor The MDC and MDIO pins are used to write or read up to 32 Control and Status Registers in 32 PHY Controllers This port can also be used to initiate Auto Negotiation for the PHY The user must leave this pin unconnected in the DCE Mode SDRAM INTERFACE SCAS W7 SDRAM Column Address Strobe Active low output used to latch the column address on the rising edge of SDCLKO It is used with commands for Bank Activate Precharge and Mo
83. OF THE LINK ETC AND THE F BIT POSITION IS ADDED FORCED TO ON 1 NOTE 2 RSYNC IN THE OUTPUT MODE TR IOCRL4 0 NOTE 3 RSYNC IN THE INPUT MODE TR IOCR14 1 NOTE 4 RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 Figure 12 23 Receive Side Boundary Timing RSYSCLK 2 048MHz E Store Enabled RSYSCLK CHANNEL 31 CHANNEL 32 CHANNEL 1 RSERO X4 YusBymsBy j 6 Y JLSB MSB l RSYNC RMSYNC RSYNC CHANNEL 31 CHANNEL 32 CHANNEL 1 RSIG Note 4 RCHCLK RCHBLK NOTE 1 RSYNC IS IN THE OUTPUT MODE TR IOCR14 0 NOTE 2 RSYNC IS IN THE INPUT MODE TR IOCR14 1 NOTE 3 RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1 NOTE 4 RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE 0000 IN CHANNEL 1 309 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 24 G 802 Timing E1 Mode Only TS 131 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 o 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK
84. OOSIE 91h s z 92h Reserved z x i B 93h S 2 s 5 _ 94h RBECBOR BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BECO 95h RBECB1R BEC15 14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8 96h RBECB2R BEC23 BEC22 21 20 19 18 BEC17 BEC16 97h E 98h 0 BC7 BC6 BCS BC4 BC3 BC2 BC1 BCO 99h RBCB1 BC15 14 BC13 BC12 BC11 BC10 BC9 BC8 9Ah RBCB2 BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16 9Bh RBCB3 BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24 9Ch Reserved B 2 2 E 9Dh Reserved 2 z 9Eh Reserved gt OFh Reserved 119 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 1 4 Serial Interface Register Bit Map Table 11 5 Serial Interface Register Bit Map ADDR Bir 7 Bir 6 5 Bir4 Bir 3 2 Bir 1 OCOh LI TSLCR gt 2 TDENPLT OC1h LILRSTPD E E RESET OC2h LI LPBK 5 4 QLP OC3h Reserved OC4h LI TPPCL p TFAD TF16 TIFV TSD TBRE OC5h TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFGO OC6h TPEN7
85. RBRE RCCE 102h LI RMPSCL RMX7 RMX6 RMX5 RMX4 RMX3 RMX2 RMX1 RMXO 103h LI RMPSCH RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8 104h LIL RPPSR 1 s REPC RAPC RSPC 105h LI RPPSRL REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL 106h LI RPPSRIE REPIE RAPIE RIPDIE RSPDIE RLPDIE REPCIE RAPCIE RSPCIE 107h 108h LI RPCBO RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPCO 109h LI RPCB1 RPC15 RPC14 RPC13 RPC12 RPC11 RPC10 RPCO9 8 10Ah 2 RPC23 RPC22 RPC21 RPC20 RPC19 RPC18 RPC17 RPC16 10Ch LL RFPCBO RFPC7 REPC6 5 REPC4 REPC3 REPC2 REPC1 RFPCO 10Dh 1 REPC15 REPC14 REPC13 REPC12 11 10 9 8 10Eh 2 RFPC23 RFPC22 RFPC21 RFPC20 RFPC19 18 REPC17 REPC16 10Fh Reserved 110h LILRAPCBO RAPC7 6 5 RAPC3 RAPC2 RAPC1 RAPCO 111h 1 RAPC15 RAPC14 RAPC13 RAPC12 RAPC11 RAPC10 RAPC9 RAPC8 112h 2 RAPC23 RAPC22 RAPC21 RAPC20 19 RAPC18 RAPC17 RAPC16 113h Reserved gt 120 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADDR Bir 7 Bir 6 5 4 Bir 3 2 Bir 1 114h LLRSPCBO RSPC7 RSPC6 5 RSPC4 RSPC3 R
86. RSIG and RSERO pin to all ones This bit has no effect in E1 mode 0 normal signaling data at RSIG and RSERO 1 force signaling data at RSIG and RSERO to all ones 238 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR ERCNT Register Description Error Counter Configuration Register Register Address 41h Bit 7 6 5 4 3 2 1 0 Name MECU ECUS EAMS VCRFS FSBE MOSCRT LCVCRF Defaut o 1 9 o 0 Bit 6 Manual Error Counter Update MECU When enabled by TR ERCNT 4 the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters The user must wait a minimum of 1 5 RCLKO clock periods before reading the error count registers to allow for proper update Bit 5 Error Counter Update Select ECUS T1 Mode 0 update error counters once a second 1 update error counters every 42ms 333 frames E1 Mode 0 update error counters once a second 1 update error counters every 62 5ms 500 frames Bit 4 Error Accumulation Mode Select EAMS 0 TR ERCNT 5 determines accumulation time 1 TR ERCNT 6 determines accumulation time Bit 3 E1 Line Code Violation Count Register Function Select VCRFS 0 7 count bipolar violations BPVs 1 count code violations CVs Bit 2 PCVCR Fs Bit Error Report Enable FSBE 0 7 do not report bit errors in Fs bit position only Ft bit position 1 7 repor
87. RSYNC pin In this mode the receive elastic store can be enabled or disabled If the receive elastic store is enabled then the backplane clock RSYSCLK can be either 1 544MHz or 2 048MHz In the ESF framing mode the ABCD signaling bits are output on RSIG in the lower nibble of each channel The RSIG data is updated once a multiframe 3ms unless a freeze is in effect In the D4 framing mode the AB signaling bits are output twice on RSIG in the lower nibble of each channel Hence bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel The RSIG data is updated once a multiframe 1 5ms unless a freeze is in effect See the timing diagrams in Section 12 for some examples 10 9 2 1 Receive Signaling Reinsertion at RSERO In this mode the user provides a multiframe sync at the RSYNC pin and the signaling data is reinserted based on this alignment In T1 mode this results in two copies of the signaling data in the RSERO data stream the original signaling data and the realigned data This is of little consequence in voice channels Reinsertion be avoided in data channels since this feature is activated on a per channel basis In this mode the elastic store must be enabled however the backplane clock can be either 1 544MHz or 2 048MHz Signaling reinsertion can be enabled on a per channel basis by setting the RSRCS bit high in the TR PCPR register The channels that will have signaling reinserted are selected by writin
88. Receive Signaling Bit Format Changes With Operating Mode See Register Definition a TRES Receive Signaling Bit Format Changes With Operating Mode See Register Definition 2 TRIRSU Receive Signaling Bit Format Changes With Operating Mode See Register Definition E ERG Receive Signaling Bit Format Changes With Operating Mode See Register Definition 128 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADD NAME Bit 7 6 Bir 5 Bit 4 Bit 3 Bit 2 Bir 1 R 06A SR OR REN m Receive Signaling Bit Format Changes With Operating Mode See Register Definition h TR RS11 06B Receive Signaling Bit Format Changes With Operating Mode See Register Definition h TR RS12 06C Receive Signaling Bit Format Changes With Operating Mode See Register Definition h TR RS13 06D Receive Signaling Bit Format Changes With Operating Mode See Register Definition h TR RS14 06 Receive Signaling Bit Format Changes With Operating Mode See Register Definition h TR RS15 06 Receive Signaling Bit Format Changes With Operating Mode See Register Definition h TR RS16 070 CRC4R SIE ODM TCSS1 TCSSO RLOSF h TR CCR1 071 BPCS1 BPCSO BPEN h TR CCR2 072 TDATFMT TGPCKEN RDATFMT RGPCKEN h TR CCR3 073 RLT3 RLT2 RLT1 RLTO UOP3 UOP2 UOP1 UOPO h TR CCR4 074 4
89. Reserved initialize to FF 111h RESERVED nde Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved initialize to FF 123 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADDR NAME Bir 7 Bir 6 Bir 5 Bir 4 3 2 1 0 112h rupis gim Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 113h aos a Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 200h RXFRMC31 RXFRMC30 29 RXFRMC28 27 26 25 24 201h 23 16 RXFRMC23 RXFRMC22 21 RXFRMC20 RXFRMC19 18 RXFRMC17 16 202h 15 8 RXFRMC15 14 13 12 RXFRMC11 10 RXFRMC9 RXFRMC8 203h T 0 RXFRMC7 RXFRMC6 RXFRMC5 RXFRMC4 RXFRMC3 RXFRMC2 RXFRMC1 RXFRMCO 204h RXFRMOK31 RXFRMOK30 RXFRMOK29 RXFRMOK28 RXFRMOK27 RXFRMOK26 RXFRMOK25 RXFRMOK24 205h 23 16 RXFRMOK23 RXFRMOK22 RXFRMOK21 RXFRMOK20 RXFRMOK19 RXFRMOK18 RXFRMOK17 RXFRMOK16 206h 15 8 RXFRMOK15 RXFRMOK14 RXFRMOK13 RXFRMOK12 RXFRMOK11 10 RXFRMOK9 RXFRMOK8 207h 7 0 RXFRMOK7 RXFRMOK6 RXFRMOK5 RXFRMOK4 RXFRMOK3 RXFRMOK2 RXFRMOK1 RXFRMOKO 300h SU Tx
90. TCM3 TCM2 TCM1 TCMO h TR TDSOSEL 075 B1 B2 B3 B4 B5 B6 B7 B8 h TR TDSOM 076 RCM4 RCM3 RCM2 RCM1 RCMO h TR RDSOSEL 077 B1 B2 B3 B4 B5 B6 B7 B8 h TR RDSOM 078 L2 L1 LO EGL JAS JABDS DJA TPD h TR LIC1 079 ETS LIRST IBPV TUA1 JAMUX SCLD CLDS h TR LIC2 TCES RCES MM1 MMO RSCLKE TSCLKE TAOZ h TR LIC3 07B CMIE 1 0 TT1 TTO RT1 RTO h TR LIC4 07C _ M M B ui B _ h Reserved 07D AGCD GC5 GC4 GC3 GC2 GC1 GCO h TR TLBC 07 GRIC GTIC 1 5 1 4 1 IAA2 IAA1 1 07 7 C6 C5 C4 C3 C2 C1 CO h TR PCICR 080 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR TCICE1 081 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR TCICE2 082 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR TCICE3 083 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 h TR TCICE4 084 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR RCICE1 129 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADD NAME Bir 7 6 5 Bit 4 3 Bit2 Bit 1 Bit0 R 085 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR RCICE2 086 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR RCICE3 087 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 h TR RCICE4 088 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR RCBR1 089 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR RCBR2 08A CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR RCB
91. TPDFCB TPRHBC TPRCB Default 0 0 0 0 0 0 0 0 Bit 3 No Carrier Queue Flush Bar NCFQ If this bit is set to 1 the queue for data passing from Serial Interface to Ethernet Interface will not be flushed when loss of carrier is detected Bit 2 Transmit Packet Deferred Fail Control Enable TPDFCB If this bit if set to 1 the current frame is transmitted immediately instead of being deferred If this bit is set to 0 the frame is deferred if CRS is asserted and sent when the CRS is unasserted indicating the media is idle Bit 1 Transmit Packet HB Fail Control Bar TPRHBC If this bit is set to 1 the current frame will not be retransmitted if a heartbeat failure is detected Bit 0 Transmit Packet Resend Control Bar TPRCB If this bit is set to 1 the current frame will not be retransmitted if any of the following errors have occurred e Jabber time out e Loss of carrier e Excessive deferral e Late collision e Excessive collisions e Under run e Collision Note that blocking retransmission due to collision applicable in MIII Half Duplex Mode can result in unpredictable System level behavior 179 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU TFSL Transmit Frame Status Low Register Name Register Description Register Address 152h Bit 7 6 5 4 3 2 1 0 Name UR EC LC ED LOC NOC FABORT Default 0 0 0 0 0 0 0 0 Bit 7 Under R
92. TR RAF TR RNAF and TR TAF TR TNAF registers Section 10 15 1 The second method which is covered in Section 10 15 2 involves an expanded version of the first method 10 15 1 Method 1 Internal Register Scheme Based on Double Frame On the receive side the TR RAF and TR RNAF registers always report the data as it received in the Sa and Si bit locations The TR RAF and TR RNAF registers are updated on align frame boundaries The setting of the receive align frame bit in Status Register 4 5 4 0 indicates that the contents of the TR RAF and TR RNAF have been updated The host can use the 5 4 0 bit to know when to read the TR RAF and TR RNAF registers The host has 250 5 to retrieve the data before it is lost On the transmit side data is sampled from the TR TAF and TR TNAF registers with the setting of the transmit align frame bit in Status Register 4 TR SR4 3 The host can use the TR SR4 3 bit to know when to update the and TR TNAF registers It has 250 to update the data or else the old data is retransmitted If the TR TAF and TR TNAF registers are only being used to source the align frame and nonalign frame sync patterns then the host need only write once to these registers Data in the Si bit position is overwritten if either the framer is 1 programmed to source the Si bits from the TSERI pin 2 in the CRC4 mode or 3 has automatic E bit insertion enabled Data in the Sa bit position is overwritten if any of the T
93. TR T1RCR1 004 RFM RB8ZS RSLC96 RZSE RJC RD4YM h TR T1RCR2 005 TJC TFPT TCPT TSSE GB7S TFDLS TBL TYEL h TR T1TCR1 006 TB8ZS TSLC96 TZSE FBCT2 FBCT1 TD4YM Reserved TB7ZS h TR T1TCR2 007 TRAI CI TAIS CI TFM PDE TLOOP h TR T1CCR1 008 TR SSIE1 T1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR SSIE1 E1 CH7 CH6 CH5 CH4 CH3 CH2 CH1 UCAW 009 TR SSIE2 T1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR SSIE2 E1 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 TR SSIE3 T1 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR SSIE3 E1 CH22 CH21 CH20 CH19 CH18 CH17 CH16 LCAW CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 h TR SSIE4 00C CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR T1RDMR1 00D CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR T1RDMR2 00 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR T1RDMR3 ID7 106 105 104 103 102 101 100 h TR IDR 010 RPDV TPDV COFA 820 1620 SEFE 825 TR INFO1 011 BSYNC BD TCLE TOCD RL3 RL2 RL1 RLO h TR INFO2 012 CRCRC FASRC CASRC h TR INFO3 013 m E T E a h Reserved 014 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 h TR IIR1 015 e SR9 h TR IIR2 016 ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC h TR SR1 917 ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC h TR IMR1 018 RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS h TR SR2 019 TR IMR2 RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS 125 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver
94. TXFRMBD27 TXFRMBD26 TXFRMBD25 TXFRVBD2A Default 0 0 0 0 0 0 0 0 0339h Bit 23 22 21 20 19 18 17 16 Name TXFRMBD23 TXFRMBD22 TXFRMBD21 TXFRMBD20 TXFRVBD19 TXFRMBD18 TXFRMBD17 TXFRMBD16 Default 0 0 0 0 0 0 0 0 033Ah Bit 15 14 13 12 11 10 09 08 Name TXFRMBD15 TXFRMBD1A TXFRMBD13 TXFRMBD12 TXFRMBD11 TXFRMBD10 TXFRMBD9 TXFRMBD8 Default 0 0 0 0 0 0 0 0 033Bh Bit 07 06 05 04 03 02 01 00 Name TXFRMBD7 TXFRMBD6 TXFRMBD5 TXFRMBD4 TXFRMBD3 TXFRMBD2 TXFRMBD1 TXFRMBDO Default 0 0 0 0 0 0 0 0 Bits 0 to 31 All Frames Aborted Counter TXFRMBD 0 31 32 bit value indicating the number of frames aborted due to any reason Each time a frame is aborted this counter is incremented by 1 This counter resets only upon device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2 32 1 times at the maximum frame rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 200 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 7 T1 E1 J1 Transceiver Registers Register Name TR MSTRREG Register Description Master Mode Register Register Address 00h Bit 7 6 5 4 3 2 1 0 Name
95. TXFRMU24 335h 23 16 TXFRMU23 TXFRMU22 TXFRMU21 TXFRMU20 TXFRMU19 TXFRMU18 TXFRMU17 TXFRMU16 336h 15 8 TXFRMU15 TXFRMU14 TXFRMU13 TXFRMU12 TXFRMU11 TXFRMU10 TXFRMU9 TXFRMU8 337h 7 0 TXFRMU7 TXFRMU6 TXFRMUS5 TXFRMU4 TXFRMU3 TXFRMU2 TXFRMU1 TXFRMUO 338h SU TxBdFrmCtr TXFRMBD31 TXFRMBD30 TXFRMBD29 TXFRMBD28 TXFRMBD27 TXFRMBD26 TXFRMBD25 TXFRMBD24 339h 23 16 TXFRMBD23 TXFRMBD22 TXFRMBD21 TXFRMBD20 TXFRMBD19 TXFRMBD18 TXFRMBD17 TXFRMBD16 33Ah 15 8 TXFRMBD15 TXFRMBD14 TXFRMBD13 TXFRMBD12 TXFRMBD11 TXFRMBD10 TXFRMBD9 TXFRMBD8 33Bh 7 0 TXFRMBD7 TXFRMBD6 TXFRMBD5 TXFRMBD4 TXFRMBD3 TXFRMBD2 TXFRMBD1 TXFRMBDO Note that the addresses in the table above are the indirect addresses that must be provided to the SU VACAWH and SU MACAWL All unused and reserved locations must be initialized to zero for proper operation 124 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 11 8 T1 E1 J1 Transceiver Register Bit Map Active when CST 0 ADD NAME Bir 7 6 Bir 5 4 Bir 3 2 Bir 1 0 R 000 TEST1 TESTO T1 E1 SFTRST h TR MSTRREG 001 RSMS RSMS2 RSMS1 RSIO TSDW TSM TSIO ODF h TR IOCR1 002 RDCLKIN TDCLKIN Reyncinv TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM h TR IOCR2 v V 003 ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC h
96. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register The LIRST TR LIC2 6 should be toggled from 0 to 1 to reset the line interface circuitry It takes the transceiver about 40ms to recover from the LIRST bit being toggled Finally after the TSYSCLK and RSYSCLK inputs are stable the receive and transmit elastic stores should be reset this step can be skipped if the elastic stores are disabled 46 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE STEP 1 Apply 3 3V supplies then apply 1 8V supplies STEP 2 Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits outlined in Section 9 2 Clear all reset bits Allow 5ms for the reset recovery STEP 3 Reset the integrated T1 E1 J1 Transceiver through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register STEP 4 The LIRST TR LIC2 6 should be toggled from 0 to 1 to reset the line interface circuitry Allow 40ms for the reset recovery STEP 5 Check the Ethernet Mapper Device ID in the GL IDRL and GL IDRH registers STEP 6 Check the T1 E1 J1 Transceiver Device ID in the TR IDR register STEP 7 Configure the system clocks Allow the clock system to properly adjust STEP 8 Initialize the entire remainder of the r
97. This bit enables an interrupt if the RAPL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit 5 Receive Invalid Packet Detected Interrupt Enable RIPDIE This bit enables an interrupt if the RIPDL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit 4 Receive Small Packet Detected Interrupt Enable RSPDIE This bit enables an interrupt if the RSPDL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit 3 Receive Large Packet Detected Interrupt Enable RLPDIE This bit enables an interrupt if the RLPDL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit 2 Receive FCS Errored Packet Count Interrupt Enable REPCIE This bit enables an interrupt if the REPCL bit in the LI RPPSRL register is set Must be set low when the packets do not have an FCS appended 0 interrupt disabled 1 interrupt enabled Bit 1 Receive Aborted Packet Count Interrupt Enable RAPCIE This bit enables an interrupt if the RAPCL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit 0 Receive Size Violation Packet Count Interrupt Enable RSPCIE This bit enables an interrupt if the RSPCL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled 164 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RPCBO Register De
98. Transmit Flow Diagram T1 TRANSMIT FLOW through DIAGRAM RA ESCR 4 TESE Estore Mux PIN S Iu a SELECTOR Off Chip 22 27777 Connection REGISTER p From d T1 rcv logic b Payload LBCR1 1 PLB Loopback THMS1 H1TC 4 HDLC FDL 1 HDLC Mux 1 ES ee HICSS gt LCHITTSBS gt HDLC El Engine 2 L THMS2 H2TC 4 HDLC FDL 2 HDLC Mux 2 ES H2TCS1 3 gt gt idle lt 2 8 gt TITCR2 5 Tx FDL nn TZSE Zero Array Stuffer pee Idle Code Mux TCICE1 3 D T1TCR1 2 N FDL Mux Sy TFDLS Loop Code Gen ae Loop Code T1CCR1 0 0 SBOC BOC Mux T1CCR1 2 TFM lt 04 12th Fs EE T1TCR22 TDAYM 3 Yellow N Loopback PARIS D T1TCR1 0 TYEL alarm Software Sig FPS or Registers ESF Yellow Ft Fs n Alarm insertion Software Sig SSIE1 3 gt F bit Mux TFPT 1 1 5 To ESF Yellow To FDL Mux Mux To FDL Mux 113 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver From ESF From BOC Yellow Alarm From F bit Mux 2 FDL za T1TCR1 5 T1CCR1 2 ESF Yellow A L TYEL T1TC
99. at the selected insertion rate When CE is set to 0 the TR NOEx registers determine how many errors are to be inserted Bits 0 3 Error Insertion Rate Select Bits ERO to ER3 ER3 ER2 ER1 ERO Error Rate 0 0 0 0 No errors inserted 0 0 0 1 1 in 16 0 0 1 0 1 in 32 0 0 1 1 1 in 64 0 1 0 0 1 in 128 0 1 0 1 1 in 256 0 1 1 0 1 in 512 0 1 1 1 1 in 1024 1 0 0 0 1 in 2048 1 0 0 1 1 in 4096 1 0 1 0 1 in 8192 1 0 1 1 1 in 16 384 1 1 0 0 1 in 32 768 1 1 0 1 1 in 65 536 1 1 1 0 1 in 131 072 1 1 1 1 1 in 262 144 297 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR NOE1 Register Description Number of Errors 1 Register Address ECh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Defaut 0 0 0 0 0 0 0 0 Bits 0 7 Number of Errors Counter Bits 0 to 7 CO to C7 Bit CO is the LSB of the 10 bit counter Register Name TR NOE2 Register Description Number of Errors 2 Register Address EDh Bit 7 6 5 4 3 2 1 0 Name C9 C8 Defaut 0 0 0 o 50 0o 0 0 Bits 0 1 Number of Errors Counter Bits 8 to 9 C8 to C9 Bit C9 is the MSB of the 10 bit counter 298 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 7 1 Number of Errors Left Register The host can read the TR NOELx registers at any time to determine how many errors
100. bit in GL CR1 controls the inactive state of the interrupt pin allowing selection of a pull up resistor or active driver The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source The latched status bits for the interrupting entity must be read to clear the interrupt Also reading the latched status bit will reset all bits in that register During a reset condition interrupts cannot be generated The interrupts from any Source can be blocked at a global level by the placing a zero in the global interrupt enable registers GL LIE GL SIE GL BIE and GL TRQIE Reading the Latched Status bit for all interrupt generating events will clear the interrupt status bit and Interrupt signal will be de asserted Note that the integrated T1 E1 J1 transceiver also generates interrupts as discussed in Section 10 3 48 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 9 2 Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Drawing Legend Interrupt Status Register Name Registers Interrupt Enable Registers Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count LI RPPSL Reserved Reserved Reserved Reserved Reserved
101. bits E1 mode or the FDL T1 mode Each HDLC controller has 128 byte buffers in the transmit and receive paths When used with time slots the user can select any time slot or multiple time slots contiguous or noncontiguous as well as any specific bits within the time slot s to assign to the HDLC controllers The user must not map both transmit HDLC controllers to the same Sa bits time slots or in T1 mode map both controllers to the FDL HDLC 1 and HDLC 2 are identical in operation and therefore the following operational description refers only to a singular controller The HDLC controller performs the entire necessary overhead for generating and receiving performance report messages PRMs as described in ANSI T1 403 and the messages as described in AT amp T TR54016 HDLC controller automatically generates and detects flags generates and checks the CRC check sum generates and detects abort sequences stuffs and destuffs zeros and byte aligns to the data stream The 128 byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention The HDLC registers are divided into four groups control configuration status information mapping and FIFOs Table 10 12 lists these registers by group 10 16 1 HDLC Configuration The TR HxTC and TR HxRC registers perform the basic configuration of the HDLC controllers Operating features such as CRC generation zero stuffer transmi
102. event occurrence cannot collide with a user read access 8 1 3 Interrupt and Pin Modes The interrupt INT pin is configurable to drive high or float when not active The INTM bit controls the pin configuration when it is set the INT pin will drive high when not active After reset the INT pin is in high impedance mode until an interrupt source is active and enabled to drive the interrupt pin 42 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 ETHERNET MAPPER 9 1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows Serial Transmit Data TCLKE and Serial Receive Data RCLKI clock inputs are used to transfer data from the serial interface These clocks can be continuous or gapped System Clock SYSCLKI input Used for internal operation This clock input cannot be a gapped clock A clock supply with 100ppm frequency accuracy is suggested A buffered version of this clock is provided on the SDCLKO pin for the operation of the SDRAM A divided and buffered version of this clock is provided on REF CLKO for the RMII MII interface Packet Interface Reference clock REF CLK input that can be 25MHz or 50MHz This clock is used as the timing reference for the RMII MII interface The Transmit and Receive clocks for the MII Interface TX CLK and RX CLK In DTE mode these are input pins and accept clocks provided by an Ethernet PHY In the DCE mode these are output pins and will o
103. for future use Bit 6 1006 Reserved for future use Bit 5 1005 If this bit is set the device contains interface Bit 4 1004 If this bit is set the device contains MII interface Bit 3 1003 If this bit is set the device contains an Ethernet PHY Bits 0 2 1000 1002 A three bit count that is equal to 000b for the first die revision and is incremented with each successive die revision May not match the two letter die revision code on the top brand of the device Register Name GL IDRH Register Description Global ID High Register Register Address 01h Bit 7 6 5 4 3 2 1 0 1015 1014 1013 1012 1011 1010 1009 1208 Default 0 0 0 0 0 0 1 0 Bits 5 7 ID13 15 Number of Ethernet ports in the device minus 1 i e 000 1 Ethernet port Bit 4 1012 If this bit is set the device has LIU functionality Bit 3 ID11 If this bit is set the device has a framer Bit 2 ID10 Reserved for future use 1009 If this bit is set the device has HDLC or X 86 encapsulation Bit 0 1008 If this bit is set the device has inverse multiplexing functionality 134 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name GL CR1 Register Description Global Control Register 1 Register Address 02h Bit 7 5 4 2 1 0 Name REF CLKO INTM RST Default 0 0 0 Bit 2 REF CLKO OFF REF CLKO This bit determines if the REF
104. high during bit 1 of time slot 26 Bit 0 Transmit CRC4 Enable TCRC4 0 CRC4 disabled 1 CRC4 enabled 235 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR E1TCR2 Register Description E1 Transmit Control Register 2 Register Address 36h Bit 7 6 5 4 3 2 1 0 Name AEBE AAIS ARA Default 0 0 0 0 0 0 0 0 Bit 2 Automatic E Bit Enable AEBE 0 E bits not automatically set in the transmit direction 1 E bits automatically set in the transmit direction Bit 1 Automatic AIS Generation AAIS 0 disabled 1 enabled Bit 0 Automatic Remote Alarm Generation ARA 0 7 disabled 1 enabled Register Name TR BOCC Register Description BOC Control Register Register Address 37h Bit 7 6 5 4 3 2 1 0 RBOCE RBR RBF1 RBFO SBOC Defaut 0 0 0 0 Bit 4 Receive BOC Enable Enables the receive BOC function The TR RFDL register reports the received BOC code and two information bits when this bit is set 0 receive BOC function disabled 1 receive BOC function enabled the TR RFDL register reports BOC messages and information Bit 3 Receive BOC Reset RBR A 0 to 1 transition resets the BOC circuitry Must be cleared and set again for a subsequent reset Bits 1 2 Receive BOC Filter Bits RBF0 RBF1 The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a va
105. is demultiplexed into an 8 bit parallel data stream and passed on with packet start packet end and packet abort indications If there is less than eight bits in the last byte an invalid packet flag is raised the packet is tagged with an abort indication and the packet size violation count is incremented If packet processing is disabled destuffing is not performed Packet size checking checks each packet for a programmable maximum and programmable minimum size As the packet data comes in the total number of bytes is counted If the packet length is below the minimum size limit the packet is marked with an aborted indication and the packet size violation count is incremented If the packet length is above the maximum size limit the packet is marked with an aborted indication the packet size violation count is incremented and all packet data is discarded until a packet start is received The minimum and maximum lengths include the FCS bytes and are determined after destuffing has occurred If packet processing is disabled packet size checking is not performed FCS error monitoring checks the FCS and aborts errored packets If an FCS error is detected the FCS errored packet count is incremented and the packet is marked with an aborted indication If an FCS error is not detected the receive packet count is incremented The FCS type 16 bit or 32 bit is programmable If FCS processing or packet processing is disabled FCS error monitoring is no
106. is incremented every 125ms by 8 Credit balances not used in 250ms are reset to 0 The maximum value of CIR can not exceed the transmit line rate If the data rate received from the Ethernet interface is higher than the CIR the receive queue buffers will fill and the high threshold water mark will invoke flow control to reduce the incoming traffic rate The CIR function is only available for software mode of operation only CIR function is only available in data received at the Ethernet Interface to be sent to WAN There is not CIR functionality for data arriving from the WAN to be sent to the Ethernet Interface Negative credits are not allowed if there is not a credit balance no frames are sent until there is a credit balance again 71 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 INTEGRATED T1 E1 J1 TRANSCEIVER 10 1 T1 E1 J1 Clocks Figure 10 1 shows the clock map of the T1 E1 transceiver The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions Although there is only one jitter attenuator which can be placed in the receive or transmit path two are shown for simplification and clarity Figure 10 1 T1 E1 J1 Clock Map TSYSCLK MCLKS 0 TR LIC4 MPSO PRE SCALER MPS1 2 048 TO 1 544 TR LIC2 3 SYNTHESIZER 1 LOCAL JITTER ATTENUATOR
107. meo 1 8 8 4 H1TTSBS 0 HDLC Engine 2 HDLC DSO 2 D LHZTTSBS KEY HDLC Sabit _ o THMS2 H2TC 4 Mux 2 F C T28aBE4 T28aBE8 D H2TTSBS 4 H2TTSBS 0 C PIN 5 SELECTOR C gt REGISTER BERTEN BIC 0 a lt BTCS14 gt from PCPR Idle Code lt _ 14 gt To Per Channel 115 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Code Mux EET rCV logic E 1 T RAN 5 F LOW Loopback DIAGRAM THMS41 H1TC 4 HMS2 H2TC4 TAF TNAF non Sa E1TCR1 7 Sa bit Mux ETTCR1 4 TSIS Si bit Mux Si CRC4 MF Align Word Does not overwrite E bits E1TCR1 0 TCRC4 Si CRC4 Mux Auto E E1TCR2 2 AEBE pit Gen Sa4S Sa8S TLINK Mux E1TCR2 5 E1TCR2 7 Auto E1TCR2 8 ARA RA Gen Mux TS1 16 gt TSA1 E1TCR1 3 Software Sig E1TCR1 0 T16S CRC E1TCR1 0 TCRC4 Calculate TDSOSEL 0 TDSOSEL 4 0 4 CRC Re CCR1 6 CRC4R 4 calculate DSO AU Monitor u E1TCR2 1 AAIS AIS Gen UA1 Gen HDB3 E1TCR1 2 THDB3 Encoding E1TCR1 5 TUA1 To Bipolar NRZ coding Mux 116 of
108. or external termination The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux outputting the received line clock at RDCLKO and bipolar or NRZ data at RPOSO and RNEGO The transceiver contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission The receive circuitry also is configurable for various monitor applications The device has a usable receive sensitivity of OdB to 43dB for 1 and OdB to 36dB for T1 which allow the device to operate 0 63mm 22AWG cables up to 2 5km 1 and 6k feet T1 in length Data input at TPOSI and TNEGI is sent through the jitter attenuation mux to the waveshaping circuitry and line driver The transceiver drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer The line driver can handle both CEPT 30 ISDN PRI lines for E1 and long haul CSU or short haul DSX 1 lines for T1 10 20 2 Receiver The receiver contains a digital clock recovery system The device couples to the receive E1 or T1 twisted pair or coaxial cable in 750 E1 applications through a 1 1 transformer See Table 10 13 for transformer details The device has the option of using software selectable termination requiring only a single fixed pair of termination resistors The transceiver s LIU is designed to be fully software selectable for E1 and T1 requiring no change to any external resistors for the re
109. pin See the timing diagrams in Section 12 0 frame mode 1 multiframe mode Bit 1 TSYNC Select TSIO 0 TSYNC is an input 1 TSYNC is an output Bit 0 Output Data Format ODF 0 bipolar data at TPOSO and TNEGO 1 NRZ data at TPOSO TNEGO 0 202 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IOCR2 Register Description Configuration Register 2 Register Address 02h Bit 7 6 5 4 3 2 1 0 Name RCLKINV TCLKINV RSYNCINV TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM Default 0 0 0 0 0 0 0 0 Bit 7 RCLKO Invert RCLKINV 0 no inversion 1 inverts signal on RCLKO output Bit 6 TCLKT Invert TCLKINV 0 no inversion 1 inverts signal on TCLKT input Bit 5 RSYNC Invert RSYNCINV 0 no inversion 1 invert Bit 4 TSYNC Invert TSYNCINV 0 no inversion 1 invert Bit 3 TSSYNC Invert TSSYNCINV 0 no inversion 1 invert Bit 2 H 100 SYNC Mode H100EN 0 normal operation 1 SYNC shift Bit 1 TSYSCLK Mode Select TSCLKM 0 if TSYSCLK is 1 544MHz 1 if TSYSCLK is 2 048 2 Bit 0 RSYSCLK Mode Select RSCLKM 0 if RSYSCLK is 1 544MHz 1 2 if RSYSCLK is 2 048MHz 203 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR T1RCR1 Register Description T1 Receive Control Register 1 Register Address 03h Bit 7 6 5 4 3 2 1 0 ARC OOF1 OOF2 SYNCC SYNCT S
110. respect to the Ethernet Interface The Receive queue is for data arriving from Ethernet interface to be transmitted to the WAN interface The Transmit queue is for data arriving from the WAN to be transmitted to the Ethernet interface Hence the transmit and receive direction terminology is the same as is used for the Ethernet MAC port The user can define the connection and the size of the transmit and receive queues The size is adjustable in units of 32 by 2048 byte packets The external SDRAM can hold up to 8192 packets of data The user must ensure that all the connection queues do no exceed this limit The user also must ensure that the transmit and receive queues do not overlap each other Unidirectional connections are not supported When the user changes the queue sizes the connection must be torn down and re established When a connection is disconnected all transmit and receive queues associated with the connection are flushed and a 1 is sourced towards the Serial transmit and the HDLC receiver The clocks to the HDLC are sourced a 0 The user can also program high and low watermarks If the queue size grows past the High watermark an interrupt is generated if enabled The registers of relevance are described in Table 9 3 The AR TQSC1 size provides the size of the transmit queue for the connection The high watermark will set a latched status bit The latched status bit will clear when the register is read The status bit is indica
111. rmi Ea RI et EN E RENE ER VERRE E RE 301 12 9 TRANSCEIVER T1 MODE FUNCTIONAL TIMING 303 4 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver E RE EAS Mu PR 308 19 OPERATING PARAMETERS sa 2 seh annu aurAS ENSEM Ia 313 1351 THERMAL CHARACTERISTICS assa ero rob ien in uda baeo 314 13 2 WM INTEREADE ua ise ue erai wes 315 52 H Rn 317 134 MDIO INTERFACE 319 195 TRANSMIT WAN INTERFACE faves a ume Dr 320 13 6 RECEIVE WAN AEE E E a E 321 322 13 8 MICROPROCESSOR BUS AC 8 324 139 AG CHARACTERISTICS REGEIVE SIDE 55 partir Eti bie nide ix 327 13 10AC CHARACTERISTICS BACKPLANE CLOCK 331 13 1 TAC CHARACTERISTICS TRANSMIT SIDE cru st eR ole bees eR 332 IIZI TAG INTERFACE DIEM reo pr RYE Yo e E Te bere dire terre Erbe S v oV RS 335 T5 SE
112. signaling is enabled 0 7 elastic store is source of multiframe sync 1 framer or TSYNC pin is source of multiframe sync Bit 6 Interrupt Disable INTDIS This bit is convenient for disabling interrupts without altering the various interrupt mask register settings 0 interrupts are enabled according to the various mask register settings 1 interrupts are disabled regardless of the mask register settings Bit 3 Transmit Channel Data Format TDATFMT 0 64kbps data contained in all 8 bits 1 56kbps data contained in seven out of the 8 bits Bit 2 Transmit Gapped Clock Enable TGPCKEN 0 TCHCLK functions normally 1 enable gapped bit clock output on TCHCLK Bit 1 Receive Channel Data Format RDATFMT 0 64kbps data contained in all 8 bits 1 56kbps data contained in seven out of the 8 bits Bit 0 Receive Gapped Clock Enable RGPCKEN 0 RCHCLK functions normally 1 enable gapped bit clock output on RCHCLK 252 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR CCR4 Register Description Common Control Register 4 Register Address 73h Bit 7 6 5 4 3 2 1 0 Name RLT3 RLT2 RLT1 RLTO Berol eg 31 70 1T 39 90 Bits 4 7 Receive Level Threshold Bits RLTO to RLT3 RLT3 RLT2 RLT1 RLTO Receive Level dB 0 0 0 0 Greater than 2 5 0 0 0 1 2 5 0 0 1 0 5 0 0 0 1 1 7
113. te PRATER RUE ER RE A EE HER EEE 82 109 2 Receive SIA M 83 109 3 Processor Based ren Me 84 DUE Haidware Based 85 10 10 PER CHANNEL IDLE CODE GENERATION iii initi intrat 86 87 TOT TOBANNEL aoo ia Eo UH Lon de od cad din 88 TOCLSELASTICOOTOBESN eu E uU Y etr 88 bere ee Rt 88 TRANSIT ERAS TIC DINE is uu D 89 10 123 Elastic Stores A 89 10 124 Miniuni Mod 89 10 13G 706 INTERMEDIATE CRC 4 UPDATING IET MODE ONLY sisi cerei rrr te er cos 90 TOME TT BIT ORIENTED CODE BOC CONTROLEER EE PE eee 91 91 91 10 16 ADDITIONAL SA AND INTERNATIONAL SI BIT OPERATION E1 92 10 16 1 Method 1 Internal Register Scheme Based on Double Frame esses 92 10 16 2 Method 2 Internal Register Scheme Based on 4 Multiframe essen 92 10 17 ADDITIONAL HDLC CONTROLLERS IN T1 E1 J
114. the presence of a 10E 3 error rate and they should not falsely trigger on a framed all 1s signal Blue Alarm criteria in the device has been set to achieve this performance It is recommended that the RBL bit be qualified with the RLOS bit Note 2 ANSI specifications use a different nomenclature than this document The following terms are equivalent RBL AIS RCL LOS RLOS LOF RYEL RAI 75 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 5 E1 Framer Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control registers Typically the control registers are only accessed when the system is first powered up Once the device has been initialized the control registers need only to be accessed when there is a change in the system configuration There are two receive control registers TR ETRCR1 and TR E1RCR2 and two transmit control registers TR E1TCR1 and TR E1TCR2 There are also four status and information registers Each of these eight registers is described in this section Table 10 3 E1 Sync Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA RESYNC CRITERIA ITU SPEC LEVEL Three consecutive incorrect FAS received FAS present in frame N and 2 FAS not present in Alternate TR E1RCR1 2 1 frame 1 The above criteria is met or three consecutive incorrect bit 2 of non FAS received words found within 8ms out of 1000 received in error
115. the idle code array into the receive data stream Register Name TR RCBR1 Register Description Receive Channel Blocking Register 1 Register Address 88h Bit 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Defaut 0 0o 0o o 0o o o0 0o Bits 0 7 Receive Channels 1 to 8 Channel Blocking Control Bits CH1 to CH8 0 force the RCHBLK pin to remain low during this channel time 1 force the RCHBLK pin high during this channel time 262 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RCBR2 Register Description Receive Channel Blocking Register 2 Register Address 89h Bit 7 6 5 4 3 2 1 0 16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Defaut 0 0 o 0 0 O 0 0 Bits 0 7 Receive Channels 9 to 16 Channel Blocking Control Bits CH9 to CH16 0 force the RCHBLK pin to remain low during this channel time 1 force the RCHBLK pin high during this channel time Register Name TR RCBR3 Register Description Receive Channel Blocking Register 3 Register Address 8Ah Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Defaut 0 Bits 0 7 Receive Channels 17 to 24 Channel Blocking Control Bits CH17 to CH24 0 force the RCHBLK pin to remain low during this channel time 1 force the pin high during this channel time Register Name TR RCBR4 Register Description Receive Channel Blocking Register
116. the receive pattern generator to the incoming PRBS or QRSS pattern The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator and then checking the next 32 data stream bits Synchronization is achieved if all 32 bits match the incoming pattern If at least is incoming bits in the current 64 bit window do not match the receive pattern generator automatic pattern resynchronization is initiated Automatic pattern resynchronization can be disabled Figure 9 9 PRBS Synchronization State Diagram 32 bits loaded 63 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 16 2 Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern The receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern and then checking the next 32 data stream bits Synchronization is achieved if all 32 bits match the incoming pattern If at least sis incoming bits in the current 64 bit window do not match the receive PRBS pattern generator automatic pattern resynchronization is initiated Automatic pattern resynchronization can be disabled Figure 9 10 Repetitive Pattern Synchronization State Diagram Pattern Matches 9 16 3 Pattern Monitoring Pattern monitoring monitors the incoming data stream for Out Of Synchronization OOS condition
117. this signal should be connected to ground This signal is only valid in half duplex mode and is ignored in full duplex mode RX CRS CRS DV M19 Receive Carrier Sense MII Should be asserted high when data from the PHY RXD S3 0 is valid For each clock pulse 4 bits arrive from the PHY Bit 0 is the least significant bit In DCE mode connect to Vpp Carrier Sense Receive Data Valid RMII This signal is asserted high when data is valid from the PHY For each clock pulse 2 bits arrive from the PHY In DCE mode this signal must be grounded RX CLK M20 Receive Clock MII Timing reference for RX DV RX ERR and RXD 3 0 which are clocked on the rising edge RX_CLK frequency is 25 2 for 100Mbit s operation and 2 5MHz for 10Mbit s operation In DTE mode this is a clock input provided by the PHY In DCE mode this is an output derived from REF CLK providing 2 5MHz 10Mbit s operation or 25 2 100Mbit s operation RXDI 0 L18 RXD 1 L19 RXD 2 L20 RXDI 3 M18 Receive Data 0 through 3 Four bits of received data sampled synchronously with the rising edge of RX_CLK For every clock cycle the PHY transfers 4 bits to the DS33R11 RXD 0 is the least significant bit of the data Data is not considered valid when RX DV is low Receive Data 0 through 1 RMII Two bits of received data sampled synchronously with REF CLK with 100Mbit s mode Accepted when CRS DV is assert
118. time as the first byte of the preamble In DTE Mode TX CLK is input from the external PHY In DCE Mode the DS33R11 provides TX CLK derived from an external reference SYSCLKI Figure 12 5 MII Transmit Functional Timing mek LJ LT LY LJ LY LIY LUI LY L FLN LN LN ogg CLR T ETA ET BE yp TX EN 301 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver In Half Duplex DTE Mode the DS33R11 supports CRS and COL signals CRS is active when the PHY detects transmit or receive activity If there is a collision as indicated by the COL input the DS33R11 will replace the data nibbles with jam nibbles After a random time interval the packet is retransmitted The MAC will try to send the packet a maximum of 16 times The jam sequence consists of 55555555h Note that the COL signal and CRS can be asynchronous to the TX CLK and are only valid in half duplex mode Figure 12 6 Transmit Half Duplex with a Collision Functional Timing Receive Data RXD 3 0 is clocked from the external PHY synchronously with RX CLK The RX CLK signal is 2 5MHz for 10Mbit s operation and 25MHz for 100Mbit s operation RX DV is asserted by the PHY from the first nibble of the preamble in 100 Mbit s operation or first nibble of SFD for 10 Mbit s operation The data on RXD 3 0 is not accepted by the MAC if RX DV is low or RX ERR is high in DTE mode RX ERR should be tied low when in DCE Mode Figure 12 7 MII Receive Functiona
119. 0 Bit 7 Spare Code Detected Condition LSPARE T1 Only Set when the spare code as defined in the TR RSCD1 2 registers is being received See Section 10 19 for details This is a double interrupt bit See Section 9 7 Bit 6 Loop Down Code Detected Condition LDN T1 Only Set when the loop down code as defined in the TR RDNCD1 2 register is being received See Section 10 19 for details This is a double interrupt bit See Section 9 7 Bit 5 Loop Up Code Detected Condition LUP T1 Only Set when the loop up code as defined in the TR RUPCD1 2 register is being received See Section 10 19 for details This is a double interrupt bit See Section 9 7 Bit 4 Loss of Transmit Clock Condition LOTC Set when the TCLKT pin has not transitioned for one channel time Forces the LOTC pin high if enabled by TR CCR1 0 This is a double interrupt bit See Section 9 7 Bit 3 Loss of Receive Clock Condition LORC Set when the RDCLKI pin has not transitioned for one channel time This is a double interrupt bit See Section 9 7 Bit 2 V5 2 Link Detected Condition V52LNK E1 Only Set on detection of a V5 2 link identification signal 6 965 This is a double interrupt bit See Section 9 7 Bit 1 Receive Distant MF Alarm Condition E1 Only Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes This alarm is not disabled in the CCS signaling mode This is a double interrupt bit See Section
120. 0 0 0 O 0 0 Bits 0 7 Transmit Channels 9 to 16 Code Insertion Control Bits CH9 to CH16 0 do not insert data from the idle code array into the transmit data stream 1 insert data from the idle code array into the transmit data stream Register Name TR TCICE3 Register Description Transmit Channel Idle Code Enable Register 3 Register Address 82h Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Defaut ee 0 0o 0o 0o o0 49 9 Bits 0 7 Transmit Channels 17 to 24 Code Insertion Control Bits CH17 to CH24 0 do not insert data from the idle code array into the transmit data stream 1 insert data from the idle code array into the transmit data stream Register Name TR TCICEA Register Description Transmit Channel Idle Code Enable Register 4 Register Address 83h Bit 7 6 5 4 3 2 1 0 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 Default 0 Bits 0 7 Transmit Channels 25 to 32 Code Insertion Control Bits CH25 to CH32 0 do not insert data from the idle code array into the transmit data stream 1 insert data from the idle code array into the transmit data stream Register Name TR RCICE1 Register Description Receive Channel Idle Code Enable Register 1 Register Address 84h Bit 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Defaut o 0 o o o o 0 0 Bits 0 7 Receive Channels 1 to 8 Code Insertion Control Bits CH1 to CH8 0 do not in
121. 0 24 0 1 1 1 25 1 0 0 0 26 1 0 0 1 27 1 0 1 0 28 1 0 1 1 29 1 1 0 0 30 1 1 0 1 31 1 1 1 0 32 1 1 1 1 293 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR BBC1 Register Description BERT Bit Count Register 1 Register Address E3h Bit 7 6 5 4 3 2 1 0 Name 7 BBC6 BBC5 BBC4 BBC3 BBC2 BBC1 BBCO Default 0 Bits 0 7 BERT Bit Counter Bits 0 to 7 BBCO to BBC7 BBCO is the LSB of the 32 bit counter Register Name TR BBC2 Register Description BERT Bit Count Register 2 Register Address E4h Bit 7 6 5 4 3 2 1 0 15 14 BBC13 BBC12 BBC11 BBC10 BBC9 BBC8 Defaut 0 Bits 0 7 BERT Bit Counter Bits 8 to 15 BBC8 to BBC15 Register Name TR BBC3 Register Description BERT Bit Count Register 3 Register Address E5h Bit 7 6 5 4 3 2 1 0 23 22 21 20 19 18 BBC17 BBC16 Defaut 0 Bits 0 7 BERT Bit Counter Bits 16 to 23 BBC16 to BBC23 Register Name TR BBC4 Register Description BERT Bit Count Register 4 Register Address E6h Bit 7 6 5 4 3 2 1 0 Name BBC31 BBC30 BBC29 BBC28 BBC27 BBC26 BBC25 BBC24 Defaut 0 Bits 0 7 BERT Bit Counter Bits 24 to 31 BBC24 to BBC31 BBC31 is the MSB of the 32 bit counter 294 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR BEC1 Register Description BERT Error Count Register 1 Regi
122. 1 TXBYTECO Default 0 0 0 0 0 0 0 0 Bits 0 31 All Bytes Transmitted Counter TXBYTEC 0 31 32 bit value indicating the number of bytes transmitted Each time a byte is transmitted this counter is incremented by 1 This counter resets only upon device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2 32 1 times at the maximum data rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 197 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU TxBytesOkCtr Register Description MAC Bytes Transmitted OK Counter Register Address 030Ch indirect 030Ch Bit 31 30 29 28 27 26 25 24 TXBYTEOK31 TXBYTEOK30 29 TXBYTEOK28 TXBYTEOK27 TXBYTEOK26 TXBYTEOK25 TXBYTEOK24 Default 0 0 0 0 0 0 0 0 030Dh Bit 23 22 21 20 19 18 17 16 Name TXBYTEOK23 TXBYTEOK22 TXBYTEOK21 TXBYTEOK20 TXBYTEOK19 TXBYTEOK18 TXBYTEOKI7 TXBYTEOK16 Default 0 0 0 0 0 0 0 0 030Eh Bit 15 14 13 12 11 10 09 08 Name TXBYTEOK15 TXBYTEOK14
123. 1 544MHz or 2 048MHz Also if the elastic is enabled in conjunction with transmit hardware signaling CCR3 7 must be set 0 85 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 10 Per Channel Idle Code Generation Channel data can be replaced by an idle code on a per channel basis in the transmit and receive directions When operated in the T1 mode only the first 24 channels are used by the device the remaining channels CH25 CH32 are not used The device contains a 64 byte idle code array accessed by the idle array address register TR IAAR and the per channel idle code register TR PCICR The contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels This substitution can be enabled and disabled on a per channel basis by the transmit channel idle code enable registers TR TCICE1 4 and receive channel idle code enable registers TR RCICE 1 4 To program idle codes first select a channel by writing to the TR IAAR register Then write the idle code to the TR PCICR register For successive writes there is no need to load the TR IAAR with the next consecutive address The TR IAAR register automatically increments after a write to the TR PCICR register The auto increment feature can be used for read operations as well Bits 6 and 7 of the TR IAAR register can be used to block write a common idle code to all transmit or receive positions in the array with a si
124. 1 TRANSCEIVER eene nns 93 CO IER oed Pak DOE DUANE DAE RU E dad Kd DAR anes 93 Iu OO 5 e mt 95 PREF MADIS E M 95 3 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 96 10 1255 Facka Byles Avalablo iude dites Red MAR 96 10 15LEGACY FDL SUPPORT T1 apa nk a pA uk 97 OR ERD AI Tr oH 97 NTC m 97 bel Y 98 TIL T9EdGEC BO OPERATION a s pU x RED HER PPM ERR EVER VUE QUO P DOR FO DE ER REL LEBER DRE CURIAM UEM ERI 98 10 20 PROGRAMMABLE IN BAND LOOP CODE GENERATION AND 99 10 2 INTERFACE UNIT ss ran teo anb hn paru Rara Ic ni Penn Roque eee Ex nni 100 pur d RAE CA co M EU 100 pu A o 1 M CU 100 Cc UII PEU TH RN 102 10 22MCLE F RESCALER ucc uc bustum 103 FORD D E Fw p CU XR E ca Fra D ORE Er ie 103 10 24 GC MI CODE MARK INVERSION OPTION eer Goa Xd La adag Co cr e ea cea eaa 103 10 20RECONIMENDED CIRCUIT eniin CER DR FR VER CO ER Cet lE e D RC D Er
125. 1 Transceiver ADD NAME BiT 7 6 Bir 5 4 Bir 3 Bit 2 Bir 1 R NOFS TEOML THR THMS TFS TEOM TZSD TCRCD h TR H2TC 0 1 TFLWM2 TFLWM1 TFLWMO RFHWM2 RFHWM1 RFHWMO h TR H2FC 0A2 RHCS8 RHCS7 RHCS6 RHCS5 RHCS4 RHCS3 RHCS2 RHCS1 h TR H2RCS1 RHCS16 RHCS15 RHCS14 RHCS13 RHCS12 RHCS11 RHCS10 RHCS9 h TR H2RCS2 0 4 RHCS24 RHCS23 RHCS22 RHCS21 RHCS20 RHCS19 RHCS18 RHCS17 h TR H2RCS3 OAS RHCS32 RHCS31 RHCS30 RHCS29 RHCS28 RHCS27 RHCS26 RHCS25 h TR H2RCS4 0A6 RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE h TR H2RTSBS THCS8 THCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 h TR H2TCS1 THCS16 THCS15 THCS14 THCS13 THCS12 THCS11 THCS10 THCS9 h TR H2TCS2 THCS24 THCS23 THCS22 THCS21 THCS20 THCS19 THCS18 THCS17 h TR H2TCS3 THCS32 THCS31 530 THCS29 THCS28 THCS27 THCS26 THCS25 h TR H2TCS4 TCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE h TR H2TTSBS OAC MS RPBA6 5 RPBA4 RPBA3 RPBA2 RPBA1 RPBAO h TR H2RPBA OAD THD7 THD6 THD5 THD4 THD3 THD2 THD1 THDO h TR H2TF OAE RHD7 RHD6 RHD5 RHD4 RHD3 RHD2 RHD1 RHDO h TR H2RF TFBA7 TFBA6 5 4 2 1 TFBAO h TR H2TFBA 0 6 1 TCO RUP2 RUP1 RUPO RDN2 RDN1 RDNO h TR IBCC 0 7 C7 C6 C5 C4 C3 C2 C1 CO h TR TCD1 OBS C7 C6 C5 C4 C3 C2 C1 CO h TR TCD2 0B9 C7 C6 C5 C4 C3 C2
126. 100 Mbps and setting this bit to zero will cause the MAC to operate at 10 Mbps When in DCE mode the bit function is inverted setting this bit to 1 will cause the MAC to operate at 10 Mbps In DTE and MII mode the MAC determines the data rate from the incoming TX CLK and RX CLK Bit 1 Automatic Flow Control Enable ATFLOW If this bit is set to 1 automatic flow control is enabled based on the connection receive queue size and high watermarks Pause frames are sent automatically in full duplex mode The pause time must be programmed through SU MACFCR The jam sequence will not be sent automatically in half duplex mode unless the JAME bit is set This bit is applicable only in software mode Bit 0 Jam Enable JAME If this bit is set to 1 a Jam sequence is sent for a duration of 4 bytes This function is only valid in half duplex mode and will only function if Automatic Flow Control is disabled Note that if the receive queue size is less than receive high threshold setting a JAME will JAM one received frame If JAME is set and the receiver queue size is higher than the high threshold all received frames are jammed until the queue empties below the threshold Note that SU GCR is only valid in the software mode 178 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description SU TFRC Transmit Frame Resend Control Register Address 151h Bit 7 6 5 4 3 2 1 0 Name NCFQ
127. 192MHz or 16 384MHz clock Only used when the transmit side elastic store function is enabled Should be tied low in applications that do not use the transmit side elastic store 31 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION TSIG B4 Transmit Signaling Input for the T1 E1 J1 Transceiver When enabled this input will sample signaling bits for insertion into outgoing PCM data stream Sampled on the falling edge of TCLKT when the transmit side elastic store is disabled Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled ETHERNET MAPPER TRANSMIT SERIAL INTERFACE TSERO E2 O Transmit Serial Data Output from Ethernet Mapper Output on the rising edge of TCLKE Selective clock periods can be skipped for output of TSERO with a gapped clock input on TCLKE The maximum data rate is 52Mbit s TCLKE F1 Serial Interface Transmit Clock Input to Ethernet Mapper The clock reference for TSERO which is output on the rising edge of the clock TCLKE supports gapped clocking up to a maximum frequency of 52MHz TDEN TBSYNC D5 Transmit Data Enable Input The transmit data enable is programmable to selectively block enable the transmit data The TDEN signal must occur one clock edge prior to the affected data bit The active polarity of TDEN is programmable in register LI TSLCR It is recommended
128. 1OBT Defaut Oo 0 0 0 0 oO 0 0 Bit 3 HDLC 2 Transmit FIFO Underrun Event H2UDR Set when the transmit FIFO empties out without having seen the TMEND bit set An abort is automatically sent This bit is latched and is cleared when read Bit 2 HDLC 2 Opening Byte Event H2OBT Set when the next byte available in the receive FIFO is the first byte of a message Bit 1 HDLC 1 Transmit FIFO Underrun Event H1UDR Set when the transmit FIFO empties out without having seen the TMEND bit set An abort is automatically sent This bit is latched and is cleared when read Bit 0 HDLC 1 Opening Byte Event H1OBT Set when the next byte available in the receive FIFO is the first byte of a message 227 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR8 Register Description Status Register 8 Register Address 24h Bit 7 6 5 4 3 2 1 0 Name BOCC RFDLAD RFDLF TFDLE RMTCH RBOC Defaut 0 o 0 9 9 o 9 Bit 5 BOC Clear Event BOCC Set when 30 FDL bits occur without an abort sequence Bit 4 RFDL Abort Detect Event RFDLAD Set when eight consecutive 1s are received on the FDL Bit 3 RFDL Register Full Event RFDLF Set when the receive FDL buffer TR RFDL fills to capacity Bit 2 TFDL Register Empty Event TFDLE Set when the transmit FDL buffer TR TFDL empties Bit 1 Receive FDL Match Event RMTCH Set whenever the contents of the TR RFDL register
129. 2 10 2 PER CHANNEL seas 73 TRETI TRANSCEIVER INTERRUPTS DR Ta FT a 73 10 4 T1 FRAMER FORMATTER CONTROL AND STATUS 74 WOT TANSAV SEU Lm 74 10 4 2 AlS Cl and Generation and Detection 74 10 4 8 Receive Side Digital Milliwatt Code Generation eese sessi nnne 75 10 5 PERAMERI IFORMATTER CONTROL AND STATUS EE EET ENKARA EIRE 76 DONNE EE Lr i m 106 rre crc E 78 107 1 Lmnecoge Violation Counter AEE E ERR ER 78 10 72 Code Violation Count Register TR POVUOR 79 10 7 3 Frames Count Register riarann aeea 80 TOA E B Couner TR cisien aa AAA a aAA AAAA E RE DAERA 80 PS0 MONITORING FUNCTION 81 SIGNALING ute Etna tx tab rin Pla ae xS enna REA 82 10 9 1 Signa assesses Ee MEE AES
130. 20 TXFRMU19 TXFRMU18 TXFRMU17 TXFRMU16 Default 0 0 0 0 0 0 0 0 0336h Bit 15 14 13 12 11 10 09 08 Name TXFRMU15 TXFRMU14 TXFRMU13 TXFRMU12 TXFRMU11 TXFRMU10 TXFRMUS TXFRMUS8 Default 0 0 0 0 0 0 0 0 0337h Bit 07 06 05 04 03 02 01 00 Name TXFRMU7 TXFRMU6 TXFRMU5 TXFRMU4 TXFRMU3 TXFRMU2 TXFRMU1 TXFRMUO Default 0 0 0 0 0 0 0 0 Bits 0 31 Frames Aborted Due to FIFO Under Run Counter TXFRMU 0 31 32 bit value indicating the number of frames aborted due to FIFO under run Each time a frame is aborted due to FIFO under run this counter is incremented by 1 This counter resets only upon device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 232 1 times at the maximum frame rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 199 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU TxBdFrmCtr Register Description MAC All Frames Aborted Counter Register Address 0338h indirect 0338h Bit 31 30 29 28 27 26 25 24 Name TXFRMBD31 TXFRMBD30 TXFRMBD29 TXFRMBD28
131. 3 A don t care if a 1 bit to 4 bit length is selected Bit 2 Receive Spare Code Definition Bit 2 C2 A don t care if a 1 bit to 5 bit length is selected Bit 1 Receive Spare Code Definition Bit 1 C1 A don t care if a 1 bit to 6 bit length is selected Bit 0 Receive Spare Code Definition Bit 0 A don t care if a 1 bit to 7 bit length is selected Register Name TR RSCD2 Register Description Receive Spare Code Definition Register 2 Register Address BFh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Defaut 9 4 30 70 1 Bits 0 7 Receive Spare Code Definition Bits 0 7 0 7 A don t care if a 1 bit to 7 bit length is selected 277 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RFDL TR BOCC 4 1 Register Description Receive FDL Register Register Address COh Bit 7 6 5 4 3 2 1 0 Name RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOCO 9 1 9 o o o o o 9 RFDL register bit definitions when TR BOCC 4 1 Bit 5 BOC Bit 5 RBOC5 Bit 4 BOC Bit 4 RBOC4 Bit 3 BOC Bit 3 RBOC3 Bit 2 BOC Bit 2 RBOC2 Bit 1 BOC Bit 1 RBOC1 Bit 0 BOC Bit 0 RBOCO Register Name TR RFDL TR BOCC 4 0 Register Description Receive FDL Register Register Address COh Bit 7 6 5 4 3 2 1 0 RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDLO Defaut 0 The receive FDL register TR RFDL reports the inc
132. 30 Bit 4 Transmit HDLC Channel Select Bit 4 THCS4 Select Channel 5 13 21 or 29 Bit 3 Transmit HDLC Channel Select Bit 3 THCS3 Select Channel 4 12 20 or 28 Bit 2 Transmit HDLC Channel Select Bit 2 THCS2 Select Channel 3 11 19 or 27 Bit 1 Transmit HDLC Channel Select Bit 1 THCS1 Select Channel 2 10 18 or 26 Bit 0 Transmit HDLC Channel Select Bit 0 THCSO Select Channel 1 9 17 or 25 269 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1TTSBS TR H2TTSBS Register Description HDLC 1 Transmit Time Slot Bits Sa Bits Select HDLC 2 Transmit Time Slot Bits Sa Bits Select Register Address 9Bh ABh Bit 4 7 6 5 4 3 2 1 0 Name TCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TCB3SE TCB2SE TCB1SE Default 0 Bit 7 Transmit Channel Bit 8 Suppress Enable TCB1SE MSB of the channel Set to 1 to stop this bit from being used Bit 6 Transmit Channel Bit 7 Suppress Enable TCB1SE Set to 1 to stop this bit from being used Bit 5 Transmit Channel Bit 6 Suppress Enable TCB1SE Set to 1 to stop this bit from being used Bit 4 Transmit Channel Bit 5 Suppress Enable Sa4 Bit Enable TCB1SE Set to 1 to stop this bit from being used Bit 3 Transmit Channel Bit 4 Suppress Enable Sa5 Bit Enable TCB1SE Set to 1 to stop this bit from being used Bit 2 Transmit Channel Bit 3 Suppress Enable Sa6 Bit Enable TCB1SE Set to 1 to stop this bit from being used Bit 1
133. 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 DEVICE REGISTERS Ten address lines are used to address the register space Table 11 1 shows the register map for the DS33R11 The addressable range for the device is 0000h to O8FFh Each Register Section is 64 bytes deep Global Registers are preserved for software compatibility with multiport devices The Serial Interface Line Registers are used to configure the serial port and the associated transport protocol The Ethernet Interface Subscriber registers are used to control and observe each of the Ethernet ports The registers associated with the MAC must be configured through indirect register write read access due to the architecture of the device When writing to a register input values for unused bits and registers those designated with should be zero as these bits and registers are reserved When a register is read from the values of the unused bits and registers should be ignored A latched status bit is set when an event happens and is cleared when read The register details are provided in the following tables Table 11 1 Register Address Map SERIAL MAPPER CHIP GLOBAL ETHERNET TAJE1 J1 PORT SELECT REGISTERS ARBITER BERT iii dos INTERFACE TRANSCEIVER Ethernet CS 0 0000h 0040h O080h 00COh 17Fh i Mapper CST 1 003Fh 007Fh OOBFh 013Fh T1 E1 J1 5 1 lt 000h 0FFh
134. 4 Register Address 8Bh Bit 7 6 5 4 3 2 1 0 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 Defaut 0 Bits 0 7 Receive Channels 25 to 32 Channel Blocking Control Bits CH25 to CH32 0 force the RCHBLK pin to remain low during this channel time 1 force the RCHBLK pin high during this channel time 263 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TCBR1 Register Description Transmit Channel Blocking Register 1 Register Address 8Ch Bit 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Defaut e qn ge Bits 0 7 Transmit Channels 1 to 8 Channel Blocking Control Bits CH1 to CH8 0 force the TCHBLK pin to remain low during this channel time 1 force the TCHBLK pin high during this channel time Register Name TR TCBR2 Register Description Transmit Channel Blocking Register 2 Register Address 8Dh Bit 7 6 5 4 3 2 1 0 16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Defaut 0o 0 0 0 0 0 0 0 Bits 0 7 Transmit Channels 9 to 16 Channel Blocking Control Bits CH9 to CH16 0 force the TCHBLK pin to remain low during this channel time 1 force the pin high during this channel time Register Name TR TCBR3 Register Description Transmit Channel Blocking Register 3 Register Address 8Eh Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Defaut 0 0 o 0 0 0 0 0 Bits 0 7 Trans
135. 5 0 1 0 0 10 0 0 1 0 1 12 5 0 1 1 0 15 0 0 1 1 1 17 5 1 0 0 0 20 0 1 0 0 1 22 5 1 0 1 0 25 0 1 0 1 1 27 5 1 1 0 0 30 0 1 1 0 1 32 5 1 1 1 0 35 0 1 1 1 1 Less than 37 5 Register Name TR TDSOSEL Register Description Transmit Channel Monitor Select Register Address 74h Bit 7 6 5 4 3 2 1 0 Name TCM4 TCM3 TCM2 TCM1 TCMO Default 0 0 0 0 0 0 0 0 Bits 0 4 Transmit Channel Monitor Bits TCMO to TCM4 TCMO is the LSB of a 5 bit channel select that determines which transmit channel data appear in the TR TDSOM register 253 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TDSOM Register Description Transmit DSO Monitor Register Register Address 75h Bit 7 6 5 4 3 2 1 0 Name B1 B2 B3 B4 B5 B6 B7 B8 Defaut 0 0o 0o O O O O O Bits 0 7 Transmit DSO Channel Bits B1 to B8 Transmit channel data that has been selected by the transmit channel monitor select register B8 is the LSB of the DS0 channel last bit to be transmitted Register Name TR RDSOSEL Register Description Receive Channel Monitor Select Register Address 76h Bit 7 6 5 4 3 2 1 0 RCM4 RCM3 RCM2 RCM1 RCMO Detur 30 9 0 Bits 0 4 Receive Channel Monitor Bits RCMO to RCM4 RCMO is the LSB of a 5 bit channel select that determines which receive DSO channel data appear in the TR RDSOM register
136. 6 5 4 3 2 1 0 Name BBED BBCO BECO BRA1 BRAO BRLOS BSYNC 9 0 0 9 o o 9 9 Bit 6 Bit Error Detected Event BBED 0 interrupt masked 1 interrupt enabled Bit 5 BERT Bit Counter Overflow Event BBCO 0 interrupt masked 1 interrupt enabled Bit 4 BERT Error Counter Overflow Event BECO 0 interrupt masked 1 interrupt enabled Bit 3 Receive All Ones Condition BRA1 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 2 Receive All Zeros Condition BRAO 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 1 Receive Loss of Synchronization Condition BRLOS 0 interrupt masked 1 7 interrupt enabled interrupts on rising and falling edges Bit 0 BERT in Synchronization Condition BSYNC 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges 230 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR PCPR Register Description Per Channel Pointer Register Register Address 28h Bit 7 6 5 4 3 2 1 0 Name RSAOICS RSRCS RFCS BRCS THSCS PEICS TFCS BTCS Defaut 0 0 0 O o O O o Bit 7 Receive Signaling All Ones Insertion Channel Select RSAOICS Bit 6 Receive Signaling Reinsertion Channel Select RSRCS Bit 5 Receive Fractional Channel Select RFCS Bit 4 Bert Receive Channel Select BRCS Bit 3 Transmit Hardware Signali
137. 7F3 RSa7F5 RSa7F7 RSa7F9 RSa7F11 RSa7F13 RSa7F15 h TR RSa7 OCF RSa8F1 RSa8F3 RSa8F5 RSa8F7 RSa8F9 RSa8F11 RSa8F 13 RSa8F 15 h TR RSa8 000 Si 0 0 1 1 0 1 1 h TR TAF 001 Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 h TR TNAF 002 TsiFO TsiF2 TsiF4 TsiF6 TsiF8 TsiF10 TsiF12 TsiF14 h TR TSiAF 003 TsiF 1 TsiF3 TsiF5 TsiF7 TsiF9 TsiF11 TsiF13 TSiF15 h TR TSiNAF 004 TRAF 1 TRAF3 TRAF5 TRAF7 TRAF9 TRAF 11 TRAF13 TRAF15 h TR TRA 005 TSa4F1 TSa4F3 TSa4F5 TSa4F7 TSa4F9 TSa4F11 TSa4F13 TSa4F15 h TR TSa4 006 TSa5F1 TSa5F3 TSa5F5 TSa5F7 TSa5F9 TSa5F11 TSa5F13 TSa5F15 h TR TSa5 007 TSa6F1 TSa6F3 TSa6F5 TSa6F7 TSa6F9 TSa6F11 TSa6F13 TSa6F15 h TR TSa6 008 TSa7F1 TSa7F3 TSa7F5 TSa7F7 TSa7F9 TSa7F11 TSa7F13 TSa7F15 h TR TSa7 009 TSa8F1 TSa8F3 TSa8F5 TSa8F7 TSa8F9 TSa8F11 TSa8F13 TSa8F15 h TR TSa8 ODA SiAF SiNAF RA Sa4 Sa5 Sa6 Sa7 Sa8 h TR TSACR ACNT7 ACNT6 ACNT5 ACNT4 ACNT3 ACNT2 ACNT1 ACNTO h TR BAWC 132 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADD NAME Bit 7 BIT 6 5 4 3 2 Bit 1 0 R ODC RPAT7 RPAT6 RPAT5 4 RPAT3 RPAT2 RPAT1 RPATO h TR BRP1 ODD RPAT15 RPAT14 RPAT13 RPAT12 RPAT11 RPAT10 RPAT9 RPAT8 h TR BRP2 ODE RPAT23 RPAT22 RPAT21 RPAT20 RPAT19 RPAT18 RPAT17 RPAT16 h TR BRP3 ODF RPAT31 RPAT30 RPAT29 RPAT28 RPAT27 RPAT26 RPAT25 RPAT24 h TR BRP4 0 0 TINV RINV PS2 PS1 50 RESYNC h TR BC1 0
138. 93 T1 408 AT amp T TR54016 TR62411 ITU T G 703 G 704 G 706 G 736 G 775 G 823 G 932 1 431 0 151 Q 161 Recommendation 1 432 03 93 B ISDN User Network Interface Physical Layer Specification ETSI ETS 300 011 ETS 300 166 5 300 233 CTR12 4 Japanese JTG 703 JTI 431 JJ 20 11 CMI Coding Only 16 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 3 APPLICATIONS The DS33R11 is ideal for application areas such as transparent LAN service LAN extension and Ethernet delivery over T1 E1 J1 T3 E3 OC 1 EC 1 G SHDSL or HDSL2 4 For an example of a complete LAN to WAN design refer to Application Note 3411 0533211 LAN to Unframed T1 E1 WAN Bridge available on our website at www maxim ic com telecom Figure 3 1 Ethernet to WAN Extension With or Without Framing N T1 E1 J1 RMII MII Stream 10 Base T 100 Base T Inter Building LAN Extension DS33R11 Clock Sources SDRAM 17 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver A ACRONYMS AND GLOSSARY BERT Bit Error Rate Tester DCE Data Communication Interface DTE Data Terminating Interface FCS Frame Check Sequence HDLC High Level Data Link Control MAC Media Access Control MII Media Independent Interface RMII Reduced Media Independent Interface WAN Wide Area Network Note 1 P
139. BC6 REBC5 REBC4 REBC3 REBC2 REBC1 REBCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Byte Count RBC 7 0 Eight bits of a 32 bit value Register description below Register Name Register Description LI RAC1 Receive Aborted Byte Count 1 Register Register Address 11Dh Bit 7 6 5 4 3 2 1 0 Name REBC15 REBC14 REBC13 REBC12 REBC11 REBC10 REBC9 8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Byte Count RBC 15 8 Eight bits of a 32 bit value Register description below Register Name Register Description LI RAC2 Receive Aborted Byte Count 2 Register Register Address 11Eh Bit 7 6 5 4 3 2 1 0 Name REBC23 REBC22 REBC21 REBC20 REBC19 REBC18 REBC17 REBC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Byte Count RBC 16 23 Eight bits of a 32 bit value Register description below Register Name Register Description LI RAC3 Receive Aborted Byte Count 3 Register Register Address 11Fh Bit 7 6 5 4 3 2 1 0 Name REBC31 REBC30 REBC29 REBC28 REBC27 REBC26 REBC25 REBC24 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Byte Count REBC 31 24 These thirty two bits indicate the number of bytes contained in packets stored in the receive FIFO with an abort indication Note Bytes discarded due to FCS extraction system loopback FIFO reset or an overf
140. BGA 27mm x 27mm 56 G6004 001 70 70 24 00 8 79 4 10 12 14 16 W 1255554959 0 1 10 2 90000000000000000000 7S900m O6Z X EZ93 4cx 95 ZAN seat PLANE 01 0 98 0 oro 090 170 5 NOTES 1 DIMENSIONS ARE IN MILLIMETERS 2 ALL DIMENSIONS AND TOLERANCE CONFORM TO ASME Y 14 5 1994 DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM AN PRIMARY DATUM CJAND SEATING PLANES ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS DALLAS MARKETING OUTLINE 256 LEAD PBGA 27X27 1 27 MM PITCH 2 33 MM THICK 4 LAYER See 296 GRO 343 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 16 DOCUMENT REVISION HISTORY REVISION DESCRIPTION 072105 New product release Page 28 Corrected pin description of REF CLK 28 Clarified text regarding use of REF CLKO DCE and RMII modes Page 29 Corrected pin description of MDC Page 43 In Section 9 1 removed from third bullet th
141. Bits PSO to PS2 i PS1 PSO Pattern Definition 0 0 0 Pseudorandom 2E7 1 0 0 1 Pseudorandom 2E11 1 0 1 0 Pseudorandom 2E15 1 0 1 1 Pseudorandom pattern QRSS 20 4 pattern with 14 consecutive zero restrictions 1 0 0 Repetitive pattern 1 0 1 Alternating word pattern Modified 55 octet Daly pattern The Daly pattern is a repeating 55 octet 1 1 0 pattern that is byte aligned into the active DSO time slots The pattern is defined in an ATIS Alliance for Telecommunications Industry Solutions Committee T1 Technical Report Number 25 November 1993 1 1 1 Pseudorandom 2E9 1 Bit 1 Load Bit and Error Counters LC A low to high transition latches the current bit and error counts into registers TR BBC1 TR BBC2 TR BBC3 TR BBC4 and TR BEC1 TR BEC2 TR BEC3 and clears the internal count This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period Must be cleared and set again for subsequent loads Bit 0 Force Resynchronization RESYNC A low to high transition forces the receive BERT synchronizer to resynchronize to the incoming data stream This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern Must be cleared and set again for a subsequent resynchronization 292 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR BC2 Register D
142. C15 is the MSB of the 16 bit path code violation count Register Name TR PCVCR2 Register Description Path Code Violation Count Register 2 Register Address 45h Bit 7 6 5 4 3 2 1 0 Name PCVC7 PCVC6 PCVC5 PCVC4 PCVC3 PCVC2 PCVC1 PCVCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Path Code Violation Counter Bits 0 to 7 PCVCO to PCVC7 PCVCO is the LSB of the 16 bit path code violation count 240 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR FOSCR1 Register Description Frames Out of Sync Count Register 1 Register Address 46h Bit 7 6 5 4 3 2 1 0 Name FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 58 Default 0 0 0 0 0 0 0 0 Bits 0 7 Frames Out of Sync Counter Bits 8 to 15 FOS8 to FOS15 515 is the MSB of the 16 bit frames out of sync count Register Name TR FOSCR2 Register Description Frames Out of Sync Count Register 2 Register Address 47h Bit 7 6 5 4 3 2 1 0 57 FOS6 FOS5 FOS4 FOS3 FOS2 FOS1 FOSO Default 0 0 0 0 0 0 0 0 Bits 0 7 Frames Out of Sync Counter Bits 0 to 7 FOSO to FOS7 FOSO is the LSB of the 16 bit frames out of sync count Register Name TR EBCR1 Register Description E Bit Count Register 1 Register Address 48h Bit 7 6 5 4 3 2 1 0 Name EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 Default 0 0 0 0 0 0 0 0 Bits 0 7 E Bit Counter Bits 8 to 15 EB8 to EB15 EB15 is the MSB
143. CAS or CRC4 multiframe boundaries are indicated through the RMSYNC output If the user selects to apply a 1 544MHz clock to the RSYSCLK pin then every fourth channel of the received E1 data is deleted and an F bit position which is forced to 1 is inserted Hence channels 1 5 9 13 17 21 25 and 29 time slots 0 4 8 12 16 20 24 28 are deleted from the received 1 data stream Also in 1 544MHz applications the RCHBLK output is not active in channels 25 through 32 i e RCBRA is not active If the two frame elastic buffer either fills or empties a controlled slip occurs If the buffer empties then a full frame of data is repeated at RSERO and the TR SR5 0 and TR SR5 1 bits are set to a 1 If the buffer fills then a full frame of data is deleted and the TR SR5 0 and TR SR5 bits are set to a 1 88 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 12 2 Transmit Elastic Store See the TR IOCR1 and TR IOCR2 registers for information about clock and I O configurations The operation of the transmit elastic store is very similar to the receive side If the transmit side elastic store is enabled a 1 544MHz or 2 048MHz clock can be applied to the TSYSCLK input Controlled slips in the transmit elastic store are reported in the TR SR5 3 bit and the direction of the slip is reported in the TR SR5 4 and TR SR5 5 bits If hardware signaling insertion is not enabled TR CCR3 7 should be set 1 10 12 2 1 T1
144. DI and JTDO IDCODE When the IDCODE instruction is latched into the parallel instruction register the identification test register is selected The device identification code is loaded into the identification register on the rising edge of JTCLK following entry into the Capture DR state Shift DR can be used to shift the identification code out serially via JTDO During Test Logic Reset the identification code is forced into the instruction register s parallel output The ID code will always have a 1 in the LSB position The next 11 bits identify the manufacturer s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version 340 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 14 3 JTAG ID Codes Table 14 2 ID Code Structure REVISION DEVICE CODE MANUFACTURER S CODE REQUIRED ID 31 28 ID 27 12 ID 11 1 ID 0 0000 0000 0000 0110 0001 000 1010 0001 1 E1 J1 0000 0000 0000 0001 0000 000 1010 0001 1 ransceiver 14 4 Test Registers IEEE 1149 1 requires a minimum of two test registers the bypass register and the boundary scan register An optional test register has been included with the DS26521 design This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test Logic Reset state of the TAP controller 14 4 1 Boundary Scan Register This register con
145. DLC Data Bit 3 THD3 Bit 2 Transmit HDLC Data Bit 2 THD2 Bit 1 Transmit HDLC Data Bit 1 THD1 Bit 0 Transmit HDLC Data Bit 0 THDO LSB of an HDLC packet data byte Register Name Register Description TR H1RF TR H2RF HDLC 1 Receive FIFO HDLC 2 Receive FIFO Register Address 9Eh AEh Bit 7 6 5 4 3 2 1 0 Name RHD7 RHD6 RHD5 RHD4 RHD3 RHD2 RHD1 RHDO Defaut 0 oO oOo o o o O0 0 Bit 7 Receive HDLC Data Bit 7 RHD7 MSB of an HDLC packet data byte Bit 6 Receive HDLC Data Bit 6 RHD6 Bit 5 Receive HDLC Data Bit 5 RHD5 Bit 4 Receive HDLC Data Bit 4 RHD4 Bit 3 Receive HDLC Data Bit 3 RHD3 Bit 2 Receive HDLC Data Bit 2 RHD2 1 Receive HDLC Data Bit 1 RHD1 Bit 0 Receive HDLC Data Bit 0 RHDO LSB of an HDLC packet data byte 271 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1TFBA TR H2TFBA Register Description HDLC 1 Transmit FIFO Buffer Available HDLC 2 Transmit FIFO Buffer Available Register Address 9Fh Afh Bit 7 6 5 4 3 2 1 0 Name 6 5 4 2 TFBA1 TFBAO Default 0 Bits 0 7 Transmit FIFO Bytes Available TFBAO to TFBA7 TFBAO is the LSB Register Name TR IBCC Register Description In Band Code Control Register Register Address B6h Bit 7 6 5 4 3 2 1 0 Name TC1 TCO RUP2 RUP1 RUPO RD
146. DLC controller TR H2RCS1 TR H2RCS2 TR H2RCS3 TR H2RCSA HDLC 2 Receive Channel Select Registers TR H2RTSBS HDLC Z2 Receive TS Sa Bit Select Sa bits are used by the receive HDLC controller TR H1TCS1 TR H1TCS2 TR H1TCS3 TR H1TCS4 Selects which channels are mapped to the transmit HDLC 1 Transmit Channel Select Registers HDLC controller TR H2TCS1 TR H2TCS2 TR H2TCS3 TR H2TCS4 HDLC 2 Transmit Channel Select Registers TR H2TTSBS HDLC 2 Transmit TS Sa Bit Select Sa bits are used by the transmit HDLC controller 2 08 49422 TR H1RF HDLC 1 Receive FIFO Register TR H2RF HDLC 1 Receive FIFO Register TR H2TF HDLC 2 Transmit FIFO Register 94 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 16 22 FIFO Control The FIFO control register TR HxFC controls and sets the watermarks for the transmit and receive FIFOs Bits 3 4 and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark When the transmit FIFO empties below the low watermark the TLWM bit in the appropriate HDLC status register TR SR6 or TR SR7 is set TLWM is a real time bit and remains set as long as the transmit FIFO s read pointer is below the watermark If enabled this condition can also cause an interrupt through the INT pin When the receive FIFO fills above the high watermark the RHWM bit in the appropriate HDLC status register is set RHWM is a real time bit and remains set as long as the rece
147. Description SU MACAWH MAC Address Write High Register Address 14Bh Bit 7 6 5 4 3 2 1 0 Name MACAW 15 MACAW 14 MACAW13 MACAW12 MACAW11 MACAW10 MACAW9 8 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Write Address MACAWS 15 High byte of the MAC indirect write address Used only for write operations Register Name SU MACRWC Register Description MAC Read Write Command Status Register Address 14Ch Bit 7 6 5 4 3 2 1 0 Name MCRW MCS Default 0 0 0 0 0 0 0 0 Bit 1 MAC Command RW MCRW If this bit is written to 1 a read is performed from the MAC If this bit is written to 0 a write operation is performed Address information for write operations must be located in SU MACAWH and SU MACAWL Address information for read operations must be located in SU MACRADH and SU MACRADL user must also write a 1 to the MCS bit and the DS33R11 will clear MCS when the operation is complete Bit 0 MAC Command Status MCS Setting MCS in conjunction with MCRW will initiate a read or write to the MAC registers Upon completion of the read or write this bit is cleared Once a read or write command has been initiated the host must poll this bit to see when the operation is complete 177 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU LPBK Ethernet Interface Loopback Control Register Register Name Register De
148. Description SU MACMIIA MAC MII Management MDIO Address Register Register Address 0014h indirect 0014h Bit 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0015h Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0016h Bit 15 14 13 12 11 10 09 08 Name PHYA4 PHYA3 PHYA2 PHYA1 PHYAO MIIA4 MIIA3 MIIA2 Default 0 1 0 1 1 0 1 0 0017h Bit 07 06 05 04 03 02 01 00 Name MIIA1 MIIAO Reserved Reserved Reserved Reserved MIIW MIIB Default 1 1 0 0 0 0 0 0 Bits 11 15 PHY Address PHYA 0 4 These 5 bits select one of the 32 available PHY address locations to access through the PHY management MDIO bus Bits 6 10 MII Address MIIA 0 4 These 5 bits are the address location within the PHY that is being accessed Bit 1 MII Write MIIW Write this bit to 1 in order to execute a write instruction over the MDIO interface Write the bit to zero to execute a read instruction Bit 0 MII Busy MIIB This bit is set to 1 by the DS33R11 during execution of a MII management instruction through the MDIO interface and is set to zero when the DS33R11 has completed the instruction The user should read this bit and en
149. Description Transmit Errored Packet High Control Register Register Address 0C7h Bit 7 6 5 4 3 2 1 0 Name MEIMS TPER6 TPER5 TPER4 TPER3 TPER2 TPER1 TPERO Default 0 0 0 0 0 0 0 0 Bit 7 Manual Error Insert Mode Select MEIMS When 0 the transmit manual error insertion signal TMEI will not cause errors to be inserted When 1 TMEI will cause an error to be inserted when it transitions from a 0 to a 1 Note Enabling TMEI does not disable error insertion using TCER 6 0 and TCEN 7 0 Bits 0 6 Transmit Errored Packet Insertion Rate TPER 6 0 These seven bits indicate the rate at which errored packets are to be output One out of every x 10 packets is to be an errored packet TPER 3 0 is the value x and TPER 6 4 is the value y which has a maximum value of 6 If TPER 3 0 has a value of Oh errored packet insertion is disabled If TPER 6 4 has a value of 6xh or 7xh the errored packet rate is x 10 TPER 6 0 value of 01h results in every packet being errored A TPER 6 0 value of OFh results in every 15 packet being errored A TPER 6 0 value of 11h results in every 10 packet being errored To initiate automatic error insertion use the following routine 1 Configure LI TEPLC and LI TEPHC for the desired error insertion mode 2 Write the LI TPPCL TIAEI bit to 1 Note that this bit is write only 3 If not using continuous error insertion LI TPELC is not equal to the user sh
150. EX E 104 10 26 1 7 108 Em pM ER er eer ete en etree error 108 Ob 108 1020 2 BERT e 110 10 204 BERT BI COUR P 110 1020 0 BERT Eror COURET X 110 10 200 Wormd COut Pale e UL DERE E MERE REI DR IE 110 10 27 PAYLOAD ERROR INSERTION FUNCTION MODE ONLY V ice ni rr C ber c oe 111 19 257 Number o Enrors Regier oirre orn Mi EE t c du pM ee aches MM 111 10 28PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER 5 o rinepri bb eet ether in aa rrr rrr EHE ERES 112 T VEI SUPPORT We TRANSMIT FLOW DIAGRAMS ia 113 11 DEVICE REGISTERS 117 118 TET Gioball Mapper Register Bit Map a REA 118 Aber Redster Bi Mapica 119 BERT Register Bi MAD shoe a aed an acs tgs a aaa neat 119 TLLA Reno Mie aCe Register BR 120
151. Enabled TSYSCLK CHANNEL 23 CHANNEL 24 CHANNEL 1 TSERI 4 X4 X yfsBMsB j X X X 4 LSB F TSSYNC CHANNEL 23 CHANNEL 24 CHANNEL 1 X s TCHCLK TCHBLK NOTE 1 TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 IF THE TPCSI BIT IS SET THEN THE SIGNALING DATAAT TSIG IS IGNORED DURING CHANNEL 24 Figure 12 19 Transmit Side 2 048MHz Boundary Timing Elastic Store Enabled TSYSCLK CHANNEL 31 CHANNEL 32 CHANNEL 1 TSERI 1X A A X A Jews X X A X X Jer MM A TSSYNC CHANNEL 31 CHANNEL 32 CHANNEL 1 TSIG BM co LM m TCHCLK TCHBLK NOTE 1 TSERI DATA IN CHANNELS 1 5 9 13 17 21 25 AND 2915 IGNORED NOTE 2 15 PROGRAMMED TO BLOCK CHANNEL 31 IF THE TPCSI BIT IS SET THEN THE SIGNALING DATA AT TSIG WLL BE IGNORED NOTE 3 TCHBLK IS FORCED TO 1 INTHE SAME CHANNELS AS TSERI IS IGNORED SEE NOTE 1 NOTE 4 THE F BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT SIDE ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1 NORMALLY THE TRANSMIT SIDE FORMATTER OVERWRITES THE F BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS THROUGH THE F BIT POSITION 307 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 12 4 E1 Mode Figure 12 20 Receive Side Timing FRAME 1 2 3 4
152. FDLM1 RFDLMO Defaut 0 0 0 o o o 0 0 Bit 7 Receive FDL Match Bit 7 RFDLM7 MSB of the FDL match code Bit 6 Receive FDL Match Bit 6 RFDLM6 Bit 5 Receive FDL Match Bit 5 RFDLM5 Bit 4 Receive FDL Match Bit 4 RFDLM4 Bit 3 Receive FDL Match Bit 3 RFDLM3 Bit 2 Receive FDL Match Bit 2 RFDLM2 Bit 1 Receive FDL Match Bit 1 RFDLM1 Bit 0 Receive FDL Match Bit 0 RFDLMO LSB of the FDL match code 279 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RAF Register Description Receive Align Frame Register Register Address C6h Bit 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default Bit 7 International Bit Si Bit 6 Frame Alignment Signal Bit 0 Bit 5 Frame Alignment Signal Bit 0 Bit 4 Frame Alignment Signal Bit 1 Bit 3 Frame Alignment Signal Bit 1 Bit 2 Frame Alignment Signal Bit 0 Bit 1 Frame Alignment Signal Bit 1 Bit 0 Frame Alignment Signal Bit 1 Register Name TR RNAF Register Description Receive Nonalign Frame Register Register Address C7h Bit 7 6 5 4 3 2 1 0 Si 1 A Sa4 Sa5 Sa6 Sa Sa8 Default Bit 7 International Bit Si Bit 6 Frame Nonalignment Signal Bit 1 Bit 5 Remote Alarm A Bit 4 Additional Bit 4 Sa4 Bit 3 Additional Bit 5 5 5 Bit 2 Additional Bit 6 Sa6 Bit 1 Additional Bit 7 Sa7 Bit 0 Additional Bit 8 Sa8 280 of 344 DS33R11 Ethernet Mapper with Integ
153. Fh enable idle code substitution for receive channels 25 through 32 The transmit channel idle code enable registers TR TCICE1 2 3 4 are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per channel code array The receive channel idle code enable registers TR RCICE1 2 3 4 are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per channel code array 87 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 11 Channel Blocking Registers The receive channel blocking registers TR RCBR1 TR RCBR2 TR RCBR3 TR RCBR4 the transmit channel blocking registers TR TCBR1 TR TCBR2 TR TCBR3 TR TCBR4 control RCHBLK TCHBLK pins respectively The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels These outputs can be used to block clocks to a USART or LAPD controller in ISDN PRI applications When the appropriate bits are set to a 1 the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time Channels 25 through 32 are ignored when the device is operated in the T1 mode 10 12 Elastic Stores Operation The device contains dual two frame elastic stores one for the receive direction and one for the transmit direction Both elastic
154. FrmCtr TXFRMC31 TXFRMC30 TXFRMC29 TXFRMC28 TXFRMC27 TXFRMC26 TXFRMC25 TXFRMC24 301h 23 16 TXFRMC23 TXFRMC22 TXFRMC21 TXFRMC20 TXFRMC19 TXFRMC18 TXFRMC17 TXFRMC16 302h 15 8 TXFRMC15 TXFRMC14 TXFRMC13 TXFRMC12 TXFRMC11 TXFRMC10 TXFRMC9 TXFRMC8 303h 7 0 TXFRMC7 TXFRMC6 TXFRMC5 TXFRMC4 TXFRMC3 TXFRMC2 TXFRMC1 TXFRMCO 308h SU TxBytesCtr TXBYTEC31 TXBYTEC30 TXBYTEC29 TXBYTEC28 TXBYTEC27 TXBYTEC26 TXBYTEC25 TXBYTEC24 309h 23 16 TXBYTEC23 22 TXBYTEC21 TXBYTEC20 TXBYTEC19 TXBYTEC18 TXBYTEC17 TXBYTEC16 30Ah 15 8 15 14 TXBYTEC13 TXBYTEC12 TXBYTEC11 10 TXBYTEC9 TXBYTEC8 30Bh 7 0 TXBYTEC7 6 5 4 2 TXBYTEC1 TXBYTECO 30Ch SU TxBytesOkCtr 1 TXBYTEOK30 TXBYTEOK29 TXBYTEOK28 27 TXBYTEOK26 TXBYTEOK25 TXBYTEOK24 30Dh 23 16 TXBYTEOK23 TXBYTEOK22 21 TXBYTEOK20 TXBYTEOK19 TXBYTEOK18 TXBYTEOK17 TXBYTEOK16 30Eh 15 8 TXBYTEOK15 14 TXBYTEOK13 TXBYTEOK12 11 TXBYTEOK10 9 8 30Fh 7 0 TXBYTEOK7 6 5 4 2 TXBYTEOK1 TXBYTEOKO 334h SU TxFrmUndr TXFRMU31 TXFRMU30 TXFRMU29 TXFRMU28 TXFRMU27 TXFRMU26 TXFRMU25
155. G Mode Select 1 for the Ethernet Mapper This pin is sampled on the rising edge of JTCLK1 and is used to place the test access port into the various defined IEEE 1149 1 states This pin has a 10kQ pullup resistor JTMS1 C8 JTAG Reset 1 for the Ethernet Mapper JTRST1 is used to asynchronously reset the test access port controller After power up a rising edge on JTRST1 will reset the test port and cause the JTRST1 C7 Ipu device I O to enter the JTAG DEVICE ID mode Pulling JTRST1 low restores normal device operation JTRST1 is pulled HIGH internally via a 10kQ resistor operation If boundary scan is not used this pin should be held low JTAG Clock 2 for the T1 E1 J1 Transceiver This signal is used JTCLK2 A6 Ipu to shift data into JTDI1 on the rising edge and out of JTDO1 on the falling edge JTAG Data In 2 for the T1 E1 J1 Transceiver Test instructions JTDI2 B6 and data clocked into this pin on rising edge of JTCLK2 This pin has a 10kO pullup resistor JTAG Data Out 2 for the T1 E1 J1 Transceiver Test instructions JTDO2 C5 Oz and data are clocked out of this pin on the falling edge of JTCLK2 If not used this pin should be left unconnected JTAG Mode Select 2 for the T1 E1 J1 Transceiver This pin is sampled on the rising edge of JTCLK2 and is used to place the dcs ed Ipu test access port into the various defined IEEE 1149 1 states This pin has a 10kQ pullup resistor
156. HDLC encoder decoder X86 encoder and decoder and the corresponding serial port The serial interface reset bit LI RSTPD RST stays set after a one is written to it but is reset to zero when the global reset signal is active or when a zero is written to it Table 9 2 Reset Functions RESET FUNCTION LOCATION COMMENTS Hardware Device Reset RST Pin Transition from a logic O to a logic 1 resets the device Hardware JTAG Reset JTRST Pin Resets the JTAG test port Global Software Reset GL CR1 Writing to this bit resets the device Serial Interface Reset LI RSTPD Writing to this bit resets the Serial Interface Queue Pointer Reset GL C1QPR Writing to this bit resets the Queue Pointers There are several features in the DS33R11 to reduce power consumption The reset bit in the LI RSTPD register minimizes power usage in the Serial Interface Additionally the RST pin or GL CR1 RST bit may be held in reset indefinitely to keep the device in a low power mode Note that exiting a reset condition requires re initialization and configuration For the lowest possible standby current clocks may be externally gated The T1 E1 J1 transceiver contains an on chip power up reset function that automatically clears the writeable register space immediately after power is supplied to the transceiver The user can issue a chip reset at any time Issuing a reset disrupts traffic flowing through the transceiver until the device is reprogrammed
157. I TRX8C Register Description Transmit Receive X 86 Control Register Address 0DAh Bit 7 6 5 4 3 2 1 0 Name X86TRC7 86 6 86 5 86 4 X86TRC3 X86TRC2 X86TRC1 X86TRCO Default 0 0 0 0 0 0 1 1 Bits 0 7 X86 Transmit Receive Control 86 0 7 This is the control field for the X 86 transmitter and expected value for the receiver The register is reset to 0x03 Register Name Register Description LI TRX86SAPIH Transmit Receive X 86 SAPIH Register Address ODBh Bit 7 6 5 4 3 2 1 0 Name TRSAPIH7 TRSAPIHG TRSAPIH5 TRSAPIH4 TRSAPIH3 TRSAPIH2 TRSAPIH1 TRSAPIHO Default 1 1 1 1 1 1 1 0 Bits 0 7 X86 Transmit Receive Address TRSAPIHO 7 This is the address field for the X 86 transmitter and expected for the receiver The register is reset to Oxfe 159 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description LI TRX86SAPIL Transmit Receive X 86 SAPIL Register Address ODCh Bit 7 6 5 4 3 2 1 0 Name TRSAPIL7 TRSAPIL6 TRSAPIL5 TRSAPIL4 TRSAPIL3 TRSAPIL2 TRSAPIL1 TRSAPILO Default 0 0 0 0 0 0 0 1 Bits 0 7 X86 Transmit Receive Control TRSAPILO 7 This is the address field for the X 86 transmitter and expected value for the receiver The register is reset to 0x01 Register Name LI CIR Register Description Commit
158. If this bit is set the interrupt is enabled for RQOVFLS Bit 1 Receive Queue Crosses Low Threshold Interrupt Enable RQLTIE If this bit is set the watermark interrupt is enabled for ROLTS Bit 0 Receive Queue Crosses High Threshold Interrupt Enable RQHTIE If this bit is set the watermark interrupt is enabled for ROHTS Register Name SU QCRLS Register Description Queue Cross Threshold Latched Status Register Address 15Dh Bit 7 5 4 3 2 1 0 RFOVFLS RQOVFLS RQHTLS RQLTLS Default Bit 3 Receive FIFO Overflow latched Status RFOVFLS This bit is set if the receive FIFO overflows for the data to be transmitted from the MAC to the SDRAM Bit 2 Receive Queue Overflow Latched Status RQOVFLS This bit is set if the receive queue has overflowed This register is cleared after a read Bit 1 Receive Queue for Connection Crossed High Threshold Latched Status 5 This bit is set if the receive queue crosses the high Watermark This register is cleared after a read Bit 0 Receive Queue for Connection Crossed Low Threshold Latched Status RQLTLS This bit is set if the receive queue crosses the low Watermark This register is cleared after a read Note the bit order differences in the high low threshold indications in SU QCRLS and the interrupt enables SU QRIE 184 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU RFRC Rec
159. KI input pins will be active LIUC B2 When a logic high is present on this input pin the T1 E1 J1 Framer is internally connected to the LIU The TPOSI TNEGI TDCLKI RPOSI RNEGI RDCLKI input pins are deactivated When LIUC is connected high the TPOSI TNEGI TDCLKI RPOSI RNEGI and RDCLKI pins should be tied low Reset for the Ethernet Mapper An active low signal on this pin resets the internal registers and logic of the protocol conversion device This pin should remain low until power SYSCLKI RX CLK and TX CLK are stable then set high for normal operation This input requires a clean edge with a rise time of 25ns or less to properly reset the device Test Reset for the T1 E1 J1 Transceiver A dual function pin A zero to one transition issues a hardware reset to the transceiver register set A reset clears all configuration registers Configuration register contents are set to zero Leaving TSTRST high will tri state all output and pins including the parallel control port Set low for normal operation Useful in board level testing TSTRST C4 Mode Control for Processor Interface 00 Read Write Strobe Used Intel Mode 01 Data Strobe Used Motorola Mode 10 Reserved Do not use 11 Reserved Do not use MODEC O B19 MODEC 1 B20 Queue Overflow for Ethernet Mapper This pin goes high when QOVF H18 the transmit or receive queue has overflowed This pin will go low when the high waterm
160. LK High Time t3 7 13 7 13 ms REF CLK to TXD TX EN Delay t4 5 10 5 10 ns Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 3 Transmit RMII Interface Timing REF CLK TXD 1 0 TX_EN 317 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 13 8 Receive RMII Interface Note 1 Figure 13 4 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS 50MHz 50MHz REF_CLK Frequency 50 50 2 REF CLK Period t1 20 20 ns REF CLK Low Time t2 7 13 7 13 ns REF CLK High Time t3 7 13 7 13 ns RXD CRS DV to REF Setup t8 5 5 E Time REF CLK to RXD CRS DV Hold 9 5 5 a Time Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 4 Receive RMII Interface Timing REF_CLK 318 of 344 RXD 3 0 WW XXXXXX V ps CRS DV DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 4 MDIO Interface Table 13 9 MDIO Interface Note 1 Figure 13 5 PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1 67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time t5 10 ns MDIO Hold Time t6 20 ns Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 5 MDIO Interf
161. Loss of Transmit Clock Condition LOLITC 0 interrupt masked 1 7 interrupt enabled generates interrupts on rising and falling edges 216 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR2 Register Description Status Register 2 Register Address 18h Bit 7 6 5 4 3 2 1 0 RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7 Receive Yellow Alarm Clear Event RYELC T1 Only Set when the receive Yellow Alarm condition is no longer detected Bit 6 Receive Unframed All Ones Clear Event RUA1C Set when the unframed all 1s condition is no longer detected Bit 5 Framer Receive Carrier Loss Clear Event FRCLC Set when the carrier loss condition at RPOSI and RNEGI is no longer detected Bit 4 Receive Loss of Sync Clear Event RLOSC Set when the framer achieves synchronization remains set until read Bit 3 Receive Yellow Alarm Condition RYEL T1 Only Set when a Yellow Alarm is received at RPOSI and RNEGI Bit 2 Receive Unframed All Ones T1 Blue Alarm E1 AIS Condition RUA1 Set when an unframed all 1s code is received at RPOSI and RNEGI Bit 1 Framer Receive Carrier Loss Condition FRCL Set when 255 or 2048 if TR E1RCR2 0 1 E1 mode or 192 T1 mode consecutive 05 have been detected at RPOSI and RNEGI Bit 0 Receive Loss of Sync Condition RLOS Set when the transceiver is not synchronized to the received data stream
162. MII MII port 137 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description GL TRQIE Global Transmit Receive Queue Interrupt Enable Register Address 0Ah Bit 7 6 5 4 3 2 1 0 Name Default 0 0 0 0 0 0 0 0 Bit 4 Transmit Queue 1 Interrupt Enable Setting this bit to 1 enables an interrupt on 115 Bit 0 Receive Queue 1 Interrupt Enable Setting this bit to 1 enables an interrupt 115 Register Name GL TRQIS Register Description Global Transmit Receive Queue Interrupt Status Register Address OBh Bit 7 6 5 4 3 2 1 0 Name 115 RQ1IS Default 0 0 0 0 0 0 0 0 Bit 4 Transmit Queue 1 Interrupt Enable 115 If this bit is set to 1 the Transmit Queue 1 has interrupt status event Transmit queue events are transmit queue crossing thresholds and queue overflows Bit 0 Receive Queue 1 Interrupt Status If this bit is set to 1 the Receive Queue 1 has interrupt status event Receive queue events are transmit queue crossing thresholds and queue overflows Register Name GL BIE Register Description Global BERT Interrupt Enable Register Address 0Ch Bit 7 6 5 4 3 2 1 0 Name BIE Default 0 0 0 0 0 0 0 0 Bit 0 BERT Interrupt Enable BIE Setting this bit to 1 enables an interrupt on BIS
163. Mode If the user selects to apply 2 048 2 clock to the TSYSCLK pin then the data input at TSERI is ignored every fourth channel Therefore channels 1 5 9 13 17 21 25 and 29 time slots 0 4 8 12 16 20 24 and 28 are ignored The user can supply frame or multiframe sync pulse to the TSSYNC input Also in 2 048MHz applications the TCHBLK output is forced high during the channels ignored by the framer 10 12 2 2E1 Mode 1 544MHz 2 048 2 clock can be applied to the TSYSCLK input The user must supply a frame sync pulse or a multiframe sync pulse to the TSSYNC input 10 12 3 Elastic Stores Initialization There are two elastic store initializations that can be used to improve performance in certain applications elastic store reset and elastic store align Both of these involve the manipulation of the elastic store s read and write pointers and are useful primarily in synchronous applications RSYSCLK TSYSCLK are locked to RCLKO TCLKT respectively Table 10 11 Table 10 11 Elastic Store Delay After Initialization INITIALIZATION REGISTER BIT DELAY Receive Elastic Store Reset TR ESCR 2 8 Clocks Delay 1 Frame Transmit Elastic Store Reset TR ESCR 6 1 Frame Delay 2 Frames Receive Elastic Store Align TR ESCR 3 75 Frame lt Delay lt 1 Frames Transmit Elastic Store Align TR ESCR 7 72 Frame lt Delay lt 1 7 Frames 10 12 4 Minimum Delay Mode Elastic store minimum delay mode c
164. N2 RDN1 RDNO Default 0 Bits 6 7 Transmit Code Length Definition Bits TCO to TC1 TC1 0 Length Selected bits 0 0 5 0 1 6 3 1 0 7 1 1 16 8 4 2 1 Bits 3 5 Receive Up Code Length Definition Bits RUPO to RUP2 RUP2 RUP1 RUPO Length Selected bits 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 16 Bits 0 2 Receive Down Code Length Definition Bits RDNO to RDN2 RDN2 RDN1 RDNO Length Selected bits NIDIA BR o h gt alalolo alalolo 272 0 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TCD1 Register Description Transmit Code Definition Register 1 Register Address B7h Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Default Bit 7 Transmit Code Definition Bit 7 C7 First bit of the repeating pattern Bits 3 6 Transmit Code Definition Bits 3 6 C3 C6 Bit 2 Transmit Code Definition Bit 2 C2 A don t care if a 5 bit length is selected Bit 1 Transmit Code Definition Bit 1 C1 A don t care if a 5 bit or 6 bit length is selected Bit 0 Transmit Code Definition Bit 0 A don t care if a 5 6 or 7 bit length is selected Register Name TR TCD2 Register Description Transmit Code Definition Register 2 Register Address B8h Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Default meme s rcm E PE cmt e P
165. Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 7 Software Signaling Insertion Enable for Channels 1 to 8 CH1 to CH8 These bits determine which channels are to have signaling inserted from the transmit signaling registers 0 7 do not source signaling data from the TR TSx registers for this channel 1 7 source signaling data from the TR TSx registers for this channel 208 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SSIE1 E1 Mode Register Description Software Signaling Insertion Enable 1 Register Address 08h Bit 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 UCAW Default 0 0 0 0 0 0 0 0 Bits 1 7 Software Signaling Insertion Enable for Channels 1 to 7 CH1 to CH7 These bits determine which channels are to have signaling inserted from the transmit signaling registers 0 7 do not source signaling data from the TR TSx registers for this channel 1 source signaling data from the TR TSx registers for this channel Bit 0 Upper CAS Align Alarm Word UCAW Selects the upper CAS align alarm pattern 0000 to be sourced from the upper 4 bits of the TS1 register 0 do not source the upper CAS align alarm pattern from the TR TS1 register 1 source the upper CAS align alarm pattern from the TR TS1 register Register Name TR SSIE2 T1 Mode Register Description Software Signaling Insertion Enable 2 Register Address 09h Bit
166. O6 TR INFO7 register is a read only register It reports the status of the E1 synchronizer in real time TR INFO7 and some of the bits in TR INFO6 and TR INFOS are not latched and it is not necessary to precede a read of these bits with a write 9 10 Serial Interface The Serial WAN interface is intended to be connected to the integrated T1 E1 J1 Transceiver However the interface supports time division multiplexed serial data input and output up to 52 Mbit s The Serial interface receives and transmits encapsulated Ethernet packets The Serial Interface block consists of the physical serial port and HDLC X 86 engine The physical interface consists of a Transmit Data Transmit Clock Transmit Enable Receive Data Receive Clock and Receive Enable The WAN serial port can operate with a gapped clock and can be connected to a framer electrical LIU optical transceiver or T E Carrier transceiver for transmission to the WAN 50 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 11 Connections and Queues The multi port devices in this product family provide bidirectional cross connections between the multiple Ethernet ports and Serial ports when operating in software mode A single connection is preserved in this single port device to provide software compatibility with multi port devices The connection will have an associated transmit and receive queue Note that the terms Transmit Queue and Receive Queue are with
167. Occurrence Event TSLIP 0 interrupt masked 1 interrupt enabled Bit 2 Receive Elastic Store Full Event RESF 0 interrupt masked 1 interrupt enabled Bit 1 Receive Elastic Store Empty Event RESEM 0 interrupt masked 1 interrupt enabled Bit 0 Receive Elastic Store Slip Occurrence Event RSLIP 0 interrupt masked 1 interrupt enabled 224 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR6 TR SR7 Register Description HDLC 1 Status Register 6 HDLC 2 Status Register 7 Register Address 20h 22h Bit 7 6 5 4 3 2 1 0 Name TMEND RPE RPS RHWM RNE TLWM TNF Defaut 0o 0 o o o j o 0 j 0 Bit 6 Transmit Message End Event TMEND Set when the transmit HDLC controller has finished sending a message This is a latched bit and is cleared when read Bit 5 Receive Packet End Event RPE Set when the HDLC controller detects either the finish of a valid message i e CRC check complete or when the controller has experienced a message fault such as a CRC checking error or an overrun condition or an abort has been seen This is a latched bit and is cleared when read Bit 4 Receive Packet Start Event RPS Set when the HDLC controller detects an opening byte This is a latched bit and is cleared when read Bit 3 Receive FIFO Above High Watermark Condition RHWM Set when the receive 128 byte FIFO fills beyond the high watermark as defined by the r
168. PCICR 7Eh Write TR PCICR EEh Write TR PCICR FFh Write TR PCICR 7Eh Example 4 Sets all transmit idle codes to 7Eh Write TR IAAR 4xh Write TR PCICR 7Eh Example 5 Sets all receive and transmit idle codes to 7Eh and enables idle code substitution in all E1 transmit and receive channels Write TR IAAR Cxh enable block write to all transmit and receive positions in the array Write TR PCICR 7Eh 7Eh is idle code Write FEh enable idle code substitution for transmit channels 2 through 8 Although an idle code was programmed for channel 1 by the block write function above enabling it for channel 1 would step on the frame alignment alarms and Sa bits Write TR TCICE2 FFh enable idle code substitution for transmit channels 9 through 16 Write FEh enable idle code substitution for transmit channels 18 through 24 Although an idle code was programmed for channel 17 by the block write function above enabling it for channel 17 would step on the CAS frame alignment and signaling information Write 4 FFh enable idle code substitution for transmit channels 25 through 32 Write 1 FEh enable idle code substitution for receive channels 2 through 8 Write TR RCICE2 FFh enable idle code substitution for receive channels 9 through 16 Write TR RCICE3 FEh enable idle code substitution for receive channels 18 through 24 Write TR RCICE4 F
169. PI and hardware modes are not supported RSER has been renamed to RSERI RCLK has been renamed to RCLKI TSER has been renamed to TSERO TCLK has been renamed to TCLKE The integrated T1 E1 J1 transceiver is software compatible with the 052155 T1 E1 J1 transceiver There a few things to note when porting a DS2155 application to this device The Facilities Data Link FDL support is available through software only The TLINK RLINK TLCLK RLCLK pins are not available on the DS33R11 Multiplexed Microprocessor Bus mode is not supported on the DS33R11 The Extended System Information Bus ESIB is not supported on the DS33R11 The MODEC pins serve the function of the 0521555 BTS pin The interim LIU Framer clock signals RCLKI RCLKO have been renamed to RDCLKI RDCLKO to avoid confusion with the receive clock connections between the transceiver and the Ethernet mapper The interim LIU Framer clock signals TCLKI TCLKO have been renamed to TDCLKI TDCLKO to avoid confusion with the receive clock connections between the transceiver and the Ethernet mapper RSER has been renamed RSERO RCLK has been renamed RCLKO TSER has been renamed TSERI TCLK has been renamed TCLKT 10 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 2 FEATURE HIGHLIGHTS 2 4 General e 256 pin 27mm BGA package 1 8V and 3 3V supplies EEE 1149 1 JTAG boundary scan e Software access to device ID and silicon revision e Developm
170. PR C1HRPR Default 0 0 0 0 0 0 Bit 3 MAC Read Pointer Reset C1MRPR Setting this bit to 1 resets the receive queue read pointer for connection 1 This queue pointer must be reset after a disconnect and before a connection The user must clear the bit before subsequent reset operations Bit 2 HDLC Write Pointer Reset C1HWPR Setting this bit to 1 resets the receive queue write pointer for connection 1 This queue pointer must be reset after a disconnect and before a connection The user must clear the bit before subsequent reset operations Bit 1 HDLC Read Pointer Reset C1MHPR Setting this bit to 1 resets the transmit queue read pointer for connection 1 This queue pointer must be reset after a disconnect and before a connection The user must clear the bit before subsequent reset operations Bit 0 Transmit Write Pointer Reset C1HRPR Setting this bit to 1 resets the transmit queue write pointer for connection 1 This queue pointer must be reset after a disconnect and before a connection The user must clear the bit before subsequent reset operations Register Name GL BISTEN Register Description BIST Enable Register Address 20h Bit 7 5 4 2 1 0 Name BISTE Default 0 0 0 0 0 0 Bit 0 BIST Enable BISTE If this bit is set the DS33R11 performs BIST test on the SDRAM Normal data communication is halted while BIST enable is high The user must reset th
171. PT15 PT14 PT13 PT12 PT11 PT10 09 PT08 Default 0 0 0 0 0 0 0 0 001Dh Bit 23 22 21 20 19 18 17 16 Name PTO7 06 05 PT04 PTO2 PTO1 PTOO Default 0 1 0 1 0 0 0 0 001Eh Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 001Fh Bit 07 06 05 04 03 02 01 00 Name Reserved Reserve Reserved Reserved Reserved Reserved FCE FCB d Default 0 0 0 0 0 0 1 0 Bits 16 31 Pause Time PT 00 15 These bits are used for the Pause Time Field in transmitted Pause Frames This value is the number of time slots the remote node should wait prior to transmission Bit 1 Flow Control Enable FCE When set to 1 the MAC automatically detects pause frames and will disable the transmitter for the requested pause time Bit 0 Flow Control Busy FCB The host can set this bit to 1 in order to initiate transmission of a pause frame During transmission of a pause frame this bit remains set The DS33R11 will clear this bit when transmission of the pause frame has been completed The user should read this bit and ensure that this bit is equal to zero prior to initiating a pause frame 190 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU MMCCTRL MAC MMC Control Register Register Name Register Description
172. R S Least significant byte of 16 bit code Bits 0 7 Transmit Code Definition Bits 0 7 C0 C7 A don t care if a 5 6 or 7 bit length is selected 273 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RUPCD1 Register Description Receive Up Code Definition Register 1 Register Address B9h Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Default Note Writing this register resets the detector s integration period Bit 7 Receive Up Code Definition Bit 7 C7 First bit of the repeating pattern Bit 6 Receive Up Code Definition Bit 6 C6 A don t care if a 1 bit length is selected Bit 5 Receive Up Code Definition Bit 5 C5 A don t care if a 1 bit or 2 bit length is selected Bit 4 Receive Up Code Definition Bit 4 C4 A don t care if a 1 bit to 3 bit length is selected Bit 3 Receive Up Code Definition Bit 3 C3 A don t care if a 1 bit to 4 bit length is selected Bit 2 Receive Up Code Definition Bit 2 C2 A don t care if a 1 bit to 5 bit length is selected Bit 1 Receive Up Code Definition Bit 1 C1 A don t care if a 1 bit to 6 bit length is selected Bit 0 Receive Up Code Definition Bit 0 A don t care if a 1 bit to 7 bit length is selected Register Name TR RUPCD2 Register Description Receive Up Code Definition Register 2 Register Address BAh Bit 7 6 5 4 3 2 1 0 C7 C6 C5 C4 C3 C2 C1 CO Defaut 0o 0 0 0 0 0 0
173. R E1TCR2 3 to TR E1TCR2 7 bits are set to 1 10 15 2 Method 2 Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers TR RSiAF TR RSINAF TR RRA and TR RSa4 TR RSa8 that report the Si and Sa bits as they are received These registers are updated with the setting of the receive CRC4 multiframe bit in Status Register 2 TR SR4 1 The host can use the TR SR4 1 bit to know when to read these registers The user has 2ms to retrieve the data before it is lost The MSB of each register is the first received See the following register descriptions for more details The transmit side also contains a set of eight registers TR TSiAF TR TSiNAF TR TRA and TR TSa4 TR TSa8 that through the transmit Sa bit control register TR TSACR be programmed to insert Si and Sa data Data is sampled from these registers with the setting of the transmit multiframe bit in Status Register 2 TR SR4 4 The host can use the TR SR4 4 bit to know when to update these registers It has 2ms to update the data or else the old data is retransmitted The MSB of each register is the first bit transmitted See the register descriptions for more details 92 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 16 Additional HDLC Controllers in T1 E1 J1 Transceiver This device has two enhanced HDLC controllers HDLC 1 and HDLC 2 Each controller is configurable for use with time slots Sa4 to Sa8
174. R1 0 CRC Mux TCPT 1 1 5 D4 bit 2 BERT Yellow Engine Alm TFM T1CCR1 2 TD4YM 1 2 2 TYEL T1TCR1 0 L TFUS BIC 3 BERT Mux opu sce BERTEN 0 C BTCS1 35 from PCPR T1TCR2 3 FBCT1 F bit CSt35 1 2 4 FBCT2 Corruption CNOEL 0 Payload error ERC 4 CE dem insertion PEICS1 3 gt i z SSIET 8 s L GB7S TITCR1 3 stuffing L B7SE T1TCR2 0 Pulse T1CCR1 1 PDE 4 Density gt TPDV INFO1 6 Enforcer CRC DSO Calculation 4 0 4 TDSOSEL O 3 Monitor TDSOM B8ZS T1TCR2 7 B8ZSE 4 Encoding Blue T1TCR1 1 TBL Alarm Bipolar NRZ coding IOCR1 0 ODF 1 2 CLK CCR1 4 ODM 4 FULL CLK TNEG 114 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 18 E1 Transmit Flow Diagram uU a me E1 TRANSMIT FLOW Hardware D IAG RAM Signaling TX ESTORE Estore 4 TESE _ Off Chip Connection RDATA From E1 rcv logic Payload Loopback Mux HDLC Engine 1 LBCR1 1 PLB 581 H1TC 4 HDLC DSO Mux 1 24 CHITTSBS gt HDLC Sa bit 1 H1TC 4 T1SaBE4 aBEA
175. R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 8 Microprocessor Bus AC Characteristics Table 13 13 AC Characteristics Microprocessor Bus Timing VDD3 3 3 3V 5 VDD1 8 1 8V 5 T 40 C to 85 C Note 1 Figure 13 9 Figure 13 10 Figure 13 11 and Figure 13 12 PARAMETER SYMBOL MIN TYP MAX UNITS Setup Time for A 12 0 Valid to CS Active t1 0 ns Setup Time for CS Active to Either RD or WR Active 2 0 ns aa Time from either RD or DS Active to DATA 7 0 3 75 d Hold Time from either RD or WR Inactive to CS Inactive t4 0 ns from CS or RD or DS Inactive to DATA 7 0 5 5 20 4 Wait Time from RW Active to Latch Data t6 80 ns Data Set Up Time to DS Active 17 10 ns Data Hold Time from RW Inactive t8 2 ns Address Hold from RW Inactive t9 0 ns Write Access to Subsequent Write Read Access Delay HO 80 yis Time Note 1 Timing parameters in this table are guaranteed by design GBD 324 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 9 Intel Bus Read Timing MODEC 00 ADDR 12 0 Address Valid 7 0 Data Valid Figure 13 10 Intel Bus Write Timing MODEC 00 ADDR 12 0 Address Valid DATA 7 0 CS CST 325 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 11 Motorola Bus Read Timing MODEC 01 ADDR 12 0 Address Valid
176. R3 08B CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 h TR RCBR4 08C CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR TCBR1 08D CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR TCBR2 08E CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR TCBR3 08F CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 h TR TCBR4 090 NOFS TEOML THR THMS TFS TEOM TZSD TCRCD h TR H1TC 091 TFLWM2 TFLWM1 TFLWMO RFHWM2 RFHWM1 RFHWMO h TR H1FC 092 RHCS8 RHCS7 RHCS6 RHCS5 RHCS4 RHCS3 RHCS2 RHCS1 h TR H1RCS1 093 RHCS16 RHCS15 RHCS14 RHCS13 RHCS12 RHCS11 RHCS10 RHCS9 h TR H1RCS2 094 RHCS24 RHCS23 RHCS22 RHCS21 RHCS20 RHCS19 RHCS18 RHCS17 h TR H1RCS3 095 RHCS32 RHCS31 RHCS30 RHCS29 RHCS28 RHCS27 RHCS26 RHCS25 h TR H1RCS4 096 RCB8SE RCB7SE RCB6SE 55 45 RCB3SE RCB2SE RCB1SE h TR H1RTSBS 097 THCS8 THCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 h TR H1TCS1 098 THCS16 THCS15 THCS14 THCS13 THCS12 THCS11 THCS10 THCS9 h TR H1TCS2 099 THCS24 THCS23 THCS22 THCS21 THCS20 THCS19 THCS18 THCS17 h TR H1TCS3 09A THCS32 THCS31 THCS30 THCS29 THCS28 THCS27 THCS26 THCS25 h TR H1TCS4 09 TCB8SE TCB7SE TCB6SE TCBSSE 45 TCB3SE TCB2SE TCB1SE h TR H1TTSBS 09 5 6 5 4 2 RPBA1 RPBAO h TR H1RPBA 09D THD7 THD6 THDS THD4 THD3 THD2 THD1 THDO h TR H1TF 09E RHD7 RHD6 RHD5 RHD4 RHD3 RHD2 RHD1 RHDO h TR H1RF O9F TFBA7 5 4 2 1 TFBAO h TR H1TFBA 130 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J
177. RRAF5 Bit 4 Remote Alarm Bit of Frame 7 RRAF7 Bit 3 Remote Alarm Bit of Frame 9 RRAF9 Bit 2 Remote Alarm Bit of Frame 11 RRAF11 Bit 1 Remote Alarm Bit of Frame 13 RRAF 13 Bit 0 Remote Alarm Bit of Frame 15 RRAF15 Register Name TR RSa4 Register Description Received Sa4 Bits Register Address CBh Bit 7 6 5 4 3 2 1 0 Name RSa4F1 RSa4F3 RSa4F5 RSa4F7 RSa4F9 RSa4F11 RSa4F13 RSa4F15 Beau a Bit 7 Sa4 Bit of Frame 1 RSa4F1 Bit 6 Sa4 Bit of Frame 3 RSa4F3 Bit 5 Sa4 Bit of Frame 5 RSa4F5 Bit 4 Sa4 Bit of Frame 7 RSa4F7 Bit 3 Sa4 Bit of Frame 9 RSa4F9 Bit 2 Sa4 Bit of Frame 11 RSa4F11 Bit 1 Sa4 Bit of Frame 13 RSa4F13 Bit 0 Sa4 Bit of Frame 15 RSa4F15 282 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RSa5 Register Description Received Sa5 Bits Register Address CCh Bit 4 7 6 5 4 3 2 1 0 Name RSa5F1 RSa5F3 RSa5F5 RSa5F7 RSa5F9 RSa5F11 RSa5F13 RSa5F15 o ao9 qn 9 uc 0 Bit 7 Sa5 Bit of Frame 1 RSa5F1 Bit 6 Sa5 Bit of Frame 3 RSa5F3 Bit 5 Sa5 Bit of Frame 5 RSa5F5 Bit 4 Sa5 Bit of Frame 7 RSa5F7 Bit 3 Sa5 Bit of Frame 9 RSa5F9 Bit 2 Sa5 Bit of Frame 11 RSa5F11 Bit 1 Sa5 Bit of Frame 13 RSa5F13 Bit 0 Sa5 Bit of Frame 15 RSa5F15 Register Name TR RSa6 Register Description Received Sa6 Bits Register Address CDh Bit
178. Receive transparency processing 7D 5D is replaced by 7D Receive abort sequence the LAPS packet is dropped if 7D7E is detect Self synchronizing payload scrambling Frame indication due to bad address control SAPI FCS error abort sequence or frame size longer than preset max 11 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 2 5 Additional HDLC Controllers in the Integrated T1 E1 J1 Transceiver Two additional independent HDLC controllers Fast load and unload features for FIFOs SS7 support for FISU transmit and receive Independent 128 byte Rx and Tx buffers with interrupt support Access FDL Sa or single multiple DS0 channels DSO access includes Nx64 or Nx56 Compatible with polled or interrupt driven environments Bit oriented code BOC support 2 6 Committed Information Rate CIR Controller CIR Rate controller limits transmission of data from the Ethernet interface to the serial interface CIR granularity at 512kbit s CIR averaging for smoothing traffic peaks 2 7 SDRAM Interface Interface for 128Mb 32 bit wide SDRAM SDRAM Interface speed up to 100MHz Auto refresh timing Automatic precharge Master clock provided to the SDRAM No external components required for SDRAM connectivity 2 8 MAC Interface MAC port with standard MII less TX ER or RMII 10Mbps and 100Mbps Data rates Configurable DTE or DCE modes Facilitates auto negotiation by host microprocessor Programmable half and fu
179. S append mode is programmable If packet processing is disabled FCS processing is not performed Packet error insertion inserts errors into the FCS bytes A single FCS bit is corrupted in each errored packet The FCS bit corrupted is changed from errored packet to errored packet Error insertion can be controlled by a register or by the manual error insertion input LI TMEI TMEI The error insertion initiation type register or input is programmable If a register controls error insertion the number and frequency of the errors are programmable If FCS append is disabled packet error insertion will not be performed If packet processing is disabled packet error insertion is not performed Stuffing inserts control data into the packet to prevent packet data from mimicking flags A packet start indication is received and stuffing is performed until a packet end indication is received Bit stuffing consists of inserting a 0 directly following any five contiguous 1 s If packet processing is disabled stuffing is not performed There is at least one flag plus a programmable number of additional flags between packets The inter frame fill can be flags or 15 followed by a start flag If the inter frame fill is all 1 s the number of 1 s between the end and start flags does not need to be an integer number of bytes however there must be at least 15 consecutive 1 s between the end and start flags The inter frame padding type is programmable I
180. S pattern with a generating polynomial of x 1 The output of the pattern generator is forced to one if the next fourteen output bits are all zero Bit 5 Pattern Type Select PTS When 0 the pattern is a PRBS pattern When 1 the pattern is a repetitive pattern BPCHR BERT Pattern Configuration High Register Register Name Register Description Register Address 83h Bit 7 6 5 4 3 2 1 0 Name PTF4 PTF3 PTF2 PTF1 PTFO Default 0 0 0 0 0 0 0 0 Bits 4 to 0 Pattern Tap Feedback PTF 4 0 These five bits control the PRBS tap feedback of the pattern generator The tap feedback is from bit y of the pattern generator y PTF 4 0 1 These bits are ignored when programmed for a repetitive pattern For a PRBS signal the feedback is an XOR of bit n and bit y The values possible are outlined in Section 9 16 145 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description BSPBOR BERT Pattern Byte0 Register Register Address Bit 7 6 5 4 3 2 1 0 Name BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSPO Default 0 0 0 0 0 0 0 0 Bits 0 to 7 BERT Pattern BSP 7 0 Lower eight bits of 32 bits Register description follows next register Register Name Register Description BSPB1R BERT Pattern Byte 1 Register Register Ad
181. S1 TS15 are labeled channel 1 through channel 15 and 517 531 are labeled channel 15 through channel 30 In E1 CAS mode the CAS signaling alignment alarm byte can be sourced from the transmit signaling registers along with the signaling data Table 10 9 Time Slot Numbering Schemes TS 011121314 5 67 89 101111213 14115 1617118 19 20 21 22 23 24 125 26 27 28 29 30 31 Channel 112 3 4 5 6 7 8 9 1011 121131415116 17 1819 20 21 22 123 24 25 126 27 28 129 30131 32 Phone 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 118 19 20 121 22 23 24 25 26 27 28 29130 10 9 4 Hardware Based Transmit Signaling In hardware based mode signaling data is input through the TSIG pin This signaling PCM stream is buffered and inserted to the data stream being input at the TSERI pin Signaling data can be inserted on a per channel basis by the transmit hardware signaling channel select THSCS function The user has the ability to control which channels are to have signaling data from the TSIG pin inserted into them on a per channel basis See Section 10 2 for details on using this per channel THSCS feature The signaling insertion capabilities of the framer are available whether the transmit side elastic store is enabled or disabled If the elastic store is enabled the backplane clock TSYSCLK can be either
182. SMG INFORMATION si cen xai pede cree cheese ds eee dev eeu vtae E EE tme 336 14 1 JTAG TAP CONTROLLER STATE MACHINE 337 14 2 aru n bota Exec deta esha Me ticle e De rou b p b RR EY ERES 339 Wa JTAG ID CODES 341 Mc ERES 341 144 1 Boundary DOR 341 341 Mem 341 14 5 JTAG FUNCTIONAL 342 15 PACKAGE INFORMATION oai lex a Ro x ER e a Ka aai 343 15 1 PACKAGE OUTLINE DRAWING OF 256 BGA VIEW FROM BOTTOM OF DEVICE ARX ERAT OD d 343 16 DOCUMENT REVISION HISTORY NE RR oaa ORA UE AD SA Ec RA 344 5 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 3 1 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 7 1 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 9 11 Figure 9 12 Figure 9 13 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 Figure 10 1 Figure 10 1 Figur
183. SPC2 RSPC1 RSPCO 115h LLRSPCB1 RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 116h LLRSPCB2 RSPC23 RSPC22 RSPC21 RSPC20 RSPC19 RSPC18 RSPC17 RSPC16 118h LLRBCO RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBCO 119h LILRBC1 RBC15 RBC14 RBC13 RBC12 RBC11 RBC10 RBC9 RBC8 11Ah LILRBC2 RBC23 RBC22 RBC21 RBC20 RBC19 18 17 16 11Bh LILRBC3 RBC31 RBC30 RBC29 RBC28 RBC27 RBC26 RBC25 RBC24 11Ch REBC7 REBC6 5 REBC4 REBC3 REBC2 REBC1 REBCO 11Dh LLRAC1 REBC15 REBC14 REBC13 REBC12 REBC11 REBC10 REBC9 REBC8 11Eh 2 REBC23 REBC22 21 REBC20 REBC19 REBC18 REBC17 REBC16 11Fh LLRAC3 REBC31 REBC30 REBC29 REBC28 REBC27 REBC26 REBC25 REBC24 120h LLRHPMUU 3 2 5 RPMUU 121h LLRHPMUS 3 3 4 2 RPMUUS 122h LILRX86S z SAPIHNE SAPILNE CNE ANE 123h LILRX86LSIE SAPINEO1IM SAPINEFEIM CNE3LIM ANE4IM 124h LLTQLT TQLT7 TQLT6 TQLT5 TQLT4 TQLT3 TQLT2 TQLT1 TQLTO 125h LLTQHT TQHT7 TQHT6 TQHT5 TQHT4 TQHT3 TQHT2 TQHT1 TQHTO 126h TFOVFIE TQOVFIE TQHTIE TQLTIE 127h LLTQCTLS 3 TFOVFLS TQOVFLS TQHTLS TQLTLS Note ODEh OFFh 128h 13Fh are reserved 121 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 1 5 Ethernet Interface Register Bit Map Table 11 6 Ethernet Interface Register Bit Map ADDR
184. STPF Note 22h 3Fh are reserved 118 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 1 2 Arbiter Register Bit Map Table 11 3 Arbiter Register Bit Map ADDR NAME Bir 7 6 5 Bit 4 Bir 3 2 Bir 1 0 40h AR RQSC1 RQSC7 RQSC6 RQSC5 RQSC4 RQSC3 RQSC2 RQSC1 RQSCO 41h AR TQSC1 TQSC7 TQSC6 TQSC5 TQSC4 TQSC3 TQSC2 TQSC1 TQSCO 11 1 3 BERT Register Bit Map Table 11 4 BERT Register Bit Map ADDR BiT 7 6 5 Bit 4 Bir 3 2 Bit 1 080h BCR RNPL RPIC MPR APRD TNPL TPIC 081h Reserved 2 082h BPCLR QRSS PTS PLF4 PLF3 PLF2 PLF1 PLFO 083h BPCHR 4 2 1 PTFO 084h BSPBOR BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSPO 085h BSPB1R BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8 086h BSPB2R BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16 087h BSPB3R BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24 088h TEICR TIER2 TIER1 TIERO BEI TSEI O8Ah Reserved 3 p O8Bh Reserved x E 08Ch BSR PMS BEC 005 O8Dh Reserved _ O8Eh BSRL PMSL BEL BECL OOSL O8Fh Reserved E 90h BSRIE PMSIE BEIE BECIE
185. Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern a pseudorandom pattern alternating word pattern or a Daly pattern For a repetitive pattern that is fewer than 32 bits the pattern should be repeated so that all 32 bits are used to describe the pattern For example if the pattern was the repeating 5 bit pattern 01101 where the rightmost bit is the one sent first and received first then TR BRP1 should be loaded with ADh TR BRP2 with B5h TR BRP3 with D6h and TR BRP4 with 5Ah For a pseudorandom pattern all four registers should be loaded with all 1s i e FFh For an alternating word pattern one word should be placed into TR BRP1 and TR BRP2 and the other word should be placed into TR BRP3 and TR BRP4 For example if the DDS stress pattern 7E is to be described the user would place 00h in TR BRP1 00h in TR BRP2 7Eh in TR BRP3 and 7Eh in TR BRP4 and the alternating word counter would be set to 50 decimal to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received 10 25 4 BERT Bit Counter The BERT Bit Counter is comprised of TR BBC1 TR BBC2 TR BBC3 and 4 Once BERT has achieved synchronization this 32 bit counter increments for each data bit i e clock received Toggling the LC control bit in TR BC1 can clear this counter This counter saturates when full and sets the BBCO status bit 10 25 5 BERT Error Counter The BERT Error Cou
186. Si Bit of Frame 4 TSiF4 Bit 4 Si Bit of Frame 6 TSiF6 Bit 3 Si Bit of Frame 8 TSiF8 Bit 2 Si Bit of Frame 10 TSiF10 Bit 1 Si Bit of Frame 12 TSiF12 Bit 0 Si Bit of Frame 14 TSiF14 Register Name TR TSINAF Register Description Transmit Si Bits of the Nonalign Frame Register Address D3h Bit 7 6 5 4 3 2 1 0 Name TSiF1 TSiF3 TSiF5 TSiF7 TSiF9 TSiF11 TSiF13 TSiF15 Defaut 0 Bit 7 Si Bit of Frame 1 TSiF1 Bit 6 Si Bit of Frame 3 TSiF3 Bit 5 Si Bit of Frame 5 TSiF5 Bit 4 Si Bit of Frame 7 TSiF7 Bit 3 Si Bit of Frame 9 TSiF9 Bit 2 Si Bit of Frame 11 TSiF11 Bit 1 Si Bit of Frame 13 TSiF13 Bit 0 Si Bit of Frame 15 TSiF15 286 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TRA Register Description Transmit Remote Alarm Register Address D4h Bit 7 6 5 4 3 2 1 0 Name TRAF1 TRAF3 TRAF5 TRAF7 TRAF9 TRAF 11 TRAF 13 TRAF15 Defaults 9r Bit 7 Remote Alarm Bit of Frame 1 TRAF1 Bit 6 Remote Alarm Bit of Frame 3 TRAF3 Bit 5 Remote Alarm Bit of Frame 5 TRAF5 Bit 4 Remote Alarm Bit of Frame 7 TRAF7 Bit 3 Remote Alarm Bit of Frame 9 TRAF9 Bit 2 Remote Alarm Bit of Frame 11 TRAF11 Bit 1 Remote Alarm Bit of Frame 13 TRAF13 Bit 0 Remote Alarm Bit of Frame 15 TRAF15 Register Name TR TSa4 Register Description Transmit Sa4 Bits Register Address D5h
187. T Repetitive Pattern Set Register 3 Register Address DEh Bit 7 6 5 4 3 2 1 0 RPAT23 RPAT22 RPAT21 RPAT20 RPAT19 RPAT18 RPAT17 RPAT16 Default 0 Bits 0 7 BERT Repetitive Pattern Set Bits 16 to 23 RPAT16 to RPAT23 Register Name TR BRP4 Register Description BERT Repetitive Pattern Set Register 4 Register Address DFh Bit 7 6 5 4 3 2 1 0 Name RPAT31 RPAT30 RPAT29 RPAT28 RPAT27 RPAT26 RPAT25 RPAT24 Defaut 0 0 0 0 O O 0 0 Bits 0 7 BERT Repetitive Pattern Set Bits 24 to 31 RPAT24 to RPAT31 RPAT31 is the LSB of the 32 bit repetitive pattern set 291 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR BC1 Register Description BERT Control Register 1 Register Address E0h Bit 6 5 4 3 2 1 0 TINV RINV PS2 PS1 PSO LC RESYNC Default Sa a a Bit 7 Transmit Pattern Load TC A low to high transition loads the pattern generator with the pattern that is to be generated This bit should be toggled from low to high whenever the host wishes to load a new pattern Must be cleared and set again for subsequent loads Bit 6 Transmit Invert Data Enable TINV 0 do not invert the outgoing data stream 1 invert the outgoing data stream Bit 5 Receive Invert Data Enable RINV 0 do not invert the incoming data stream 1 invert the incoming data stream Bits 2 4 Pattern Select
188. T pin toggles low if enabled through TR IMR8 1 This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event occurs The framer also contains a zero destuffer which is controlled through the TR T1RCR2 3 bit In both ANSI T1 403 and TR54016 communications on the FDL follows a subset of an LAPD protocol The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag 01111110 or an abort signal 11111111 If enabled through TR T1RCR2 3 the device automatically looks for five 1s in a row followed by a If it finds such a pattern it automatically removes the zero If the zero destuffer sees six or more 1s in a row followed by a 0 the 0 is not removed The TR T1RCR2 3 bit should always be set to a 1 when the device is extracting the FDL Refer to Application Note 335 DS2141A DS2151 Controlling the FDL for information about using the device in FDL applications in this legacy support mode 97 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 17 3 Transmit Section The transmit section shifts out into the T1 data stream either the FDL in the ESF framing mode or the Fs bits in the D4 framing mode contained in the transmit FDL register TR TFDL When a new value is written to TR TFDL itis multiplexed serially LSB first into the proper position in the outgoing T1 data stream After the full 8 b
189. TIE Serial Interface Transmit Queue Cross Threshold Interrupt Enable Register Address 126h Bit 7 5 4 3 2 1 0 Name TFOVFIE TQOVFIE TQLTIE Default 0 0 0 0 0 0 0 Bit 3 Transmit FIFO Overflow for Connection Interrupt Enable TFOVFIE If this bit is set the watermark interrupt is enabled for TFOVFLS Bit 2 Transmit Queue Overflow for Connection Interrupt Enable TQOVFIE If this bit is set the watermark interrupt is enabled for 5 Bit 1 Transmit Queue for Connection High Threshold Interrupt Enable TQHTIE If this bit is set the watermark interrupt is enabled for TQHTS Bit 0 Transmit Queue for Connection Low Threshold Interrupt Enable TQLTIE If this bit is set the watermark interrupt is enabled for TQLTS Register Name Register Description LI TQCTLS Serial Interface Transmit Queue Cross Threshold Latched Status Register Address 127h Bit 7 5 4 3 2 1 0 Name TFOVFLS 5 TQHTLS TQLTLS Default Bit 3 Transmit Queue FIFO Overflowed Latched Status 5 This bit is set if the transmit queue FIFO has overflowed This register is cleared after a read This FIFO is for data to be transmitted from the HDLC to be sent to the SDRAM Bit 2 Transmit Queue Overflow Latched Status TQOVFLS This bit is set if the transmit queue has overflowed This register is cleared after a rea
190. TUDE T1 102 87 T1 403 CB 119 OCT 79 AND 1 431 TEMPLATE 500 400 300 200 100 100 200 300 400 500 600 700 TIME ns 105 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 10 Jitter Tolerance DEVICE TOLERANCE 7 62411 DEC 90 ITU T G 823 T E 2 0 lt gt amp 2 gt 5 100 1k FREQUENCY Hz Figure 10 11 Jitter Tolerance E1 Mode DEVICE TOLERANCE 2 1 5 UNIT INTERVALS o MINIMUM TOLERANCE LEVEL AS PER ITU G 823 2 4k 100 1k FREQUENCY Hz 106 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 12 Jitter Attenuation T1 Mode gt 2 lt 2 2 Lu un lt tx Lu E gt TR 62411 Dec 90 Prohibited Area 5 1 MODE N N 100 1K FREQUENCY Hz Figure 10 13 Jitter Attenuation E1 Mode JITTER ATTENUATION dB ITU G 7XX TBR12 Prohibited Area Prohibited Area E1 MODE 100 1k FREQUENCY Hz 107 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 14 Optional Crystal Connections 1 544MHz 2 048MHz NOTE C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJ UST FOR THE INPUT CAPACITANCE OF THE DEVICE 10 25 T1 E1 J1 TRANSCEIVER BERT FUNCTION The BERT block can generate an
191. This allows the user to set not only the watermarks but also to decide when to send a pause frame or not based on watermark crossings On the receive side the user has control over whether to respond to the pause frame sent by the distant end PCF bit Note that if automatic flow control is enabled the user cannot modify the FCE bit in the MAC flow control register On the Transmit queue the user has the option of setting high and low thresholds and corresponding interrupts There is no automatic flow control mechanism for data received from the Serial side waiting for transmission over the Ethernet interface during times of heavy Ethernet congestion 54 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 9 3 Flow Control Using Pause Control Frame 8 m gt Receive Queue Low Water Receive Queue High SR Water Mark Receive Queue initiate Flow control Growth 9 13 2 Half Duplex Flow Control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node The receiving node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant end In both 100Mbit s and 10Mbit s MII RMII modes 4 bytes are jammed upon reception of a new frame Note that the jamming mechanism does not jam the current frame that is being received during the watermark crossing but will wait to jam the next frame
192. Transmit Channel Bit 2 Suppress Enable Sa7 Bit Enable TCB1SE Set to 1 to stop this bit from being used Bit 0 Transmit Channel Bit 1 Suppress Enable Sa8 Bit Enable TCB1SE LSB of the channel Set to 1 to stop this bit from being used Register Name TR H1RPBA TR H2RPBA Register Description HDLC 1 Receive Packet Bytes Available HDLC 2 Receive Packet Bytes Available Register Address 9Ch ACh Bit 7 6 5 4 3 2 1 0 Name MS RPBA6 RPBA5 RPBA4 RPBA3 RPBA2 RPBA1 RPBAO Defaut 0o 0 0 O 0 0 0 0 Bit 7 Message Status MS 0 bytes indicated by RPBAO through RPBA6 are the end of a message Host must check the INFO5 or INFO6 register for details 1 bytes indicated by RPBAO through RPBA6 are the beginning or continuation of a message The host does not need to check the INFOS or INFOG register Bits 0 6 Receive FIFO Packet Bytes Available Count RPBAO to RPBA6 RPBAO is the LSB 270 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description TR H1TF TR H2TF HDLC 1 Transmit FIFO HDLC 2 Transmit FIFO Register Address 9Dh ADh Bit 7 6 5 4 3 2 1 0 Name THD7 THD6 THD5 THD4 THD3 THD2 THD1 THDO Defaut 0 0 0 0 0 0 O o Bit 7 Transmit HDLC Data Bit 7 THD7 MSB of an HDLC packet data byte Bit 6 Transmit HDLC Data Bit 6 THD6 Bit 5 Transmit HDLC Data Bit 5 THD5 Bit 4 Transmit HDLC Data Bit 4 THD4 Bit 3 Transmit H
193. Transmit PMU Update Status TPMUS This bit is set when the Transmit PMU Update is completed This bit is cleared when TPMUU is reset 158 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 5 2 X 86 Registers X 86 transmit and common registers are used to control the operation of the X 86 encoder and decoder Register Name LI TX86EDE Register Description X 86 Encoding Decoding Enable Register Address 0D8h Bit 7 6 5 4 3 2 1 0 Name X86ED Default 0 0 0 0 0 0 0 0 Bit 0 X 86 Encoding Decoding X86ED If this bit is set to 1 X 86 encoding and decoding is enabled for the Transmit and Receive paths The MAC Frame is encapsulated in the X 86 Frame for Transmit and the X 86 headers are checked for in the received data If X 86 functionality is selected the X 86 receiver byte boundary is provided by the RBSYNC signal and the DS33R11 provides the transmit byte synchronization TBSYNC No HDLC encapsulation is performed Register Name LI TRX86A Register Description Transmit Receive X 86 Address Register Address 0D9h Bit 7 6 5 4 3 2 1 0 Name X86TRA7 X86TRA6 X86TRA5 X86TRA4 X86TRA3 X86TRA2 X86TRA1 X86TRAO Default 0 0 0 0 0 1 0 0 Bits 0 7 X86 Transmit Receive Address X86TRAO 7 This is the address field for the X 86 transmitter and for the receiver The register default value is 0x04 Register Name L
194. UCTION CODES SAMPLE PRELOAD BYPASS EXTEST BoudayScan 00 SAMPLE PRELOAD This is a mandatory instruction for the IEEE 1149 1 specification This instruction supports two functions The digital I Os of the device be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture DR state SAMPLE PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift DR state BYPASS When the BYPASS instruction is latched into the parallel instruction register JTDI connects to JTDO through the one bit bypass test register This allows data to pass from JTDI to JTDO not affecting the device s normal operation EXTEST This allows testing of all interconnections to the device When the EXTEST instruction is latched in the instruction register the following actions occur Once enabled via the Update IR state the parallel outputs of all digital output pins are driven The boundary scan register is connected between JTDI and JTDO The Capture DR will sample all digital inputs into the boundary scan register CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO The outputs will not change during the CLAMP instruction HIGHZ All digital outputs of the device are placed in a high impedance state The BYPASS register is connected between JT
195. UT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC 4 0 eo Bit 7 Input Level Under Threshold ILUT This bit is set whenever the input level at RRING falls below the threshold set by the value in TR CCR4 4 through TR CCR4 7 The level must remain below the programmed threshold for approximately 50ms for this bit to be set This is a double interrupt bit Section 9 7 Bit 6 Timer Event TIMER Follows the error counter update interval as determined by the ECUS bit in the error counter configuration register TR ERCNT T1 set on increments of 1 second or 42ms based on RCLKO E1 set on increments of 1 second or 62 5ms based on RCLKO Bit 5 Receive Signaling Change of State Event RSCOS Set when any channel selected by the receive signaling change of state interrupt enable registers TR RSCSE1 through TR RSCSE4 changes signaling state Bit 4 Jitter Attenuator Limit Trip Event JALT Set when the jitter attenuator FIFO reaches to within 4 bits of its useful limit This bit is cleared when read Useful for debugging jitter attenuation operation Bit 3 Line Interface Receive Carrier Loss Condition LRCL Set when the carrier signal is lost This is a double interrupt bit Section 9 7 Bit 2 Transmit Current Limit Exceeded Condition TCLE Set when the 50mA RMS current limiter is activated whether the current limiter is enabled or not This is a double interrupt bit Section 9 7
196. VC2 PCVC1 PCVCO h TR PCVCR2 046 FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 59 58 h TR FOSCR1 047 FOS7 FOS6 FOS5 54 FOS3 FOS2 FOS1 FOSO h TR FOSCR2 048 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 h TR EBCR1 049 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EBO h TR EBCR2 04A LTS LIUC LLB RLB PLB FLB h TR LBCR 04B CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 h TR PCLR1 04C CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 h TR PCLR2 04D CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 h TR PCLR3 04E CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 h TR PCLR4 04 TR ESCR TESALGN TESR TESMDM TESE RESALGN RESR RESMDM RESE 127 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver ADD NAME BiT 7 6 5 Bit 4 Bir 3 BiT 2 Bir 1 R h n TRASH Transmit Signaling Bit Format Changes With Operating Mode See Register Definition ae TRITS2 Transmit Signaling Bit Format Changes With Operating Mode See Register Definition E uius Transmit Signaling Bit Format Changes With Operating Mode See Register Definition e TET Transmit Signaling Bit Format Changes With Operating Mode See Register Definition TRUE Transmit Signaling Bit Format Changes With Operating Mode See Register Definition EU Transmit Signaling Bit Format Changes With Operating Mode See Register Definition d TS Transmit Signaling Bit Format Changes With Operating Mod
197. W MIIB 0018h Oe Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0019h 23 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 001Ah 15 8 MIID15 MIID14 MIID13 MIID12 MIID11 MIID10 MIIDO9 MIIDO8 001Bh 7 0 MIIDO7 MIIDOG MIIDO5 MIIDO4 MIIDO3 MIIDO2 MIIDO1 MIIDOO 001Ch incon CR prs PT14 PT13 PT12 11 10 PTOO PTOB 001Dh 23 16 PTO7 5 PT04 2 PTO1 PTOO 001Eh 15 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 001Fh 7 0 Reserved Reserved Reserved Reserved Reserved PCF FCE FCB 100h ey S Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 101h 23 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 102h 15 8 Reserved Reserved MXFRM10 MXFRM9 MXFRM8 MXFRM7 MXFRM6 MXFRM5 103h 7 0 MXFRM4 MXFRM3 MXFRM2 MXFRM1 MXFRMO Reserved Reserved Reserved 10Ch RESERVED Ad Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved initialize to FF 10Dh RESERVED rpm Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved initialize to FF 10Eh RESERVED TETEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved initialize to FF 10Fh RESERVED pres Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved initialize to FF 110h RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved
198. Y OVERWRITTEN IN THE TRANSMIT FORMATTER WITHTHE CAS MF ALIGNMENT NIBBLE 0000 NOTE 6 SHOWN IS ATNAF FRAME BOUNDARY Figure 12 27 Transmit Side Boundary Timing TSYSCLK 1 544MHz Elastic Store Enabled TSYSCLK CHANNEL 23 CHANNEL 24 CHANNEL 1 TSERI o d ASBMSB j TSSYNC TCHCLK TCHBLK NOTE 1 THE F BIT POSITION IN THE TSERI DATAIS IGNORED NOTE 2 TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 311 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 28 Transmit Side Boundary Timing TSYSCLK 2 048MHz Elastic Store Enabled TSYSCLK CHANNEL 31 CHANNEL 32 CHANNEL 1 Y TSERI TSSYNC 2 CHANNEL 32 CHANNEL 1 22 CHANNEL 31 TCHCLK TCHBLK NOTE 1 TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31 312 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to Vss except 0 5V to 5 5V Supply Voltage VDD3 3 Range with Respect to 0 3V to 3 6V Supply Voltage VDD1 8 with Respect to 0 0 3V to 2 0V Ambient Operating Temperature
199. YNC IS ENABLED TR IOCRL6 1 NOTE 3 RSYNC IN THE MULTIFRAME MODE TR IOCRL5 1 Figure 12 11 Receive Side ESF Timing FRAME RSYNC RFSYNC RSYNC RSYNC NOTE 1 RSYNC IN FRAME MODE TR IOCR1 4 0 AND DOUBLE MDE FRAME SYNC IS NOT ENABLED TR JOCR1 6 0 NOTE 2 RSYNC IN FRAME MODE TR IOCR1 4 0 AND DOUBLE MDE FRAME SYNC IS ENABLED TR IOCR16 1 NOTE 3 RSYNC IN MULTIFRAME MODE TR IOCR14 1 303 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 12 12 Receive Side Boundary Timing Elastic Store Disabled RCLKO SN NN M CHANNEL 23 CHANNEL 24 CHANNEL 1 RSERO LSB MSB LSB MSB POL RSYNC RFSYNC CHANNEL 23 CHANNEL 24 CHANNEL 1 RSIG A C A DIB A B YCIA DIB RCHCLK RCHBLK NOTE 1 RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 Figure 12 13 Receive Side 1 544MHz Boundary Timing Elastic Store Enabled RSYSCLK CHANNEL 23 CHANNEL 24 CHANNEL 1 RSERO JLSBMSB F MSB RSYNC
200. YNCE RESYNC Default 0 0 0 0 0 0 0 0 Bit 6 Auto Resync Criteria ARC 0 resync OOF or RCL event 1 resync on OOF only Bits 4 5 Out of Frame Select Bits OOF2 OOF1 OOF2 OOF1 Out Of Frame Criteria 0 0 2 4 frame bits in error 0 1 2 5 frame bits in error 1 0 2 6 frame bits in error 1 1 2 6 frame bits in error Bit 3 Sync Criteria SYNCC In D4 Framing Mode 0 search for Ft pattern then search for Fs pattern 1 cross couple Ft and Fs pattern In ESF Framing Mode 0 7 search for FPS pattern only 1 search for FPS and verify with CRC6 Bit 2 Sync Time SYNCT 0 qualify 10 bits 1 qualify 24 bits Bit 1 Sync Enable SYNCE 0 auto resync enabled 1 auto resync disabled Bit 0 Resynchronize RESYNC When toggled from low to high a resynchronization of the receive side framer is initiated Must be cleared and set again for a subsequent resync 204 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR T1RCR2 Register Description T1 Receive Control Register 2 Register Address 04h Bit 7 6 5 4 3 2 1 0 Name RFM RB8ZS RSLC96 RZSE RJC RD4YM Default 0 0 0 0 0 0 0 0 Bit 6 Receive Frame Mode Select RFM 0 D4 framing mode 1 ESF framing mode Bit 5 Receive B8ZS Enable RB8ZS 0 B8ZS disabled 1 B8ZS enabled Bit 4 Receive SLC 96 Enable RSL C96 Only set this bit to a 1 in D4 SLC 96 framing applica
201. a from the network The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications The jitter attenuator removes phase jitter from the transmitted or received signal The crystal less jitter attenuator requires only a 2 048MHz MCLK for both E1 and T1 applications with the option of using a 1 544MHz MCLK in T1 applications and can be placed in either transmit or receive data paths An additional feature of the LIU is a CMI coder decoder for interfacing to optical networks On the transmit side clock data and frame sync signals are provided to the framer by the backplane interface section The framer inserts the appropriate synchronization framing patterns alarm information calculates and inserts the CRC codes and provides the B8ZS HDB3 zero code suppression and AMI line coding The receive side framer decodes AMI B8ZS and HDB3 line coding synchronizes to the data stream reports alarm information counts framing coding CRC errors and provides clock data and frame sync signals to the backplane interface section 41 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Both the transmit and receive path of the integrated T1 E1 J1 transceiver also have two HDLC controllers The HDLC controllers transmit and receive data through the framer block The HDLC controllers can be assigned to any time slot gro
202. a from the TR TSa7 register into the transmit data stream 1 insert data from the TR TSa register into the transmit data stream Bit 0 Additional Bit 8 Insertion Control Bit Sa8 0 do not insert data from the TR TSa8 register into the transmit data stream 1 insert data from the 5 8 register into the transmit data stream Register Name TR BAWC Register Description BERT Alternating Word Count Rate Register Address DBh Bit 7 6 5 4 3 2 1 0 ACNT 7 6 5 ACNT4 ACNT3 ACNT2 ACNT1 ACNTO Default __ 0 Bits 0 7 Alternating Word Count Rate Bits 0 to 7 ACNTO to ACNT7 ACNTO is the LSB of the 8 bit alternating word count rate counter 290 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR BRP1 Register Description BERT Repetitive Pattern Set Register 1 Register Address DCh Bit 7 6 5 4 3 2 1 0 Name RPAT7 RPAT6 RPAT5 RPAT4 RPAT3 RPAT2 RPAT1 RPATO Bero o 0c iL 9p Bits 0 7 BERT Repetitive Pattern Set Bits 0 to 7 RPATO to RPAT7 RPATO is the LSB of the 32 bit repetitive pattern set Register Name TR BRP2 Register Description BERT Repetitive Pattern Set Register 2 Register Address DDh Bit 7 6 5 4 3 2 1 0 Name RPAT15 RPAT14 RPAT13 RPAT12 RPAT11 RPAT10 RPAT9 RPAT8 Default O0 Bits 0 7 BERT Repetitive Pattern Set Bits 8 to 15 RPAT8 to RPAT15 Register Name TR BRP3 Register Description BER
203. ace Timing MDC MDIO MDIO AN AMOR 319 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 5 Transmit WAN Interface Table 13 10 Transmit WAN Interface Note 1 Figure 13 6 PARAMETER SYMBOL MIN TYP MAX UNITS TCLKE Frequency 52 MHz TCLKE Period t1 19 2 ns TCLKE Low Time 2 8 ns TCLKE High Time t3 8 ns TCLKE to TSERO Output Delay t4 3 10 ns TCLKE to TBSYNC Setup Time tb 3 5 ns TBSYNC Hold Time t6 7 ns TCLKE to TDEN Output Delay t7 3 5 ns Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 6 Transmit WAN Interface Timing t2 TCLKE lt gt lt gt TBSYNC AP 320 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 6 Receive WAN Interface Table 13 11 Receive WAN Interface Note 1 Figure 13 7 PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19 2 ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSERI Setup Time t4 7 ns RDEN Setup Time t4 7 ns RBSYNC Setup Time t4 7 ns RDEN Setup Time t4 7 ns RBSYNC Setup Time t4 7 ns RSERI Hold Time t5 2 ns RBSYNC Hold Time t5 2 ns RDEN Hold Time t5 2 ns RBSYNC Hold Time t5 2 ns Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 7 Receive WAN Interface Timing r gt
204. ackplane mode Access to the data streams in between the framer formatter and the elastic stores User selectable synthesized clock output 14 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 2 14 Test and Diagnostics IEEE 1149 1 support Programmable on chip bit error rate tester BERT Pseudorandom patterns including QRSS User defined repetitive patterns Daly pattern Error insertion single and continuous Total bit and errored bit counts Payload error insertion Error insertion in the payload portion of the T1 frame in the transmit path Errors can be inserted over the entire frame or selected channels Insertion options include continuous and absolute number with selectable insertion rates F bit corruption for line testing Loopbacks remote local analog and per channel loopback 15 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 2 15 Specifications Compliance The DS33R11 meets relevant telecommunications specifications The following table provides the specifications and relevant sections that are applicable to the DS33R11 Table 2 1 T1 Related Telecommunications Specifications IEEE 802 3 2002 CSMA CD access method and physical layer specifications RFC1662 PPP in HDLC like Framing RFC2615 PPP over SONET SDH X 86 Ethernet over LAPS RMII Industry Implementation Agreement for Reduced MII Interface Sept 1997 ANSI T1 403 1995 T1 231 19
205. after the SU RQHT bit is set If the queue remains above the high threshold received frames will continue to be jammed This jam sequence is stopped when the queue falls below the high threshold 9 13 3 Host Managed Flow Control Although automatic flow control is recommended flow control by the host processor is also possible By utilizing the high watermark interrupts the host processor can manually issue pause frames or jam incoming packets to exert backpressure on the transmitting node Pause frames can be initiated with SU MACFCR FCB bit Jam sequences can be initiated be setting SU GCR JAME The host can detect pause frames by monitoring SU RFSB3 UF and SU RFSB3 CF Jammed frames will be indistinguishable from packet collisions 55 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 14 Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY The interface consists of a 10 100Mbit s MII RMII interface and an Ethernet MAC In RMII operation the interface contains seven signals with a reference clock of 50 MHz In operation the interface contains 17 signals and a clock reference of 25MHz The DS33R11 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS If the port is configured for in DCE mode REF CLK must be 25 2 The DS33R11 will internally generate the TX and RX CLK outputs at 25MHz for 100Mbps 2 5MHz for 10Mbps required for DCE
206. ame TR SR5 Register Description Status Register 5 Register Address 1Eh Bit 7 6 5 4 3 2 1 0 Name TESF TESEM TSLIP RESF RESEM RSLIP Defaut 9 o o 9 o o o 9 Bit 5 Transmit Elastic Store Full Event TESF Set when the transmit elastic store buffer fills and a frame is deleted Bit 4 Transmit Elastic Store Empty Event TESEM Set when the transmit elastic store buffer empties and a frame is repeated Bit 3 Transmit Elastic Store Slip Occurrence Event TSLIP Set when the transmit elastic store has either repeated or deleted a frame Bit 2 Receive Elastic Store Full Event RESF Set when the receive elastic store buffer fills and a frame is deleted Bit 1 Receive Elastic Store Empty Event RESEM Set when the receive elastic store buffer empties and a frame is repeated Bit 0 Receive Elastic Store Slip Occurrence Event RSLIP Set when the receive elastic store has either repeated or deleted a frame 223 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR5 Register Description Interrupt Mask Register 5 Register Address 1Fh Bit 7 6 5 4 3 2 1 0 Name TESF TESEM TSLIP RESF RESEM RSLIP Defaut 0 o 0 9 o o o 9 Bit 5 Transmit Elastic Store Full Event TESF 0 interrupt masked 1 interrupt enabled Bit 4 Transmit Elastic Store Empty Event TESEM 0 interrupt masked 1 interrupt enabled Bit 3 Transmit Elastic Store Slip
207. aming pattern in the D4 mode or errors in the FPS framing pattern in the ESF mode When TR FOSCR is operated in this mode it is disabled during receive loss of synchronization RLOS 1 conditions Table 10 8 shows what the FOSCR is capable of counting Table 10 8 T1 Frames Out of Sync Counting Arrangements COUNT MOS OR F BIT ERRORS COUNTED IN THE FOSCRs TR ERCNT 1 Number of multiframes out of sync FRAMING MODE TR T1RCR1 3 Errors in the Ft pattern Number of multiframes out of sync Errors in the FPS pattern In E1 mode TR FOSCR counts word errors in the FAS in time slot 0 This counter is disabled when RLOS is high FAS errors are not counted when the framer is searching for FAS alignment and or synchronization at either the CAS or CRC4 multiframe level Since the maximum FAS word error count in a one second period is 4000 this counter cannot saturate The frames out of sync count register 1 TR FOSCR1 is the most significant word and TR FOSCR2 is the least significant word of a 16 bit counter that records frames out of sync 10 7 4 E Bit Counter TR EBCR This counter is only available E1 mode E bit count register 1 TR EBCR1 is the most significant word and TR EBCR2 is the least significant word of a 16 bit counter that records far end block errors FEBE as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe These count registers increment once each time the received E bit is s
208. an be used when the elastic store s system clock is locked to its network clock i e RCLKO locked to RSYSCLK for the receive side and TCLKT locked to TSYSCLK for the transmit side TR ESCR 5 and TR ESCR 1 enable the transmit and receive elastic store minimum delay modes When enabled the elastic stores are forced to a maximum depth of 32 bits instead of the normal two frame depth This feature is useful primarily in applications that interface to 2 048MHz bus Certain restrictions apply when minimum delay mode is used In addition to the restriction mentioned above RSYNC must be configured as an output when the receive elastic store is in minimum delay mode TSYNC must be configured as an output when transmit minimum delay mode is enabled In a typical application RSYSCLK and TSYSCLK are locked to RCLKO and RSYNC frame output mode is connected to TSSYNC frame input mode of the slip contention logic in the framer is disabled since slips cannot occur On power up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals the elastic store reset bits TR ESCR 2 and TR ESCR 6 should be toggled from a 0 to a 1 to ensure proper operation 89 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 13 G 706 Intermediate CRC 4 Updating E1 Mode Only The device can implement the G 706 CRC 4 recalculation at intermediate path points When this mode is enabled the data stream presented a
209. and tr tr 25 ns Fall Times Delay TCLKO to TPOSO TNEGO Valid top 50 ns Delay TCLKT to TESO UT UTDO Valid tp 50 ns Delay TCLKT to TCHBLK TCHCLK t 50 js TSYNC 82 Delay TSYSCLK to TCHCLK TCHBLK tps 22 ns Note 1 Timing parameters in this table are guaranteed by design GBD Note 2 TSYSCLK 1 544MHz Note 3 TSYSCLK 2 048MHz 332 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 17 Transmit Side Timing gg TCLKT gt 4p TESO X TSERI TDATA 02 TCHCLK TCHBLK TSYNC TSYNC NOTE 1 TSYNC IS IN THE OUTPUT MODE 1 1 1 NOTE 2 TSYNC IS IN THE INPUT MODE IOCR1 1 0 NOTE 3 TSERI IS SAVPLED ON THE FALLING EDGE OF TCLKT WHEN THE TRANSMIT SIDE ELASTIC STORE IS DISABLED NOTE 4 TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLKT WHEN THE TRANSMIT SIDE ELASTIC STORE IS DISABLED 333 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 13 18 Transmit Side Timing Elastic Store Enabled us TSYSCLK TSER etna TCHCLK ri ees oe gt TCHBLK TSSYNC NOTE 1 TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED NOTE 2 TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED Figure 13 19 Transmit Line Interface Timing TDCLKO TPOSO TNEGO gt tipp di
210. are left to be inserted Register Name TR NOEL1 Register Description Number of Errors Left 1 Register Address EEh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Deus 10 0 0o 0o 0 o0 o 205 Bits 0 7 Number of Errors Left Counter Bits 0 to 7 CO to C7 Bit CO is the LSB of the 10 bit counter Register Name TR NOEL2 Register Description Number of Errors Left 2 Register Address EFh Bit 7 6 5 4 3 2 1 0 C9 C8 Defaut 0 0 oO 0 0 Bits 0 1 Number of Errors Left Counter Bits 8 to 9 C8 to C9 Bit C9 is the MSB of the 10 bit counter 299 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 12 FUNCTIONAL TIMING 12 1 Functional Serial Timing The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces TDEN is an input signal that can be used to enable or block the TSERO data The shaded bits are not clocked by the DS33R11 The TDEN must occur one bit before the effected bit in the TSERO stream Note that polarity of the TDEN is selectable through LI TSLCR In the figure below TDEN is active low allowing the bits to clock and inactive high causing the next data bit not be clocked TCLKE can be gapped as shown in the following figure Similarly the receiver function is governed by RCLKI RDEN and RSERI RSERI data will not be provided to the receiver for the bits blocked wh
211. ark is reached again T1 E1 J1 Receive Loss of Sync Loss of Transmit Clock A dual function output that is controlled by the CCR1 0 control bit This pin RLOS LTC N1 be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the pin has not been toggled for 5us T1 E1 J1 Receive Carrier Loss Set high when the T1 E1 J1 line RCL B5 9 interface detects a carrier loss T1 E1 J1 Receive Signaling Freeze Output Set high when the RSIGF P3 signaling data is frozen by either automatic or manual intervention Used to alert downstream equipment of the condition 36 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION SYSTEM CLOCKS System Clock In for Ethernet Mapper 100MHz System Clock input to the DS33R11 used for internal operation This clock is SYSCLKI V8 buffered and provided at SDCLKO for the SDRAM interface The DS33R11 also provides a divided version output at the REF CLKO pin A clock supply with x100ppm frequency accuracy is suggested Master Clock Input for the T1 E1 J1 Transceiver A 50ppm clock source This clock is used internally for both clock data MCLK HA recovery and for the jitter attenuator for both T1 and E1 modes The clock rate can be 16 384MHz 8 192MHz 4 096 2 or 2 048MHz When using the transceiver in T1 only operation a 1 544MHz 50ppm c
212. ata into the F bit position framed 1 BERT does source data into the F bit position unframed Bit 1 BERT Direction BERTDIR 0 network BERT transmits toward the network TTIP and TRING and receives from the network RTIP and RRING The BERT pattern can be looped back to the receiver internally by using the framer loopback function 1 system BERT transmits toward the system backplane RSERO and receives from the system backplane TSERI Bit 0 BERT Enable BERTEN 0 BERT disabled 1 BERT enabled 296 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR ERC Register Description Error Rate Control Register Register Address EBh Bit 7 6 5 c 3 2 1 0 Name WNOE ER3 ER2 ER1 ERO Default up Bit 7 Write NOE Registers WNOE If the host wishes to update to the TR NOEx registers this bit must be toggled from a 0 to a 1 after the host has already loaded the prescribed error count into the TR NOEx registers The toggling of this bit causes the error count loaded into the TR NOEx registers to be loaded into the error insertion circuitry on the next clock cycle Subsequent updates require that the WNOE bit be set to 0 and then 1 once again Bit 4 Constant Errors CE When this bit is set high and the ERO to ER3 bits are not set to 0000 the error insertion logic ignores the number of error registers TR NOE1 TR NOE2 and generates errors constantly
213. ation 5 detection and generation E1 ETS 300 011 RAI generation G 965 V5 link detect Ability to monitor one DSO channel in both the transmit and receive paths In band repeating pattern generators and detectors o Three independent generators and detectors o from 1 to 8 bits or 16 bits in length RCL RLOS RRA and RAIS alarms interrupt on change of state Flexible signaling support o Software or hardware based o Interrupt generated on change of signaling data o Receive signaling freeze on loss of sync carrier loss or frame slip Addition of hardware pins to indicate carrier loss and signaling freeze Automatic RAI generation to ETS 300 011 specifications Access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support o Ability to calculate and check CRC6 according to the Japanese standard o Ability to generate Yellow Alarm according to the Japanese standard 2 13 TDM Bus Dual two frame independent receive and transmit elastic stores o Independent control and clocking o Controlled slip capability with status o Minimum delay mode supported Programmable output clocks for fractional T1 E1 HO and H12 applications Hardware signaling capability o Receive signaling reinsertion to a backplane multiframe sync o Availability of signaling in a separate PCM data stream o Signaling freezing Ability to pass the T1 F bit position through the elastic stores in the 2 048 2 b
214. ator is loaded with a pattern value before pattern generation starts The pattern value is programmable 0 2 1 When PRBS and QRSS patterns are generated the seed value is all ones 64 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 16 4 1 Error Insertion Error insertion inserts errors into the outgoing pattern data stream Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interface If pattern inversion is enabled the data stream is inverted before the overhead stuff bits are inserted Pattern inversion is programmable on or off 9 16 4 2 Performance Monitoring Update All counters stop counting at their maximum count A counter register is updated by asserting low to high transition the performance monitoring update signal PMU During the counter register update process the performance monitoring status signal PMS is de asserted The counter register update process consists of loading the counter register with the current count resetting the counter forcing the zero count status indication low for one clock cycle and then asserting PMS No events shall be missed during an update procedure 9 17 Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering FCS processing packet error insertion stuffing packet abort sequence insertion inter frame padding and packet scrambling The data o
215. bit errors and counts the incoming bits An OOS condition is declared when the synchronization state machine is not in the state An OOS condition is terminated when the synchronization state machine is in the Sync state Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output If they do not match a bit error is declared and the bit error and bit counts are incremented If they match only the bit count is incremented The bit count and bit error count are not incremented when an OOS condition exists 9 16 4 Pattern Generation Pattern Generation generates the outgoing test pattern and passes it onto Error Insertion The transmit pattern generator is a 32 bit shift register that shifts data from the least significant bit LSB or bit 1 to the most significant bit MSB or bit 32 The input to bit 1 is the feedback For a PRBS pattern generating polynomial x x 1 the feedback is an XOR of bit n and bit y For a repetitive pattern length n the feedback is bit n The values for n and y are individually programmable The output of the receive pattern generator is the feedback If QRSS is enabled the feedback is an XOR of bits 17 and 20 and the output is forced to one if the next 14 bits are all zeros QRSS is programmable on or off For PRBS and QRSS patterns the feedback is forced to one if bits 1 through 31 are all zeros When a new pattern is loaded the pattern gener
216. ccess these message fields through the TR TFDL and TR RFDL registers Refer to Application Note 345 DS2141A DS2151 DS2152 SLC 96 for a detailed description about implementing an SL C 96 function 98 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 19 Programmable In Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length This function is available only in T1 mode To transmit a pattern the user loads the pattern into the transmit code definition registers TR TCD1 and TR TCD2 and selects the proper length of the pattern by setting the TCO and TC1 bits in the in band code control TR IBCC register When generating a 1 2 4 8 or 16 bit pattern both transmit code definition registers must be filled with the proper code Generation of a 3 5 6 and 7 bit pattern only requires TR TCD1 to be filled Once this is accomplished the pattern is transmitted as long as the TLOOP control bit TR T1CCR1 0 is enabled Normally unless the transmit formatter is programmed to not insert the F bit position the framer overwrites the repeating pattern once every 193 bits to send the F bit position For example to transmit the standard loop up code for CSUs which is a repeating pattern of 10000100001 set TR TCD1 80h TR IBCC 0 and TR T1CCR1 0 1 The framer has three programmable pattern detec
217. ceive side The receive side allows the user to configure the transceiver for 750 1000 or 1200 receive termination by setting the RT1 TR LIC4 1 and RTO TR LIC4 0 bits When using the internal termination feature the resistors labeled R in Figure 10 7 should be 600 each If external termination is used RT1 and RTO should be set to 0 and the resistors labeled in Figure 10 7 should be 37 50 500 or 600 each depending on the line impedance There are two ranges of user selectable receive sensitivity for 1 and E1 The bit of TR LIC1 TR LIC 1 4 selects the full or limited sensitivity The resultant E1 or T1 clock derived from MCLK is multiplied by 16 through an internal PLL and fed to the clock recovery system The clock recovery system uses the clock from the PLL circuit to form a 16 times over sampler that is used to recover the clock and data This over sampling technique offers outstanding performance to meet jitter tolerance specifications shown in Figure 10 10 Normally the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI HDB3 or T1 AMI B8ZS waveform presented at the RTIP and RRING inputs If the jitter attenuator is placed in the receive path as is the case in most applications the jitter attenuator restores the RCLKO to an approximate 50 duty cycle If the jitter attenuator is either placed in the transmit path or is disabled the RCLKO output can exhibit slightly shorter high cycles of the clock Th
218. ching for the CAS MF alignment word This is a read only non latched real time bit It is not necessary to precede the read of this bit with a write Bit 0 CRC4 MF Sync Active CRC4SA Set while the synchronizer is searching for the CRC4 MF alignment word This is a read only non latched real time bit It is not necessary to precede the read of this bit with a write Register Name TR H1RC TR H2RC Register Description HDLC 1 Receive Control HDLC 2 Receive Control Register Address 31h 32h Bit 7 6 5 4 3 2 1 0 Name RHR RHMS RSFD poraa ESTEE VERE QOO Bit 7 Receive HDLC Reset RHR Resets the receive HDLC controller and flushes the receive FIFO Must be cleared and set again for a subsequent reset 0 normal operation 1 7 reset receive HDLC controller and flush the receive FIFO Bit 6 Receive HDLC Mapping Select RHMS 0 7 receive HDLC assigned to channels 1 receive HDLC assigned FDL T1 mode Sa bits mode Bits 1 5 Unused must be set to 0 or proper operation Bit 0 Receive 57 Fill In Signal Unit Delete RSFD 0 normal operation all FISUs are stored in the receive FIFO and reported to the host 1 When a consecutive FISU having the same BSN the previous FISU is detected it is deleted without host intervention 233 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR E1RCR1 Register
219. cket with an abort indication is detected Bit 5 Receive Invalid Packet Detected Latched RIPDL This bit is set when a packet with a noninteger number of bytes is detected Bit 4 Receive Small Packet Detected Latched RSPDL This bit is set when a packet smaller than the minimum packet size is detected Bit 3 Receive Large Packet Detected Latched RLPDL This bit is set when a packet larger than the maximum packet size is detected Bit 2 Receive FCS Errored Packet Count Latched REPCL This bit is set when the REPC bit in the RPPSR register transitions from zero to one Bit 1 Receive Aborted Packet Count Latched RAPCL This bit is set when the RAPC bit in the RPPSR register transitions from zero to one Bit 0 Receive Size Violation Packet Count Latched RSPCL This bit is set when the RSPC bit in the RPPSR register transitions from zero to one 163 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description LI RPPSRIE Receive Packet Processor Status Register Interrupt Enable Register Address Bit 7 6 5 4 3 2 1 0 Name REPIE RAPIE RIPDIE RSPDIE RLPDIE REPCIE RAPCIE RSPCIE Default 0 0 0 0 0 0 0 0 Bit 7 Receive FCS Errored Packet Interrupt Enable REPIE This bit enables an interrupt if the REPL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit 6 Receive Aborted Packet Interrupt Enable RAPIE
220. counter to increment 2 32 1 times at the maximum frame rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 194 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description Register Address 0204h Bit Name Default 0205h Bit Name Default 0206h Bit Name Default 0207h Bit Name Default SU RxFrmOkCtr MAC Frames Received OK Counter 0204h indirect 31 30 29 28 27 26 25 24 1 RXFRMOK30 RXFRMOK29 RXFRMOK28 RXFRMOK27 RXFRMOK26 RXFRMOK25 RXFRMOK24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 23 RXFRMOK22 RXFRMOK21 RXFRMOK20 RXFRMOK19 RXFRMOK18 RXFRMOK17 RXFRMOK16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 09 08 RXFRMOK15 RXFRMOK14 RXFRMOK13 RXFRMOK12 RXFRMOK11 RXFRMOK10 RXFRMOK9 RXFRMOK8 0 0 0 0 0 0 0 0 07 06 05 04 03 02 01 00 RXFRMOK RXFRMOK6 RXFRMOK5 RXFRMOK4 RXFRMOK3 RXFRMOK2 RXFRMOK1 RXFRMOKO 0 0 0 0 0 0 0 0 Bits 0 31 Frames Received OK Counter RXFRMOK 0 31 32 bit value indicating the number of frames received and determined to be valid Each time a valid frame is received this counter is incremented by 1 This counter resets only upon
221. cription below Register Name Register Description LI RSPCB1 Receive Size Violation Packet Count Byte 1 Register Register Address 115h Bit 7 6 5 4 3 2 1 0 Name RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Size Violation Packet Count RSPC 15 8 Eight bits of a 24 bit value Register description below Register Name LI RSPCB2 Register Description Receive Size Violation Packet Count Byte 2 Registers Register Address 116h Bit 7 6 5 4 3 2 1 0 Name RSPC23 RSPC22 RSPC21 RSPC20 RSPC19 RSPC18 RSPC17 RSPC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Size Violation Packet Count RSPC 23 16 These twenty four bits indicate the number of packets received with a packet size violation below minimum above maximum or noninteger number of bytes The byte count for these packets is included in the receive aborted byte count register REBCR 168 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description LI RBCO Receive Byte Count 0 Register Register Address Bit 7 6 5 4 3 2 1 0 Name RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive By
222. ct which channels can cause a change of state indication The change of state is indicated in status register 5 TR SR1 5 If signaling integration TR CCR1 5 is enabled then the new signaling state must be constant for three multiframes before a change of state is indicated The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the 1 5 bit The signaling integration mode is global and cannot be enabled on a channel by channel basis The user can identity which channels have undergone a signaling change of state by reading the TR RSINFO1 TR RSINFOA registers The information from these registers inform the user which TR RSx register to read for the new signaling data All changes are indicated the TR RSINFO1 TR RSINFOA registers regardless of the TR RSCSE1 TR RSCSEA registers 82 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 9 2 Hardware Based Receive Signaling In hardware based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin RSIG is a signaling PCM stream output on a channel by channel basis from the signaling buffer The signaling data T1 robbed bit or E1 TS16 is still present in the original data stream at RSERO The signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the
223. cted 1 E1 mode selected Bit 6 Line Interface Reset LIRST Setting this bit from a0 to a 1 initiates an internal reset that resets the clock recovery state machine and recenters the jitter attenuator Normally this bit is only toggled on power up Must be cleared and set again for a subsequent reset Bit 5 Insert IBPV A 0 to 1 transition on this bit causes a single BPV to be inserted into the transmit data stream Once this bit has been toggled from a to a 1 the device waits for the next occurrence of three consecutive 1s to insert the BPV This bit must be cleared and set again for a subsequent error to be inserted Bit 4 Transmit Unframed All Ones 1 The polarity of this bit is set such that the device transmits an all ones pattern on power up or device reset This bit must be set to a 1 to allow the device to transmit data The transmission of this data pattern is always timed off of the JACLK 0 transmit all ones at TTIP and TRING 1 transmit data normally Bit 3 Jitter Attenuator Mux JAMUX Controls the source for JACLK 0 JACLK sourced from MCLK 2 048MHz or 1 544MHz at MCLK 1 JACLK sourced from internal PLL 2 048MHz at MCLK Short Circuit Limit Disable ETS 1 SCLD Controls the 50mA RMS current limiter 0 enable 50mA current limiter 1 disable 50mA current limiter Bit 0 Custom Line Driver Select CLDS Setting this bit to a 1 redefines the operation of the transmit line driver
224. ctions for operation are shown in Figure 9 5 and Figure 9 6 9 15 2 RMII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high RMII interface operates synchronously from the external 50MHz reference REF CLK Only seven signals are required The following figure shows the RMII architecture Note that DCE mode is not supported for RMII mode and RMII is valid only for full duplex operation Figure 9 7 RMII Interface DS33R11 External PHY TXD 1 0 TX EN CRS DV RXD 1 0 REF CLK 61 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 15 3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs each with 32 registers The MII block communicates with the external PHY using 2 wire serial interface composed of MDC serial clock and MDIO for data The MDIO data is valid on the rising edge of the MDC clock The Frame format for the MII Management Interface is shown Figure 9 8 The read write control of the MII Management is accomplished through the indirect SU MACMIIA MII Management Address Register and data is passed through the indirect SU MACMIID Data Register These indirect registers are accessed through the MAC Control Registers defined in Table 9 6 The MDC clock is internally generated and runs at 1 67MHz Figure 9 8 MII Managem
225. d Bit 1 Transmit Queue for Connection Exceeded High Threshold Latched Status 5 This bit is set if the transmit queue crosses the High Watermark This register is cleared after a read Bit 0 Transmit Queue for Connection Exceeded Low Threshold Latched Status TQLTLS This bit is set if the transmit queue crosses the Low Watermark This register is cleared after a read 173 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII MII bus operation and establish the MAC parameters as required by the user The MAC Registers cannot be addressed directly from the Processor port The registers below are used to perform indirect read or write operations to the MAC registers The MAC Status Registers are shown in Table 11 7 Accessing the MAC Registers is described in the Section 9 15 11 6 1 Ethernet Interface Register Bit Descriptions Register Name Register Description SU MACRADL MAC Read Address Low Register Register Address 140h Bit 7 6 5 4 3 2 1 0 Name MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRAO Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Read Address MACRAO 7 Low byte of the MAC indirect register address Used only for read operations Register Name Register Description SU MACRADH MAC Read Address High Register Regi
226. d detect pseudorandom and repeating bit patterns It is used to test and stress data communication links and it is capable of generating and detecting the following patterns pseudorandom patterns 2E7 2E11 2E15 and QRSS Arepetitive pattern from 1 to 32 bits in length Alternating 16 bit words that flip every 1 to 256 words Daly pattern The BERT receiver has a 32 bit bit counter and a 24 bit error counter The BERT receiver reports three events a change in receive synchronizer status a bit error being detected and if either the bit counter or the error counter overflows Each of these events can be masked within the BERT function through the BERT control register 1 TR BC1 If the software detects that the BERT has reported an event then the software must read the BERT information register BIR to determine which event s has occurred To activate the BERT block the host must configure the BERT mux through the TR BIC register 10 25 1 BERT Status 5 9 contains the status information on the BERT function The host can be alerted through this register when there is a BERT change of state A major change of state is defined as either a change in the receive synchronization i e the BERT has gone into or out of receive synchronization a bit error has been detected or an overflow has occurred in either the bit counter or the error counter The host must read status register 9 TR SR9 to determine the change of state
227. d loop to generate low jitter clocks Common applications include generation of port and backplane system clocks The TR CCR2 register is used to enable TR CCR2 0 and select TR CCR2 1 and TR CCR2 2 the clock frequency of the BPCLK pin 10 28 Fractional T1 E1 Support The transceiver can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1 E1 or ISDN PRI applications The receive and transmit paths have independent enables Channel formats supported include 56kbps and 64kbps This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins Setting TR CCR3 0 1 causes the RCHCLK pin to output a gapped clock as defined by the receive fractional T1 E1 function of the TR PCPR register Setting TR CCR3 2 1 causes the pin to output a gapped clock as defined by the transmit fractional T1 E1 function of the TR PCPR register TR CCR3 1 and TR CCR3 3 can be used to select between 64kbps and 56kbps operation See Section 10 2 for details about programming the per channel function In T1 mode no clock is generated at the F bit position When 56kbps mode is selected the LSB clock in the channel is omitted Only the seven most significant bits of the channel have clocks 112 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 29 T1 E1 J1 Transmit Flow Diagrams Figure 10 17 T1 J1
228. de Register Write SRAS W9 SDRAM Row Address Strobe Active low output used to latch the row address on rising edge of SDCLKO It is used with commands for Bank Activate Precharge and Mode Register Write SDCS V10 SDRAM Chip Select Active low output enables SDRAM access SWE W10 SDRAM Write Enable This active low output enables write operation and auto precharge SBA 0 Y11 SBA 1 V11 SDRAM Bank Select These 2 bits select 1 of 4 banks for the read write precharge operations Note SDRAM operations are controlled entirely by the DS33R11 No user programming for SDRAM buffering is required 29 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION SDATA 0 W2 SDATA 1 YA SDATA 2 Y2 SDATA 3 Y5 SDATA 4 Y3 SDATA 5 W5 SDATA 6 V5 SDATA 7 W6 SDATA 8 V6 SDATA 9 WA SDATA 10 VA SDATA 11 V2 SDATA 12 V3 SDATA 13 V1 SDRAM Data Bus Bits 0 to 31 The 32 pins of the SDRAM data SDATA 14 W3 bus are inputs for read operations and outputs for write operations SDATA 15 W1 At all other times these pins high impedance SDATA 16 Y16 SDATA 17 Y17 Note All SDRAM operations are controlled entirely by the SDATA 18 V18 DS33R11 No user programming for SDRAM b
229. device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2 32 1 times at the maximum frame rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 195 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU TxFrmCtr Register Description MAC Frames Transmitted Counter Register Address 0300h indirect 0300h Bit 31 30 29 28 27 26 25 24 Name TXFRMC31 TXFRMC30 TXFRMC29 TXFRMC28 TXFRMC27 TXFRMC26 TXFRMC25 TXFRMC24 Default 0 0 0 0 0 0 0 0 0301h Bit 23 22 21 20 19 18 17 16 Name TXFRMC23 TXFRMC22 TXFRMC21 TXFRMC20 TXFRMC19 TXFRMC18 TXFRMC17 TXFRMC16 Default 0 0 0 0 0 0 0 0 0302h Bit 15 14 13 12 11 10 09 08 Name TXFRMC15 TXFRMC14 TXFRMC13 TXFRMC12 TXFRMC11 TXFRMC10 TXFRMC9 TXFRMC8 Default 0 0 0 0 0 0 0 0 0303h Bit 07 06 05 04 03 02 01 00 Name TXFRMC7 TXFRMC6 TXFRMC5 TXFRMC4 TXFRMC3 TXFRMC2 TXFRMC1 TXFRMCO Default 0 0 0 0 0 0 0 0 Bits 0 31 All Frames Transmitted Counter TXFRMC 0 31 32 bit value indicating the number of frames transmitted Each
230. dless of the TR SSIEx registers The TR SSIEx registers still define which channels are to have B7 stuffing preformed 1 source signaling data as enabled by the TR SSIEx registers Bit 3 Global Bit 7 Stuffing GB7S 0 7 allow the SSIEx registers to determine which channels containing all Os are to be bit 7 stuffed 1 force bit 7 stuffing in all O byte channels regardless of how the TR SSIEx registers are programmed Bit 2 TFDL Register Select TFDLS 0 7 source FDL or Fs bits from the internal TR TFDL register legacy FDL support mode 1 source FDL or Fs bits from the internal HDLC controller Bit 1 Transmit Blue Alarm TBL 0 transmit data normally 1 transmit an unframed all ones code at TPOS and TNEG Bit 0 Transmit Yellow Alarm TYEL 0 do not transmit yellow alarm 1 transmit yellow alarm 206 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR T1TCR2 Register Description T1 Transmit Control Register 2 Register Address 06h Bit 7 6 5 4 3 2 1 0 Name TB8ZS TSLC96 TZSE FBCT2 FBCT1 TD4YM TB7ZS Default 0 0 0 0 0 0 0 0 Bit 7 Transmit B8ZS Enable TB8ZS 0 B8ZS disabled 1 B8ZS enabled Bit 6 Transmit SLC 96 Fs Bit Insertion Enable TSLC96 Only set this bit to a 1 in D4 framing applications Must be set to 1 to source the Fs pattern from the TR TFDL register See Section 10 18 for details 0 SLC 96 Fs bit insertion disabled 1 SLC 96 Fs bit insertion
231. dress Bit 7 6 5 4 3 2 1 0 Name BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8 Default 0 0 0 0 0 0 0 0 Bits 0 to 7 BERT Pattern BSP 15 8 8 bits of 32 bits Register description below Register Name BSPB2R Register Description BERT Pattern Byte2 Register Register Address Bit 7 6 5 4 3 2 1 0 Name BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16 Default 0 0 0 0 0 0 0 0 Bits 0 to 7 BERT Pattern BSP 23 16 8 bits of 32 bits Register description below Register Name BSPB3R Register Description BERT Seed Pattern Byte3 Register Register Address Bit 7 6 5 4 3 2 1 0 Name BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24 Default 0 0 0 0 0 0 0 0 Bits 0 to 8 BERT Pattern BSP 31 24 Upper 8 bits of 32 bits Register description below BERT Pattern BSP 31 0 These 32 bits are the programmable seed for a transmit PRBS pattern or the programmable pattern for a transmit or receive repetitive pattern BSP 31 is the first bit output on the transmit side for a 32 bit repetitive pattern or 32 bit length PRBS BSP 31 is the first bit input on the receive side for a 32 bit repetitive pattern 146 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TEICR Register Description Transmit Error Insertion Control Register Register Address 88h Bit 7 6 5 4 3 2 1 0 Name TIER2 TIER1 TIERO BEI TSEI Default 0 0 0 0 0 0 0 0
232. e PMSIE BEIE BECIE OOSIE Default 0 0 0 0 0 0 0 0 Bit 3 Performance Monitoring Update Status Interrupt Enable PMSIE This bit enables an interrupt if the PMSL bit is set 0 interrupt disabled 1 interrupt enabled Bit 2 Bit Error Interrupt Enable BEIE This bit enables an interrupt if the BEL bit is set 0 interrupt disabled 1 interrupt enabled Bit 1 Bit Error Count Interrupt Enable BECIE This bit enables an interrupt if the BECL bit is set 0 interrupt disabled 1 interrupt enabled Bit 0 Out Of Synchronization Interrupt Enable OOSIE This bit enables an interrupt if the OOSL bit is set 0 interrupt disabled 1 interrupt enabled 148 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description RBECBOR Receive Bit Error Count Byte 0 Register Register Address Bit 7 6 5 4 3 2 1 0 Name BEC6 5 BECA 2 BEC1 BECO Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Error Count BEC 0 7 Lower eight bits of 24 bits Register description below Register Name RBECB1R Register Description Receive Bit Error Count Byte 1 Register Register Address Bit 7 6 5 4 3 2 1 0 Name BEC15 BEC14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Error Count BEC 8 15 Eight bits of a 24 b
233. e See Register Definition Eu Transmit Signaling Bit Format Changes With Operating Mode See Register Definition TRATSU Transmit Signaling Bit Format Changes With Operating Mode See Register Definition E TR TSiO Transmit Signaling Bit Format Changes With Operating Mode See Register Definition TRISH Transmit Signaling Bit Format Changes With Operating Mode See Register Definition 05B Transmit Signaling Bit Format Changes With Operating Mode See Register Definition h TR TS12 ES TREE Transmit Signaling Bit Format Changes With Operating Mode See Register Definition 050 Transmit Signaling Bit Format Changes With Operating Mode See Register Definition h TR TS14 05 Transmit Signaling Bit Format Changes With Operating Mode See Register Definition h TR TS15 05 Transmit Signaling Bit Format Changes With Operating Mode See Register Definition h TR TS16 TERES Receive Signaling Bit Format Changes With Operating Mode See Register Definition lh TERS Receive Signaling Bit Format Changes With Operating Mode See Register Definition a Receive Signaling Bit Format Changes With Operating Mode See Register Definition E TR REA Receive Signaling Bit Format Changes With Operating Mode See Register Definition 064 EAE NT h Receive Signaling Bit Format Changes With Operating Mode See Register Definition m Receive Signaling Bit Format Changes With Operating Mode See Register Definition Taney
234. e and back off limit for half sU MAGUS duplex The transmit and receive enable bits must be set for the MAC to operate Management MDIO Address Register The address for SU MACMIIA PHY access through the MDIO interface 2 MDIO Data Register Data to be written to or read from 0018h 001Bh SU MACMIID the PHY through interface 001Ch 001Fh SU MACFCR MAC Flow Control Register 0100h 0103h SU MMCCTRL MAC MMC Control Register Bit 0 for resetting the status counters Table 9 7 MAC Status Registers ADDRESS REGISTER DESCRIPTION 0200h 0203h SU RxFrmCtr All frames received counter 0204h 0207h SU RxFrmOkCtr Number of received frames that are good 0300h 0303h SU TxFrmCtr Number of frames transmitted 0308h 030Bh SU TxBytesCtr Number of bytes transmitted 030Ch 030Fh SU TxBytesOkCtr Number of bytes transmitted with good frames 0334h 0337h SU TxFrmUndr Transmit FIFO underflow counter 0338h 033Bh SU TxBdFrmCtr Transmit number of frames aborted 60 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 15 1 MII Mode Options The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low The MII interface consists of 17 pins For instructions on clocking the Ethernet Interface while mode see Section 9 1 Diagrams of system conne
235. e 10 1 Figure 10 1 LIST OF FIGURES Ethernet to WAN Extension With or Without Framing rr strate tta ren tta da 17 Main Block Diagram R 20 Block Diagram of T ICA 21 Er UNE UNS T 22 Receive and Transmit FFODIBE aiaiai 23 WA TST Backplane Inter ade uiuis ese edi sese tian t que ERE PR odo 24 ZOO Lr NIB PINOUT 40 Clocking Tor the e 44 Device Interrupt Information Flow arte tta reta taa rta bita aeta kh a aeta seta arte 49 Flow Control Using Pause Control Frame esaeen 55 IEEE 802 3 Fram 56 Configured as DTE Connected to an Ethernet PAY in reete 58 DS39R11 6 onngured as DCE In MIT TOR s arti iere be tn a a Den dab a a dn dai 59 DINI 61 MII
236. e 9 11 HDLC Encapsulation of MAC Frame Number of Bytes Flag 0x7E 1 Destination Adrs DA 6 Source Adrs SA 6 Length Type 2 MAC Client Data 48 1500 FCS for 4 FCS for HDLC 0 2 4 Flag 0x7E MSB LSB 67 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 19 X 86 Encoding and Decoding X 86 protocol provides a method for encapsulating Ethernet Frame onto LAPS LAPS provides HDLC type framing structure for encapsulation of Ethernet frames LAPS encapsulated frames can be used to send data onto a SONET SDH network The DS33R11 expects a byte synchronization signal to provide the byte boundary for the X 86 receiver This is provided by the RBSYNC pin The functional timing is shown in Figure 12 4 The X 86 transmitter provides a byte boundary indicator with the signal TBSYNC The functional timing is shown in Figure 12 3 Note that in some cases additional logic may be required to meet RSYNC TSYNC sychronization timing requirements when operating in X 86 mode Figure 9 12 LAPS Encoding of MAC Frames Concept IEEE 802 3 MAC Frame LAPS Rate Adaption SDH 68 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 9 13 X 86 Encapsulation of the MAC frame MSB Flag 0x7E Address 0x04 Control 0x03 1st Octect of SAPI Oxfe 2nd Octect of SAPI 0x01 D
237. e DS33R11 after completion of BIST test before normal dataflow can begin 140 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name GL BISTPF Register Description BIST Pass Fail Register Address 21h Bit 7 4 3 2 1 0 Name BISTDN BISTPF Default 0 0 0 0 0 0 Bit 1 BIST DONE BISTDN If this bit is set to 1 the DS33R11 has completed the BIST Test initiated by BISTE The pass fail result is available in BISTPF Bit 0 BIST Pass Fail BISTPF This bit is equal to 0 after the DS33R11 performs BIST testing on the SDRAM and the test passes This bit is set to 1 if the test failed This bit is valid only after the BIST test is complete and the BIST DN bit is set If set this bit can only be cleared by resetting the DS33R11 GL SDMODE1 Global SDRAM Mode Register 1 Register Name Register Description Register Address 3Ah Bit 7 6 5 4 3 2 1 0 Name WT BL2 BL1 BLO Default 0 0 0 0 0 0 1 1 Bit 3 Wrap Type WT This bit is used to configure the wrap mode 0 Sequential 1 Interleave Bits 0 2 Burst Length 0 through 2 BLO BL2 These bits are used to determine the Burst Length Note This register has a nonzero default value This should be taken into consideration when initializing the device Note After changing the value of this register the user must toggle the GLL SDMODEWS SDMWV bit to write th
238. e new values to the SDRAM 141 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description GL SDMODE2 Global SDRAM Mode Register 2 Register Address 3Bh Bit 2 7 6 5 4 3 2 1 0 Name LTMOD2 LTMOD1 LTMODO Default 0 0 0 0 0 0 1 0 Bits 0 2 CAS Latency Mode LTMODO LTMOD2 These bits are used to setup CAS Latency Note Only CAS Latency of 2 or 3 is allowed Note This register has a nonzero default value This should be taken into consideration when initializing the device Note After changing the value of this register the user must toggle the GLL SDMODEWS SDMWV bit to write the new values to the SDRAM GL SDMODEWS Global SDRAM Mode Register Write Status Register Name Register Description Register Address 3Ch Bit 7 6 5 4 3 2 1 0 Name SDMW Default 0 0 0 0 0 0 0 0 Bit 0 SDRAM Mode Write SDMW Setting this bit to 1 will write the current values of the mode control and refresh time control registers to the SDRAM user must clear this bit and set it again for subsequent write operations Register Name GL SDRFTC Register Description Global SDRAM Refresh Time Control Register Address 3Dh Bit 7 6 5 4 3 2 1 0 Name SREFT7 SREFT6 SREFT5 SREFTA SREFT3 SREFT2 SREFT1 SREFTO Default 0 1 0 0 0 1 1 0 Bit
239. e sentence The user can utilize the built in REF CLKO output clock to drive this input Also removed from the fifth bullet the sentence This output clock can be used as an input to allowing the user to have less oscillator for the system Page 45 In Section 9 1 1 updated the section to show that in DCE and RMII operating modes the REF CLKO signal should not be used to provide an input to due to the reset requirements in these operating modes Page 46 In Section 9 2 corrected low power mode information 030807 Page 56 In Section 9 14 removed the following sentence from the first paragraph The REF CLKO output can be used to source the REF input Page 68 In Section 9 19 clarified X 86 mode synchronization Page 123 In Table 11 7 corrected SU MACCR register map Page 173 Corrected SU GCR H10S bit definition Page 183 Corrected default value for RMPS bit 0 the SU RMFSRL register definition Page 183 Corrected the SU RQLT and SU RQHT default values to zero Page 186 Corrected SU MACCR PM and SU MACCR PAM bit definitions Page 319 In Table 13 10 added TCLKE to TBSYNC Setup Time Minimum of 3 5ns Page 334 Added a note regarding the special considerations required for dual JTAG controllers 2 344 of 344 Maxim Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied
240. eceive high watermark register TR RHWMR Bit 2 Receive FIFO Not Empty Condition RNE Set when the receive 128 byte FIFO has at least 1 byte available for a read Bit 1 Transmit FIFO Below Low Watermark Condition TLWM Set when the transmit 128 byte FIFO empties beyond the low watermark as defined by the transmit low watermark register TR TLWMR Bit 0 Transmit FIFO Not Full Condition TNF Set when the transmit 128 byte FIFO has at least 1 byte available 225 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR6 TR IMR7 Register Description HDLC 1 Interrupt Mask Register 6 HDLC 2 Interrupt Mask Register 7 Register Address 21h 23h Bit 7 6 5 4 3 2 1 0 TMEND RPE RPS RHWM RNE TLWM TNF Defaut 0 0 0 0 0 0 0 0 Bit 6 Transmit Message End Event TMEND 0 interrupt masked 1 interrupt enabled Bit 5 Receive Packet End Event RPE 0 interrupt masked 1 interrupt enabled Bit 4 Receive Packet Start Event RPS 0 interrupt masked 1 interrupt enabled Bit 3 Receive FIFO Above High Watermark Condition RHWM 0 interrupt masked 1 interrupt enabled interrupts on rising edge only Bit 2 Receive FIFO Not Empty Condition RNE 0 interrupt masked 1 interrupt enabled interrupts on rising edge only Bit 1 Transmit FIFO Below Low Watermark Condition TLWM 0 interrupt masked 1 interrupt enabled interrupts on rising
241. ed When configured for 10Mbit s mode the data is sampled once every 10 clock periods RX DV K19 Receive Data Valid This active high signal indicates valid data from the PHY The data RXD is ignored if RX_DV is not asserted high RX ERR K18 Receive Error Asserted by the MAC PHY for one or more RX CLK periods indicating that an error has occurred Active High indicates Receive code group is invalid If CRS DV is low RX ERR has no effect This is synchronous with RX CLK In DCE mode this signal must be grounded Receive Error RMII Signal is synchronous to REF CLK TX CLK H19 Transmit Clock MII Timing reference for TX EN and TXD 3 0 The TX CLK frequency is 25 2 for 100Mbit s operation and 2 5MHz for 10Mbit s operation In DTE mode this is a clock input provided by the PHY In DCE mode this is an output derived from REF CLK providing 2 5MHz 10Mbit s operation or 25MHz 100Mbit s operation 27 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION TXDI 0 F19 Transmit Data 0 through 3 MII TXD 3 0 is presented synchronously with the rising edge of TX CLK TXD 0 is the least TXD 1 F18 significant bit of the data When TX EN is low the data on TXD hould be i E20 should be ignored Transmit Data 0 through 1 RMII Two bits of data TXD 1 0 EW presented synchronously wit
242. ed Reserved Reserved Reserved Reserved Reserved 0007h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0008h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0009h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 000Ah Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 000Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 000Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 000Dh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OOOEh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OOOFh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0010h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0011h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0012h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0013h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0014h aber oe Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0015h 23 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0016h 15 8 PHYA4 PHYA3 PHYA2 PHYA1 PHYAO MIIA4 MIIA3 MIIA2 0017h 7 0 MIIA1 MIIAO Reserved Reserved Reserved Reserved MII
243. ed T1 E1 J1 Transceiver 9 7 Interrupt Information Registers The interrupt information registers provide an indication of which status registers SR1 through SR9 are generating an interrupt When an interrupt occurs the host can read TR IIR1 and TR IIR2 to quickly identify which of the nine status registers are causing the interrupt 9 8 Status Registers When a particular event or condition has occurred or is still occurring in the case of conditions the appropriate bit in a status register is set to a 1 of the status registers operate in a latched fashion This means that if an event or condition occurs a bit is set to a 1 It remains set until the user reads that bit An event bit is cleared when it is read and it is not set again until the event has occurred again Condition bits such as RBL RLOS etc remain set if the alarm is still present The user always proceeds a read of any of the status registers with a write The byte written to the register informs the device which bits the user wishes to read and have cleared The user writes a byte to one of these registers with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user does not wish to obtain the latest information on When a 1 is written to a bit location the read register is updated with the latest information When 0 is written to a bit position the read register is not updated and the previous value is held A write to the status r
244. edge only Bit 0 Transmit FIFO Not Full Condition TNF 0 interrupt masked 1 interrupt enabled interrupts on rising edge only 226 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR INFO5 TR INFO6 Register Description HDLC 1 Information Register HDLC 2 Information Register Register Address 2Eh 2Fh Bit 7 6 5 4 3 2 1 0 Name TEMPTY TFULL REMPTY PS2 PS1 PSO Defaut 0 0o o o 0 o0 o o Bit 5 Transmit FIFO Empty TEMPTY A real time bit that is set high when the FIFO is empty Bit 4 Transmit FIFO Full TFULL A real time bit that is set high when the FIFO is full Bit 3 Receive FIFO Empty REMPTY A real time bit that is set high when the receive FIFO is empty Bits 0 2 Receive Packet Status PS0 to PS2 These are real time bits indicating the status as of the last read of the receive FIFO PS2 PS1 50 Packet Status 0 0 0 In Progress 0 0 1 Packet OK Packet ended with correct CRC codeword 0 1 0 Error A closing flag was detected preceded by a corrupt codeword Abort Packet ended because an abort signal was detected seven 0 or more 1s in a row Overrun HDLC controller terminated reception of packet because 1 0 0 receive FIFO is full Register Name TR INFO4 Register Description HDLC Event Information Register 4 Register Address 2Dh Bit 7 6 5 4 3 2 1 0 Name H2UDR 2 H1UDR H
245. egister space with 00 or otherwise if specifically noted in the register s definition including the reserved bits and reserved register locations STEP 9 Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh STEP 10 Setup connection the GL CON1 register STEP 11 Configure the Serial Port register space as needed STEP 12 Configure the Ethernet Port register space as needed STEP 13 Configure the Ethernet MAC indirect registers as needed STEP 14 Configure the T1 E1 J1 Framer as needed STEP 15 Configure the T1 E1 J1 LIU as needed STEP 16 Configure the external Ethernet PHY through the MDIO interface STEP 17 Clear all counters and latched status bits STEP 18 Set the queue size in the Arbiter and reset the queue pointers for the Ethernet and serial interfaces STEP 19 After the TSYSCLK and RSYSCLK inputs to the T1 E1 J1 transceiver are stable the receive and transmit elastic stores should be reset this step can be skipped if the elastic stores are disabled STEP 20 Enable Interrupts as needed STEP 21 Begin handling interrupts and latched status events 9 4 Global Resources In order to maintain software compatibility with the multiport devices in the product family a set of global registers are located at OFOh OFFh The global registers include Global resets global interrupt status interrupt masking clock configuration and the Device ID registers See the Global Register Definitions in Table 11
246. egisters is immediately followed by a read of the same register This write read scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register This operation is key in controlling the device with higher order languages Status register bits are divided into two groups condition bits and event bits Condition bits are typically network conditions such as loss of sync or all ones detect Event bits are typically markers such as the one second timer elastic store slip etc Each status register bit is labeled as a condition or event bit Some of the status registers have bits for both the detection of a condition and the clearance of the condition For example TR SR2 has a bit that is set when the device goes into a loss of sync state TR SR2 0 a condition bit and a bit that is set TR SR2 4 an event bit when the loss of sync condition clears goes in sync Some of the status register bits condition bits do not have a separate bit for the condition clear event but rather the status bit can produce interrupts on both edges setting and clearing These bits are marked as double interrupt bits An interrupt is produced when the condition occurs and when it clears 9 9 Information Registers Information registers operate the same as status registers except they cannot cause interrupts They are all latched except for TR INFO7 and some of the bits in TR INFO5 and TR INF
247. eive Frame Rejection Control Register Name Register Description Register Address 15Eh Bit 7 6 5 4 3 2 1 0 UCFR CFRR LERR CRCERR DBR MIIER BFR Default 0 0 0 0 0 0 0 0 Bit 6 Uncontrolled Control Frame Reject UCFR When set to 1 Control Frames other than Pause Frames are allowed When this bit is equal to zero nonpause control frames are rejected Bit 5 Control Frame Reject CFRR When set to 1 control frames are allowed When this bit is equal to zero all control frames are rejected Bit 4 Length Error Reject LERR When set to 1 frames with an unmatched frame length field and actual number of bytes received are allowed When equal to zero only frames with matching length fields and actual bytes received will be allowed Bit 3 CRC Error Reject CRCERR When set to 1 frames received with a CRC error or MII error are allowed When equal to zero frames with CRC or MII errors are rejected Bit 2 Dribbling Bit Reject DBR When set to 1 frames with lengths of noninteger multiples of 8 bits are allowed When equal to zero frames with dribbling bits are rejected The dribbling bit setting is only valid only if there is not a collision or runt frame Bit 1 MII Error Reject MIIER When set to 1 frames are allowed with Receive Errors When equal to zero frames with MII errors are rejected Bit 0 Broadcast Frame Reject BFR When set to 1 broadcast frames are allowed Whe
248. elay Mode RESMDM See Section 10 12 4 for details 0 elastic stores operate at full two frame depth 1 7 elastic stores operate at 32 bit depth Bit 0 Receive Elastic Store Enable RESE 0 elastic store is bypassed 1 elastic store is enabled 244 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TS1 to TR TS16 Register Description Transmit Signaling Registers E1 Mode CAS Format Register Address 50h to 5Fh L SB stre eec xd TS2 TS3 54 55 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 245 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TS1 to TR TS16 Register Description Transmit Signaling Registers E1 Mode CCS Format Register Address 50h to 5Fh t t l 91 9 TS10 74 75 82 83 84 o o 35 39 TS12 99 100 101 102 103 104 513 TS14 TS15 TS16 246 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TS1 to TR TS12 Register Description Transmit Signaling Registers T1 Mode ESF Format Register Address 50h to 5Bh MsB 8 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 247 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TS1 to TR TS12 Register Descri
249. en RDEN is inactive The RDEN polarity can be programmed by LI RSLCR The RDEN signal must be coincident with the RSERI bit that needs to be blocked Figure 12 1 Tx Serial Interface Functional Timing TCLKE TDEN TSERO TCLKE Gapped TSERO RCLKI RDEN RSERI RCLKI Gapped RSERI 300 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver The DS33R11 provides the TBSYNC signal as a byte boundary indication to an external interface when X 86 LAPS functionality is selected The functional timing of TBSYNC is shown in the following figure TBSYNC is active high on the last bit of the byte being shifted out and occurs every 8 bits For the serial receiver interface RBSYNC is used to provide byte boundary indication to the DS33R11 when X 86 LAPS mode is used The functional timing is shown in Figure 12 3 In X 86 Mode the receiver expects the RBSYNC byte indicator as shown in Figure 12 4 Figure 12 3 Transmit Byte Sync Functional Timing TCLKE TBYSYNC TSERO last bit 1st bit Figure 12 4 Receive Byte Sync Functional Timing LI LI LI L RBYSYNC er RSERI Past bit istbit_ 12 2 MII and RMII Interfaces The MII Interface Transmit Port has its own TX CLK and data interface The data TXD 3 0 operates synchronously with TX CLK The LSB is presented first TX CLK should be 2 5MHz for 10Mbit s operation and 25MHz for 100Mbit s operation TX EN is valid at the same
250. enabled Bit 5 Transmit FDL Zero Stuffer Enable TZSE Set this bit to 0 if using the internal HDLC controller instead of the legacy support for the FDL See Section 15 for details 0 zero stuffer disabled 1 zero stuffer enabled Bit 4 F Bit Corruption Type 2 FBCT2 Setting this bit high enables the corruption of one Ft D4 framing mode or FPS ESF framing mode bit in every 128 Ft or FPS bits as long as the bit remains set Bit 3 F Bit Corruption Type 1 FBCT1 A low to high transition of this bit causes the next three consecutive Ft D4 framing mode or FPS ESF framing mode bits to be corrupted causing the remote end to experience a loss of synchronization Bit 2 Transmit Side D4 Yellow Alarm Select TD4YM 0 Os in bit 2 of all channels 1 a 1 in the S bit position of frame 12 Bit 0 Transmit Side Bit 7 Zero Suppression Enable TB7ZS 0 no stuffing occurs 1 7 bit 7 forced to a 1 in channels with all Os 207 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR T1CCR1 Register Description T1 Common Control Register 1 Register Address 07h Bit 7 6 5 4 3 2 1 0 Name TRAI CI TAIS CI TFM PDE TLOOP Default 0 0 0 0 0 0 0 0 Bit 4 Transmit RAI CI Enable TRAI Cl Setting this bit causes the ESF RAI CI code to be transmitted in the FDL bit position 0 do not transmit the ESF RAI CI code 1 transmit the ESF code Bit 3 Transmit AIS CI E
251. ent Frame Opco Turn Preamble Start d Phy Adrs Phy Reg Aroun Data Idle d 16 1 32 bits 2bis 2bits 5 bits 5 bits 2 bits bits Bit READ 111 111 01 10 PHYA 4 0 PHYR 4 0 22 722777777 2 WRITE 111 111 01 01 PHYA 4 0 PHYR 4 0 10 PHYD 15 0 2 9 16 BERT in the Ethernet Mapper The BERT in the Ethernet Mapper can be used for generation and detection of BERT patterns The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment The following restrictions are related to the BERT The RDEN and TDEN are inputs that can be used to gap bits e BERT will transmit even when the device is set for X 86 mode and TDEN is configured as an output e normal traffic flow is halted while the BERT is in operation e If the BERT is enabled for a Serial port it will override the normal connection e If there is a connection overridden by the BERT when BERT operation is terminated the normal operation is restored The transmit direction generates the programmable test pattern and inserts the test pattern payload into the data stream The receive direction extracts the test pattern payload from the receive data stream and monitors the test pattern payload for the programmable test pattern BERT Features e PRBS and QRSS patterns of 2 1 2 1 2 1 and QRSS pattern support e Programmab
252. ent support includes evaluation kit driver source code and reference designs e Reference design routes on a two layer PC board e Programmable output clocks for fractional T1 E1 HO and H12 applications 2 2 Microprocessor Interface Parallel control port with 8 bit data bus Nonmultiplexed Intel and Motorola timing modes Internal software reset and external hardware reset input pin Supports polled or interrupt driven environments Software access to device ID and silicon revision Global interrupt output pin 2 3 HDLC Ethernet Mapping Dedicated HDLC controller engine for protocol encapsulation Compatible with polled or interrupt driven environments Programmable FCS insertion and extraction Programmable FCS type Supports FCS error insertion Programmable packet size limits Minimum 64 bytes and maximum 2016 bytes Supports bit stuffing destuffing Selectable packet scrambling descrambling 1 Separate FCS errored packet and aborted packet counts Programmable inter frame fill for transmit HDLC 2 4 X 86 Link Access Protocol for SONET SDH Ethernet Mapping Programmable X 86 address control fields for transmit and receive Programmable 2 byte protocol SAPI field for transmit and receive 32 bit FCS Transmit transparency processing 7E is replaced by 7D Transmit transparency processing 7D replaced by 7D 5D Receive rate adaptation 7D DD is deleted Receive transparency processing 7D is replaced by 7E
253. ently being detected Bit 5 Transmit Current Limit Exceeded TCLE A real time bit that is set when the 50mA RMS current limiter is activated whether the current limiter is enabled or not Bit 4 Transmit Open Circuit Detect TOCD A real time bit that is set when the device detects that the TTIP and TRING outputs are open circuited Bits 0 3 Receive Level Bits RLO to RL3 Real time bits RL3 RL2 RL1 RLO Receive Level dB 0 0 0 0 Greater than 2 5 0 0 0 1 2 5 to 5 0 0 0 1 0 5 0 to 7 5 0 0 1 1 7 5 to 10 0 0 1 0 0 10 0 to 12 5 0 1 0 1 12 5 to 15 0 0 1 1 0 15 0 to 17 5 0 1 1 1 17 5 to 20 0 1 0 0 0 20 0 to 22 5 1 0 0 1 22 5 to 25 0 1 0 1 0 25 0 to 27 5 1 0 1 1 27 5 to 30 0 1 1 0 0 30 0 to 32 5 1 1 0 1 32 5 to 35 0 1 1 1 0 35 0 to 37 5 1 1 1 1 Less than 37 5 NOTE RLO through RL3 only indicate the signal range as specified by the bit in TR LIC1 Example if EGL 1 and in T1 mode RLO through will only indicate a signal range of gt 2 5dB to 15dB even if the signal is lt 15dB 213 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR INFO3 Register Description Information Register 3 Register Address 12h Bit 7 6 5 4 3 2 1 0 CRCRC FASRC CASRC Default 0 0 0 0 0 0 0 0 Bit 2 CRC Resync Criteria Met Event CRCRC Set w
254. ep up transformer to the network See Section 10 24 for details TRING T1 T2 Transmit Analog Ring Output for the T1 E1 J1 Transceiver Analog line driver outputs Two connections are provided to improve signal quality These pins connect via a 1 2 step up transformer to the network See Section 10 24 for details RTIP K1 Receive Analog Tip Input for the T1 E1 J1 Transceiver Analog input for clock recovery circuitry These pins connect via a 1 1 transformer to the network See Section 10 24 for details RRING M1 Receive Analog Ring Input for the T1 E1 J1 Transceiver Analog input for clock recovery circuitry These pins connect via a 1 1 transformer to the network See Section 10 24 for details T1 E1 J1 TRANSMIT FRAMER INTERFACE TSERI Transmit Serial Data Input to the T1 E1 J1 Framer Transmit NRZ serial data Sampled on the falling edge of TCLKT when the transmit side elastic store is disabled Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled TCLKT D2 Transmit Clock for the T1 E1 J1 Transceiver 1 544MHz or a 2 048MHz primary clock Used to clock data from the TSERI pin through the transmit side formatter TCHBLK A2 Transmit Channel Block for the T1 E1 J1 Transceiver A user programmable output that can be forced high or low during any of the channels Synchronous with TCLKT when the transmit side elastic store is disabled Synchronous wit
255. eristics Backplane Clock Synthesis Vpp 3 3V 5 Ta 40 C to 85 C Note 1 Figure 13 16 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay RCLKO to BPCLK tpi 10 ns Note Timing parameters in this table are guaranteed by design GBD Figure 13 16 Receive Timing Delay RCLKO to BPCLK RCLKO NOTE IF RCLKOIS 1544 MHZ BPCLK WILL BE ASYNCHRONOUS 331 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 11 AC Characteristics Transmit Side Table 13 16 AC Characteristics Transmit Side Voo 3 3V 5 Ta 0 C to 85 C Note 1 Figure 13 17 Figure 13 18 and Figure 13 19 PARAMETER SYMBOL CONDITIONS MIN TYP E1 MAX UNITS 488 1 TCLKT Period tcp 648 T1 ns tcu 20 0 5 tcp TCLKT Pulse Width tot 20 0 5 top ns 488 E1 TDCLKI Period tip 648 T1 ns tiu 20 0 5 tip TDCLKI Pulse Width Rm 20 O05 tp ns Note 2 648 TSYSCLK Period tsp Note 3 448 ns j 20 0 5 tsp TSYSCLK Pulse Width tsp 20 0 5 tep ns TSYNC or TSSYNC Setup to TCLKT or t 20 TSYSCLK Falling SY TSYNC or TSSYNC Pulse Width tpw 50 ns TSERI TSIG TDATA TPOSI TNEGI Setup to TCLKT TSYSCLK TDCLKI tsu 20 ns Falling TSERI TSIG TDATA Hold from TCLKT t 20 or TSYSCLK Falling BP TPOSI TNEGI Hold from TDCLKI 2 tup 20 ns Falling TCLKT TDCLKI or TSYSCLK Rise
256. ers selected by the current instruction will retain their previous state The controller will remain in this state while JTMS is LOW A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2 DR state Exit2 DR A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update DR state and terminate the scanning process A rising edge on JTCLK with JTMS LOW will enter the Shift DR state 337 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Update DR A falling edge on JTCLK while in the Update DR state will latch the data from the shift register path of the test registers into the data output latches This prevents changes at the parallel output due to changes in the shift register Select IR Scan All test registers retain their previous state The instruction register will remain unchanged during this state With JTMS LOW a rising edge on JTCLK moves the controller into the Capture IR state and will initiate a scan sequence for the instruction register JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test Logic Reset state Capture IR The Capture IR state is used to load the shift register in the instruction register with a fixed value This value is loaded on the rising edge of JTCLK If JTMS is HIGH on the rising edge of JTCLK the controller will enter the Exit1 IR state If JTMS is LOW on the rising edge of JTCLK the controller will enter t
257. escription Register Address 04h Bit 7 5 4 2 1 0 Name RLCALS1 TLCALS1 Default Bit 4 Receive Serial Interface Clock Activity Latched Status 1 RLCALS1 This bit is set to 1 if the receive clock for Serial Interface 1 has activity This bit is cleared upon read Bit 0 Transmit Serial Interface Clock Activity Latched Status 1 TSCALS1 This bit is set to 1 if the transmit clock for Serial Interface 1 has activity This bit is cleared upon read GL SRCALS Global SDRAM Reference Clock Activity Latched Status Register Name Register Description Register Address 05h Bit 7 5 4 2 1 0 Name REFCLKS SYSCLS Default Bit 1 Reference Clock Activity Latched Status REFCLKS This bit is set to 1 if REF CLK has activity This bit is cleared upon read Bit 0 System Clock Input Latched Status SYSCLS This bit is set to 1 if SYSCLKI has activity This bit is cleared upon read Register Name GL LIE Register Description Global Serial Interface Interrupt Enable Register Address 06h Bit 7 5 4 1 0 Name LIN1TIE LIN1RIE Default 0 0 0 0 0 Bit 4 Serial Interface 1 TX Interrupt Enable LINE1TIE Setting this bit to 1 enables an interrupt on LINTTIS Bit 0 Serial Interface 1 RX Interrupt Enable LINE1RIE Setting this bit to 1 enables an interrupt on LINTRIS 136 of 344 DS33R11 Ethe
258. escription BERT Control Register 2 Register Address E1h Bit 7 6 5 4 3 2 1 0 Name EIB2 EIB1 EIBO SBE RPL3 RPL2 RPL1 RPLO Default 0 Bits 5 7 Error Insert Bits 0 to 2 EIBO to EIB2 Automatically inserts bit errors at the prescribed rate into the generated data pattern Can be used for verifying error detection features EIB2 EIB1 EIBO Error Rate Inserted 0 0 0 No errors automatically inserted 0 0 1 10E 1 0 1 0 10E 2 0 1 1 10E 3 1 0 0 10E 4 1 0 1 10E 5 1 1 0 10E 6 1 1 1 10E 7 Bit 4 Single Bit Error Insert SBE A low to high transition creates a single bit error Must be cleared and set again for a subsequent bit error to be inserted Bits 0 3 Repetitive Pattern Length Bit 3 RPLO to RPL3 RPLO is the LSB and RPL3 is the MSB of a nibble that describes how long the repetitive pattern is The valid range is 17 0000 to 32 1111 These bits are ignored if the receive BERT is programmed for a pseudorandom pattern To create repetitive patterns fewer than 17 bits in length the user must set the length to an integer number of the desired length that is less than or equal to 32 For example to create a 6 bit pattern the user can set the length to 18 0001 or to 24 0111 or to 30 1101 Length RPL3 RPL2 RPL1 RPLO bits 17 0 0 0 0 18 0 0 0 1 19 0 0 1 0 20 0 0 1 1 21 0 1 0 0 22 0 1 0 1 23 0 1 1
259. eshold RQLT 0 7 The receive queue low threshold for the connection in increments of 32 packets of 2048 bytes each The value of this register is multiplied by 32 2048 bytes to determine the byte location of the threshold Note that the receive queue is for data that was received from the Ethernet Interface to be sent to the Serial Interface Register Name SU RQHT Register Description Receive Queue High Threshold Watermark Register Address 15Bh Bit 7 6 5 4 3 2 1 0 Name RQHT7 RQHT6 RQHT5 RQHT4 RQHT3 RQHT2 RQHT1 RQHTO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Queue High Threshold RQTH 0 7 The receive queue high threshold for the connection in increments of 32 packets of 2048 bytes each The value of this register is multiplied by 32 2048 bytes to determine the byte location of the threshold Note that the receive queue is for data that was received from the Ethernet Interface to be sent to the Serial Interface 183 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU QRIE Register Description Receive Queue Cross Threshold enable Register Address 15Ch Bit 7 6 5 4 3 2 1 0 Name RFOVFIE RQVFIE RQLTIE RQHTIE Default 0 0 0 0 0 0 0 0 Bit 3 Receive FIFO Overflow Interrupt Enable RFOVFIE If this bit is set the interrupt is enabled for RFOVFLS Bit 2 Receive Queue Overflow Interrupt Enable RQVFIE
260. estination Adrs DA Source Adrs SA Length Type MAC Client Data PAD FCS for MAC FCS for LAPS Flag 0x7E Number of Bytes 1 1 1 46 1500 LSB The DS33R11 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured for X 86 mode in the register LI TX86E The DS33R11 provides the following functions Control Registers for Address Control SAPIH SAPIL 32 bit FCS enabled Programmable X541 scrambling The sequence of processing performed by the receiver is as follows Programmable octets X 1 descrambling Detect the Start Flag 7E Remove Rate adaptation octets 7d dd Perform transparency processing 7d 5e is converted to 7e and 7d 5d is converted to 7d Check for a valid Address Control and SAPI fields LI TRX86A to LI TRX86SAPIL Perform FCS checking Detect the closing flag 69 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver The X86 received frame is aborted if If 7d 7E is detected This is an abort packet sequence in X 86 Invalid FCS is detected The received frame has less than 6 octets Control SAPI and address field are mismatched to the programmed value Octet 7d and octet other than 5d 5e 7e or dd is detected For the transmitter if X 86 is enabled the sequence of processing is as follows Construct frame including start flag SAPI Control and MAC frame Calculate FCS Pe
261. et to 0 Since the maximum E bit count in a one second period is 1000 this counter cannot saturate The counter is disabled during loss of sync at either the FAS or CRCA level it continues to count if loss of multiframe sync occurs at the CAS level 80 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 8 DSO Monitoring Function The transceiver has the ability to monitor one DSO 64kbps channel in the transmit direction and DSO channel in the receive direction at the same time In the transmit direction the user determines which channel is to be monitored by properly setting the TCMO to TCM4 bits in the TR TDSOSEL register In the receive direction the RCMO to RCMA bits in the TR RDSOSEL register need to be properly set The DSO channel pointed to by the TCMO to TCM4 bits appear in the transmit DSO monitor TR TDSOM register The DSO channel pointed to by the RCMO to RCM4 bits appear in the receive DSO TR RDSOM register The TCM4 to TCMO and RCM4 to RCMO bits should be programmed with the decimal decode of the appropriate T1or E1 channel T1 channels 1 through 24 map to register values 0 through 23 E1 channels 1 through 32 map to register values 0 through 31 For example if DSO channel 6 in the transmit direction and DSO channel 15 in the receive direction needed to be monitored then the following values would be programmed into TR TDSOSEL and TR RDSOSEL TCM4 0 RCM4 0 TCM3 0 RCM3 1 TCM2 1 RCM2
262. f TCLKO with the bipolar data out of the transmit side formatter This pin is normally connected to TNEGI TPOSI B3 Transmit Positive Data Input Sampled on the falling edge of TDCLKI for data to be transmitted out onto the T1 line Can be internally connected to TPOSO by connecting the LIUC pin high TPOSI and TNEGI can be connected together in NRZ applications TPOSO E1 Transmit Positive Data Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter Can be programmed to source NRZ data by the output data format TR IOCR1 0 control bit This pin is normally connected to TPOSI TDATA A4 Transmit Data Sampled on the falling edge of TCLKT with data to be clocked through the transmit side formatter This pin is normally connected to TESO TESO D4 Transmit Elastic Store Output Updated on the rising edge of TCLKT with data out of the transmit side elastic store whether the elastic store is enabled or not This pin is normally connected to TDATA 35 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION HARDWARE AND STATUS PINS Line Interface Unit Connect When a logic low is present on this input pin the T1 E1 J1 Framer and LIU are not internally connected The line interface circuitry will be separated from the framer formatter circuitry and the TPOSI TNEGI TDCLKI RPOSI RNEGI and RDCL
263. f packet processing is disabled inter frame padding is not performed Packet abort insertion inserts a packet abort sequences as necessary If a packet abort indication is detected a packet abort sequence is inserted and inter frame padding is done until a packet start flag is detected The abort sequence is FFh If packet processing is disabled packet abort insertion is not performed The packet scrambler is a x 1 scrambler that scrambles the entire packet data stream The packet scrambler runs continuously and is never reset In bit synchronous mode scrambling is performed one bit at a time In byte synchronous mode scrambling is performed 8 bits at a time Packet scrambling is programmable Once all packet processing has been completed serial data stream is passed on to the Transmit Serial Interface 65 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 18 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling packet delineation inter frame fill filtering packet abort detection destuffing packet size checking FCS error monitoring FCS byte extraction and bit reordering The data coming from the Receive Serial Interface is a serial data stream Packet processing can be disabled clear channel enable Disabling packet processing disables packet delineation inter frame fill filtering packet abort detection destuffing packet size c
264. for both T1 E1 and applications that use gapped clocks The TDEN signal is provided for interfacing to framers that do not have a gapped clock facility Transmit Byte Sync Output This output can be used by an external Serial to Parallel to convert TSERO stream to byte wide data This output indicates the last bit of the byte data sent serially on TSERO This signal is only active in the X 86 Mode T1 E1 J1 RECEIVE FRAMER INTERFACE RSERO H2 Receive Serial Data for T1 E1 J1 Transceiver Received NRZ serial data Updated on rising edges of RCLKO when the receive side elastic store is disabled Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled RCLKO G3 Receive Clock Output from the T1 E1 J1 Framer 1 544MHz T1 or 2 048MHz E1 clock that is used to clock data through the receive side framer Normally connected to the RCLKI input RCHBLK A1 Receive Channel Block for the T1 E1 J1 Transceiver A user programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels Synchronous with RCLKO when the receive side elastic store is disabled Synchronous with RSYSCLK when the receive side elastic store is enabled Also useful for locating individual channels in drop and insert applications for external per channel loopback and for per channel conditioning See the Channel Blocking Registers section RCHCLK G2 Rece
265. g to the TR PCDR1 TR PCDR3 registers for 1 mode and TR PCDR1 TR PCDRA registers for E1 mode E1 mode the user generally selects all channels or none for reinsertion In E1 mode signaling reinsertion on all channels can be enabled with a single bit TR SIGCR 7 GRSRE This bit allows the user to reinsert all signaling channels without having to program all channels through the per channel function 10 9 2 2 Force Receive Signaling All Ones In T1 mode the user can on a per channel basis force the robbed bit signaling bit positions to a 1 by using the per channel register Section 10 2 The user sets the BTCS bit in the TR PCPR register The channels that will be forced to 1 are selected by writing to the TR PCDR1 TR PCDRS registers 10 9 2 3 Receive Signaling Freeze The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of synchronization OOF event carrier loss or frame slip This action meets the requirements of BellCore TR TSY 000170 for signaling freezing To allow this freeze action to occur the RFE control bit TR SIGCR 4 should be set high The user can force a freeze by setting the RFF control bit TR SIGCR 3 high The RSIGF output pin provides a hardware indication that a freeze is in effect The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG pin and at the RSERO pin if receive signaling reinsertion is enabled When f
266. gh host processor intervention There are 2 basic mechanisms that are used for flow control e In half duplex mode a jam sequence is sent that causes collisions at the far end The collisions cause the transmitting node to reduce the rate of transmission e In full duplex mode flow control is initiated by the receiving node sending a pause frame The pause frame has a timer parameter that determines the pause timeout to be used by the transmitting node Note that the terms transmit queue and receive queue are with respect to the Ethernet Interface The Receive Queue is the queue for the data that arrives on the MII RMII interface is processed by the MAC and stored in the SDRAM Transmit queue is for data that arrives from the Serial port is processed by the HDLC and stored in the SDRAM to be sent to the MAC transmitter The following flow control options are possible e Automatic flow control can be enabled in software mode with the SU GCR ATFLOW bit Note that the user does not have control over SU MACFCR FCE and FCB bits if ATFLOW is set The mechanism of sending pause or jam is dependent only on the receive queue high threshold e Manual flow control can be performed through software when SU GCR ATFLOWZ O The host processor must monitor the receive queues and generate pause frames full duplex and or jam bytes through the SU MACFCR FCB SU GCR JAME and SU MACFCR FCE bits Note that in order to use flow control the receive queue si
267. gister Register Address 100h Bit 7 6 5 4 3 2 1 0 Name RDENPLT Default 0 0 0 0 0 0 0 0 Bit 0 Receive Data Enable Polarity RDENPLT Receive Data Enable Polarity If set to 1 RDEN Low enables reception of the bit LI RPPCL Receive Packet Processor Control Low Register Register Name Register Description Register Address 101h Bit 7 6 5 4 3 2 1 0 Name RFPD RF16 RFED RDD RBRE RCCE Default 0 0 0 0 0 0 0 0 Bit 5 Receive FCS Processing Disable RFPD When equal to 0 FCS processing is performed and FCS is appended to packets When set to 1 FCS processing is disabled the packets do not have an FCS appended In X 86 mode FCS processing is always enabled Bit 4 Receive FCS 16 Enable RF16 When 0 the error checking circuit uses a 32 bit FCS When 1 the error checking circuit uses a 16 bit FCS This bit is ignored when FCS processing is disabled In X 86 mode the FCS is always 32 bits Bit 3 Receive FCS Extraction Disable RFED When 0 the FCS bytes are discarded When 1 the FCS bytes are passed on This bit is ignored when FCS processing is disabled In X 86 mode FCS bytes are discarded Bit 2 Receive Descrambling Disable RDD When equal to 0 1 descrambling is performed When set to 1 descrambling is disabled Bit 1 Receive Bit Reordering Enable RBRE When equal to 0 reordering is disabled and the firs
268. gister Address 40h Bit 7 6 5 4 3 2 1 0 Name GRSRE RFE RFF RCCS TCCS FRSAO Defaut 0 0 9 o 9 Bit 7 Global Receive Signaling Reinsertion Enable GRSRE This bit allows the user to reinsert all signaling channels without programming all channels through the per channel function 0 do not reinsert all signaling 1 reinsert all signaling Bit 4 Receive Freeze Enable RFE See Section 10 9 2 3 for details 0 no freezing of receive signaling data occurs 1 allow freezing of receive signaling data at RSIG and RSERO if receive signaling reinsertion is enabled Bit 3 Receive Force Freeze RFF Freezes receive side signaling at RSIG and RSERO if receive signaling reinsertion is enabled overrides receive freeze enable RFE See Section 10 9 2 3 for details 0 do not force a freeze event 1 7 force a freeze event Bit 2 Receive Time Slot Control for CAS Signaling RCCS Controls the order that signaling is placed into the receive signaling registers This bit should be set 0 in T1 mode 0 7 signaling data is CAS format 1 signaling data is CCS format Bit 1 Transmit Time Slot Control for CAS Signaling TCCS Controls the order that signaling is transmitted from the transmit signaling registers This bit should be set 0 in T1 mode 0 7 signaling data is CAS format 1 7 signaling data is CCS format Bit 0 Force Receive Signaling All Ones FRSAO In T1 mode this bit forces all signaling data at the
269. gisters 0 7 do not source signaling data from the TR TSx registers for this channel 1 source signaling data from the TR TSx registers for this channel 210 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR T1RDMR1 Register Description T1 Receive Digital Milliwatt Enable Register 1 Register Address 0Ch Bit 7 6 5 4 3 2 1 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Digital Milliwatt Enable for Channels 1 to 8 CH1 to CH8 0 do not affect the receive data associated with this channel 1 7 replace the receive data associated with this channel with digital milliwatt code Register Name TR T1RDMR2 Register Description T1 Receive Digital Milliwatt Enable Register 2 Register Address 0Dh Bit 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Digital Milliwatt Enable for Channels 9 to 16 CH9 to CH16 0 7 do not affect the receive data associated with this channel 1 replace the receive data associated with this channel with digital milliwatt code Register Name TR T1TRDMR3 Register Description T1 Receive Digital Milliwatt Enable Register 3 Register Address OEh Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Digital Milliwatt Enable for Channels 17 to 24 CH17 to CH24 0 do not affect
270. h TSYSCLK when the transmit side elastic store is enabled Useful for locating individual channels in drop and insert applications for external per channel loopback and for per channel conditioning TCHCLK G1 Transmit Channel Clock for the T1 E1 J1 Transceiver A 192kHz T1 or 256kHz E1 clock that pulses high during the LSB of each channel Can also be programmed to output a gated transmit bit clock for fractional T1 E1 applications Synchronous with TCLKT when the transmit side elastic store is disabled Synchronous with TSYSCLK when the transmit side elastic store is enabled Useful for parallel to serial conversion of channel data TSSYNC A5 Transmit System Sync for the T1 E1 J1 Transceiver Only used when the transmit side elastic store is enabled A pulse at this pin will establish either frame or multiframe boundaries for the transmit side Should be tied low in applications that do not use the transmit side elastic store TSYNC C1 Transmit Sync for the T1 E1 J1 Transceiver pulse at this pin will establish either frame or multiframe boundaries for the transmit side Can be programmed to output either a frame or multiframe pulse If this pin is set to output pulses at frame boundaries it can also be set via TR IOCR1 3 to output double wide pulses at signaling frames in T1 mode TSYSCLK 4 Transmit System Clock for the T1 E1 J1 Transceiver 1 544 2 2 048MHz 4 096MHz 8
271. h identifies frame boundaries Receive Multiframe Sync for the T1 E1 J1 Transceiver An extracted pulse one RCLKO wide elastic store disabled or one RSYSCLK wide elastic store enabled is output at this pin which identifies multiframe boundaries RMSYNC U3 Receive Signaling Output Outputs signaling bits in a PCM RSIG L3 format Updated on rising edges of RCLKO when the receive side elastic store is disabled Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled 33 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION ETHERNET MAPPER RECEIVE SERIAL INTERFACE Receive Serial Data Input to Ethernet Mapper Receive Serial RSERI H1 data arrives on the rising edge of RCLKI Normally connected to RSERO Serial Interface Receive Clock Input to the Ethernet Mapper RCLKI F2 Reference clock for receive serial data on RSERI Gapped clocking is supported up to the maximum RCLKI frequency of 52 MHz Receive Data Enable for the Ethernet Mapper The receive data enable is programmable to block the receive data The RDEN must be coincident with the RSERI data bit to be blocked or enabled The active polarity of is programmable in register LI RSLCR It is recommended for both T1 E1 and T3 E3 applications that use gapped clocks The RDEN signal is provided for interfacing to framers that do not have a gapped c
272. h of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital milliwatt pattern The digital milliwatt code is an 8 byte repeating pattern that represents a 1kHz sine wave 1E 0B 0B 1E 9E 8B 8B 9E Each bit in the TR TTRDMRx registers represents a particular channel If a bit is set to a 1 then the receive data in that channel is replaced with the digital milliwatt code If a bit is set to 0 no replacement occurs Table 10 2 T1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA Note 1 fewer Os are received more Os are received Yellow Alarm RAI When bit 2 of 256 consecutive When bit 2 of 256 consecutive D4 Bit 2 Mode channels is set to O for at least 254 channels is set to O for fewer than TR T1RCR2 0 0 occurrences 254 occurrences D4 12th F Bit Mode When the 12th framing bit is setto 1 When the 12th framing bit is set to TR T1RCR2 0 1 this mode is for two consecutive occurrences 0 for two consecutive occurrences also referred to as the Japanese Yellow Alarm ESF Mode When 16 consecutive patterns of When 14 or fewer patterns of OOFF OOFF appear in the FDL hex out of 16 possible appear in the FDL Red Alarm LRCL When 192 consecutive Os are When 14 or more 1s out of 112 Also referred to as loss of signal received possible bit positions are received Note 1 The definition of Blue Alarm or AIS is an unframed all ones signal Blue Alarm detectors should be able to operate properly in
273. h the rising edge of REF_CLK Transmit Enable MII This pin is asserted high when data TXD 3 0 is being provided by the DS33R11 The signal is deasserted prior to the first nibble of the next frame This signal is synchronous TX EN F20 with the rising edge TX CLK It is asserted with the first bit of the preamble Transmit Enable RMII When this signal is asserted the data on TXD 1 0 is valid This signal is synchronous to the REF CLK Reference Clock RMII and MII When in RMII mode all signals from the PHY are synchronous to this clock input for both transmit and receive This required clock can be up to 50MHz and should have 100ppm accuracy When in MII mode in DCE operation the DS33R11 uses this input to generate the RX CLK and TX CLK outputs as required for the Ethernet PHY interface When the MII interface is used with DTE operation this clock is not required and should be tied low REF CLK A19 In DCE and RMII modes this input must have a stable clock input before setting the RST pin high for normal operation Reference Clock Output RMII and MII A derived clock output up to 50MHz generated by internal division of the SYSCLKI signal REF CLKO A20 Frequency accuracy of the REF CLKO signal will be proportional to the accuracy of the user supplied SYSCLKI signal See Section 9 1 1 for more information DCE or DTE Selection The user must set this pin high for DCE Mode selection or low for DTE
274. he Shift IR state Shift IR In this state the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output The parallel register as well as all test registers remains at their previous states A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1 IR state A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift IR state while moving data one stage thorough the instruction shift register Exit1 IR A rising edge on JTCLK with JTMS LOW will put the controller in the Pause IR state If JTMS is HIGH on the rising edge of JTCLK the controller will enter the Update IR state and terminate the scanning process Pause IR Shifting of the instruction shift register is halted temporarily With JTMS HIGH a rising edge on JTCLK will put the controller in the Exit2 IR state The controller will remain in the Pause IR state if JTMS is LOW during a rising edge on JTCLK Exit2 IR A rising edge on JTCLK with JTMS LOW will put the controller in the Update IR state The controller will loop back to Shift IR if JTMS is HIGH during a rising edge of JTCLK in this state Update IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state Once latched this instruction becomes the current instruction A rising edge
275. he data is enabled and output by the DS33R11 LI RSTPD Serial Interface Reset Register Register Name Register Description Register Address 0C1h Bit 7 6 5 4 3 2 1 0 Name RESET Default 0 0 0 0 0 0 0 0 Bit 1 RESET If this bit set to 1 the Data Path and Control and Status for this interface are reset The Serial Interface is held in Reset as long as this bit is high This bit must be high for a minimum of 200ns for a valid reset to occur 151 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver LI LPBK Serial Interface Loopback Control Register Register Name Register Description Register Address 0C2h Bit 7 6 5 4 3 2 1 0 Name s QLP Default 0 0 0 0 0 0 0 0 Bit 0 Queue Loopback Enable QLP If this bit set to 1 data received on the Serial Interface is looped back to the Serial Interface transmitter Received data will not be sent from the Serial Interface to the Ethernet Interface Buffered packet data will remain in queue until the loopback is removed 11 5 1 2 Transmit HDLC Processor Register Bit Descriptions LI TPPCL Transmit Packet Processor Control Low Register Register Name Register Description Register Address 0C4h Bit 7 6 5 4 3 2 1 0 Name TFAD TF16 TIFV TSD TBRE TIAEI Default 0 0 0 0 0 0 0 0 Note The user should take care not to modify
276. he extracted packets over the Ethernet port The WAN serial port can operate with a gapped clock and is designed to be connected to the integrated T1 E1 J1 transceiver for transmission The DS33R11 be configured through an 8 bit microprocessor interface port Diagnostic capabilities include loopbacks PRBS pattern generation detection and 16 bit loop up loop down code generation and detection The DS33R11 provides two on board clock dividers for the system clock input and reference clock input for the 802 3 interfaces further reducing the need for ancillary devices The integrated transceiver is a software selectable T1 E1 or J1 single chip transceiver SCT for short haul and long haul applications The transceiver is composed of an LIU framer HDLC controllers and a TDM backplane interface and is controlled by the 8 bit parallel port The transceiver is software compatible with the DS2155 and 052156 The LIU is composed of transmit and receive interfaces and jitter attenuator The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used T1 waveform generation includes DSX 1 line build outs as well as CSU line build outs of 7 5dB 15dB and 22 5dB E1 waveform generation includes G 703 waveshapes for both 75Q coax and 1200 twisted cables The receive interface provides network termination and recovers clock and dat
277. he following occurs 1 T1 Mode An unframed all ones code is transmitted at TPOSO and TNEGO E1 Mode Normal data is transmitted at TPOSO and TNEGO 2 Data at RPOSI and RNEGI is ignored 3 All receive side signals take on timing synchronous with TCLKT instead of RDCLKI Please note that it is not acceptable to have RCLKO connected to TCLKT during this loopback because this causes an unstable condition 242 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR PCLR1 Register Description Per Channel Loopback Enable Register 1 Register Address 4Bh Bit 7 6 5 4 3 2 1 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits 0 7 Per Channel Loopback Enable for Channels 1 to 8 CH1 to CH8 0 loopback disabled 1 enable loopback source data from the corresponding receive channel Register Name TR PCLR2 Register Description Per Channel Loopback Enable Register 2 Register Address 4Ch Bit 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 7 Per Channel Loopback Enable for Channels 9 to 16 CH9 to CH16 0 loopback disabled 1 enable loopback source data from the corresponding receive channel Register Name TR PCLR3 Register Description Per Channel Loopback Enable Register 3 Register Address 4Dh Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0
278. hecking FCS error monitoring and FCS byte extraction Only packet descrambling and bit reordering are not disabled The packet descrambler is a self synchronous x 1 descrambler that descrambles the entire packet data stream Packet descrambling is programmable The descrambler runs continuously and is never reset The descrambling is performed one bit at a time Packet descrambling is programmable If packet processing is disabled the serial data stream is demultiplexed in to an 8 bit data stream before being passed on If packet processing is disabled a packet boundary is arbitrarily chosen and the data is divided into packets of programmable size dependent on maximum packet size setting These packets are then passed on to bit reordering with packet start and packet end indications Data then bypasses packet delineation inter frame fill filtering packet abort detection destuffing packet size checking FCS error monitoring and FCS byte extraction Packet delineation determines the packet boundary by identifying a packet start or end flag Each time slot is checked for a flag sequence 7Eh Once a flag is found it is identified as a start end flag and the packet boundary is set The flag check is performed one bit at a time If packet processing is disabled packet delineation is not performed Inter frame fill filtering removes the inter frame fill between packets When a packet end flag is detected all data is discarded until a pac
279. hen 915 1000 codewords are received in error Bit 1 FAS Resync Criteria Met Event FASRC Set when three consecutive FAS words are received in error Note During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment If during this process an FAS emulator exists the FAS synchronizer may temporarily align to the emulator The FASRC will go active indicating a search for a valid FAS has been activated Bit 0 CAS Resync Criteria Met Event CASRC Set when two consecutive CAS MF alignment words are received in error Register Name TR IIR1 Register Description Interrupt Information Register 1 Register Address 14h Bit 7 6 5 4 3 2 1 0 Name SR8 SR SR6 SR5 SR4 SR3 SR2 SR1 Defaut o 0 o o o o 0 j 0 Bits 0 7 Status Register 1 8 SR1 SR8 When set to 1 these bits indicate that an enabled interrupt is active in the associated T1 E1 J1 status register Register Name TR IIR2 Register Description Interrupt Information Register 2 Register Address 15h Bit 7 6 5 4 3 2 1 0 SR9 Defaut 39 0o o o 0o o o o Bits 0 Status Register 9 SR9 When set to 1 this bit indicates that an enabled interrupt is active in the associated T1 E1 J1 status register 214 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR1 Register Description Status Register 1 Register Address 16h Bit 7 6 5 4 3 2 1 0 IL
280. her bipolar violations or code violations can be counted Bipolar violations are defined as consecutive marks of the same polarity In this mode if the HDB3 mode is set for the receive side then HDB3 codewords are not counted as BPVs If TR ERCNT 3 is set then the LVC counts code violations as defined ITU O 161 Code violations are defined as consecutive bipolar violations of the same polarity In most applications the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code This counter increments at all times and is not disabled by loss of sync conditions The counter saturates at 65 535 and does not roll over The bit error rate on an E1 line would have to be greater than 10 before the VCR would saturate Table 10 6 Table 10 6 E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT TR ERCNT 3 COUNTED IN THE LCVCRs CVs 78 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 7 2 Path Code Violation Count Register TR PCVCR In T1 mode the path code violation count register records Ft Fs or CRC6 errors in T1 frames When the receive side of a framer is set to operate in the T1 ESF framing mode TR PCVCR records errors in the CRC6 codewords When set to operate in the T1 D4 framing mode TR PCVCR counts errors in the Ft framing bit position Through the TR ERCNT 2 bit a framer can be programmed to also report errors in the Fs framing bit posi
281. hernet Mapper with Integrated T1 E1 J1 Transceiver 13 2 MII Interface Table 13 5 Transmit MII Interface Note 1 Figure 13 1 PARAMETER SYMBOL 10 WW toners wax UNITS TX Period t1 400 40 ns TX_CLK Low Time 2 140 260 14 26 ns TX CLK High Time t3 140 260 14 26 ns TX CLK to TXD TX EN Delay t4 0 20 0 20 ns Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 1 Transmit MII Interface Timing TX CLK TXD 3 0 315 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 13 6 Receive MII Interface Note 1 Figure 13 2 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD RX_DV to RX_CLK Setup t8 5 5 Time RX CLK to RXD RX DV Hold 9 5 5 nS Time Note 1 Timing parameters in this table are guaranteed by design GBD Figure 13 2 Receive MII Interface Timing RX_CLK 316 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 13 3 RMII Interface Table 13 7 Transmit RMII Interface Note 1 Figure 13 3 PARAMETER SYMBOL 10 SAX WIN tomes UNITS REF_CLK Frequency REF Period t1 20 20 ns REF_CLK Low Time 2 13 7 13 ns REF_C
282. host terminates the loop by writing a new message to the FIFO the loop terminates one or two flags are transmitted and the new message starts If not disabled through TCRCD the transmitter automatically appends a 2 byte CRC code to the end of all messages This is useful for transmitting consecutive 557 FISUs without host intervention Bit 5 Transmit HDLC Reset THR Resets the transmit HDLC controller and flushes the transmit FIFO An abort followed by 7Eh or FFh flags idle is transmitted until a new packet is initiated by writing new data into the FIFO Must be cleared and set again for a subsequent reset 0 normal operation 1 reset transmit HDLC controller and flush the transmit FIFO Bit 4 Transmit HDLC Mapping Select THMS 0 transmit HDLC assigned to channels 1 transmit HDLC assigned to FDL T1 mode Sa bits E1 mode Bit 3 Transmit Flag Idle Select TFS This bit selects the intermessage fill character after the closing and before the opening flags 7Eh 0 7Eh 1 2 Transmit End of Message Should be set to 1 just before the last data byte of an HDLC packet is written into the transmit FIFO at HxTF If not disabled through TCRCD the transmitter automatically appends a 2 byte CRC code to the end of the message Bit 1 Transmit Zero Stuffer Defeat TZSD The zero stuffer function automatically inserts a 0 in the message field between the flags after five consecutive 1s to prevent the em
283. hrough TR T1TCR1 4 T1 mode or TR E1TCR1 6 E1 mode In T1 mode only TS1 TS12 are used Signaling data can be sourced from the TR TS registers on a per channel basis by using the software signaling insertion enable registers TR SSIE1 TRSSIE4 10 9 3 1 T1 Mode In T1 ESF framing mode there are four signaling bits per channel A B and D TS1 TS12 contain a full multiframe of signaling data In T1 D4 framing mode there are only two signaling bits per channel A and B In T1 D4 framing mode the framer uses the C and D bit positions as the A and B bit positions for the next multiframe In D4 mode two multiframes of signaling data can be loaded into TS1 TS12 The framer loads the contents of 51 512 into the outgoing shift register every other D4 multiframe In D4 mode the host should load new contents into 51 512 on every other multiframe boundary and no later than 120 after the boundary In T1 mode only registers TR SSIE1 TR SSIE3 are used since there are only 24 channels in a T1 frame 84 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 9 3 2 E1 Mode In E1 mode 516 carries the signaling information This information can be in either CCS common channel signaling or CAS channel associated signaling format The 32 time slots are referenced by two different channel number schemes E1 In Channel numbering TS0 TS31 are labeled channels 1 through 32 In Phone Channel numbering T
284. iated this bit must be set to 0 and back to 1 If PMU goes low before the PMS bit goes high an update might not be performed Bit 5 Receive New Pattern Load RNPL A zero to one transition of this bit will cause the programmed test pattern QRSS PTS PLF 4 0 PTF 4 0 and BSP 31 0 to be loaded in to the receive pattern generator This bit must be changed to zero and back to one for another pattern to be loaded Loading a new pattern will forces the receive pattern generator out of the Sync state which causes a resynchronization to be initiated Note QRSS PTS PLF 4 0 PTF 4 0 and BSP 31 0 must not change from the time this bit transitions from O to 1 until four RCLKI clock cycles after this bit transitions from O to 1 Bit 4 Receive Pattern Inversion Control RPIC When 0 the receive incoming data stream is not altered When 1 the receive incoming data stream is inverted Bit 3 Manual Pattern Resynchronization MPR A zero to one transition of this bit will cause the receive pattern generator to resynchronize to the incoming pattern This bit must be changed to zero and back to one for another resynchronization to be initiated Note A manual resynchronization forces the receive pattern generator out of the Sync state Bit 2 Automatic Pattern Resynchronization Disable When 0 the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during the current 64 bit windo
285. icate the packet size the incoming data is to be broken into The maximum packet size allowable is 2016 bytes plus the FCS bytes Any values programmed that are greater than 2016 FCS will have the same effect as 2016 FCS value In X 86 mode the X 86 encapsulation bytes are included in maximum size control Register Name LI RPPSR Register Description Receive Packet Processor Status Register Register Address 104h Bit 7 6 5 4 3 2 1 0 Name REPC RAPC RSPC Default 0 0 0 0 0 0 0 0 Bit 2 Receive FCS Errored Packet Count REPC This read only bit indicates that the receive FCS errored packet count is nonzero Bit 1 Receive Aborted Packet Count RAPC This read only bit indicates that the receive aborted packet count is nonzero Bit 0 Receive Size Violation Packet Count This read only bit indicates that the receive size violation packet count is nonzero 162 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RPPSRL Register Description Receive Packet Processor Status Register Latched Register Address 105h Bit 7 6 5 4 3 2 1 0 Name REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL Default Bit 7 Receive FCS Errored Packet Latched REPL This bit is set when a packet with an errored FCS is detected Bit 6 Receive Aborted Packet Latched RAPL This bit is set when a pa
286. in a Maxim Dallas Semiconductor product No circuit patent licenses are implied Maxim Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2007 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor Corporation
287. intenacs Register BI Msn np HE ERR EOM ERIS Li ERE e EE REOR 122 SIL 123 11 2 GLOBAL REGISTER DEFINITIONS FOR ETHERNET 134 ille ARBITER REG Ga Oda CH nOD DECORE Kad Pac raa oer p EG CRF URL 143 VEL DOG ONO 143 BERI REDSLER Sasha sisi anneal ass Y LER CE i rf 144 TES SERISE INTERFACE icis pe certo pe Pa tae ert rd He du eo teats 151 77 5 Serial interface Transmit and Common ais aak 151 11 5 2 Serial Interface Transmit Register Bit Descriptions eese anus sene nane kn Rabe ke EE aan 151 152 TRANSAT HDLC Aa 152 TLGA WES 41 200 2 0 m 159 UE Gena NETO m 161 1 ETHERNET INTERFACE REGISTERS CHR ie 174 146 1 Ethene ternate Register Bie el GM 174 186 Tq TIVE TAL TRANSCEIVER REGISTERS 201 TAM UC 2e Len 299 12 FUNCTIONAL TIMING ciiis pni ioo Inno ER RRDa ER CUNG inna Fox ky 300 12 1 FUNCTIONAL SERIAL I O 0 0 000000000000000001 s sse a snis 300 122 MM ANID INTERFACES oso uar
288. ion the associated performance monitoring update signal xxPMU During the counter register update process the associated performance monitoring status signal xxPMS is deasserted The counter register update process consists of loading the counter register with the current count resetting the counter forcing the zero count status indication low for one clock cycle and then asserting xxPMS No events are missed during this update procedure A latched bit is set when the associated event occurs and remains set until it is cleared by reading Once cleared a latched bit will not be set again until the associated event occurs again Reserved configuration bits and registers should be written to zero 11 5 1 Serial Interface Transmit and Common Registers Serial Interface Transmit Registers are used to control the HDLC transmitter associated with each Serial Interface The register map is shown in the following Table Note that throughout this document the HDLC Processor is also referred to as a packet processor 11 5 1 1 Serial Interface Transmit Register Bit Descriptions LI TSLCR Transmit Serial Interface Configuration Register Register Name Register Description Register Address 0COh Bit 7 6 5 4 3 2 1 0 Name 2 TDENPLT Default 0 0 0 0 0 0 0 0 Bit 0 Transmit Data Enable Polarity TDENPLT If set to 1 TDEN is active low for enable In the default mode when TDEN is logic high t
289. ion receive mode Bit 1 Transmit Synchronization G 703 Clock Enable TSCLKE 0 disable 1 544MHz T1 2 048MHz E1 transmit synchronization clock 1 enable 1 544MHz T1 2 048MHz E1 transmit synchronization clock Bit 0 Transmit Alternate Ones and Zeros TAOZ Transmit a 101010 pattern customer disconnect indication signal at TTIP and TRING The transmission of this data pattern is always timed off of TCLKT 0 7 disabled 1 enabled 258 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR LIC4 Register Description Line Interface Control 4 Register Address 7Bh Bit 7 6 5 4 3 2 1 0 Name CMIE 51 50 TT1 TTO RT1 RTO Defaut 0 0 0 0 0 O 0 0 Bit 7 CMI Enable CMIE 0 disable CMI mode 1 enable CMI mode Bit 6 CMI Invert CMII 0 CMI normal at TTIP and RTIP 1 invert CMI signal at TTIP and Bits 4 5 MCLK Prescaler T1 Mode MCLK MHz MPS MPSO RECS 1 544 0 0 0 3 088 0 1 0 6 176 1 0 0 12 352 1 1 0 2 048 0 0 1 4 096 0 1 1 8 192 1 0 1 16 384 1 1 1 E1 Mode MCLK JAMUX MHz MES MPSO TR LIC2 3 2 048 0 0 0 4 096 0 1 0 8 192 1 0 0 16 384 1 1 0 Bits 2 3 Transmit Termination Select TTO TT1 TT1 TTO Internal Transmit Termination Configuration 0 0 Internal transmit side termination disabled 0 1 Internal transmit side 75Q enab
290. is is because of the highly over sampled digital clock recovery circuitry See the Receive AC Timing Characteristics in Section 13 9 for more details When no signal is present at RTIP and RRING a receive carrier loss RCL condition occurs and the RCLKO is derived from the JACLK source 100 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 20 2 1 Receive Level Indicator and Threshold Interrupt The device reports the signal strength at RTIP and RRING in 2 5dB increments through RL3 RLO located Information Register 2 TR INFO2 This feature is helpful when trouble shooting line performance problems The device can initiate an interrupt whenever the input falls below a certain level through the input level under threshold indicator TR SR1 7 Using the RLTO RLTA bits of the TR CCR4 register the user can set a threshold 2 5dB increments The TR SR1 7 bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in RLTO RLTA The level must remain below the programmed threshold for approximately 50ms for this bit to be set The accuracy of the receive level indication is 1 LSB 2 5dB from 25 C to 85 C and 2 LSBs 5dB from 40 C to 25 C 10 20 2 2 Receive G 703 Synchronization Signal E1 Mode The transceiver is capable of receiving a 2 048MHz square wave synchronization clock as specified in Section 13 of ITU G 703 October 1998 In order to use the device in this mode
291. is turned off 1 REF CLKO is disabled and outputs an active low signal 0 REF CLKO is active and in accordance with RMII MII Selection Bit 1 INT pin mode INTM This bit determines the inactive mode of the INT pin The INT pin always drives low when active 1 Pin is high impedance when not active 0 Pin drives high when not active Bit 0 Reset RST When this bit is set to 1 all of the internal data path and status and control registers except this RST bit on all ports are reset to their default state This bit must be set high for a minimum of 100ns 0 Normal operation 1 Reset and force all internal registers to their default values Register Name GL BLR Register Description Global BERT Connect Register Register Address 03h Bit 7 5 4 2 1 0 Name BLC1 Default 0 0 0 0 0 0 Bit 0 BERT Connect 1 BLC1 If this bit is set to 1 the BERT is connected to Serial Interface 1 The BERT transmitter is connected to the transmit serial port and receive to receive serial port When the BERT is connected normal data transfer is interrupted Note that connecting the BERT overrides a connection to the Serial Interface if a connection exists When the BERT is disconnected the connection is restored 135 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver GL RTCAL Global Receive and Transmit Serial Port Clock Activity Latched Status Register Name Register D
292. ished specifications known as errata Multiple revisions of any device be simultaneously available through various sales channels For information about device errata click here www maxim ic com errata 1 of 344 REV 030807 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 1 2 TABLE OF CONTENTS DESCRIPTION 9 FEATURE QE QN EIU 11 2 1 11 2 2 MICROPROCESSOR 0000 enm rhee rere erre ree eee ree enne T3 23 HDLC ETHERNET MAPPING AGIR Hot a Env Fg cu ec RN LE VR E 11 24 86 LINK ACCESS PROTOCOL FOR SONET SDH ETHERNET MAPPING emen 11 2 5 ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1 E1 J1 12 2 6 COMMITTED INFORMATION RATE CIR A PEE E 12 Al ODORAM INTERFACE a a a ean 12 2 9 MAC INTERFACE 12 ZI ONE INTERFACE 13 2 10 CLOCK aT SZER Pot RR Re mE 13 13 DUET PRAMEN 14 p uU M M 14 CET 15 2 15 SPECIFICATIONS
293. isted cables AIS generation independent of loopbacks Alternating ones and zeros generation Square wave output Open drain output option NRZ format option Transmitter power down Transmitter 50mA short circuit limiter with current limit exceeded indication Transmit open circuit detected indication Line interface function can be completely decoupled from the framer formatter 2 10 Clock Synthesizer Output frequencies include 2 048 2 4 096MHz 8 192 2 and 16 384MHz Derived from recovered receive clock 2 11 Jitter Attenuator 32 bit or 128 bit crystal less jitter attenuator Requires only a 2 048 2 master clock for both 1 and T1 operation with the option to use 1 544MHz for T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication 13 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 2 12 T1 E1 J1 Framer Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats include D4 SLC 96 and ESF Detailed alarm and status reporting with optional interrupt support Large path and line error counters for o 1 CV CRC6 and framing bit errors o 1 CV CRCA E bit and frame alignment errors Timed or manual update modes DS1 idle code generation on a per channel basis in both transmit and receive paths o User defined o Digital milliwatt ANSI T1 403 1998 Support RAI CI detection and gener
294. it from a 0 to a 1 forces the read and write pointers into opposite frames maximizing the delay through the transmit elastic store Transmit data is lost during the reset It should be toggled after TSYSCLK has been applied and is stable See Section 10 12 3 for details Do not leave this bit set HIGH Bit 5 Transmit Elastic Store Minimum Delay Mode TESMDM See Section 10 12 4 for details 0 elastic stores operate at full two frame depth 1 elastic stores operate at 32 bit depth Bit 4 Transmit Elastic Store Enable TESE 0 elastic store is bypassed 1 elastic store is enabled Bit 3 Receive Elastic Store Align RESALGN Setting this bit from a 0 to a 1 forces the receive elastic store s write read pointers to a minimum separation of half a frame No action is taken if the pointer separation is already greater or equal to half a frame If pointer separation is less than half a frame the command is executed and the data is disrupted It should be toggled after RSYSCLK has been applied and is stable Must be cleared and set again for a subsequent align See Section 10 12 3 for details Bit 2 Receive Elastic Store Reset RESR Setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames maximizing the delay through the receive elastic store It should be toggled after RSYSCLK has been applied and is stable See Section 10 12 3 for details Do not leave this bit set HIGH Bit 1 Receive Elastic Store Minimum D
295. it value Register description below Register Name RBECR2 Register Description Receive Bit Error Count Byte 2 Register Register Address Bit 7 6 5 4 3 2 1 0 Name BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Error Count BEC 16 23 Upper 8 bits of the register Bit Error Count BEC 0 23 These twenty four bits indicate the number of bit errors detected in the incoming data stream This count stops incrementing when it reaches a count of FF FFFFh The associated bit error counter will not incremented when an OOS condition exists RBCBO Receive Bit Count Byte 0 Register Register Name Register Description Register Address 98h Bit 7 6 5 4 3 2 1 0 Name 6 BC5 BC4 BC3 BC2 BC1 BCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Count BC 0 7 Eight bits of a 32 bit value Register description below 149 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description RBCB1 Receive Bit Count Byte 1 Register 1 Register Address 99h Bit 7 6 5 4 3 2 1 0 15 14 BC13 BC12 BC11 BC10 BC9 BC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Count BC 8 15 Eight bits of a 32 bit value Register description below Register Name RBCB2 Register Description Receive Bit Coun
296. itivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB or 0 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications The jitter attenuator removes phase jitter from the transmitted or received signal The crystal less jitter attenuator requires only a 2 048 2 MCLK for both E1 and T1 applications with the option of using a 1 544MHz MCLK in T1 applications and be placed in either transmit or receive data paths An additional feature of the LIU is a CMI coder decoder for interfacing to optical networks On the transmit side clock data and frame sync signals are provided to the framer by the backplane interface section The framer inserts the appropriate synchronization framing patterns alarm information calculates and inserts the CRC codes and provides the B8ZS HDB3 zero code suppression and AMI line coding The receive side framer decodes AMI B8ZS and HDB3 line coding synchronizes to the data stream reports alarm information counts framing coding CRC errors and provides clock data and frame sync signals to the backplane interface section Diagnostic capabilities include loopbacks PRBS pattern generation detection and 16 bit loop up and loop down code generation and detection Both the transmit and receive path have two HDLC controllers The HDLC controllers transmit and receive data through the framer block The HDLC controllers can be assigned to any time slot group of time slo
297. its have been shifted out the framer signals the host microcontroller by setting the TR SR8 2 bit to a 1 that the buffer is empty and that more data is needed The INT also toggles low if enabled through TR IMR8 2 The user has 2ms to update TR TFDL with a new value If TR TFDL is not updated the old value in TR TFDL is transmitted once again The framer also contains a zero stuffer that is controlled through the TR T1TCR2 5 bit In both ANSI T1 403 and TR54016 communications on the FDL follows a subset of an LAPD protocol The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag 01111110 or an abort signal 11111111 If enabled through TR T1TCR2 5 the framer automatically looks for five 1s in a row If it finds such a pattern it automatically inserts 0 after the five 1s The TR T1TCR2 5 bit should always be set to a 1 when the framer is inserting the FDL 10 18 D4 SLC 96 Operation In the D4 framing mode the framer uses the TR TFDL register to insert the Fs framing pattern To allow the device to properly insert the Fs framing pattern the TR TFDL register at address C1h must be programmed to 1Ch and the following bits must be programmed as shown TR T1TCR1 2 0 source Fs data from the TR TFDL register TR T1TCR2 6 1 allow the TR TFDL register to load on multiframe boundaries Since the SLC 96 message fields share the Fs bit position the user can a
298. itten to the MAC Data has been written after a write command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACWD2 Register Description MAC Write Data Register 2 Register Address 148h Bit 7 6 5 4 3 2 1 0 Name MACWD23 MACWD22 MACWD21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Write Data 2 MACWD16 23 One of four bytes of data to be written to the MAC Data has been written after a write command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACWD3 Register Description MAC Write Data 3 Register Address 149h Bit 7 6 5 4 3 2 1 0 Name MACD31 MACD30 MACD29 MACD28 MACD27 MACD26 MACD25 MACD24 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Write Data 3 MACD24 31 One of four bytes of data to be written to the MAC Data has been written after a write command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACAWL Register Description MAC Address Write Low Register Address 14Ah Bit 7 6 5 4 3 2 1 0 Name MACAW 7 MACAW6 MACAW 5 MACAWA MACAWS MACAW2 MACAW1 MACAWO Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Write Address MACAWO 7 Low byte of the MAC indirect write address Used only for write operations 176 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register
299. ive Channel Clock for the T1 E1 J1 Transceiver A 192kHz T1 or 256kHz E1 clock that pulses high during the LSB of each channel can also be programmed to output a gated receive bit clock for fractional T1 E1 applications Synchronous with RCLKO when the receive side elastic store is disabled Synchronous with RSYSCLK when the receive side elastic store is enabled Useful for parallel to serial conversion of channel data 32 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION Receive Sync for the T1 E1 J1 Transceiver An extracted pulse one RCLKO wide is output at this pin which identifies either frame TR IOCR1 5 0 or multiframe TR IOCR1 5 1 boundaries If set to output frame boundaries then via TR IOCR1 6 RSYNC can SYNC 94 HO also be set to output double wide pulses on signaling frames in T1 mode If the receive side elastic store is enabled then this pin can be enabled to be an input via TR IOCR1 4 at which a frame or multiframe boundary pulse is applied Receive System Clock for the Transceiver 1 544MHz 2 048MHz 4 096 2 or 8 192MHz clock Only used when the receive side elastic store function is enabled Should be tied low in applications that do not use the receive side elastic store RSYSCLK F4 Receive Frame Sync Pre Receive Elastic Store for T1 E1 J1 RFSYNC A3 Transceiver An extracted 8kHz pulse RCLKO wide is output at this pin whic
300. ive FIFO s write pointer is above the watermark If enabled this condition can also cause an interrupt through the INT pin 10 16 3 HDLC Mapping The HDLC controllers must be assigned a space in the T1 E1 bandwidth in which they transmit and receive data The controllers can be mapped to either the FDL T1 Sa bits E1 or to channels If mapped to channels then any channel or combination of channels contiguous or not can be assigned to an HDLC controller When assigned to a channel s any combination of bits within the channel s can be avoided The TR HxRCS1 TR HxRCSA registers are used to assign the receive controllers to channels 1 24 T1 or 1 32 E1 according to the following table REGISTER CHANNELS TR HxRCS1 1 8 TR HxRCS2 9 16 TR HxRCS3 17 24 TR HxRCS4 25 32 The TR HxTCS1 TR HxTCS4 registers are used to assign the transmit controllers to channels 1 24 T1 or 1 32 E1 according to the following table REGISTER CHANNELS TR HxTCS1 1 8 TR HxTCS2 9 16 TR HxTCS3 17 24 TR HxTCS4 25 32 95 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 16 4 FIFO Information The transmit FIFO buffer available register indicates the number of bytes that can be written into the transmit FIFO The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer 10 16 5 Receive Packet B
301. ize of SU RMFSRL frames to be accepted from the MII RMII receive interface MAC Control SU MACCR This register provides configuration control for the MAC 57 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 14 1 DTE and DCE Mode The Ethernet MII RMII port can be configured for DCE or DTE Mode When the port is configured for the DTE Mode it can be connected to an Ethernet PHY In DCE mode the port can be connected to MII RMII MAC devices other than an Ethernet PHY The DTE DCE connections for the DS33R11 in MII mode are shown in the following two figures In DCE Mode the DS33R11 transmitter is connected to an external receiver and DS33R11 receiver is connected to an external MAC transmitter The selection of DTE or DCE mode is done by the hardware pin DCEDTES Figure 9 5 Configured as DTE Connected to an Ethernet PHY in MII Mode DS33R11 N Rx Ethernet Phy RXD 3 0 RXD 3 0 DTE DCE RXDV RXDV RX CLK RX ERR RX CRS COL DET RX CLK RX ERR RX CRS COL DET TXD 3 0 TX CLK TXD 3 0 TX CLK MDIO MDIO MDC MDC A 58 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 9 6 DS33R11 Configured as DCE in MII Mode 0533211 RXD 3 0 RXDV RX_CLK RX_ERR RX_CRS COL_DET Tx TXD 3 0 TXD 3 0 TX CLK TX EN MDIO
302. ket start flag is detected The inter frame fill can be flags or all 15 The number of 1 s between flags does not need to be an integer number of bytes and if at least 7 15 are detected in the first 16 bits after a flag all data after the flag is discarded until a start flag is detected There may be only one flag between packets When the inter frame fill is flags the flags may have a shared zero 011111101111110 If there is less than 16 bits between two flags the data is discarded If packet processing is disabled inter frame fill filtering is not performed Packet abort detection searches for a packet abort sequence Between a packet start flag and a packet end flag if an abort sequence is detected the packet is marked with an abort indication the aborted packet count is incremented and all subsequent data is discarded until a packet start flag is detected The abort sequence is seven consecutive ones If packet processing is disabled packet abort detection is not performed Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence A start flag is detected a packet start is set the flag is discarded destuffing is performed until an end flag is detected a packet end is set and the flag is discarded In bit synchronous mode bit destuffing is performed Bit destuffing consists of discarding any 0 that directly follows five contiguous 1 s After destuffing is completed the serial bit stream
303. kets over the Ethernet ports Access is provided to the signals between the serial port and the integrated T1 E1 J1 transceiver The Ethernet packet interface supports MII and RMII interfaces allowing the DSZ33R11 to connect to commercially available Ethernet PHY and MAC devices The Ethernet interface can be configured for 10Mbit s or 100Mbit s service in DTE and DCE configurations The DS33R11 MAC interface rejects frames with bad FCS and short frames less than 64 bytes Ethernet frames are queued and stored in external 32 bit SDRAM The DS33R11 SDRAM controller enables connection to a 128Mb SDRAM without external glue logic at clock frequencies up to 100MHz The SDRAM is used for both the transmit and receive data queues The receive queue stores data to be sent from the packet interface to the WAN serial interface The transmit queue stores data to be sent from the WAN serial interface to the Ethernet LAN packet interface The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes The sizing of the queues can be adjusted by software The user can also program high and low watermarks for each queue that can be used for automatic or manual flow control The packet data stored in the SDRAM is encapsulated in HDLC or X 86 LAPS to be transmitted over the WAN interface The device also provides the capability for bit and packet scrambling The WAN interface also receives encapsulated Ethernet packets and transmits t
304. l Timing LS LS LY LCI LI LS LU LI L fF US LUIS LO 1 J E A Jj E MJ B L Jj C In RMII Mode TX EN is high with the first bit of the preamble The TXD 1 0 is synchronous with the 50MHz REF CLK For 10 Mbit s operation the data bit outputs are updated every 10 clocks Figure 12 8 RMII Transmit Interface Functional Timing Reck a op oo og ep 0 1 0 d d TX EN 302 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver RMII Receive data on RXD 1 0 is expected to be synchronous with the rising edge of the 50 MHz REF CLK The data is only valid if CRS DV is high The external PHY asynchronously drives CRS_DV low during carrier loss Figure 12 9 RMII Receive Interface Functional Timing mero RXD V OJLPTREETATMYTBTETET f f Pe pe TST 12 3 Transceiver T1 Mode Functional Timing Figure 12 10 Receive Side D4 Timing FRAME RFSYNC RSYNC RSYNC 2 RSYNC NOTE 1 RSYNC IN THE FRAME MODE TR IOCRL5 0 AND DOUBLE MDE FRAME SYNC IS NOT ENABLED TR IOCR1 6 0 NOTE 2 RSYNC IN THE FRAME MODE TR IOCRL5 0 AND DOUBLE WMDE FRAME S
305. l customer installation is the same for both ESF and D4 operation Setting the TAIS CI bit in the TR T1TCCR1 register and the TBL bit in the TR T1TCR1 register causes the device to transmit the AIS CI code The RAIS CI status bit in the TR SR4 register indicates the reception of AIS CI signal The RAI CI remote alarm indication customer installation code for T1 ESF operation is a special form of the ESF Yellow Alarm an unscheduled message Setting the RAIS CI bit in the TR T1CCR1 register causes the device to transmit the RAI CI code The RAI CI code causes a standard Yellow Alarm to be detected by the receiver When the host processor detects a Yellow Alarm it can then test the alarm for the RAI CI state by checking the BOC detector for the RAI CI flag That flag is a 011111 code in the 6 bit BOC message The RAI CI code for T1 D4 operation is a 10001011 flag in all 24 time slots To transmit the RAI CI code the host sets all 24 channels to idle with a 10001011 idle code Since this code meets the requirements for a standard T1 D4 Yellow Alarm the host can use the receive channel monitor function to detect the 100001011 code whenever a standard Yellow Alarm is detected 74 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 4 3 T1 Receive Side Digital Milliwatt Code Generation Receive side digital milliwatt code generation involves using the receive digital milliwatt registers TR T1RDMR1 2 3 to determine whic
306. l receive channels 1 1 Updates all transmit and receive channels Bits 0 5 Channel Pointer Address Bits IAAO to IAA5 These bits select the channel to be programmed with the idle code defined the TR PCICR register IAAO is the LSB of the 5 bit channel code Channel 1 is 01h Register Name TR PCICR Register Description Per Channel Idle Code Register Register Address 7Fh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 CO Default a Bits 0 7 Per Channel Idle Code Bits CO to C7 This register defines the idle code to be programmed in the channel selected by the TR IAAR register CO is the LSB of the idle code this bit is transmitted last Register Name TR TCICE1 Register Description Transmit Channel Idle Code Enable Register 1 Register Address 80h Bit 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Defaut 0o 0 0 0 o 0 0 0 Bits 0 7 Transmit Channels 1 to 8 Code Insertion Control Bits CH1 to CH8 0 do not insert data from the idle code array into the transmit data stream 1 insert data from the idle code array into the transmit data stream 260 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TCICE2 Register Description Transmit Channel Idle Code Enable Register 2 Register Address 81h Bit 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 D aut 0 0
307. le repetitive pattern The repetitive pattern length and pattern are programmable length n 1 to 32 and pattern 0 to 2 1 e 24 bit error count and 32 bit bit count registers e Programmable bit error insertion Errors can be inserted individually 62 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 16 1 Receive Data Interface 9 16 1 1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern The receive pattern generator is a 32 bit shift register that shifts data from the least significant bit LSB or bit 1 to the most significant bit MSB or bit 32 The input to bit 1 is the feedback For a PRBS pattern generating polynomial x x 1 the feedback is an XOR of bit n and bit y For a repetitive pattern length n the feedback is bit n The values for n and y are individually programmable 1 to 32 The output of the receive pattern generator is the feedback If QRSS is enabled the feedback is an XOR of bits 17 and 20 and the output is forced to one if the next 14 bits are all zeros QRSS is programmable on or off For PRBS and QRSS patterns the feedback is forced to one if bits 1 through 31 are all zeros Depending on the type of pattern programmed pattern detection performs either PRBS synchronization or repetitive pattern synchronization 9 16 1 2 PRBS Synchronization PRBS synchronization synchronizes
308. led 1 0 Internal transmit side 100Q enabled 1 1 Internal transmit side 120Q enabled Bits 0 1 Receive Termination Select RT1 RT1 RTO Internal Receive Termination Configuration 0 0 Internal receive side termination disabled 0 1 Internal receive side 750 enabled 1 0 Internal receive side 100Q enabled 1 1 Internal receive side 120Q enabled 259 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IAAR Register Description Idle Array Address Register Register Address 7Eh Bit 7 6 5 4 3 a5 1 0 Name GRIC GTIC 5 4 IAA1 IAAO Default i Bit 7 Global Receive Idle Code GRIC Setting this bit causes all receive channels to be set to the idle code written to the TR PCICR register This bit must be set 0 for read operations The value in bits IAAO IAA5 must be a valid transmit channel 01h to 20h for E1 mode 01h to 18h for T1 mode Bit 6 Global Transmit Idle Code Setting this bit causes all transmit channels to be set to the idle code written to the PCICR register This bit must be set 0 for read operations The value in bits IAAO IAA5 must be a valid transmit channel 01h to 20h for E1 mode 01h to 18h for T1 mode GRIC GTIC FUNCTION 0 0 Updates a single transmit or receive channel 0 1 Updates all transmit channels 1 0 Updates al
309. lid message Consecutive BOC Codes for REEI REFA Valid Sequence Identification Oo 0 E OM NINE Bit 0 Send BOC SBOC Set 1 to transmit the BOC code placed in bits 0 to 5 of the TR TFDL register 236 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RSINFO1 TR RSINFO2 TR RSINFO3 TR RSINFO4 Register Description Receive Signaling Change of State Information Register Address 38h 39h 3Ah 3Bh MB J 059 RSINFO1 RSINFO2 RSINFO3 0 29 CH28 CH27 CH26 25_ RSINFO4 When a channel s signaling data changes state the respective bit in registers TR RSINFO 1 4 is set An interrupt is generated if the channel was also enabled as an interrupt source by setting the appropriate bit in TR RSCSE1 4 The bit remains set until read Register Name TR RSCSE1 TR RSCSE2 TR RSCSE3 TR RSCSE4 Register Description Receive Signaling Change of State Interrupt Enable Register Address 3Ch 3Dh 3Eh 3Fh MsB RSCSE1 RSCSE2 RSCSE3 0 8 CH27 CH26 CH25 RSCSE4 Setting any of the CH1 CH30 bits in the TR RSCSE1 TR RSCSE4 registers causes an interrupt when that channel s signaling data changes state 237 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SIGCR Register Description Signaling Control Register Re
310. lision occurred on the received packet A late collision is one that occurs after the 64 byte collision window Bit 0 Frame Too Long FTL This bit is set to 1 if a frame exceeds the 1518 byte maximum standard Ethernet frame This bit is only an indication and causes no frame truncation 181 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU RFSB3 Receive Frame Status Byte 3 Register Name Register Description Register Address 157h Bit 7 5 4 3 2 1 0 Name MF BF MCF UF CF LE Default 0 0 0 0 0 0 0 Bit 7 Missed Frame MF This bit is set to 1 if the packet is not successfully received from the MAC by the packet Arbiter Bit 4 Broadcast Frame BF This bit is set to 1 if the current frame is a broadcast frame Bit 3 Multicast Frame MCF This bit is set to 1 if the current frame is a multicast frame Bit 2 Unsupported Control Frame UF This bit is set to 1 if the frame received is a control frame with an opcode that is not supported If the Control Frame bit is set and the Unsupported Control Frame bit is clear then a pause frame has been received and the transmitter is paused Bit 1 Control Frame CF This bit is set to 1 when the current frame is a control frame This bit is only valid in full duplex mode Bit 0 Length Error LE This bit is set to 1 when the frames length field and the actual byte count are unequal This bit is only valid for 802 3 frames
311. ll duplex modes Flow control for both half duplex back pressure and full duplex PAUSE modes Programmable Maximum MAC frame size up to 2016 bytes Minimum MAC frame size 64 bytes Discards frames greater than programmed maximum MAC frame size and runt nonoctet bounded or bad FCS frames upon reception Configurable for promiscuous broadcast discard mode Programmable threshold for SDRAM queues to initiate flow control and status indication MAC loopback support for transmit data looped to receive data at the MII RMII interface 12 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 2 9 T1 E1 J1 Line Interface Requires only a 2 048 2 master clock for both E1 and T1 operation with the option to use 1 544MHz for T1 operation Fully software configurable Short haul and long haul applications Automatic receive sensitivity adjustments Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1 applications Receive level indication in 2 5dB steps from 42 5dB to 2 5dB Internal receive termination option for 75O 1000 and 1200 lines Internal transmit termination option for 75 1000 and 1200 lines Monitor application gain settings of 20dB 26dB and 32dB G 703 receive synchronization signal mode Flexible transmit waveform generation T1 DSX 1 line build outs T1 CSU line build outs of 7 5dB 15dB and 22 5dB E1 waveforms include G 703 waveshapes for both 75Q coax and 1200 tw
312. lock Source Select Bit 0 TCSS1 TCSS1 TCSSO Transmit Clock Source 0 0 The TCLKT pin is always the source of transmit clock 0 4 Switch to the clock present at RCLKO when the signal at the TCLKT pin fails to transition after 1 channel time Use the scaled signal present at MCLK as the transmit clock The 1 i TCLKT pin is ignored Use the signal present at RCLKO as the transmit clock The TCLKT pin 1 1 is ignored Bit 1 Transmit Clock Source Select Bit 0 550 Bit 0 Function of the RLOS LOTC Output RLOSF 0 7 receive loss of sync RLOS 1 7 loss of transmit clock LOTC 251 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR CCR2 Register Description Common Control Register 2 Register Address 71h Bit 7 6 5 4 3 2 1 0 Name BPCS1 BPCSO BPEN Defaut 9 o o o o 9 o Bits 1 2 Backplane Clock Selects 50 BPCS1 BPCS1 BPCSO BPCLK Frequency MHz 0 0 16 384 0 1 8 192 1 0 4 096 1 1 2 048 Bit 0 Backplane Clock Enable BPEN 0 7 disable BPCLK pin pin held at logic O 1 enable BPCLK Register Name TR CCR3 Register Description Common Control Register 3 Register Address 72h Bit 7 6 5 4 3 2 1 0 Name TMSS INTDIS TDATFMT TGPCKEN RDATFMT RGPCKEN Defaut 0 o 0 0 Bit 7 Transmit Multiframe Sync Source TMSS Should be set 0 only when transmit hardware
313. lock facility RDEN p RBSYNC Receive Byte Synchronization Input Provides byte synchronization input to X 86 decoder This signal will go high at the last bit of the byte as it arrives This signal can occur at maximum rate every 8 bits Note that a long as the R11 receives one RBSYNC indicator The X 86 receiver will determine the byte boundary Hence the R11 does not require a continuous 8 bit sync indicator A new sync pulse is required if the byte boundary changes T1 E1 J1 FRAMER LIU INTERIM SIGNALS Receive Clock Input to the T1 E1 J1 Framer Clock used to clock RDCLKI M4 data through the receive side framer This pin is normally connected to RDCLKO Can be internally connected to RDCLKO by connecting the LIUC pin high Receive Clock Output from the T1 E1 J1 LIU Buffered RDCLKO M3 recovered clock from the network This pin is normally connected to RDCLKI Receive Negative Data Input Sampled on the falling edge of RDCLKI for data to be clocked through the receive side framer RNEGI L4 RPOSI RNEGI be connected together for NRZ interface Can be internally connected to RNEGO by connecting the LIUC pin high Receive Negative Data Output from the T1 E1 J1 LIU Updated RNEGO N2 on the rising edge of RDCLKO with the bipolar data out of the line interface This pin is normally tied to RNEGI Receive Positive Data Input to the T1 E1 J1 Framer Sampled on the falling edge of RDCLKI for da
314. lock source can be used Backplane Clock from T1 E1 J1 Transceiver A user selectable BPCLK B1 synthesized clock output that is referenced to the clock that is output at the RCLKO pin Eight Times Clock from the T1 E1 J1 Transceiver An 8x clock that is locked to the recovered network clock provided from the 8XCLK K4 clock data recovery block if the jitter attenuator is enabled on the receive side or from the TDCLKI pin if the jitter attenuator is enabled on the transmit side Quartz Crystal Driver for the T1 E1 J1 Transceiver A quartz XTALD crystal of 2 048MHz optional 1 544MHz in T1 only operation be applied across MCLK and XTALD instead of a clock source at Leave open circuited if a clock source is applied at MCLK 37 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION JTAG INTERFACE JTAG Clock 1 for the Ethernet Mapper This signal is used to JTCLK1 AT Ipu shift data into JTDI1 on the rising edge and out of JTDO1 on the falling edge JTAG Data In 1 for the Ethernet Mapper Test instructions and JTDI1 C9 Ipu data are clocked into this pin on the rising edge of JTCLK1 This has a 10 pullup resistor JTAG Data Out 1 for the Ethernet Mapper Test instructions and JTDO1 B7 Oz data are clocked out of this pin on the falling edge of JTCLK1 If not used this pin should be left unconnected JTA
315. low condition may be included in this count 170 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver LI RHPMUU Serial Interface Receive HDLC PMU Update Register Register Name Register Description Register Address 120h Bit 7 6 5 4 3 2 1 0 Name RPMUU Default 0 0 0 0 0 0 0 0 Bit 0 Receive PMU Update RPMUU This signal causes the receive cell packet processor block performance monitoring registers counters to be updated A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data and the counters reset 0 or 1 This update updates performance monitoring counters for the Serial Interface LI RHPMUS Serial Interface Receive HDLC PMU Update Status Register Register Name Register Description Register Address 121h Bit 7 6 5 4 3 2 1 0 Name RPMUUS Default 0 0 0 0 0 0 0 0 Bit 0 Receive PMU Update Status RPMUUS This bit is set when the Transmit PMU Update is completed This bit is cleared when RPMUU is set to 0 Register Name LI RX86S Register Description Receive X 86 Latched Status Register Register Address Bit 7 6 4 3 2 1 0 Name SAPIHNE SAPILNE CNE ANE Default Bit 3 SAPI High is not equal to LI TRX86SAPIH Latched Status SAPIHNE This latched status bit is set if SAPIH is n
316. mat conversions from D4 to ESF This function is not available when the receive side elastic store is enabled RSYNC must be set to output multiframe pulses TR IOCR1 5 1 and TR IOCR1 4 0 0 RSYNC outputs a pulse at every multiframe 1 RSYNC outputs a pulse at every other multiframe Bit 6 RSYNC Mode Select 2 RSMS2 T1 Mode RSYNC pin must be programmed the output frame mode TR IOCR1 5 0 TR IOCR1 4 0 0 7 do not pulse double wide in signaling frames 1 do pulse double wide in signaling frames E1 Mode RSYNC pin must be programmed in the output multiframe mode TR IOCR1 5 1 TR IOCR1 4 0 0 RSYNC outputs CAS multiframe boundaries 1 RSYNC outputs CRC4 multiframe boundaries Bit 5 RSYNC Mode Select 1 RSMS1 Selects frame or multiframe pulse when RSYNC pin is in output mode In input mode elastic store must be enabled multiframe mode is only useful when receive signaling reinsertion is enabled See the timing diagrams in Section 12 0 frame mode 1 multiframe mode Bit 4 RSYNC I O Select RSIO Note This bit must be set to 0 when TR ESCR O 0 0 RSYNC is an output 1 RSYNC is an input only valid if elastic store enabled Bit 3 TSYNC Double Wide TSDW Note This bit must be set to 0 when TR IOCR1 2 1 or when TR IOCR1 1 0 0 do not pulse double wide in signaling frames 1 do pulse double wide in signaling frames Bit 2 TSYNC Mode Select TSM Selects frame or multiframe mode for the TSYNC
317. matches TR RFDLM1 or TR RFDLM2 Bit 0 Receive BOC Detector Change of State Event RBOC Set whenever the BOC detector sees a change of state to a valid BOC The setting of this bit prompts the user to read the TR RFDL register Register Name TR IMR8 Register Description Interrupt Mask Register 8 Register Address 25h Bit 7 6 5 4 3 2 1 0 Name BOCC RFDLAD RFDLF TFDLE RMTCH RBOC 9 o 9 o 9 9 9 9 Bit 5 BOC Clear Event BOCC 0 interrupt masked 1 interrupt enabled Bit 4 RFDL Abort Detect Event RFDLAD 0 interrupt masked 1 interrupt enabled Bit 3 RFDL Register Full Event RFDLF 0 interrupt masked 1 interrupt enabled Bit 2 TFDL Register Empty Event TFDLE 0 interrupt masked 1 interrupt enabled Bit 1 Receive FDL Match Event RMTCH 0 interrupt masked 1 interrupt enabled Bit 0 Receive BOC Detector Change of State Event RBOC 0 interrupt masked 1 interrupt enabled 228 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR SR9 Register Description Status Register 9 Register Address 26h Bit 7 6 5 4 3 2 1 0 Name BBED BBCO BECO BRA1 BRAO BRLOS BSYNC Defaut 9 0 0 9 9 o o o Bit 6 BERT Bit Error Detected BED Event BBED A latched bit that is set when a bit error is detected The receive BERT must be in synchronization for it to detect bit errors Cleared when read Bit 5 BERT Bit Counte
318. me Register Description Register Address 0CAh Bit 7 6 5 4 3 2 1 0 Name TEPFIE Default 0 0 0 0 0 0 0 0 Bit 0 Transmit Errored Packet Insertion Finished Interrupt Enable TEPFIE This bit enables an interrupt if the TEPFL bit in the LI TPPSRL register is set 0 interrupt disabled 1 interrupt enabled 155 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI TPCRO Register Description Transmit Packet Count Byte 0 Register Address 0 Bit 7 6 5 4 3 2 1 0 Name 7 TPC6 TPC5 TPC4 2 1 TPCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Packet Count TPC 7 0 Eight bits of 24 bit value Register description below Register Name LI TPCR1 Register Description Transmit Packet Count Byte 1 Register Address 0CDh Bit 7 6 5 4 3 2 1 0 Name TPC15 TPC14 TPC13 12 11 10 9 TPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Packet Count TPC 15 8 Eight bits of 24 bit value Register description below Register Name LI TPCR2 Register Description Transmit Packet Count Byte 2 Register Address Bit 7 6 5 4 3 2 1 0 Name TPC23 TPC22 TPC21 TPC20 TPC19 TPC18 TPC17 TPC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Packet Count TPC 23 16 These twenty four bi
319. microprocessor interface 7 16 Address Bit 7 Address bit 7 of the microprocessor interface A8 C16 Address Bit 8 Address bit 8 of the microprocessor interface A9 C15 Address Bit 9 Address bit 9 of the microprocessor interface DO MA 107 Data Bit 0 Bidirectional data bit 0 of the microprocessor interface Least Significant Bit Not driven when CS 1 or RST 0 04 B14 02 Data Bit 1 Bidirectional data bit 1 of the microprocessor interface Not driven when CS 1 or RST 0 Data Bit 2 Bidirectional data bit 2 of the microprocessor interface Ex 944 Not driven when CS 1 or RST 0 Data Bit 3 Bidirectional data bit 3 of the microprocessor interface Be pes In Not driven when CS 1 or RST 0 Data Bit 4 Bidirectional data bit 4 of the microprocessor interface 4 loz Not driven when CS 1 or RST 0 Data Bit 5 Bidirectional data bit 5 of the microprocessor interface pa 548 E Not driven when CS 1 or RST 0 Data Bit 6 Bidirectional data bit 6 of the microprocessor interface po diia mE Not driven when CS 1 or RST 0 D7 B12 02 Data Bit 7 Bidirectional data bit 7 of the microprocessor interface Most Significant Bit Not driven when CS 1 or RST 0 Write Intel Mode The DS33R11 captures the contents of the data bus 20 07 on the rising edge of WR and writes them to the addressed register location CS must be held low during write WR RW C11 operations Read Write Motorola Mode Used to indicate read or
320. mit Channels 17 to 24 Channel Blocking Control Bits 17 to CH24 0 force the TCHBLK pin to remain low during this channel time 1 force the TCHBLK pin high during this channel time Register Name TR TCBR4 Register Description Transmit Channel Blocking Register 4 Register Address 8Fh Bit 7 6 5 4 3 2 1 0 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 Defaut 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Channels 25 to 32 Channel Blocking Control Bits CH25 to CH32 0 force the TCHBLK pin to remain low during this channel time 1 force the TCHBLK pin high during this channel time 264 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1TC TR H2TC Register Description HDLC 1 Transmit Control HDLC 2 Transmit Control Register Address 90h AOh Bit 7 6 5 4 3 2 1 0 Name NOFS TEOML THR THMS TFS TEOM TZSD TCRCD Default 0 Bit 7 Number of Flags Select NOFS 0 send one flag between consecutive messages 1 send two flags between consecutive messages Bit 6 Transmit End of Message and Loop TEOML To loop on a message this bit should be set to a 1 just before the last data byte of an HDLC packet is written into the transmit FIFO The message repeats until the user clears this bit or a new message is written to the transmit FIFO If the host clears the bit the looping message completes then flags are transmitted until a new message is written to the FIFO If the
321. miter is disabled TCLE indicates that a short circuit condition exists Status Register TR SR1 2 provides a latched version of the information which can be used to activate an interrupt when enabled by the TR IMR1 register The TPD bit TR LIC1 0 powers down the transmit line driver and three states the TTIP and TRING pins 10 20 3 2 Transmit Open Circuit Detector The device can also detect when the TTIP or TRING outputs are open circuited TOCD TR INFO2 4 provides a real time indication of when an open circuit is detected TR SR1 provides a latched version of the information TR SR1 1 which be used to activate an interrupt when enabled by the TR IMR1 register 10 20 3 3 Transmit BPV Error Insertion When IBPV TR LIC2 5 is transitioned from a 0 to a 1 the device waits for the next occurrence of three consecutive 1s to insert a BPV IBPV must be cleared and set again for another BPV error insertion 10 20 3 4 Transmit G 703 Synchronization Signal E1 Mode The transceiver can transmit the 2 048MHz square wave synchronization clock as specified in Section 13 of ITU G 703 October 1998 In order to transmit the 2 048MHz clock when in E1 mode set the transmit synchronization clock enable TR LIC3 1 1 102 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 21 MCLK Prescaler A 16 384MHz 8 192MHz 4 096MHz 2 048MHz or 1 544MHz clock must be applied at MCLK ITU specification G 703 requires an accu
322. mode from the REF input In MII mode with DTE operation the TX CLK and RX CLK signals are generated by the PHY and are inputs to the DS33R11 For more information on clocking the Ethernet Interface see Section 9 1 The data received from the MII or RMII interface is processed by the internal IEEE 802 3 compliant Ethernet MAC The user can select the maximum frame size up to 2016 bytes that is received with the SU RMFSRH and SU RMFSRL registers The maximum frame length in bits is the number specified in SU RMFSRH and SU RMFSRL multiplied by 8 Any programmed value greater than 2016 bytes will result in unpredictable behavior and should be avoided The maximum frame size is shown in Figure 9 4 The length includes only destination address source address VLAN tag 2 bytes type length field data and CRC32 The frame size is different than the 802 3 type length field Frames from the Ethernet PHY or received from the packet processor are rejected if greater than the maximum frame size specified Each Ethernet frame sent or received generates status bits SU TFSH and SU TFSL and SU RFSBO to SU RFSB3 These are real time status registers and will change as each frame is sent or received Hence they are useful to the user only when one frame is sent or received and the status is associated with the frame sent or received Figure 9 4 IEEE 802 3 Ethernet Frame Preamble SFD Destination Adrs Source Address
323. n equal to zero broadcast frames are rejected 185 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 6 2 MAC Registers The control Registers related to the control of the individual Mac s are shown in the following Table The DS33R11 keeps statistics for the packet traffic sent and received The register address map is shown in the following Table Note that the addresses listed are the indirect addresses that must be provided to SU MACRADH SU MACRADL or SU MACAWH SU MACAWL SU MACCR MAC Control Register Register Name Register Description Register Address 0000h indirect 0000h Bit 4 31 30 29 28 27 26 25 24 Name Reserved Reserved Reserved HDB PS Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0001h Bit 23 22 21 20 19 18 17 16 Name DRO Reserved OMLO F PM PAM Reserved Reserved Default 0 0 0 0 0 0 0 0 0002h Bit 4 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved LCC Reserved DRTY Reserved ASTP Default 0 0 0 0 0 0 0 0 0003h Bit 07 06 05 04 03 02 01 00 Name BOLMT1 BOLMTO DC Reserved TE RE Reserved Reserved Default 0 0 0 0 0 0 0 0 Bit 28 Heartbeat Disable When set to 1 the heartbeat SQE function is disabled This bit should be set to 1 when operating in mode Bit 27 Port Select PS This bit should be equal to 0 for proper o
324. n these bits are set to 1 data from the corresponding receive channel replaces the data on TSERI for that channel 77 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 7 Error Counters The transceiver contains four counters that are used to accumulate line coding errors path errors and synchronization errors Counter update options include one second boundaries 42ms T1 mode only 62ms E1 mode only or manual See Error Counter Configuration Register TR ERCNT When updated automatically the user can use the interrupt from the timer to determine when to read these registers four counters saturate at their respective maximum counts and they do not roll over Note Only the line code violation count register has the potential to overflow but the bit error would have to exceed 10E 2 before this would occur 10 7 1 Line Code Violation Counter TR LCVCR In T1 mode code violations are defined as bipolar violations BPVs or excessive Os If the B8ZS mode is set for the receive side then B8ZS codewords are not counted This counter is always enabled it is not disabled during receive loss of synchronization RLOS 1 conditions Table 10 5 shows what the LCVCRs count Table 10 5 T1 Line Code Violation Counting Options COUNT EXCESSIVE ZEROS COUNTED IN THE LCVCRs TR ERCNT 0 i BPVs 16 consecutive 0s BPVs B8ZS codewords not counted BPVs 8 consecutive 05 In E1 mode eit
325. nable TAIS CI Setting this bit and the TBL bit TR TTTCR1 1 causes the AIS CI code to be transmitted at TPOSO and TNEGO as defined in ANSI T1 403 0 do not transmit the AIS CI code 1 transmit the AIS CI code TR TTTCR1 1 must also be set 1 Bit 2 Transmit Frame Mode Select TFM 0 D4 framing mode 1 ESF framing mode Bit 1 Pulse Density Enforcer Enable PDE The framer always examines the transmit and receive data streams for violations of these which are required by ANSI T1 403 No more than 15 consecutive Os and at least N 1s in each and every time window of 8 x N 1 bits where N 1 through 23 Violations for the transmit and receive data streams are reported in the TR INFO1 6 and TR INFO1 7 bits respectively When this bit is set to 1 the T1 E1 J1 transceiver forces the transmitted stream to meet this requirement no matter the content of the transmitted stream When running B8ZS this bit should be set to 0 since B8ZS encoded data streams cannot violate the pulse density requirements 0 7 disable transmit pulse density enforcer 1 enable transmit pulse density enforcer Bit 0 Transmit Loop Code Enable TLOOP See Section 10 19 for details 0 transmit data normally 1 replace normal transmitted data with repeating code as defined in registers TR TCD1 and TR TCD2 Register Name Register Description TR SSIE1 T1 Mode Software Signaling Insertion Enable 1 Register Address 08h Bit 7 6 5 4 3 2 1 0
326. nal 32 768MHz E1 or 24 704MHz T1 clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing When the device divides by either 15 or 17 it also sets the jitter attenuator limit trip JALT bit in Status Register 1 TR SR1 4 10 23 CMI Code Mark Inversion Option The device provides a CMI interface for connection to optical transports This interface is a unipolar 1T2B signal type Ones are encoded as either a logical 1 or O level for the full duration of the clock period Zeros are encoded as a 0 to 1 transition at the middle of the clock period Figure 10 6 CMI Coding Transmit and receive CMI are enabled through TR LIC4 7 When this register bit is set the TTIP pin outputs CMI coded data at normal levels This signal can be used to directly drive an optical interface When CMI is enabled the user can also use HDB3 B8ZS coding When this register bit is set the RTIP pin becomes a unipolar CMI input The CMI signal is processed to extract and align the clock with data 103 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 24 Recommended Circuits Figure 10 7 Basic Interface VDD DS33R11 O 1uF 0 01pF DVDD e e e TRANSMIT LINE DVSS e O 4gF 10yF TVDD TVSS e 0 1 10uF RECEIVE LINE SIC RVDD ae RVSS e e 0 1 NOTE 1 ALL RESISTOR VALUES ARE 1 NOTE 2 RESISTORS SHOULD
327. nel Bit 7 Suppress Enable RCB7SE Set to 1 to stop this bit from being used Bit 5 Receive Channel Bit 6 Suppress Enable RCB6SE Set to 1 to stop this bit from being used Bit 4 Receive Channel Bit 5 Suppress Enable Sa4 Bit Enable RCB5SE Set to 1 to stop this bit from being used Bit 3 Receive Channel Bit 4 Suppress Enable Sa5 Bit Enable RCBASE Set to 1 to stop this bit from being used Bit 2 Receive Channel Bit 3 Suppress Enable Sa6 Bit Enable RCB3SE Set to 1 to stop this bit from being used Bit 1 Receive Channel Bit 2 Suppress Enable Sa7 Bit Enable RCB2SE Set to 1 to stop this bit from being used Bit 0 Receive Channel Bit 1 Suppress Enable Sa8 Bit Enable RCB1SE LSB of the channel Set to 1 to stop this bit from being used 268 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1TCS1 TR H1TCS2 TR H1TCS3 TR H1TCS4 TR H2TCS1 TR H2TCS2 TR H2TCS3 TR H2TCS4 Register Description HDLC 1 Transmit Channel Select HDLC 2 Transmit Channel Select Register Address 97h 98h 99h 9Ah A8h A9h Bit 7 6 5 4 3 2 1 0 Name THCS7 THCS6 THCS5 THCS4 THCS3 THCS2 THCS1 THCSO Default 0 Bit 7 Transmit HDLC Channel Select Bit 7 THCS7 Select Channel 8 16 24 or 32 Bit 6 Transmit HDLC Channel Select Bit 6 THCS6 Select Channel 7 15 23 or 31 Bit 5 Transmit HDLC Channel Select Bit 5 THCS5 Select Channel 6 14 22 or
328. ng have been received at RPOSI and RNEGI Bit 3 Sixteen Zero Detect Event 16ZD Set when a string of at least 16 consecutive Os regardless of the length of the string have been received at RPOSI and RNEGI Bit 2 Severely Errored Framing Event SEFE Set when two out of six framing bits Ft or FPS are received in error Bit 1 B8ZS Codeword Detect Event B8ZS Set when a B8ZS codeword is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not by TR T1TCR2 7 Useful for automatically setting the line coding Bit 0 Frame Bit Error Event FBE Set when an Ft D4 or FPS ESF framing bit is received in error 212 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR INFO2 Register Description Information Register 2 Register Address 11h Bit 7 6 5 4 3 2 1 0 Name BSYNC BD TCLE TOCD RL3 RL2 RL1 RLO 1 0 0 ee Bit 7 BERT Real Time Synchronization Status BSYNC Real time status of the synchronizer this bit is not latched This bit is set when the incoming pattern matches for 32 consecutive bit positions It is cleared when six or more bits out of 64 are received in error Refer to BSYNC in the BERT status register TR SRS9 for an interrupt generating version of this signal Bit 6 BOC Detected BD A real time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is curr
329. ng Channel Select THSCS Bit 2 Payload Error Insert Channel Select PEICS Bit 1 Transmit Fractional Channel Select TFCS Bit 0 Bert Transmit Channel Select BTCS See Section 10 2 for a general overview of per channel operation See Section 10 10 for more information on per channel idle code generation See Section 10 6 for more information on per channel loopback operation 231 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR PCDR1 Register Description Per Channel Data Register 1 Register Address 29h Bit 7 6 5 4 3 2 1 0 Name Default CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Register Name TR PCDR2 Register Description Per Channel Data Register 2 Register Address 2Ah Bit 7 6 5 4 3 2 1 0 Name Default CH16 CH15 CH14 CH13 CH12 CH11 CH10 Register Name TR PCDR3 Register Description Per Channel Data Register 3 Register Address 2Bh Bit 7 6 5 4 3 2 1 0 Name Default CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Register Name TR PCDR4 Register Description Per Channel Data Register 4 Register Address 2Ch Bit 7 6 5 4 3 2 1 0 Name Default CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 See Section 10 2 for a general overview of per channel operation See Section 10 10 for more information on per channel idle code generation See Section 10 6 for more information on per channel loopback operation 232 of 344 DS33R11 Ethernet Mapper wi
330. ngle write to the TR PCICR register Bits 6 and 7 of the TR IAAR register should not be used for read operations TR TCICE1 4 and TR RCICE1 4 are used to enable idle code replacement on a per channel basis Table 10 10 Idle Code Array Address Mapping BITS 0 to 5 OF IAAR REGISTER MAPS TO CHANNEL 0 Transmit Channel 1 1 Transmit Channel 2 2 Transmit Channel 3 30 Transmit Channel 31 31 Transmit Channel 32 32 Receive Channel 1 33 Receive Channel 2 34 Receive Channel 3 62 Receive Channel 31 63 Receive Channel 32 86 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 10 1 Idle Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh Write TR IAAR 02h select channel 3 in the array Write TR PCICR 7Eh set idle code to 7Eh Example 2 Sets transmit channels 3 4 5 and 6 idle code to 7Eh and enables transmission of idle codes for those channels Write TR IAAR 02h select channel 3 in the array Write TR PCICR 7Eh set channel 3 idle code to 7Eh Write TR PCICR 7Eh set channel 4 idle code to 7Eh Write TR PCICR 7Eh set channel 5 idle code to 7Eh Write TR PCICR 7Eh set channel 6 idle code to 7Eh Write 3Ch enable transmission of idle codes for channels 3 4 5 and 6 Example 3 Sets transmit channels 3 4 5 and 6 idle code to 7Eh EEh FFh and 7Eh respectively Write TR IAAR 02h Write TR
331. nni 326 Motorola Bus Write Timing MODEL QJ naan iaai 326 TU T 328 Receive Side Timing Elastic Store Enabled 004 4 329 Receive Line Interlace eT TO S EEUU 330 Receive Timing Delay ROCLKO to BPCLK 331 MD S IU E LU T LI E ST 333 Transmit Side Timing Elastic Store Enabled ener 334 USNC Line Interlace LT 334 Interace Timing Diagram esris 335 JTAG Funotional Block aar oti ko Pid 336 PT 339 JAG Funetonal TIM dc 342 7 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver LIST OF TABLES Table 2 1 T1 Related Telecommunications Specifications 2 16 Table 7 1 Detailed Pin iecit en Fei Y RI ERG FON LH CREE REDE tease VR ER 25 Table 9 1 Clocking Options for the Ethernet Interface eese eet rtr rh Rr d IY PR edd EXE 43 Table 2 2 Reset FONCIONS M 46 Table 9 3 Registers Related to Connections and 0000 52 MMC
332. nter is comprised of TR BEC1 TR BEC2 and TR BEC3 Once BERT has achieved synchronization this 24 bit counter increments for each data bit received in error Toggling the LC control bit in TR BC1 can clear this counter This counter saturates when full and sets the BECO status bit 10 25 6 BERT Alternating Word Count Rate When the BERT is programmed in the alternating word mode each word repeats for the count loaded into TR BAWC One word should be placed into TR BRP1 and TR BRP2 and the other word should be placed into TR BRP3 TR BRP4 110 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 26 Payload Error Insertion Function T1 Mode Only An error insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path This function is only available in T1 mode Errors can be inserted over the entire frame or the user can select which channels are to be corrupted Errors are created by inverting the last bit in the count sequence For example if the error rate 1 in 16 is selected the 16th bit is inverted F bits are excluded from the count and are never corrupted Error rate changes occur on frame boundaries Error insertion options include continuous and absolute number with both options supporting selectable insertion rates Table 10 14 Transmit Error Insertion Setup Sequence STEP ACTION 1 Enter desired error rate in the TR ERC
333. ntil five seconds has elapsed to ensure the code is continuously present 99 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 20 Line Interface Unit LIU The LIU contains three sections the receiver that handles clock and data recovery the transmitter that waveshapes and drives the T1 line and the jitter attenuator These three sections are controlled by the line interface control registers LIC1 LIC4 which are described in the following sections The LIU has its own T1 E1 mode select bit and can operate independently of the framer function The transceiver can switch between T1 or E1 networks without changing external components on the transmit or receive side Figure 10 7 shows a network connection using minimal components In this configuration the transceiver can connect to T1 J1 or E1 750 or 1200 without component changes The receiver can adjust the 1200 termination to 1000 or 750 The transmitter can adjust its output impedance to provide high return loss characteristics for 1200 1000 and 750 lines Other components be added to this configuration to meet safety and network protection requirements Section 10 24 10 20 1 LIU Operation The analog AMI HDB3 waveform off the E1 line or the AMI B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the device The user has the option to use internal termination software selectable for 750 1000 1200 applications
334. of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 7 1 256 Ball BGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A RCHBLK TCHBLK RFSYNC TDATA TSSYNC JTCLK2 JTCLK1 RST NC INT cs D6 D3 vss 6 0 REF REIS BPCLK LIUC JrDP JTDO JTRST2 JTMS2 VDD1 8 RODS 07 04 Di voos A1 M TsYNC TNEGI JTDO2 vss WRRW VDD48 05 D2 9 5 A2 MDC MDIO D TDcLK TNEGO Teso CST vss vss vss DVDD DVDD DVDD vss vss voos TPOSO TSERO TSERI TSYSCLK pvpp vss ien TCLKE 1 8 RSYSCLK VDD3 T on TX EN G TCHCLK RCHCLK RCLKO RSYNC vop3 voos PCE H RSERI RSERO RDATA MCLK vop3 aovF TX CLK vss J Rvss RVSS RPOSI XTALD VDD3 vop1 8 vss VDD18 K RTP RVss VDD3 ERR RX DV vss L RVDD RVSS VDD3 io or Y M RRING Rvss RDCLKO RDCLKI VDD3 P I RS by N es pvss 003 coL vss vss P Tvss ReIGF 03 001 8 1 8 vss R
335. of interrupts on the device several features are available to help sort out and identify which event is causing an interrupt When an interrupt occurs the host should first read the TR IIR1 and TR IIR2 registers interrupt information registers to identify which status register or registers is producing the interrupt Once that is determined the individual status register or registers can be examined to determine the exact source Once an interrupt has occurred the interrupt handler routine should set the INTDIS bit TR CCR3 6 to stop further activity on the interrupt pin After all interrupts have been determined and processed the interrupt hander routine should re enable interrupts by setting the INTDIS bit 0 Note that the integrated Ethernet Mapper also generates interrupts as discussed in Section 9 6 73 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 4 T1 Framer Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control registers Typically the control registers are only accessed when the system is first powered up Once the transceiver has been initialized the control registers only need to be accessed when there is a change in the system configuration There are two receive control registers TR TTRCR1 and TR T1RCR2 two transmit control registers TR T1TCR1 and TR T1TCR2 a common control register TR T1CCR1 Each of these registers i
336. of the 16 bit E bit count Register Name TR EBCR2 Register Description E Bit Count Register 2 Register Address 49h Bit 7 6 5 4 3 2 1 0 Name EB6 EB5 EB4 EB3 EB2 EB1 EBO Default 0 0 0 0 0 0 0 0 Bits 0 7 E Bit Counter Bits 0 to 7 EBO to EB7 EBO is the LSB of the 16 bit E bit count 241 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR LBCR Register Description Loopback Control Register Register Address 4Ah Bit 7 6 5 4 3 2 1 0 Name LIUC LLB RLB PLB FLB Default 0 0 0 0 0 0 0 0 Bit 4 Line Interface Unit Mux Control LIUC This is a software version of the LIUC pin When the LIUC pin is connected high the LIUC bit has control When the LIUC pin is connected low the framer and LIU are separated and the LIUC bit has no effect 0 LIU internally connected to framer 1 LIU disconnected from framer Use TPOSI TNEGI TDCLKI RPOSI RNEGI RDCLKI pins LIUCPin LIUC Bit 0 0 LIU and framer separated 1 LIU and framer separated 9 LIU and framer connected LIU and framer separated Bit 3 Local Loopback LLB When this bit is set to 1 data continues to be transmitted as normal through the transmit side of the transceiver Data being received at RTIP and RRING are replaced with the data being transmitted Data in this loopback passes through the jitter attenuator See Figure 6 3 for more details Bit 2 Remote
337. oming FDL or the incoming Fs bits The LSB is received first Bit 7 Receive FDL Bit 7 RFDL7 MSB of the received FDL code Bit 6 Receive FDL Bit 6 RFDL6 Bit 5 Receive FDL Bit 5 RFDL5 Bit 4 Receive FDL Bit 4 RFDL4 Bit 3 Receive FDL Bit 3 RFDL3 Bit 2 Receive FDL Bit 2 RFDL2 Bit 1 Receive FDL Bit 1 RFDL1 Bit 0 Receive FDL Bit 0 RFDLO LSB of the received FDL code 278 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR TFDL Register Description Transmit FDL Register Register Address C1h Bit 7 6 5 4 3 2 1 0 Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDLO Default 0 Note Also used to insert Fs framing pattern D4 framing mode The transmit FDL register TR TFDL contains the FDL information that is to be inserted on a byte basis into the outgoing T1 data stream The LSB is transmitted first Bit 7 Transmit FDL Bit 7 TFDL7 MSB of the transmit FDL code Bit 6 Transmit FDL Bit 6 TFDL6 Bit 5 Transmit FDL Bit 5 TFDL5 Bit 4 Transmit FDL Bit 4 TFDL4 Bit 3 Transmit FDL Bit 3 TFDL3 Bit 2 Transmit FDL Bit 2 TFDL2 Bit 1 Transmit FDL Bit 1 TFDL1 Bit 0 Transmit FDL Bit 0 TFDLO L SB of the transmit FDL code Register Name TR RFDLM1 TR RFDLM2 Register Description Receive FDL Match Register 1 Receive FDL Match Register 2 Register Address C2h C3h Bit 4 7 6 5 4 3 2 1 0 Name RFDLM7 RFDLM6 RFDLM5 RFDLM4 RFDLM3 RFDLM2 R
338. on JTCLK with JTMS held low will put the controller in the Run Test Idle state With JTMS HIGH the controller will enter the Select DR Scan state 338 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 14 2 TAP Controller State Diagram Test Logic Reset y 0 1 Select Idle J DR Scan A yO _ 1 Capture DR ShiftDR Me Pause DR 0 0 2 c DR y 1 Update DR lt Update IR 1 0 1 0 K 4 14 2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length When the TAP controller enters the Shift IR state the instruction shift register is connected between JTDI and JTDO While in the Shift IR state a rising edge on JTCLK with LOW will shift the data one stage towards the serial output at JTDO A rising edge on JTCLK in the Exit1 IR state or the Exit2 IR state with JTMS HIGH will move the controller to the Update IR state The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output Instructions supported by the DS26521 and its respective operational binary codes are shown in Table 14 1 339 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 14 1 Instruction Codes for IEEE 1149 1 Architecture INSTRUCTION SELECTED REGISTER INSTR
339. on for both the framer and LIU 0 RCL declared upon 255 consecutive Os 125us 1 RCL declared upon 2048 consecutive Os 1ms 234 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR E1TCR1 Register Description E1 Transmit Control Register 1 Register Address 35h Bit 7 6 5 4 3 2 1 0 Name TFPT T16S 1 TSiS TSA1 THDB3 TG802 TCRC4 Default 0 0 0 0 0 0 0 0 Bit 7 Transmit Time Slot 0 Pass Through TFPT 0 FAS bits Sa bits remote alarm sourced internally from the TR TAF and TR TNAF registers 1 FAS bits Sa bits remote alarm sourced from TSERI Bit 6 Transmit Time Slot 16 Data Select T16S 0 time slot 16 determined by the TR SSIEx registers and the THSCS function in the TR PCPR register 1 7 source time slot 16 from TR TS1 to TR TS16 registers Bit 5 Transmit Unframed All Ones TUA1 0 transmit data normally 1 transmit an unframed all ones code at TPOSO and TNEGO Bit 4 Transmit International Bit Select TSiS 0 sample Si bits at TSERI pin 1 source Si bits from TR TAF and TR TNAF registers in this mode TR E1TCR1 7 must be set to 0 Bit 3 Transmit Signaling All Ones 5 1 0 normal operation 1 force time slot 16 in every frame to all ones Bit 2 Transmit HDB3 Enable THDB3 0 HDB3 disabled 1 HDB3 enabled Bit 1 Transmit G 802 Enable TG802 See Section 10 10 for details 0 do not force TCHBLK high during bit 1 of time slot 26 1 force TCHBLK
340. ot equal to LI TRX86SAPIH This latched status bit is cleared upon read Bit 2 SAPI Low is not equal to LI TRX86SAPIL Latched Status SAPILNE This latched status bit is set if SAPIL is not equal to LI TRX86SAPIL This latched status bit is cleared upon read Bit 1 Control is not equal to LI TRX8C This latched status bit is set if the control field is not equal to LI TRX8C This latched status bit is cleared upon read Bit 0 Address is not equal to LI TRX86A ANE This latched status bit is set if the X 86 Address field is not equal to LI TRX86A This latched status bit is cleared upon read 171 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RX86LSIE Register Description Receive X 86 Interrupt Enable Register Address 123h Bit 7 6 5 4 3 2 1 0 Name SAPINEO1IM SAPINEFEIM CNE3LI ANE4IM M Default 0 0 0 0 0 0 0 0 Bit 3 SAPI Octet not equal to LI TRX86SAPIH Interrupt Enable SAPINEO1IM If this bit is set to 1 LI RX86S SAPIHNE will generate an interrupt Bit 2 SAPI Octet not equal to LI TRX86SAPIL Interrupt Enable SAPINEFEIM If this bit is set to 1 LI RX86S SAPILNE will generate an interrupt Bit 1 Control not equal to LI TRX8C Interrupt Enable CNE3LIM If this bit is set to 1 LI RX86S CNE will generate an interrupt Bit 0 Address not equal to LI TRX86A Interrupt Enable ANEAIM If this bit is set to 1 LI RX86S ANE will
341. ould monitor the LI TPPSR TEPF bit for completion of the error insertion If interrupt on completion of error insertion is enabled LI TPPSRIE TEPFIE 1 the user only needs to wait for the interrupt condition 4 Proceed with the cleanup routine listed below Cleanup routine 1 Write LI TEPLC and LI TEPHC each to 00h 2 Write the LI TPPCL TIAEI bit to 0 154 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver LI TPPSR Transmit Packet Processor Status Register Register Name Register Description Register Address 0C8h Bit 7 6 5 4 3 2 1 0 Name 2 TEPF Default 0 0 0 0 0 0 0 0 Bit 0 Transmit Errored Packet Insertion Finished TEPF This bit is set when the number of errored packets indicated by the TPEN 7 0 bits in the TEPC register have been transmitted This bit is cleared when errored packet insertion is disabled or a new errored packet insertion process is initiated LI TPPSRL Transmit Packet Processor Status Register Latched Register Name Register Description Register Address 0C9h Bit 7 6 5 4 3 2 1 0 Name Default 2 Bit 0 Transmit Errored Packet Insertion Finished Latched TEPFL This bit is set when the TEPF bit in the TPPSR register transitions from zero to one LI TPPSRIE Transmit Packet Processor Status Register Interrupt Enable Register Na
342. ovide a pulse on frame multiframe boundaries If signaling reinsertion is enabled signaling data in TS16 is realigned to the multiframe sync input on RSYNC Otherwise a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store The framer always indicates frame boundaries on the network side of the elastic store by the RFSYNC output whether the elastic store is enabled or not Multiframe boundaries are always indicated by the RMSYNC output If the elastic store is enabled then RMSYNC outputs the multiframe boundary on the backplane side of the elastic store 10 12 1 1 T1 Mode If the user selects to apply 2 048MHz clock to the RSYSCLK pin then the data output at RSERO is forced to all 1s every fourth channel and the F bit is passed into the MSB of TSO Hence channels 1 bits 1 7 5 9 13 17 21 25 and 29 time slots O bits 1 7 4 8 12 16 20 24 and 28 are forced to a 1 Also in 2 048MHz applications the RCHBLK output is forced high during the same channels as the RSERO pin This is useful in T1 to E1 conversion applications If the two frame elastic buffer either fills or empties a controlled slip occurs If the buffer empties then a full frame of data is repeated at RSERO and the TR SR5 0 and TR SR5 1 bits are set to a 1 If the buffer fills then a full frame of data is deleted and the TR SR5 0 and TR SR5 2 bits are set to a 1 10 12 1 2E1 Mode If the elastic store is enabled then either
343. peration Bit 23 Disable Receive Own DRO When set to 1 the MAC disables the reception of frames while TX EN is asserted When this bit equals zero transmitted frames are also received by the MAC This bit should be cleared when operating in full duplex mode Bit 21 Loopback Operating Mode OMLO When set to 1 data is looped from the transmit side back to the receive side without being transmitted to the PHY Bit 20 Full Duplex Mode Select F When set to 1 the MAC transmits and receives data simultaneously When in full duplex mode the heartbeat check is disabled and the heartbeat fail status should be ignored Bit 19 Promiscuous Mode PM When set to 1 the MAC is in Promiscuous Mode and forwards all frames Note that the default value is 1 Bit 18 Pass All Multicast PAM When set to 1 the MAC forwards Multicast Frames 186 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Bit 12 Late Collision Control LCC When set to 1 enables retransmission of a collided packet even after the collision period When this bit is clear retransmission of late collisions is disabled Bit 10 Disable Retry DRTY When set to 1 the MAC makes only a single attempt to transmit each frame If a collision occurs the MAC ignores the current frame and proceeds to the next frame When this bit equals 0 the MAC will retry collided packets 16 times before signaling a retry error Bit 8 Automatic Pad Stripping
344. pins are used to indicate read and write operations and latch data through the interface With Motorola timing selected the Read Write RW pin is used to indicate read and write operations while the Data Strobe DS pin is used to latch data through the interface The interrupt output pin INT is an open drain output that will assert a logic low level upon a number of software maskable interrupt conditions This pin is normally connected to the microprocessor interrupt input The register map is shown in Table 11 1 8 1 1 Read Write Data Strobe Modes The processor interface can operate in either read write strobe mode or data strobe mode When MODEC 1 0 00 the read write strobe mode is enabled and a negative pulse on RD performs a read cycle and a negative pulse on WR performs a write cycle When MODEC 1 0 pins 01 the data strobe mode is enabled and a negative pulse on DS when RW is high performs a read cycle and a negative pulse on DS when RW is low performs a write cycle The read write strobe mode is commonly called the Intel mode and the data strobe mode is commonly called the Motorola mode 8 1 2 Clear on Read The latched status registers will clear on a read access It is important to note that in a multi task software environment the user should handle all status conditions of each register at the same time to avoid inadvertently clearing status conditions The latched status register bits are carefully designed so that an
345. pper with Integrated T1 E1 J1 Transceiver Register Name LI TIFGC Register Description Transmit Inter Frame Gapping Control Register Register Address 0C5h Bit 7 6 5 4 3 2 1 0 Name TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFGO Default 0 0 0 0 0 0 0 1 Bits 0 7 Transmit Inter Frame Gapping TIFG 7 0 These eight bits indicate the number of additional flags and bytes of inter frame fill to be inserted between packets The number of flags and bytes of inter frame fill between packets is at least the value of TIFG 7 0 plus 1 Note If inter frame fill is set to all 1 s a TFIG value of 2 or 3 will result in a flag two bytes of 1 s and an additional flag between packets Register Name Register Description LI TEPLC Transmit Errored Packet Low Control Register Register Address 0C6h Bit 7 6 5 4 3 2 1 0 Name TPEN7 TPEN6 5 4 TPENS3 TPEN2 TPEN1 TPENO Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Errored Packet Insertion Number TPEN 7 0 These eight bits indicate the total number of errored packets to be transmitted when triggered by TIAEI Error insertion will end after this number of errored packets have been transmitted A value of FFh results in continuous errored packet insertion at the specified rate 153 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI TEPHC Register
346. ption Transmit Signaling Registers T1 Mode D4 Format Register Address 50h to 5Bh MsB SB 51 TS2 TS3 54 TS5 TS6 57 TS8 TS9 TS10 TS11 TS12 Note In D4 format TR TS1 TR TS12 contain signaling data for two frames Bold type indicates data for second frame 248 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RS1 to TR RS12 Register Description Receive Signaling Registers 1 Mode ESF Format Register Address 60h to 6Bh MsB S B 51 RS2 RS3 RS4 RSS RS6 RS7 RS8 RS9 RS10 RS11 RS12 Register Name TR RS1 to TR RS12 Register Description Receive Signaling Registers T1 Mode D4 Format Register Address 60h to 6Bh MsB 1 B RS2 RS3 RS4 RSS RS6 RS7 RS8 RS9 RS10 RS11 RS12 Note D4 format TR TS1 TR TS12 contain signaling data for two frames Bold type indicates data for second frame 249 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RS1 to TR RS16 Register Description Receive Signaling Registers E1 Mode CAS Format Register Address 60h to 6Fh 10 pi ee sies ci esp cc 3 RS2 RS3 RS4 RSS RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 Register Name TR RS1 to TR RS16 Register Description Receive Signaling Registers E1 Mode CCS Forma
347. r Overflow Event BBCO A latched bit that is set when the 32 bit BERT bit counter BBC overflows Cleared when read and is not set again until another overflow occurs Bit 4 BERT Error Counter Overflow BECO Event BECO A latched bit that is set when the 24 bit BERT error counter BEC overflows Cleared when read and is not set again until another overflow occurs Bit 3 BERT Receive All Ones Condition BRA1 A latched bit that is set when 32 consecutive 1s are received Allowed to be cleared once a 0 is received This is a double interrupt bit Section 9 7 Bit 2 BERT Receive All Zeros Condition BRAO A latched bit that is set when 32 consecutive Os are received Allowed to be cleared once a 1 is received This is a double interrupt bit Section 9 7 Bit 1 BERT Receive Loss of Synchronization Condition BRLOS A latched bit that is set whenever the receive BERT begins searching for a pattern Once synchronization is achieved this bit remains set until read This is a double interrupt bit Section 9 7 Bit 0 BERT in Synchronization Condition BSYNC Set when the incoming pattern matches for 32 consecutive bit positions Refer to BSYNC in the TR INFO2 register for a real time version of this bit This is a double interrupt bit Section 9 7 229 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR9 Register Description Interrupt Mask Register 9 Register Address 27h Bit 7
348. racy of 50ppm for both T1 and 1 TR62411 and ANSI specifications require an accuracy of 32ppm for T1 interfaces A prescaler divides the 16MHz 8MHz or 4MHz clock down to 2 048MHz There is an on board PLL for the jitter attenuator which converts the 2 048MHz clock to a 1 544MHz rate for T1 applications Setting JAMUX TR LIC2 3 to a logic O bypasses this PLL 10 22 Jitter Attenuator The device contains an on board jitter attenuator that can be set to a depth of either 32 or 128 bits through the JABDS bit TR LIC1 2 The 128 bit mode is used in applications where large excursions of wander are expected The 32 bit mode is used in delay sensitive applications The characteristics of the attenuation are shown in Figure 10 12 The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit TR LIC1 3 Setting the DJA bit TR LIC1 1 disables in effect removes the jitter attenuator On board circuitry adjusts either the recovered clock from the clock data recovery block or the clock applied at the TCLKT pin to create a smooth jitter free clock that is used to clock data out of the jitter attenuator FIFO It is acceptable to provide a gapped bursty clock at the TCLKT pin if the jitter attenuator is placed on the transmit side If the incoming jitter exceeds either 120Ulp p buffer depth is 128 bits or 28Ulp p buffer depth is 32 bits then the transceiver divides the internal nomi
349. rated T1 E1 J1 Transceiver Register Name TR RSiAF Register Description Received Si Bits of the Align Frame Register Address C8h Bit 7 6 5 4 3 2 1 0 Name SiFO SiF2 SiF4 SiF6 SiF8 SiF10 SiF12 SiF14 Beau 05 0 0 qc 9r 4 0 01 Bit 7 Si Bit of Frame 0 SiFO Bit 6 Si Bit of Frame 2 SiF2 Bit 5 Si Bit of Frame 4 SiF4 Bit 4 Si Bit of Frame 6 SiF6 Bit 3 Si Bit of Frame 8 SiF8 Bit 2 Si Bit of Frame 10 SiF10 Bit 1 Si Bit of Frame 12 SiF12 Bit 0 Si Bit of Frame 14 SiF14 Register Name TR RSINAF Register Description Received Si Bits of the Nonalign Frame Register Address C9h Bit 7 6 5 4 3 2 1 0 SiF1 SiF3 SiF5 SiF7 SiF9 SiF11 SiF13 SiF15 Defaults 0c J 9 1 Bit 7 Si Bit of Frame 1 SiF1 Bit 6 Si Bit of Frame 3 SiF3 Bit 5 Si Bit of Frame 5 SiF5 Bit 4 Si Bit of Frame 7 SiF7 Bit 3 Si Bit of Frame 9 SiF9 Bit 2 Si Bit of Frame 11 SiF11 Bit 1 Si Bit of Frame 13 SiF13 Bit 0 Si Bit of Frame 15 SiF15 281 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RRA Register Description Received Remote Alarm Register Address Cah Bit 7 6 5 4 3 2 1 0 Name RRAF1 RRAF3 RRAF5 RRAF7 RRAF9 RRAF 11 RRAF 13 RRAF15 Beraut E 9 9 qo oo n 29r 3 c ee 9r Bit 7 Remote Alarm Bit of Frame 1 RRAF1 Bit 6 Remote Alarm Bit of Frame 3 RRAF3 Bit 5 Remote Alarm Bit of Frame 5
350. ration enabled at the same time Table 10 4 E1 Alarm Criteria ITU ALARM SET CRITERIA CLEAR CRITERIA SPECIFICATION An RLOS condition exists on power up prior to initial synchronization when a RLOS resync criteria has been met or when a manual resync has been initiated by TR E1RCR1 0 RCL 255 or 2048 consecutive Os received as At least 32 1s in 255 bit times G 775 G 962 determined by TR E1RCR2 0 are received Bit 3 of nonalign frame set to 1 for three Sit Sol nonalign frame 0 O 162 R 0 for three consecutive consecutive occasions 2 1 4 occasions Fewer than three Os in two frames 512 More than two Os in two O 162 bits frames 512 bits 1 6 1 2 Bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes V52LNK Two out of three Sa7 bits are 0 G 965 10 6 Per Channel Loopback The per channel loopback registers PCLRs determine which channels if any from the backplane should be replaced with the data from the receive side or i e off of the T1 or E1 line If this loopback is enabled then transmit and receive clocks and frame syncs must be synchronized One method to accomplish this is to connect RCLKO to TCLKT and RFSYNC to TSYNC There are no restrictions on which channels can be looped back or on how many channels can be looped back Each of the bit positions in the per channel loopback registers TR PCLR1 TR PCLR2 TR PCLR3 TR PCLR4 represents DSO channel the outgoing frame Whe
351. reezing is enabled RFE 1 the signaling data is held in the last known good state until the corrupting error condition subsides When the error condition subsides the signaling data is held in the old state for at least an additional 9ms or 4 5ms in D4 framing mode before updating with new signaling data 83 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 10 3 Simplified Diagram of Transmit Signaling Path TRANSMIT SIGNALING REGISTERS T1 E1 DATA STREAM SIGNALING amp TSIG BUFFERS TR T1TCR1 4 PER CHANNEL PER CHANNEL CONTROL CONTROL TR PCPR 3 TR SSIE1 TR SSIE4 ONLY APPLIES TO T1 MODE 10 9 3 Processor Based Transmit Signaling In processor based mode signaling data is loaded into the transmit signaling registers TS1 TS16 by the host interface On multiframe boundaries the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream The user can employ the transmit multiframe interrupt in status register 4 TR SR4 4 to know when to update the signaling bits The user need not update any transmit signaling register for which there is no change of state for that register Each transmit signaling register contains the robbed bit signaling T1 or TS16 CAS signaling E1 for two time slots that are inserted into the outgoing stream if enabled to do so t
352. register Note If TR ER3 through TR ERO 0 no errors are generated even if the constant error insertion feature is enabled 2A For constant error insertion set CE 1 TR ERC 4 Or 2B For a defined number of errors Set CE O TR ERC 4 Load TR NOE1 and TR NOE2 with the number of errors to be inserted Toggle WNOE TR ERC 7 from 0 to 1 to begin error insertion 10 26 1 Number of Errors Registers The number of error registers determine how many errors are generated Up to 1023 errors can be generated The host loads the number of errors to be generated into the TR NOE1 and TR NOE2 registers The host can also update the number of errors to be created by first loading the prescribed value into the TR NOE registers and then toggling the WNOE bit in the error rate control registers Table 10 15 Error Insertion Examples VALUE WRITE READ 000h Do not create any errors No errors left to be inserted 001h Create a single error One error left to be inserted 002h Create two errors Two errors left to be inserted 3FFh Create 1023 errors 1023 errors left to be inserted 111 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 27 Programmable Backplane Clock Synthesizer The transceiver contains an on chip clock synthesizer that generates a user selectable clock output on the BPCLK pin referenced to the recovered receive clock RCLKO The synthesizer uses a phase locke
353. revious versions of this document used the term Subscriber to refer to the Ethernet Interface function The register names have been allowed to remain with a SU prefix to avoid register renaming Note 2 Previous versions of this document used the term Line to refer to the Serial Interface The register names have been allowed to remain with a LI prefix to avoid register renaming Note 3 The terms Transmit Queue and Receive Queue are with respect to the Ethernet Interface The Receive Queue is the queue for the data that arrives on the MII RMII interface is processed by the MAC and stored in the SDRAM Transmit queue is for data that arrives from the Serial port is processed by the HDLC and stored in the SDRAM to be sent to the MAC transmitter Note 4 This data sheet assumes a particular nomenclature of the T1 operating environment In each 125us frame there are 24 8 bit channels plus a framing bit It is assumed that the framing bit is sent first followed by channel 1 Each channel is made up of eight bits that are numbered 1 to 8 Bit number 1 is the MSB and is transmitted first Bit number 8 is the LSB and is transmitted last The term locked is used to refer to two clock signals that are phase or frequency locked or derived from a common clock i e a 1 544MHz clock be locked to 2 048 2 clock if they share the same 8kHz component Throughout this data sheet the following abbreviations are used
354. rform transparency processing 7E is translated to 7D5E 7D is translated to 7D5D Append the end flag 7E Scramble the sequence X Note that the serial transmit and receive registers apply to the X 86 implementations with specific exceptions The exceptions are outlined in the serial interface transmit and receive register sections 70 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 20 Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility The CIR can be used restricts the transport of received MAC data to a programmable rate The CIR location is shown in the Figure 6 1 The CIR will restrict the data flow from the Receive MAC to Transmit HDLC This can be used for provisioning and billing functions towards the WAN The user must set the CIR register to control the amount of data throughput from the MAC to HDLC transmit The CIR register is in granularity of 500kbit s with a range of 0 to 52Mbit s The operation of the CIR is as follows The CIR block counts the credits that are accumulated at the end of every 125ms If data is received and stored in the SDRAM to be sent to the Serial Interface the interface will request the data if there is a positive credit balance If the credit balance is negative transmit interface does not request data New credit balance is calculated credit balance old credit balance frame size in bytes after the frame is sent The credit balance
355. rnet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description GL LIS Global Serial Interface Interrupt Status Register Address 07h Bit 7 6 5 4 3 2 0 LIN1TIS LIN1RIS Default 0 0 0 0 0 0 0 Bit 4 Serial Interface 1 TX Interrupt Status LINE1TIS This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event Serial Interface interrupts consist of HDLC interrupts and X 86 interrupts Bit 0 Serial Interface 1 RX Interrupt Status LINER1IS This bit is set if Serial Interface 1 Receive has enabled interrupt generating event Serial Interface interrupts consist of HDLC interrupts and X 86 interrupts Register Name Register Description GL SIE Global Ethernet Interface Interrupt Enable Register Address 08h Bit 7 6 5 4 3 2 0 SUB1IE Default 0 0 0 0 0 0 0 Bit 0 Ethernet Interface 1 Interrupt Enable SUB1IE Setting this bit to 1 enables an interrupt on SUB1S Register Name GL SIS Register Description Global Ethernet Interface Interrupt Status Register Address 09h Bit 7 6 5 4 3 2 0 Name SUB1IS Default 0 0 0 0 0 0 0 Bit 0 Ethernet Interface 1 Interrupt Status SUB1IS This bit is set to 1 if Ethernet Interface 1 has an enabled interrupt generating event The Ethernet Interface consists of the MAC and The R
356. rom receive FIFO and store in message buffer 9 Read TR INFOS register 10 If PS2 PS1 PSO 000 then go to Step 4 11 If PS2 PS1 PSO 001 then packet terminated OK save present message buffer 12 If PS2 PS1 PSO 010 then packet terminated with CRC error 13 If PS2 PS1 PSO 011 then packet aborted 14 If PS2 PS1 PSO 100 then FIFO overflowed 15 Go to Step 3 96 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 17 Legacy FDL Support T1 Mode 10 17 1 Overview To provide backward compatibility to the older 0521 52 T1 device the transceiver maintains the circuitry that existed in the previous generation of the T1 framer In new applications it is recommended that the HDLC controllers and BOC controller described in Section 10 14 and 10 16 are used 10 17 2 Receive Section In the receive section the recovered FDL bits or Fs bits are shifted bit by bit into the receive FDL register TR RFDL Because the TR RFDL is 8 bits in length it fills up every 2ms 8 x 250us The framer signals external microcontroller that the buffer has filled through the TR SR8 3 bit If enabled through TR IMR8 3 the INT pin toggles low indicating that the buffer has filled and needs to be read The user has 2ms to read this data before it is lost If the byte in the TR RFDL matches either of the bytes programmed into the TR RFDLM1 or TR RFDLM2 registers then the TR SR8 1 bit is set to 1 and the IN
357. ropriate bit s in the TR PCPR register The user then writes to the TR PCDR registers to select the channels for that function The following is an example of mapping the transmit and receive BERT function to channels 9 12 20 and 21 Write 11h to TR PCPR Write 00h to TR PCDR1 Write Ofh to TR PCDR2 Write 18h to TR PCDR3 Write 00h to TR PCDRA The user may write to the TR PCDR1 4 with multiple functions in the TR PCPR register selected but can only read the values from the TR PCDR1 4 registers for a single function at a time More information about how to use these per channel features can be found in the TR PCPR register 10 3 T1 E1 J1 Transceiver Interrupts Various alarms conditions and events in the T1 E1 J1 transceiver can cause interrupts For simplicity these are all referred to as events in this explanation All status registers can be programmed to produce interrupts Each status register has an associated interrupt mask register For example TR SR1 status register 1 has an interrupt control register called TR IMR1 interrupt mask register 1 Status registers are the only sources of interrupts in the device On power up all writeable registers of the T1 E1 J1 transceiver are automatically cleared Since bits in the TR IMRx registers have to be set 1 to allow a particular event to cause an interrupt no interrupts can occur until the host selects which events are to product interrupts Since there are potentially many sources
358. ropriate interrupt has been serviced and cleared as long as no additional enabled interrupt conditions are present in the associated status register All Latched Status bits must be cleared by the host writing a 1 to the bit location of the interrupt condition that has been serviced In order for individual status conditions to transmit their status to the next level of interrupt logic they must be enabled by placing a 1 in the associated bit location of the correct Interrupt Enable Register The Interrupt enable registers are LI TPPSRIE LI RPPSRIE LI RX86LSIE BSRIE SU QRIE GL LIE GL SIE GL BIE and GL TRQIE Latched Status bits that have been enabled via Interrupt Enable registers are allowed to pass their interrupt conditions to the Global Interrupt Status Registers The Interrupt enable registers allow individual Latched Status conditions to generate an interrupt but when set to zero they do not prevent the Latched Status bits from being set Therefore when servicing interrupts the user should AND the Latched Status with the associated Interrupt Enable Register in order to exclude bits for which the user wished to prevent interrupt service This architecture allows the application host to periodically poll the latched status bits for noninterrupt conditions while using only one set of registers Note the bit orders of SU QRIE and SU QCRLS are different Note that the inactive state of the interrupt output pin is configurable The INTM
359. rt sequence BOC messages are transmitted as long as TR BOCC 0 is set 10 14 1 1 Transmit a BOC 1 Write 6 bit code into the TR TFDL register 2 Set the SBOC bit in TR BOCC 1 10 14 2 Receive BOC The receive BOC function is enabled by setting TR BOCC 4 1 The TR RFDL register now operates as the receive BOC message and information register The lower six bits of the TR RFDL register BOC message bits are preset to all 1s When the BOC bits change state the BOC change of state indicator TR SR8 0 alerts the host The host then reads the TR RFDL register to get the BOC status and message A change of state occurs when either a new BOC code has been present for a time determined by the receive BOC filter bits RBFO and in the TR BOCC register or a nonvalid code is being received 10 14 2 1 Receive a BOC Set integration time through TR BOCC 1 and TR BOCC 2 Enable the receive BOC function 4 1 Enable interrupt TR IMR8 0 1 Wait for interrupt to occur Read the TR RFDL register If TR SR2 7 1 then a valid BOC message was received The lower six bits of the TR RFDL register comprise the message SEE OI 91 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 15 Additional Sa and International Si Bit Operation E1 Only When operated in the E1 mode the transceiver provides two methods for accessing the Sa and the Si bits The first method involves using the internal
360. rted from the transmit signaling registers 0 7 do not source signaling data from the TR TSx registers for this channel 1 source signaling data from the TR TSx registers for this channel Register Name TR SSIE3 E1 Mode Register Description Software Signaling Insertion Enable 3 Register Address 0Ah Bit 7 6 5 4 3 2 1 0 22 21 20 19 18 17 16 LCAW Default 0 0 0 0 0 0 0 0 Bits 1 7 Software Signaling Insertion Enable for LCAW and Channels 16 to 22 CH16 to CH22 These bits determine which channels are to have signaling inserted from the transmit signaling registers 0 7 do not source signaling data from the TR TSx registers for this channel 1 source signaling data from the TR TSx registers for this channel Bit 0 Lower CAS Align Alarm Word LCAW Selects the lower CAS align alarm bits xyxx to be sourced from the lower 4 bits of the TS1 register 0 do not source the lower CAS align alarm bits from the TR TS1 register 1 source the lower CAS alarm align bits from the TR TS1 register Register Name TR SSIE4 Register Description Software Signaling Insertion Enable 4 Register Address OBh Bit 7 6 5 4 3 2 1 0 Name CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 Default 0 0 0 0 0 0 0 0 Bits 0 7 Software Signaling Insertion Enable for Channels 22 to 30 CH23 to CH30 These bits determine which channels are to have signaling inserted from the transmit signaling re
361. ry 3ms on ESF MF boundaries Bit 1 Receive CRC4 Multiframe Event RCMF E1 Only Set on CRC4 multiframe boundaries continues to set every 2ms on an arbitrary boundary if CRC4 is disabled Bit 0 Receive Align Frame Event RAF E1 Only Set every 250us at the beginning of align frames Used to alert the host that Si and Sa bits are available in the TR RAF and TR RNAF registers 221 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IMR4 Register Description Interrupt Mask Register 4 Register Address 1Dh Bit 7 6 5 4 3 2 1 0 Name RAIS CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7 Receive AIS CI Event RAIS CI 0 interrupt masked 1 interrupt enabled Bit 6 Receive Signaling All Ones Event RSAO 0 interrupt masked 1 interrupt enabled Bit 5 Receive Signaling All Zeros Event RSAZ 0 interrupt masked 1 interrupt enabled Bit 4 Transmit Multiframe Event TMF 0 interrupt masked 1 interrupt enabled Bit 3 Transmit Align Frame Event TAF 0 interrupt masked 1 interrupt enabled Bit 2 Receive Multiframe Event RMF 0 interrupt masked 1 interrupt enabled Bit 1 Receive 4 Multiframe Event RCMF 0 interrupt masked 1 interrupt enabled Bit 0 Receive Align Frame Event RAF 0 interrupt masked 1 interrupt enabled 222 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register N
362. s 0 7 SDRAM Refresh Time Control SREFTO SREFT7 These 8 bits are used to control the SDRAM refresh frequency The refresh rate will be equal to this register value x 8 x 100MHz Note This register has a nonzero default value This should be taken into consideration when initializing the device Note After changing the value of this register the user must toggle the GLL SDMODEWS SDMWV bit to write the new values to the SDRAM 142 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface It is responsible for queuing and dequeuing data to an external SDRAM The arbiter handles requests from the HDLC and MAC to transfer data to from the SDRAM The base address of the Arbiter register space is 0040h 11 3 1 Arbiter Register Bit Descriptions AR RQSC1 Arbiter Receive Queue Size Connection Register Name Register Description Register Address 40h Bit 7 6 5 4 3 2 1 0 Name RQSC7 RQSC6 RQSC5 RQSC4 RQSC3 RQSC2 RQSC1 RQSCO Default 0 0 1 1 1 1 0 1 Bits 0 7 Receive Queue Size RQSC 0 7 These 7 bits of the size of receive queue associated with the connection Receive queue is for data arriving from the MAC to be sent to the WAN The Queue address size is defined in increments of 32 x 2048 bytes The queue size is AR RQSC1 multiplied by 32 to determine the number of 2048 by
363. s described in this section 10 4 1 T1 Transmit Transparency The software signaling insertion enable registers TR SSIE1 TR SSIEA4 can be used to select signaling insertion from the transmit signaling registers 51 512 a per channel basis Setting a bit in the SSIEx register allows signaling data to be sourced from the signaling registers for that channel In transparent mode bit 7 stuffing and or robbed bit signaling is prevented from overwriting the data in the channels If a DSO is programmed to be clear no robbed bit signaling is inserted nor does the channel have bit 7 stuffing performed However in the D4 framing mode bit 2 is overwritten by a 0 when a Yellow Alarm is transmitted Also the user has the option to globally override the TR SSIEx registers from determining which channels are to have bit 7 stuffing performed If the TR TTTCR1 3 and TR T1TCR2 0 bits are set to 1 then all 24 T1 channels have bit 7 stuffing performed on them regardless of how the TR SSIEx registers are programmed In this manner the TR SSIEx registers are only affecting the channels that are to have robbed bit signaling inserted into them 10 4 2 AIS CI and RAI CI Generation and Detection The device can transmit and detect the RAI CI and AIS CI codes in T1 mode These codes are compatible with and do not interfere with the standard RAI Yellow and AIS Blue alarms These codes are defined in ANSI T1 403 The AIS CI code alarm indication signa
364. scription Register Address 14Fh Bit 7 6 5 4 3 2 1 0 Name QLP Default 0 0 0 0 0 0 0 0 Bit 0 Queue Loopback Enable QLP If this bit is set to 1 data from the Ethernet Interface receive queue is looped back to the transmit queue Buffered data from the serial interface will remain until the loopback is removed SU GCR Ethernet Interface General Control Register Register Name Register Description Register Address 150h Bit 7 5 4 3 2 1 0 Name CRCS 105 ATFLOW JAME Default 0 0 0 0 0 1 0 Bit 3 CRCS If this bit is zero default the received MAC or Ethernet Frame CRC is stripped before the data is encapsulated and transmitted on the serial interface Data received from the serial interface is decapsulated a CRC is recalculated and appended to the packet for transmission to the Ethernet interface If this bit is set to 1 the CRC is not stripped from received packets prior to encapsulation and transmission to the serial interface and data received from the serial interface is decapsulated directly No CRC recalculation is performed on data received from the serial interface Note that the maximum packet size supported by the Ethernet interface is still 2016 this includes the 4 bytes of CRC Bit 2 H10S This bit controls the 10 100 selection for RMII and DCE Mode When in RMII mode setting this bit to 1 will cause the MAC will operate at
365. scription Receive Packet Count Byte 0 Register Register Address 108h Bit 7 6 5 4 3 2 1 0 Name RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Packet Count RPC 7 0 Eight bits of a 24 bit value Register description below Register Name LI RPCB1 Register Description Receive Packet Count Byte 1 Register Register Address 109h Bit 7 6 5 4 3 2 1 0 RPC15 RPC14 RPC13 RPC12 RPC11 RPC10 RPCO9 RPCOS8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Packet Count RPC 15 8 Eight bits of a 24 bit value Register description below Register Name LI RPCB2 Register Description Receive Packet Count Byte 2 Register Register Address 10Ah Bit 7 6 5 4 3 2 1 0 Name RPC23 RPC22 RPC21 RPC20 RPC19 RPC18 RPC17 RPC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Packet Count RPC 23 16 These twenty four bits indicate the number of packets stored in the receive FIFO without an abort indication Note Packets discarded due to system loopback or an overflow condition are included in this count This register is valid when clear channel is enabled 165 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RFPCBO Register Description Receive FCS Errored Packet Count Byte 0 Register Register Address 10Ch Bit 7 6 5 4 3 2
366. sert data from the idle code array into the receive data stream 1 insert data from the idle code array into the receive data stream 261 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR RCICE2 Register Description Receive Channel Idle Code Enable Register 2 Register Address 85h Bit 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Bea ee Bits 0 7 Receive Channels 9 to 16 Code Insertion Control Bits CH9 to CH16 0 do not insert data from the idle code array into the receive data stream 1 insert data from the idle code array into the receive data stream Register Name TR RCICE3 Register Description Receive Channel Idle Code Enable Register 3 Register Address 86h Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Defaut 0 Bits 0 7 Receive Channels 17 to 24 Code Insertion Control Bits CH17 to CH24 0 do not insert data from the idle code array into the receive data stream 1 7 insert data from the idle code array into the receive data stream Register Name TR RCICEA Register Description Receive Channel Idle Code Enable Register 4 Register Address 87h Bit 7 6 5 4 3 2 1 0 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 Default 0 Bits 0 7 Receive Channels 25 to 32 Code Insertion Control Bits CH25 to CH32 0 do not insert data from the idle code array into the receive data stream 1 insert data from
367. set the receive synchronization clock enable TR LIC3 2 1 10 20 2 3 Monitor Mode Monitor applications in both E1 and T1 require various flat gain settings for the receive side circuitry The device can be programmed to support these applications through the monitor mode control bits MM1 and in the TR LIC3 register Figure 10 5 Figure 10 5 Typical Monitor Application PRIMARY T1 E1 LINE T1 E1 TERMINATING T DEVICE 1 1 in XCVR MONITOR PORT JACK SECONDARY T1 E1 TERMINATING DEVICE 101 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 20 3 Transmitter The transceiver uses a phase lock loop along with a precision digital to analog converter DAC to create the waveforms that are transmitted onto the E1 or T1 line The waveforms created by the device meet the latest ETSI ITU T ANSI and AT amp T specifications The user selects which waveform is generated by setting the ETS bit TR LIC2 7 for E1 or T1 operation then programming the L2 L1 LO bits in register TR LIC1 for the appropriate application 2 048MHz or 1 544MHz clock is required at TDCLKI for transmitting data presented at TPOSI and TNEGI Normally these pins are connected to TCLKO TPOSO and TNEGO However the LIU can operate in an independent fashion ITU specification G 703 requires an accuracy of 50ppm for both T1 and E1 TR62411 ANSI specifications require an acc
368. ster Address 141h Bit 7 6 5 4 3 2 1 0 Name MACRA1 MACRA1 MACRA1 MACRA1 MACRA1 MACRA1 MACRA9 MACRA8 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Read Address 8 15 High byte of the MAC indirect register address Used only for read operations Register Name SU MACRDO Register Description MAC Read Data Byte 0 Register Address 142h Bit 7 6 5 4 3 2 1 0 Name MACRD7 MACRD6 MACRD5 MACRD4 MACRD3 MACRD2 MACRD1 MACRDO Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Read Data 0 MACRDO 7 One of four bytes of data read from the MAC Valid after a read command has been issued and the SU MACRWC MCS bit is zero 174 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU MACRD1 Register Description MAC Read Data Byte 1 Register Address 143h Bit 7 6 5 4 3 2 1 0 MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 MACRD8 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Read Data 1 MACRD8 15 One of four bytes of data read from the MAC Valid after a read command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACRD2 Register Description MAC Read Data Byte 2 Register Address 144h Bit 7 6 5 4 3 2 1 0 MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16 Default 0 0 0 0 0 0 0 0
369. ster Address E7h Bit 7 6 5 4 3 2 1 0 EC6 EC5 EC4 EC3 EC2 EC1 ECO Defaut 0 0 o o o o 0 Bits 0 7 Error Counter Bits 0 to 7 ECO to EC7 ECO is the LSB of the 24 bit counter Register Name TR BEC2 Register Description BERT Error Count Register 2 Register Address E8h Bit 7 6 5 4 3 2 1 0 Name EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 Defaut 0 Bits 0 7 Error Counter Bits 8 to 15 EC8 to EC15 Register Name TR BEC3 Register Description BERT Error Count Register 3 Register Address E9h Bit 7 6 5 4 3 2 1 0 23 22 21 20 19 EC18 EC17 EC16 Defaut 0 Bits 0 7 Error Counter Bits 16 to 23 EC16 to EC23 ECO is the MSB of the 24 bit counter 295 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR BIC Register Description BERT Interface Control Register Register Address EAh Bit 7 6 5 4 3 2 1 0 Name RFUS TBAT TFUS BERTDIR BERTEN Defaut 0 0 0 Bit 6 Receive Framed Unframed Select RFUS 0 BERT is not sent data from the F bit position framed 1 BERT is sent data from the F bit position unframed Bit 4 Transmit Byte Align Toggle TBAT A 0 to 1 transition forces the BERT to byte align its pattern with the transmit formatter This bit must be transitioned in order to byte align the Daly pattern Bit 3 Transmit Framed Unframed Select TFUS 0 BERT does not source d
370. stores are fully independent The transmit and receive side elastic stores can be enabled disabled independently of each other Also each elastic store can interface to either a 1 544MHz or 2 048MHz 4 096MHz 8 192MHz 16 384MHz backplane without regard to the backplane rate the other elastic store is interfacing to The elastic stores have two main purposes Firstly they can be used for rate conversion When the device is in the T1 mode the elastic stores can rate convert the T1 data stream to a 2 048MHz backplane In E1 mode the elastic store can rate convert the E1 data stream to a 1 544MHz backplane Secondly they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous i e not locked backplane clock which can be 1 544MHz or 2 048MHz In this mode the elastic stores manage the rate difference and perform controlled slips deleting or repeating frames of data in order to manage the difference between the network and the backplane The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates 10 12 1 Receive Elastic Store See the TR IOCR1 and TR IOCR2 registers for information about clock and I O configurations If the receive side elastic store is enabled then the user must provide either a 1 544MHz 2 048MHz clock at the RSYSCLK pin The user has the option of either providing a frame multiframe sync at the RSYNC pin or having the RSYNC pin pr
371. sure that it is equal to zero prior to beginning a MDIO instruction 188 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name SU MACMIID Register Description MAC MII MDIO Data Register Register Address 0018h indirect 0018h Bit 31 30 29 28 27 26 25 24 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0019h Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 001Ah Bit 15 14 13 12 11 10 09 08 Name MIID15 MIID14 MIID13 MIID12 MIID1 1 MIID10 MIIDO9 MIIDO8 Default 0 0 0 0 0 0 0 0 001Bh Bit 07 06 05 04 03 02 01 00 Name MIIDO7 MIIDO6 MIIDO5 MIIDO4 MIIDO3 MIIDO2 MIIDO1 MIIDOO Default 0 0 0 0 0 0 0 0 Bits 0 15 MII MDIO Data MIID 00 15 These two bytes contain the data to be written to or the data read from the MII management interface 189 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU MACFCR MAC Flow Control Register Register Name Register Description Register Address 001Ch indirect 001Ch Bit 31 30 29 28 27 26 25 24 Name
372. t Register Address 60h to 6Fh prc 7 8 151 122 RS16 250 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR CCR1 Register Description Common Control Register 1 Register Address 70h Bit 7 6 5 4 3 2 1 0 Name MCLKS CRCAR SIE ODM DICAI TCSS1 TCSSO RLOSF Default 0 0 0 0 0 0 0 0 Bit 7 MCLK Source MCLKS Selects the source of MCLK 0 MCLK is source from the MCLK pin 1 MCLK is source from the TSYSCLK pin Bit 6 CRC 4 Recalculate CRC4R 0 transmit CRC 4 generation and insertion operates in normal mode 1 transmit CRC 4 generation operates according to G 706 intermediate path recalculation method Bit 5 Signaling Integration Enable SIE 0 signaling changes of state reported on any change in selected channels 1 signaling must be stable for three multiframes in order for a change of state to be reported Bit 4 Output Data Mode ODM 0 pulses at TPOSO and TNEGO are one full TCLKO period wide 1 pulses at TPOSO and TNEGO are one half TCLKO period wide Bit 3 Disable Idle Code Auto Increment DICAI Selects deselects the auto increment feature for the transmit and receive idle code array address register See Section 10 10 0 addresses in TR IAAR register automatically increment on every read write operation to the TR PCICR register 1 addresses in TR IAAR register do not automatically increment Bit 2 Transmit C
373. t 6 Automatic Gain Control Enable AGCE 0 use Transmit AGC TR TLBC bits 0 5 are don t care 1 do not use Transmit AGC TR TLBC bits 0 5 set nominal level Bits 0 5 Gain Control Bits GC0 GC5 The through GC5 bits control the gain setting for the nonautomatic gain mode Use the tables below for setting the recommended values The LB line build out column refers to the value in the LO L2 bits in TR LIC1 Line Interface Control 1 register NETWORK MODE GC5 GC4 G GC2 G G e T1 Impedance Match Off T1 Impedance Match On E1 Impedance Match Off E1 Impedance Match On 2 o o amp 2 o o o amp ow 2 o o o c gt 4 S S A LB IoOooOI B cOo oO o oooo oo 256 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR LIC2 Register Description Line Interface Control 2 Register Address 79h Bit 7 6 5 4 3 2 1 0 Name ETS LIRST IBPV TUA1 JAMUX SCLD CLDS Defaut 0 9 0 9 o 0o 9 Bit 7 E1 T1 Select ETS 0 T1 mode sele
374. t Byte 2 Register Register Address 9Ah Bit 7 6 5 4 3 2 1 0 Name BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Count BC 16 23 Eight bits of a 32 bit value Register description below Register Name RBCB3 Register Description Receive Bit Count Byte 3 Register Register Address 9Bh Bit 7 6 5 4 3 2 1 0 Name BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24 Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Count BC 24 31 Upper 8 bits of the register Bit Count BC 0 31 These thirty two bits indicate the number of bits in the incoming data stream This count stops incrementing when it reaches a count of FFFF FFFFh The associated bit counter will not incremented when an OOS condition exists 150 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port The Serial Interface register map consists of registers that are common functions transmit functions and receive functions Bits that are underlined are read only all other bits can be written All reserved registers and bits with designation should be written to zero unless specifically noted in the register definition When read the information from reserved registers and bits designated with should be discarded Counter registers are updated by asserting low to high transit
375. t TSERI already has the FAS NFAS CRC multiframe alignment word and CRC 4 checksum in time slot 0 The user can modify the Sa bit positions This change in data content is used to modify the CRC 4 checksum This modification however does not corrupt any error information the original CRC 4 checksum may contain In this mode of operation TSYNC must be configured to multiframe mode The data at TSERI must be aligned to the TSYNC signal If TSYNC is an input then the user must assert TSYNC aligned at the beginning of the multiframe relative to TSERI If TSYNC is an output the user must multiframe align the data presented to TSERI Figure 10 4 CRC 4 Recalculate Method TPOSO TNEGO INSERT EXTRACT lt NEW 4 OLD CRC 4 k CODE CODE m d k CRC 4 MODIFY CALCULATOR Sa BIT POSITIONS NEW Sa BIT DATA 90 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 14 T1 Bit Oriented Code BOC Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side The BOC function is available only in T1 mode 10 14 1 Transmit BOC Bits 0 to 5 in the TR TFDL register contain the BOC message to be transmitted Setting 0 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position The transmit BOC controller automatically provides the abo
376. t and receive HDLC mapping options and idle flags are selected here These registers also reset the HDLC controllers 93 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Table 10 12 HDLC Controller Registers REGISTER FUNCTION CONTROL AND CONFIGURATION TR H1TC HDLC 1 Transmit Control Register General control over the transmit HDLC controllers TR H2TC HDLC 2 Transmit Control Register TR H1RC HDLC 1 Receive Control Register TR H2RC HDLC 2 Receive Control Register TR H1FC HDLC 1 FIFO Control Register Sets high watermark for receiver and low TR H2FC HDLC 2 FIFO Control Register watermark for transmitter STATUS AND INFORMATION TR SR6 HDLC 1 Status Register Key status information for both transmit and TR IMR6 HDLC 1 Interrupt Mask Register Selects which bits in the status registers SR7 and TR IMR7 HDLC 2 Interrupt Mask Register SR8 cause interrupts TR INFO4 HDLC 1 and 2 Information Register Information about HDLC controller TR INFO5 HDLC 1 Information Register TR INFO6 HDLC 2 Information Register TR H1RPBA HDLC 1 Receive Packet Bytes Available TR H2RPBA HDLC 2 Receive Packet Bytes Available from the receive FIFO TR H1TFBA HDLC 1 Transmit FIFO Buffer Available TR H2TFBA HDLC 2 Transmit FIFO Buffer Available the transmit FIFO MAPPING TR H1RCS1 TR H1RCS2 TR H1RCS3 TR H1RCS4 Selects which channels are mapped to the receive HDLC 1 Receive Channel Select Registers H
377. t bit errors in Fs bit position as well as Ft bit position Bit 1 Multiframe Out of Sync Count Register Function Select MOSCRF 0 7 count errors in the framing bit position 1 count the number of multiframes out of sync Bit 0 T1 Line Code Violation Count Register Function Select LCVCRF 0 do not count excessive 05 1 count excessive 0 239 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR LCVCR1 Register Description Line Code Violation Count Register 1 Register Address 42h Bit 7 6 5 4 3 2 1 0 Name LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCVC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Line Code Violation Counter Bits 8 to 15 LCVC8 to LCVC15 LCVC 15 is the MSB of the 16 bit code violation count Register Name TR LCVCR2 Register Description Line Code Violation Count Register 2 Register Address 43h Bit 7 6 5 4 3 2 1 0 Name LCVC7 LCVC6 LCVC5 LCVCA LCVC3 LCVC2 LCVC1 LCVCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Line Code Violation Counter Bits 0 to 7 LCVCO to LCVC7 LCVCO is the LSB of the 16 bit code violation count Register Name TR PCVCR1 Register Description Path Code Violation Count Register 1 Register Address 44h Bit 7 6 5 4 3 2 1 0 PCVC15 14 PCVC13 12 11 10 9 PCVC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Path Code Violation Counter Bits 8 to 15 PCVC8 to PCVC15 PCV
378. t bit received is expected to be the MSB DT 7 of the byte When set to 1 bit reordering is enabled and the first bit received is expected to be the LSB DT 0 of the byte Bit 0 Receive Clear Channel Enable RCCE When equal to 0 packet processing is enabled When set to 1 the device is in clear channel mode and all packet processing functions except descrambling and bit reordering are disabled 161 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description LI RMPSCL Receive Maximum Packet Size Control Low Register Register Address 102h Bit 7 6 5 4 3 2 1 0 Name RMX7 RMX6 RMX5 RMX4 RMX3 RMX2 RMX1 RMXO Default 1 1 1 0 0 0 0 0 Bits 0 7 Receive Maximum Packet Size RMX 7 0 Eight bits of a sixteen bit value Register description below Register Name Register Description LI RMPSCH Receive Maximum Packet Size Control High Register Register Address 103h Bit 7 6 5 4 3 2 1 0 Name RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8 Default 0 0 0 0 0 1 1 1 Bits 0 7 Receive Maximum Packet Size RMX 8 15 These sixteen bits indicate the maximum allowable packet size in bytes The size includes the FCS bytes but excludes bit byte stuffing Note If the maximum packet size is less than the minimum packet size all packets are discarded When packet processing is disabled these sixteen bits ind
379. t must be retransmitted due to a collision Bit 6 Heartbeat Failure HBF When this bit is set the device failed to detect a heart beat after transmission This bit is not valid if an under run has occurred Bits 2 5 Collision Count 0 3 These 4 bits indicate the number of collisions that occurred prior to successful transmission of the previous frame Not valid if Excessive Collisions is set to 1 Bit 1 Late Collision LCO When set to 1 the MAC observed a collision after the 64 byte collision window Bit 0 Deferred Frame DEF When set to 1 the current frame was deferred due to carrier assertion by another node after being ready to transmit 180 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver SU RFSBO Receive Frame Status Byte 0 Register Name Register Description Register Address 154h Bit 7 6 5 4 3 2 1 0 Name FL7 FL6 FL5 FL4 FL3 FL2 FL1 FLO Default 0 0 0 0 0 0 0 0 Bits 0 7 Frame Length FL 0 7 These 8 bits are the low byte of the length in bytes of the received frame with FCS and Padding If Automatic Pad Stripping is enabled this value is the length of the received packet without PCS or Pad bytes The upper 6 bits are contained in SU RFSB1 Register Name Register Description SU RFSB1 Receive Frame Status Byte 1 Register Address 155h Bit 7 6 5 4 3 2 1 0 Name RF WT FL13 FL12 FL11 FL10 FL9 FL8 Default 0 0 0 0 0 0 0 0
380. t performed FCS byte extraction discards the FCS bytes If FCS extraction is enabled the FCS bytes are extracted from the packet and discarded If FCS extraction is disabled the FCS bytes are stored in the receive FIFO with the packet If FCS processing or packet processing is disabled FCS byte extraction is not performed 66 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Bit reordering changes the bit order of each byte If bit reordering is disabled the incoming 8 bit data stream DT 1 8 with DT 1 being the MSB and DT 8 being the LSB is output to the Receive FIFO with the MSB RFD 7 or 15 23 or 31 and the LSB in RFD O or 8 16 or 24 of the receive FIFO data RFD 7 0 or 15 8 23 16 or 31 24 If bit reordering is enabled the incoming 8 bit data stream DT 1 8 is output to the Receive FIFO with the MSB in RFD 0 and the LSB in RFD T7 of the receive FIFO data RFD 7 0 DT 1 is the first bit received from the incoming data stream Once all of the packet processing has been completed The 8 bit parallel data stream is demultiplexed into a 32 bit parallel data stream The Receive FIFO data is passed on to the Receive FIFO with packet start packet end packet abort and modulus indications At a packet end the 32 bit word may contain 1 2 3 or 4 bytes of data depending on the number of bytes in the packet The modulus indications indicate the number of bytes in the last data word of the packet Figur
381. ta to be clocked through the RPOSI J3 receive side framer RPOSI and RNEGI can be connected together for an NRZ interface Can be internally connected to RPOSO by connecting the LIUC pin high Receive Positive Data Output from the T1 E1 J1 LIU Updated RPOSO N3 on the rising edge of RDCLKO with bipolar data out of the line interface This pin is normally connected to RPOSI Receive Data from the T1 E1 J1 Framer Updated on the rising RDATA H3 edge of RCLKO with the data out of the receive side framer before passing through the Elastic Store Serial Interface Transmit Clock Input for the T1 E1 J1 LIU Line TDCLKI D1 interface transmit clock This pin is normally tied to TCLKO be internally connected to TCLKO by connecting the LIUC pin high 34 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION TDCLKO C2 Transmit Clock Output from the T1 E1 J1 Framer Buffered clock that is used to clock data through the transmit side formatter either TCLKT or RDCLKI This pin is normally tied to TDCLKI TNEGI C3 Transmit Negative Data Input Sampled on the falling edge of TDCLKI for data to be transmitted out onto the T1 line Can be internally connected to TNEGO by connecting the LIUC pin high TPOSI and TNEGI can be connected together in NRZ applications TNEGO D3 Transmit Negative Data Output Updated on the rising edge o
382. tains both a shift register path and a latched parallel output for all control cells and digital I O cells and is n bits in length 14 4 2 Bypass Register This is a single one bit shift register used in conjunction with the BYPASS CLAMP and HIGHZ instructions which provides a short path between JTDI and JTDO 14 4 3 Identification Register The identification register contains a 32 bit shift register and a 32 bit latched parallel output This register is selected during the IDCODE instruction and when the TAP controller is in the Test Logic Reset state 341 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 14 5 JTAG Functional Timing This functional timing for the JTAG circuits shows The JTAG controller starting from reset state e Shifting out the first 4 LSB bits of the IDCODE e Shifting in the BYPASS instruction 111 while shifting out the mandatory X01 pattern e Shifting the TDI pin to the TDO pin through the bypass shift register An asynchronous reset occurs while shifting Figure 14 3 JTAG Functional Timing INST STATE JTCLK JTRST JTMS JTDI JTDO Output Pin 342 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 15 PACKAGE INFORMATION The package drawing s in this data sheet may not reflect the most current specifications The package number provided for each package is a link to the latest package outline information 15 1 256 Ball
383. te Addresses 110h through 113h must each be initialized with all 175 FFh for proper software mode operation 193 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description SU RxFrmCtr Frames Received Counter Register Address 0200h indirect 0200h Bit 31 30 29 28 27 26 25 24 Name RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24 Default 0 0 0 0 0 0 0 0 0201h Bit 23 22 21 20 19 18 17 16 Name RXFRMC23 RXFRMC22 RXFRMC21 RXFRMC20 RXFRMC19 RXFRMC18 RXFRMC17 RXFRMC16 Default 0 0 0 0 0 0 0 0 0202h Bit 15 14 13 12 11 10 09 08 Name RXFRMC15 RXFRMC14 RXFRMC13 RXFRMC12 RXFRMC11 RXFRMC10 RXFRMC9 RXFRMC8 Default 0 0 0 0 0 0 0 0 0203h Bit 07 06 05 04 03 02 01 00 Name RXFRMC7 RXFRMC6 RXFRMC5 RXFRMC4 RXFRMC3 RXFRMC2 RXFRMC1 RXFRMCO Default 0 0 0 0 0 0 0 0 Bits 0 31 Frames Received Counter RXFRMC 0 31 32 bit value indicating the number of frames received Each time a frame is received this counter is incremented by 1 This counter resets only upon device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the
384. te Count RBC 7 0 Eight bits of a 32 bit value Register description below Register Name LI RBC1 Register Description Receive Byte Count 1 Register Register Address Bit 7 6 5 4 3 2 1 0 Name RBC15 RBC14 RBC13 RBC12 RBC11 RBC10 RBC9 RBC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Byte Count RBC 15 8 Eight bits of a 32 bit value Register description below Register Name LI RBC2 Register Description Receive Byte Count 2 Register Register Address 11Ah Bit 7 6 5 4 3 2 1 0 Name RBC23 RBC22 RBC21 RBC20 RBC19 RBC18 RBC17 RBC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Byte Count RBC 23 16 Eight bits of a 32 bit value Register description below Register Name LI RBC3 Register Description Receive Byte Count 3 Register Register Address 11Bh Bit 7 6 5 4 3 2 1 0 Name RBC31 RBC30 RBC29 RBC28 RBC27 RBC26 RBC25 RBC24 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Byte Count RBC 31 24 These thirty two bits indicate the number of bytes contained in packets stored in the receive FIFO without an abort indication Note Bytes discarded due to FCS extraction system loopback FIFO reset or an overflow condition may be included in this count 169 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name LI RACO Register Description Receive Aborted Byte Count 0 Register Register Address 11Ch Bit 7 6 5 4 3 2 1 0 Name REBC7 RE
385. te packets that can be stored in the queue This queue is constructed in the external SDRAM Note Queue size of 0 is not allowed and should never be set AR TQSC1 Arbiter Transmit Queue Size Connection 1 Register Name Register Description Register Address 41h Bit 7 6 5 4 3 2 1 0 Name TQSC7 TQSC6 TQSC5 TQSC4 TQSC3 TQSC2 TQSC1 TQSCO Default 0 0 0 0 0 0 1 1 Bits 0 7 Transmit Queue Size TQSC 0 7 This is size of transmit queue associated with the connection The queue address size is defined in increments of 32 packets The range of bytes will depend on the external SDRAM connected to the DS33R11 Transmit queue is the data queue for data arriving on the WAN that is sent to the MAC Note that queue size of 0 is not allowed and should never be set 143 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 4 BERT Registers Register Name BCR Register Description BERT Control Register Register Address 80h Bit 7 6 5 4 3 2 1 0 Name PMU RNPL RPIC MPR APRD TNPL TPIC Default 0 0 0 0 0 0 0 0 Bit 7 This bit must be kept low for proper operation Bit 6 Performance Monitoring Update PMU This bit causes a performance monitoring update to be initiated A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data and the counters reset 0 or 1 For a second performance monitoring update to be init
386. ted Information Rate Register Address ODDh Bit 7 6 5 4 3 2 1 0 Name CIRE CIR6 5 4 2 CIR1 CIRO Default 0 0 0 0 0 0 0 1 Bit 7 Committed Information Rate Enable CIRE Set this bit to 1 to enable the Committed Information Rate Controller feature Bits 0 6 Committed Information Rate CIRO 6 These bits provide the value for the committed information rate The value is multiplied by 500kbit s to get the CIR value The user must ensure that the CIR value is less than or equal to the maximum Serial Interface transmit rate The valid range is from 1 to 104 Any values outside this range will result in unpredictable behavior Note that a value of 104 translates to a 52Mbit s line rate Hence if the CIR is above the line rate the rate is not restricted by the CIR For instance if using a T1 line and the CIR is programmed with a value of 104 it has no effect in restricting the rate 160 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 11 5 3 Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface Note that throughout this document HDLC Processor is also referred to as Packet Processor The receive packet processor block has seventeen registers 11 5 3 1 Receive Serial Register Bit Descriptions Register Name LI RSLCR Register Description Receive Serial Interface Configuration Re
387. ted by LI TOCTLS TOHTS Interrupts can be enabled on the latched bit events by LI TQTIE A latched status bit LI TQCTLS TQLTS is also set when the queue crosses a low watermark The Receive Queue functions in a similar manner Note that the user must ensure that sizes and watermarks are set in accordance with the configuration speed of the Ethernet and Serial interfaces The DS33R11 does not provide error indication if the user creates a connection and queue that overwrites data for another connection queue The user must take care in setting the queue sizes and watermarks The registers of relevance are AR RQSC1and SU QCRLS Queue size should never be set to 0 51 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver It is recommended that the user reset the queue pointers for the connection after disconnection The pointers must be reset before a connection is made If this disconnect connect procedure is not followed incorrect data may be transmitted The proper procedure for setting up a connection follows Set up the queue sizes for both transmit and receive queue AR TQSC1 and 5 1 Set up the high low thresholds and interrupt enables if desired GL TROIE LI TQTIE SU QRIE Reset all the pointers for the connection desired GL C1QPR Set up the connections GL CON1 If a connection is disconnected reset the queue pointers after the disconnection Table 9 3 Registers Related to Connections and Queues
388. ter Address DAh Bit 7 6 5 4 3 2 1 0 Name SiAF SINAF RA Sa4 Sa5 Sa6 8 Defaut 0 0 0 o 0o 0o 0 0 Bit 7 International Bit in Align Frame Insertion Control Bit SiAF 0 do not insert data from the TR TSiAF register into the transmit data stream 1 insert data from the TR TSiAF register into the transmit data stream Bit 6 International Bit in Nonalign Frame Insertion Control Bit SiNAF 0 do not insert data from the TR TSiNAF register into the transmit data stream 1 insert data from the TR TSiNAF register into the transmit data stream Bit 5 Remote Alarm Insertion Control Bit RA 0 do not insert data from the register into the transmit data stream 1 insert data from the TR TRA register into the transmit data stream Bit 4 Additional Bit 4 Insertion Control Bit Sa4 0 do not insert data from the TR TSa4 register into the transmit data stream 1 insert data from the TR TSa4 register into the transmit data stream Bit 3 Additional Bit 5 Insertion Control Bit Sa5 0 do not insert data from the TR TSa5 register into the transmit data stream 1 7 insert data from the TR TSa5 register into the transmit data stream Bit 2 Additional Bit 6 Insertion Control Bit Sa6 0 do not insert data from the TR TSa6 register into the transmit data stream 1 insert data from the TR TSa6 register into the transmit data stream Bit 1 Additional Bit 7 Insertion Control Bit Sa7 0 do not insert dat
389. th Integrated T1 E1 J1 Transceiver Register Name TR INFO7 Register Description Information Register 7 Real Time Non Latched Register Register Address 30h Bit 7 6 5 4 3 2 1 0 5 5 CSC4 CSC3 CSC2 CSCO FASSA CASSA CRCASA Default 0 0 0 0 0 0 0 0 Bits 3 7 CRC4 Sync Counter Bits CSC2 to CSC4 The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level The counter can also be cleared by disabling the CRC4 mode TR ETRCR1 3 0 This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level ITU G 706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms then the search should be abandoned and proper action taken The CRC4 sync counter rolls over CSCO is the LSB of the 6 bit counter Note The bit next to LSB is not accessible CSC1 is omitted to allow resolution to gt 400ms using 5 bits These are read only non latched real time bits It is not necessary to precede the read of these bits with a write Bit 2 FAS Sync Active FASSA Set while the synchronizer is searching for alignment at the FAS level This is a read only non latched real time bit It is not necessary to precede the read of this bit with a write Bit 1 CAS MF Sync Active CASSA Set while the synchronizer is sear
390. the receive data associated with this channel 1 7 replace the receive data associated with this channel with digital milliwatt code 211 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR IDR Register Description Device Identification Register Register Address OFh Bit 7 6 5 4 3 2 1 0 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 IDO Default 1 0 1 1 X X X X Bits 4 7 Device ID 1 4 to 1 7 The upper four bits of TR IDR are used to display the transceiver ID Bits 0 3 Chip Revision Bits IDO to ID3 The lower four bits of TR IDR are used to display the die revision of the chip IDO is the LSB of a decimal code that represents the chip revision Register Name TR INFO1 Register Description Information Register 1 Register Address 10h Bit 7 6 5 4 3 2 1 0 RPDV TPDV COFA 820 1620 SEFE B8ZS FBE Default 0 0 0 0 0 0 0 0 Bit 7 Receive Pulse Density Violation Event RPDV Set when the receive data stream does not meet the ANSI T1 403 requirements for pulse density Bit 6 Transmit Pulse Density Violation Event TPDV Set when the transmit data stream does not meet the ANSI T1 403 requirements for pulse density Bit 5 Change of Frame Alignment Event COFA Set when the last resync resulted in a change of frame or multiframe alignment Bit 4 Eight Zero Detect Event 8ZD Set when a string of at least eight consecutive Os regardless of the length of the stri
391. this register value during packet error insertion Bits 5 6 Transmit FCS Append Disable TFAD This bit controls whether or not an FCS is appended to the end of each packet When equal to 0 the calculated FCS bytes are appended to packets When set to 1 packets are transmitted without FCS In X 86 Mode FCS is always 32 bits and is always appended to the packet Bit 4 Transmit FCS 16 Enable TF16 When 0 the FCS processing uses a 32 bit FCS When 1 the FCS processing uses a 16 bit FCS In X 86 Mode 32 bit FCS processing is always enabled regardless of this bit Bit 3 Transmit Bit Synchronous Inter frame Fill Value TIFV When 0 inter frame fill is done with the flag sequence 7Eh When 1 inter frame fill is done with all 1 s FFh This bit is ignored X 86 mode and the interframe flag is always 7E Bit 2 Transmit Scrambling Disable TSD When equal to 0 1 scrambling is performed When set to 1 scrambling is disabled Bit 1 Transmit Bit Reordering Enable TBRE When equal to 0 bit reordering is disabled The first bit transmitted is from the MSB of the transmit FIFO byte TFD 7 When set to 1 bit reordering is enabled The first bit transmitted is from the LSB of the transmit FIFO byte TFD 0 Bit 0 Transmit Initiate Automatic Error Insertion TIAEI This write only bit initiates error insertion See the LI TEPHC register definition for details of usage 152 of 344 DS33R11 Ethernet Ma
392. threshold is exceeded the DS33R11 will send a pause frame with the timer value programmed by the user See Table 9 6 for more information It is recommended that 80 slots 80 by 64 bytes or 5120 bytes be used as the standard timer value The pause frame causes the distant transmitter to pause for a time before starting transmission again The pause command has a multicast address 01 80 62 00 00 01 The high and low thresholds for the receive queue are configurable by the user but it is recommended that the high threshold be set approximately 96 packets from the maximum size of the queue and the low threshold 96 packets lower than the high threshold The DS33R11 will send a pause frame as the queue has crossed the high threshold and a frame is received Pause is sent every time a frame is received in the high threshold state Pause control will only take care of temporary congestion Pause control does not take care of systems where the traffic throughput is too high for the queue sizes selected If the flow control is not effective the receive queue will eventually overflow This is indicated by SU QCRLS RQOVFL latched bit If the receive queue is overflowed any new frames will not be received The user has the option of not enabling automatic flow control In this case the thresholds and corresponding interrupt mechanism to send pause frame by writing to flow control busy bit in the MAC flow control registers SU MACFCR FCB SU GCR JAME and SU MACFCR
393. time a frame is transmitted this counter is incremented by 1 This counter resets only upon device reset does not saturate and rolls over to zero upon reaching the maximum value The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2 32 1 times at the maximum frame rate The user should store the value from the beginning of the measurement period for later calculations and take into account the possibility of a roll over to occurring 196 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description SU TxBytesCtr All Bytes Transmitted Counter Register Address 0308h indirect 0308h Bit 31 30 29 28 27 26 25 24 Name TXBYTEC31 TXBYTEC30 TXBYTEC29 TXBYTEC28 TXBYTEC2 TXBYTEC26 TXBYTEC25 TXBYTEC24 Default 0 0 0 0 0 0 0 0 0309h Bit 4 23 22 21 20 19 18 17 16 Name TXBYTEC23 TXBYTEC22 TXBYTEC21 TXBYTEC20 19 18 TXBYTEC16 Default 0 0 0 0 0 0 0 0 030Ah Bit 4 15 14 13 12 11 10 09 08 Name TXBYTEC15 14 12 11 TXBYTEC10 TXBYTEC9 TXBYTEC8 Default 0 0 0 0 0 0 0 0 030Bh Bit 07 06 05 04 03 02 01 00 Name TXBYTEC7 TXBYTEC6 TXBYTEC5 TXBYTEC4 TXBYTEC3 TXBYTEC2 TXBYTEC
394. tion The TR PCVCR is disabled during receive loss of synchronization RLOS 1 conditions Table 10 7 shows what errors the TR PCVCR counts Table 10 7 T1 Path Code Violation Counting Arrangements COUNTED 2 FRAMING MODE COUNT Fs ERRORS IN THE PCVCRs D4 Errors in the Ft pattern D4 Errors in both the Ft and Fs patterns Errors in the CRC6 codewords In E1 mode the path code violation count register records CRC4 errors Since the maximum CRC4 count in a one second period is 1000 this counter cannot saturate The counter is disabled during loss of sync at either the FAS or CRC4 level it continues to count if loss of multiframe sync occurs at the CAS level Path code violation count register 1 TR PCVCR1 is the most significant word and TR PCVCR2 is the least significant word of a 16 bit counter that records path violations PVs 79 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 10 7 3 Frames Out of Sync Count Register TR FOSCR In T1 mode TR FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync This number is useful in ESF applications needing to measure the parameters loss of frame count LOFC and ESF error events as described in AT amp T publication TR54016 When TR FOSCR is operated in this mode it is not disabled during receive loss of synchronization RLOS 1 conditions TR FOSCR has an alternate operating mode whereby it counts either errors in the Ft fr
395. tions See Section 10 18 for details 0 SLC 96 disabled 1 SLC 96 enabled Bit 3 Receive FDL Zero Destuffer Enable RZSE Set this bit to 0 if using the internal HDLC BOC controller instead of the legacy support for the FDL See Section 10 17 for details 0 zero destuffer disabled 1 7 zero destuffer enabled Bit 2 Reserved Set to zero for proper operation Bit 1 Receive Japanese CRC6 Enable RJC 0 use ANSI AT amp T ITU CRC6 calculation normal operation 1 use Japanese standard 6704 CRC6 calculation Bit 0 Receive Side D4 Yellow Alarm Select RD4YM 0 Os in bit 2 of all channels 1 a 1 in the S bit position of frame 12 J1 Yellow Alarm Mode 205 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR T1TCR1 Register Description T1 Transmit Control Register 1 Register Address 05h Bit 7 6 5 4 3 2 1 0 Name TJC TFPT TCPT TSSE GB7S TFDLS TBL TYEL Default 0 0 0 0 0 0 0 0 Bit 7 Transmit Japanese CRC6 Enable TJC 0 use ANSI AT amp T ITU CRC6 calculation normal operation 1 use Japanese standard JT G704 CRC6 calculation Bit 6 Transmit F Bit Pass Through TFPT 0 F bits sourced internally 1 F bits sampled at TSERI Bit 5 Transmit CRC Pass Through TCPT 0 7 source CRC6 bits internally 1 CRC6 bits sampled at TSERI during F bit time Bit 4 Transmit Software Signaling Enable TSSE 0 do not source signaling data from the TR TSx registers regar
396. tors Typically two of the detectors are used for loop up and loop down code detection The user programs the codes to be detected in the receive up code definition TR RUPCD1 and TR RUPCD2 registers and the receive down code definition TR RDNCD1 and TR RDNCD2 registers and the length of each pattern is selected through the TR IBCC register There is a third detector spare that is defined and controlled through the TR RSCD1 TR RSCD2 and TR RSCC registers When detecting a 16 bit pattern both receive code definition registers are used together to form a 16 bit register For 8 bit patterns both receive code definition registers are filled with the same value Detection of a 1 2 3 4 5 6 and 7 bit pattern only requires the first receive code definition register to be filled The framer detects repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E 2 The detectors are capable of handling both F bit inserted and F bit overwrite patterns Writing the least significant byte of the receive code definition register resets the integration period for that detector The code detector has a nominal integration period of 36ms Hence after about 36ms of receiving a valid code the proper status bit LUP at TR SR3 5 LDN at TR SR3 6 and LSPARE at TR SR3 7 is set to a 1 Normally codes are sent for a period of five seconds It is recommended that the software poll the framer every 50ms to 1000ms u
397. ts portion of a time slot or to FDL T1 or Sa bits E1 Each controller has 128 byte FIFOs thus reducing the amount of processor overhead required to manage the flow of data In addition built in support for reducing the processor time is required in SS7 applications The backplane interface provides a versatile method of sending and receiving data from the host system Elastic stores provide a method for interfacing to asynchronous systems converting from a T1 E1 network to 2 048 2 4 096MHz 8 192MHz or N x 64kHz system backplane The elastic stores also manage slip conditions asynchronous interface An 8 bit parallel microcontroller port provides access for control and configuration of all the features of the device The internal 100MHz SDRAM controller interfaces to a 32 bit wide 128Mb SDRAM The SDRAM is used to buffer the data from the Ethernet and WAN ports for transport The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes Diagnostic capabilities include SDRAM BIST loopbacks PRBS pattern generation detection and 16 bit loop up and loop down code generation and detection The DS33R11 operates with a 1 8V core supply and 3 3V I O supply 9 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver The integrated Ethernet Mapper is software compatible with the 0533711 Ethernet mapper There are a few things to note when porting a 05332711 application to this device The S
398. ts indicate the number of packets extracted from the Transmit FIFO and output in the outgoing data stream 156 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name Register Description LI TBCRO Transmit Byte Count Byte 0 Register Address 0DOh Bit 7 6 5 4 3 2 1 0 Name TBC6 TBC5 TBC4 2 TBC1 TBCO Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Byte Count TBC 0 7 Eight bits of 32 bit value Register description below Register Name LI TBCR1 Register Description Transmit Byte Count Byte 1 Register Address 0D1h Bit 7 6 5 4 3 2 1 0 Name TBC15 TBC14 TBC13 TBC12 TBC11 TBC10 TBC9 TBC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Byte Count TBC 15 8 Eight bits of 32 bit value Register description below Register Name LI TBCR2 Register Description Transmit Byte Count Byte 2 Register Address 0D2h Bit 7 6 5 4 3 2 1 0 Name TBC23 TBC22 TBC21 TBC20 TBC19 TBC18 TBC17 TBC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Byte Count TBC 23 16 Eight bits of 32 bit value Register description below Register Name LI TBCR3 Register Description Transmit Byte Count Byte 3 Register Address 0D3h Bit 7 6 5 4 3 2 1 0 Name TBC31 TBC30 TBC29 TBC28 TBC27 TBC26 TBC25 TBC24 Default 0 0 0 0
399. ttings in Receive Frame Rejection Control register SU RFRC The user can program whether to reject or accept frames with the following errors e MII error asserted during the reception of the frame e Dribbling bits occurred in the frame e CRC error occurred e Length error occurred the length indicated by the frame length is inconsistent with the number of bytes received e Control frame was received The mode must be full duplex e Unsupported control frame was received Note that frames received that are runt frames or frames with collision will automatically be rejected Table 9 5 Registers Related to Setting the Ethernet Port REGISTER NAME FUNCTION Transmit Frame Resend This register determines if the current frame is retransmitted SU TFRC Control due to various transmit errors Transmit Frame Status Low and Transmit Frame Status High SU TFSL and These two registers provide the real time status of the SU TFSH transmit frame Only apply to the last frame transmitted Receive Frame Status Byte 0 These registers provide the real time status for the received SU RFSBO to 3 to 3 frame Only apply to the last frame received Receive Frame Rejection SU RFRC This register provides settings for reception or rejection of Control frame based on errors detected by MAC Receiver Maximum Frame High and Receiver Maximum Frame Low SU RMFSRH and The settings for this register provide the maximum s
400. ture Test Access Port TAP Bypass Register TAP Controller Boundary Scan Register Instruction Register Device Identification Register The Test Access Port has the necessary interface pins JTRST JTCLK JTMS JTDI and See the descriptions for details Refer to IEEE 1149 1 1990 IEEE 1149 1a 1993 and IEEE 1149 1b 1994 for details about the Boundary Scan Architecture and the Test Access Port Figure 14 1 JTAG Functional Block Diagram Boundary Scan Register Identification Register Bypass Register Instruction Register Test Access Port 336 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 14 1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK See Figure 14 2 for a diagram of the state machine operation Test Logic Reset Upon power up the TAP Controller is in the Test Logic Reset state The Instruction register will contain the IDCODE instruction All system logic of the device will operate normally Run Test Idle
401. uffering is required SDATA 19 Y19 SDATA 20 V19 SDATA 21 Y20 SDATA 22 U19 SDATA 23 W20 SDATA 24 U20 SDATA 25 T19 SDATA 26 T20 SDATA 27 Y18 SDATA 28 W19 SDATA 29 V17 SDATA 30 W17 SDATA 31 W16 SDA 0 W14 SDA 1 W12 SDA 2 Y15 SDRAM Address Bus 0 to 11 The 12 pins of the SDRAM address SDA 3 W15 bus output the row address first followed by the column address SDA 4 Y14 The row address is determined by SDAO to SDA11 at the rising SDA 5 V13 edge of clock Column address is determined by SDAO SDA9 and SDA 6 W13 SDA11 at the rising edge of the clock SDA10 is used as an auto SDAI7 Y12 precharge signal SDAI8 V12 Note All SDRAM operations are controlled entirely by the 110 DS33R11 No user programming for SDRAM buffering is required SDA 11 W11 SDMASKIT M SDRAM Mask 0 through 3 When high a write is done for that SDMASK 2 V16 byte The least significant byte is SDATA7 to SDATAO The most SDMASK 5 15 significant byte is SDATA31 to SDATA24 SDRAM CLK Out System clock output to the SDRAM This clock Y 4 is a buffered version of SYSCLKI 30 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION T1 E1 J1 ANALOG LINE INTERFACE TTIP R1 R2 Transmit Analog Tip Output for the T1 E1 J1 Transceiver Analog line driver outputs Two connections are provided to improve signal quality These pins connect via a 1 2 st
402. ulation of a flag or abort sequence by the data pattern The receiver automatically removes destuffs any 0 after five 1s in the message field 0 7 enable the zero stuffer normal operation 1 7 disable the zero stuffer Bit 0 Transmit CRC Defeat TCRCD A 2 byte CRC code is automatically appended to the outbound message This bit can be used to disable the CRC function 0 enable CRC generation normal operation 1 disable CRC generation 265 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1FC TR H2FC Register Description HDLC 1 FIFO Control HDLC 2 FIFO Control Register Address 91h Ath Bit 7 6 5 4 3 2 1 0 Name TFLWM2 TFLWM1 TFLWMO RFHWM2 RFHWM1 RFHWMO Defaut 9 o 9 o 9 o Bits 3 5 Transmit FIFO Low Watermark Select TFLWMO to TFLWM2 TFLWM2 TFLWM1 TFLWMO Transmit FIFO Watermark bytes 0 0 0 4 2 0 1 16 D 1 0 32 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 Bits 0 2 Receive FIFO High Watermark Select RFHWM0 to RFHWM2 RFHWM2 RFHWMO Receive FIFO Watermark bytes 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 266 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Register Name TR H1RCS1 TR H1RCS2 TR H1RCS3 TR H1RCS4 TR H2RCS1 TR H2RCS2 TR H2RCS3 TR
403. un UR When this bit is set to 1 the frame was aborted due to a data under run condition of the transmit buffer Bit 6 Excessive Collisions EC When this bit is set to 1 a frame has been aborted after 16 successive collisions while attempting to transmit the current frame If the Disable Retry bit is set to 1 then Excessive Collisions will be set to 1 after the first collision Bit 5 Late Collision LC When this bit is set to 1 a frame was aborted by collision after the 64 bit collision window Not valid if an under run has occurred Bit 4 Excessive Deferral ED When this bit is set to 1 a frame was aborted due to excessive deferral Bit 3 Loss Of Carrier LOC When this bit is set to 1 a frame was aborted due to loss of carrier for one or more bit times Valid only for noncollided frames Valid only in half duplex operation Bit 2 No Carrier NOC When this bit is set to 1 a frame was aborted because no carrier was found for transmission Bit 1 Reserved Bit 0 Frame Abort FABORT When this bit is set to 1 the MAC has aborted a frame for one of the above reasons When this bit is clear the previous frame has been transmitted successfully Register Name SU TFSH Register Description Transmit Frame Status High Register Address 153h Bit 7 6 5 4 3 2 1 0 Name PR HBF CC2 CC1 CCO LCO DEF Default 0 0 0 0 0 0 0 0 Bit 7 Packet Resend PR When this bit is set the current packe
404. up of time slots portion of a time slot or to FDL T1 or Sa bits E1 Each controller has 128 byte FIFOs thus reducing the amount of processor overhead required to manage the flow of data In addition built in support for reducing the processor time is required in SS7 applications The backplane interface provides a versatile method of sending and receiving data from the host system Elastic stores provide a method for interfacing to asynchronous systems converting from a T1 E1 network to 2 048MHz 4 096MHz 8 192MHz or N x 64kHz system backplane The elastic stores also manage slip conditions asynchronous interface 8 1 Processor Interface Microprocessor control of the DS33R11 is accomplished through the interface pins of the microprocessor port The 8 bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC 1 0 pins When MODEC 1 0 00 bus timing is in Intel mode as shown in Figure 13 9 and Figure 13 10 When MODEC 1 0 01 bus timing is in Motorola mode as shown in Figure 13 11 and Figure 13 12 The address space is mapped through the use of 10 address lines AO A9 Multiplexed Mode is not supported on the processor interface See the timing diagrams in AC Electrical Characteristics in Section 13 for more details The Chip Select CS pin must be brought to a logic low level to gain read and write access to the microprocessor port With Intel timing selected the Read RD and Write WR
405. uracy of 32ppm for T1 interfaces The clock can be sourced internally from RCLKO or JACLK See TR LIC2 3 TR LIC4 4 and TR LIC4 5 for details Because of the nature of the transmitter s design very little jitter less than 0 005Ulp p broadband from 10Hz to 100kHz is added to the jitter present on TCLKT Also the waveforms created are independent of the duty cycle of TCLKT The transmitter in the device couples to the E1 or T1 transmit twisted pair or coaxial cable in some E1 applications through a 1 2 step up transformer For the device to create the proper waveforms the transformer used must meet the specifications listed in Table 10 13 The device has the option of using software selectable transmit termination The transmit line drive has two modes of operation fixed gain or automatic gain In the fixed gain mode the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude In the automatic gain mode the transmitter adjusts its output level to compensate for slight variances in the network load See the Transmit Line Build Out Control TR TLBC register for details 10 20 3 1 Transmit Short Circuit Detector Limiter The device has an automatic short circuit limiter that limits the source current to 50mA RMS into 10 load This feature be disabled by setting the SCLD bit TR LIC2 1 1 TCLE TR INFO2 5 provides a real time indication of when the current limiter is activated If the current li
406. using MII mode with DTE operation the MII clocks RX CLK and TX CLK are inputs that are expected to be provided by the external PHY While using MII mode with DCE operation the MII clocks TX CLK and RX CLK are output by the DS33R11 and are derived from the 25MHz REF input More information on MII mode can be found in Section 9 15 1 9 1 2 Serial Interface Clock Modes The serial interface timing is determined by the line clocks Both the transmit and receive clocks TCLKE and RCLKI are inputs and can be gapped 45 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 2 Resets and Low Power Modes The external RST pin and the global reset bit in GL CR1 create an internal global reset signal The global reset signal resets the status and control registers on the chip except the GL CR1 RST bit to their default values and resets all the other flops to their reset values The processor bus output signals are also placed in high impedance mode when the RST pin is active low The global reset bit GL CR1 RST stays set after a one is written to it but is reset to zero when the external RST pin is active or when a zero is written to it Allow 5ms after initiating a reset condition for the reset operation to complete The Serial Interface reset bit in LI RSTPD resets all the status and control registers on the serial interface to their default values except for the LI RSTPD RST bit The serial interface includes the
407. utput an internally generated clock to the Ethernet PHY The output clocks are generated by internal division of REF CLK In mode only the REF input is used REF CLKO is an output clock that is generated by dividing the 100MHz System clock SYSCLKI by 2 or 4 A Management Data Clock MDC output is derived from SYSCLKI and is used for information transfer between the internal Ethernet MAC and external PHY The MDC clock frequency is 1 67 2 Clocking of the integrated T1 E1 J1 tansceiver is discussed in Section 10 1 The following table provides the different clocking options for the Ethernet interface Table 9 1 Clocking Options for the Ethernet Interface RMINIS SPEED DCEDTE Resor TX O MI 10 Mbps DTE 25MHz eee O MI 10 Mbps DCE 25MHz pe 1 67MHz O MI 100 Mbps DCE 25MHz 2 ONU COUR 1 67MHz 1 10 Mbps E 50MHz 4 nem 1 67MHz 1 RMII 100 Mbps 50MHz Nos mom mum 1 67MHz 43 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver Figure 9 1 Clocking for the DS33R11 OVW LANYSHLA HJTIOH LNOO 98 lHOd 7143 LINSNV L 143g LANYSAHLA 98 X O 10H H3AISOSNVHL
408. utput from the Transmit Packet Processor to the Transmit Serial Interface is a serial data stream bit synchronous mode HDLC processing can be disabled clear channel enable Disabling HDLC processing disables FCS processing packet error insertion stuffing packet abort sequence insertion and inter frame padding Only bit reordering and packet scrambling are not disabled Bit reordering changes the bit order of each byte If bit reordering is disabled the outgoing 8 bit data stream DT 1 8 with DT 1 being the MSB and DT 8 being the LSB is output from the Transmit FIFO with the MSB in TFD 7 or 15 23 or 31 and the LSB in or 8 16 or 24 of the transmit FIFO data TFD 7 0 15 8 23 16 or 31 24 If bit reordering is enabled the outgoing 8 bit data stream DT 1 8 is output from the Transmit FIFO with the MSB TFD 0 and the LSB in TFD 7 of the transmit FIFO data TFD 7 0 In bit synchronous mode DT 1 is the first bit transmitted FCS processing calculates an FCS and appends it to the packet FCS calculation is a CRC 16 or CRC 32 calculation over the entire packet The polynomial used for FCS 16 is x6 x x 1 The polynomial used for FCS 32 is x x7 x x7 x19 x XT x X9 x x x x 1 The FCS is inverted after calculation The FCS type is programmable If FCS append is enabled the calculated FCS is appended to the packet If FCS append is disabled the packet is transmitted without an FCS The FC
409. w the incoming data stream bit and the receive pattern generator output bit did not match When 1 the receive pattern generator will not automatically resynchronize to the incoming pattern Note Automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the Sync state Bit 1 Transmit New Pattern Load TNPL A zero to one transition of this bit will cause the programmed test pattern QRSS PTS PLF 4 0 PTF 4 0 and BSP 31 0 to be loaded in to the transmit pattern generator This bit must be changed to zero and back to one for another pattern to be loaded Note QRSS PTS PLF 4 0 PTF 4 0 and BSP 31 0 must not change from the time this bit transitions from 0 to 1 until four TCLKE clock cycles after this bit transitions from O to 1 Bit 0 Transmit Pattern Inversion Control TPIC When 0 the transmit outgoing data stream is not altered When 1 the transmit outgoing data stream is inverted 144 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver BPCLR BERT Pattern Configuration Low Register Register Name Register Description Register Address 82h Bit 7 6 5 4 3 2 1 0 Name QRSS PTS PLF4 PLF3 PLF2 PLF1 PLFO Default 0 0 0 0 0 0 0 0 Bit 6 QRSS Enable QRSS When 0 the pattern generator configuration is controlled by PTS PLF 0 4 and PTF 0 4 and BSP 0 31 When 1 the pattern generator configuration is forced to a QRS
410. well as CSU line build outs of 7 5dB 15dB and 22 5dB E1 waveform generation includes G 703 waveshapes for both 750 coax and 1200 twisted cables The receive interface provides network termination and recovers clock and data from the network The receive sensitivity adjusts automatically to the incoming signal and can be programmed for OdB to 43dB or OdB to 12dB for E1 applications and OdB to 15dB or OdB to 36dB for T1 applications The jitter attenuator removes phase jitter from the transmitted or received signal The crystal less jitter attenuator requires only a 2 048MHz MCLK for both E1 and T1 applications with the option of using a 1 544MHz MCLK in T1 applications and can be placed in either transmit or receive data paths More information on microprocessor control is available in Section 8 1 19 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 6 BLOCK DIAGRAMS Figure 6 1 Main Block Diagram RMII MODE OVW LANYSHL gt A HJTIOHINOO ARBITER 98 X O 10H 98 X O 10H l332Vd Y lHOd 7143 LINSNVYL 143g H3AISOSNVHL SDRAM PORT lHOd 7145 JAI3O3H 2 lt 3IAI3O3H cj gt lt 2
411. write operation RW must be set high for a register read cycle and low for a register write cycle 25 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION Read Data Strobe Intel Mode The DS33R11 drives the data bus 00 07 with the contents of the addressed register while RD and CS are both low B11 20 J Data Strobe Motorola Mode Used to latch data through the microprocessor interface DS must be low during read and write operations Chip Select for Protocol Conversion Device This pin must be CS A11 taken low for read write operations When CS is high the RD DS and WR signals are ignored Chip Select for the T1 E1 J1 Transceiver Must be low to read or CST D7 write the T1 E1 J1 transceiver Interrupt Output Outputs a logic zero when an unmasked interrupt event is detected INT is deasserted when all interrupts OZ have been acknowledged and serviced Active low Inactive state is programmable in register GL CR1 is deasserted when all interrupts have been acknowledged and serviced Active low Inactive state is programmable in register GL CR1 26 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver NAME PIN TYPE FUNCTION MII RMII PHY PORT COL DET N18 Collision Detect MII Asserted by the MAC PHY to indicate that a collision is occurring In DCE Mode
412. ytes Available The lower 7 bits of the receive packet bytes available register indicates the number of bytes 0 through 127 that can be read from the receive FIFO The value indicated by this register lower seven bits informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message This value refers to one of four possibilities the first part of a packet the continuation of a packet the last part of a packet or a complete packet After reading the number of bytes indicated by this register the host then checks the HDLC information register for detailed message status If the value in the TR HxRPBA register refers to the beginning portion of a message or continuation of a message then the MSB of the TR HxRPBA register returns a value of 1 This indicates that the host can safely read the number of bytes returned by the lower seven bits of the TR HxRPBA register but there is no need to check the information register since the packet has not yet terminated successfully or otherwise 10 16 5 1 Receive HDLC Code Example The following is an example of a receive HDLC routine 1 Reset receive HDLC controller 2 Set HDLC mode mapping and high watermark 3 Start new message buffer 4 Enable RPE and RHWM interrupts 5 Wait for interrupt 6 Disable RPE and RHWM interrupts 7 Read TR HxRPBA register TR HxRPBA lower 7 bits are byte count MSB is status 8 Read N and 7Fh bytes f
413. ze AR RQSC1 must be 02h or greater The receive queue high threshold SU RQHT must be set to 01h or greater but must be less than the queue size If the high threshold is set to the same value as the queue size automatic flow control will not be effective The high threshold must always be set to less than the corresponding queue size The following table provides all the options on flow control mechanism for DS33R11 Table 9 4 Options for Flow Control TYPE MODE Half Duplex Full Duplex Configuration Halt Duplex Automatic Flow Pell Duplex Manuel Automatic Flow Flow Control Flow Control Control Control ATFLOW Bit 0 1 0 1 JAME Bit Controlled By User N A N A Automatically FCB Bit Controlled Pause N A N A Controlled by User Automatically Controlled Controlled FCE Bit Controlled By User Automatically Controlled By User Automatically Pause Timer N A N A Programmed by User Programmed by User 53 of 344 DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 9 13 1 Full Duplex Flow Control Automatic flow control is enabled by default The host processor can disable this functionality with SU GCR ATFLOW The flow control mechanism is governed by the high watermarks SU RQHT The SU RQLT low threshold can be used as indication that the network congestion is clearing up The value of SU RQLT does not affect the flow control When the connection queue high

Maxim DS33R11 Switch User Manual

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