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Kodak 800 SERIES Camcorder User Manual

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1. AGP DRAM Control Internal DRAM Control AGP Bridge Host Bridge Graphics Host Bridge Master Bus 0 Bus 0 Bus 0 Bus 0 Dev 1 Dev 0 Dev 2 Dev 0 Hub Interface Hub Interface Hub Interface 0 Logical PCI Bus 0 ICH Hub Interface PCI Hub I F PCI Devices LPC Device Bridge P2P Bus 0 PBus 0 Dev 31 Dev 30 F Fcn 0 Primary PCI Fen 0 Bus B programmable Logical PCI Bus 0 2 3 1 Multi Mode Capability Requirements There are multiple Device Modes that are supported by the three PCI devices within this component 1 AGP Mode The AGP slot is populated with an AGP graphics card and the AGP interface device is active The internal graphics controller is inactive GFX Mode with Local Memory The internal graphics device is active The AGP slot is populated with a GPA card and the AGP interface device is inactive GFX Mode with Shared Memory The internal graphics device is active The AGP slot is not populated with a GPA card or an AGP graphics card and the AGP interface device is inactive PCI Mode The internal graphics controller and the AGP interface device are both inactive The display data cycles are routed through the hub interface to the PCI display device 2 3 1 1 Supported Single Monitor and Multi monitor Configurations For modern operating systems that have multiple monitor support the primar
2. 355 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Descriptions Display Color Mode 0000 CRT standard VGA text and graphics mode and 1 bit 2 bit 4 bit packed graphics mode Default 0001 Reserved 0010 CRT 8 bit packed extended graphics mode 0011 Reserved 0100 CRT 16 bit packed 5 5 5 extended graphics mode Targa compatible 0101 CRT 16 bit packed 5 6 5 extended graphics mode XGA compatible 0110 CRT 24 bit extended graphics mode compressed 0111 CRT 24 bit extended graphics mode uncompressed In this mode pixels are stored only on the lower three bytes plane 0 1 2 of each double word and the most significant byte of each double word plane 3 is not used Hardware Cursor Display Enable Software should always set this bit to 1 The setting of this bit to 1 should not do any harm even while in VGA mode 0 Disable default 1 Enable Enable Extended Status Read Mode 0 Disable default 1 With this bit enabled the status of the internal state machines and values of the red and green data in the input holding register through the normal DAC register ports is available The register ports are redefined as follows when this bit is set DACMASK Returns red input data holding value DACWX Returns green input data holding value DACSTATE Returns the status of the internal state machines in bits 7 2 CRT Overscan Color 0 Disable default 1 Enable Protected
3. Intel 815 Chipset Graphics Controller PRM Rev 1 0 monochrome BLT operand following the BLT_TEXT command The BLT engine will receive this data through the command stream and use it as the source data for this BLT operation The BLT engine will be set to the same color depth as the graphics system 8 bits per pixel in this case Since the source data in this BLT operation is monochrome color expansion must be used to convert it to an 8 bpp color depth To ensure that the gray background behind this letter f is preserved per pixel write masking will be performed using the monochrome source data as the pixel mask The BLT Setup and Text command packets are used to select the features to be used in this BLT operation Only the fields required by these two command packets must be programmed carefully The BLT engine ignores all other registers and fields The source select field must be set to 1 to indicate that the source data is provided by the host processor through the IMMEDIATE_BLT command packet Finally the raster operation field should be programmed with the 8 bit value CCh to select the bit wise logical operation that simply copies the source data to the destination Selecting this bit wise operation in which no pattern data is used as an input causes the BLT engine to automatically forego reading pattern data from the frame buffer The Setup Pattern Source Expansion Foreground Color Register to specify the color with which
4. 262 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Post Divisor Select clock 2 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 default 101 Divide by 32 11x Reserved VCO Loop Divide clock 2 0 Divided by 4 M default 1 Divided by 16 M 14 12 Post Divisor Select clock 1 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 default 101 Divide by 32 11x Reserved VCO Loop Divide clock 1 0 Divided by 4 M default 1 Divided by 16 M Post Divisor Select clock 0 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 default 101 Divide by 32 11x Reserved VCO Loop Divide clock 0 0 Divided by 4 default 1 Divided by 16 263 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 14 7 PWR_CLKC Power Management and Miscellaneous Clock Control Address Offset 6014h 06017h Default Value 0000 0101 h Attribute R W Size 32 bits 31 17 16 Reserved 15 12 11 10 9 8 Reserved 1 0 7 2 Reserved Display Internal Clock PLL DAC VCO Enable as 1 Display Clock PLL VCO 0 Enable default 1 Disable Internal DAC Enable 0 Disables the internal DAC PowerDown If HSYNC VSYNCControl 0 0 disables HSYNC and VSYNC 1 Enables the internal DAC and does not allow disable of HSYN
5. 47 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 5 6 Saving the Hardware State Note that the VGA register unlocking protocol must be performed in order to access some of the registers described below During a state change the driver should preserve the following registers to provide complete state restoration in the future e IO Control CR80 e Address Mapping GR10 e Bit Blit Control MM 0x7000C e Video Clock 2 M MM 0x6008 e Video Clock 2 N MM 0x600C e Video Clock 2 Divisor Select MM 0x6012 e Vertical Total CRX 30 e Vertical Display End CRX 31 e Vertical Sync Start CRX 32 e Vertical Blank Start CRX 33 e Horizontal Total CRX 35 e Horizontal BInk CRX 39 e Ext Offset CRX 41 e Interlace Control CRX 70 e Hardware Status Mask Register MM 0x2098 e Interrupt Enable Register MM 0x20A0 e Interrupt Identity Register MM 0x20A4 e Interrupt Mask Register MM 0x20A8 e Error Mask Register MM 0x20B4 e Display Control Register MM 0x70008 e Pixel Pipeline Configuration 0 Register MM 0x70009 e Pixel Pipeline Configuration 1 Register MM 0x7000A e Pixel Pipeline Configuration 2 Register MM 0x7000B e Watermark and Burstlength Control MM 0x20D8 e Low priority ring information MM 0x2030 0x203F 48 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Restoring the Hardware State The graphics adapter state should be restored by performing the following steps Note some of the synchronization operation
6. 70 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description SMM Space Locked D_LCK When D_LCK is set to 1 then D_LCK GMS USMM and the most significant bit of LSMM become read only D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a reset The combination of D_LCK and LSMM provide convenience with security The BIOS can use LSMM 071 to initialize SMM space and then use D_LCK to lock down SMM space in the future so that no application software or BIOS itself can violate the integrity of SMM space even if the program has knowledge of the LSMM function This bit also Locks the DRP and DRP2 registers E_SMRAM_ERR E_SMERR This bit is set when processor accesses the defined memory ranges in Extended SMRAM HSEG or TSEG while not in SMM mode It is software s responsibility to clear this bit The software must write a 1 to this bit to clear it This bit is Not set for the case of an Explicit Write Back operation Initialization and Usage of Stolen Memory SMRAM Register Bits 7 4 control the theft of memory from Main Memory space for use as Graphics Local Memory and SMM TSEG memory The blocks of memory selected by these fields are NOT accessible as general system RAM When Bit 5 of the SMRAM register is a 1 the TSEG segment of memory can ONLY be accessed by the processor in SMM mode No other agent can access this memory Therefore BIOS should initialize this b
7. 9 4 5 AR12 Memory Plane Enable Register I O and Memory Offset Address Read at 3C1h and Write at 3COh index 12h Default O00UU UUUUb U Undefined Attributes Read Write 7 6 5 4 3 2 1 0 Reserved 00 Video Status Mux Enable Enable Enable Enable Plane 3 Plane 2 Plane 1 Plane 0 5 o e Reserved Read as Os Video Status Mux These 2 bits are used to select 2 of the 8 possible palette bits P7 P0 to be made available to be read via bits 5 and 4 of the Input Status Register 1 ST01 The table below shows the possible choices Bit 5 4 ST01 Bit 5 ST01 Bit 4 00 P2 default PO default 01 P5 P4 10 P3 P1 11 P7 P6 These bits are typically unused by current software they are provided for EGA compatibility Enable Plane 3 0 These 4 bits individually enable the use of each of the 4 memory planes in providing 1 of the 4 bits used in video output to select 1 of 16 possible colors from the palette to be displayed 0 Disable the use of the corresponding memory plane in video output to select colors forcing the bit that the corresponding memory plane would have provided to a value of 0 1 Enable the use of the corresponding memory plane in video output to select colors Note AR12 is referred to in the VGA standard as the Color Plane Enable Register The words plane color plane display memory plane and memory map have been all been used in IBM literature on the VGA standard to describe the 4 se
8. 0 ccceeeeeeeeeseeeeeesneeeeeenaes 280 15 4 4 Overlay Destination Window Position Size Registers cceeeeeee 281 15 4 4 1 DWINPOS Destination Window Position Register 0 281 15 4 4 2 DWINSZ Destination Window Size Register eeee 281 15 4 5 Overlay Source Size ReGiSters ce ceececeeeeeeeeeeeeeneeeeeteteeeeetiaeeeeetneeeeee 282 15 4 5 1 SWID Source Width Register eeceeeeeeeeeeeeteeeeeeenteeeeeeaes 282 15 4 5 2 SWIDQW Source Width In QWords Register eeeeeee 283 15 4 5 3 SHEIGHT Source Height Register eceeeesseeeeeesteeeeeenaes 284 15 4 6 Overlay Scale Factor ReGisters cccccceeceeeeeeeeteeeeseaeeeeeeneeeeeeneeeereaa 285 15 4 6 1 YRGBSCALE Y RGB Scale Factor Register eeeeee 285 15 4 6 2 UVSCALE UV Scale Factor Register 286 15 4 7 Overlay Color Correction ReQiSters ccceececeesteeeeeeeneeeeeeteeeeeetnaeeeeees 287 15 4 7 1 OVOCLRCO Overlay 0 Color Correction 0 Register 0 287 15 4 7 2 OVOCLRC1 Overlay 0 Color Correction 1 Register 0 00 287 15 4 8 Overlay Destination Color Key Registers cceececceeesetreeeeseteeeeetteeeees 288 15 4 8 1 DCLRKV Destination Color Key Value Register e 288 15 4 8 2 DCLRKM Destination Color Key Mask Register e 289 15 4 9 Overlay Source Color Key Registers 0 ccccccceeeseeeeeestneeeeestieeeeetnieeeeees 290
9. 13 1 1 13 1 2 The GC shall support both D3D and OGL notations The selection can be done in the GFXRENDERSTATE_RASTER_ RULE state variable Axis Aligned Rectangles Axis aligned rectangles are described by three vertices as shown in the adjacent figure The vertices should always describe a right triangle where the base of the triangle is parallel to the x axis and the vertical leg of the triangle is parallel to the y axis Primitive Winding Order The winding order of the vertices is considered if Primitive Culling is enabled In the example above the winding order is clock wise In triangle strip the winding order toggles on every triangle e g CW CCW CW CCW and so on Therefore hardware toggles the culling orientation on every triangle to match up with the strip sequence If the primitive type is triangle strip culling orientation is toggled on the 2 4 6 triangle and so on If the primitive type is triangle strip with reverse winding order culling orientation is toggled on the 1 3 5 triangles and so on 205 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 1 3 13 1 4 13 1 5 206 intel Position Mask In Variable vertex format a position mask is sent to indicate the present of X Y Z and 1 W parameters If 1 W RHW is declared not present in the vertex packet hardware forces 1 w equal to 1 In the case Z is declared not present the Z value of the last triangle from
10. 16 Adrs 32 32 Adrs 64 64 Adrs 128 128 Adrs 192 192 For X 5 Result 0 8 0 5 lt lt 4 gt gt 7 5 For X 11 Result 8 16 8 3 lt lt 4 gt gt 7 1 For X 24 Result 16 32 16 8 lt lt 3 gt gt 7 24 For X 63 Result 31 64 32 31 lt lt 2 gt gt 7 63 For X 100 Result 64 128 64 36 lt lt 1 gt gt 7 100 For X 156 Result 128 192 128 28 lt lt 1 gt gt 7 156 For X 200 Result 192 256 192 8 lt lt 1 gt gt 7 200 273 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 Memory Offset Registers 15 4 1 Overlay Buffer Pointer Registers These registers provide address pointers into the system memory or Local memory buffer areas The buffers must be QWord aligned Pixel panning on a pixel basis is done using the byte addresses Overlay buffers need to be QWord aligned and the stride should be a QWord multiple Buffer pointers should always be aligned to the natural boundaries based on the data format For planar formats YUV410 YUV420 the Y and UV pointers should be naturally aligned to each other Their natural alignment depends on the particular data format Format Alignment Pixels Bytes RGB packed 1 2 YUV 4 2 2 packed 2 4 YUV 4 1 1 packed 8 12 YUV Planar 1 1 Only the Register Update Address register should be written while the overlay is active
11. Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Intel 815 Chipset System Block Diagram cscscscscsesesesesesesesesesesescsescscsescsees 18 Intel 82815 Chipset GMCH Block Diagram ccccccceceeeeeeeeeeeeieeeeetnneeeeeena 19 Conceptual Platform PCI Configuration Diagram ccccceeeeeeeeereeeenteeeeeeee 23 Device Mode Auto Detect Flowchart ee eececeeeeeneeeeeeteeeeeeneeeeeneeeeeenaneeenenaes 25 System Memory Address Map c ceseececceeeeeeeseeeeceacaeeeeeeesesennaeaeeeeeeeeeeeenaees 29 Detailed Memory System Address Map ccccecceceeseeeeeeeeeeeeeenieeeeeeneeeeseaaes 29 Graphics Controller Register Memory and I O Mabp eceeeeeeeeeeeeeeees 30 GTT Mapping nisni ante enterinteteeadeniey dati eden aE 42 Source Corruption in BLT with Overlapping Source and Destination Locations 54 Correctly Performed BLT with Overlapping Source and Destination Locations 55 Suggested Starting Points for Possible Source amp Destination Overlap SITUATIOMS sataisi ees cova guns anennaaedorsadaaduadinadsensandenteetedadcaadaadceataagacasssanaties 56 Representation of On Screen Single 6 Pixel Line in the Frame Buffer 57 Representation of On Screen 6x4 Array of Pixels in the Frame B
12. Intel 815 Chipset Graphics Controller PRM Rev 1 0 10 Programming InterlaCe aiec AANE T ANAE O ei A ERER 141 10 1 Reserved Bits and Software Compatibility 0 0 0 eceeeceeeeeeeneeeeeeeeeeeeeeenaeeeeeeneeeeneaes 141 10 2 V OVERVIEW oii ed vtitecucban a baa eee edhe ted beta e A aw heya S e a T E AANA 141 10 3 GC Register Programming ccceccececceceeeeeeeeeneeeeeeeeeeeesecacaeeeeeeeeesecaueaeeeeeeeeenennaees 142 10 4 GC Instruction Stream Snan uaa i e a a a aA 142 10 4 1 Instruction USE k eina a a e s a aa iaaa 142 10 4 2 Instruction Transport OVeErvieW ccccecceceeeeeeeeeecaeeeeeeeeeseeenaeeeeeeeeeteeea 142 10 4 3 INStrUlCtiOn Farsele Annaa aaa ies edaagancsadedateaae wieeeadetatvearaanansie 143 10 4 4 Ring Butters RB S ra aa aaa eae aenda aeeie aa a aee aAa a 144 10 4 4 141 Ring Buffer Registers aessseesesseessrneserrnnessrnnesrennnerennestnnneenennasnen 144 10 4 4 2 Ring Buffer Initialization eeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaees 145 10 4 4 3 Ring Buffer Use cece ccencceeeeseeeeeeecaneeeeececeneedeneeseedeneeesedeneens 145 10 4 5 Batch B ffErS einna raa a wag o aa r a ar 146 10 4 6 Instruction Arbitration nse a e a aa ai 147 10 4 6 1 Arbitration Rationale cc cccecccccececeseeneseeeeeeeeseaaeeeseeeeeeeeanensees 147 10 4 6 2 Wait INStrUCtiOns sinasin nenda atat a a aderi 147 10 4 6 3 Instruction Arbitration Points nnssoeoenannnnnnssnsnnnrrnness
13. 0 Cleared by graphics controller Disable Mcomp Instructions Disable processing of mcomp instructions by parser 1 Disable 0 Enable Disable GDI Blitter Instructions Disable processing of Blitter instructions 1 Disable 0 Enable Disable Render 3D Stretch Instructions Disable processing of 3D instructions Client 00h by parser 1 Disable 0 Enable Disable State Variable Updates 1 Disable 0 Enable Disable Render Palette Updates 1 Disable 0 Enable 314 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 1 12 INSTPS Instruction Parser State Register debug Address Offset 020C4h Default Value 0000h Access Read Only Size 32 bits This register contains the state code of the Instruction Parser in the CSI Decoding the contents of this register will indicate what the Instruction Parser is currently doing 31 17 16 15 14 13 12 11 10 9 8 CSINTR CSSTDW Reserved cont E 16 15 CSINTR State Machine Is responsible for the working the CS PI Interrupt cycle generation interface 00 INTRIDLE This is the reset state It is also the idle state The state machine comes back to this state on getting acknolwedged in either of the two request states 01 INTREQON In this state the command stream turns on the interrupt flag to the HubLink unit and requests service 11 INTREQOFF In this state the command stream turns off the interrupt flag to the HubLink unit and requ
14. 1 Enable 0 Disable default Z Buffer Write Enable Mask 1 Update 0 Do Not Update Z Buffer Write Enable 1 Enable 0 Disable default The frame buffer write enable feature can be used to reliably render coplanar layered polygons An example of this type of layering would be to render a window on a wall With a 16 bit z buffer there is not sufficient precision to render this type of scene with consistent priority Some pixels of the window will be intermixed with some pixels of the wall due to precision inaccuracies 13 22 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_FOG_COLOR The GFXRENDERSTATE FOG COLOR state instruction format is 31 29 Client 03h Render Processor 28 24 3DState24NP Non pipelined 15h 3 0 23 19 Fog Color Red Bits 7 3 of the red fog color component The default value is 0 unsigned int 18 16 Reserved Oh 15 10 Fog Color Green Bits 7 2 of the green fog color component The default value is 0 unsigned int Reserved Oh 7 Fog Color Blue Bits 7 3 of the blue fog color component The default value is 0 unsigned int GFXRENDERSTATE_DRAWING_ RECTANGLE INFO The values programmed in this packet are in screen coordinates In full screen mode the screen pitch and height minus one need to be programmed into this packet For example for screen size of 1280x1024 the values programmed should be Xmin 0 Ymin 0 Xmax 1279 Ymax 1023 When r
15. 1Dh Surface Format Oh 8 bpt Indexed 1h 8 bpt 2h 16 bpt 3h 4h Reserved 5h 4 2 2 6h 7h Reserved Reserved 0h Texel Pixel Format 8 bpt Indexed Surface Format 00 RGB 565 01 ARGB 1555 10 ARGB 4444 11 AY 88 8 bpt Surface Format 00 Reserved 01 Reserved 10 Reserved 11 Reserved 16 bpt Surface Format 00 RGB 565 01 ARGB 1555 10 ARGB 4444 11 AY 88 4 2 2 00 YCrCb Swap Y format 01 YCrCb Normal 10 YCrCb UV Swap 11 YCrCb UV Y Swap Output Channel Selection Selects the muxing for the possible 4 channels available in the surface at the output of the filter and the 4 output channels from the Mapping Engine Mapping Engine Output Channels ME ME ME ME Oh Fo Fy F2 F3 1h F3 2h F2 E F3 3h Reserved 219 Intel 815 Chipset Graphics Controller PRM Rev 1 0 220 DWord Color Space Conversion Enable 0 Do not perform conversion 1 Perform color space conversion assuming biased chromanance values Vertical Line Stride The number of lines to skip between logically adjacent lines The Forward Backward Reference Picture Structure bits override this value when processing the GFXBLOCK instruction 0 Do not skip any lines 1 Skip 1 line provides support of Interleaved field surfaces Vertical Line Stride Offset The number of lines to add as an initial offset when the Vertical Line Stride is 1 This value is overridden by the F
16. CRT Controller Interpretation Enable bit has no effect on CR41 and CR13 124 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 22 CR14 Underline Location Register I O and Memory Offset Address 3B5h 3D5h index 14h Default OUUU UUUUb U Undefined Attributes Read Write 7 6 5 4 0 Reserved DWord Count By Underline Location 0 Mode 4 Reserved Read as Os DWord Mode 0 Frame buffer addresses are interpreted by the frame buffer address decoder as being either byte addresses or word addresses depending on the setting of bit 6 of the CRT Mode Control Register CR17 1 Frame buffer addresses are interpreted by the frame buffer address decoder as being DWord addresses regardless of the setting of bit 6 of the CRT Mode Control Register CR17 Note that this bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register CR17 to select how frame buffer addresses from the processor are interpreted by the frame buffer address decoder as shown below CR14 6 CR17 6 Addressing Mode 0 Word Mode Byte Mode DWord Mode DWord Mode clock depending upon the setting of bit 3 of the CRT Mode Control Register 1 The memory address counter is incremented either every 4 character clocks or every 2 character clocks depending upon the setting of bit 3 of the CRT Mode Control Register Note that this bit is used in conjunction with bit 3 of the CRT Mode Control Register CR17 to selec
17. Intel 815 Chipset Graphics Controller PRM Rev 1 0 360 Bit Descriptions 17 Vertical Blank Enable 0 Vertical Blank Status Disabled 1 Vertical Blank Status Enabled Overlay Registers Upated Enable 0 Overlay Registers have been updated during Vertical Blank Status Disabled 1 Overlay Registers have been updated during Vertical Blank Status Enabled 15 Flat Panel Hot Plug Detect Status This bit is the state of the TVCLKIN pin of the TV Flat Panel interface This pin signals an interrupt when it is low When an interrupt is asserted on the pin this status bit reads back as a 1 This bit is forced low when the TVCLKIN pin is selected as a Clock Input reference to the Dot Clock PLL and NOT an Interrupt pin 0 Flat Panel Hot Plug Detect asserted 1 Flat Panel Hot Plug Detect not asserted forced to 1 when used as CLKIN 10 Flat Panel Hot Plug Detect edge catcher This bit is the edge detector for bit 15 above It is set to 1 when it detects a low to high transition 0 Flat Panel Hot Plug Detect not asserted bit 15 has not transitioned from 1 to O forced to 0 when used as CLKIN 1 Flat Panel Hot Plug Detect asserted bit 15 has transitioned from 1 to 0 Vertical Sync Status 0 Vertical Sync not asserted 1 Vertical Sync asserted Display Line Compare Status 0 Display Line Compare Status not asserted 1 Display Line Compare Status asserted 1 Vertical Blank Status 0 Vertical Blank Status not ass
18. Scissor Rectangle Enable 0 Disable default 1 Enable SS E a a Scissor Rectangle Enable Mask 1 Scissor Rectangle Enable Mask 1 Update 0 Do Not Update Update 0 Do Not Update 245 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 24 246 GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO The coordinate in this instruction packet is relative to the origin upper left corner DWord 4 of the drawing rectangle defined in the GFXKRENDERSTATE DRAWING RECTANGLE INFO packet The coordinates of the scissor rectangle do not need to be clipped to screen boundary before sent to hardware Client 03h Rendering Engine 24 3DStateMWNP Non pipelined 1Dh 2316 16 Opcode 81h 150 0 15 0 DWORD_LENGTH 21 31 16 Ymin Y coordinate of upper left corner Only the lower 10 bits is used by hardware This value is pixel aligned U10 format and reference to the origin unclipped upper left corner of the drawing rectangle 15 0 Xmin X coordinate of upper left corner Only the lower 11 bits is used by hardware This value is pixel aligned U11 format and reference to the origin unclipped upper left corner of the drawing rectangle 2 31 16 Ymax Y coordinate of lower right corner Only the lower 10 bits is used by hardware This value is pixel aligned U10 format and reference to the origin unclipped upper left corner of the drawing rectangle 15 0 Xmax X coordinate of lower right corner O
19. The color specified as the background color for use in the color expansion of monochrome source data is compared to the color resulting from the bit wise operation performed for each pixel If these two colors are not equal then the byte s at the destination corresponding to the current pixel are written with the result of the bit wise operation Source color transparency The color specified as the background color for use in the color expansion of monochrome source data is compared to the color specified by the byte s at the destination corresponding to the current pixel If these two colors are not equal then the byte s at the destination corresponding to the current pixel are written with the result of the bit wise operation The color specified as the background color for use in the color expansion of monochrome source data is compared to the color resulting from the bit wise operation performed for each pixel If these two colors are equal then the byte s at the destination corresponding to the current pixel are written with the result of the bit wise operation The color specified as the background color for use in the color expansion of monochrome source data is compared to the color specified by the byte s at the destination corresponding to the current pixel If these two colors are equal then the byte s at the destination corresponding to the current pixel are written with the result of the bit wise operation Destination color
20. Vertical Total Register CRO6 and the 2 most significant bits are supplied by bits 5 and 0 of the Overflow Register CRO7 In standard VGA modes these 4 bits of this register are not used In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical total is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Total Register CRO6 and the 4 most significant bits are supplied by these 4 bits of this register This 10 bit or 12 bit value should be programmed to be equal to the total number of scan lines minus 2 132 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 30 CR31 Extended Vertical Display End Register I O and Memory Offset Address 3B5h 3D5h index 31h Default 00h Attributes Read Write 7 4 3 0 Reserved 0000 Vertical Display End Bits 11 8 Reserved Read as Os This field must be Os when this register is written Vertical Display End Bits 11 8 The vertical display enable end is a 10 bit or 12 bit value that specifies the number of the last scan line within the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical display enable end is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Display Enable End Register CR12 and the 2 most significant bits are supplied
21. be Zero ee 31 26 Reserved Must be Zero The maximum GC graphics address is 64 MBs 25 0 Source Scan Line Address These 26 bits are used by the over scan line fetching state machine to address the source data Source data is read when ever there is room in the internal memory buffer to avoid the read latency between scan lines NOTES This is a working register If this register is read while the BLT Engine is busy the contents are unpredictable 12 3 22 D_SLH Destination Scan Line Height 202 Memory Offset Address 40078h Default None Attributes RO DWord accessible D_SLH is a working register which contains the current height that the over scan line state machine uses 31 16 15 0 Destination Scan Line Height Reserved Must be Zero J o o ee OSOS Destination Scan Line Height These 16 bits specify the height of the destination data in terms of the number of scan lines Reserved Must be Zero NOTES This is a working register If this register is read while the BLT Engine is busy the contents are unpredictable Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 23 D_SLRADD Destination Scan Line Read Address Memory Offset Address 4007Ch Default None Attributes RO DWord accessible 31 26 25 0 Reserved Must Destination Scan Line Read Address Bits 25 0 be Zero 31 26 Reserved Must be Zero The maximum GC Graphics address is 64 MBs 25 0 Destination Address Thes
22. 10h OEh 00h FFh 00h Oth 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh OCh 00h OFh 00h 08h 00h 00h 00h 00h 10h OAh 00h FFh 00h 08h 08h 08h 08h 08h 08h 08h 10h 18h 18h 18h 18h 18h 18h 18h OEh 00h OFh 08h 00h 7 00h 00h 00h 00h 10h OAh 00h FFh 00h 08h 08h 08h 08h 08h 08h 08h 10h 18h 18h 18h 18h 18h 18h 18h OEh 00h OFh 00h 08h 132 col Opt 1 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh OCh 00h OFh 00h 75 132 col Opt 2 00h 00h 00h 00h 10h OEh 00h FFh OCh 00h OFh 00h 00h Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 76 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Frame Buffer Access The VGA frame buffer is located at AOOOh BFFFh This is the standard VGA frame buffer address The physical location of the frame buffer is at the top of main memory The size can either be 512 KB or 1 MB This is selected in the SMRAM register which is documented in the Initialization Registers section of this document The frame buffer is not stored in local memory but it is taken from the top of main memory as described in the SMRAM register description 77 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 78 9 1 Intel 815 Chipset Graphics Contr
23. 15 4 9 1 SCLRKVH Source Color Key Value High Register 00 290 15 4 9 2 SCLRKVL Source Color Key Value Low Register 20 291 15 4 9 3 SCLRKM Source Color Key Mask Register 291 15 4 10 Overlay Configuration Registers ceceeeeeeeseeeeeenneeeeeenaeeeeeeneeeeeeaas 293 15 4 10 1 OVOCONF Overlay Configuration Register c eee 293 15 4 11 OVOCMD Overlay Command Register ceceeseeeeeenteeeeeetteeeeeeaes 294 15 4 12 Overlay Alpha Blend Window Position Size Registers eeceeeee 298 15 4 12 1 AWINPOS Alpha Blend Window Position Register 0 298 15 4 12 2 AWINSZ Alpha Blend Window Size Register eeeeee 299 19 5 Overlay Fip INSTRUCTION 2c 0 E eave fob a de ete a alae en ede 299 16 Instruction Memory and Interrupt Control Registers ceccccecceceeeeeeeeenceeceeeeeeeeeseteeeeeees 301 16 1 Instruction Control Registers 20 2 cecceeeeceeeeeeeeeeeeeeeseeeeeeeseeeeeeeseeeeeeseeeaeeeseeaeeeeeenaeees 301 16 1 1 FENCE Graphics Memory Fence Table Registers ccceseeeeees 301 16 1 2 PGTBL_CTL Page Table Control Register cecceeeseeeeeesteeeeeenaes 303 16 1 3 PGTBL_ER Page Table Error Register 0 cccceceseeeeeeeeeeeenteeeeeeaes 304 16 1 4 PGTBL_ERRMSK Page Table Error Mask Register 0 cceeeeeeees 306 16 1 5 RINGBUF Ring Buffer Registers 20 0 cccceeeeseeeeeeeeneeeeeeeneeeeetnaeeeeneaas 30
24. 815 chipset remains in AGP Mode APCONT 0 0 If the AGP PCI configuration cycle results in a Master Abort then it is assumed no external AGP graphics device is present and the System BIOS programs the Intel 815 chipset to Internal Graphics Mode by setting APCONT 0 1 During the same configuration cycle as setting the APCONT 0 to either 0 or 1 the BIOS should set APCONT 2 GFX AGP Select Lock 1 to lock the configuration mode System BIOS will then initialize the minimum set of the Intel 815 chipset configuration registers required to detect and test system memory System BIOS interrogates each System Memory DIMM via the Serial Presence Detect SPD mechanism ICH I2C cycles System BIOS determines if system configuration is capable of 133 MHz operation Requirements for 133 MHz operation include the Intel 815 chipset in AGP Mode and System Memory populated with up to two double sided or three single sided PC133 compliant DIMMs If system is 133 MHz capable as determined by the previous step System BIOS upshifts the System Memory operating frequency from 100 MHz to 133 MHz as follows Note that the Intel 815 chipset typically resets internally to 100 MHz SM operation a Program external clock generator chip i e CK815 for 133 MHz System Memory clocking via ICH I2C port Byte 3 Bit 0 set to 1 b Wait for 1 us to allow the Clock Generator to stabilize the external System Memory clocks
25. AR14 Pixel Width Clock Select 0 Six bits of video data translated from 4 bits via the palette are output every dot clock 1 Two sets of 4 bits of data are assembled to generate 8 bits of video data which is output every other dot clock and the Palette Registers AR 00 0F are bypassed Note This bit is set to 0 for all of the standard VGA modes except mode 13h 102 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Pixel Panning Compatibility 0 Scroll both the upper and lower screen regions horizontally as specified in the Pixel Panning Register AR13 1 Scroll only the upper screen region horizontally as specified in the Pixel Panning Register AR13 This bit has application only when split screen mode is being used where the display area is divided into distinct upper and lower regions which function somewhat like separate displays 0 Disables blinking in graphics modes and for text modes sets bit 7 of the character attribute bytes to control background intensity instead of blinking 1 Enables blinking in graphics modes and for text modes sets bit 7 of the character attribute bytes to control blinking instead of background intensity The blinking rate is derived by dividing the VSYNC signal The Blink Rate Control Register FR19 defines the blinking rate Enable Line Graphics Character Code Every 9th pixel of a horizontal line i e the last pixel of each horizontal lin
26. DWORD_LENGTH 0 1 31 0 Color Factor This is a 32 bit value in ARGB 8888 format The top 8 bits used by the alpha blending stage and the lower 24 bits used by the color blending stage 232 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_COLOR_CHROMA_KEY ColorKey and ChromaKey are terms used to describe two methods of removing a specific color or range of colors from a map that is applied to a primitive When a color palette is used with indices to indicate a color in the palette the indices can be compared against a state variable ColorKey Index Value and if a match occurs and ColorKey is enabled then an action will be taken to remove this value s contribution to the resulting pixel color The ChromaKey mode refers to testing the RGB components to see if they fall between a high Chroma High Value and low Chroma_Low_ Value state variable values If the color of a texel contribution is in this range and ChromaKey is enabled then an action will be taken to remove this contribution to the resulting pixel color When the color value of the nearest neighbor texel falls within the range of the ChromaKey values or the palletized texel index matches the ColorKey value the pixel can be programmed by the Kill Pixel state variable to not be written back to the frame buffer If neither Key mode applies then a blend occurs as described below When multiple texture is enabled only the color of texel 0 is
27. The only exception is during VGA pixel doubling mode During VGA pixel doubling active pixel time must be a multiple of 4 pixels to account for centering with VGA pixel doubling and non active times must be a multiple of 2 pixels clocks All fields are excess 0 encoded This means that the hardware uses the value 1 where value is the entry in the field Therefore if a 0 is programmed into a field the hardware uses the value 1 for that field HTOTAL Horizontal Total Register Address Offset 60000h Default Value 00000000h Access Read Write Size 32 bits 31 28 27 16 Reserved Horizontal Total Display Pixels 15 11 10 0 Reserved Horizontal Active Display Pixels p ooo e O 27 16 Horizontal Total Display Pixels This 12 bit field provides a horizontal total up to 4096 pixels encompassing 2048 active display pixels front back border pixels and horizontal retrace period Any pending event HSYNC VSYNC is reset at htotal 10 0 Horizontal Active Display Pixels This 11 bit field provides horizontal active display resolutions up to 2048 pixels Note that the first horizontal active display pixel always starts at 0 333 Intel 815 Chipset Graphics Controller PRM Rev 1 0 17 2 HBLANK Horizontal Blank Register Address Offset 60004h Default Value 00000000h Access Read Write Size 32 bits 31 28 27 16 15 12 11 0 Reserved Horizontal Blank Start p ooo o e O 27 16 Horizontal Blank End Horizontal blank en
28. This register is not present in 2D 7 0 Reserved 00000000 Reserved This register did something useful in 554 and was not completely removed from Portola database even though it does nothing useful 9 6 41 CR82 Blink Rate Control I O and Memory Offset Address 3B5h 3D5h index 82h Default 00h Default 83h is the VGA default but 88h is used instead because that s a more visually appealing value Attributes Read Write The h w default for this register does not match the VGA compatibility requirements BIOS must make sure to set this register to correct value 7 6 5 0 Character Blink Duty VSync Blink Rate Cycle J o o o eO S Character Blink Duty Cycle Character Blink is also known as Attribute Blink 00 50 duty cycle 01 25 duty cycle 10 50 duty cycle power on default VSync Blink Rate Controls the cursor blink rate in terms of the number of VSyncs on the following basis the programmed value must be the actual value 2 1 The default is 3 140 10 1 10 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Programming Interface The Graphics Controller GC contains an extensive set of registers and instructions also referred to as Commands for controlling 2D 3D and video operations This section describes the programmer s interface to these registers and instructions Reserved Bits and Software Compatibility In many registers instruction and memory
29. memory with Overlay 0 register loads during Vertical Blank OVOCONF Overlay Configuration Register Memory Address Offset 64h R W On chip Reg Mem Addr Offset 30164h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 8 Reserved Reserved Cr Cb Reserved YUV Conv Reserved Line Buf Rdjust En En Conf Reserved Reserved os Reserved Cr Cb Readjust Enable Reserved Field in Intel 810 Chipset Reserved for future implementations 0 Disable Cr Cb Readjust 1 Enable Cr Cb Readjust TV Out mode convert back to U V excess 128 and Y Y 16 Reserved YUV Conversion Enable Reserved for future implementations The conversion disabled setting should only be used when the overlay data is being directed out to the video side port 0 Enable YUV Conversion 1 Disable YUV Conversion TV Out YUV 4 4 4 mode Reserved Line Buffer Configuration Sets the line buffer configuration 0 2 720 pixel line buffers 1 1 1440 pixel line buffer 293 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 11 OVOCMD Overlay Command Register Memory Address Offset 68h R W On chip Reg Mem Addr Offset 30168h RO debug path Default Value 00h Access see address offset above Size 32 bits This register provides the data the overlay engine needs to begin work A write to this register sets an internal bit readable by the status that will cause all the register values
30. pias 134th Scan Lin 21C80h 135th Scan Lin 135 135 b_blt12 vsd The figure above shows the display on which this letter f is to be drawn As shown in this figure the entire display has been filled with a gray color The letter f is to be drawn into an 8x8 region on the display with the upper left hand corner at the coordinates 128 128 Source Data in System Memory for Example Character Drawing BLT Source Data Pixel 0 Pixel 7 0 63 57 56 48 47 40 39 32 31 24 23 16 15 87 o 0 7 7 7 Pixel 0 7 Pixel 7 7 90000004 00010004 00010000 00111104 00010004 0001000 00001104 90000004 7 0 0 0 b_blit13 vsc The figure above shows both the 8x8 pattern making up the letter f and how it is represented somewhere in the host s system memory the actual address in system memory is not important The letter f is represented in system memory by a block of monochrome graphics data that occupies 8 bytes Each byte carries the 8 bits needed to represent the 8 pixels in each scan line s worth of this graphics data This type of pattern is often used to store character fonts in system memory During this BLT operation the host processor will read this representation of the letter f from system memory and write it to the BLT engine by performing memory writes to the ring buffer as an immediate
31. the Parser halts when it parses this instruction until the beginning of the next display vertical blank If executed out of a ring buffer the Parser sets a flag that eliminates that ring from the arbitration until the flag is cleared This flag is cleared by the appropriate edge detection of the Display Vertical Blank signal assertion DISPLAY FLIP PENDING If this bit is set and this instruction is executed out of a Batch Buffer the Parser halts when it parses this instruction until the flip event new front buffer address has now been loaded into the active front buffer registers If executed out of a ring buffer the Parser sets a flag that eliminates that ring from the arbitration till the flip event If there is no flip pending the parser just proceeds Mechanism The execution of a front buffer packet by the parser sets a flag FlipPendingFlag that is cleared by the flip event If the FlipPendingFlag is set and this instruction shows up with this bit set then the parser will wait for flip event just as described for the bit above If FlipPendingFlag is not set and this instructions shows up with this bit set the instruction has no effect and parser moves on If the execution of this instruction happens to coincide with the flip event the parser behaves as if the FlipPendingFlag is not set The flip event can be a function of hsync or vsync as selected by the front buffer packet SCAN LINES This instruction with this bit set should be
32. 0 bit2 plane 0 bitO plane 1 bit6 plane 1 bit4 plane 1 bit2 plane 1 bit O This alternating pattern is meant to accommodate the use of the Odd Even mode of organizing the 4 memory planes which is used by standard VGA modes 2h and 3h Bits 6 5 1x Four bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the palette in a pattern that iterates per byte through memory planes 0 through 3 First the 4 most significant bits of a byte in memory plane 0 are transferred via the 4 serial output bits followed by the 4 least significant bits of the same byte Next the same transfers occur from the parallel byte in memory planes 1 2 and lastly 3 Each transfer provides either the upper or lower half of an 8 bit value for the color for each pixel making possible a choice of 1 of 256 colors per pixel Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer Bit3 plane 0 bit7 plane O bit3 plane1bit7 plane 1 bit3 plane 2bit7 plane 2 bit3 plane 3 bit 7 plane 3 bit 3 Bit2 plane 0 bit6 plane O bit2 plane1bit6 plane 1 bit2 plane2bit6 plane 2bit2 plane 3 bit6 plane 3 bit 2 Bit1 planeObit5 planeObit1 plane1bit5 plane 1 bit1 plane2bit5 plane 2 bit1 plane 3 bit5 plane 3 bit 1 BitO plane 0 bit4 plane O bitO plane1bit4 plane 1 bitO plane 2bit4 plane 2 bitO plane 3 bit4 plane 3 bit O This pattern is meant to accommodate mode 13h a standard VGA 256 color graphics mode Intel 815 Chipset Graphics C
33. 1 The adapter is in color monitor mode In this mode the control register is 3D4 and 3D5 and status is at 3DA See the section on VGA compatibility for a description of the register space that must be acquired 5 4 2 Protect Registers Locking and Unlocking To make use of some protected VGA registers a locking and unlocking mechanism needs to be implemented The following steps illustrate how to unlock or unprotect the VGA registers e Send a VERT SYNC _END value to the register at vgaBase 4 e Read the value in the register at vgaBase 5 e Clear the high order bit of the value just read e Write the resulting value back into the register at vgaBase 5 5 4 3 Checking Memory Frequency The driver behavior occasionally must be modified depending on the frequency at which the memory is running The following steps illustrate how to determine the local memory frequency e Read the contents of the Intel 82815 chipset Configuration Register PCI address space 0x50 e Examine the value of bit 4 e The value is interpreted as follows 0 Frequency is 100 MHz 1 Frequency is 133 MHz 5 5 Hardware State Under certain conditions it may be necessary to save and restore the hardware state of the graphics adapter These conditions include mode switching output device switching processing changes in power state and others The next two sections provide a brief description of the state saving and restoration requirements
34. 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 365 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 352X480_70Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 366 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 367 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 400x300_70Hz Dot Clock Value M
35. 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 410 OxAO Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1280x1024 _72Hz Dot Clock Value 132 132 MHz Dot Clock HINOTINVESA M Value 0x0014 N Value 0x0002 P Value 0x20 CROO 0xD3 CR01 Ox9F CRO2 Ox9F CRO3 0x97 CR04 OxAA CRO5 0x1B CRO6 0x29 CRO7 0x10 CRO9 0x40 CR10 0x00 CR11 0x03 CR12 OxFF CR13 OxAO Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 411 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1280x1024 _75Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 41
36. 15 00 Destination Pitch positive 13 00 are implemented in Intel 810 chipset 2 BRO2 31 00 ClipRect Y1 Address Top 25 00 are implemented inIntel 810 chipset 3 BRO3 31 00 ClipRect Y2 Address Bottom 25 00 are implemented in Intel 810 chipset 4 BRO4 31 16 ClipRect X2 coordinate Right 27 16 12 bits are implemented in the Intel 815 p g p chipset 15 00 ClipRect X1 Coordinate Left 11 00 12 bits are implemented in the Intel 815 chipset 5 31 24 Reserved Must be Zero 5 BROS 23 00 Setup Background Color All 6 31 24 Reserved Must be Zero 6 BRO6 23 00 Setup Foreground Color SLB amp TB only 7 BR20 31 00 DW0 least significant for a Monochrome Pattern 8 BR21 31 00 DW1 most significant for a Monochrome Pattern 1 BRO1 166 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 3 PIXEL_BLT The Destination X coordinate and Destination Y Address is compared with the ClipRect registers If it is within all 4 comparisons then the pixel supplied in the SETUP_BLT instruction is written with the raster operation to Destination Y Address Destination X coordinate bytes per pixel Powe Te ee 31 29 Client 02h 2D Processor 28 22 Instruction Target Opcode 20h 21 06 Destination X Coordinate 17 06 12 bits are implemented in the Intel 815 chipset Reserved Must be Zero 04 00 Dword Length 00h 1 BRO9 31 00 Destination Y Address address of the first pi
37. 17 Monochrome source data bit position of the first pixel within a byte per scan line Reserved Must be Zero 15 00 Dword Length 04 DWL Number of Immediate double words h 0 use background Reserved Must be Zero Must Be One 1 25 24 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved 23 16 Raster Operation 15 00 Destination Pitch signed 13 00 are implemented in Intel 810 chipset 2 BR14 31 16 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BR09 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset Reserved Must be Zero 4 BR18 23 00 Source Background Color 8 oo inmeditematsowe O 176 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 13 FULL_BLT The full BLT is the most comprehensive BLT instruction It provides the ability to specify all 3 operands destination source and pattern The source and pattern operands are the same bit width as the destination operand The whole color pattern 8 x 8 pixels 8 16 or 64 DWs is read at the beginning of the BLT and stored in the Texture Cache The pattern vertical alignment specifies which scan line of the pattern is used first The destination address specifies the horizontal alignment The only memory accesses required
38. 2 3 324 lIR Interrupt Identity Register Address Offset 020A4h Default Value 0000h Access Read Write Clear Size 16 bits The individual interrupt s which occurred are determined via this register The bit is set by the interrupt event and held until cleared by writing a 1 into the bit position 14 13 10 8 HW Reserved Pri Dply Reserved Overlay 0 Reserved Detect Flip Flip Error Pending Pending Master 6 5 4 3 2 0 Pri Dply Reserved Reserved Reserved Reserved User Breakpoint Event Defined Interrupt Description Interrupt Identity See Table 17 1 Interrupt occurred Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 2 4 IMR Interrupt Mask Register Address Offset 020A8h Default Value FFFFh Access Read Write Size 16 bits An interrupt that is masked by this register will not appear in the Interrupt Identity Register and will not generate an interrupt 10 8 HW Reserved Pri Dply Reserved Overlay 0 Reserved Detect Flip Flip Error Pending Pending Master 6 5 4 3 2 0 Pri Dply Reserved Reserved Reserved Reserved User Breakpoint Event Defined Interrupt Description Interrupt Mask Bits See Table 17 0 Not Masked 1 Masked 325 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 2 5 ISR Interrupt Status Register Address Offset 020ACh Default Value 0100h probably still not quite correct value Access Read Only Size 16 bi
39. 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 379 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 720x480_75Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 380 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 40 140 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 381 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 720x576_60Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7
40. A converters one each for the red green and blue components used to produce a color on a CRT display The palette DAC is also frequently called the RAMDAC to emphasize the presence of memory alongside the three D to A converters and the palette itself is often referred to as the CLUT or color look up table During normal use the palette DAC is operated either in direct color mode or indexed color mode Direct color mode is used with pixel depths of 15 16 or 24 bits per pixel In direct color mode the pixel data received from the frame buffer through the sequencer and the attribute controller directly specifies the color for a given pixel This pixel data is pre formatted such that certain bits of the pixel data for each pixel are used to provide the red green and blue output values for each of the three corresponding 8 bit D to A converters Indexed color mode is used with pixel depths of 8 bits per pixel or less In indexed color mode the incoming pixel data for each pixel is actually an 8 bit index that is used to choose one of the 256 color data positions within the palette Each color data position holds a 24 bit color value that specifies the actual 8 bit red green and blue values for each of the three corresponding 8 bit D to A converters In essence the colors for each pixel are specified indirectly with the actual choice of colors taking place in the color data positions of the palette while the incoming pixel data chooses from am
41. Address Read at 3C1h and Write at 3COh index 00h 0Fh Default OOUU UUUUb U Undefined Attributes Read Write 7 6 5 0 Description 7 6 Reserved Read as Os Palette Bits P 5 0 In each of these 16 registers these are the lower 6 of 8 bits that are used to map either text attributes or pixel color input values for modes that use 16 colors to the 256 possible colors available to be selected in the palette Note Bits 3 and 2 of the Color Select Register AR14 supply bits P7 and P6 for the values contained in all 16 of these registers Bits 1 and 0 of the Color Select Register AR14 can also replace bits P5 and P4 for the values contained in all 16 of these registers if bit 7 of the Mode Control Register AR10 is set to 1 9 4 3 AR10 Mode Control Register I O and Memory Offset Address Read at 3C1h and Write at 3COh index 10h Default UUh U Undefined Attributes Read Write Palette Pixel Pixel Reserved Enable Enable Select Graphics Bits P5 Width Clk Panning 0 Blink Line Display Alpha P4 Select Select Compat Select Graphics Type Mode Bkgnd Int Char Code Description Palette Bits P5 P4 Select 0 P5 and P4 for each of the 16 selected colors for modes that use 16 colors are individually provided by bits 5 and 4 of their corresponding Palette Registers AR 00 0F 1 P5 and P4 for all 16 of the selected colors for modes that use 16 colors are provided by bits 1 and 0 of Color Select Register
42. Buffer 1 Field 1 14 Not Active Pixel This bit indicates the Display Horizontal Blank Active state includes Border Updated real time set by leading edge of Overlay s display HBLANK and cleared by the trailing edge of Overlay s HBLANK 0 HBlank inactive 1 HBlank active default a eem o 12 Not Active Video Scan Line This bit indicates the Display Vertical Blank Active state includes Border Updated real time set by leading edge of Overlay s display VBLANK and cleared by the trailing edge of Overlay s VBLANK 0 VBlank inactive 1 VBlank active default Display Line Status This field displays the line number Reset to zero at the trailing edge of display VBLANK Incremented at the trailing edge of Overlay s display HBLANK 15 3 Gamma Correction Note that the registers in this section are read from or written to directly at the memory address offset location specified 15 3 1 1 GAMC 5 0 Gamma Correction Registers Memory Address Offset 30010h 30027h GAMC5 30010h GAMC4 30014h GAMC3 30018h GAMC2 3001Ch GAMC1 30020h GAMCO 30024h Default Value GAMC5 COCOCOh GAMC4 808080h GAMC3 404040h GAMC2 202020h GAMC1 101010h GAMCO 080808h Access R W Size 32 bits 269 Intel 815 Chipset Graphics Controller PRM Rev 1 0 270 intel These registers determine the characteristics of the gamma correction for the overlay data Each register is 32 bits wide The registe
43. CRT Overscan Color Overscan 0 Palette Addressing 0 Disable default 1 Enable Extended Palette Addressing Enables access to all 8 locations 7 2 Reserved 000000 1 VGA Wrap 0 256 KB wrap state default for memory starting at A0000 1 Do not wrap 356 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Descriptions GUI Mode 0 Standard VGA and extended 4 bpp 16 color resolutions default Can still access memory in linear mode 1 High Resolution i e not VGA or extended planar Transition from VGA modes to hires mode or opposite Software will turn the display engine off screen off using SRO1 Screen Off and wait for at least two HSYNC periods and no more than two VSYNC periods since one of the isochronous streams is DRAM refresh controlled by DRAMCXH DRAM Refresh Status the wait should not be so long as to cause the DRAM content to degrade before writing to PIXCONF 0 and turning the display on This should ensure that all the data requested from the display engine will be out of the local memory interface before PIXCOMF is touched In addition while switching from hi res to VGA or VGA to hi res software will ensure that all the other isochronous streams are off before programming PIXCONF O NOTES Bits 27 24 are not normally used by the graphics BIOS or by the drivers because the gamma values are specific to a particular display device and apply to two color or hi color
44. Clip Rectangle Y2 Address Bits 25 0 These 26 bits specify the bottom clipping address of the destination data This clip compare is inclusive draw if destination address is less than or equal to this address This address points to the first byte of a scan line The Clip Rectangle X registers take care of the pixel positions within a scan line 188 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 5 BR04 Clip Rectangle X1 and X2 Memory Offset Address 40010h Default None Attributes RO DWord accessible BR04 is loaded by either the SETUP_BLT or SETUP_MONO PATTERN SL BLT instructions and is used with PIXEL BLT SCANLINE BLT or TEXT BLT instructions 31 28 27 16 Reserved Must be Zero Clip Rectangle X2 coordinate right 11 00 15 12 11 0 Reserved Must be Zero Clip Rectangle X1 coordinate left 11 00 31 28 Reserved Must be Zero 27 16 Clip Rectangle X2 Coordinate These 12 bits specify the right most X coordinate which is written to the destination The comparison is inclusive with a less than or equal The byte address of this coordinate is scan line address X2 bytes pixel 15 12 Reserved Must be Zero 11 0 Clip Rectangle X1 Coordinate These 12 bits specify the left most X coordinate which is written to the destination The comparison is inclusive with a greater than or equal The byte address of this coordinate is scan line address X1 bytes pixel 189 Intel 815
45. DIMMs Additionally the GMCH also provides a 1024 entry deep refresh queue The GMCH can be configured to keep up to 4 pages open within the memory array Pages can be kept open in any one bank of memory SCKE 5 0 are used in configurations requiring powerdown mode for the SDRAM Multiplexed AGP and Display Cache Interface The Intel 82815 chipset GMCH multiplexes an AGP interface with a display cache interface for internal 3D graphics performance improvement The display cache is used only in the internal graphics When an AGP card is installed in the system the GMCH internal graphics will be disabled and the AGP controller will be enabled AGP Interface A single AGP connector is supported by the GMCH AGP interface The AGP buffers operate in one of two selectable modes in order to support the AGP Universal Connector e 3 3V drive not 5 volt safe This mode is compliant to the AGP 1 0 and 2 0 specifications e 1 5V drive not 3 3 volt safe This mode is compliant with the AGP 2 0 specification The following table shows the AGP Data Rate and the Signaling Levels supported by the GMCH Data Rate Signaling Level 1 5V 3 3V 1x AGP Yes Yes 2x AGP Yes Yes 4x AGP Yes No The AGP interface supports 4x AGP signaling AGP semantic PIPE or SBA 7 0 cycles to SDRAM are not snooped on the host bus AGP FRAME cycles to SDRAM are snooped on the host bus The GMCH supports PIPE or SBA 7 0 AGP address mechanis
46. DISP_SL Display Scan Line Count Memory Offset Address 70000h Default 0000h Attributes Read only This register enables the read back of the display vertical line counter In interlaced display modes the line counter is initialized to the field and is incremented by two at each HSYNC The display line values are from CRTTG the CRT timing generator or the TV FP timing generator depending on whether the TV FP timing generator is enabled and not in FP VESA VGA Mode LCDTV_C 31 1 AND LCDTV_C 28 0 or not The line counter changes at the leading edge of HSYNC and can be safely read during display enable active time When in TV FP centering mode scan line 0 is the first active scan line of the TV FP not the first line of the centered active display 15 12 11 0 Line Counter for Display 11 0 Cee Line Counter for Display 11 00 353 Intel 815 Chipset Graphics Controller PRM Rev 1 0 20 2 354 intel DISP_SLC Display Scan Line Count Range Compare Memory Offset Address 70004h Default 0000h Attributes Read only The Top and Bottom Line Count Compare registers are compared with the display line values from CRTTG the CRT timing generator or the TV FP timing generator depending upon whether the TV FP timing generator is enabled and not in FP VESA VGA Mode LCDTV _C 31 1 AND LCDTV_C 28 0 or not The line counter changes at the leading edge of HSYNC It can be safely read during the display enable
47. Definitions This section describes the BLT Engine instruction fields These descriptions are in the format of register descriptions For debug purposes the read only addresses indicated provide BLT Engine status BROO BLT Opcode and Control Memory Offset Address 40000h Default 0000 0000 Attributes RO DWord accessible BROO is the last executed instruction DWord 0 Bits 22 5 are written by every DWO of every instruction Bits 31 30 and 4 0 are status bits Bits 28 27 are written from the DWO 15 14 ofa Setup instruction and Bit 29 is written with a 1 when a Setup instruction is written Bit 29 is a decode of the Setup instruction Opcode 30 Reserved Must be Zero 29 Setup Mono Pattern 28 22 21 20 19 17 16 Instruction Target Opcode Reserved Monochrome Bit 0 Must be Source Start Byte 1 Zero Packed Text Scan i Destination Pattern Mono BLT Line Transparency Vertical Pattern BLT Mode Alignment 21 20 19 17 15 14 Reserved Must be Zero BLT Engine Busy This bit indicates whether the BLT Engine is busy 1 or idle 0 This bit is replicated in the SETUP BLT Opcode amp Control register 1 Busy 0 Setup Monochrome Pattern This bit is decoded from the Setup instruction opcode to identify whether a color 0 or monochrome 1 pattern is used with the SCANLINE_BLT instruction 1 Monochrome Instruction Target Opcode This is the contents of the Instruction Target field from the la
48. In either case the surface address programmed in this instruction must be in graphics address space The GTT must be programmed to set up a scatter gather translation from graphics memory pages to physical pages in cacheable memory A surface that is being mapped to cacheable space must not be tiled or fenced A further restriction is that the source data must be the same pixel width as the destination The only function which is allowed is color copies with a positive destination pitch and direction The source operand can be either sign to allow mirroring in the vertical direction An immediate source operand is not allowed BLT Engine Instructions The following instructions are directed to the BLT Engine The Instruction Target field is used as an opcode by the BLT Engine state machine to qualify the control bits which are relevant for executing the instruction The description for each DWord and bit field is contained in the BLT Engine Instruction Definition section Each DWord in a packet has a corresponding Instruction Definition description where the details of the operation of the function are described All reserved fields must be programmed to Os 163 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 2 1 164 Note intel SETUP_BLT The setup instruction supplies common setup information including clipping coordinates used exclusively with the following 3 instructions 1 PIXEL _ BLT PB 1 pixel write wi
49. Intel 815 Chipset Graphics Controller PRM Rev 1 0 3 4 38 Table 4 Table 5 intel Indirect VGA and Extended VGA Register Indices Programming an index value into the appropriate SRX GRX ARX or CRX register indirectly accesses the registers listed in this section The index and data register address locations are listed in the previous section Additional details concerning the indirect access mechanism are provided in the VGA and Extended VGA Registers Chapter see SRxx GRxx ARxx or CRxx sections 2D Sequence Registers 3C4h 3C5h Pines sm 00h SROO Sequencer Reset SRO1 Clocking Mode 2D Graphics Controller Registers 3CEh 3CFh intel Table 6 Table 7 Intel 815 Chipset Graphics Controller PRM Rev 1 0 2D Attribute Controller Registers 3C0h 3C1h Index Sym Register Name AROO Palette Register 0 ARO1 Palette Register 1 ARO2 Palette Register 2 ARO3 Palette Register 3 AR04 Palette Register 4 ARO5 Palette Register 5 ARO6 Palette Register 6 07 ARO7 Palette Register 7 08h ARO8 Palette Register 8 09h ARO9 Palette Register 9 OAh AROA Palette Register A OBh AROB Palette Register B OCh AROC Palette Register C oD AROD Palette Register D AROE Palette Register E AROF Palette Register F AR10 Mode Control 11h AR11 Overscan Color AR12 Memory Plane Enable AR13 Horizontal Pixel Panning AR14 Color Select 2D CRT Controller Registers 3B4h 3D4h 3B5h 3D5h maes sm OOO esistrtime
50. Offset or Monochrome Source Quadwords 40040h 40043h BR16 Pattern Expansion Background and Solid Pattern Color Reserved 50000h 5FFFFh 35 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Table 2 3 3 36 Memory Mapped Registers Address Offset Symbol Register Name Access LCD TV Out Registers 60000h 6FFFFh IW R R VGA and Extended VGA Register Map For I O locations the value in the address column represents the register I O address For memory mapped locations this address is an offset from the base address programmed in the MMADR register PCI Configuration register Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 3 3 1 VGA and Extended VGA I O and Memory Register Map Table 3 I O and Memory Register Map Register Name Read Register Name Write VGA CRTC Index CRX monochome VGA Feature Control Register FCR 3C0h VGA Attribute Controller Index ARX VGA Attribute Controller Index ARX VGA Attribute Controller Data alternating writes select ARX or write ARxx Data 3C1h VGA Attribute Controller Data Reserved read ARxx data DACWX DACWX 3CFh VGA Graphics Controller Data GRxx VGA Graphics Controller Data GRxx 2D Registers 3D4h VGA CRTC Index CRX VGA CRTC Index CRX 3D5h VGA CRTC Data CRxx VGA CRTC Data CRxx 2D Registers 3D8h 3D9h Reserved Reserved 3DAh VGA Status Register ST01 VGA Feature Control Register FCR 37
51. Otherwise values will be loaded by writing the register image into memory and writing the command register with the address of the memory image in the Register Update address 15 4 1 1 OBUF_0Y Overlay Buffer 0 Y Pointer Register Memory Buffer Address Offset 00h R W On chip Reg Mem Addr Offset 30100h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 26 25 0 Overlay Buffer 0 Y Pointer p ooo o e O to the last byte of the line 25 0 Overlay Buffer 0 Y Pointer For Y Planar or packed color data byte address Must be pixel aligned low order bit zero for 16 bpp packed formats When mirroring horizontally X backwards this points 274 intel 15 4 1 2 15 4 1 3 Intel 815 Chipset Graphics Controller PRM Rev 1 0 OBUF_1Y Overlay Buffer 1 Y Pointer Register Memory Address Offset 04h R W On chip Reg Mem Addr Offset 30104h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 26 25 0 Overlay Buffer 1 Y Pointer 25 0 Overlay Buffer 1 Y Pointer For Y Planar or packed color data byte address Must be pixel aligned low order bit zero for 16 bpp packed formats When mirroring horizontally X backwards this points to the last byte of the line OBUF_0U Overlay Buffer 0 U Pointer Register Memory Address Offset 08h R W On chip Reg Mem Addr Offset 30108h RO debug path Default Value 00h Access see address offset
52. PRM Rev 1 0 This page is intentionally left blank 44 5 1 5 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Basic Initialization Procedures Initialization Sequence The initialization of graphics driver resources can be broken down into three categories hardware detection frame buffer initialization and hardware register initialization Each category is discussed in more detail in the following sections In all discussions that follow there is a basic assumption that the graphics adapter has completed the power on video BIOS initialization or video BIOS reset Therefore the adapter is in a known state and will respond in compliance with the VGA and VESA specifications Hardware Detection Probe Most operating systems will probe for installed devices The Intel 8281x family of devices advertise their presence in PCI space by using unique values in the PCI Vendorld and Deviceld locations The following table lists the device IDs used to identify the members of the 8281x family of graphics adapters Vendor Id Device Id PCI Device Characteristics PCI Offset 0 PCI Offset 2 Number 8086 7120 0 Intel 82810 chipset bridge 8086 7121 1 Intel 82810 chipset 8086 7122 0 Intel 82810 chipset DC100 bridge 8086 7123 1 Intel 82810 chipset DC100 8086 7124 0 Intel 82810E chipset bridge 8086 7125 1 Intel 82810E chipset 8086 1100 0 Intel 8281
53. Pattern Format is disabled bits 29 28 0 and any Y Cr or Cb pattern bits bits 27 22 are set the error data must be set to 0 The alternative is to ensure that the Y Cr or Cb pattern bits bits 27 22 are set to 0 ee Client 03h Rendering Engine EZE 24 Rendering Block 1Eh 2316 16 Opcode 00h 150 0 150 DWORD_LENGTH 5 Intra coded Correction Data DWords 27 24 Y Block Pattern Enable disable correction data for the Y block s Cr Block Pattern Enable disable intra coded correction data for the Cr block 31 30 Block Type 00 Reserved Macroblock The Luminance and Chromanance blocks are all predicted from this instruction The Height Width and Motion Vectors are shifted right 1 bit when processing the chromanance blocks 01 Luminance Y Block 10 Chromanance Red Cr Block 11 Chromanance Blue Cb Block 29 28 Block Pattern Format 00 Disable Block Pattern Usage and Intra coded Correction data The Height and Width are not constrained and need only be less than 1024 Intra coded Correction data is not allowed in this state 01 Single Block Uses bit 27 for a Luminance block and bits 23 22 for the chromanance blocks respectively If intra coded correction data is present the order of the data is row major for the entire width of the block 10 Halves Left and Right Uses bits 27 26 for the two halves of the Luminance block respective Intra coded correction data is delivered in row
54. QW 16 tiles Reserved MBZ Flip type 0 Synch flip 1 Async flip Dword Length 00h 1 31 26 Reserved MBZ 25 3 2 0 Front Buffer Base Address Virtual memory address bits 25 3 max 64MB The default value is 0 unsigned int Reserved MBZ 158 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 11 2 9 GFXCMDPARSER _Z BUFFER_INFO This instruction is used to specify the base address and pitch of the Z buffer surface used by the 3D Rendering engine This is an immediate command and therefore software must guarantee that the Rendering Engine and the local cache are flushed prior to modifying the z buffer information The format of the GFXCMDPARSER Z BUFFER_INFO instruction is 2 31 29 29 Client 000 Rendering Processor Opcode 16h Reserved MBZ Dword Length 00h Reserved 25 12 Base Address The base address of the Z buffer in linear space The Memory Interface unit uses this address in conjunction with the Memory Fence Table Registers to determine the virtual Tiled address of the buffer This surface address linear must be at least 4KB aligned in addition it must be 4 times pitch aligned 1 0 Pitch This is the pitch of the Z Buffer This is used by the TLB in computing the absolute address of Z requests 00 512 bytes 01 1KB 10 2KB 11 4KB 11 210 GFXCMDPARSER_REPORT_HEAD These instruction causes the active ring buffer Head Pointer to be written to a cacheabl
55. Reserved 16 1 8 _IPEHR lInstruction Parser Error Header Register debug Address Offset 0208Ch Default Value 0000h Access Read Only Size 32 bits This register is used to identify the instruction packet that generates an invalid instruction interrupt to the processor The IPEHR will contain the header word of the offending packet For debug purposes the header of all instructions parsed will be written to this register If an error occurs the instruction parser halts An interrupt indicating an error will be generated if it is unmasked p ooo e O Header This field will contain the instruction Header field of the instruction packet that generates an invalid instruction interrupt 311 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 1 9 INSTDONE Instruction Stream Interface Done Register Address Offset 02090h Default Value FFFF FFFFh Access Read only Size 32 bits This read only register reports engine done signals 31 24 Reserved 23 19 18 17 16 El A 15 14 13 12 11 10 9 CC_DONE MG_DON DG_DON QCC_DO FTCH_DO MEC_DO MECO D CCMC_D E E NE NE NE ONE ONE 7 6 5 4 3 2 1 0 Reserved Blitter Mapping Render Batch Reserved Intr Ring Low Prior Done Eng Done Eng Done Done Empty Ring Emp a 2 avona Erone Gene uput Dore eco pon O Ce foes O SS Ce fowo SSS 312 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Render Engine Done Batch D
56. System Reset J Figure 4 Memory and Basic chipset Initialization Mode 1 AGP Card DEV 0 REG53H Bit1 0 AGP Card Detected No Mode 2 Internal Graphics with Display Cache on GPA Card DEV 0 REG53H BIT1 1 Display Cache GPA Card Detected Mode 3 Internal Graphics with gt Shared Memory DEV 0 REG53H BIT1 1 REG70OH BIT7 6 11 or 10 25 Intel 815 Chipset Graphics Controller PRM Rev 1 0 2 3 1 3 26 intel Software Start Up Sequence The following sequence of events will occur during the initialization of an Intel 815 chipset based system 1 10 11 12 13 The ICH asserts PCIRST either in response to an initial assertion of PWROK or a write to an I O Port System BIOS runs basic POST code to test the processor System BIOS initializes the minimum set of Intel 815 chipset configuration registers required to initiate a PCI configuration cycle towards the AGP PCI interface e g bus 1 Note that following a system reset condition the Intel 815 chipset will always be in AGP Mode Internal Graphics disabled System BIOS detects if an AGP graphics card is present by attempting a configuration read cycle to the Intel 815 chipset AGP PCI interface If the configuration cycle completes successfully then it is assumed that an external graphics device is present on the AGP interface and the Intel
57. Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 370 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 25 125 175 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 371 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 640x400_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 372 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 25 125 175 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory s
58. a chained batch buffer cannot re enable writes to system memory If the IP detects an instruction that is disallowed in protected mode it stores the header of the instruction the origin of the instruction and an error code In addition such an event can generate an interrupt or a hardware write to system memory if enabled and unmasked At this point the IP can only be reactivated by a reset Intel 815 Chipset Graphics Controller PRM Rev 1 0 INTel 10 5 Instruction Format GC instructions are defined with various formats The first DWord of all instructions is called the header DWord The header contains the only field common to all instructions the client field that determines the major GC unit that will process the instruction data The Instruction Parser examines the client field of each instruction to condition the further processing of the instruction and route the instruction data accordingly Valid client values are e Instruction Parser 00h e 2D Processor 02h e 3D Processor 03h GC instructions vary in length though are always multiples of DWords The length of an instruction is either e implied by the client opcode e fixed by the client opcode yet included in a header field so the IP explicitly knows how much data to copy process e variable with a field in the header indicating the total length of the instruction Note that GC instruction sequences require QWord alignment and padding to QWord length to
59. above Size 32 bits 31 26 25 o Overlay Buffer 0 U Pointer p ooo e O 25 0 Overlay Buffer 0 U Pointer This register is used for YUV Planar Modes only It points to the start of the U addresses in the interleaved UV formats byte address 275 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 1 4 15 4 1 5 276 OBUF_0V Overlay Buffer 0 V Pointer Register Memory Address Offset OCh R W On chip Reg Mem Addr Offset 3010Ch RO debug path Default Value 00h Access see address offset above Size 32 bits 31 26 25 0 Overlay Buffer 0 V Pointer 25 0 Overlay Buffer 0 V Pointer This register is used for YUV Planar Modes only It points to the start of the V addresses in the interleaved UV formats byte address OBUF_1U Overlay Buffer 1 U Pointer Register Memory Address Offset 10h R W On chip Reg Mem Addr Offset 30110h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 26 25 0 Overlay Buffer 1 U Pointer Descriptiont Overlay Buffer 1 U Pointer This register is used for YUV Planar Modes only It points to the start of the U addresses in the interleaved UV formats byte address intel 15 4 1 6 15 4 2 15 4 2 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 OBUF_1V Overlay Buffer 1 V Pointer Register Memory Address Offset 14h R W On chip Reg Mem Adar Offset 30114h RO debug path Default Value 00h Access see a
60. and Memory Offset Address 3B5h 3D5h index 07h Default UUOU UUU0b U Undefined Attributes Read Write Group 0 Protection on bits 7 5 3 0 7 6 5 4 3 2 1 0 Vert Sync Vert Disp Vert Total Line Cmp Vert Bink Vert Sync Vert Disp Vert Total Start Bit 9 En Bit 9 Bit 9 Bit 8 Start Bit 8 Start Bit 8 En Bit 8 Bit 8 E Vertical Sync Start Bit 9 The vertical sync start is a 10 bit or 12 bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical sync start is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Sync Start Register CR10 and the most and second most significant bits are supplied by this bit and bit 2 respectively of this register In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical display end is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Sync Start Register CR10 and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Sync Start Register CR32 register In extended modes neither this bit nor bit 2 of this register are used This 10 bit or 12 bit value should be programmed to be equal to the number of scan lines from the beginning of the active display a
61. and third vertices 1 enable 0 disable This flag field is valid only in the first vertex of the triangle definition It is reserved otherwise Triangle Edge V0 V1 Enable This flag enables anti aliasing and wireframe capabilities for the triangle edge defined by the first and second vertices 1 enable 0 disable This flag field is valid only in the first vertex of the triangle definition It is reserved otherwise Y position Relative to origin of drawing rectangle or dest buffer Valid data range is 383 to 1663 IEEE float 2 ao Z position Normalized depth Valid data range is 0 to 1 IEEE float Z Bias Valid data range is 1 to 1 IEEE float 5 Color Alpha Valid data range is 0 to 255 unsigned int Color Red Valid data range is 0 to 255 unsigned int Color Green Valid data range is 0 to 255 unsigned int Color Blue Valid data range is 0 to 255 unsigned int 31 24 ot Factor Valid data range is 0 to 255 unsigned int 16 23 16 Specular Red Valid data range is 0 to 255 unsigned int 8 Specular Green Valid data range is 0 to 255 unsigned int 70 Specular Blue Valid data range is 0 to 255 unsigned int 31 0 Tu 0 Texture coordinates Data valid over entire IEEE floating point range IEEE float 31 0 Tv 0 Texture coordinates Data valid over entire IEEE floating point range IEEE float 31 0 Tu 1 Texture coordinates Data valid over entire IEEE floating point
62. as an output This value is only written into the register if LTVDA DATA MASK is also asserted The value will appear on the pin if this data value is actually written to this register and the LTVDA DIRECTION VALUE contains a value that will configure the pin as an output 0 Do NOT write LTVDA Data Value bit default 1 Write LTVDA Data Value bit LTVDA Direction Value R W This is the value that should be used to define the ouput enable of the LTVDA pin This value is only written into the register if LTVDA DIRECTION MASK is also asserted The value that will appear on the pin is defined by what is in the register for the LTVDA DATA VALUE bit 0 Pin is configured as an input default 1 Pin is configured as an output 10 LTVDA Data Mask R W This is a mask bit to determine whether the LTVDA DATA VALUE bit should be written into the register 350 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description LTVDA Direction Mask R W This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the register 0 Do NOT write LTVDA Direction Value bit default 1 Write LTVDA Direction Value bit The Data In bits 12 4 of the GPIOA GPIOB register are read only however data is only latched into these bits when a write is done to the respective bytes of the GPIOA GPIOB register Thus a read of the Data In bits must be preceded with a dummy write LTVCK Data Val
63. be the actual initial phase or the initial phase minus one 279 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 3 4 INIT_PH Initial Phase Register Memory Address Offset 28h R W On chip Reg Mem Addr Offset 30128h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 6 5 0 Reserved Initial Phase minus one es 5 4 3 2 5 0 Initial Phase minus one These bits provide a method of creating a negative initial phase If the corresponding bit is set the initial phase is the register value minus one These bits should only be set in cases where the buffer pointer is pointing to the first pixel of the line or column because it will effectively cause the first pixel to be duplicated Y Vertical Buffer Field 0 Y Vertical Buffer Field 1 Y Horizontal UV Vertical Buffer Field 0 1 UV Vertical Buffer Field 1 0 UV Horizontal 280 intel 15 4 4 15 4 4 1 15 4 4 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Overlay Destination Window Position Size Registers These registers allow for the positioning of the overlay data relative to the graphics display or the secondary display active region It allows pixel accurate positioning When using a secondary display the area outside the overlay windows will be black RGB 0 0 0 DWINPOS Destination Window Position Register Memory Address Offset 2Ch R W On chip Reg Mem Addr Offset 3012Ch RO debu
64. display device when performing an auto selection of the primary display device If the GMCH is in AGP mode this algorithm gives preference to the AGP graphics device over a PCI VGA device If the Intel 815 chipset is in GFX mode this algorithm gives preference to the internal graphics controller over a PCI VGA device Once the primary display device has been initialized system BIOS will pass control to the Video Option ROM corresponding to that display device If and only if the GMCH is in GFX Mode APCONT 0 1 the Video Option ROM will perform initialization routines described below System BIOS then completes the system test including testing the rest of main memory The following System BIOS initialization steps only apply if the GMCH is in Internal Graphics Mode Not AGP 1 System BIOS determines if a GPA card i e Local Memory is present This is accomplished the same as on the Intel 810 chipset Enable Local Memory via the DRT DRAMCL and DRAMCH offsets 3000 3002h and attempt to write and readback a location in Local Memory If the readback returns the same data that was written previously then it can be assumed that Local Memory is present If a GPA card is present the following additional steps take place e System BIOS configures the Local Memory Timing Options via the DRAMCL register at Device 2 Memory Mapped Register offset 3001h There is no Serial Presence Detect mechanism available for the Loca
65. divided by the size of the map prior to delivery to the GC This means that map addresses which lie on the map have a range of 0 0 to 1 0 3D rendering utilized normalized coordinates Un normalized coordinates are in units of texels pixels and have not been divided by the associated map s height or width Un normalized coordinates allow the Motion Compensation and Arithmetic Stretch Blitter operations to be specified in pixels avoiding floating point issues Un normalized coordinates are not usually specified outside of the map extents These two coordinate sets may also have different wrap clamp and mirror settings State Variable Relationships Coordinate Sets m Map Information Texels Blending Stages 215 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Eeg 6 5 4 1 Normalized Coordinate Set 0 Coordinates are not normalized 1 Coordinates are normalized 7 4 0 o7 oe 5 Address V Valid values are Oh Wrap 1h Mirror 2h Clamp 3h Wrap Shortest Address U State Variable Mask 0 Do not update 1 Update Reserved 00h 1 Address U Valid values are Oh Wrap 1h Mirror 2h Clamp 3h Wrap Shortest 216 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 7 GFXRENDERSTATE_MAP_INFO The Mapping Engine is capable of fetching texels from at most two maps per pixel This instruction specifies the attributes relating
66. event bits Status OR of unmasked Display event bits Leal EES oe 2 Note that the display line compare is also used through the instruction parser packet interface S ema o resend SSS gt Rees o 2 Reed SSS 1 User Defined Interrupt The Instruction Parser passed a user defined interrupt packet This is intended to be used with another mechanism e g STOREDW instruction to determine the source of the packet to generate the store dword In addition to the HWSTAM register the corresponding bit in the IMR Interrupt Mask Register Offset O20A8h must also be unmasked to halt the parsing of further commands At the break point command packet if both the HWSTAM and IMR are unmasked the command parser will stop processing further commands until the breakpoint bit in the IIR Interrupt Identity Register Offset O20A4h is cleared Breakpoint The Instruction Parser parsed a breakpoint interrupt packet The GFXCMDPARSER_BREAKPOINT_INTERRUPT packet can be used to generate a store dword cycle from the command streamer to main memory and halt the parsing of further commands The HWSTAM Hardware Status Mask Register Offset 02098h must have the break point bit unmasked 321 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 2 1 HWSTAM Hardware Status Mask Register Address Offset 02098h Default Value FFFFh Access Read Write Size 16 bits This register has the same format as the Interrupt Control Reg
67. for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 376 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 377 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 720x400_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 378 35 135 5 MHz Dot Clock Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for
68. in system cacheable memory and either is small or only accessed once it can be copied directly to the instruction stream versus to graphics accessible memory e The IMMEDIATE BLT data MUST transfer an even number of DWs The BLT engine will hang if it does not get an even number of DWs e Monochrome source data is sent through the instruction stream e All monochrome source scan lines and pixels that fall within the ClipRect Y addresses and X coordinates are written ignoring the raster operation to Destination Y Address Destination X coordinate bytes per pixel Source expansion color registers are always in the SETUP_BLT Come e e SE o Bit 0 Byte 1 packed Byte packing is for the Windows NT driver 15 00 Dword Length 02 DWL Number of Immediate double words h 1 BRO8 31 16 Destination X2 Coordinate Ending Right 27 16 12 bits are implemented in the Intel 815 chipset 15 00 Destination X1 coordinate Starting Left X2 X1 1 width in pixels 11 00 12 bits are implemented in the Intel 815 chipset 2 BR09 31 00 Destination Y1 Address address of the first pixel on the first scan line 25 00 are implemented in Intel 810 chipset 3 BR10 31 00 Destination Y2 Address address of the first pixel on the last scan line 25 00 are implemented in Intel 810 chipset 31 00 Immediate Data DW 1 6 thru DWL 3 Immediate Data DWs 2 through DWORD_LENGTH DWL 169 Intel 815 Chipset Graphics C
69. in the Color Expansion Background Color Register 3 Reserved Must be Zero 29 Monochrome Source Transparency Mode This bit applies only when the source data is in monochrome This bit determines whether or not the byte s at the destination corresponding to the pixel to which a given bit of the source data also corresponds will actually be written if that source data bit has the value of 0 This feature can make it possible to use the source as a transparency mask The BLT Engine is configured to accepted either monochrome or color source data via the opcode field 0 This causes normal operation with regard to the use of the source data Wherever a bit in the source data has the value of 0 the color specified in the background color register is used as the source operand in the bit wise operation for the pixel corresponding to the source data bit and the bytes at the destination corresponding to that pixel are written with the result Wher a bit in the source data has the value of 0 the byte s at the destination corresponding to the pixel to which the source data bit also corresponds are simply not written and the data at those byte s at the destination are allowed to remain unchanged 186 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Descriptions Monochrome Pattern Transparency Mode This bit applies only when the pattern data is monochrome This bit determines whether or not the byte s at the destination corres
70. loaded through the command packet that uses it Similarly color patterns with color depths of 8 16 and 32 bits per pixel must start on 64 byte 128 byte and 256 byte boundaries respectively Color patterns with color depths of 24 bits per pixel must start on 256 byte boundaries despite the fact that the actual color data fills only 3 bytes per pixel The next 4 figures show how monochrome 8bpp 16bpp 24bpp and 32bpp pattern data respectively is organized in memory Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Figure 15 8bpp Pattern Data Occupies 64 Bytes 8 quadwords 63 57 56 48 47 40 39 32 31 24 23 16 15 8 7 0 Pixel 0 7 Pixel 0 O OOh 08h 10h 18h 20h 28h 30h Pixel 7 7 Pixel 7 O 38h b_blt9 vsd Figure 16 16bpp Pattern Data Occupies 128 Bytes 16 quadwords 63 48 47 32 31 16 15 0 Pixel 0 0 00h a eared eS i ial 68h Pixel 0 7 70h Pixel 7 7 78h b_blt10 vsd Figure 17 24bpp Pattern Data Occupies 256 Bytes 32 quadwords 48 47 40 39 32 31 24 23 16 15 Pixel 0 0 Green Blue Pixel 7 0 Red Green Blue Throw Away Fourth Bytes for Pixels 0 0 Through 7 0 Pixel 0 7 Red Green Blue Pixel 7 7 Green Blue Throw Away Fourth Bytes for Pixels 0 7 Through 7 7 b_blit11 vsc 61 Intel 815 Chipset Graphics Controller PRM Rev 1 0 6 2 5 62 Fig
71. modes 16 and 24 bit It is necessary to program the palette first with the gamma adjusted values There is only one palette so if both 3 2 are set they have the same gamma adjustments Typical code and typical drivers leave these bits as zero 20 3 2 BLTCNTL BLT Control Memory Offset Address 7000Ch Default 0000h Attributes Read Write Reserved BLT Status E BLT Status RO This read only bit reflects the busy status of BLT Engine only 0 Idle default 1 Busy 20 3 3 SWF 1 3 Software Flag Registers Memory Offset Address SWF1 70014h SWF2 70018h SWF3 7001Ch Default 00000000h Attributes Read Write These 32 bit registers are used as scratch pad space in BIOS and have no effect on hardware 357 Intel 815 Chipset Graphics Controller PRM Rev 1 0 20 3 4 _DPLYBASE Display Base Address Register Memory Offset Address 70020h Default 0000h Attributes Read Write The display can be read from graphics memory This register is the display staging register when written The load register is transferred into the active register on the asserting edge of Vertical Sync The read back register is from the active register 31 26 25 3 2 0 E 31 26 Reserved Bits lt 27 26 gt are implemented as scratch bits Display Base Address Bits 25 03 This is the base address of the display 358 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 20 3 5 DPLYSTAS Display
72. pipelined and the render pipe is flushed before such a state variable is updated All the other state variables are pipelined default 3DPrim 3DStateMW 011 Opcode 11101 23 16 15 0 DWord Count Multiple Sub Opcode DWord 00h 7Fh 150 intel Table 13 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Graphics Controller Instructions 00h Command Parser 02h 2D Processor Instruction GFXCMDPARSER_NOP_IDENTIFICATION GFXCMDPARSER_BREAKPOINT_INTERRUPT GFXCMDPARSER_USER_INTERRUPT GFXCMDPARSER_WAIT_FOR_EVENT GFXCMDPARSER_FLUSH GFXCMDPARSER_CONTEXT_SEL GFXCMDPARSER_DEST_BUFFER_INFO GFXCMDPARSER _FRONT_BUFFER_INFO GFXCMDPARSER _Z_BUFFER_INFO GFXCMDPARSER_REPORT_HEAD GFXCMDPARSER_ARB_ON_OFF GFXCMDPARSER _DEST_BUFFER_INFO GFXCMDPARSER_OVERLAY_FLIP GFXCMDPARSER_LOAD_SCAN_LINES_INCL GFXCMDPARSER_LOAD_SCAN_LINES_EXCL GFXCMDPARSER_STORE_DWORD_IMM GFXCMDPARSER_STORE_DWORD_INDEX GFXCMDPARSER_BATCH_BUFFER SETUP_BLT SETUP_MONO_PATTERN_SL_BLT PIXEL_BLT SCANLINE_BLT TEXT_BLT TEXT_Immediate_BLT COLOR_BLT PAT_BLT MONO_PAT_BLT SRC_COPY_BLT MONO_SRC_COPY_BLT MONO_SRC_COPY_Immediate_BLT FULL_BLT FULL_MONO_SRC_BLT FULL_MONO_PATTERN_BLT FULL_MONO_PATTERN_MONO_SRC_BLT 151 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Table 13 Graphics Controller Instructions Client Instruction 03h Rendering Processor GFXPRIMITIVE GFXBLOCK GFXRENDERSTATE_VERTEX_FORMAT GFXRENDERSTATE_MAP_TEXEL
73. range IEEE float Tv 1 Texture coordinates Data valid over entire IEEE floating point range IEEE float 208 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 2 GFXRENDERSTATE_VERTEX_FORMAT Flexible Vertex Format Packet 31 29 Client 03h Render Processor 28 24 3DState24 05h 23 12 Reserved 00h B Texture Coordinate Count This field identifies how many coordinates are present in the vertex The valid range is 0 2 6 bituseColransAbnerreset O Z Offset Present Reserved 00h DX6 Normal Vector Present Bit 3 Position Mask Oh Invalid 1h XYZ Present RHW not present 2h XYZRHW Present 3h XY Present RHW and Z not present 4h XYRHW Present Z not present 5h 7h Reserved o Reserved 00h 1 209 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 3 210 intel GFXBLOCK The GFXBLOCK instruction is used with Motion Compensation It is a variable length instruction which contains intra coded correction data at the end of the instruction The DWORD_ LENGTH must correspond to the Block Pattern Bits that identify which quadrants of the block have associated correction data When the horizontal or vertical block pattern are disabled the block pattern bits are assumed to be set All of the block pattern bits must also be set when the Prediction Type is intra coded Having no correction data is also valid to enable support for skipped blocks When the Block
74. raster operation The pattern vertical alignment indicates on which byte to start The horizontal alignment is relative to the destination from the lower bits of the destination address The monochrome pattern transparency mode indicates whether to use the pattern background color or deassert the write enables when the bit in the pattern is 0 When the pattern bit is 1 then the pattern foreground color is used in the ROP operation The ROP value chosen should involve the Mono pattern data in the ROP operation e Only a positive destination pitch is allowed ones ee Pes 1 BR13 31 29 Reserved Must be Zero she Pattern Transparency Mode 1 transparency enabled use background a Reserved Must be Zero Must Be One 1 25 24 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color eeo o reserved 23 16 Raster Raster Operation 15 00 Destination Pitch positive 13 00 are implemented in Intel 810 chipset 2 BR14 31 16 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BR09 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset 172 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 10 SRC_COPY_BLT This BLT instruction performs a color source copy where the only operands involved is a color s
75. register with the M REG value and N REG value 2 Write the clock 1 byte of the Display amp LCD Clock Divisor Select Register with the P REG value 3 Write the MSR register bits 3 2 01 to select DCLK1 257 Intel 815 Chipset Graphics Controller PRM Rev 1 0 14 2 258 intel Example Programming Sequence DCLK2 1 Write the Display Clock 2 Divisor register with the M REG value and N REG value 2 Write the clock 2 byte of the Display amp LCD Clock Divisor Select Register with the P REG value 3 Write the MSR register bit 3 1 to select DCLK2 Example Programming Sequence LCD CLK 1 Write the LCD clock Divisor register with the M REG value and N REG value 2 Write the LCD byte of the Display amp LCD Clock divisor Select Register with the P REG value 3 Write the LCD TV Out Control 31 1 and 0 1 MSR 3 2 are ignored when this condition is true DCLK_0D Display Clock 0 Divisor Register Address Offset 06000h 06003h Default Value 00030013h Attribute R W Size 32 bits The Display Clock 0 Divisor register and the Display amp LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer Data is written to the Display Clock 0 Divisor register followed by a write to the Clock 0 byte of the Display amp LCD Clock Divisor Select Register The completion of the write to the Display amp LCD Clock Divisor Select Register causes data from both r
76. ring buffer start at MM 0x2038 but preserve the reserved bits Restore the Low Priority Ring Buffer Length field but preserve the Automatic Report Header Pointer bits and set the Ring Buffer Valid flag Turn on the screen Relock the protected register space in order to complete the state restoration process At this point the graphics adapter should function completely in the mode identified by the saved state information 51 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 52 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 6 Bit Engine Programming 6 1 BLT Engine Programming Considerations 6 1 1 When the Source and Destination Locations Overlap It is possible to have BLT operations in which the locations of the source and destination data overlap This frequently occurs in BLT operations where a user is shifting the position of a graphical item on the display by only a few pixels In these situations the BLT engine must be programmed so that destination data is not written into destination locations that overlap with source locations before the source data at those locations has been read Otherwise the source data will become corrupted The following figure shows how the source data can be corrupted when a rectangular block is copied from a source location to an overlapping destination location The BLT engine reads from the source location and writes to
77. sent after the LOAD_SCAN_LINES instruction If executed out of a batch buffer this instruction will cause the parser to halt and wait if the scan_line_window indicator is asserted If the scan line window indicator is de asserted the parser just moves on If executed out of a ring buffer the Parser sets a flag if the scan line window indicator is asserted This flag eliminates that ring from the arbitration until the it is cleared This flag is cleared by the trailing edge of the scan_line_window indicator If the scan line window indicator is deasserted the flag is not set and the parser moves on For more information look at the load_scan_line packet 155 Intel 815 Chipset Graphics Controller PRM Rev 1 0 11 2 5 GFXCMDPARSER_FLUSH This instruction will flush all drawing engines and the frame buffer cache a k a local cache In addition it will conditionally invalidate the map cache After this instruction is completed and followed by a store DWord processor access to graphics memory will be coherent a O O 7 31 29 Client 000 Instruction Parser 28 23 Opcode 04h Reserved 000000h ne INVALIDATE_MAP_CACHE When this bit is set the parser will wait until the rendering pipeline is done and then invalidate the mapping engine cache 11 2 6 GFXCMDPARSER_CONTEXT _SEL The GFXCMDPARSER CONTEXT SEL instruction is used to inform the input interface to load or use one of two sets of state variables The Pipeline support
78. suggests a connection to the enabling or disabling the graphics system 79 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 1 1 ST00 Input Status 0 I O and Memory Offset Address 3C2h Default 00h Attributes Read Only 7 6 5 4 3 0 CRT Int Reserved 00 RGB Cmp Reserved 0000 Sen a e CRT Interrupt Pending Note that the generation of interrupts can be enabled through bits 4 5 of the Vertical Retrace End Register CR11 This ability to generate interrupts at the start of the vertical retrace interval is a feature that is typically unused by current software This bit is here for EGA compatibility 0 CRT vertical retrace interval interrupt is not pending 1 CRT vertical retrace interval interrupt is pending a Reserved Read as Os RGB Comparator Sense This bit returns the state of the output of the RGB output comparator s BIOS uses this bit to determine whether the display is a color or monochrome CRT 0 Monochrome 1 Color BIOS blanks the screen or clears the frame buffer to display only black Next BIOS configures the D to A converters and the comparators to test for the presence of a color display Finally if the BIOS does not detect any colors it tests for the presence of a display The result of each such test is read via this bit Reserved Read as Os 80 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 1 2 ST01 nput Status 1 I O and Memory Off
79. supports pipelining of up to 4 outstanding transaction requests on the host bus Host bus addresses are decoded by the GMCH for accesses to system memory PCI memory and PCI I O via hub interface PCI configuration space and Graphics memory The GMCH takes advantage of the pipelined addressing capability of the processor to improve the overall system performance The Intel 82815 chipset GMCH supports the 370 pin socket processor 19 Intel 815 Chipset Graphics Controller PRM Rev 1 0 2 2 2 2 2 3 20 intel e 370 pin socket PGA370 The PGA370 is a zero insertion force ZIF socket that a processor in the FC PGA package will use to interface with a system board System Memory Interface The GMCH integrates a system memory controller that supports a 64 bit 100 133 MHz SDRAM array The only DRAM type supported is industry standard Synchronous DRAM SDRAM The SDRAM controller interface is fully configurable through a set of control registers The GMCH supports industry standard 64 bit wide DIMMs with SDRAM devices The thirteen multiplexed address lines SMAA 12 0 along with the two bank select lines SBS 1 0 allow the GMCH to support 2M 4M 8M 16M and 32M x64 DIMMs Only asymmetric addressing is supported The GMCH has six SCS lines two copies of each for electrical loading enabling the support of up to six 64 bit rows of SDRAM The GMCH targets SDRAM with CL2 and CL3 and supports both single and double sided
80. table above The Memory Read Latch Data register and this additional function served by 2 bits are features of the VGA standard that were never documented by IBM 9 3 7 GR05 Graphics Mode Register I O and Memory Offset Address 3CFh Index 05h Default OUUU U0UUb U Undefined Attributes Read Write Reserved Shift Register Control Odd Even Read Reserved Write Mode 0 Mode 0 E Reserved Read as Os 93 Intel 815 Chipset Graphics Controller PRM Rev 1 0 94 Description Shift Register Control In standard VGA modes pixel data is transferred from the 4 graphics memory planes to the palette via a set of 4 serial output bits These 2 bits of this register control the format in which data in the 4 memory planes is serialized for these transfers to the palette Bits 6 5 00 One bit of data at a time from parallel bytes in each of the 4 memory planes is transferred to the palette via the 4 serial output bits with 1 of each of the serial output bits corresponding to a memory plane This provides a 4 bit value on each transfer for 1 pixel making possible a choice of 1 of 16 colors per pixel Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer Bit3 plane 3 bit7 plane 3bit6 plane3bit5 plane 3 bit4 plane 3 bit3 plane 3 bit2 plane 3 bit1 plane 3 bit O Bit2 plane 2 bit7 plane2bit6 plane2bit5 plane 2 bit4 plane 2 bit3 plane 2 bit2 plane 2 bit 1 plane 2 bit O Bit1 plane 1 bit7 plane 1bit6 plan
81. the DDDA DATA VALUE bit 0 Pin is configured as an input default 1 Pin is configured as an output 348 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description DDDA Direction Mask R W This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the register 0 Do NOT write DDDA Direction Value bit default 1 Write DDDA Direction Value bit The Data In bits 12 4 of the GPIOA register are read only however data is only latched into these bits when a write is done to the respective bytes of the GPIOA register Thus a read of the Data In bits must be preceded with a dummy write DDCK Data Value R W This is the value that should be place on the DDCK pin as an output This value is only written into the register if DDCK DATA MASK is also asserted The value will appear on the pin if this data value is actually written to this register and the DDCK DIRECTION VALUE contains a value that will configure the pin as an output DDCK Data Mask R W This is a mask bit to determine whether the DDCK DATA VALUE bit should be written into the register 0 Do NOT write DDCK Data Value bit default 1 Write DDCK Data Value bit DDCK Direction Value R W This is the value that should be used to define the ouput enable of the GPIOO pin This value is only written into the register if DDCK DIRECTION MASK is also asserted The value that will appear on the pin is defined by
82. the bytes at the destination corresponding to that pixel are written with the result Wherever a bit in the pattern data has the value of 0 the byte s at the destination corresponding to the pixel to which the pattern data bit also corresponds are simply not written and the data at those byte s at the destination are allowed to remain unchanged Source Select Mode Configures the BLT Engine to read the source data from the frame buffer at the location specified in the Source Address Register Configures the BLT Engine to accept the source data from the instruction stream controller through the IMMEDIATE_BLT instruction The BLT Engine will hang if it does not get an even number of DWs 00 8 Bit Color Depth 01 16 Bit Color Depth 10 24 Bit Color Depth 11 Reserved Raster Operation Select These 8 bits are used to select which one of 256 possible raster operations is to be performed by the BLT Engine The 8 bit values and their corresponding raster operations are intended to correspond to the 256 possible raster operations specified for graphics device drivers in the Microsoft Windows environment The opcode must indicate a monochrome source operand if ROP FO 15 14 Reserved Must be Zero 13 0 Destination Pitch Offset These 14 bits store the signed memory address offset value by which the destination address originally specified in the Destination Address Register is incremented or decremented as each scan line s
83. the destination location starting with the left most pixel in the top most line of both as shown in step a As shown in step b corruption of the source data has already started with the copying of the top most line in step a part of the source that originally contained lighter colored pixels has now been overwritten with darker colored pixels More source data corruption occurs as steps b through d are performed At step e another line of the source data is read but the two right most pixels of this line are in the region where the source and destination locations overlap and where the source has already been overwritten as a result of the copying of the top most line in step a Starting in step f darker colored pixels can be seen in the destination where lighter colored pixels should be This errant effect occurs repeatedly throughout the remaining steps in this BLT operation As more lines are copied from the source location to the destination location it becomes clear that the end result is not what was originally intended 53 Intel 815 Chipset Graphics Controller PRM Rev 1 0 54 Figure 9 intel Source Corruption in BLT with Overlapping Source and Destination Locations Source Destination Source Destination b_blit2 vsd Figure 10 Intel 815 Chipset Graphics Controller PRM Rev 1 0 The BLT engine can alter the order in which source data is read and destination data i
84. the row scan counter RSOut and RSOut0 before finally being presented to the input bits of the frame buffer address decoder FBIn15 FBIn0 128 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Table 10 Memory Address Counter Address Bits 15 0 Byte Mode Word Mode Word Mode DWord Mode CR14 bit 6 0 CR14 bit 6 0 CR14 bit 6 0 CR14 bit 6 1 CR17 bit 6 1 CR17 bit 6 0 CR17 bit 6 0 CR17 bit 6 X CR17 bit 5 X CR17 bit 5 1 CR17 bit 5 0 CR17 bit 5 X MAOutO MAOut1 MAOut2 MAOut3 MAOut4 MAOut5 MAOut6 MAOut7 MAOut8 MAOut9 MAOut10 MAOut11 MAOut12 MAOut13 MAOut14 MAOut15 X Don t Care 129 Intel 815 Chipset Graphics Controller PRM Rev 1 0 130 Table 11 Frame Buffer Address Decoder FBInO FBIn1 FBIn2 FBIn3 FBIn4 FBIn5 FBIn6 FBIn7 FBIn8 FBIn9 FBIn10 FBIn11 FBIn12 FBIn13 FBIn14 FBIn15 CR17 bit 1 1 CR17 bit 0 1 MAOutO MAOut1 MAOut2 MAOut3 MAOut4 MAOut5 MAOut6 MAOut8 MAOut9 MAOut10 MAOut11 MAOut12 MAOut13 MAOut14 MAOut15 MAOut7 CR17 bit 1 1 CR17 bit 1 0 CR17 bit 1 0 CR17 bit 0 0 ORTHO Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 26 CR18 Line Compare Register I O and Memory Offset Address 3B5h 3D5h index 18h Default Undefined Attributes Read Write en Line Compare Bits 7 0 This register provides the 8 least significant bits of a 10 bit value that specifies the scan line at which the memory address count
85. this register Lock Dot Clock PLL N M Regs to a 0 which allows normal programming of the Dot Clock PLL registers This bit should be disabled when driving a TV 27 17 Reserved MBZ 14 FP 740 Data Ordering 0 740 Compliant Data Ordering 1 Flat Panel Data Ordering R 7 0 G 7 4 followed by G 3 0 B 7 0 LCD Information Data Enable When enabled transfers data from GC to the external device during Vertical sync This transfer should be qualified by blank signal 0 Disable 1 Enable Currently planned for Debug purposes FPHSYNC Control 1 FPHSYNC is disabled elf in FP VESA VGA Mode then this pin goes to the level of the VGA HSYNC when disabled elf not in FP VESA VGA Mode then this pin goes is in the deasserted state as specified by the HSYNC Polarity Control field 0 FPHSYNC is enabled eWhen in FP VESA VGA Mode then the VGA timing generator is the source of this signal eWhen not in FP VESA VGA Mode then the source of this signal is this timing generator FPVSYNC Output Control 1 Tristates the FPVSYNC pin 0 FPVSYNC is active unless LCD TV Out Enable is deasserted Though this bit is provided the GC always use VSYNC as output 11 FPVSYNC Control 1 FPVSYNC is disabled elf in FP VESA VGA Mode then this pin goes to the level of the VGA VSYNC when disabled elf not in FP VESA VGA Mode then this pin goes is in the deasserted state as specified by the VSYNC Polarity Control field 0
86. to be read When the source data is provided by IMMEDIATE_BLT instruction these 14 bits store the number of bytes to be counted from the beginning of a scan line s worth of data to where the next scan line s worth of data begins Note that if the intended source of a BLT operation is within on screen frame buffer memory this offset is normally set to accommodate the fact that each subsequent scan line s worth of source data lines up vertically with the source data in the scan line above However if the intended source of a BLT operation is within off screen memory this offset can be set to accommodate a situation in which the source data exists as a single contiguous block of bytes where in each subsequent scan line s worth of source data is stored at a location immediately after the location where the source data for the last scan line ended When monochrome source data is being processed this field is used for indicating the total number of Quadwords of data in the source data stream Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 13 BR12 Source Address Memory Offset Address 40030h Default None Attributes RO DWord accessible 26 25 31 Reserved Must Source Address Bits 25 0 be Zero p e 31 26 Reserved Must be Zero The maximum GC Graphics address is 64 MBs 25 0 Source Address Bits 25 0 These 26 bits are used to specify the starting pixel address of the color source data
87. toward the bottom such that a Y value of 0 0 would specify the center of a pixel texel 15 14 Reserved 00h 13 12 4 2 2 Channel Write Select Select which channel s are written to the destination buffer when the surface format is 4 2 2 using byte masks 00 Write all channels Y Cr and Cb 01 Write only the Y channel 10 Write only the Cr channel 11 Write only the Cb channel Reserved Additional Buffer Formats 10 8 Dest Buffer Format Oh Any 8 bit Surface 1h RGB 555 16th bit is written as 0 2h RGB 565 3h Reserved ARGB 8888 4h 4 2 2 YCrCb Y Swap format in memory 5h 4 2 2 YcrCb Normal format in memory 6h 4 2 2 YcrCb UV Swap format in memory 7h 4 2 2 YerCb UV Y Swap format in memory Reserved 00h 1 Vertical Line Stride The number of lines to skip between logically adjacent lines 0 Do not skip any lines 1 Skip 1 line provides support for Interleaved field surfaces B Vertical Line Stride Offset The number of lines to add as an initial offset when the Vertical Line Stride is 1 0 Add no offset top field 1 Add 1 bottom field 252 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 29 Programming Hints Rules The following provides programming hints rules for 3D Motion Compensation and Stretch Blitter operations Drawing and Scissor Rectangles e Must declare a Drawing Rectangle packet first before Scissor Rectangle packet e Coordinates of Drawing Rectangle mus
88. transparency Pattern Vertical Alignment Specifies which scan line s worth which 1 of the 8 horizontal rows of the 8x8 pattern will appear on the first scan line s worth of the data written to the destination Depending upon the location of the destination the upper left hand corner of the upper left hand tile of the pattern is usually aligned with the upper left hand corner of the block of data written to the destination The BLT Engine determines the horizontal alignment relative to the destination from the lower bits of the destination address however the vertical alignment relative to the destination must be supplied through these bits Destination Read Modify Write This bit is decoded from the last instruction s opcode field and Destination Transparency Mode to identify whether a Destination read is needed 3 Color Source This bit is decoded from the last instructions opcode field to identify whether a color 1 source is used Monochrome Source This bit is decoded from the last instructions opcode field to identify whether a monochrome 1 source is used 1 pattern is used Color Pattern This bit is decoded from the last instructions opcode field to identify whether a color Monochrome Pattern This bit is decoded from the last instructions opcode field to identify whether a monochrome 1 pattern is used 185 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 2 _BR01 Setup BLT Raster OP Contr
89. use of GFXCMDPARSER_ BATCH BUFFER instructions that specify the starting address and length of the batch buffers For detailed information on these buffers refer to the Programming Interface Chapter Note Intel 815 Chipset Graphics Controller PRM Rev 1 0 Graphics Translation Table GTT Range Definition Address Offset 10000h FFFFh Default Value Page table range 64 KB Access aligned DWord QWord Write Only This range defined within the graphics memory mapped register space is for the memory manager to access the graphics translation table A page table write will invalidate that entry in internal translation table caches TLBs The translation table resided in system memory and can be accessed by the memory manager directly However to ensure coherency between hardware maintained translation caches and the translation table in main memory the memory manager must use this range to update the translation table The page table is required to be QW aligned with each entry being DWord aligned such that each QW stores the translation for 2 4 KB pages Page Table base address for graphics memory is programmed in the PGTB_CNTL register For graphics memory of 64 MB with a TLB block size of 4 KB 16K entries are needed Each entry is 4 bytes hence the page table size is 64 KB Page Table Entry 1 DWord per 4 KB page 31 30 29 12 11 3 2 1 0 V 1 Valid page table entry PTE 0 Invalid page table entry PTE An access t
90. used for ChromaKey or ColorKey The color of texel 1 is not subject to texture color chroma key Filtering and use of texel 1 if enabled proceeds normally irrespective of color chroma key Kill Pixel Mode This is the default function for texture color chroma key in D3D Prior to DX7 it was the only function Pixels whose sampled texels are considered matching the color chroma key are killed discarded and not drawn regardless of any subsequent pipeline operations The Intel 810 chipset implementation of the matching criteria is somewhat different than the D3D reference rasterizer behavior introduced in DX6 1 DX6 1 will kill the pixel if any contributing sampled texels match the key Here contributing is defined as having an non zero filter beta weight as opposed to non contributing texels that may be sampled fetched but effectively not used This behavior tends to enlarge keyed out areas depending on the size of the filter The Intel 810 chipset implementation only kills a pixel if the nearest neighbor sampled texel matches the key Non nearest neighbor texels matching the key are effectively replaced by the nearest neighbor s color alpha and then used in the filter This behavior avoids the enlargement of keyed out areas The Intel 815 chipset supports both Kill Pixel modes The default is the DX6 1 implementation Blend Mode This mode was intended to support the BLENDCOLORKEY D3D
91. was therefore deemed too confusing hence the Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 2 2 SR00 Sequencer Reset I O and Memory Offset Address 3C5h Index 00h Default 00h Attributes Read Write Reserved 000000 Reserved Reserved scratch scratch bit bit Reserved Read as 000000 Write has no effect hardware Read Write scratch bit required for VGA compatibility Read previously written value Write stores written value This bit is a fully readable writeable MMIO location in the hardware It has no other functionality in the hardware 1 Read Write scratch bit required for VGA compatibility Read previously written value Write stores written value This bit is a fully readable writeable MMIO location in the hardware It has no other functionality in the Programming Hints e It has been noted that legacy Video BIOS code has the bits 1 0 programmed to 11 values for reason not fully understood Experiment was done on 810 Video BIOS with leaving these 2 bits at the default values It was found that full screen DOS box mode does not behave properly in that case However with Video BIOS programming up the bits to 11 values the problem was corrected 85 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 2 3 86 SR01 Clocking Mode I O and Memory Offset Address 3C5h Index 01h Default 00h Attributes Read Write Es Reserved Read as Os Screen O
92. what is in the register for the DDCK DATA VALUE bit 0 Pin is configured as an input default 1 Pin is configured as an output GPIO0 Direction Mask R W This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the register 0 Do NOT write DDCK Direction Value bit default 1 Write DDCK Direction Value bit 349 Intel 815 Chipset Graphics Controller PRM Rev 1 0 19 2 2 GPlOB General Purpose I O Control Register B Address offset 05014h Default value 00h 00h OOOUD000b 000U0000b ACCESS Read write Size 32 bit This register controls the general purpose I O pins LTVCK and LTVDA which are used to create an I C connection to the external Digital Video Out controller 31 16 15 13 12 11 10 9 8 Reserved LTVDA LTVDA LTVDA LTVDA LTVDA Data In Data value Data mask Direction Direction value Mask Reserved LTVCK LTVCK LTVCK LTVCK LTVCK Data In Data value Data mask Direction Direction value Mask ee 31 16 Reserved 15 13 Reserved LTVDA Data In RO This is the value that is sampled on the LTVDA pin as an input The Data In bits 12 4 of the GPIOA GPIOB register are read only however data is only latched into these bits when a write is done to the respective bytes of the GPIOA GPIOB register Thus a read of the Data In bits must be preceded with a dummy write LTVDA Data Value R W This is the value that should be place on the LTVDA pin
93. worth of destination data is written into the frame buffer by the BLT Engine so that the destination address will point to the next memory address to which the next scan line s worth of destination data is to be written If the intended destination of a BLT operation is within on screen frame buffer memory this offset is normally set so that each subsequent scan line s worth of destination data lines up vertically with the destination data in the scan line above However if the intended destination of a BLT operation is within off screen memory this offset can be set so that each subsequent scan line s worth of destination data is stored at a location immediately after the location where the destination data for the last scan line ended in order to create a single contiguous block of bytes of destination data at the destination 197 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 15 BR14 Destination Width amp Height 198 Memory Offset Address 40038h Default None Attributes RO DWord accessible BR14 contains the values for the height and width of the data to be BLT If these values are not correct such that the BLT Engine is either expecting data it does not receive or receives data it did not expect the system can hang 31 29 28 16 Reserved Must Destination Height be Zero Reserved Must Destination Byte Width be Zero ee 31 29 Reserved Must be Zero Destination Height These 13 bits specif
94. 0 Do Not Update Source Z Bias Enable 1 Enable 0 Disable default Specular Enable State Mask 1 Update 0 Do Not Update Specular Enable 1 Enable 0 Disable default Fog Enable State Mask 1 Update 0 Do Not Update Fog Enable 1 Enable 0 Disable default Alpha Enable State Mask 1 Update 0 Do Not Update Alpha Test Enable 1 Enable 0 Disable default Blend Enable State Mask 1 Update 0 Do Not Update I I I I I ne ll I I I I Es I Blend Enable 1 Enable 0 Disable default Z Enable State Mask 1 Update 0 Do Not Update Z Enable 1 Enable 0 Disable default 241 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 20 242 GFXRENDERSTATE_BOOLEAN_ENA_2 es ee 7 6 5 4 3 2 1 0 4 Mapping Cache Enable Mask 1 Update 0 Do Not Update Mapping Cache Enable 1 Enable 0 Disable default Any change made to the Mapping Cache Enable state variable must be followed by a GFXCMDPARSER_FLUSH instruction to cause the hardware to flush the 3D pipeline Alpha Dither Enable Mask 1 Update 0 Do Not Update ae Specular Dither Enable Mask 1 Update 0 Do Not Update Specular Dither Enable 1 Enable 0 Disable default Color Dither Enable Mask 1 Update 0 Do Not Update Color Dither Enable 1 Enable 0 Disable default Frame Buffer Write Enable Mask 1 Update 0 Do Not Update Frame Buffer Write Enable
95. 0 Down Interpolation 111 Reserved Mirroring Mirroring affects the buffer address values used See buffer address description for details 00 Normal 01 Horizontal Mirroring 10 Vertical Mirroring 11 Both Horizontal and vertical Y adjust Defines the range of Y and UV values in the source data This bit is only has an effect in YUV formats 0 Y 0 255 UV 128 1 Y 16 235 UV 112 UV source values are always in excess 128 format 295 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description 4 2 2 Byte Order Affects the byte order for 4 2 2 data For other data formats these bits should be set to zero 00 Normal 01 UV Swap 10 Y Swap 11 Y and UV swap Source Format 0000 Reserved 0001 Reserved 0010 RGB 5 5 5 0011 RGB 5 6 5 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 YUV 4 2 2 1001 YUV 4 1 1 1010 Reserved 1011 Reserved 1100 YUV 4 2 0 MPEG 1 or 2 1101 Reserved 1110 YUV 4 1 0 1111 Reserved Flip TV Out Field Select Selects which TV Out field polarity for flips 0 Between FO and F1 1 Between F1 and FO Flip Qualification Flip Qualification amp Display VBLANkK Flips can be caused automatically by the capture port logic on the completion of a field or frame capture This event will be synchronized either with the display overlay VBLANK event or the display overlay VBLANK event combined with the current TV field M
96. 0 Protection register Instruction IP MBZ Description The GMCH is using its capability to interface with and AGP card The internal graphics controller is disabled in this mode Graphics Performance Accelerator Card This is a new implementation which allows local memory devices to be placed on a card that plugs into the AGP slot When an AGP card is not present an GPA card can be added to improve performance by acting as a display cache for the Z buffer only of up to 4 MB The GPA card was previously known as the AIMM Add In Memory Module Command Stream Interface same as instruction stream interface Graphics Controller The GMCH is using its internal graphics capability This means that the ability to interface with an AGP card is disabled The Graphics and Memory Controller Hub component that contains the functionality of an MCH plus an internal graphics controller As per the original IBM VGA specification CRT Controller registers CR 0 7 can be write protected via CR11 bit 7 In BIOS code this write protection is set following each mode change Note that other group protection levels have no current use and are not supported by the GC Only Group 0 Protection is supported The GC has a set of graphics instructions In some documents the term command is used for instruction Instruction Parser Must Be Zero 15 Intel 815 Chipset Graphics Controller PRM Rev 1 0 1 2 16 Term MCH MM MM
97. 00 pixels e The GMCH provides a Digital Video Out interface to connect an external device to drive a 1280x1024 resolution non scalar DDP digital Flat Panel with appropriate EDID 1 2 data or digital CRTs The interface has 1 8V signaling to allow it to operate at higher frequencies This interface can also connect to a 1 8V TV Out encoder 21 Intel 815 Chipset Graphics Controller PRM Rev 1 0 2 2 6 Table 1 2 2 4 2 3 22 Note System Clocking intel The Intel 82815 chipset GMCH has a new type of clocking architecture It has integrated SDRAM buffers that run at either 100 or 133 MHz independent of the system bus frequency See table below for supported system bus and system memory bus frequencies The system bus frequency is selectable between 66 MHz 100 MHz or 133 MHz The GMCH uses a copy of the USB clock as the DOT Clock input for the graphics pixel clock PLL Supported System Bus and System Memory Bus Frequencies Front Side Bus System Memory Display Cache Interface Frequency Bus Frequency Frequency 66 MHz 100 MHz 133 MHz or DVMT 100 MHz 100 MHz 133 MHz or DVMT 133 MHz 100 MHz 133 MHz or DVMT 133 MHz 133 MHz 133 MHz or DVMT GMCH Power Delivery The Intel 82815 chipset GMCH core voltage is 1 85V System Memory runs off of a 3 3V supply Display cache memory runs off of the AGP 3 3V supply AGP 1X 2X I O can run off of either a 3 3V or a 1 5V supply AGP 4X I O require a
98. 00030013h Attribute R W Size 32 bits The Display Clock 2 Divisor register and Display amp LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer Data is written to Display Clock 2 Divisor register followed by a write to the Clock 2 byte of the Display amp LCD Clock Divisor Select Register The completion of the write to the Display amp LCD Clock Divisor Select Register causes data from both registers to transfer to the VCO register file simul taneously This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence 31 26 25 16 15 10 9 0 25 16 VCO 2 N Divisor N Divisor value calculated for the desired output frequency default 03h so VCO 2 M Divisor M Divisor value calculated for the desired output frequency default 13h Intel 815 Chipset Graphics Controller PRM Rev 1 0 LCD_CLKD LCD Clock Divisor Register Address Offset 0600Ch 0600Fh Default Value 00030013h Attribute R W Size 32 bits The LCD Clock Divisor register and Display amp LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer Data is written to LCD Clock Divisor register followed by a write to the LCD Clock byte of the Display amp LCD Clock Divisor Select Register The completion of the write to the Display amp LCD Clock Divisor Select Register causes data from bot
99. 000h 03FFFh Reserved 04000h 04FFFh 04000h 04FFFh Reseed o O I O Control Registers 05000h 05FFFh Clock Control and Power Management Registers 06000h 06FFFh 06000h 06003h DCLK_OD Display Clock 0 Divisor 06004h 06007h DCLK_1D Display Clock 1 Divisor 06008h O0600Bh DCLK_2D Display Clock 2 Divisor W W 0600Ch 0600Fh LCD_CLKD LCD Clock Divisor 06010h 06013h DCLK_ODS Display and LCD Clock Divisor Select 06014h 06017h PWR_CLKC Power Management and Miscellaneous Clock Control Reserved 07000h OFFFFh Graphics Translation Table Range Definition 10000h 1FFFFh 10000h 1FFFFh Graphics Translation Table Range Definition wo Reserved 20000h 2FFFFh R W R W R W R W R W R W 33 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Table 2 Memory Mapped Registers Address Offset Symbol Register Name Access Overlay Registers 30000h 03FFFFh For additional address offsets in the double buffering scheme see Overlay Chapter 30000h 30003h Overlay 0 Register Update Address Overlay 0 R W 30174h 30177h Alpha Blend Window Size 34 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Table 2 Memory Mapped Registers Address Offset Symbol Register Name Access BLT Engine Status 40000h 4FFFFh Software Debug 40000h 40003h BROO BLT Opcode and Control 40004h 40007h BRO1 Setup BLT Raster OP Control and Destination Offset 4002Ch 4002Fh BR11 BLT Source Pitch
100. 0h 09h 03h 00h 02h 00h 0 A3h 2Dh 27h 28h 90h 2Bh AOh BFh 1Fh 00h 4Dh OBh OCh 00h 00h 00h 00h 83h 85h 5Dh 14h 1Fh 63h BAh A3h FFh 00h 09h 03h 00h 02h 00h 0 67h 2Dh 27h 28h 90h 2Bh AOh BFh 1Fh 00h 4Fh ODh OEh 00h 00h 00h 00h 9Ch 8Eh 8Fh 14h 1Fh 96h B9h A3h FFh 00h 08h 03h 00h 02h 00h 63h 2Dh 27h 28h 90h 2Bh AOh BFh 1Fh 00h C7h O6h 07h 00h 00h 00h 00h 9Ch 8Eh 8Fh 14h 1Fh 96h B9h A3h FFh 00h 09h 03h 00h 02h 00h 4 A3h 2Dh 27h 28h 90h 2Bh AOh BFh 1Fh 00h 4Dh OBh OCh 00h 00h 00h 00h 83h 85h 5Dh 14h 1Fh 63h BAh A3h FFh 00h 09h 03h 00h 02h 00h 1 67h 2Dh 27h 28h 90h 2Bh AOh BFh 1Fh 00h 4Fh ODh OEh 00h 00h 00h 00h 9Ch 8Eh 8Fh 14h 1Fh 96h B9h A3h FFh 00h 08h 03h 00h 02h 00h 63h SFh 4Fh 50h 82h 55h 81h BFh 1Fh 00h C7h 06h 07h 00h 00h 00h 00h 9Ch 8Eh 8Fh 28h 1Fh 96h B9h A3h FFh 00h 01h 03h 00h 02h 00h 2 A3h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h 4Dh OBh OCh 00h 00h 00h 00h 83h 85h 5Dh 28h 1Fh 63h BAh A3h FFh 00h 01h 03h 00h 02h 00h 2 67h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h 4Fh ODh OEh 00h 00h 00h 00h 9Ch 8Eh 8Fh 28h 1Fh 96h B9h A3h FFh 00h 00h 03h 00h 02h 00h 63h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h C7h O6h 07h 00h 00h 00h 00h 9Ch 8Eh 8Fh 28h 1Fh 96h B9h A3h FFh 00h 01
101. 1 This functionality only works for a primary display of 16 and 24 bits per pixel pixel R alphaR primary display R 1 alphaR overlay R Constant Alpha Green 7 0 This involves three 4 x 8 bit alpha multipliers to be inserted in the Overlay and Primary Display merging logic When the alpha blend is selected the most significant 4 bits of each alpha channel is used as the alpha term If the original 8 bits of the alpha channel FF the alpha channel value is treated as a 1 If alpha 0 1 0 must also be treated as a 1 This functionality only works for a primary display of 16 and 24 bits per pixel pixel G alphaG primary display G 1 alphaG overlay G 7 0 Constant Alpha Blue 7 0 This involves three 4 x 8 bit alpha multipliers to be inserted in the Overlay and Primary Display merging logic When the alpha blend is selected the most significant 4 bits of each alpha channel is used as the alpha term If the original 8 bits of the alpha channel FF the alpha channel value is treated as a 1 If alpha 0 1 0 must also be treated as a 1 This functionality only works for a primary display of 16 and 24 bits per pixel pixel B alphaB primary display B 1 alphaB overlay B intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 10 Overlay Configuration Registers 15 4 10 1 There is only 1 Overlay Configuration register which controls both overlay streams It is read from
102. 1 2 9 GFXCMDPARSER _Z BUFFER_INFO ccccccccecccesseteteteseteeeseseeeeeees 159 11 2 10 GFXCMDPARSER_REPORT_ HEAD 0 cccccccccceseseseeeceseceseeeeeeeeeeeeeeees 159 11 2 11 GFXCMDPARSER_ARB_ON_ OFF cccccccccececeseceeeeeeececeseceseseeeeeeeeeeees 160 11 2 12 GFXCMDPARSER_OVERLAY_ FLIP cccccccccccccesessceeeceseseceeeseeeseeeseeees 160 11 2 13 GFXCMDPARSER_LOAD_ SCAN LINES _ INCL eeeeeeeeeees 160 11 2 14 GFXCMDPARSER_LOAD_ SCAN LINES EXCL ceeeeeeeeees 161 11 2 15 GFXCMDPARSER_STORE_ DWORD_IMM uu ccc ceceeeeeeeeeeeeeeees 161 11 2 16 GFXCMDPARSER_STORE_DWORD_INDEX ccccccccccccceeseseeeeeeeees 161 11 2 17 GFXCMDPARSER_BATCH_BUFFER cccccccccccccccseeeeeeeseeeeeseseeeeeeeees 162 12 QSL AMSTRUCTIONS nanena catiieeis dross a oa gece indies sceutegs a dashes chet dada hs A dae aa ee 163 12 1 BLTs To and From Cacheable Memory cccceeeececceeeeeeeeeeeeeneeeeeenaeeeeeenaeeeeeenaeeeeneaas 163 122 BET Engine IMSthuctions seenen e a ra e cosines 163 12 2 1 e aa E a BLE E E TEA A E E A E N 164 12 2 2 SETUP_MONO_PATTERN_SL_BLT ccccceseseseseeesesesesssteeeeeeeaeaeaes 166 12 2 3 PIXEL BIT ter the lene tapet oes Like Ase ieee oh canes ed te homens 167 12 2 4 SCANEINE BER irin iniaa aire adari dari ro idris 167 12 2 5 TEXT BET a E eh vet i E E ee ee 168 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 2 6 TEXT Immediate BET eeri nr han alae e
103. 1 5V supply The AGP interface voltage is determined by the VDDQ generation on the motherboard Three PCI Devices on GMCH The Intel 82815 chipset GMCH contains three PCI Devices The management of active devices is controlled via bit 0 of the APCONT register See the Intel 815 Chipset 82815 Graphics and Memory Controller GMCH EDS for details on PCI configuration registers e Device 0 Host Bridge PCI bus 0 interface Main Memory Controller Graphics Aperture controller e Device 1 AGP Bridge AGP 2X 4X interface AGP Mode e Device 2 Internal Graphics Device GFX Mode Devices and 2 are mutually exclusive Only one of these two devices can be active at any given time Device selection is performed during the start up sequence and can only be set once The lock bit must be set after device selection The following diagram shows more detail at a platform level The GMCH is shown in both AGP Mode left side and GFX Mode right side Only one mode can be active at any given time The processor and ICH functions remain unchanged by the GMCH mode of operation intel Figure 3 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Conceptual Platform PCI Configuration Diagram Processor AGP AGP Mode GFX Mode Secondary PCI PCI Configuration PCI Configuration Bus aA i Window in I O Space Window in I O Space programmable
104. 111 64 QWs 17 12 MM Display FIFO Watermark Number of QWs stored in FIFOs below which the DSI will generate requests to LMI Value has to less than 32 and should be as recommended in the high priority bandwidth analysis spreadsheet 10 8 LM Display Burst Length Reserved in Intel 815 chipset Size in QWs of individual requests issued to Memory Use Multiples of 16 QWs for tiled memory 000 8 QWs N A if Trickle Feed is on 001 16 QWs 010 24 QWs 011 32 QWs 100 40 QWs 101 48 QWs 110 56 QWs 111 64 QWs 7 6 Overlay Watermark Number of QWs stored in the overlay FIFO below which a new overlay request will be generated 00 24 QWs default 01 20 QWs 10 16 QWs 11 12 QWs LM Display FIFO Watermark Reserved in Intel 815 chipset Number of QWs stored in FIFOs below which the DSI will generate requests to LMI Value has to less than 32 and should be as recommended in the high priority bandwidth analysis spreadsheet 17 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 LCD TV Out Register Description During LCD or TV Out mode the BIOS will program the following LCD TV Out registers These registers are 32 bit memory mapped These registers are not double buffered and take effect when loaded Further this subsystem takes into account modified CR register values during vertical blank time for centering This subsystem allows the timing generator to be programmed to pixel granularity
105. 15 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 385 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 800x600_60Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 386 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 45 145 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 387 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Param
106. 2 OxA1 OxAO Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR04 OxA7 CR13 OxAO Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 413 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1600x900_60Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 414 OxA2 OxA2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 415 Intel 815 Chipset Graphics Co
107. 5 N 5 MUX 4 1 Tatchhigh X Slope 0x00 v Is N 8X7Multipli ip N ultiplier 7 0x00 latchhigh Y N N vi e K MUX 2 1 chet remainde Tatch amp to15 mw VY N miche My 4 1 N se latchhigh 70 Tatch32t063 Ej Tatch64to128 N Shifter shifts data to get 8 bits Lower bits are padded by zeros remainder iremainder Ly 271 Intel 815 Chipset Graphics Controller PRM Rev 1 0 272 intel As shown the inputs to the function are e PCI Register Bus The chip internal PCI data bus and the appropriate register decodes for loading the Gamma breakpoint values e Red In 2e07 00 The Red color component of the Overlay Stream e Green In 2e07 00 The Red color component of the Overlay Stream e Blue In 2e07 00 The Red color component of the Overlay Stream The output of the function is e Red Out The Gamma corrected Red color component e Green Out The Gamma corrected Green color component e Blue Out The Gamma corrected Blue color component Gamma Correction Theory Of Operation The Gamma Correction function outlined above is implemented via piece wise linear interpolator that allows any arbitrary curve to be output as a function of any linear input The function provides smooth continuous interpolations efficiently in hardware while taking little compromise in the preciseness of the output curve relative to the ideal The breakpoints of the curve are defined via software and loaded vi
108. 5 chipset GMCH host hub interface bridge DRAM controller FSB limited to 100 MHz 8086 1101 1 Intel 82815 chipset FSB limited to 100 MHz AGP bridge 8086 1102 2 Intel 82815 chipset FSB limited to 100 MHz Internal graphics device 8086 1110 0 Intel 82815 chipset no AGP internal graphics only GMCH host hub interface bridge DRAM controller 8086 1112 2 Intel 82815 chipset no AGP internal graphics only Internal graphics device 8086 1120 0 Intel 82815 chipset no internal graphics AGP only GMCH host hub interface bridge DRAM controller 8086 1121 1 No internal graphics AGP only AGP bridge 8086 1130 0 Intel 82815 chipset fully featured GMCH host hub interface bridge DRAM controller 8086 1131 1 Intel 82815 chipset fully featured AGP bridge 8086 1132 2 Intel 82815 chipset fully featured Internal graphics device 45 Intel 815 Chipset Graphics Controller PRM Rev 1 0 5 3 46 intel Once the operating system has identified the device it can load the appropriate driver One of the first tasks of the driver is to make sure that the device matches the driver Checking that the driver and device match is done in much the same way that the operating system identifies the graphics adapter That is the PCI Vendorld and Productld values are examined Some operating systems will make available to the driver the values it found during its scan If not the driver must scan the PCI space until it finds a match
109. 8 16 1 6 HWS_PGA Hardware Status Page Address Register 310 16 1 7 IPEIR Instruction Parser Error Identification Register debug 311 16 1 8 IPEHR Instruction Parser Error Header Register debug 0 311 16 1 9 INSTDONE Instruction Stream Interface Done Register 312 16 1 10 _NOPID NOP Identification Register eeeeeeeeeeeeeeeeteeeeeenteeeeeeaes 313 16 1 11 INSTPM tInstruction Parser Mode Register csecceeseeeeeesteeeeeenaes 314 16 1 12 INSTPS Instruction Parser State Register debug cceeeeeeeeeees 315 16 1 13 _BBP_PTR Batch Buffer Parser Pointer Register debug 0 317 16 1 14 ABB _STR Active Batch Buffer Start Address Register debug 317 16 1 15 ABB END Active Batch Buffer End Address Register debug 318 16 1 16 _DMA_FADD DMA Engine Fetch Address debuQ ccceeeeeeeeenees 318 16 1 17 MEM _MODE Memory Interface Mode Register debug eee 319 16 2 Interrupt Control Registers ernan ar O EE Ea 320 16 2 1 HWSTAM Hardware Status Mask Register 322 16 2 2 lER Interrupt Enable Register ccccceeeseeeeeeeneeeeeeneeeeeeceeeeeeneeeeseaas 323 16 2 3 IlR Interrupt Identity Register eccceeeeeeeeeeeeneeeeeeneeeeeeaeeeeeenaeeeeeeaas 324 16 2 4 IMR Interrupt Mask ReQiSter ccecceeceeeeeeceeeeeeeeeeeseenaeeeeeeneeeeeeaaes 325 Intel 815 Chipset Graphics Controller PR
110. A EASi 84 9 2 1 SRX Sequencer INAOX cccccececeeecceececeeeeeeeeeeeceeeeeseesceeeeeeeeeeeesenaeeeeees 84 9 2 2 SROO Sequencer Reset ecccceceeeeeeeeeeeeeceeeeeeeseeaeaeeeeeeeseesnnneeeeeeess 85 9 2 3 SRO1 CIocking Mode eeeeeceeeeeeeeeeeeeeeeeeeeeeeseeeeeeeseneeeeeseeeaeeeseeaeeeeeeaees 86 9 2 4 SRO2 Plane Map Mask cccccceeseceeceeeeeeeseceeeaeeeeeeeseeaeaeeeeeeeeeseesenaeeeeees 87 9 2 5 SROS Gharacter FOM asire ioana eee E segce lag REA A EEA IARA EE AEA 88 9 2 6 SR04 Memory Mode ReGiSter cccccceeceeeeeeeeeeeeseeneeeeseeeeeeeseeaeeeseeeaees 89 9 2 7 SRO7 Horizontal Character Counter Reset ccccecceceeeeeeeeeenteeeeeeneees 90 9 3 Graphics Controller RegistelS c cccceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeaeeeseeeaeeeseneaeeeeeenaees 90 9 3 1 GRX GRxX Graphics Controller Index Register cceeeeereeeeteeeeeneees 90 9 3 2 GROO0 Set Reset ReQiSter ecccecccceeeeeeeeeeeeeseeeeeeeseeeeeeeseeeeeeeseeaeeeeeenaees 91 9 3 3 GR0O1 Enable Set Reset Register ecccceeeeceeeseeeeeeeseeeeeeeeeeeeeseenanes 91 9 3 4 GRO2 Color Compare Register ce cccececeeceeeeeeeeeeeeeeeeeseeeeeeseeneeeeseeenaees 92 9 3 5 GRO3 Data Rotate Register ecccceeeeeeeeeeeeeeeeeeeeeeeeseeeeeeseeeeeeeeeaeees 92 9 3 6 GR04 Read Plane Select Register ceccecececeeeeeeeeeeeeseeeeeeeseeeeeeeeeaees 93 9 3 7 GR05 Graphi
111. A8 Read the current value of the Interrupt Mask Register Clear everything but the reserved bits 14 13 OR in the saved value of the Interrupt Mask Register Write the result back into the Interrupt Mask Register Error Mask Register MM 0x20B4 Read the current value of the Error Mask Register Clear everything but the reserved bits 15 6 OR in the saved value of the Error Mask Register Write the result back into the Error Mask Register intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark and Burstlength Control MM 0x20D8 Read the current value of the Watermark and Burstlength Control Register Clear the burst length and watermark bits bits 22 20 17 12 10 8 and 5 0 OR in the saved value of the Watermark and Burstlength Control Register Write the result back into the Watermark and Burstlength Control Register Disable the low priority ring buffer in preparation for setting new values by clearing the RING_VALID bit in the Low Priority Ring Buffer Length field at MM 0x203C Read the current value of the Low Priority Ring Buffer Length field MM 0x203C Clear the valid bit bit 0 Write the result back into the Low Priority Ring Buffer Length field Set up the low priority ring buffer Write a 0 to the low priority ring buffer tail at MM 0x2030 Write a 0 to the low priority ring buffer head at MM 0x2034 Restore the low priority
112. ARSER FRONT BUFFER INFO instruction For the sync flip the flag is cleared when the vertical sync occurs For async flip the flag is cleared when the hardware determines all the information for the new buffer is acquired this is estimated to be 32 scan lines Setting and clearing this flag generates a system memory write to the location stored in the Hardware Status Vector Address Register if unmasked in the Hardware Status Mask Register Clearing this flag will generate an external interrupt if unmasked in the Interrupt Mask Register and enabled in the Interrupt Enable Register The flush instruction should be issued prior to the flip instruction this is to ensure that hardware pipeline and cache structures are flushed and the rendered scene that is to be displayed next is in memory The flush instruction waits for the blitter and the render map pipeline to be Not Busy and the local cache to be coherent with memory before parsing continues The format of the GFXCMDPARSER FRONT BUFFER INFO instruction is me e y SESA Front Buffer Pitch A 12 bit value that specifies the number of QWs of frame buffer memory occupied by each horizontal row of characters This loading is similar to the loading of the offset registers CR41 3 0 CR13 7 0 except that the pitch in this case is specified in QWs Will not be loaded in case of Async flip Example of pitch computation for 1024x768 16 bpp 1024 pixels 2 B 1 pixel 1 QW 8 B 1 tile 16
113. Access Read Write Size 32 bits This register is new to the Intel 815 chipset i e not in the Intel 810 chipset The bits in this register mask out the corresponding page table error preventing it from being reported in the Page Table Error Register The Page Table Error Register can only show one page table error and associated error type at a time and the error reported is one with the highest priority amongst all current page table errors This Page Table Error Mask Register can be used to mask out higher priority errors such that a lower priority error can be reported if currently asserted Page table errors are reported with the following priority highest to lowest OS DS host render blit mapping engine CS and BF If any page table error occurs the highest priority error that is not masked with the associated bit in this Page Table Error Mask Register will be reported in the Page Table Error Register along with the associated error type All lower priority page table errors will not be reported Procedure for determining if a particular type of low priority page table error has occurred 1 Bit 4 of the Error Status Register will be a 1 if any page table error has occurred 2 Mask out all page table errors by writing 000000FFh to the Page Table Error Mask Register this is done because the Error Status Register bit 4 will not be cleared if any page table error is asserted 3 Unmask the target page table error
114. Addresses from the memory address counter are shifted twice to become DWord aligned DWord Mode Addresses from the memory address counter are shifted twice to become DWord aligned Address Wrap Note that this bit is only effective when word mode is made active by setting bit 6 in both the Underline Location Register and this register to 0 0 Wrap frame buffer address at 16 KB This is used in CGA compatible modes 1 No wrapping of frame buffer addresses Reserved Read as Os 127 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Count By 2 This bit is used in conjunction with bit 5 of the Underline Location Register CR14 to select the number of character clocks are required to cause the memory address counter to be incremented 0 The memory address counter is incremented either every character clock or every 4 character clocks depending upon the setting of bit 5 of the Underline Location Register 1 The memory address counter is incremented either every other clock CR14 5 CR17 3 Address Incrementing Interval 0 every character clock every 2 character clocks every 4 character clocks every 2 character clocks Horizontal Retrace Select This bit provides a way of effectively doubling the vertical resolution by allowing the vertical timing counter to be clocked by the horizontal retrace clock divided by 2 usually it would be undivided 0 The vertical timing counter is clocked by the horiz
115. Argument Alpha Arg2 Mask 0 Do not update 1 Update Reserved 00h Alpha Arg2 Valid values are Oh Reserved 1h Alpha Factor 2h Reserved 3h Iterated Alpha 4h Reserved 5h Current Alpha 6h TexelO Alpha 7h Texel1 Alpha Reserved 00h Invert Alpha Arg2 0 Do not Invert Argument 1 Invert Argument Alpha Operation Mask 0 Do not update 1 Update 231 Intel 815 Chipset Graphics Controller PRM Rev 1 0 0 4 0 Alpha Operation Valid values are 00h Reserved Enable Disable of stage is programmed in the Color Operation field 01h Select Arg1 02h Select Arg2 03h Modulate 04h Modulate and Multiply by 2 05h Modulate and Multiply by 4 O6h Add 07h Add Signed 08h Linearly Blend using the Iterated Alpha as the Blend Term 09h Reserved OAh Linearly Blend using the Alpha Factor as the Blend Term OBh Reserved Linearly Blend when a pre multiplied map alpha is present OCh Reserved Pre modulate OCh Reserved Bump Environment Map ODh Reserved Bump pre modulate with luminance channel OFh Reserved 10h Linearly Blend using Texel0 s Alpha as the Blend Term 11h Linearly Blend using Texel1 s Alpha as the Blend Term 12h 1Fh Reserved 13 14 GFXRENDERSTATE_COLOR_FACTOR This instruction specifies a constant color factor which can be used in the blending stages a e SOS 31 29 Client 03h Rendering Engine 28 24 3DStateMW 1Dh 23 16 Instruction 1h
116. C and VSYNC via HSYNC VSYNC Control 0 default 264 intel 15 Note Intel 815 Chipset Graphics Controller PRM Rev 1 0 Overlay Registers This chapter contains the Overlay and Gamma Correction registers and an Overlay instruction The current graphics controller implements one overlay that is referred to as Overlay 0 Note that the Overlay 0 control registers are indirectly written by first setting up a buffer in memory and then instructing the graphics controller to update the on chip registers from this buffer Software can invoke the update process by writing to the OVOADD register or by issuing the Overlay Flip instruction Note that the Gamma Correction registers are read written directly The register instruction categories are listed in the Overlay Register Instruction Categories table The Intel 815 chipset does not support overlay for low display resolution modes Thus the overlay is not supported for all resolution modes smaller than 640x480 System Memory On chip registers for Overlay O base 301 px ao read only debug Base MMADR PCI R Memory buffer area for loading on chip r Software setsup register values HW updates on chip regs for next VBLA Base xx Base OVOADD R overlay1 vsd Do not use the Wait for VBLANK mechanism to force a sequence of overlay flips Use the Wait for Scan Lines mechanism with the scan line set up to be at least 1 scan line after vertical blank s
117. CRO7 Overflow Register ccccceceeeseteeeeeeeeeeeeeteneeeeeteeeeeesaeeeeeetnaeeeee 114 9 6 10 CRO8 Preset Row Scan Register cceceeeeceeeseeeeeeeeeeeeeeeteieeeeetneeeereas 117 9 6 11 CRO9 Maximum Scan Line Register eceeeceeeeeseeeeeeeseteeeeeeeeeeeeees 118 9 6 12 CROA Text Cursor Start Register ceceeeeeeeneeeeeeeneeeeeenieeeeetneeeeeee 119 9 6 13 CROB Text Cursor End Register ccccceceeceeeeeeeeeeeeneeeeesnieeeeetnaeeeeteaa 119 9 6 14 CROC Start Address High Register 0 ccecceceeceeeeeteeeeestieeeeeenteeeereae 120 9 6 15 CROD Start Address Low Register 0 cccececeeeeeeeeetieeeeeeeieeeertneeeeeeas 121 9 6 16 CROE Text Cursor Location High Register ceececeeeseteeeeesteeeeees 121 9 6 17 CROF Text Cursor Location Low ReQjister c cccesecceeessteeeeeeteeeereee 122 9 6 18 CR10 Vertical Sync Start Register ccceeeseeeeeeeeteeeeeeeneeeeetneeeeeeea 122 9 6 19 CR11 Vertical Sync End Register cccceceeceeeeeeeeeeeeneeeeeetieeeeeeneeeereea 123 9 6 20 CR12 Vertical Display Enable End Register 0 cececeeeeeeeeeeeteeeeeeee 124 9 6 21 CR13 Offset ReGiISten sore riki EEEE AEEA AT EEEN 124 9 6 22 CR14 Underline Location Register esssseeeeseeeseerreseerrserrsserrrssrernssne 125 9 6 23 CR15 Vertical Blanking Start Register ccceeeceeeseteeeeeeeneeeeeetteeeeeee 126 9 6 24 CR16 Vertical Blanking En
118. CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 382 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 43 143 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 383 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 720x576_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 384 Intel 8
119. CURBASE Cursor Base Address Register Memory Offset Address 70084h Default 0000h Attributes Read Write The cursor can only be read from System memory This register is double buffered The load register is transferred into the active register on the asserting edge of Vertical Sync 31 29 28 8 7 0 ee Cursor Base Address Bits 28 08 These 21 bits provide most significant bits of a 29 bit physical address of the graphics non cacheable system memory space where the 512 to 1 KB cursor data space for cursor is to be located This is a physical address No GTT translation 20 4 3 CURPOS Cursor Position Register Memory Offset Address 70088h Default 0000h Attributes Read Write CURPOS is double buffered The load register is transferred to the active register on the asserting edge of Vert Sync 31 30 27 26 16 Y Position Reserved Cursor Y Position Magnitude Bits 10 0 Sign Bit 15 14 11 10 0 X Position Reserved Cursor X Position Magnitude Bits 10 0 Sign Bit 31 Cursor Y Position Sign Bit This bit provides the sign bit of a signed 12 bit value that specifies the horizontal position of cursor Default is 0 26 16 Cursor Y Position Magnitude Bits 10 0 This field provides the magnitude bits of a signed 12 bit value that specifies the vertical position of cursor The sign bit of this value is provided by bit 31of this register Default is 0 15 Cursor X Position Sign Bit This bit provides the sign bit of a
120. Chipset Graphics Controller PRM Rev 1 0 12 3 6 BR05 Setup Expansion Background Color Memory Offset Address 40014h Default None Attributes RO DWord accessible 3 24 23 0 1 Reserved Must be Zero Setup Expansion Background Color Bits 23 0 es o o e O 31 24 Reserved Must be Zero 23 0 Setup Expansion Background Color Bits 23 0 These bits provide the one two or three bytes worth of color data that select the background color to be used in the color expansion of monochrome pattern or source data for either the SCANLINE_BLT or TEXT_BLT instructions BRO5 is also used as the solid pattern for the PIXEL_BLT instruction Whether one two or three bytes worth of color data is needed depends upon the color depth to which the BLT Engine has been set For a color depth of 24bpp 16bpp and 8bpp bits 23 0 15 0 and 7 0 respectively are used 12 3 7 _BRO6 Setup Expansion Foreground Color Memory Offset Address 40018h Default None Attributes RO DWord accessible 31 24 23 0 Reserved Must be Zero Setup Expansion Foreground Color Bits 23 0 es o ee O 31 24 Reserved Must be Zero Whether one two or three bytes worth of color data is needed depends upon the color depth to which the BLT Engine has been set For a color depth of 24bpp 16bpp and 8bpp bits 23 0 15 0 and 7 0 respectively are used 23 0 Setup Expansion Foreground Color Bits 23 0 These bits provide the one two or three bytes
121. D instructions are used to program the 3D pipeline state and perform 3D Stretch Blt and MotionComp operations All 3D state instructions are of fixed length while the rendering instructions are all variable length Refer to the Rendering Engine Instruction Chapter for a description of the 3D instructions Figure 29 Instruction Format For First DWord TYPE Parser 00h NOP Identification No DWord Count OXh Single DWord Packets Instruction Dependent Data 1Xh Two DWord Packets 5 0 DWord Count 2Xh Store DWord Packets 5 0 DWord Count 3Xh Ring Batch Buffer Pkts 5 0 DWord Count fraps OC OOC SN C 2D 010 Opcode Instruction Dependent Data 3DState24 011 Opcode 00000 01111 Instruction Dependent Data en e Pesce sete 3DState24NP Opcode 10000 11000 Instruction Dependent Data 23 0 24 non pipelined state and mask bits Opcode 11100 23 19 18 16 15 0 16 Texture state and Sub Opcode i 00h 7Fh Map mask bits Opcode 11100 23 19 18 16 15 0 16 Scissor state and Sub Opcode 80h FFh Rect No mask bits Rsvd 3DState16 3DState16NP 3DStateMWNP Multiple DWord 3DBlock Opcode 11101 23 16 15 0 DWord Count Sub Opcode 80h FFh Opcode 11110 23 16 15 0 DWord Count Sub Opcode Opcode 11111 23 16 17 0 DWord Count Sub Opcode NOTES 1 SrcCopylmmBit does not follow the 2D format 2 The qualifier NP indicates that the state variable is non
122. D5h index O0Bh Default OUUU UUUUb U Undefined Attributes Read Write This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup a k a cursor and cursor 2 which are intended to be used in graphics modes This text cursor exists only in text modes and so this register is entirely ignored in graphics modes 6 5 7 4 0 Text Cursor Skew Text Cursor End Reserved Read as Os 6 5 Text Cursor Skew This field specifies the degree to which the start and end of each horizontal line of pixels making up the cursor is delayed to compensate for internal pipeline delays These 2 bits describe the delay in terms of a number character clocks 00 No delay 01 Delayed by 1 character clock 10 Delayed by 2 character clocks 11 Delayed by 3 character clocks Text Cursor End This field specifies which horizontal line of pixels in a character box is to be used to display the last horizontal line of the cursor in text mode The horizontal lines of pixels in a character box are numbered from top to bottom with the top most line being number 0 The value specified by these 5 bits should be the number of the last horizontal line of pixels on which the cursor is to be shown 119 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 14 CROC Start Address High Register I O and Memory Offset Address 3B5h 3D5h index 0Ch Default Undefined Attributes Read Writ
123. DCLK_ODS Display and LCD Clock Divisor Select 06014h 06017h PWR_CLKC Power Management and Miscellaneous Clock Control LCD TV Out g gjg 60000h 60003h HTOTAL Horizontal Total 60004h 60007h Horizontal Blank 60008h 6000Bh Horizontal Sync 6000Ch 6000Fh Vertical Total 60010h 60013h Vertical Blank 60014h 60017h Vertical Sync 60018h 6001Bh LCD TV Out Control 6001Ch 6001Fh Overlay Active Register 60020h 60023h Border Color Pattern Display and Cursor Control Registers 70008h 7000Bh PIXCONF Pixel Pipeline Configuration i g S 7 5 Intel 815 Chipset Graphics Controller PRM Rev 1 0 2D Graphics Controller Registers 3CEh 3CFh Refer to Chapter 9 VGA and Extended VGA Registers for detailed bit field descriptions Index Sym Register Name GR10 Address Mapping GR11 Page Selector 2D CRT Controller Registers 3B4h 3D4h 3B5h 3D5h Refer to Chapter 9 VGA and Extended VGA Registers for detailed bit field descriptions 73 Intel 815 Chipset Graphics Controller PRM Rev 1 0 7 6 74 Initialization Values for VGA Registers Mode gt Register MSR CROO CRO1 CRO2 CRO3 CR04 CR05 CRO6 CRO7 CRO8 CRO9 CROA CROB CROC CROD CROE CROF CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 SROO SRO1 SR02 SR03 SR04 GROO 0 63h 2Dh 27h 28h 90h 2Bh AOh BFh 1Fh 00h C7h 06h 07h 00h 00h 00h 00h 9Ch 8Eh 8Fh 14h 1Fh 96h B9h A3h FFh 0
124. FPVSYNC is enabled eWhen in FP VESA VGA Mode then the VGA timing generator is the source of this signal eWhen not in FP VESA VGA Mode then the source of this signal is this timing generator Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description FPHSYNC Output Control 1 Tristates the FPHSYNC pin 0 FPHSYNC is active unless LCD TV Out Enable is deasserted Border Enable 1 Border to the LCD TV encoder is enabled 0 Border to the LCD TV encoder is disabled Active Data Order 1 Reversed pixel data ordering G 3 0 B 7 0 followed by R 7 0 G 7 4 0 Normal pixel data ordering R 7 0 G 7 4 followed by G 3 0 B 7 0 Active Data Polarity 1 Inverted Pixel Data 0 Normal Pixel Data VSYNC Polarity Control When the LCD TV timing generator is disabled the polarity is controlled by the VGA registers 1 Active high 0 Active low HSYNC Polarity Control When the LCD TV timing generator is disabled the polarity is controlled by the VGA registers 1 Active high 0 Active low BLANK Polarity Control 1 Active high 0 Active low Dot Clock Source 1 Dot Clock PLL Reference Source is External Pin CLKIN 0 Dot Clock PLL Reference Source is the default PLL source The CLKIN pin can be used an Interrupt for FP hot plug detection When the pin is used as a clock the interrupt signal is forced to the deassertion level The CLKIN Interr
125. GA range does not require a translation table and VGA range paging allows access to all of local memory if it is setup with bit 4 of this register or to all the stolen for VGA main memory space Access to graphics range requires GTT to be set up and will result in a prefetch unless prefetch is disabled Access to VGA range will not result in prefetch 3 BIOS should access local memory through the back door mechanism by setting GR10 17h GR11 0 and GR6 0 only when local memory has been enabled MMADR 3000h else the system will hang in a snoop stall forever 9 3 12 GR11 Page Selector I O and Memory Offset Address 3CFh Index 11h Default 00h Attributes R W ee Page Select Selects a 64KB window within VGA space in NLVM mode or all of local memory when Page Mapping is enabled GR10 0 1 In addition this register is used for page selection of memory mapped register addresses 99 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 3 13 GR 14 1F Software Flags I O and Memory Offset Address Default Attribute 3CFh Index 14h 1fh 00 R W ee Software Flags Used as scratch pad space in BIOS These have no effect on H W 100 9 4 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Attribute Controller Registers Unlike the other sets of indexed registers the attribute controller registers are not accessed through a scheme employing entirely separate index and data ports I O addr
126. GA vertical resolutions the standard VGA display should use All extended modes including those with a vertical resolution of 480 scan lines use a setting of 0 for both of these bits This setting was reserved in the VGA standard 83 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Table 8 9 2 9 2 1 84 CRT Display Sync Polarities V Display Horizontal Vertical Frequency Frequency N 480 Line 31 5 KHZ 60 Hz Sequencer Registers The sequencer registers are accessed via either I O space or Memory space To access the registers the VGA Sequencer Index register SRX at I O address 3C4h or memory address 3C4h is written with the index of the desired register Then the desired register is accessed through the data port for the sequencer registers at I O address 3C5 or memory address 3C5 SRX Sequencer Index I O and Memory Offset Address 3C4h Default 00h Attributes Read Write 7 3 2 0 Reserved 00000 Sequencer Index ao Reserved Read as Os reason for calling it the Plane Mask Register SRO7 is a standard VGA register that was not documented by IBM It is not an graphics controller extension 2 0 Sequencer Index This field contains a 3 bit Sequencer Index value used to access sequencer data re gisters at indices 0 through 7 Notes 1 SR02 is referred to in the VGA standard as the Map Mask Register However the word map is used with multiple meanings in the VGA standard and
127. Gin Bout As Bin Aout As Ain Destination Rout 1 As Rin Gout 1 As Gin Bout 1 As Bin Aout 1 As Ain The Both Inv_Sre_ Alpha blend factor is Source Rout 1 As Rin Gout 1 As Gin Bout 1 As Bin Aout 1 As Ain Destination Rout As Rin Gout As Gin Bout As Bin Aout As Ain The blending factors shall be applied to the source and destination RGBA values and computed using one of the blending equations shown below The equation is selected by a state variable Add Cs S Cd D Where Cs is the source RGBA Cd is the destination RGBA S is the source blending factor and D is the destination blending factor Intel 815 Chipset Graphics Controller PRM Rev 1 0 Description 31 29 Client 03h Rendering Processor 28 24 3DState24 08h 23 16 Reserved 00h 15 Specular RGB State Mask 0 Do Not Update 1 Update 14 Specular RGB Enable 0 Disable default 1 Enable Controls specular color interpolation When enabled a full RGB specular color is interpolated otherwise a monochrome specular value is interpolated 13 Color Monochrome Diffuse Enable State Mask 0 Do Not Update 1 Update Color Monochrome Diffuse Enable 0 Disable default 1 Enable i Source Destination Blend State Reserved default oe In the case of the monochrome state variables the rasterizer will shade primitives by interpolatin
128. Graphics Controller PRM Rev 1 0 CR02 0xA0 CR13 0xA0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 405 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1280x960_60Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 406 OxAB OxAO Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR13 OxAO Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 407 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parame
129. I address space e Allocate enough memory for the frame buffer from a memory pool created during initialization The amount of memory is determined by system characteristics but should default to at least 8 MB e Ifa hardware cursor is being used allocate memory for the hardware cursor from the same memory pool The hardware does not use the GART to access the memory for the cursor so local to physical memory address translation must be performed The hardware cursor memory address should be programmed into the CURBASE register memory mapped address 70084h e The low priority ring buffer memory should be initialized to 0 The low priority ring buffer pointers should be programmed into the ring buffer pointer registers RINGBUF which begin at offset 2030h in the memory mapped IO space Intel 815 Chipset Graphics Controller PRM Rev 1 0 5 4 Hardware Register Initialization 5 4 1 Color vs Monochrome Monitors The mapping and initialization of some hardware registers depends in part on whether the graphics adapter is attached to a monochrome or color monitor The following steps illustrate how to determine the type of output device attached to the graphics adapter e Read the Miscellaneous Output Register 0x3CC e Test the low order bit of the Miscellaneous Output Register and interpret it as follows 0 The adapter is in monochrome monitor mode In this mode the control register is 3B4 and 3B5 and status is at 3BA
130. IO Qw R W register R WC register R WO register RO register WO register intel Description The Memory Controller Hub component that contains the processor interface DRAM controller and AGP interface The MCH communicates with the ICH over a proprietary interconnect called the hub interface previously known as HubLink The MCH was called the North Bridge NB in previous chip sets MCH will be used to refer to non graphics portion of the GMCH Memory Mapped address space Memory Mapped I O space Quad Word 64 bits 8 Bytes Read Write A register with this attribute can be read and written Read Write Clear A register bit with this attribute can be read and written However a write of 1 clears sets to 0 the corresponding bit and a write of 0 has no effect Read Write Once A register bit with this attribute can be written to only once after power up After the first write the bit becomes read only Read Only In some cases if a register is read only writes to this register location have no effect However in other cases two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register See the I O and memory map tables for details Write Only In some cases If a register is write only reads to this register location have no effect However in other cases two separate registers are located at the same location where a rea
131. Interrupt Ring 02050h 0205Fh Reserved 02060h 0207Fh Reserved Default Value 00000000h Access Read 32 bit Write Only Size 4 DWords Each Ring buffer is defined by a four DWord register set which includes starting address length head pointer and tail pointer The ring buffer can be disabled when empty A driver uses two sets of ring buffers low priority and interrupt Instruction ring buffers must be located in main memory There is no hardware support for ring buffers that are mapped to local memory There is neither a hardware error detection for intentional or inadvertent attempts to map the ring buffers to local memory This requirement applies to both low priority and interrupt rings Intel 810 Chipset and Intel 815 Chipset Errata Address Offset 2030h 207Fh DWord Offset 0 1 2 and 3 Bit 2 1 Automatic Report Head pointer Autoreport happens on a 64K or 128K boundary When the head pointer crosses the ring buffer size on an autoreport boundary the hardware erroneously reports the head pointer address ring buffer size as opposed to wrapping around and reporting 0 This is an Intel 810 chipset and Intel 815 chipset Silicon Errata Note that the size of the ring buffer is not restricted to a power of two A software work around can be implemented as follows The reported head pointer should be bit wise AND d by the size of the ring buffer minus 1B For example ring buffer size 128KB HW reported head
132. LT engine requires only four pieces of information the starting address of the first sub block the length of a sub block the offset in bytes pitch of the starting address of each subsequent sub block and the quantity of sub blocks Source Data The source data may exist in the frame buffer or main memory graphics memory where the BLT engine may read it directly or it may be provided to the BLT engine by the host processor through the command packets The block of source graphics data may be either contiguous or discontinuous and may be either in color with a color depth that matches that to which the BLT engine has been set or monochrome The source select bit in the command packets specifies whether the source data exists in the frame buffer or is provided through the command packets Monochrome source data is always specified as being supplied through an immediate command packet 6 2 3 Intel 815 Chipset Graphics Controller PRM Rev 1 0 If the color source data resides within the frame buffer or main memory graphics memory then the Source Address Register specified in the command packets is used to specify the address of the source However if the host processor provides the source data then this register takes on a different function and the three least significant bits of the Source Address Register can be used to specify a number of bytes that must be skipped in the first quadword received from the command packet to reach t
133. Location Bits 15 8 This field provides the 8 most significant bits of a 16 bit value that specifies the address offset from the beginning of the frame buffer at which the text cursor is located Bits 7 0 of the Text Cursor Location Low Register CROF provide the 8 least significant bits 121 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 17 CROF Text Cursor Location Low Register I O and Memory Offset Address 3B5h 3D5h index OFh Default Undefined Attributes Read Write This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup a k a cursor and cursor 2 which are intended to be used in graphics modes This text cursor exists only in text modes and so this register is entirely ignored in graphics modes Pe Text Cursor Location Bits 7 0 This field provides the 8 least significant bits of a 16 bit value that specifies the address offset from the beginning of the frame buffer at which the text cursor is located Bits 7 0 of the Text Cursor Location High Register CROD provide the 8 most significant bits 9 6 18 CR10 Vertical Sync Start Register I O and Memory Offset Address 3B5h 3D5h index 10h Default Undefined Attributes Read Write a Vertical Sync Start Bits 7 0 This register provides the 8 least significant bits of either a 10 bit or 12 bit value that specifies the beginning of the vertical sync pulse relative to the
134. M Rev 1 0 17 18 19 20 21 10 16 2 5 ISR Interrupt Status Register ce eceeeeeeeeeeeeeeeeeeeeeseneeeeeeeeeeeeneeeereea 326 16 2 6 Error Identity Mask and Status Registers 0 ccceeeeeeeeeeeeeeeeeeteeeeeeaees 327 16 2 6 1 Page Table Error handling in Intel 815 Chipsets 327 16 2 6 2 Resetting the Page Table Error ccccccceeeeeeeeeeeeeeseeneeeeseeneeees 328 16 2 6 3 ElR Error Identity Register eceeeeeeeeeeeeeeeeeeeeseeneeeseeaees 329 16 2 6 4 EMR Error Mask Register 0 ccceeeeeeeeeeeeeeeseeneeeeeeeeneeeeseeeaees 329 16 2 6 5 ESR Error Status Register ccceeceeeceeeeeeeeeeeneeeeeeeneeeeeeaees 330 16 3 Display Interface Control erosin eana aa iea iiae T ia 331 16 3 1 FW_BLC FIFO Watermark and Burst Length Control 0 eee 331 LCD TV Out Register Description 00 2 2 eect eeteee eee eete ee ee ee ee ee taeeeeetaeeeeetaeeeeesneeeeetnaeeeee 333 17 1 HTOTAL Horizontal Total Register 0 cceceeeseeeeeeeeeeeeeeenneeeeeeaeeeeeeneeeeesneeeeeeaes 333 17 2 HBLANK Horizontal Blank Register 0 ccccceeeeeeeeeeeeeeeeeeeneeeeeeaeeeeeenaeeeeesnaeeeeeaaes 334 17 3 HSYNC Horizontal Sync Register c cc eecceeeeeeeeeeeeeneeeeeseeeeeeenaeeeeeeaeeeeeeaeeeeeeaes 335 17 4 VTOTAL Vertical Total Register cccccecccceeeenneeeeeenneeeeeenaeeeeeeneeeeeeneeeeeteeeseeaes 336 17 5 VBLANK Vertical Blank Register 0 cccceccseeees
135. Map ececcceccceeeetteeeeetineeeetiieeeeetieeeeetieeeereieeee 36 3 3 1 VGA and Extended VGA I O and Memory Register Map 37 3 4 Indirect VGA and Extended VGA Register Indices 0000 2 ececeeeeeteeeeeteeeeeettteeeeetnaeeeee 38 3 4 1 Graphics Address Translation ccccccccecceceeeeeeeeeeneeeeeeeeeeeeeeenaneeeeeeenees 41 3 4 2 Memory Buffers for GC s Instruction Interface eeteeeeeeeeeeeeetteeeeeees 42 Graphics Translation Table GTT Range Definition eeecceeeeeeeeeeneeeeeenneeeeeenaeeeeeenaeeeeeeaas 43 Basic Initialization Procedures cccccceeeeceeceececeeeeeeenaeeeeeeeeeseceaaeceeeeeeesecsneaeeeeseseseenaeaeeeeeess 45 5 1 Initialization SEQUENCE Wi ccccascccdesseidecdersesd aag iadaaa aaa aaa a adana adaa 45 5 2 Hardware Detection Probe cccceeseeeeeeeeeeeeeeeeeeeseeaaeeeeeeaeeeseeaeeeseeaeeeeeeneeeseeaaes 45 5 3 Frame Buffer InitialiZation ccccccccceeeecceceeeeeeeeeeaeceeeeeeesecacaeceeeeeeeseceaaeeeeeeetesenaees 46 5 4 Hardware Register InitialiZation eee eeceeeeceeeeeeeeeenneeeeeeaeeeeeeaeeeseeaeeeseeaeeeeeeneeeeeeaaes 47 5 4 1 Color vs Monochrome Monitors ecccceeeeeeeeeeeeeceeeeeeeseeeeseeeeeeeeteees 47 5 4 2 Protect Registers Locking and Unlocking ccccecesseeeeeetteeeeesteeeeeenaes 47 5 4 3 Checking Memory Frequency c cececceeeeeeneeeeeeeneeeeeeenaeeesesaeeeeeeneeeeseaas 47 5 5 Hardware States saissesvtiaccer
136. Map B These three bits are used to select the character map character generator tables to be used as the secondary character set font Note that the numbering of the maps is not sequential Bit 3 2 5 Map Number Table Location 00 0 1st 8KB of plane 2 at offset 0 default 00 1 2nd 8KB of plane 2 at offset 8K 01 0 3rd 8KB of plane 2 at offset 16K 01 1 4th 8KB of plane 2 at offset 24K 10 0 5th 8KB of plane 2 at offset 32K 10 1 6th 8KB of plane 2 at offset 40K 11 0 7th 8KB of plane 2 at offset 48K 11 1 8th 8KB of plane 2 at offset 56K N WON OF A O Character Map Select Bits for Character Map A These three bits are used to select the character map character generator tables to be used as the primary character set font Note that the numbering of the maps is not sequential Bit 1 0 4 Map Number Table Location 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 1st 8KB of plane 2 at offset 0 default 2nd 8KB of plane 2 at offset 8K 3rd 8KB of plane 2 at offset 16K 4th 8KB of plane 2 at offset 24K 5th 8KB of plane 2 at offset 32K 6th 8KB of plane 2 at offset 40K 7th 8KB of plane 2 at offset 48K 8th 8KB of plane 2 at offset 56K N WON OO A O 1 In text modes bit 3 of the video data s attribute byte normally controls the foreground intensity This bit may be redefined to control switching between character sets This latter function is enabled whenever there is a difference in the values of the Character Font Sel
137. O O 39 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Index Sym Register Name Sh 7a 40 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 3 4 1 Graphics Address Translation The Intel 815 chipset uses a logical memory addressing concept for accessing graphics data The GC supports a 64 MB logical address space where each 4 KB logical page can be mapped to a physical memory page in System RAM PCI Memory or an optional Display Cache memory This mapping is performed through the use of a Graphics Translation Table GTT GC engines can address the full 64 MB logical address space The processor is provided access to either the full 64 MB space or just the lower 32 MB via a PCI memory range associated with the graphics device The GTT is allocated in system RAM and maintained by the graphics driver The 4 KB aligned physical address of the 64 KB GTT is programmed via the GC s PGTBL register Each of the 16K DWord GTT entries can map a 4 KB logical page to a physical memory page Fields in the GTT entry control the mapping of that logical page in the following manner e V whether or not that logical 4 KB page is mapped to a physical memory page Accesses to invalid pages will result in an error interrupt e T1T0 the physical memory address space of the mapped page System RAM page no processor cache snoop PCI Memory page processor cache snooped if below TOM Display Cache
138. OD is determined at a textured pixel This 2 s complement fixed point value has 2 integer bits and 4 fractional bits and is signed extended before being added to the LOD Valid data value range from 4 0 to 3 9375 S2 4 The default value is 0 225 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 11 GFXRENDERSTATE_MAP_PALETTE_LOAD The Texture Palette is loaded using the following instruction All 256 entries of the texture palette must be loaded every time this command packet is sent In other words even if only one entry of the texture palette needs to be updated all 256 entries must be loaded and sent using this command packet Figure 38 State Variable Relationships Coordinate Sets _ Map Information Texels Blending Stages Powe ee ee Client 03h Rendering Engine 3DStateMWNP Non pipelined 1Dh Opcode 82h DWORD_LENGTH 255 31 16 Reserved 00h 1 16 bit Color 0 Format RGB 565 1555 4444 YCrCb 565 or Al 88 256 31 16 Reserved 00h 16 bit Color 255 Format RGB 565 1555 4444 YCrCb 565 or Al 88 226 Figure 39 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES The Rendering Engine supports three map color blend stages for the red green and blue channels Any of these stages may perform an operation utilizing up to two texels from the Mapping Engine the iterated fa
139. OS 27 16 Vertical Sync End Vertical sync end expressed in terms of absolute line numbers relative to the vertical active display start Notes 1 When VSYNC Start is programmed equal to VBLNK Start both VSYNC and VBLANK will be asserted on the same pixel clock VSYNC Start programmed beyond the VTOTAL end will prevent the VSYNC start and VSYNC end to occur 11 0 Vertical Sync Start Vertical sync start expressed in terms of absolute line number relative to the vertical active display start Notes 1 Minimum VSYNC width is 2 lines A VSYNC programmed to 1 scan line does not generate the correct picture An asserted VSYNC will be cleared as soon as VTOTAL end is reached regardless of the value in the VSYNC End register Intel 815 Chipset Graphics Controller PRM Rev 1 0 LCDTV_C LCD TV Out Control Register Address Offset 60018h Default Value 00000000h Access Read Write Size 32 bits LCD TV SYNC Centering FP VESA Reserved Out Polarity Enable VGA Mode Enable Control 23 16 15 Reserved FP 740 LCD Info Reserved VSYNC HSYNC VSYNC HSYNC Data Data Control Control Output Output Ordering Enable Control Control Active Active VSYNC HSYNC BLANK Dot Clock Lock Dot Data 2 Data Polarity Polarity Polarity Source Clock PLL Pixel Order Polarity Control Control Control N M Regs LCD TV Out Enable 1 Enable This bit enables the LCD TV digital interface The LCD TV Timing Generator is jammed to
140. Pixel 0 of Vertical Front Porch when this bit is a 0 The timing generator may be ignored depending on the LCD Timing Generator Bit 29 0 Disable and Tristate the whole interface TVDATA 11 0 BLANK TVHSYNC TVVSYNC and TVCLK 1 0 CLKIN is not disabled and can be used for Flat Panel Hot Plug detection SYNC Polarity Control 0 Source of TVHSYNC TVVSYNC polarity is the LCDTV_C LCD TV Out Control Register in multi sync mode default 1 Source of TVHSYNC TVVSYNC polarity is the MSR WMiscellaneous Output Register in multi sync mode Centering Enable 0 Disable The LCD TV timing generator controls all display timing when enabled by bit 31 above 1 Enable Centers the VGA active image as defined in the VGA CRT registers within LCD TV active image 339 Intel 815 Chipset Graphics Controller PRM Rev 1 0 340 Post eseripon SE FP VESA VGA Mode 0 Disable Use the LCD TV Timing Generator VGA Sync Polarity is ignored FP Sync Polarity is used Centering can be enabled for fixed resolution flat panels or TVs The Flat Panel Dot clock PLL timing registers must be used for both flat panels and TVs After these registers are written the Lock Dot Clock PLL N M Registers must be set to 1 which makes the Dot Clock PLL only use the Flat Panel PLL registers 1 Enable Use the VGA Timing Generator VGA Sync polarity is passed though and FP Sync Polarity is ignored Centering must be disabled Also set bit 0 of
141. Pixels Shifted Bit 6 5 9 Pixel Text 8 Pixel Text amp Graphics 00 0 0 01 9 8 10 18 16 11 27 24 Starting Row Scan Count This field specifies which horizontal line of pixels within the character boxes of the characters used on the top most row of text on the display will be used as the top most scan line The horizontal lines of pixels of a character box are numbered from top to bottom with the top most line of pixels being number 0 If a horizontal line of the these character boxes other than the top most line is specified then the horizontal lines of the character box above the specified line of the character box will not be displayed as part of the top most row of text characters on the display Normally the value specified by these 5 bits should be 0 so that all of the horizontal lines of pixels within these character boxes will be displayed in the top most row of text ensuring that the characters in the top most row of text do not look as though they have been cut off at the top 117 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 11 CRO9 Maximum Scan Line Register I O and Memory Offset Address 3B5h 3D5h index 09h Default 00h Attributes Read Write Double Scanning Enable 0 Disable When disabled the clock to the row scan counter is equal to the horizontal scan rate This is the normal setting for many of the standard VGA modes and all of the extended modes Enable When enabled the clock to the r
142. R15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 402 Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR02 0xA0 CR13 0xA0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 403 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1280x720_75Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 404 96 196 MHz Dot Clock OxAO OxAO Intel 815 Chipset
143. R42 Bits 23 through 18 of this value are provided by bits 5 through 0 of the Extended Start Address Register CR40 Bits 17 through 10 of this value are provided by the Start Address High Register CROC Bits 9 through 2 of this value are provided by this register Bits 1 and 0 of this value are always 0 and therefore not provided It should be further noted that in extended modes these 32 bits from these four registers are double buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance To change the start address in extended modes all three registers must be set for the new value and then bit 7 of the Extended Start Address Register CR40 must be set to 1 Only if this is done will the hardware update the start address on the next VSYNC When this update has been performed the hardware will set bit 7 of the Extended Start Address Register CR40 back to 0 9 6 16 CROE Text Cursor Location High Register I O and Memory Offset Address 3B5h 3D5h index 0Eh Default Undefined Attributes Read Write This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup a k a cursor and cursor 2 which are intended to be used in graphics modes This text cursor exists only in text modes and so this register is entirely ignored in graphics modes Text Cursor
144. RENDERSTATE BLEND ENABLE 3 RENDERSTATE BLEND COLOR Texture compositing RENDERSTATE_ BLEND ENABLE 1 Blending OFF 2 Blending On Additional Blending Modes The color calculator super unit of the graphics device shall support four new Blending operations The blend factors for the source and destination colors are controlled by separate state variables and shall be defined as shown below The RGBA values of the source and destination are indicated with the subscripts s and d respectively 235 Intel 815 Chipset Graphics Controller PRM Rev 1 0 The Zero blend factor is Rout 0 Gout 0 Bout 0 Aout 0 The One blend factor is Rout Rin Gout Gin Bout Bin Aout Ain The Src_Color blend factor is Rout Rs Rin Gout Gs Gin Bout Bs Bin Aout As Ain The Inv_Src_Color blend factor is Rout 1 Rs Rin Gout 1 Gs Gin Bout 1 Bs Bin Aout 1 As Ain The Src_Alpha blend factor is Rout As Rin Gout As Gin Bout As Bin Aout As Ain The Inv_Src_Alpha blend factor is Rout 1 As Rin Gout 1 As Gin Bout 1 As Bin Aout 1 As Ain The Dst_Color blend factor is Rout Rd Rin Gout Gd Gin Bout Bd Bin Aout Ad Ain The Inv Dst_ Color blend factor is Rout 1 Rd Rin Gout 1 Gd Gin Bout 1 Bd Bin Aout 1 Ad Ain The Both Src_Alpha blend factor is Source Rout As Rin Gout As
145. S GFXRENDERSTATE_MAP_COORD_SETS GFXRENDERSTATE_MAP_INFO GFXRENDERSTATE_MAP_FILTER GFXRENDERSTATE_MAP_LOD_LIMITS GFXRENDERSTATE_MAP_LOD_CONTROL GFXRENDERSTATE_MAP_PALETTE_LOAD GFXRENDERSTATE_MAP_LOD_BIAS GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES GFXRENDERSTATE_COLOR_FACTOR GFXRENDERSTATE_COLOR_CHROMA_KEY GFXRENDERSTATE_SCR_DST_BLEND_MONO GFXRENDERSTATE_Z_BIAS_ALPHA_FUNC_REF GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_MODE GFXRENDERSTATE_BOOLEAN_ENA_1 GFXRENDERSTATE_BOOLEAN_ENA_ 2 GFXRENDERSTATE_FOG_COLOR GFXRENDERSTATE_DRAWING_RECTANGLE_INFO GFXRENDERSTATE_SCISSOR_ENABLE GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO GFXRENDERSTATE_ANTI_ALIASING GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION_RULE GFXRENDERSTATE_DEST_BUFFER_VARIABLES 152 11 11 1 11 2 11 2 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Instruction Parser Instructions Introduction The Graphics Controller GC contains an extensive set of instruction for controlling 2D and 3D operations This section describes the programmer s interface to these instructions The instructions can be categorized as follows e 3D Instructions The 3D pipeline states and processing functions are controlled by a set of 3D instructions See the 3D Instruction section for detailed instruction descriptions e 2D Instructions The 2D instructions are used to invoke BLT operations See the 2D Register and instruction section for detailed
146. Status Select Register Memory Offset Address 70024h Default 0000h Attributes Read Write This register selects the proper events to be signaled to the Interrupt Control Register in the command stream Status bits 0 and 1 are logically ORed to become the Vertical Blank status bit and status bits 8 9 and 10 are logically ORed to become the Display Event status bit These 2 sets of status bits are on separate bytes for future expansion purposes The architecture allows each byte to be logically ORed The enables for each status bit is in the corresponding bit or the upper word If a status enable bit is asserted then the corresponding status bit is considered in the interrupt generation The Status bits capture the event if enabled and are cleared by writing a 1 to the bit This register has separate byte enables for writing 31 27 Reserved FP Hot Vert Line Plug Comp En Enable 23 18 17 16 Reserved Verit Blank OVL Reg En Upd En 15 14 11 10 9 8 FP Hot Reserved FP Hot VSYNC Vert Line Plug Status Plug Comp Interrupt Reserved Verit BInk OVL Reg Dply Event Upd VbInk Sel Sel E 31 27 Reserved Flat Panel Hot Plug Detect Enable 0 Flat Panel Hot Plug Detect Disabled 1 Flat Panel Hot Plug Detect Enabled Display Line Compare Enable 0 Display Line Compare Status Disabled 25 Vertical Sync Status Enable 0 Vertical Sync Status Disabled 1 Vertical Sync Status Enabled 1 Display Line Compare Status Enabled 359
147. T Display Color Mode Control 14 13 12 11 10 9 8 8 Bit DAC Reserved Cursor Extended CRT Reserved Palette Enable Display Status Overscan Addr Enable Read Color Reserved 000 Reserved Reserved Reserved VGA Wrap GUI Mode 0 System 0 Write 32 p o e O 31 28 Reserved 0000 Display path Graphics Gamma Enable See note 0 16 and 24 BPP graphics data bypasses palette default 1 16 and 24 BPP graphics data goes through palette 26 Overlay path Gamma Enable See note 0 Video data bypasses palette default 1 Video data goes through the palette Useful when Alpha Blending the Overlay with the Primary Display to provide gamma correction for the display device The Overlay Gamma Correction should be set up to un gamma the overlay surface bringing it into the linear space before performing the alpha blending Both the primary display 27 1 and the Overlay 26 1 should be passed through the palette after alpha blending to provide proper gamma correction for the display device 25 21 Reserved 00000 20 CRT Control Signal Delay This bit affects CRT Display enable and CRT Blank signal delay with respect to CRT HSYNC and CRT VSYNC when the standard VGA pixel pipeline is used by CRT display engine This bit has no effect on Flat Panel centering or optimized timing modes 0 CRT Display Enable and CRT Blank are delayed for standard VGA compatibility default 1 CRT Display Enable and CRT Blank are not delayed
148. T _FOR_EVENT instruction This instruction overrides any previous EXCL instruction The format is ee 31 29 Client 000 Instruction Parser 28 23 Instruction Target 12h Reserved Dword Length 00h 31 16 Start Scan Line Number Line 0 is the first line of the display frame End Scan Line Number Line 0 is the first line of the display frame 160 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 11 2 14 GFXCMDPARSER_LOAD_SCAN_LINES_EXCL This instruction is used to initialize the scan line window registers in the Display engine If the display refresh is outside this window the display engine asserts a signal that is used by the instruction parser to process the WAIT_FOR_EVENT instruction This instruction overrides any previous INCL instruction The format is A Client 000 Instruction Parser a 23 Instruction Target 13h a 6 Reserved DWord Length 00h 9 _ 16 Start Scan Line Number Line 0 is the first line of the display frame 15 0 End Scan Line Number Line 0 is the first line of the display frame 11 2 15 GFXCMDPARSER_STORE_DWORD_IMM This instruction immediately causes a system write of the data word in the packet to the address which is also in the instruction packet Note All store DWords will invalidate the host graphics pre fetch cache The GFXCMDPARSER STORE DWORD IMM instruction format is a a S 29 Client 000 Instruction Parser ay 23 Instruction Target 20h a 6 Re
149. The lower 3 bits are used to indicate the position of the first valid byte within the first Quadword of the source data NOTES This is a working register If BR12 is read while the BLT Engine is busy the contents are unpredictable The value contained in this register while the BLT Engine is busy has no relationship to the programmed value that can be read when the BLT Engine is idle 195 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 14 BR13 BLT Raster OP Control and Destination Pitch Memory Offset Address 40034h Default 0000 xxxx Attributes RO DWord accessible 31 30 29 28 27 26 25 24 23 16 x Mon Mon Dynamic Dir Src Pat Color Raster Operation Select Trans Trans Depth Reserved Destination Pitch Offset Must be Zero ee O Solid Pattern Select This bit applies only when the pattern data is monochrome This bit determines whether or not the BLT Engine actually performs read operations from the frame buffer to load the pattern data Use of this feature to prevent these read operations can increase BLT Engine performance if use of the pattern data is indeed not necessary The BLT Engine is configured to accept either monochrome or color pattern data via the opcode field 0 This causes normal operation with regard to the use of the pattern data The BLT Engine proceeds with the process of reading the pattern data and the pattern data is used as the pattern operand for all bit wise operations The BLT Eng
150. VARIABLES The GFXRENDERSTATE DEST BUFFER VARIABLES instruction is used to specify the information about the destination buffer This information is used to initialize rendering hardware parameters The destination buffer contains the pixel color data for the scene being rasterized by the 3D Rendering Engine This is a non pipelined state variable Two examples of how the Origin BIAS works are shown below Origin Bias 0 0 0 0 Origin Bias 0 5 0 5 1 75 0 25 0 origin vsd The format is 31 29 Client 03h Rendering Engine 28 24 3DStateMWNP Non pipelined 1Dh 23 16 Opcode 85h DWORD_LENGTH 0 251 Intel 815 Chipset Graphics Controller PRM Rev 1 0 cs 1 31 24 Reserved 00h 23 20 Destination Origin Horizontal Bias This is an unsigned value 0 4 that is used to bias the origin of the X values associated with the vertices of a primitive The unbiased origin is located in the upper left corner of a square pixel with the center located at 0 5 0 5 A bias value of 8h would move the origin toward the right such that an X value of 0 0 would specify the center of a pixel 19 16 Destination Origin Vertical Bias This is an unsigned value 0 4 which is used to bias the origin of the Y values associated with the vertices of a primitive The unbiased origin is located in the upper left corner of a square pixel texel with the center located at 0 5 0 5 A bias value of 8h would move the origin
151. Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 368 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 82 182 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 369 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 640x350_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed
152. Watermark for 24 bpp at 133 MHz local memory speed 393 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1024X768_60Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 394 OxA3 Intel 815 Chipset Graphics Controller PRM Rev 1 0 CROO OxA1 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 395 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1024X768_75Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 b
153. _1 TT ToS 28100h 28108h 256 256 261 256 a 256th Scan Line Note Drawing is not to scale 0 479 639 a79 b_bitS5 vsd The figure above shows an example of contiguous graphics data a horizontal line made up of six adjacent pixels within a single scan line on a display with a resolution of 640x480 Presuming that the graphics system driving this display has been set to 8 bits per pixel and that the frame buffer s starting address of Oh corresponds to the upper left most pixel of this display then the six pixels that make this horizontal line starting at coordinates 256 256 would occupy six bytes starting at frame buffer address 28100h and ending at address 28105h In this case there is only one scan line s worth of graphics data in this single horizontal line so the block of graphics data for all six of these pixels exists as a single contiguous block comprised of only these six bytes The starting address and the number of bytes are the only pieces of information that a BLT engine would require to read this block of data The simplicity of the above example of a single horizontal line contrasts sharply to the example of discontinuous graphics data depicted in the figure below The simple six pixel line of the figure above is now accompanied by three more six pixel lines placed on subsequent scan lines resulting in the 6x4 block of pixels shown 57 Intel 815 Chipset Graphics Contr
154. a exists in the frame buffer starting at the first byte of the frame buffer Vertical Blanking Start Bit 9 The vertical blanking start is a 10 bit or 12 bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical blanking start is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Blanking Start Register CR15 and the most and second most significant bits are supplied by this bit and bit 3 of the Overflow Register CR09 respectively In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical blanking start is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Blanking Start Register CR15 and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Blanking Start Register CR33 In extended modes neither this bit nor bit 3 of the Overflow Register CR09 are used This 10 bit or 12 bit value should be programmed to be equal to the number of scan line from the beginning of the active display area to the beginning of the blanking period Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical blanking period begin
155. a retrace signal of W the following algorithm is used Value of Horizontal Sync start Register CRO4 width of horizontal retrace signal in character clock units 5 bit result to be programmed in this field 113 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 8 CRO06 Vertical Total Register I O and Memory Offset Address 3B5h 3D5h index 06h Default 00h Attributes Read Write Group 0 Protection Ss Vertical Total Bits 7 0 This field provides the 8 least significant bits of either a 10 bit or 12 bit value that specifies the total number of scan lines This includes the scan lines both inside and outside of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical total is specified with a 10 bit value The 8 least significant bits of this value are supplied by these 8 bits of this register and the 2 most significant bits are supplied by bits 5 and 0 of the Overflow Register CRO7 In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical total is specified with a 12 bit value The 8 least significant bits of this value are supplied by these 8 bits of this register and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Total Register CR30 This 10 bit or 12 bit value should be programmed to equal the total number of scan lines minus 2 9 6 9 CR07 Overflow Register I O
156. a the PCI internal data bus In general the implementation outlined above allows for 7 logarithmically spaced breakpoints of which the 5 internal breakpoints are software definable the 2 endpoints are predefined at zero and 255 decimal The value at a given breakpoint and the breakpoint 1 using the MSB which is 1 of an 8 bit color are looked up in the table simultaneously These two points define the exact desired values at those breakpoints The values between the breakpoints are linearly interpolated using the remaining bits of the color The output of the function therefore evaluates the equation Result mX B Where m Slope B Initial Value defined at table entry N The slope m is derived by taking the difference between the breakpoint defined by N and the next successive breakpoint N 1 The value at N 1 is simply derived via the input wiring to the mux Since all slopes are defined to be positive for this function the use of an unsigned multiplier is sufficient for this function Latch Output Value Latch Address Area Of Interest Intel 815 Chipset Graphics Controller PRM Rev 1 0 The following gives a more detailed description of the algorithm A line with two coordinate points as x1 yl and x2 y2 can be defined by the following equation y2 slope x2 x1 yl This implies slope of the line is slope y2 yl x2 x1 Another point with X
157. able identifies which fields are used VW or ignored for various permutations The first two columns identify which cases either discrete or integrated graphics devices use The Pitch field must be specified in all cases 217 Intel 815 Chipset Graphics Controller PRM Rev 1 0 218 Figure 34 Discrete Integrated Base Utilize Fence Fence Tiled Tile Surface Device Device Address Bits Registers Range Hit Surface Walk 31 26 Ew SO e o j e i e evans ee ee rr vance ee ve fw tt The pitch specified in this instruction must be the same as the pitch in the corresponding fence register Surfaces that contain mip maps are located within a single rectangular area of memory identified by the base address of the upper left corner and a pitch The pitch must be specified at least as large as the next power of two equal to or greater than the widest mip map These surfaces may be overlapped in memory and must adhere to the following memory organization rules e The Base Address must be 4 KB aligned e Each successively smaller mip map must lie vertically below and left aligned e Each mip map must have its upper left corner vertically aligned to an even quadword address The following figures show an example of a 32x8 16 bpt and a 4x8 16 bpt map where the dashed lines identify quadwords Mip map Surface Organization Example Intel 815 Chipset Graphics Controller PRM Rev 1 0 3DstateMW
158. able specifies a value with which to offset the source z value before performing the z compare test refer to as backend Z bias This is used for coplanar polygon priority If two polygons are to be rendered which are coplanar due to the inherent precision differences induced by unique x y and z values there is no guarantee which polygon will be closer or farther By using the Z bias state variable it is possible to offset the source z value compare value before comparing with the destination z value The Z bias value is added at the LSBs of a 16 bit z representation Using the Z bias state variable affects the source z value and the result of the z bias addition is written to the z buffer Also Z biasing is supported by adding to the source z coefficients Co after setup and then interpolation is performed refer to as frontend Z bias This is done through the vertex instruction packet by enabling z bais in the control word and specifying a z bias value with the vertex data The result of the addition will be used in z function comparison The result is written back to the Z buffer Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_ MODE The provoking vertex refers to the vertex that selected the flat shaded color for the primitive In the OpenGL specification the third second triangle line vertex should used In D3D specification the first vertex should be used There is an additional mode to al
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160. ackground color to be used in the color expansion of monochrome source data during BLT operations This register is also used to support destination transparency mode and Solid color fill Whether one two three or four bytes worth of color data is needed depends upon the color depth to which the BLT Engine has been set For a color depth of 24bpp 16bpp and 8bpp bits 23 0 15 0 and 7 0 respectively are used 12 3 20 BR19 Source Expansion Foreground Color Memory Offset Address 4004Ch Default None Attributes RO DWord accessible 31 24 23 0 Reserved Must be Zero Source Expansion Foreground Color Bits 23 0 ee 31 24 Reserved Must be Zero Debug implementation specific 31 26 bmnewcliplw 12 07 23 0 Pattern Source Expansion Foreground Color Bits 23 0 These bits provide the one two or three bytes worth of color data that select the foreground color to be used in the color expansion of monochrome source data during BLT operations Whether one two or three bytes worth of color data is needed depends upon the color depth to which the BLT Engine has been set For a color depth of 24bpp 16bpp and 8bpp bits 23 0 15 0 and 7 0 respectively are used 201 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 21 S SLADD Source Scan Line Address Memory Offset Address 40074h Default None Attributes RO DWord accessible 31 26 25 0 Reserved Must Source Scan Line Address Bits 25 0
161. active time The Top compare register operator is a less than or equal while the Bottom compare register operator is a greater than or equal The results of these two comparisons are communicated to the command stream controller for generating interrupts status and command stream flow control wait for scanline These registers can be loaded from the command stream and read through the PCI When in TV FP centering mode scan line 0 is the first active scan line of the TV FP not the first line of the centered active display 31 30 28 27 16 In Ex Top Line Count Compare for Display SLC 11 00 Bottom Line Count Compare for Display SLC 11 00 oa N o Reserved 31 Inclusive Exclusive 1 Inclusive within the range 0 Exclusive outside of the range 27 16 Top Line Count Compare for Display SLC 11 00 This register is used as the top comparison less than or equal to value with the display vertical line counter 11 0 Bottom Line Count Compare for Display SLC 11 00 This register is used as the bottom comparison greater than or equal to value with the display vertical line counter Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 20 3 Pixel Pipeline Control 20 3 1 PIXCONF Pixel Pipeline Configuration Memory Offset Address 70008h Default 00000000h Attributes Read Write 31 28 Reserved 0000 Display Overlay Reserved Reserved Gamma Gamma Enable Enable Reserved 000 CR
162. ad Offset Tail Offset software has to leave at least one QWord free at all times i e the buffer is considered full when only one QWord is free e Automatic Report Head Enable Software can request to have the hardware Head Pointer register contents written reported to snooped system memory on a periodic basis This is desirable as software needs to use the Head Offset to determine the amount of free space in the RB and having the Head Pointer periodically reported to system memory provides a fairly accurate Head Offset value automatically i e without having to explicitly store a Head Offset value via an instruction The Head Pointer register will be stored at an RB specific displacement into the hardware status page defined by the HWSTAM register Ring Buffer Characteristics Alignment 4 KB page aligned Length Programmable in numbers of 4 KB pages Start Pointer Programmable page aligned address of the buffer Head pointer Programmable to initially setup ring Hardware maintained DWord Offset in the ring buffer Pointer wraps DMA pointer Hardware maintained DMA request Double QWord Offset Pointer wraps Tail pointer Programmable Double QWord Offset in the ring buffer Ring Buffer Initialization Before initializing a RB software must first allocate the desired number of 4 KB pages for use as buffer space Then the RINGBUF registers associated with the RB are programmed Once the Ring Buffer Valid bit is set the RB wi
163. ady been read Suggested Starting Points for Possible Source amp Destination Overlap Situations Destination Destination Destinatior ttt Source Source Source Source Destination Source Source Destination Destination Source Source Destination Source Source Source Source Destinatio Destination EFEFEF Destinatior Hi b_blt4 vsd The figure above shows the recommended lines and pixels to be used as starting points in each of 8 possible ways in which the source and destination locations may overlap In general the starting point should be within the area in which the source and destination overlap Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 6 2 Basic Graphics Data Considerations 6 2 1 Contiguous vs Discontinuous Graphics Data Graphics data stored in memory particularly in the frame buffer of a graphics system has organizational characteristics that often distinguish it from other varieties of data The main distinctive feature is the tendency for graphics data to be organized in a discontinuous block of graphics data made up of multiple sub blocks of bytes instead of a single contiguous block of bytes Figure 12 Representation of On Screen Single 6 Pixel Line in the Frame Buffer 0 0 639 N 63 32 34 o 270F8h
164. aeeeseenaeeeeseaes 353 20 2 DISP_SLC Display Scan Line Count Range Compare ceeeeeseeeeeeeeteeeeeenaes 354 20 3 Pixel Pipeline Control ccccccecccecececcce cece ee eeeeceaeeeceeeeceaeaeeeceeeeesesqecaeeeeeeeeesessenaeeeeees 355 20 3 1 PIXCONF Pixel Pipeline Configuration cccccceecseeseeeeeseeneeeeeeeneeees 355 20 3 2 BLTCNTL BLT Control onia T E a a aa 357 20 3 3 SWEF 1 3 Software Flag ReQisters ccccceeeeeeeeeeeeeeeeeceeeeeeenieeeeeeaes 357 20 3 4 DPLYBASE Display Base Address Register cccceeeeeeeeeteeeeeeneees 358 20 3 5 DPLYSTAS Display Status Select Register eccceeeeeeeeeereeeeeeeneees 359 20 4 hardware Cursolisc 4 sain vet della Rei Sie 361 20 4 1 CURCNTR Cursor Control Register ccceeeceeeeseeeeeeesieeeeeenieeeeseaes 361 20 4 2 CURBASE Cursor Base Address Register ceeeeeeeeeesteeeenteeeeeenaes 362 20 4 3 CURPOS Cursor Position Register cccceeseeeeeesteeeeeesneeeeeenneeeeeenaes 362 Appendix A Mode Parameters ccccccccceceeeneeeeeeneeeeeeineeeeeeceeeeesceeeeeeneeeeeeaeeeeeeneeeseenaeeeeeeaas 363 intel Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25
165. al Display Pixels 15 11 10 0 Reserved Vertical Active Display Pixels p ooo o e OS 27 16 Vertical Total Display Pixels Total vertical display lines This 12 bit field provides a vertical total up to 4096 lines encompassing 2048 active display lines top bottom border lines and vertical retrace period 10 0 Vertical Active Display Pixels Active vertical display lines This 11 bit field provides vertical active display resolution up to 2048 lines Note that the first vertical active display line always starts at 0 Intel 815 Chipset Graphics Controller PRM Rev 1 0 VBLANK Vertical Blank Register Address Offset 60010h Default Value 00000000h Access Read Write Size 32 bits 31 28 27 16 15 12 11 0 Reserved Vertical Blank Start ee 27 16 Vertical Blank End Vertical blank end expressed in terms of absolute line number relative to the vertical active display start Note Vertical blank will be deasserted when vertical total occurs irrespective of what is programmed in vertical blank end Vertical Blank Start Vertical blank start expressed in terms of absolute line number relative to the vertical active display start 337 Intel 815 Chipset Graphics Controller PRM Rev 1 0 17 6 338 VSYNC Vertical Sync Register Address Offset 60014h Default Value 00000000h Access Read Write Size 32 bits 31 28 27 16 Reserved Vertical Sync End 15 12 11 0 Reserved Vertical Sync Start p ooo o e
166. aller than the destination window then the last pixel or last scan line accessed is used to fill the right and bottom areas The minimum source width per operand Y U and V for planar formats packed formats have only one operand is two QWords SWID Source Width Register Memory Address Offset 34h R W On chip Reg Mem Addr Offset 30134h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 24 23 16 15 9 8 0 ce 23 16 UV Source Width The number of bytes contained in a single line of planar UV source data This is unused in packed modes and for planar modes it is used for the U and V source width assumed to be the same or in the interleaved mode YI64 as TBD When the last pixel is reached and the complete destination window has not been filled this pixel will be repeated until the end of the destination window When displaying YUV 4 1 1 data this field contains the number of U bytes which identical to the number of V bytes and 1 4 of the Y bytes When displaying YUV 4 2 2 data the atomic unit is a doubleword 2 Ys U V When displaying YUV 4 1 1 data the atomic unit is 3 doublewords 8 Ys 2U 2V The starting offset within the buffer must reflect this restriction Y RGB Source Width The number of bytes contained in a single line of source data In planar modes this is the Y source width This should include all contributing pixel data When the last pixel is reached a
167. an external analog display monitor 31 16 15 13 12 11 10 9 8 Reserved DDDA DDDA DDDA DDDA DDDA Data In Data value Data Mask Direction Direction value Mask Reserved DDCK DDCK DDCK DDCK Data value Data Mask Direction Direction value Mask ee 31 16 Reserved 15 13 Reserved 12 DDDA Data In RO This is the value that is sampled on the DDDA pin as an input The Data In bits 12 4 of the GPIOA GPIOB register are read only however data is only latched into these bits when a write is done to the respective bytes of the GPIOA GPIOB register Thus a read of the Data In bits must be preceded with a dummy write DDDA Data Value R W This is the value that should be place on the DDDA pin as an output This value is only written into the register if DDDA DATA MASK is also asserted The value will appear on the pin if this data value is actually written to this register and the DDDA DIRECTION VALUE contains a value that will configure the pin as an output 10 DDDA Data Mask R W This is a mask bit to determine whether the DDDA DATA VALUE bit should be written into the register 0 Do NOT write DDDA Data Value bit default 1 Write DDDA Data Value bit DDDA Direction Value R W This is the value that should be used to define the ouput enable of the DDDA pin This value is only written into the register if DDDA DIRECTION MASK is also asserted The value that will appear on the pin is defined by what is in the register for
168. anual flips can occur by an update of the overlay registers due to the writing of the Overlay Update Address Register when the register data specifies that the buffer field should be changed or through a command packet that specifies a register update that changes the buffer field This can also be synchronized with the TV field Manual flip command 00 Flip standard 01 Flip amp TV Out Field Automatic flipping 10 Capture Frame field 11 Capture Frame field amp TV Out Field 11 is a Reserved encoding for Intel 810 chipset Vertical Initial Phase Select Selects which initial vertical phase register to use The choice is to always use the same register or alternate for field processing between the two registers This bit will be overridden by the capture port when autoflipping 0 Use only field buffer 0 initial vertical phase 1 Use both initial vertical phase values 296 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Display Flip Type This bit affects the buffer addressing used for buffer display and the use of the initial vertical phase Frame mode starts addressing at the value contained in the buffer address register and increments by stride as it increments from line to line Initial phase selection is based on the buffer and the vertical Initial phase select bit Field mode uses the field bit to determine if the start address should be the value in the start address register
169. are Compare Compare Plane 3 Plane 2 Plane 1 Plane 0 ee Reserved Read as Os Color Compare Plane 3 0 When the Read Mode bit bit 3 of the Graphics Mode Register GR05 is set to select Read Mode 1 all 8 bits of each byte of each of the 4 memory planes of the frame buffer corresponding to the address from which a processor read access is being performed are compared to the corresponding bits in this register if the corresponding bit in the Color Don t Care Register GRO7 is set to 1 The value that the processor receives from the read access is an 8 bit value that shows the result of this comparison wherein value of 1 in a given bit position indicates that all of the corresponding bits in the bytes across all of the memory planes that were included in the comparison had the same value as their memory plane s respective bits in this register 9 3 5 GR03 Data Rotate Register I O and Memory Offset Address 3CFh Index 03h Default OUh U Undefined Attributes Read Write 4 3 7 5 2 0 Reserved Read as Os Function Select These bits specify the logical function if any to be performed on data that is meant to be written to the frame buffer using the contents of the memory read latch just before it is actually stored in the frame buffer at the intended address location 00 Data being written to the frame buffer remains unchanged and is simply stored in the frame buffer 01 Data being written to the frame buf
170. ask programmable e Context 1 is intended to be used for StretchBLT In Context 1 Blending is not supported for Stretch BLT In this context Blending is only supported for Sub Picture 255 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 256 intel 14 14 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Clock Control Registers The clock control registers are accessed by writing to the memory mapped address offset The Intel 815 chipset has three PLLs to generate all the clocks The Host PLL generates the host clock whose frequency is controlled by an external strap In addition the Host PLL generates the system and local memory core clock and graphics core clock The Hub PLL generates the clock for the Hub Interface unit The Display PLL generates the display or LCD clock The display clock can be controlled by three blocks of registers DCLK0 DCLK1 and DCLK2 Each display clock has its own Display Clock i Divisor registers for M N and a byte of Display amp LCD Clock Divisor Select Register within which are P Divisor values and can be programmed independently DCLKO and DCLK1 normally are programmed to 25 175 MHz and 28 322 MHz respectively VGA compatible clocks DCLK2 is used for non VGA modes The Display Clock i Divisor register and the appropriate byte of Display amp LCD Clock Divisor Select Register are programmed with the loop parameters to be load
171. at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 390 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 391 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 854X480_75Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 392 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed
172. at address 20080h 63 Intel 815 Chipset Graphics Controller PRM Rev 1 0 64 Figure 20 Pattern Data for Example Pattern Fill BLT Pattern Data 7 0 100000h 100008h 100010h 100018h 100020h 100028h 100030h 100038h 7 7 b_blt22 vsc As shown in figure above the pattern data occupies 64 bytes starting at address 100000h As always the pattern data represents an 8x8 array of pixels The BLT command packet is used to select the features to be used in this BLT operation and must be programmed carefully The vertical alignment field should be set to 0 to select the top most horizontal row of the pattern as the starting row used in drawing the pattern starting with the top most scan line covered by the destination The pattern data is in color with a color depth of 8 bits per pixel so the dynamic color enable should be asserted with the dynamic color depth field should be set to 0 Since this BLT operation does not use per pixel write masking destination transparency mode this field should be set to 0 Finally the raster operation field should be programmed with the 8 bit value of FOh to select the bit wise logical operation in which a simple copy of the pattern data to the destination takes place Selecting this bit wise operation in which no source data is used as an input causes the BLT engine to automatically forego either reading source data from the frame buffer or waiting for the host processor
173. be placed in Ring and Batch Buffers The following subsections provide a brief overview of the GC instructions by client type Figure 29 provides a diagram of the formats of the header DWords for all GC instructions Table 13 provides a list of instruction mnemonics by client type 10 5 1 Instruction Parser Instructions Instruction Parser IP instructions are basically those instructions which do not require processing by the 2D or 3D Rendering Mapping engines The functions performed by these instructions include e Control of the instruction stream e g Batch Buffer commands breakpoints ARB On Off etc e Hardware synchronization e g flush wait for event e Software synchronization e g Store DWORD report head e Graphics buffer definition e g Display buffer Overlay buffer 3D Destination and Z buffer e Miscellaneous functions Refer to the Instruction Parser Instructions Chapter for a description of these instructions 10 5 2 2D Instructions The 2D instructions include various flavors of Blt operations along with instructions to set up the Blt engine state without actually performing a Blt Most instructions are of fixed length though there are a few instructions that include a variable amount of inline data at the end of the instruction Refer to the 2D Instructions Chapter for a description of these instructions 149 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 10 5 3 3D Instructions The 3
174. beginning of the active display area of a screen In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 this value is described in 10 bits with bits 7 2 of the Overflow Register CRO7 supplying the 2 most significant bits In extended modes where bit 0 of the I O Control Register CR80 is set to 1 this value is described in 12 bits with bits 3 0 of the Extended Vertical Sync Start Register CR32 supplying the 4 most significant bits This 10 bit or 12 bit value should equal the vertical sync start in terms of the number of scan lines from the beginning of the active display area to the beginning of the vertical sync pulse Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical sync pulse begins 122 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 19 CR11 Vertical Sync End Register I O and Memory Offset Address 3B5h 3D5h index 1 1h Default 0U00 UUUUb U Undefined Attributes Read Write 7 6 5 4 3 0 Protect Reserved Vert Int Vert Int Vertical Sync End Regs 0 7 Enable Clear a e ____ Protect Registers 0 7 Note that the ability to write to Bit 4 of the Overflow Register CR07 is not affected by this bit i e bit 4 of the Overflow Register is always writeable 0 Enable writes to registers CR 00 07 default 1 Disable writes to registers CR 00 07 Reserved In t
175. bit to generate an interrupt at 1 DE active Either a horizontal retrace interval or a vertical retrace interval is currently taking place 81 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 1 3 FCR Feature Control I O and Memory Offset Address 3BAh 3DAh Write 3CAh Read Default 00h Attributes See Address above The address selection for reads is dependent on CGA or MDA emulation mode as selected via the MSR register 3 7 4 2 0 Reserved 0000 VSYNC Reserved 000 Control Descriptions Reserved Read as 0 VSYNC Control 0 Vsync output on the VSYNC pin default 1 Logical OR of VSync and Display Enable output on the VSYNC pin This capability is provided for IBM compatibility Reserved Read as 0 82 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 1 4 MSR Miscellaneous Output I O and Memory Offset Address 3C2h Write 3CCh Read Default 00h Attributes See Address above VSYNC HSYNC Page Reserved Clock Select 1 0 Polarity Polarity Select 0 Address CRT VSync Polarity 0 Positive Polarity default 1 Negative Polarity CRT HSync Polarity 0 Positive Polarity default 1 Negative Polarity Page Select In Odd Even Memory Map Mode 1 GR6 this bit selects the upper or lower 64 KB page in display memory for processor access 0 Upper page default 1 Lower page Selects between two 64 KB pages of frame buffer memory du
176. by bits 6 and 1 of the Overflow Register CRO7 In standard VGA modes these 4 bits of this register are not used In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical display enable end is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Display Enable End Register CR12 and the 4 most significant bits are supplied by these 4 bits of this register This 10 bit or 12 bit value should be programmed to be equal to the number of the last scan line within in the active display area Since the active display area always starts on the Oth scan line this number should be equal to the total number of scan lines within the active display area minus 1 133 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 31 CR32 Extended Vertical Sync Start Register I O and Memory Offset Address 3B5h 3D5h index 32h Default 00h Attributes Read Write 7 4 3 0 Reserved Read as Os This field must be Os when this register is written 3 0 Vertical Sync Start Bits 11 8 The vertical sync start is a 10 bit or 12 bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical sync start is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of
177. by writing a 0 to the associated bit in the Page Table Error Mask Register 4 Read bit 4 of the Error Status Register If it is a 1 then the target page table error has occurred and the values reported in the Page Table Error Register are valid Otherwise the target page table error has not occurred 31 9 8 Reserved BF Error Mask 7 6 5 4 3 2 1 0 CS DMA OS Error DS Error Host Error Render TL Blit NC Blit ME Error Error Mask Mask Mask Error Error Error Mask Mask Mask Mask Mask Intel 815 Chipset Graphics Controller PRM Rev 1 0 Buffer Unit Page Table Error Mask 0 Not Masked default 1 Masked Command Streamer DMA Page Table Error Mask 0 Not Masked default 1 Masked Overlay Page Table Error Mask 0 Not Masked default 1 Masked Display Page Table Error Mask 0 Not Masked default 1 Masked Host Page Table Error Mask 0 Not Masked default 1 Masked Render Operation Page Table Error Mask 0 Not Masked default 1 Masked Destination Blit Operation Page Table Error Mask 0 Not Masked default 1 Masked Source Blit Operation Page Table Error Mask 0 Not Masked default 1 Masked Mapping Engine Operation Page Table Error Mask 0 Not Masked default 1 Masked 307 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 1 5 308 RINGBUF Ring Buffer Registers Address Offset 02030h 0207Fh 02030h 0203Fh Low Priority Ring 02040h 0204Fh
178. cal blanking start is specified with a 10 bit value The most and second most significant bits of this value are supplied by bit 5 of the Maximum Scan Line Register CROQ and bit 3 of the Overflow Register CRO7 respectively In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical blanking start is specified with a 12 bit value The 4 most significant bits of this value are supplied by bits 3 0 of the Extended Vertical Blanking Start Register CR33 This 10 bit or 12 bit value should be programmed to be equal the number of scan lines from the beginning of the active display area to the beginning of the vertical blanking period Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which vertical blanking begins 9 6 24 CR16 Vertical Blanking End Register I O and Memory Offset Address 3B5h 3D5h index 16h Default Undefined Attributes Read Write This register provides an 8 bit value that specifies the end of the vertical blanking period relative to its beginning ee Vertical Blanking End Bits 7 0 This 8 bit value should be set equal to the least significant 8 bits of the result of adding the length of the vertical blanking period in terms of the number of scan lines that occur within the length of the vertical blanking period to the value that specifies the beginning of the vertical blanking period see the des
179. cal retrace interval The horizontal retrace interval is the period during the drawing of each scan line containing active video data when the active video data is not being displayed This period includes the horizontal front and back porches and the horizontal sync pulse The horizontal retrace interval is always longer than the horizontal sync pulse The vertical retrace interval is the period during which the scan lines not containing active video data are drawn It is the period that includes the vertical front and back porches and the vertical sync pulse The vertical retrace interval is always longer than the vertical sync pulse Display Enable is a status bit bit 0 in VGA Input Status Register 1 that indicates when either a horizontal retrace interval or a vertical retrace interval is taking place In the IBM EGA graphics system and the ones that preceded it including MDA and CGA it was important to check the status of this bit to ensure that one or the other retrace intervals was taking place before reading from or writing to the frame buffer In these earlier systems reading from or writing to frame buffer at times outside the retrace intervals meant that the CRT controller would be denied access to the frame buffer in while accessing pixel data needed to draw pixels on the display This resulted in either snow or a flickering display The term Display Enable is an inaccurate description for this status bit since the name
180. ce color the iterated alpha and or a constant color State Variable Relationships Coordinate Sets lt m Map Information Texels Blending Stages The following equations are supported by each blending stage Colorout Arg1 Arg2 Add Colorout Arg1 Arg2 0 5 Add Signed Excess 128 Colorout Otterated Arg 1 Otiteratea Arg2 The settings for these stages are specified in the following instruction When enable a stage for color operation the corresponding alpha stage will also be enabled The arguments and operation fields of the corresponding alpha stage must be programmed accordingly 227 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Come De fe 21 20 Update Blending Stage Index The valid range is 0 2 Current Accumulator Select Mask 0 Do not update 1 Update Write result to Current Register or Accumulator Select 0 Current Register default 1 Accumulator Color Arg1 Mask 0 Do not update 1 Update Color Arg1 Valid values are Oh All Ones 1h Color Factor 2h Accumulator Color illegal setting for stage 0 3h Iterated Color 4h Specular Color 5h Current Color 6h TexelO Color 7h Texel1 Color Replicate Arg1 Alpha to Color Channels 0 Do not Replicate Alpha to Color Channels 1 Replicate Alpha to Color Channels Invert Color Arg1 0 Do not Invert Argument 1 Inve
181. ce data Where a bit in the source data has the value of 0 the color specified in the background color register is used as the source operand in the bit wise operation for the pixel corresponding to the source data bit and the bytes at the destination corresponding to that pixel are written with the result Where a bit in the source data has the value of 0 the byte s at the destination corresponding to the pixel to which the source data bit also corresponds are simply not written and the data at those byte s at the destination are allowed to remain unchanged 196 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Descriptions Monochrome Pattern Transparency Mode This bit applies only when the pattern data is monochrome This bit determines whether or not the byte s at the destination corresponding to the pixel to which a given bit of the pattern data also corresponds will actually be written if that pattern data bit has the value of 1 This feature can make it possible to use the pattern as a transparency mask The BLT Engine is configured to accepted either monochrome or color pattern data via the opcode in the Opcode and Control register This causes normal operation with regard to the use of the pattern data Where a bit in the pattern data has the value of 0 the color specified in the background color register is used as the pattern operand in the bit wise operation for the pixel corresponding to the pattern data bit and
182. ce pitch must be 16 QWs for Tiled organization of memory i e MAP_INFO _DWI1 3 0 2 4h e Texture surface pitch in bytes must be gt Map_ Width in bytes Le 8 2 MAP_INFO_DWI 30 gt 9 MAP_INFO_DW213 0 now 2mapsize 1 8 2 MAP_INFO_DWIB 0 gt MAP INFO _DW2 9 0 pow2mapsize 0 e Texture base address MAP_INFO_DW3 26 4 must be QW aligned Also 2n surface pitch lt texture base address lt 2n 1 surface pitch e Color Pitch and Z Pitch Pitch of tiled region e Only Bit 26 4 in the Texture Map Base Address are used in texture address calculation Context 1 e No state variable pipelining in Context 1 Change of state variables required a pipeline flush e No Multi TX in context 1 Only texel 0 is available The texture surface pitch MAP_INFO_DW1 3 0 is expressed in terms of og2 pitch in QWs 2 The Color Z pitch DEST_BUFFER INFO _DW2 1 0 Z_ BUFFER INFO _DW1 1 0 is expressed in terms of og2 pitch in QWs 64 254 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel e Z buffering is not supported Z_en is overloaded to 0 e State variables that have a context1 are blend_en dest_blend 3 0 src_blend 3 0 xoffset 1 1 0 yoffset 11 0 all Dest Buffer format variable packet all Map Info packet Map Cache enable e Limit support on FVF packet format is supported TX coordinate count 1 Specular Fog Present 0 Diffuse Alpha Present programmable Z_Offset_Present 0 Position M
183. cleared by a processor write of a one to the appropriate bit contained in the error id register followed by a write of a one to this bit in the IIR Further information on the source of the error comes from the Error Status Register which along with the Error Mask Register determine which error conditions will cause the error status bit and the interrupt to occur The intent is to use the error bits to detect errors during debug and testing Error conditions during normal operation should not occur e MM LM Refresh timer error Indicates a refresh request buffer overrun e Page Table Error Indicates a page table error e Display or Overlay under run Set on either a display or overlay under run error See display and overlay status registers to determine source of the error e Instruction Parser Error The Instruction Parser encounters an error while parsing an instruction Sync Status Toggle This bit is toggled when the instruction parser completes a flush with the sync enable bit active in the instruction parser mode register The toggle event will happen after all the graphics engines are flushed The store dword resulting from this toggle will cause the processor s view of graphics memory to be coherent as well invalidate the host graphics cache Primary Display Flip Pending Status bit is set on a pending flip and cleared when the flip occurs whereas IIR reflects Flip Occurred which is contrary to the general definition
184. clude e Support for a single processor configuration Intel 815 Chipset Graphics Controller PRM Rev 1 0 e 64 bit AGTL based System Bus Interface at 66 100 133 MHz e 32 bit Host Address Support e 64 bit System Memory Interface with optimized support for SDRAM at 100 133 MHz e Integrated 2D amp 3D Graphics Engines e Integrated H W Motion Compensation Engine e Integrated 230 MHz DAC e Integrated Digital Video Out Port e 133 MHz Display Cache e AGP 1X 2X 4X Controller Figure 2 Intel 82815 Chipset GMCH Block Diagram System Bus Interface t Memory Interface h y Buffer _ Display Engine 3D Engine HW Motion Comp 3D Analog ca Engine Display H DAC Overlay Sr Out _ 2D Engine HW Cursor i Stretch cep Me BLT Eng igita Digital Video Out Video lt ia t a BLT Eng O ee Leeeeshewenoee DDC 4 2C AGP Interface AGP lt 4 Display Cache Local Memory Pins Interface Hub Interface System Memory gmch_blk2 vsd 2 2 1 Host Interface The host interface of the GMCH is optimized to support the Intel Pentium III processor and Intel Celeron processor in the FC PGA package The GMCH implements the host address control and data bus interfaces within a single device The GMCH supports a 4 deep in order queue i e
185. color depth to which the BLT engine has been set of color data that are set to carry value corresponding to either the foreground or background color that have been specified for use in this conversion process If a given bit of monochrome source data carries a value of 1 then the byte s of color data resulting from the conversion process will be set to carry the value of the foreground color If a given bit of monochrome source data carries a value of 0 then the resulting byte s will be set to the value of the background color The foreground and background colors used in the color expansion of 59 Intel 815 Chipset Graphics Controller PRM Rev 1 0 6 2 4 60 Figure 14 intel monochrome source data can be set in the source expansion foreground color register and the source expansion background color register The BLT Engine requires that the bit alignment of each scan line s worth of monochrome source data be specified Each scan line s worth of monochrome source data is word aligned but can actually start on any bit boundary of the first byte Monochrome text is special cased and it is bit packed where there are no invalid pixels bits between scan lines There is a 3 bit field which indicates the starting pixel position within the first byte for each scan line Mono Source Start The BLT engine also provides various clipping options for use with specific BLT commands BLT_TEXT with a monochrome source Clipping is suppor
186. conversion If the source data overlay is within the range then the primary display is selected If the overlay is in RGB mode the most significant bits are duplicated on the least significant to form 8 bit channels R lt 4 0 gt gt R lt 4 0 4 2 gt G lt 5 0 gt gt G lt 5 0 5 4 gt B lt 4 0 gt gt B lt 4 0 4 2 gt before the source key comparison is made Destination Color Key failing takes precedence over the Source Chroma Key failing If both fail then the primary display is selected SCLRKVH Source Color Key Value High Register Memory Address Offset 58h R W On chip Reg Mem Addr Offset 30158h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 24 23 0 i Source Key Value High This value is the high value that is compared with the overlay pixel per 8 bit channel An overlay value greater than this field on any channel that is enabled fails the comparison and passes the overlay pixel Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 9 2 _SCLRKVL Source Color Key Value Low Register Memory Address Offset 5Ch R W On chip Reg Mem Addr Offset 3015Ch RO debug path Default Value 00h Access see address offset above Size 32 bits 31 24 23 0 ee 1 Included in comparison 0 Not included in comparison 23 0 Source Key Value Low In the format of the source specifies the low end greater than or equal of the range of excluded source
187. cription of the Vertical Blanking Start Register for details 126 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 25 CR17 CRT Mode Control I O and Memory Offset Address 3B5h 3D5h index 17h Default OUUO UUUUb U Undefined Attributes Read Write Horizontal Select Retrace Row Scan Select Cntr CRT Controller Reset 0 Forces horizontal and vertical sync signals to be inactive No other registers or outputs are affected 1 Permits normal operation Word Mode or Byte Mode 0 The memory address counter s output bits are shifted by 1 bit position before being passed on to the frame buffer address decoder such that they are made into word aligned addresses when bit 6 of the Underline Location Register CR17 is set to 0 The memory address counter s output bits remain unshifted before being passed on to the frame buffer address decoder such that they remain byte aligned addresses when bit 6 of the Underline Location Register CR17 is set to 0 Note that this bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register CR17 to control how frame buffer addresses from the memory address counter are interpreted by the frame buffer address decoder as shown below CR14 6 CR17 6 Addressing Mode Word Mode Addresses from the memory address counter are shifted once to become word aligned Byte Mode Addresses from the memory address counter are not shifted DWord Mode
188. cs Mode Register c ccceeeeceeeeeeeeeeeeeeeeeeseeeeeeeseeaeeeeeenaees 93 9 3 8 GRO6 WMiscellaneous ReGISter cceceeeeeeeeeeeeeeeeeeeeeeeeseeeeeeseeaeeeseaeees 96 9 3 9 GRO7 Color Don t Care Register ceecceceeecceeeeseeneeeeseeeeeeeseeteeeeeeaees 97 9 3 10 GRO8 Bit Mask ReGister cccceeceeeeeeeseeeeeeeeeeeeeeseeeeeeeseeeeeeeseeaeeeseeaees 97 9 3 11 GR1IO Addr ss Mapping e aaa a a dade ceiiday tacts aa E a ES 98 9 3 12 GRI1 Page SeleCtOR iin a AT A T N 99 9 3 13 GR 14 1F Software Flags c ccecccceceeeeeceeceeceeeeeeeseceeaeeeeeeeeeeeeteenaees 100 9 4 Attribute Controller Registers ccccccccesescccceteeccccessecceeetsececeeneeedeenteeeaceeseneaeeetaeeeeeetens 101 9 4 1 ARX Attribute Controller Index Register ccceceeeeeeeeeeieeeeeeieeeeeeee 101 9 4 2 AR 00 0F Palette Registers 0 F cccccceceeeeeeeceeeeeeeeeeeeceeeeeeeeeteees 102 9 4 3 AR10 Mode Control Register ssssssseeesenesesrrssrtnestrresttnnesrennssennssenn 102 9 4 4 AR11 Overscan Color Register 0 ccccceeceeceeeeeeeeeeeteneeeeetieeeeersneeeee 104 9 5 9 6 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 4 5 AR12 Memory Plane Enable Register ce cescceeeeeeeeceeeeeeeeeeneeeeeeeaas 104 9 4 6 AR13 Horizontal Pixel Panning Register ccccseeceeeeseeeeeetteeeeeenaes 105 9 4 7 AR14 Color Select ReQiSter ceceee
189. cs locations Interrupt Control 01000h OOFFFh VGA and Ext VGA Registers VGA and Ext VGA Registers 31 19 00000h MMADR Regist Base pene gfx_reg_m 30 Intel 815 Chipset Graphics Controller PRM Rev 1 0 VGA and Extended VGA Control Registers 00000h 00FFFh These registers are located in both I O space and memory space The VGA and Extended VGA registers contain the following register sets General Control Status Sequencer SRxx Graphics Controller GRxx Attribute Controller ARxx VGA Color Palette and CRT Controller CRxx registers Detailed bit descriptions are provided in the VGA and Extended VGA Register Chapter The registers within a set are accessed using an indirect addressing mechanism as described at the beginning of each section Note that some of the register description sections have additional operational information at the beginning of the section Instruction Memory Interrupt Control and Error Registers 01000h 02FFFh The Instruction and Interrupt Control registers are located in main memory space and contain the following types of registers Instruction Control Registers Ring Buffer registers and page table control registers are located in this address range Various instruction status error and operating registers are located in this group of registers Graphics Memory Fence Registers The Graphics Memory Fence registers are used for memory tiling capabilities Inte
190. ct the actual value of the corresponding bit in the incoming 8 bit pixel data In direct color mode the palette is not used and the data in this register is ignored 107 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 5 2 DACSTATE DAC State Register I O and Memory Offset Address 3C7h Default 00h Attributes Read Only 7 2 1 0 Reserved 000000 DAC State J e Reserved Read as Os 1 0 DAC State This field indicates which of the two index registers was most recently written Bits 1 0 Index Register Indicated 00 Palette Write Index Register at I O Address 3C7h default 01 Reserved 10 Reserved 11 Palette Read Index Register at I O Address 3C8h 9 5 3 DACRX Palette Read Index Register I O and Memory Offset Address 3C7h Default 00h Attributes Write Only ee Palette Read Index The 8 bit index value programmed into this register chooses which of 256 standard color data positions within the palette or which of 8 alternate color data positions depending on the state of a bit in the Pixel Pipeline Control 0 Register are to be made accessible for being read via the Palette Data Register DACDATA The index value held in this register is automatically incremented when all three bytes of the color data position selected by the current index have been read 9 5 4 DACWX Palette Write Index Register I O and Memory Offset Address 3C8h Default 00h Attributes Write Only ee Palette Wri
191. d Z_BIAS 7 0 FOG_CLR 23 0 ALPHA REF 7 0 ALPHA FUNC 2 0 KILL PIXEL COLOR KEYH 15 0 COLOR KEYL 15 0 COLOR INDEX 7 0 DEST BUFFER VARIABLES DRAWING RECTANGLE INFO SCISSOR RECTANGLE INFO These have been grouped appropriately into packets that tell the instruction parser that these are non pipelined state variables The 3D pipeline will be flushed up to and including the Color Calculator stage before these state variables are updated The pixel cache or the streamers do not need to be flushed for state change It is important for the application to group these changes into one pipeline to minimize performance impact This optimization has no software impact other than a slight performance impact 213 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 5 GFXRENDERSTATE_MAP_TEXELS The Mapping Engine is capable of generating at most two texels per pixel The texels may be obtained from two separate maps or the same map using different u v coordinates The binding between the texels which are generated by the engine and the coordinate set and the map information state is specified with this instruction The texels are generated in the order specified by the Texel Index If no texel is enabled texture mapping is disabled and this is the default condition If one of the two texels is enabled one texture coordinate will be used for texture mapping If both texels are enabled both texture coordinates will be used for text
192. d Register 0 cceeseeeceeeeeeeeeeeeeteeeeetneeeeeeee 126 9 6 25 CR17 CRT Mode Control carini aae REE ARR AER IEE 127 9 6 26 CR18 Line Compare Register sesssssseesssirsserrssetrrssrtrnssrtnnsstennssrennnne 131 9 6 27 CR22 Memory Read Latch Data Register 0 ccceeeeceeeeeeteeeeeenteeeeeeee 131 9 6 28 CR24 Test Register for Toggle State of Attribute Controller Register 132 9 6 29 CR30 Extended Vertical Total Register eeceeeeeeseeeeeeteeeeeetteeeeeeee 132 9 6 30 CR31 xtended Vertical Display End Register cccceeeceeeeeeeeeee 133 9 6 31 CR32 Extended Vertical Sync Start Register 0 ceeeeeeeeeeeeteeeeeeee 134 9 6 32 CR33 Extended Vertical Blanking Start Register 0 ceseeseereeeee 135 9 6 33 CR35 Extended Horizontal Total Time Register 136 9 6 34 CR39 Extended Horizontal Blank Time Register 136 9 6 35 CR40 Extended Start Address Register ccececceeeseteeeeeireeeeenteeeeeeee 137 9 6 36 CR41 Extended Offset Register cccceeceeeeseteeeeeseteeeeettieeeeenieeeeeeaa 138 9 6 37 CR42 Extended Start Address High Register 138 9 6 38 CR70 Interlace Control Register cccccccecceeeeeeeeeeeseneeeeeenieeeeeeneeeeeena 139 9 6 39 CR80 1 O Controls ayeee ieee ener 139 9 6 40 GR81 ReSCINVEO is aos EE chastenes vas E AAAA 140 9 6 41 CR82 Blink Rate Control cceceeeeeeeeeeeeeeeneeeee entree ee seeeeeseeeeesieeeeeaa 140
193. d accesses one of the registers and a write accesses the other register See the I O and memory map tables for details Reference Documents The following documents should be available for reference when using this specification e Intel 815 Chipset Intel 82815 chipset Graphics and Memory Controller Hub GMCH External Design Specification EDS e Intel 82801AA ICH and Intel 82801 AB ICH0 I O Controller Hub Datasheet e Intel 82801BA ICH2 I O Controller Hub External Design Specification EDS e Intel 82802AB 82802AC Firmware Hub FWH Datasheet Intel 815 Chipset Graphics Controller PRM Rev 1 0 Intel 815 Chipset Overview The chipset consists of an Intel 82815 chipset Graphics and Memory Controller Hub GMCH an I O Controller Hub ICH for the I O subsystem and a Firmware Hub FWH The GMCH integrates a system memory SDRAM controller that supports a 64 bit 100 133 MHz SDRAM array The Intel 815 chipset family includes e Intel 815 chipset This chipset consists of the Intel 82815 chipset GMCH the 82801AA ICH and the 82802AB 82802AC FWH e Intel 815E chipset This chipset consists of the Intel 82815 chipset GMCH the 82801BA ICH2 and the 82802AB 82802AC FWH The Intel 82815 chipset GMCH integrates a Display Cache SDRAM controller that supports a 32 bit 133 MHz SDRAM array for enhanced integrated 2D and 3D graphics performance Multiplexed with the display cache interface is an AGP control
194. d expressed in terms of absolute pixel number relative to the horizontal active display start Note An asserted HBlank will be deasserted when HTotal occurs irrespective of what is programmed in HBlank end Horizontal Blank Start Horizontal blank start expressed in terms of absolute pixel number relative to the horizontal active display start 334 Intel 815 Chipset Graphics Controller PRM Rev 1 0 HSYNC Horizontal Sync Register Address Offset 60008h Default Value 00000000h Access Read Write Size 32 bits 31 28 27 16 Reserved Horizontal Sync End 15 12 11 0 Reserved Horizontal Sync Start ee 27 16 Horizontal Sync End Horizontal sync end expressed in terms of absolute pixel number relative to the horizontal active display start Notes 1 Minimum HSYNC width is 1 pixel clock 1 An asserted HSYNC will be cleared as soon as HTOTAL end is reached regardless of the value in the HSYNC End register 11 0 Horizontal Sync Start Horizontal sync start expressed in terms of absolute pixel number relative to the horizontal active display start Note that when HSYNC Start is programmed equal to HBLANK Start both HSYNC and HBLANK will be asserted on the same pixel clock 335 Intel 815 Chipset Graphics Controller PRM Rev 1 0 17 4 336 VTOTAL Vertical Total Register Address Offset 6000Ch Default Value 00000000h Access Read Write Size 32 bits 31 28 27 16 Reserved Vertical Tot
195. d in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BROY 31 00 Destination Address Address of the first byte to be written ta 25 00 are implemented in Intel 810 chipset ati 14 Reserved Must be Zero Source Pitch quadword aligned and signed 13 00 are implemented in Intel 810 chipset 5 BR12 31 00 Source Address 25 00 are implemented in Intel 810 chipset 173 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 11 MONO_SRC_COPY_BLT This BLT instruction performs a monochrome source copy where the only operands involved is a monochrome source and destination The source and destination operands cannot overlap which means that the X direction must always be forward All non text monochrome sources are word aligned At the end of a scan line the monochrome source the bits until the next word boundary must be ignored The Monochrome source data bit position field lt 2 0 gt indicates which bit position within the first byte of the scan line should be used as the first source pixel The monochrome source transparency mode indicates whether to use the source background color or deassert the write enables when the bit in the source is 0 When the source bit is 1 the source foreground color is used in the ROP operation The ROP value chosen should involve the Mono source data in the ROP operation The Destination pitch can either be positive
196. d in this document For details on PCI configuration registers refer to the Intel 815 Chipset 82815 Graphics and Memory Controller GMCH EDS Figure 5 shows a high level representation of the system memory address map Figure 6 provides additional details on mapping specific memory regions as defined and supported by the GMCH chipset Figure 5 System Memory Address Map 4GB c ovrerp rg PCI j f Memory Local Memory Address Memory Mapped Range Range Range Top of the Main Memory 4 ceeee cece ee l Main Memory Address Independently Range Programmable Non 0 Overlapping Memory Windows mem_map_s Figure 6 Detailed Memory System Address Map System Memory Space 64 GB Extended P6 Memory 4 GB Max TOM OFFFFFK _ _ 1 MB Pcl Upper BIOS Area femo 512 MB a 64 KB 2099 Fa pevoedt Sanne OEFFFF Lower BIOS Area 64 KB 16 KB X 4 0E0000 x ODEFEFA S98 KE 16MB _ y lt yY Optional ISA Hole a Expansion Card 15 MB BIOS F and Buffer Aref Main Memo 128 KB Range 16 KB x 8 i ocoo00h E 768 KB 1 MB Satna OBFFFFh Std PCI ISA mapped to the gt Video Mem i SMM Mem DOS internal AGP 128 KB 640 KB 0A0000h Compatibilit O9FFFFh 640 KB Memon DOS Area 640 KB OMB 0 000000h OKB mem_map2 vsd 29 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 3 1 Memory and I O Space Registe
197. d out texel is UNDEFINED If only non nearest neighbor texels are found to match the key those texels are effectively replaced by the nearest neighbor color alpha prior to application of the filter The Intel 815 chipset supports both blend modes The default is the DX7 implementation 31 29 Client 03h Rendering Engine 28 24 3DStateMW 1Dh 23 16 Instruction 2h DWORD_LENGTH 1 ee a 1 Reserved 00h KeyedPixelControl Write Mask 0 Do not update 1 Update 29 KeyedPixelControl 0 OLD Algorithms Intel 810 chipset Compatible If killpix mode is enabled then a pixel is killed if and only if the nearest texel is keyed out If killpix mode is disabled then for any pixel that has a keyed out nearest texel the alpha value forced to 0 The contributed RGBA of any other texels that are keyed out are replaced by the RGBA of the nearest texel and blended as usual 1 NEW Algorithms DX6 1 Kill Pixel DX7 Blend Default If killpix mode is enabled then a pixel is killed if any of the texels contributing to its color is keyed out If killpix mode is disabled then for any contributing texel which is keyed out R G B A are forced to 0 Any such texel will still be blended with the other texels as usual 4 2 Kill Pixel Write Mask 0 Do not update 1 Update 2 Kill Pixel Write When Match on Key 0 Do not Kill Pixel 1 Kill Pixel Enabling the Kill Pixel Write state prevents the pixel from b
198. date a GC state required by the pending LP stream Instruction Arbitration Rules At an arbitration point the IP will consider the current state of instruction execution i e Low Priority vs Interrupt Ring vs Batch along with the current state of the RBs and possibly pending wait events The IP will then determine how to proceed with execution given that status information and the following instruction stream priorities highest priority to lowest 1 Next instruction in batch buffer regardless of initiating ring buffer 2 Next instruction pending in IRB assuming IRB arbitration is enabled 3 Initiation of LP batch buffer including resumption of interrupted LP batch chain 4 Next instruction pending in LPRB Batch Buffer Protected Mode To ensure that the graphics controller does not corrupt system memory or graphics memory through invalid instructions from a batch buffer sequence the batch buffer instruction has a flag that can be set to indicate that it is from a non trusted source When the IP processes a non trusted batch buffer from one of the ring buffers it does not allow any immediate store DWord instructions because this instruction causes writes to system memory not gathered through the GTT The protection mode Protected or Unprotected is set in the batch buffer instruction that is in the ring buffer The protection mode set persists throughout the batch buffer sequence including batch buffers that are chained Thus
199. ddress offset above Size 32 bits 31 26 25 0 Overlay Buffer 1 V Pointer i 25 0 Overlay Buffer 1 V Pointer This register is used for YUV Planar Modes only It points to the start of the V addresses in the interleaved UV formats byte address Overlay Stride Registers These values represent the width of the buffer that contains the overlay data This is independent of the actual width displayed and is used to determine the line to line increment of the overlay buffer In two line buffer mode there is only room for 180 quadwords per scan line If the source address is not quadword aligned then for formats YUV4 2 0 YUV4 2 2 and RGB the source must be less then 720 pixels The stride must be quadword aligned OVOSTRIDE Overlay 0 Stride Register Memory Address Offset 18h R W On chip Reg Mem Addr Offset 30118h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 26 28 16 15 13 12 0 Reserved Overlay 0 UV planar Reserved Overlay 0 Y planar or Buffer Stride YUV RGB Buffer Stride a 28 16 Overlay 0 UV planar Buffer Stride Only used for YUV Planar formats and gives the U or V buffer stride in bytes This is a two s complement number and is negative during Y mirroring The low order three bits are always zero forcing a QWord alignment The range is 4 KB Overlay 0 Y planar or YUV RGB Buffer Stride Buffer Y planar or YUV RGB packed stride in bytes This is a two s comple
200. de 0 During a processor write to the frame buffer the addressed byte in each of the 4 memory planes is written with the processor write data after it has been rotated by the number of counts specified in the Data Rotate Register GRO3 If however the bit s in the Enable Set Reset Register GRO1 corresponding to one or more of the memory planes is set to 1 then those memory planes will be written to with the data stored in the corresponding bits in the Set Reset Register GROO 01 Write Mode 1 During a processor write to the frame buffer the addressed byte in each of the 4 memory planes is written to with the data stored in the memory read latches The memory read latches stores an unaltered copy of the data last read from any location in the frame buffer 10 Write Mode 2 During a processor write to the frame buffer the least significant 4 data bits of the processor write data is treated as the color value for the pixels in the addressed byte in all 4 memory planes The 8 bits of the Bit Mask Register GRO8 are used to selectively enable or disable the ability to write to the corresponding bit in each of the 4 memory planes that correspond to a given pixel A setting of 0 in a bit in the Bit Mask Register at a given bit position causes the bits in the corresponding bit positions in the addressed byte in all 4 memory planes to be written with value of their counterparts in the memory read latches A setting of 1 in a Bit Mask Regi
201. de Filter state variable identifies the filtering operation to utilize when the map is minimized and a texel is smaller than a pixel When this occurs the either Nearest or Linear filtering is performed In Nearest filtering the texel with coordinates nearest to the desired pixel value is used In Linear filtering a weighted average of a 2 by 2 area of texels surrounding the desired pixel is used The Mag Mode s Filter state variable describes operations where the map is magnified and a texel is larger than one pixel In this mode the finest texture map LOD 0 is addressed and the state variable selects between Nearest and Linear filtering In Nearest filtering the texel with coordinates nearest to the desired pixel value is used In Linear filtering a weighted average of a 2 by 2 area of texels surrounding the desired pixel is used Cae a Intel 815 Chipset Graphics Controller PRM Rev 1 0 Anisotropic Filtering Enabled Mask 0 Do not update 1 Update Anisotropic Filtering Enabled 0 Disable Anisotropic Filtering 1 Enable Anisotropic Filtering Mip Mode Filter Mask 0 Do not update 1 Update Reserved 00h Mip Mode Filter Valid values are 00 None Disable mip mapping 01 Nearest Select the nearest mip map 02 Dithered Dither between nearest mip maps 03 Linear interpolate between nearest mip maps combined with linear min mag filters this is Trilinear filtering Mag Mode Filter Mask 0 Do no
202. ding bit in this register if the corresponding bit in the Enable Set Reset Register GRO1 is set to 1 When the Write Mode bits bits 0 and 1 of the Graphics Mode Register GRO5 are set to select Write Mode 3 all processor data written to the frame buffer is rotated then logically ANDed with the contents of the Bit Mask Register GR08 and then treated as the addressed data s bit mask while value of these four bits of this register are treated as the color value 9 3 3 GR01 Enable Set Reset Register I O and Memory Offset Address 3CFh Index 01h Default OUh U Undefined Attributes Read Write Reserved 0000 Enable Enable Enable Enable Set Set Reset Set Set Reset Reset Pln Pin Reset Pin Pin 3 2 1 0 E Reserved Read as Os 3 0 Enable Set Reset Plane 3 0 This register works in conjunction with the Set Reset Register GROO The Write Mode bits bits 0 and 1 must be set for Write Mode 0 for this register to have any effect 0 The corresponding memory plane can be read from or written to by the processor without any special bitwise operations taking place 1 The corresponding memory plane is set to 0 or 1 as specified in the Set Reset Register GROO 91 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 3 4 GRO2 Color Compare Register I O and Memory Offset Address 3CFh Index 02h Default OUh U Undefined Attributes Read Write Reserved 0000 Color Color Color Color Compare Comp
203. documented by IBM ee Horizontal Character Counter 9 3 Graphics Controller Registers The graphics controller registers are accessed via either I O space or Memory space To access the registers the VGA Graphics Controller Index Register at I O address 3CEh or memory address 3CEh is written with the index of the desired register Then the desired register is accessed through the data port for the graphics controller registers at I O address 3CFh or memory address 3CFh 9 3 1 GRX GRX Graphics Controller Index Register I O and Memory Offset Address 3CEh Default OOOUUUUUb U Undefined Attributes Read Write 7 4 3 0 Reserved 0000 Graphics Controller Register Index Ce SOS Reserved Read as Os 3 0 Sequencer Register Index This field selects any one of the graphics controller registers GR 00 1F to be accessed via the data port at I O location 3CFh 90 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 3 2 GR00 Set Reset Register I O and Memory Offset Address 3CFh index 00h Default OUh U Undefined Attributes Read Write 7 4 3 2 1 0 Reserved 0000 Set Reset Set Reset Set Reset Set Reset Plane 3 Plane 2 Plane 1 Plane 0 Reserved Read as Os Set Reset Plane 3 0 When the Write Mode bits bits 0 and 1 of the Graphics Mode Register GR05 are set to select Write Mode 0 all 8 bits of each byte of each memory plane are set to either 1 or 0 as specified in the correspon
204. e Pe Start Address Bits 15 8 or 17 10 This register provides either bits 15 through 8 of a 16 bit value that specifies the memory address offset from the beginning of the frame buffer or bits 17 through 10 of a 32 bit buffer address at which the data to be shown in the active display area begins default is 0 In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the start address is specified with a 16 bit value The eight bits of this register provide the eight most significant bits of this value while the eight bits of the Start Address Low Register CROD provide the eight least significant bits In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the start address is specified with a 32 bit value Bits 31 through 24 of this value are provided by the Extended Start Address High Register CR42 Bits 23 through 18 of this value are provided by bits 5 through 0 of the Extended Start Address Register CR40 Bits 17 through 10 of this value are provided by this register Bits 9 through 2 of this value are provided by the Start Address Low Register CROD Bits 1 and 0 of this value are always 0 and therefore not provided It should be further noted that in extended modes these 32 bits from these four registers are double buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous ap
205. e snooped system memory location The location written is relative to the address programmed in the Hardware Status Page Address Register and depends on which ring buffer is active Refer to the description of the HSW_ PGA register The format is Pome Te ee 31 29 Client 000 Instruction Parser 28 23 23 28 23 Opcode 07h 220 0 Reserved MBZ 159 Intel 815 Chipset Graphics Controller PRM Rev 1 0 11 2 11 GFXCMDPARSER_ARB_ON_OFF The GFXCMDPARSER ARB ON OFF instruction is used to inform the input interface to turn on off all the rings except the ring that this instruction is executed from It can be use from a batch buffer This instruction can be used to prevent other ring buffers from interrupting an instruction sequence The format is a 31 29 Client 000 Instruction Parser 28 23 Opcode 08h Arbitration ON OFF 1 ON 0 OFF 11 2 12 GFXCMDPARSER_OVERLAY_FLIP Powe ome me Client 000 Instruction Parser Instruction Target 11h Reserved Dword Length 00h Reserved MBZ 28 03 Register Update Address This address is used by the Overlay at the next VBLANK event to start requesting data from memory Reserved MBZ 11 2 13 GFXCMDPARSER_LOAD_SCAN_LINES_INCL This instruction is used to initialize the scan line window registers in the Display engine If the display refresh is within this window the Display engine asserts a signal that is used by the instruction parser to process the WAI
206. e 1 bit5 plane 1 bit4 plane 1 bit3 plane 1 bit2 plane 1 bit1 plane 1 bitO BitO planeObit7 planeObit6 planeObit5 plane 0 bit4 plane 0 bit3 plane O bit2 plane O bit1 plane O bit O Bits 6 5 01 Two bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the palette in a pattern that alternates per byte between memory planes 0 and 2 and memory planes 1 and 3 First the even numbered and odd numbered bits of a byte in memory plane 0 are transferred via serial output bits 0 and 1 respectively while the even numbered and odd numbered bits of a byte in memory plane 2 are transferred via serial output bits 2 and 3 Next the even numbered and odd numbered bits of a byte in memory plane 1 are transferred via serial output bits 0 and 1 respectively while the even numbered and odd numbered bits of memory plane 3 are transferred via serial out bits 1 and 3 This provides a pair of 2 bit values one 2 bit value for each of 2 pixels on each transfer making possible a choice of 1 of 4 colors per pixel Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer Bit3 plane 2 bit7 plane2bit5 plane 2 bit3 plane2bit1 plane3bit7 plane 3 bit5 plane 3 bit3 plane 3 bit 1 Bit2 plane2bit6 plane 2bit4 plane2bit2 plane2bitO plane 3 bit6 plane 3 bit4 plane 3 bit2 plane 3 bit O Bit1 plane 0 bit7 planeObit5 planeObit3 plane 0 bit1 plane 1 bit7 plane 1 bit5 plane 1 bit3 plane 1 bit 1 BitO planeObit6 planeObit4 plane
207. e 2 bits 00 8 Bit Color Depth 01 16 Bit Color Depth 10 24 Bit Color Depth 11 Reserved Raster Operation Select These 8 bits are used to select which one of 256 possible raster operations is to be performed by the BLT Engine The 8 bit values and their corresponding raster operations are intended to correspond to the 256 possible raster operations specified for graphics device drivers in the Microsoft Windows environment The opcode field must indicate a monochrome source if ROP FO 15 14 Reserved Must be Zero 13 0 Destination Pitch Offset These 14 bits store the signed memory address offset value by which the destination address originally specified in the Destination Address Register is incremented or decremented as each scan line s worth of destination data is written into the frame buffer by the BLT Engine so that the destination address will point to the next memory address to which the next scan line s worth of destination data is to be written If the intended destination of a BLT operation is within on screen frame buffer memory this offset is normally set so that each subsequent scan line s worth of destination data lines up vertically with the destination data in the scan line above However if the intended destination of a BLT operation is within off screen memory this offset can be set so that each subsequent scan line s worth of destination data is stored at a location immediately after the loca
208. e 26 bits specify the scan line address of the destination data being read This is a working register NOTES This is a working register If this register is read while the BLT Engine is busy the contents are unpredictable 203 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 204 intel 13 13 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Rendering Engine Instructions This chapter describes the 3D instructions and motion compensation instruction that controls the Graphics controller GC rendering engine The GC Rendering Engine shall receive all software driver instructions through the instruction interface ring buffers GFXPRIMITIVE This instruction performs most of the rendering operations performed by the GC Triangle and Triangle lists are rendered using this instruction Triangle strips and fans reduce the number of vertices which must be delivered to the hardware for adjacent triangles and are also supported by this instruction Lines and Line Lists continue to be supported The GC also supports the rendering of axis aligned rectangles The vertices of these primitives are may be of variable length For example one call to GFXPRIMITIVE may include only the X Y values at the vertices while another call may specify all 44 bytes of attribute information at each vertex The following sections consider these primitives in detail Figure 30 Rectangle Vertices
209. e Reais 169 12 2 7 CQLOR lt BED aaa aE E E A eacnnaoeanies 170 12 2 8 PAT BLT radiri r r Avid A eect 171 12 2 9 MONO PAT BET orana an E aan ean ita dial 172 12 2 10 SRO COPY BET en sccctua we aia ain alate es 173 12 2 11 MONO _SRC_COPY_ BLT E EE EAU 174 12 2 12 MONO _SRC_COPY_IMMEDIATE_BLLT ce ccccceeeeeeeeeeeeneeeeetteeeeeeaes 175 122 132 FULE BET sche cin ile tahitian eee 177 12 2 14 FULL_MONO_SRC_BLT airian E E EAE 178 12 2 15 FULLO MONO FATTERN BGI pra na EAA a 180 12 2 16 FULL_MONO_PATTERN_MONO_SRC_BLT eee 182 12 3 BLT Engine Instruction Definitions sseeaeessseessneesinneerinnesinnnnennsadainnneaninnaainnnnnannadanaa 184 12 3 1 BROO BLT Opcode and Control cccceceeeeeeceeeeeeeeeeneeeeeeeeeetenseaeees 184 12 3 2 BRO1 Setup BLT Raster OP Control and Destination Offset 186 12 3 3 BRO2 Clip Rectangle Y1 ACdreSs cccesccceeeeseeeeeeeseeeeeeeneeeeeenaeeeeeeaes 188 12 3 4 BRO3 Clip Rectangle Y2 ACdreSs cccececcceeeeeteeeeeeeteeeeeeneeeeeeneeeeneaes 188 12 3 5 BRO4 Clip Rectangle X1 ANd X2 0 eccceeeeeeeeeeeeteeeeeeeeeeeeseeeeeeaeeeeeeaaes 189 12 3 6 BRO5 Setup Expansion Background Colot cccccccecceceeeeeeeesenaees 190 12 3 7 BRO6 Setup Expansion Foreground Color ccccccccceeeeeeeeeseneees 190 12 3 8 BRO7 Setup Color Pattern Address 0 ceceececceceeeeeeeeeecaeeeeeeeeeeeeaees 191 12 3 9 BRO8 Desti
210. e just mimic external interface 1001 CPRHLD2 Hold Address and Data for one more clock 1010 CPRWT Wait State 1011 CPRPOPA If fast load 1100 CPRPOPB If fast load 316 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 1 13 BBP_PTR Batch Buffer Parser Pointer Register debug Address Offset 020C8h Default Value 00000000h Access Read Only Size 32 bits This register contains the offset from the batch buffer start address of the DWord being parsed by the Instruction Parser 18 2 31 19 1 0 i Batch Buffer Address Pointer Offset 16 1 14 ABB_STR Active Batch Buffer Start Address Register debug Address Offset 020CCh Default Value 00000000h Access Read Only Size 32 bits This register is loaded with the start address of the Batch Buffer request The ABB_STR and ABB _END Registers will not get loaded if they are popped off of the stack This can occur if a low priority ring batch buffer is interrupted at a chain point by Interrupt Priority ring execution and then is later continued The Start and End addresses for the low priority ring chain portion that was interrupted will not be stored in the ABB_STR and ABB _END Registers This is an operational anomaly that will not be corrected 31 26 25 3 2 1 0 Reserved Batch Buffer Request Start Address Reserved Source of the Batch buffer i 1 0 Source of the Batch Buffer 00 Low Priority Ring 01 Interrrupt Ring 1X R
211. e of each 9 pixel wide character box is assigned the same attributes as the background of the character of which the given pixel is a part Every 9th pixel of a horizontal line i e the last pixel of each horizontal line of each 9 pixel wide character box is assigned the same attributes as the 8th pixel if the character of which the given pixel is a part This setting is intended to accommodate the line drawing characters of the PC s extended ASCII character set characters with an extended ASCII code in the range of BOh to DFh In IBM literature describing the VGA standard the range of extended ASCII codes that are said to include the line drawing characters is mistakenly specified as COh to DFh rather than the correct range of BOh to DFh Select Display Type 0 Attribute bytes in text modes are interpreted as they would be for a color display 1 Attribute bytes in text modes are interpreted as they would be for a monochrome display Graphics Alphanumeric Mode 0 Alphanumeric text mode 1 Graphics mode 103 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 4 4 AR11 Overscan Color Register I O and Memory Offset Address Read at 3C1h and Write at 3COh index 1 1h Default UUh U Undefined Attributes Read Write ee yS Overscan These 8 bits select the overscan border color The border color is displayed during the blanking intervals For monochrome displays this value should be set to 00h
212. ea always starts on the Oth scan line this number should be equal to the total number of scan lines within the active display area minus 1 Vertical Total Bit 9 The vertical total is a 10 bit or 12 bit value that specifies the total number of scan lines This includes the scan lines both inside and outside of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical total is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Total Register CRO6 and the most and second most significant bits are supplied by this bit and bit 0 respectively of this register In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical total is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Total Register CRO6 and the 4 most significant bits are supplied by 3 0 bits of the Extended Vertical Total Register CR30 In extended modes neither this bit nor bit O of this register are used This 10 bit or 12 bit value should be programmed equal to the total number of scan lines minus 2 Line Compare Bit 8 This bit provides the second most significant bit of a 10 bit value that specifies the scan line at which the memory address counter restarts at the value of 0 Bit 6 of the Maximum Scan Line Register CRO9 supplies the most significan
213. each row of 8 pixels of pattern data takes up 24 consecutive bytes Reserved Must be Zero These bits always return 0 when read 191 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 9 BRO8 Destination X1 and X2 Memory Offset Address 40020h Default None Attributes RO DWord accessible BROS is loaded by either PIXEL BLT SCANLINE BLT or TEXT BLT instructions The PIXEL _ BLT instruction only writes the destination X coordinate register 31 28 27 16 Reserved Must be Zero Destination X2 coordinate right 11 00 15 12 11 0 Reserved Must be Zero Destination X1 or X coordinate left 11 00 es o o o ee O 31 28 Reserved Must be Zero 27 16 Destination X2 coordinate These 12 bits specify the right most X coordinate which is written to the destination if not clipped The comparison is inclusive with a less than or equal The byte address of this coordinate is scan line address X2 bytes pixel 15 12 Reserved Must be Zero Note Some instructions affect only one pixel requiring only one coordinate other instructions affect multiple pixels and need both coordinates 11 0 Destination X1 or X coordinate left These 12 bits specify the left most X coordinate which is written to the destination This is also the working register where it changes while the BLT Engine is working The comparison is inclusive with a greater than or equal The byte address of this coordinate is scan line addr
214. ead Latch Data Register I O and Memory Offset Address 3B5h 3D5h index 22h Default 00h Attributes Read Only Memory Read Latch Data This field provides the value currently stored in 1 of the 4 memory read latches Bits 1 and 0 of the Read Map Select Register GRO4 select which of the 4 memory read latches may be read via this register 131 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 28 CR24 Test Register for Toggle State of Attribute Controller Register I O and Memory Offset Address 3B5h 3D5h index 24h Default 00h Attributes Read Only Toggle Reserved 0000000 Status Ls e O Toggle Status Last write to attribute register was to 0 index port 1 data port 6o Reserved Read as Os 9 6 29 CR30 Extended Vertical Total Register I O and Memory Offset Address 3B5h 3D5h index 30h Default 00h Attributes Read Write 7 4 3 0 Reserved 0000 Vertical Total Bits 11 8 i Reserved Read as Os This field must be Os when this register is written 3 0 Vertical Total Bits 11 8 The vertical total is a 10 bit or 12 bit value that specifies the total number of scan lines This includes the scan lines both inside and outside of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical total is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the
215. ead Write Group 0 Protection Hor Blank Horizontal Sync Delay Horizontal Sync End End Bit 5 Horizontal Blanking End Bit 5 This bit provides the most significant bit of a 6 bit value that specifies the end of the horizontal blanking period relative to its beginning Bits 4 0 of Horizontal Blanking End Register CRO3 supplies the 5 least significant bits See CR0O3 4 0 for further details This 6 bit value should be set to the least significant 6 bits of the result of adding the length of the blanking period in terms of character clocks to the value specified in the Horizontal Blanking Start Register CR02 Horizontal Sync Delay This field defines the degree to which the start and end of the horizontal sync pulse are delayed to compensate for internal pipeline delays This capability is supplied to implement VGA compatibility These field describes the delay in terms of a number character clocks Bit 6 5 Amount of Delay 00 no delay 01 delayed by 1 character clock 10 delayed by 2 character clocks 11 delayed by 3 character clocks Horizontal Sync End This field provides the 5 least significant bits of a 5 bit value that specifies the end of the horizontal sync pulse relative to its beginning A value equal to the 5 least significant bits of the horizontal character counter value at which time the horizontal retrace signal becomes inactive logical 0 Thus this 5 bit value specifies the width of the horizontal sync pulse To obtain
216. eansds EAEI A dual seeds add ceetesaceeeads tek 69 7 1 Standard VGA REGIStOMS aaa a EE AEA i icede hada ccctendsveestlageeted tag secteada AEAEE 69 7 2 SMRAM REGIStOMS isis rAr apes ARES AARAA eTEN ANATRA LADET PERAE eens 69 7 2 1 SMRAM System Management RAM Control Register Device 0 69 7 3 Display I O GPIO Clock LCD and Pixel Pipeline Registers cccsseseceeeeeees 72 7 4 2D Graphics Controller Registers SCEh 3CFh ssssssssssesrssesrrsseerrssrrrrssrrrrssrrrrsserens 73 7 5 2D CRT Controller Registers 3B4h 3D4h 3B5h 3D5N eeeceeeeeeeeeeeeeeeeeeeeneeeeeeaes 73 7 6 Initialization Values for VGA Registers 0 0 ceecceeeeeeneeeeeeneeeeeeaeeeeeeaeeeeeenaeeeeeenaeeeeeenas 74 8 Frame Buffer ACCOSS ii iis2cccei eecocek sidecceecadecei se taucecel i i i ecu erei i iaaa dia 77 9 VGA and Extended VGA Registers 000 0 cccceeceeeeceeeneee centr ee eeeaeeeeeeaeeeseaaeeeseecaeeeseeaaeeeseenaeeeeneaes 79 9 1 General Control amp Status Registers 000 0 ececeeeceeceeeeeeeeeeeeseeeeeeeseeeeeeeseeeaeeeseeaeeeeenaeees 79 9 1 1 S 100 Input Status 0 siani araia aeaaaee aa e e aa ae cade 80 9 1 2 STO1 Input Status Te iia ena aeea reas arie aaa t eaaa aroraa eaa iris lanai 81 9 1 3 FCR Feature Control srie R EAT T 82 9 1 4 MSR Miscellaneous Output c ccceceeeeeeecceeceeeeeeeseecneaeceeeeeeeseesanaeeeeees 83 9 2 SEQUENCEN REGISLSMS eeii niran aea AEE lecdaad sieges AEE AR EEE
217. east significant bits of this value are supplied by bits 7 0 of the Vertical Sync Start Register CR10 and the most and second most significant bits are supplied by bit 7 and this bit respectively of this register In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical display end is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Sync Start Register CR10 and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Sync Start Register CR32 register In extended modes neither this bit nor bit 7 of this register are used This 10 bit or 12 bit value should be programmed to be equal to the number of scan lines from the beginning of the active display area to the start of the vertical sync pulse Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical sync pulse begins Vertical Display Enable End Bit 8 The vertical display enable end is a 10 bit or 12 bit value that specifies the number of the last scan line within the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical display enable end is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Display Enable End Register CR12 and the most and sec
218. ec i FWH Firmware Hub LAN Controller ICH2 L 1 Super i i ie VO Controller Hub i riain es la AC 97 Audio Codec Graphie ore Memory 64 Bit 1 Controller Hub 100 133 MHz Oniy System 1 Memory Memory Controller AGP Contoller 1 Graphcs Controller i 3D Engine i 2D Engine 1 PCI Slots ICH 6 Req Gnt pairs 1 i PCI Bus 1 Option bosooeesel 815_SysBik I O Controller Hub The 82801AA ICH 82801BA ICH2 functions and capabilites are listed below Unless otherwise specified the function capability applies to both ICH and ICH2 e PCI Rev 2 2 compliant with support for 33 MHz PCI operations e ICH supports up to 6 Req Gnt pairs e Power Management Logic Support e Enhanced DMA Controller Interrupt Controller amp Timer Functions e Integrated IDE controller ICH supports Ultra ATA 66 ICH Ultra ATA 100 66 33 ICH2 e Integrated LAN Controller ICH2 only e USB host interface with support for two USB ports ICH Four ports ICH2 e System Management Bus SMBus compatible with most I C devices e AC 97 2 1 Compliant Link for Audio and Telephony CODECs e Low Pin Count LPC interface e Firmware Hub FWH interface support e Alert On LAN Intel 82815 Chipset GMCH Overview Figure 2 is a block diagram of the GMCH illustrating the various interfaces and integrated functions The functions and capabilities in
219. ecewise linear approximation of a curve There are 6 individual breakpoint values logarithmically spaced in the Color Intensity domain Only one set of 8 values is provided and shared for each of the Red Green and Blue intensity components These values shall be loadable via software control and are programmable For each of Red Green and Blue the appropriate Gamma breakpoint pairs are looked up and smoothly interpolated between to arrive at the final Red Green and Blue values that are output to the DAC Gamma Correction Unit Block Diagram 7 stage 1 stage 2 stage 3 stage 4 0x00 latch8to15 X 7 K MUX 4 1 Taichiow latch 6to34 Box denotes latch32to63 f ji i tatenszin6s aA logic replicated N N MUX 2 1 BRN latch6stot27 ee i latent28t091 MUX 4 1 N 2 latchhigh g latent R s V L 4 0 Prae92to25 a Cino V 2 cine amp 10 27 Z N Priority Encoder 7 latchiow gt rer ler NA Down Counter Ae gi Grote i mri eM RedGAMMA BLOCK Adder N amma Va 1 Enables signals required to Mussel Slope gt DIAGRAM Adder to calculate Slope corrected value select appropriate data for slope the slope H N gt V TN calculation ipoint V iea ne 1 0 6 0 tater A 18 7 tatoh1 92102
220. ect A and the Character Font Select B bits If the two values are the same the character select function is disabled and attribute bit 3 controls the foreground intensity 2 Bit 1 of the Memory Mode Register SR04 must be set to 1 for the character font select function of this register to be active Otherwise only character maps 0 and 4 are available 88 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 2 6 SR04 Memory Mode Register I O and Memory Offset Address 3C5h index 04h Default 00h Attributes Read Write 7 4 3 2 1 0 Reserved 0000 Chain 4 Odd Even Extended Reserved Memory 0 T Reserved Read as Os Chain 4 Mode The selections made by this bit affect both processor Read and Write accesses to the frame buffer 0 The manner in which the frame buffer memory is mapped is determined by the setting of bit 2 of this register default 1 The frame buffer memory is mapped in such a way that the function of address bits 0 and 1 are altered so that they select planes 0 through 3 2 Odd Even Mode Bit 3 of this register must be set to 0 for this bit to be effective The selections made by this bit affect only processor writes to the frame buffer 0 The frame buffer memory is mapped in such a way that the function of address bit 0 such that even addresses select planes 0 and 2 and odd addresses select planes 1 and 3 default 1 Addresses sequentially access data within a bit map and the c
221. ed into the clock synthesizer The MSR 3 2 register is used to select between DCLKO default DCLK1 and DCLK2 Writing to LCD TV Out Control 31 1 and 0 1 selects the LCD clock The MSRJ 3 2 are ignored when this condition is true The data written to these registers are calculated based on the reference frequency the desired output frequency and characteristic VCO constraints as described in the Functional Description From the calculation the M N and P values are obtained Programming Notes Three blocks of registers exist to program up to three unique frequencies for the display clock These registers are named DCLKO0 DCLK1 and DCLK2 Each of these blocks can be programmed independently of each other However only one can be used to control the DPLL at any given time The MSR register bits 3 2 is used to determine which of the DCLKO 1 2 registers groups will control the DPLL Writing to the MSR register bits 3 2 also transfers the Display Clock Divisor and Display amp LCD Clock Divisor Select Register contents to the VCO register file Example Programming Sequence DCLKO 1 Write the Display Clock 0 Divisor register with the M REG value and N REG value 2 Write the clock 0 byte of the Display amp LCD Clock Divisor Select Register with the P REG value 3 Write the MSR register bits 3 2 00 to select DCLKO NOTE This is the default value Example Programming Sequence DCLK1 1 Write the Display Clock 1 Divisor
222. ed so that the data of the next color data position becomes accessible for being written This allows the contents of all 256 color data positions of the palette to be written by specifying only the index of the Oth color data position in the Palette Write Index Register and then simply performing 768 successive writes to the Palette Data Register In addition to the standard set of 256 color data positions of the palette there is also an alternate set of 8 color data positions used to specify the colors used to draw the cursor and these are also accessed using the very same sub addressing scheme A bit in the Pixel Pipeline Configuration Register PIXCONF determines whether the standard 256 color data positions or the alternate eight color data positions are to be accessed through this sub addressing scheme DACMASK Pixel Data Mask Register I O and Memory Offset Address 3C6h Default Undefined Attributes Read Write Pixel Data Mask In indexed color mode the 8 bits of this register are logically ANDed with the 8 bits of pixel data received from the frame buffer for each pixel The result of this ANDing process becomes the actual index used to select color data positions within the palette This has the effect of limiting the choice of color data positions that may be specified by the incoming 8 bit data 0 Corresponding bit in the resulting 8 bit index being forced to 0 1 Allows the corresponding bit in the resulting index to refle
223. eeeeceeaeeeeeeeeeesecacaeeeeeeesesecsieaeeeeeeesetenaees 19 2 2 2 System Memory Interface eccceeeeeeeeeeeeeeeeeeeeeeeeeeeeenaeeeeeenaeeeeeenaeeeeeeaas 20 2 2 3 Multiplexed AGP and Display Cache Interface sseeeeeeeeeeeeseneeees 20 2 2 4 H b tS ra CO eas icons naaa a aaia aaia 21 2 2 5 Intel 82815 Chipset GMCH Integrated Graphics Support 006 21 2 2 6 System CIOCKING esaeran a aiedeeeaticeedndeacrniiceeds hacdieveleaea Hacer aliens 22 2 2 7 GMCH Power Delivery 0 ccccccesecceceesneceeeesenecdesebaeeectebnecdeesetedeesbenedenebaed 22 2 3 Three PCI Devices om GMOH wrveisccivstescccrvarsctuvseiducexsaductene yaaa aa ia aa adia aa a 22 2 3 1 Multi Mode Capability Requirements ecccceceeeeeeeeeeceeeeeeeeeennaees 23 2 3 1 1 Supported Single Monitor and Multi monitor Configurations 23 2 324222 SYSICM SAIU een 25 2 3 1 3 Software Start Up Sequence ccececeeceeceeeeeeeeeceecaeeeeeeeeeseeaees 26 2 3 1 4 Switching Device modes 00 0 0 eeeeeeeeeeee ee teeeeeeseeeeeeeteeeaeeeeeenaees 28 System Address Map tecosiesccedcat pececse nce healed ecesledvedesh presets eeu teviecesdsisdae E 29 3 1 Memory and I O Space Registers cccccceeeeeeeeeeeeeeeeeeeaeeeseeaeeeeeeaeeeseeeeeeeeneeeeeeaes 30 3 2 GC Register Memory Address Map cceeecceeceseneeeeeeeneeeeeenaeeeeesaeeeeeenaeeeeeenaeeeeeeaas 32 3 3 VGA and Extended VGA Register
224. eeeeeeeeneeeeeeneeeeesaeeeeeenaeeeensaeeeeenaaes 337 17 6 VSYNC Vertical Sync ReGister ce ecccceeeeeeeeeeeenneeeeeeeneeeesaeeeeeeaeeeeeenaeeessesaeeeeeeaes 338 17 7 LCDTV_C LCD TV Out Control Register 0 ecceeeeeeeeeeesneeeeeeeneeeeeeteeeeseneeeeeeaes 339 17 8 OVRACT Overlay Active ReQister ccceececeeesteeeeeeeneeeeeenneeeeeeneeeeeenaeeeeeeieeeeeeaas 342 17 9 _BCLRPAT Border Color Pattern Register ccccceeececceeceeeeeeeteceeeeeeeeeeteesnaeees 342 Local Memory Interface nire r a a 343 18 1 DRT DRAM Row Ty saassssessssseessrnesssnneernnnestnnnasnannnsttenanntunnatenndntannnttaneetannaanannennan 343 18 2 DRAMCL DRAM Control LOW ceeccceeeeeteeeeeenneeeeeeeeeeeeeaeeeeeeaeeeseeieeeeseneeeeeeaes 344 18 3 DRAMCH DRAM Control High 0 cccceeeeseeeeeeeeeeeeeeeeeeeeesneeeseenaeeeeeenaeeeeseneeeseeaes 345 VO Control REGISters vx saxisestee inte atten e ee deat Ma et al ed deed eee de 347 19 1 HVSYNC HSYNC VSYNC Control Register ccc cccceeeeecneeeeeenneeeeeeteeeeeeneeeeeeaes 347 19 2 GPIO REJSO S a rar E cvs T eaiatea c paaaee aah ARS 348 19 2 1 GPlOA General Purpose I O Control Register A a e 348 19 2 2 GPlOB General Purpose I O Control Register B a se 350 Display And Cursor ReQiSters ccccccccesecscecessadecceseeccecusencccensaeceqceeeadadeneneadeceneneseecnecaacentes 353 20 1 DISP_SL Display Scan Line Count 00 eee eeeeeee tree eaeeeeeeaeeeee
225. eeeesneeeeeenneeeseeneeeeeenaeeeeeeneeeeeeaas 106 VGA Color Palette Registers 2c cccceceeceeecceneeededsneeeeedeneeeeessneeeeesneeeeetaneeeeedeneeeeetanes 106 9 5 1 DACMASK Pixel Data Mask ReGister ccccceeeseneeeeeeneeeeeeeneeeeeeaaes 107 9 5 2 DACSTATE DAC State Register 0 cceeecceeeeeneeeeeeeteeeeeeneeeeeeneeeeeeaas 108 9 5 3 DACRX Palette Read Index Register ccceeccceeeesteeeeeeeteeeeetteeeeeenaes 108 9 5 4 DACW X Palette Write Index Register ccceccceceeeeeeeeeeeeeeeeetneeeeeeaas 108 9 5 5 DACDATA Palette Data Register ccceeesneeeeeesteeeeeeneeeeeenaeeeeeeaas 109 GR GonitrollersRegisten aii GIAE R O RE T 109 9 6 1 CRX CRT Controller Index Register seseseeeeeeeeereserresrerrererrssrernssne 110 9 6 2 CROO Horizontal Total Register eccceeeeeeeeeseeeeeeeeeneeeeesteeeeetieeeeeaa 111 9 6 3 CRO1 Horizontal Display Enable End Register cecceeeeeeeeeeeeeee 111 9 6 4 CRO2 Horizontal Blanking Start Register ccceeceeeseeeeeeeeteeeeeee 111 9 6 5 CRO3 Horizontal Blanking End Register cccceeeseeeeeeeeeteeeeenneeeereee 112 9 6 6 CR04 Horizontal Sync Start Register cecceeeeeeeseeeeeeetteeeeeenteeeereae 112 9 6 7 CRO5 Horizontal Sync End ReQister ceceeeeeeeeeeeeeeeeeneeeeenneeeeeeee 113 9 6 8 CRO6 Vertical Total Register cc eceeeeeeeeeeeeeeeeeeeeesieeeeeseeeeeeenaeeeerena 114 9 6 9
226. eeneeeeeenaeeeeeeaeeeeeenaeeeeneaas 248 13 27 GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION_RULE 0 eee 249 13 28 GFXRENDERSTATE_DEST_BUFFER_VARIABLEG 0 ccceeeeseeeeeeeeeeeeeenteeeeeenaes 251 13 29 Programming Hints RUIeCS c ee eeeeeceenneeeceeneeeeeeeaeeeeeeaaeeeeeeaeeeeesaeeeeesnaeeeseenaeeeeeeaas 253 Clock Control ReGiSters ossimori eiir a a aa ari a 257 14 1 Programming Notes oerssisiicieriniiid ieia ii ei i di 257 14 2 DCLK_0D Display Clock 0 Divisor Register sesesseseeeeesrreserresrerrsstrrnsrtrnssennssrenn 258 14 3 DCLK_1D Display Clock 1 Divisor Register 0 cceeeceeeeeeneeeeeenneeeeeeneeeeenaeeeeeeaaes 259 14 4 DCLK_2D Display Clock 2 Divisor Register cc cecceceeeeeneeeeenneeeeeeneeeeetateeeeeaaes 260 14 5 LCD CLKD LCD Clock Divisor Register 0 cccceeeeceeeeeeneeeeeenneeeeeenaeeeeeenaeeeeneaas 261 14 6 DCLK_0DS Display amp LCD Clock Divisor Select Register 0 cceeeeeeeesteeeenees 262 14 7 PWR _CLKC Power Management and Miscellaneous Clock Control 0cee 264 Overlay REGIStCIS isc icc integrons cde a scan toes oa ce dined cute snd seat enna toevG set adapta fdas papaceed TT 265 15 1 OVOADD Overlay 0 Register Update Address Register ccscceeeestreeeetteeeeenaes 267 15 2 DOVOSTA Display Overlay 0 Status Register 00 0 eeccceeeesteeeeeenneeeeeeteeeeetteeeeeaaes 268 15 3 Gamma Commection cceccccceceeeaccceesuncedeeeanedeec
227. eeseeneeeeeeaas 205 13 1 GFXPRIMITIVE aieiai eiiiai iE NE EANA ENE EEA VEEE A AANA TEN ANE 205 13 1 1 Axis Aligned Rectangles ccccccceccceecneeeceeeneeeeeeeieeeeeeneeesseaeeeseeneeeeeeaes 205 13 1 2 Primitive Winding Order nierien e rE EE E ra 205 13 1 3 Position MaS Krr enna abe Det ares hae ade tanh a Ne cs ca ahead 206 13 1 4 Biasi aaa a dee tea e hace dea csi alte a ed terete ate 206 13 1 5 Primitive Rendering Instruction Format c ccescccceeeeseeeeeeeeeeeeesteeeeeeaaes 206 13 1 6 Variable Length Vertex Formats for Rendering Instructions 00 207 13 1 7 GRXAVERTEX miai stoke east cht eavahen A E ceva dee neato deevaced ase 208 13 2 GFXRENDERSTATE_VERTEX_FORMAT 0 ecccccceececeeeeeeeeeeeeeeeeeeeeeeeeeseeaeeeeeneaees 209 13 3 GFXBLOCK ies seine needed eee ee ead ea ded needa eed ied dl 210 13 3 1 Motion Vector Format aini einai aiir aariaa riai aaaea 213 13 4 Non pipelined State Variables cccccccceeeeecececeeeeeeeeeeaeeeeeeeeseceacaeeeeeeesetesseneeeeees 213 13 5 GFXRENDERSTATE_MAP_TEXELS renererien E A RR a 214 13 6 GFXRENDERSTATE_MAP_COORD_SETS c cc ceceeceeeeeeeeeeeeeeeeeseeeeeeseeeeeeseenaees 215 13 7 GFXRENDERSTATE MAP INFO rosiner ar a Oa T TE 217 13 8 GFXRENDERSTATE MAP FILTER purina oiae A a A e ETa 222 Intel 815 Chipset Graphics Controller PRM Rev 1 0 14 15 13 9 GFXRENDERSTATE_MAP_LOD_LIMITS 0 ce eeeceeeeeenneeeeeenieeeeeeneeeeee
228. efresh overrun Page Table Error 1 Page table error 0 Cleared by a processor write of a one to the error identity bit registers to determine source of the error Instruction Parser Error The Instruction Parser encounters an error while parsing an instruction 1 Error 3 Display or Overlay Under run 1 Display or overlay under run error 0 Cleared by a processor write of a one to the Error identity bit See display and overlay status 0 Cleared by a processor write of a one to the Error identity bit Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 2 6 3 ElR Error Identity Register Address Offset 020B0h Default Value 00h Access Read Write Clear Size 16 bits Reserved MM LM Display or Reserved Reserved Instruction Refresh Overlay Parser timer error under run Error E Error Identity Bits See Error Identity Mask and Status Register Bit Definitions table 1 Error occurred 16 2 6 4 EMR Error Mask Register Address Offset 020B4h Default Value FFh Access Read Write Size 16 bits Reserved MM LM Display or Reserved Reserved Instruction Refresh Overlay Parser timer error under run Error E Error Mask Bits See Error Identity Mask and Status Register Bit Definitions table 0 Not masked 1 Masked 329 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 2 6 5 _ESR Error Status Register Address Offset 020B8h Default Value FFh Access Read Onl
229. egisters can be read through Overlay Source Color Key Debug read path See OVOADD register Overlay Configuration description Overlay Command Overlay Flip Instruction NA e This instruction invokes the Overlay register update 266 Intel 815 Chipset Graphics Controller PRM Rev 1 0 OVO0OADD Overlay 0 Register Update Address Register Memory Address Offset 30000h 30003h Default Value 00000000 Access R W Size 32 bits This register provides a physical memory address that will be used on the next register update for Overlay 0 This register is double buffered to allow it to be updated during overlay display Updating Register Values A write to this register sets an internal bit readable through the status register that causes all the register values that were written to the memory buffer area to be loaded into the corresponding on chip registers and become active on the next VBLANK event Overlay 0 Flip is asserted after all registers are updated from memory Debug Read Path For Overlay 0 Registers The read path is the active register The staging register is not readable Memory Address Offset 30100h 301xxh xx register offset These registers will provide a debug read path for testing overlay internal register functionality The address offsets correspond to the memory offsets used to load the registers 31 29 28 0 Register Update Address Physical memory address that will be used on the next register
230. egisters to transfer to the VCO register file simul taneously This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence 31 26 25 16 15 10 9 0 ee 20 veo em owner Whore cai rib aeresoapu ease ate Ton Intel 815 Chipset Graphics Controller PRM Rev 1 0 DCLK_1D Display Clock 1 Divisor Register Address Offset 06004h 06007h Default Value 00100053h Attribute R W Size 32 bits The Display Clock 1 Divisor register and the Display amp LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer Data is written to the Display Clock 1 Divisor register followed by a write to the Clock 1 byte of the Display amp LCD Clock Divisor Select Register The completion of the write to the Display amp LCD Clock Divisor Select Register causes data from both registers to transfer to the VCO register file simul taneously This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence 31 26 25 16 15 10 9 0 25 16 VCO 1 N Divisor N Divisor value calculated for the desired output frequency default 10h so VCO 1 M Divisor M Divisor value calculated for the desired output frequency default 53h 259 Intel 815 Chipset Graphics Controller PRM Rev 1 0 14 4 260 DCLK_2D Display Clock 2 Divisor Register Address Offset 06008h 0600Bh Default Value
231. eing written into the destination buffer independent of any alpha test Color Index Value Mask 0 Do not update 1 Update ChromaKey Low Value Mask 0 Do not update 1 Update 2 ChromaKey High Value Mask 0 Do not update 1 Update 23 0 ChromaKey Low Value This is a 24 bit value in RGB 888 format Only the upper 5 6 5 bits of the RGB 888 color are compared against the texel colors 31 24 Color Index Value This is an 8 bit color index The default value is 0 23 0 ChromakKey High Value This is a 24 bit value in RGB 888 format Only the upper 5 6 5 bits of the RGB 888 color are compared against the texel colors 2 t 2 Table 15 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_SRC_DST_BLEND_MONO The state variable Specular_RGB_Enable is set in the graphics command GFXRENDERSTATE SRC _DST_ BLEND MONO It is also dependent on the value of the state variable Specular_Enable which is set in the graphics command GFXRENDERSTATE BOOLEAN ENA 1 Selecting Specular Mode Specular RGB Enable Bits 15 14 of GFXRENDERSTATE_SRC_DST_BLEND_MONO 0 1 Specular Enable 0 No Specular No Specular Bits 9 8 of 1 Monochrome Specular Full Color RGB GFXRENDERSTATE_BOOLEAN_ENA_1 Specular The GC 3D section of the graphics device supports alpha blend modes defined in the following state variables except where noted as Not Implemented 1 RENDERSTATE SRC DST BLEND 2
232. elect a color from that palette This example assumes that the color specified at index 00h in the palette is black and therefore bits 7 0 of this register should be set to 00h to select black as the foreground color The BLT engine ignores bits 23 8 of this register because the selected color depth is 8 bits per pixel Even though the color expansion being performed on the source data normally requires that both the foreground and background colors be specified the value used to specify the background color is not important in this example Per pixel write masking is being performed with the monochrome source data as the pixel mask which means that none of the pixels in the source data that will be converted to the background color will ever be written to the destination Since these pixels will never be seen the value programmed into the Pattern Source Expansion Background Color Register to specify a background color is not important The Destination Width and Height Registers are not used The Y1 Y2 X1 and X2 are used be program with values that describe to the BLT engine the 8x8 pixel size of the destination location The Destination Y1 and Y2 address registers must be programmed with the starting and ending scan line address of the destination data This address is specified as an offset from the start of the frame buffer of the scan line at the destination that will be written to first The destination X1 and X2 registers must be programmed w
233. emory Bus Frequencies 05 22 Memory Mapped Registers c ccccceeeeeeeeeeeeeseeeeeeeeeeeeeeeseeeaeeeseneeeeeseenaneeeenaaees 32 W O and Memory Register Map ecseseeeeeesneeeeeeeeeeeeeeeeeeeaaeeeeeeaaeeeeseaaeeeeaaaeeeesaaees 37 2D Sequence Registers 3C4h 3CSN eee eeeceeeeseeeeeeeeteeeeeenteeeeeseeeeeenaeeeeeenaes 38 2D Graphics Controller Registers SCEN 3CFN 0 eecceeeeeeeeeeeeseeeeeetteeeeeeaes 38 2D Attribute Controller Registers CON 3C1h 0 eeeeeeeeeeeeeeeneeeeeeeenteeeeeeaae 39 2D CRT Controller Registers 3B4h 3D4h 3B5h 3D5h eneee 39 CRT Display Sync Polarities 0 eee eeeeeeeeeeeeeeeenaeeeeeeaeeeeeeaeeeeeeaeeeeeenaeeeeneaas 84 VGA Address Range ici iss seceicscecetacsceecesssceeei tesccecvesceeeusiceeet seactcuesteceevbiseeeeestace 99 Memory Address Counter Address Bits 15 0 c ecceeeeeeeeeeeeeteeeeeeeeeeees 129 Frame Buffer Address DeCOdel cccccecceeeeeeeenteeeeeenaeeeeeeaaeeeeeeaeeeeeenaeeeeeeaas 130 Ring Buffer Characteristics cccccceeeceeeeeeeeeeeeeeeeeeeenaeeeseeaeeeeeeaeeeseeneeeeseaas 145 Graphics Controller Instructions cccccceeeeeeeceeceeeeeeeseceacaeeeeeeeeeeenaneeeeeees 151 Summary of Source Surface Formats with Filter Output Channel Mappings 217 Selecting Specular MOdG c0 cesstececserecneeueeceeteseceeeceshtqaeceentaeeeeneteseeventeseteseie 235 Overlay Register Instruction Categories eccceeee
234. endering rectangle primitives the height or width of the drawing rectangle must be greater than 1 e g Xmax Xmin gt 1 and Ymax Ymin gt 1 The drawing rectangle coordinates need to be clipped to the screen boundary by software before send down to hardware 243 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Client 03h Rendering Engine EZE 24 3DStateMWNP Non pipelined 1Dh 2316 16 Opcode 80h 150 0 15 0 DWORD_LENGTH 13 Drawing Scissor Rectangle clipping Enable for validation purpose only This bit should be set to enable in normal mode 0 Enable 1 Disable Clipped DR Ymin Y coordinate of upper left corner of drawing rectangle after being clipped to screen boundary Only the lower 10 bits in U10 format is used by hardware This value is a pixel aligned unsigned integer and reference to the upper left corner of the 2D buffer defined in the dest buffer info packet Clipped DR Xmin X coordinate of upper left corner rectangle after being clipped to screen boundary Only the lower 11 bits in U11 format is used by hardware This value is a pixel aligned unsigned integer and reference to the upper left corner of the 2D buffer defined in the dest buffer info packet Clipped DR Ymax Y coordinate of lower right corner rectangle after being clipped to screen boundary Only the lower 10 bits in U10 format is used by hardware This value is a pixel aligned unsigned integer and reference to t
235. ented in Intel 810 chipset 179 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 15 FULL_MONO_PATTERN_BLT 180 The full BLT is the most comprehensive BLT instruction It provides the ability to specify all 3 operands destination source and pattern The pattern operand is monochrome and the source operand is the same bit width as the destination operand The monochrome pattern is loaded from the instruction stream The pattern vertical alignment specifies which scan line of the pattern is used first The destination address specifies the horizontal alignment The only operands accessed from memory are the source and destination operands The monochrome pattern transparency mode indicates whether to use the pattern background color or deassert the write enables when the bit in the source is 0 When the source bit is 1 then the pattern foreground color is used in the ROP operation The ROP value chosen should involve the Mono pattern data in the ROP operation Both the source and destination pitches can be either sign The pattern direction follows the destination operand The Intel 815 chipset hardware has a restriction that the BLT color source and destination operands must not co exist on the same 32 Byte cacheline To work around this issue e For BLTs that have sharing of a cacheline for a given scanline the driver must treat this as an overlapping BLT case e For linear memory the surfaces allocated
236. er Save reserved bits 6 5 and 2 Clear all other bits OR in the saved value of the Pixel Pipeline Configuration 0 Register Write the result back into the Pixel Pipeline Configuration 0 Register Pixel Pipeline Configuration 2 Field MM 0x7000b Read the current value of the Pixel Pipeline Configuration 2 Register Save reserved bits 7 4 and 1 0 Clear all other bits OR in the saved value of the Pixel Pipeline Configuration 2 Register Write the result back into the Pixel Pipeline Configuration 2 Register Pixel Pipeline Configuration 1 Field MM 0x7000a Read the current value of the Pixel Pipeline Configuration 1 Register Clear the Display Color Mode bit bits 3 0 OR in the saved value of the Pixel Pipeline Configuration 1 Register Write the result back into the Pixel Pipeline Configuration 1 Register Hardware Status Mask Register MM 0x2098 Read the current value of the Hardware Status Mask Register Clear everything but the reserved bits 14 13 OR in the saved value of the Hardware Status Mask Register Write the result back into the Hardware Status Mask Register Interrupt Enable Register MM 0x20A0 Read the current value of the Interrupt Enable Register Clear everything but the reserved bits 14 13 OR in the saved value of the Interrupt Enable Register Write the result back into the Interrupt Enable Register Interrupt Mask Register MM 0x20
237. er They are referred to as the Interrupt and Low Priority RBs and are basically identical except for differences in arbitration rules and priority Figure 27 Ring Buffers Graphics Memory Wrap Around Low Priority Ring Interrupt Ring Starting Addres Head Pointer DMA Pointer Tail Pointer Starting Addres Head Pointer DMA Pointer Tail Pointer RingBuf vsd 10 4 4 1 Ring Buffer Registers A Ring Buffer is defined by a set of two Ring Buffer registers Low and High Priority Before an RB can be used for instruction transport software needs to program these registers The fields contained within these registers are as follows e Ring Buffer Valid This bit controls whether the RB is included in the instruction arbitration process Software must program all other RB parameters before enabling an RB An RB can be disabled and later re enabled Enabling or disabling an RB does not of itself change any other RB register fields e Start Address This field points to a contiguous 4 KB aligned linear e g not tiled memory address region which provides the actual instruction buffer area e Buffer Length The size of the buffer in 4KB increments up to 2MB e Head Offset This is the DWord offset from Start Address of the next instruction that the IP will execute The IP will update this field as instructions are retired Note that if instructions are pending execution the IP will likely have fetched inst
238. er End Address Must be a QW aligned physical memory address a Reserved MBZ Helpful Hint Use GFXCMDPARSER NOP_IDENTIFICATION to pad buffer to a QW length intel 12 12 1 12 2 Note Intel 815 Chipset Graphics Controller PRM Rev 1 0 2D Instructions This chapter contains the 2D graphics controller instructions For each instruction the format specifies the functionality of a field When an instruction does not require a field it is ignored All registers can only be written through instructions No program I O writing of the BLT registers is allowed BLTs To and From Cacheable Memory The blitter can be used to transfer data from cacheable memory to graphics memory and vice versa using the blitter command packets The source or destination operands in these packets can be steered towards cacheable memory Patterns may be used with the source The driver is required to flush the drawing pipelines before and after each copy command targeting cacheable memory In addition the driver is required to turn arbitration off if this command is used from the low priority ring buffer An example sequence from the low priority ring buffer is ARB_OFF FLUSH SCB FLUSH SCB FLUSH ARB_ON Where all Source copy blits SCBs use cacheable memory Either the source or destination surface can be in cacheable memory Both Source and Dest surfaces in cacheable memory as part of the same blit operation is not allowed
239. er restarts at the value of 0 Bit 6 of the Maximum Scan Line Register CRO9 supplies the most significant bit and bit 4 of the Overflow Register CRO7 supplies the second most significant bit Normally this 10 bit value is set to specify a scan line after the last scan line of the active display area When this 10 bit value is set to specify a scan line within the active display area it causes that scan line and all subsequent scan lines in the active display area to display video data starting at the very first byte of the frame buffer The result is what appears to be a screen split into a top and bottom part with the image in the top part being repeated in the bottom part This register is only used in split screening modes and this is not a problem because split screening is not actually used for extended modes As a result there is no benefit to extending the existing overflow bits for higher resolutions When used in cooperation with the Start Address High Register CROC and the Start Address Low Register CROD it is possible to create a split display as described earlier but with the top and bottom parts displaying different data The top part will display whatever data exists in the frame buffer starting at the address specified in the two aforementioned start address registers while the bottom part will display whatever data exists in the frame buffer starting at the first byte of the frame buffer 9 6 27 _CR22 Memory R
240. erted 1 Vertical Blank Status asserted Overlay Registers Updated Status 0 Overlay Registers have been updated during Vertical Blank Status not asserted 1 Overlay Registers have been updated during Vertical Blank Status asserted Intel 815 Chipset Graphics Controller PRM Rev 1 0 20 4 Hardware Cursor The hardware cursor registers are memory mapped and accessible through 32 bit accesses 20 4 1 CURCNTR Cursor Control Register Memory Offset Address 70080h Default 0000h Attributes Read Write This register is double buffered The load register is transferred into the active register on the asserting edge of Vertical Sync Cursor Mode Reserved Select ee Reserved Cursor Coordinate System Origin Select 0 Selects the outermost upper left hand corner of the screen border as the origin for the coordinate system used to position cursor default 1 Selects the upper left hand corner of the active display area as the origin for the coordinate system used to position cursor Reserved 010 Reserved 011 Reserved 100 64x64 2bpp 3 color and transparency mode 101 64x64 2bpp AND XOR 2 plane mode 110 64x64 2bpp 4 color mode 111 Reserved 2 0 Cursor Mode Select These three bits select the mode for the cursor as follows 000 Cursor is disabled This is the default after reset 001 32x32 2bpp AND XOR 2 plane mode 361 Intel 815 Chipset Graphics Controller PRM Rev 1 0 20 4 2
241. ertices ecreis 205 State Variable Relationships ccccccceeeeceeceeeeeeceecaeeeeeeeeeeeceaeaeeeeeeeseteenaees 214 State Variable Relationships cccccceceeceeceeceeeeeeseeceeeeeeeeeseseenaeeeeeeeeeeees 215 State Variable Relationships cccccccceeecceceeeeeeeeeaeceeeeeeeseceaaeeeeeeeeeteenaees 217 Mip map Surface Organization Example cccceeeeeeeeceeceeeeeeeeeentnaeeeeess 218 State Variable Relationships ccccccceeeeceeceeeeeeceecaeceeeeeeeseceeaeeeeeeeseteenaees 222 State Variable Relationships ccccccceesecceceeeeeeeeececeeeeeeeseeeaaeeeeeeeeeeeenaees 224 State Variable Relationships ccccccceceecceceeeeeeeeeaeceeeeeeeseneueaeeeeeeesetennaees 225 State Variable Relationships ccccccceececeeceeeeeeeeeceeceeeeeeeseceaaeeeeeeeeeeeenaees 226 State Variable Relationships ccccccceeecceeceeeeeeceecaeceeeeeeesecenaeeeeeeeeeeeenaees 227 State Variable Relationships ccccececcecceceeeeeeeeneeeceeeeeeeeeenaeaeeeeeeeeeeeeaees 230 Gamma Correction Unit Block Diagram ccccceeeeeeeeeeneeeeeeeceeeeseeaeeeseeaees 271 11 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Tables 12 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Supported System Bus and System M
242. erved Paging RAS to CAS RAS RAS Mode CAS Latency Riming Precharge Control Override Timing Cee Reserved Paging Mode Control PMC 0 Page Open Mode In this mode the GMCH memory controller tends to leave pages open 1 Page Close Mode In this mode The GMCH memory controller tends to leave pages closed RAS to CAS Override RCO In units of local memory clock periods i e row activate command to read write command Bit RAS to CAS delay trcp 0 determined by CL bit default CAS Latency CL In units of local memory clock periods CL RAS to CAS delay trcp 2 3 default RAS Riming RT This bit controls RAS active to precharge and refresh to RAS active delay in local memory clocks Bit RAS act To precharge tras Refresh to RAS act trc 0 5 8 1 7 10 default RAS Precharge Timing RPT This bit controls RAS precharge in local memory clocks Bit RAS Precharge trp 0 2 1 3 default 344 Intel 815 Chipset Graphics Controller PRM Rev 1 0 DRAMCH DRAM Control High Address offset 03002h Default value 08h Access Read write Size 8 bit 4 3 7 5 2 0 DRAM Refresh Rate Special Mode Select DRAM Refresh Rate DRR DRAM refresh is controlled using this field Disabling refresh results in the eventual loss of DRAM data although refresh can be briefly disabled without data loss The field must be set to normal refresh as soon as possible once DRAM testing is comp
243. es where bit 0 of the I O Control Register CR80 is set to 0 the vertical blanking start is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Blanking Start Register CR15 and the most and second most significant bits are supplied by bit 5 of the Maximum Scan Line Register CR09 and bit 3 of the Overflow Register CRO7 respectively In standard VGA modes these four bits are not used In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical blanking start is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Blanking Start Register CR15 and the 4 most significant bits are supplied by these 4 bits of this register This 10 bit or 12 bit value should be programmed to be equal to the number of scan line from the beginning of the active display area to the beginning of the blanking period Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical blanking period begins 135 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 33 CR35 Extended Horizontal Total Time Register I O and Memory Offset Address 3B5h 3D5h index 35h Default 00h Attributes Read Write 7 1 0 Reserved 0000000 Ext Horiz Total it Description 7 1 Reserved When this register is writ
244. es worth of color data is needed depends upon the color depth to which the BLT Engine has been set For a color depth of 24bpp 16bpp and 8bpp bits 23 0 15 0 and 7 0 respectively are used 12 3 18 BR17 Pattern Expansion Foreground Color Memory Offset Address 40044h Default None Attributes RO DWord accessible 31 24 23 0 Reserved Must be Zero Pattern Expansion Foreground Color Bits 23 0 E 31 24 Reserved Must be Zero 23 0 Pattern Expansion Foreground Color Bits 23 0 These bits provide the one two three or four bytes worth of color data that select the foreground color to be used in the color expansion of monochrome pattern data during BLT operations Whether one two or three or bytes worth of color data is needed depends upon the color depth to which the BLT Engine has been set For a color depth of 24bpp 16bpp and 8bpp bits 23 0 15 0 and 7 0 respectively are used 200 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 19 BR18 Source Expansion Background and Destination Color Memory Offset Address 40048h Default None Attributes RO DWord accessible 31 24 23 0 Reserved Must be Zero Source Expansion Background Color Bits 23 0 ao OOS 31 24 Reserved Must be Zero Debug implementation specific 31 25 bmnewcliplw 6 0 Source Expansion Background Color Bits 23 0 These bits provide the one two or three bytes worth of color data that select the b
245. escribed above will toggle the flip flop back to writing to the index ARX Attribute Controller Index Register I O and Memory Offset Address 3COh Default O0O0UU UUUUb U Undefined Attributes Read Write 5 7 6 4 0 Reserved 00 Video Attribute Controller Register Index Enable Reserved Read as Os Video Enable Note that In the VGA standard this is called the Palette Address Source bit 0 Disable Attribute controller color registers AR 00 0F can be accessed by the processor 1 Enable Attribute controller color registers AR 00 0F are inaccessible by the processor Attribute Controller Register Index These five bits are used to select any one of the attribute controller registers AR 00 14 to be accessed Note AR12 is referred to in the VGA standard as the Color Plane Enable Register The words plane color plane display memory plane and memory map have been all been used in IBM literature on the VGA standard to describe the four separate regions in the frame buffer where the pixel color or attribute information is split up and stored in standard VGA planar modes This use of multiple terms for the same subject was deemed to be confusing therefore AR12 is called the Memory Plane Enable Register Attribute Controller Register Index 101 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 4 2 AR 00 0F Palette Registers 0 F I O and Memory Offset
246. eserved 317 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 1 15 ABB_END Active Batch Buffer End Address Register debug Address Offset 020D0h Default Value 00000000h Access Read Only Size 32 bits This register is loaded with the end address of the Batch Buffer request The ABB_STR and ABB_END Registers will not get loaded if they are popped off of the stack This can occur if a low priority ring batch buffer is interrupted at a chain point by Interrupt Priority ring execution and then is later continued The Start and End addresses for the low priority ring chain portion that was interrupted will not be stored in the ABB_STR and ABB_END Registers This is an operational anomaly that will not be corrected 31 26 25 3 2 1 0 Reserved Batch Buffer Request End Address Reserved Source of the Batch buffer 25 3 Batch Buffer Request End Address 2 Reserved 0 Source of the Batch Buffer 00 Low Priority Ring 01 Interrrupt Ring 1X Reserved 16 1 16 DMA_FADD DMA Engine Fetch Address debug Address Offset 020D4h Default Value 00000000h Access Read Only Size 32 bits This register contains the offset from the start address of the instruction being fetched by the DMA engine 31 26 25 3 2 1 0 Current Address of the DMA Pointer User of DMA Eng Ce 1 0 User of the DMA Engine 00 Low Priority Ring 01 Interrupt Ring 10 Batch Buffer from Low Priority Ring 11 Batch Buffer from Inte
247. eserved Read as Os 8 9 Dot Clocks This bit determines whether a character clock is 8 or 9 dot clocks long 0 9 dot clocks 9 horizontal pixels per character in text modes with a horizontal resolution of 720 pixels default 1 8 dot clocks 8 horizontal pixels per character in text modes with a horizontal resolution of 640 pixels Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 2 4 SRO2 Plane Map Mask I O and Memory Offset Address 3C5h Index 02h Default 00h Attributes Read Write 7 4 3 0 Memory Planes Processor Write Access Enable Reserved Read as Os used with multiple meanings in the VGA standard and was therefore considered too confusing hence the reason for calling it the Plane Mask Register 3 0 Memory Planes 3 0 Processor Write Access Enable In both the Odd Even Mode and the Chain 4 Mode these bits still control access to the corresponding color plane 0 Disable 1 Enable Note This register is referred to in the VGA standard as the Map Mask Register However the word map is 87 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 2 5 SRO3 Character Font I O and Memory Offset Address 3C5h index 03h Default 00h Attributes Read Write Reserved 00 Char Map Char Map Character Map A Select Character Map B Select A Select B Select bits 2 and 1 bits 2 and 1 bit 0 bit 0 Reserved Read as Os Character Map Select Bits for Character
248. ess X1 bytes pixel 192 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 10 BRO9 Destination Address and Destination Y1 Address Memory Offset Address 40024h Default None Attributes RO DWord accessible 31 26 25 0 Reserved Must Destination and Destination Y1 and Y Address Bits 25 0 be Zero ee 31 26 Reserved Must be Zero Destination and Destination Y1 and Y Address Bits These 26 bits specify the starting pixel address of the destination data This register is also the working destination address register and changes as the BLT Engine performs the accesses Used as the scan line address Destination Y Address amp Destination Y1 Address for BLT instructions PIXEL_BLT SCANLINE_BLT and TEXT_BLT In this case the address points to the first pixel in a scan line and is compared with the ClipRect Y1 amp Y2 address registers to determine whether the scan line should be written or not The Destination Y1 address is the top scan line to be written for text This register is always the last register written for a BLT drawing instruction Writing BRO9 starts the BLT engine execution Note Some instructions affect only one scan line requiring only one coordinate other instructions affect multiple scan lines and need both coordinates NOTES This is a working register If BROQ is read while the BLT engine is busy the contents are unpredictable 12 3 11 BR10 Destination Y2 Address Me
249. ess 3COh or memory address 3COh is used both as the read and write for the index register and as the write address for the data port I O address 3C 1h or memory address 3C 1h is the read address for the data port To write to one of the attribute controller registers the index of the desired register must be written to T O address 3COh or memory address 3COh and then the data is written to the very same I O memory address A flip flop alternates with each write to I O address 3COh or memory address 3COh to change its function from writing the index to writing the actual data and back again This flip flop may be deliberately set so that I O address 3C0h or memory address 3COh is set to write to the index which provides a way to set it to a known state by performing a read operation from Input Status Register STO1 at I O address 3BAh or memory address 3BAh or 3DAh or memory address 3DAh depending on whether the graphics system has been set to emulate an MDA or a CGA as per MSR 0 To read from one of the attribute controller registers the index of the desired register must be written to T O address 3COh or memory address 3COh and then the data is read from I O address 3C 1h or memory address 3C lh A read operation from I O address 3C1h or memory address 3C1h does not reset the flip flop to writing to the index Only a write to 3COh or memory address 3COh or a read from 3BAh or 3DAh or memory address 3BAh or 3DAh as d
250. ests service 14 13 CSSTDW State Machine Is responsible for generation of the Store DWord snoop cycle to the PI unit on behalf of the command parser and the interrupt report meachnism 000 STDWIDLE Waiting for next Store DWord Cycle 001 STDWINTR INT Report Store DWord Cycle in progress 010 STDWCP Command Parser Initiated Store DWord Cycle 100 STDWAUTO Auto report of head pointer 011 STDWINTD Request accepted wait for HT to take data 101 STDWCPD Request accepted wait for HT to take data 110 STDWAUTD Request accepted wait for HT to take data 315 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description CSDMA State Machine Is responsible for the control of the DMA FIFO It get requests from the arbitration state machine It manages the FIFO so that requests are only made when there is space in the FIFO 00 DMAIDLE Reset State No DMA Active 01 DMAREQ Request State Generate request 10 DMAWT Wait State Stay in this state till space becomes available 11 DMARWT Wait for Acknowledge State Stay in this state till acknowledged Hold request CSSW State Machine Main Arbiter between Low Priority Ring Interrupt Priority Ring and Batch Buffer 00 SWIDLE Reset State 01 SWBLOCK Assert Parser Block 10 SWSTOP Once Parser has gone to idle request the dma engine to stop 11 SWPOP Once the DMA has gone to idle pop the FIFO till the CSDMA indicates DMA done CSARB State Mac
251. eters for Screen Resolution Refresh Rate 800x600_72Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 388 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dot Clock Value 49 149 5 MHz Dot Clock Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 389 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 800x600_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp
252. f the 12 bit value It is required of software to write both CR41 3 0 and CR13 7 0 to the desired 12 bit offset value for correct hardware operation Where an 8 bit value is desired for example in standard VGA mode software must write 0000 to CR41 3 0 and the desired 8 bit value to CR13 7 0 Note that unlike the operation of the other CRTC extension registers CR80 0 CRT Controller Interpretation Enable bit has no effect on CR41 and CR13 9 6 37 CR42 Extended Start Address High Register I O and Memory Offset Address 3B5h 3D5h index 42h Default 00h Attributes Read Write E Start Address High Bits 31 24 This register provides bits 31 24 of a 32 bit buffer address that the data to be shown in the active display area begins default is 0 In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the start address is specified with a 16 bit value The eight bits of the Start Address High Register CROC provide the eight most significant bits of this value while the eight bits of the CROD register provide the eight least significant bits In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the start address is specified with a 32 bit value Bits 31 24 of this value are provided by this register Bits 23 18 of this value are provided by bits 5 0 of the Extended Start Address Register CR40 Bits 17 10 of this value are provided by the Start Address H
253. f we are not in AGP mode 00 Internal Graphics Device Disabled No memory Stolen 01 Internal Graphics Device Enabled No memory Stolen 10 Internal Graphics Device Enabled 512K of memory Stolen for frame buffer 11 Internal Graphics Device Enabled 1M of memory Stolen for frame buffer Note When the Internal Graphics Device is Disabled 00 the Graphics Device and all of its memory and I O functions are disabled and the clocks to this logic are turned off memory accesses to the VGA range AQ000 BFFFF will be forwarded on to the hub interface and the Graphics Local Memory space is NOT stolen from main memory Any change to the SMRAM register will not affect AGP mode or cause the controller to go into AGP mode When this field is non 0 the Internal Graphics Device and all of its memory and I O functions are enabled all non SMM memory accesses to the VGA range will be handled internally and the selected amount of Graphics Local Memory space 0 512K or 1M is stolen from the main memory Graphics Memory is stolen AFTER TSEG Memory is stolen Once D_LCK is set these bits becomes read only GMCH does not support VGA on local memory Software must not use the 01 mode for VGA Upper SMM Select USMM This field is used to enable disable the various SMM memory ranges above 1 MB TSEG is a block of memory Stolen from Main Memory at TOM Size TOM that is only accessable by the proces
254. fer is logically ANDed with the data in the memory read latch before it is actually stored in the frame buffer 10 Data being written to the frame buffer is logically ORed with the data in the memory read latch before it is actually stored in the frame buffer 11 Data being written to the frame buffer is logically XORed with the data in the memory read latch before it is actually stored in the frame buffer Rotate Count These bits specify the number of bits to the right to rotate any data that is meant to be written to the frame buffer just before it is actually stored in the frame buffer at the intended address location 92 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 3 6 GR04 Read Plane Select Register I O and Memory Offset Address 3CFh Index 04h Default OUh U Undefined Attributes Read Write 7 2 1 0 Reserved 000000 Read Plane Select Reserved Read as Os Read Plane Select These two bits select the memory plane from which the processor reads data in Read Mode 0 In Odd Even Mode bit 0 of this register is ignored In Chain 4 Mode both bits 1 and 0 of this register are ignored The four memory planes are selected as follows 00 Plane 0 01 Plane 1 10 Plane 2 11 Plane 3 These two bits also select which of the four memory read latches may be read via the Memory read Latch Data Register CR22 The choice of memory read latch corresponds to the choice of plane specified in the
255. ff The display and hardware cursor will be disabled by setting the Screen Off bit However the Overlay stream will continue to be displayed so it must be halted separately if you want to blank the screen 0 Normal Operation default 1 Disables video output blanks the screen and turns off the picture generating logic This allows the full memory bandwidth to be available for processor accesses Synchronization pulses to the display however are maintained Setting this bit to 1 can be used as a way to more rapidly update the frame buffer 0 Load video shift registers every 1 or 2 character clocks depending on bit 2 of this register default 1 Load shift registers every 4th character clock Dot Clock Divide Setting this bit to 1 divides the dot clock by two and stretches all timing periods This bit is used in standard VGA 40 column text modes to stretch timings to create horizontal resolutions of either 320 or 360 pixels as opposed to 640 or 720 pixels normally used in standard VGA 80 column text modes 0 Sequencer master clock output on the PCLK pin used for 640 720 pixel modes Pixel clock is left unaltered default 1 Pixel clock divided by 2 output on the PCLK pin used for 320 360 pixel modes Shift Load Bit 4 of this register must be 0 for this bit to be effective 0 Load video data shift registers every character clock default 1 Load video data shift registers every other character clock R
256. for a page table Error Type 4 i e bits 2 0 100 indicating a translated address that points to PAM SMM and other restricted spaces in main memory This field is normally undefined and only registers a valid entry upon an occurrence of a page table error type 4 Occurrence of a page table error type 4 is recorded in MMIO register 20B8h Error Status Register bit 4 5 3 Error Identification Identifies the TLB that caused the error After an error Render Mapping and Blitter engines will stop execution However overlay display and host operations will not stop Each Source records the first error and ignores subsequent errors See the Page Table Error Mask Register for more debug help 000 Buffer BF Unit 001 Overlay 010 Display 011 Host 100 Render 101 Blitter 110 Mapping 111 Command Stream Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Error Type 000 Invalid Table 001 Invalid Page table entry 010 Incorrect target for Display surface Request to Im if the surface started in mm or vice versa Overlay surface Request to Im 011 Invalid Miss during Display Overlay accesses 100 Illegal translation data translation is valid and address points to PAM SMM over top and other restricted spaces in main memory 101 Access to local memory when not present 110 Surface tiled in Y when not allowed Render Display Overlay 111 Reserved Notes T
257. for the remainder of the BLT is source and destination accesses Both the source and destination pitches can be either sign The pattern direction follows the destination operand The Intel 815 chipset hardware has a restriction that the BLT color source and destination operands must not co exist on the same 32 Byte cacheline To work around this issue e For BLTs that have sharing of a cacheline for a given scanline the driver must treat this as an overlapping BLT case e For linear memory the surfaces allocated must be 32B cacheline aligned ee e X Direction 1 written from right to left decrementing backwards 0 incrementing 29 28 Reserved Must be Zero Reserved Must be Zero Must Be One 1 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved Destination Pitch signed 13 00 are implemented in Intel 810 chipset 2 BR14 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 177 Intel 815 Chipset Graphics Controller PRM Rev 1 0 DWord Bit Description 3 BROY 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset 31 14 Reserved Must be Zero 4 BR11 13 00 Source Pitch quadword aligned and signed 13 00 are implemented in Intel 810 chipset 5 BR12 31 00 Source Address 25 00 are
258. fset 30140h RO debug path Default Value 00h Access see address offset above Size 32 bits Vertical Scale Factor Reserved Horizontal X Scale Factor Y RGB Vertical Y RGB Scale Down Factor Scale Y RGB Integer Integer Bie Description Vertical Scale Factor Y RGB This is a fractional positive number that represents the scale factor to be used in vertical scaling For packed formats it applies to all color components and for planar YUV formats it is use for the Y component only Always Bit 31 20 1 gt scale gt 1 64 the maximum vertical up zoom is 64X 1 Scale for up scale fractional portion of the scale factor for down scaling 19 17 Reserved Horizontal Scale Factor Y RGB Integer This field is used only for horizontal down scale In the case of planar formats it specifies the integer portion of the scale factor for Y data Only Horizontal down scaling of 2 or less to 1 is supported Horizontal Scale Factor Y RGB This is a fractional positive number that represents the scale factor to be used in horizontal scaling Always 1 gt scale20 Reserved Vertical Down Scale Integer This field is used only for vertical down scale In the case of planar formats it specifies the integer portion of the scale factor for Y data 285 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 6 2 286 UVSCALE UV Scale Factor Register Memory Address Offset 44h R W On chip Reg Mem Addr Offset 30144h RO debug pat
259. g path Default Value 00h Access see address offset above Size 32 bits 31 27 26 16 15 11 10 0 Display Vertical top line Display Horizontal left pixel 26 16 Display Vertical top line Display vertical top in lines O begin at display first line 10 0 Display Horizontal left pixel Determines where on the display screen coordinates the overlay display will begin Display Horizontal Left in pixels O begin at display left edge DWINSZ Destination Window Size Register Memory Address Offset 30h R W On chip Reg Mem Addr Offset 30130h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 27 26 16 15 11 10 0 a 26 16 Vertical Size Destination Vertical Size in lines never specifies scan lines off the active display Horizontal Size Destination Horizontal Size in pixels never specifies pixels off the active display 281 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 5 15 4 5 1 282 intel Overlay Source Size Registers These registers provide information to the overlay engine on what data needs to be fetched from memory If the overlay destination window is smaller than the result of the scaled up source it will be clipped on the right and bottom of the overlay window The source data is clipped within one QWord Source width must not specify an additional QWord or more of data that is not required to satisfy the destination If the scaled source is sm
260. g the blue color and using the result for the red green and blue color components for specular and diffuse colors 237 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 17 238 GFXRENDERSTATE_Z BIAS ALPHA FUNC_REF Z Bias This is a signed value that is added to the source Z value prior to the Z compare function This 2 s complement fixed point value has 7 integer bits and 0 fractional bits and is sign extended before being added to the destination Z value Valid data values range from 128 to 127 S7 The default value is 0 The Z value written back to Z buffer included this Z bias value Alpha Function Valid values are 00h Reserved 01h Never never pass 02h Less pass if the source Alpha is less than the Alpha reference 03h Equal pass if the source Alpha is equal to the source Alpha 04h Lequal pass if the source Alpha is less than or equal to the source Alpha 05h Greater pass if the source Alpha is greater than the source Alpha 06h Notequal pass if the source Alpha is note equal to the source Alpha 07h Gequal pass if the source Alpha is greater than or equal to the source Alpha 08h Always always pass Alpha Reference value for color calculation equation s This is bits 7 3 of an alpha reference value This value specifies a reference alpha value which pixels are tested against when alpha testing is enabled The default value is 0 unsigned int The Z Bias state vari
261. gnoring the raster operation to Destination Y Address Destination X coordinate bytes per pixel Source expansion color registers are always in the SETUP_BLT Note All graphics controller BRO3 fields monochrome clipping parameters are computed by the hardware while performing clipping Powe De ee T 1 BRO8 31 16 Destination X2 Coordinate Ending Right 27 16 12 bits are implemented in the Intel 815 chipset 15 00 Destination X1 Coordinate Starting Left X2 X1 1 width in pixels 11 00 12 bits are implemented in the Intel 815 chipset 3 BR10 31 00 Destination Y2 Address address of the first pixel on the last scan line 25 00 are implemented in Intel 810 chipset 4 BR11 31 16 Reserved Must be Zero 15 00 Number of monochrome source Quadwords 1 1 to 64k Quadwords 64 to 4M bits 2 BROY 31 00 Destination Y1 Address address of the first pixel on the first scan line 25 00 are implemented in Intel 810 chipset 5 BR12 31 00 Source Address address of the first byte of the first pixel on the first scan line 25 00 are implemented in Intel 810 chipset 168 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 6 TEXT_Immediate_BLT This instruction allows the Driver to send data through the instruction stream which eliminates the read latency of reading a source from memory This allows graphics primitives such as Text to execute much faster If an operand is
262. h Access Read 32 bit Write only Size 8x 32 bits each The Memory Hub MH performs address translation between linear space and tiled space The intent of tiling is to locate graphics data that are close in X and Y surface axes in one memory page while still locating some amount of line oriented data sequentially in memory for display efficiency All 3D rendering is done such that the QWords of any one span are all located in the same memory page which improves rendering performance Tiled memory is supported for rendering surfaces located in graphics memory A tiled memory surface is a surface which has a secondary pitch and height which are subsets of the surface s total pitch and height The graphics controller maintains the constants required by the memory interface to perform the address translations for up to eight tiled regions each with a different pitch and size The memory interface needs the surface pitch and tile height to perform the address translation It uses the fence base address size constants and the surface address to determine if the rendering surface is tiled and swizzle the bits as required by tiling Since fence ranges are at least 512 KB and aligned 7 address bits are required to specify the lower bound In addition the fence lower bound must be fence size aligned A Tile represents 2 KB of memory Tile height is fixed at 16 Based on this the surface pitch has to be programmed in tiles Eight Fence Table Regis
263. h Default Value 00h Access see address offset above Size 32 bits 31 20 19 16 Vertical Scale Factor UV Reserved 15 14 3 2 Reserved Horizontal Scale Factor UV UV Down Scale Integer E Vertical Scale Factor UV Used only in YUV planar modes to set the scale factor for the UV data This is different in formats where the UV data is vertically sub sampled Bit 31 20 1 gt scale gt 1 64 the maximum vertical up zoom is 64X 14 3 Horizontal Scale Factor UV Used only in YUV modes to set the scale factor for the UV data This is different in formats where the UV data is sub sampled UV Down Scale Integer This field is used only for vertical down scale It specifies the integer portion of the scale factor for UV data intel 15 4 7 15 4 7 1 15 4 7 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Overlay Color Correction Registers Used for YUV sources only Adjustments are made before the RGB conversion OVOCLRC0 Overlay 0 Color Correction 0 Register Memory Address Offset 48h R W On chip Reg Mem Addr Offset 30148h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 17 16 8 N i 16 8 Contrast 7 3F 3 6 format Bypassing Contrast even for RGB is accomplished by programming this field to 1 0 7 0 Brightness Range 127 a value of zero disables this adjustment affect This value gets added to the Y value after contrast multiply and jus
264. h 03h 00h 02h 00h 3 A3h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h 4Dh OBh OCh 00h 00h 00h 00h 83h 85h 5Dh 28h 1Fh 63h BAh A3h FFh 00h 01h 03h 00h 02h 00h 3 67h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h 4Fh ODh OEh 00h 00h 00h 00h 9Ch 8Eh 8Fh 28h 1Fh 96h B9h A3h FFh 00h 00h 03h 00h 02h 00h A6h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h 4Dh OBh OCh 00h 00h 00h 00h 83h 85h 5Dh 28h ODh 63h BAh A3h FFh 00h 00h 03h 00h 03h 00h 7 66h 5Fh 4Fh 50h 82h 55h 81h BFh 1Fh 00h 4Fh ODh OEh 00h 00h 00h 00h 9Ch 8Eh 8Fh 28h OFh 96h B9h A3h FFh 00h 00h 03h 00h 02h 00h 132 col Opt 1 6Bh AOh 83h 85h 82h 8Ah 81h BFh 1Fh 00h 4Fh ODh OEh 00h 00h 00h 00h 9Ch 8Eh 8Fh 42h 1Fh 96h B9h A3h FFh 00h 01h 03h 00h 02h 00h 132 col Opt 2 6Bh 9Eh 83h 84h 81h 8Ah 9Eh BFh 1Fh 00h 4Fh OEh OFh 00h 00h 00h 00h 9Ch 8Eh 8Fh 42h 1Fh 96h B9h A3h FFh 00h 01h 03h 00h 02h 00h Mode gt Register GR01 GR02 GR03 GR04 GR05 GRO6 GRO7 GRO8 AROO ARO1 ARO2 ARO3 AR04 AROS ARO6 ARO7 ARO8 ARO9 AROA AROB AROC AROD AROE AROF AR10 AR11 AR12 AR13 AR14 0 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 06h 07h 10h 11h 12h 13h 14h 15h 16h 17h 08h 00h OFh 00h 00h o 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39
265. h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 08h 00h OFh 00h 00h 0 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh OCh 00h OFh 00h 08h 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 06h 07h 10h 11h 12h 13h 14h 15h 16h 17h 08h 00h OFh 00h 00h 4 00h 00h 00h 00h 10h OEh 00h FFh 00h O1h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 08h 00h OFh 00h 00h 1 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh OCh 00h OFh 00h 08h Intel 815 Chipset Graphics Controller PRM Rev 1 0 00h 00h 00h 00h 10h OEh 00h FFh 00h O1h 02h 03h 04h 05h O6h 07h 10h 11h 12h 13h 14h 15h 16h 17h 08h 00h OFh 00h 00h 2 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 08h 00h OFh 00h 00h 2 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh OCh 00h OFh 00h 08h 00h 00h 00h 00h 10h OEh 00h FFh 00h Oth 02h 03h 04h 05h 06h 07h 10h 11h 12h 13h 14h 15h 16h 17h 08h 00h OFh 00h 00h 3 00h 00h 00h 00h 10h OEh 00h FFh 00h 01h 02h 03h 04h 05h 14h 07h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 08h 00h OFh 00h 00h 3 00h 00h 00h 00h
266. h extended modes or performance enhancements will prevent the Intel 815 chipset family products from booting The registers in this document are normally programmed by the video BIOS These registers also may be documented in other sections of this document Standard VGA Registers All VGA registers are in standard locations and initialized by means of standard procedures This section will document all nonstandard registers that are needed for initialization of the Intel 815 chipset SMRAM Registers The SMRAM register is in the chipset s PCI configuration space Device 0 Since this register is not documented anywhere else the entire register description is provided here SMRAM System Management RAM Control Register Device 0 Address Offset 70h Default Value 00h Access Read Write Read Only Size 8 bits The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated and how much if any memory is Stolen from the System to support both SMRAM and Graphics Local Memory needs Graphics Mode Select Upper SMM Select Lower SMM Select SMM Space Locked 69 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Graphics Mode Select GMS This field is used to enable disable the Internal Graphics device and select the amount of Main Memory that is Stolen to support the Internal Graphics device in VGA non linear mode only These 2 bits only have meaning i
267. h registers to transfer to the VCO register file simultane ously This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence 31 26 25 16 15 10 9 0 ee 25 16 VCO LCD N Divisor N Divisor value calculated for the desired output frequency default 03h 90 VCO LCD M Divisor M Divisor value calculated for the desired output frequency default 13h 261 Intel 815 Chipset Graphics Controller PRM Rev 1 0 14 6 DCLK_0DS Display amp LCD Clock Divisor Select Register Address Offset 06010h 06013h Default Value 40404040h Attributes R W Size 32 bits Display clock 1 i 0 to 2 becomes effective after programming the appropriate byte i i 0 to 2 in this register LCD clock becomes effective after programming byte 3 in this register Reserved Post Divisor Select LCD Clk Reserved VCO Loop Reserved Div LCD clk 23 22 20 19 18 17 16 Reserved Post Divisor Select Clk 2 Reserved VCO Loop Reserved Div clk 2 15 14 12 11 10 9 8 Reserved Post Divisor Select Clk 1 Reserved VCO Loop Reserved Div clk 1 6 4 3 2 1 0 Reserved Post Divisor Select Clk 0 Reserved VCO Loop Reserved DPLL Div clk 0 DSYNCON ql i Post Divisor Select LCD Clock 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 default 101 Divide by 32 11x Reserved 26 VCO Loop Divide LCD Clock 0 Divided by 4 default 1 Divided by 16
268. h the graphics system has been set Monochrome patterns require 8 bytes and is supplied through the instruction Color patterns of 8 16 and 24 bits per pixel color depth must start on 64 byte 128 byte and 256 byte boundaries respectively Note In the case of 24 bits per pixel each scan line s worth each row of 8 pixels of pattern data takes up 32 consecutive bytes not 24 It is formatted so that there is a contiguous block of 8 sets of 3 bytes each corresponding to 1 of the 8 pixels followed by a contiguous block of the 8 extra bytes When the BLT Engine reads 24 bit per pixel pattern data it will read only the first 24 bytes of each scan line s worth of data picking up the 8 sets of 3 bytes for each of the 8 pixels and entirely ignoring the remaining 8 bytes Reserved Must be Zero These bits always return 0 when read 199 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 17 BR16 Pattern Expansion Background amp Solid Pattern Color Memory Offset Address 40040h Default None Attributes RO DWord accessible 31 24 23 0 Reserved MBZ Pattern Expansion Background Color Bits 23 0 31 24 Reserved Must be Zero 23 0 Pattern Expansion Background Color Bits 23 0 These bits provide the one two three or four bytes worth of color data that select the background color to be used in the color expansion of monochrome pattern data during BLT operations Whether one two three or four byt
269. havior as follows e In Unprotected Mode the parser generates an error if it parses a store DWORD immediate instruction It is assumed that an unprotected batch buffer has not been verified by the driver and can have invalid store DWORD immediate instructions that write over protected areas in cacheable memory e In protected state the parser will allow all instructions to be parsed It is assumed that a batch buffer identified as protected has been verified by the driver to ensure that store DWORD immediate instructions do not corrupt the operating system The Intel 815 chipset hardware implementation has batch buffer size limit set at 512 KB 8B The instruction needs a Buffer Start Address and a Buffer End Address that both must be QW aligned physical memory addresses Using this start and end address the batch buffer size definition is Batch Buffer Size Buffer End Address Buffer Start Address 8 Bytes This means the batch buffer does include valid commands up to and including the end address location Start_Address Valid Command Start_Address 8 Valid Command oe gt Total Size End Start 8B End_ Address 8 Valid Command must be limited to 512KB 8B End_ Address Valid Command C Client 000 Instruction Parser Instruction Target 30h Reserved Dword Length 01h Buffer Start Address Must be a QW aligned physical memory address Reserved po Protection id 1 Un Protected 0 Protected 2 Buff
270. he Memory Interface unit uses this address in conjunction with the Memory Fence Table Registers to determine the virtual Tiled address of the dest buffer This surface address linear must be at least 4 KB aligned in addition it must be 4 times pitch aligned aligned Reserved MBZ 1 0 Pitch This is the pitch of the Back Buffer This is used by the TLB in computing the absolute address of the color requests 00 512 bytes 01 1KB 10 2KB 11 4KB 157 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 11 2 8 GFXCMDPARSER _FRONT_BUFFER_INFO The GFXCMDPARSER FRONT BUFFER _INFO instruction is used to initialize the base address of the scene to be display by the Display Engine DE a k a flip There are two choices for this instruction In the first choice the Instruction Parser sends the base address to the DE where its update is synchronized to the display syncs sync flip In the second choice the DE s update is on the following hsync async flip In the case of a double buffer swap operation requiring a flip between the display and render surface base addresses in addition to the FRONT _BUFFER_INFO packet a DEST _BUFFER_INFO instruction will also need to be specified Note that no special hardware is provided to synchronize these instructions together A bit of the Interrupt Status Register represents the status of the flip instruction This flag is set when the Instruction Parser processes the GFXCMDP
271. he IP employs a set of rules to arbitrate among these instruction stream sources This section describes these rules and discusses the reasoning behind them Arbitration Rationale The Low Priority Ring Buffer LPRB is considered the primary mechanism by which drivers will pass instructions to the GC However the insertion of instruction sequences into the LPRB must be a synchronous operation i e software must guarantee mutually exclusive access to the LPRB among contending sources drivers This ensures that one driver does not corrupt another driver s partially completed instruction stream There are two general sources of requirements for asynchronous instruction generation and execution interrupt handlers and contending drivers An interrupt handler may be invoked when a driver is in the process of inserting instructions into the LPRB To permit the interrupt handler to generate an instruction stream the Interrupt Ring Buffer IRB is provided The IRB instruction stream is considered higher priority than the LPRB stream this priority is manifested in how the IRB is treated in the arbitration rules Note however that software retains some control over this arbitration process The GFXCMDPARSER_ ARB ON_OFF instruction can be used from the LP instruction stream RB or batch buffer to temporarily disable the IRB from arbitration This can be used to define uninterruptible critical sections in the LP stream e g where some GC state need
272. he VGA standard this bit was used to switch between 3 and 5 frame buffer refresh cycles during the time required to draw each horizontal line Vertical Interrupt Enable Note that the graphics controller does not provide an interrupt signal which would be connected to an input of the system s interrupt controller Bit 7 of Input Status Register 0 STOO indicates the status of the vertical retrace interrupt and can be polled by software to determine if a vertical retrace interrupt has taken place Bit 4 of this register can be used to clear a pending vertical retrace interrupt 0 Enable the generation of an interrupt at the beginning of each vertical retrace period 1 Disable the generation of an interrupt at the beginning of each vertical retrace period Vertical Interrupt Clear Note that the graphics controller does not provide an interrupt signal which would be connected to an input of the system s interrupt controller Bit 7 of Input Status Register 0 STOO indicates the status of the vertical retrace interrupt and can be polled by software to determine if a vertical retrace interrupt has taken place Bit 5 of this register can be used to enable or disable the generation of vertical retrace interrupts 0 Setting this bit to 0 clears a pending vertical retrace interrupt This bit must be set back to 1 to enable the generation of another vertical retrace interrupt Vertical Sync End This 4 bit field provides a 4 bit value that specif
273. he addressed byte of any or all of the 4 memory planes simultaneously 2 This bit mask is applicable to any data written into the frame buffer by the processor including data that is also subject to rotation logical functions AND OR XOR and Set Reset To perform a proper read modify write cycle into frame buffer each byte must first be read from the frame buffer by the processor and this will cause it to be stored in the memory read latches The Bit Mask Register must be set and the new data then must be written into the frame buffer by the processor 97 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 3 11 GR10 Address Mapping I O and Memory Offset Address 3CFh Index 10h Default 00h Attributes R W Paging to Packed Linear Page LM Mode Mapping Mapping Enable Description Reserved Page to Local Memory Enable Used Only if GR10 0 1 Paging enabled and GR10 1 1 or GR10 2 1 Either packed mode or Linear mode is enabled and GR10 3 0 VGA Buffer selected 0 Page to VGA Buffer 1 Page to Physical Local Memory VGA Buffer Memory Map Select 0 VGA Buffer default 1 Memory Map Packed Mode Enable 0 Address and data translation are bused register settings default 1 Forced extended pack pixel address translation In page mapping mode register GROG selects the video memory address Linear Mapping PCI 0 Disable default 1 Enable Page Mapping Enable Thi
274. he first byte of valid source data In cases where the host processor provides the source data it does so by writing the source data to ring buffer directly after the BLT command that requires the data or uses an IMMEDIATE INDIRECT BLT command packet which has a size and pointer to the operand in Main memory graphics memory There is also an address space used for debug where the processor can write the source data It is a 64 KB memory space on the host bus There is no actual memory allocated to this memory space so any data that is written to this location cannot be read back This memory space is simply a range of memory addresses that the BLT engine s address decoder watches for the occurrence of any memory writes The BLT engine loads all data written to any memory address within this memory space or through the command packet in the order in which it is written regardless of the specific memory address to which it is written and uses that data as the source data in the current BLT operation The block of bytes sent by the host processor to either this data port or through the command packets must be quadword aligned although the source data contained within the block of bytes does not need to be aligned As mentioned earlier the least significant three bits of the Source Address Register are used to specify the number of bytes that must be skipped in the first quadword of color data to reach the first byte of valid source data To accomm
275. he odd numbered memory planes planes 1 and 3 and the even numbered memory planes planes 0 and 2 0 AO functions normally 1 AO is switched with a high order address bit in terms of how it is used in address decoding The result is that AO is used to determine which memory plane is being accessed AO 0 for planes 0 and 2 and AO 1 for planes 1 and 3 Graphics Text Mode 0 Text mode 1 Graphics mode 96 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 3 9 GR07 Color Don t Care Register I O and Memory Offset Address 3CFh Index 07h Default OUh U Undefined Attributes Read Write Reserved 0000 Reserved Read as Os Ignore Color Plane 3 0 Note that these bits have effect only when bit 3 of the Graphics Mode Register GR05 is set to 1 to select read mode 1 0 The corresponding bit in the Color Compare Register GR02 is not used in color comparisons 1 The corresponding bit in the Color Compare Register GR02 is used in color comparisons 9 3 10 GR08 Bit Mask Register I O and Memory Offset Address 3CFh Index 08h Default Undefined Attributes Read Write E Bit Mask 0 The corresponding bit in each of the 4 memory planes is written to with the corresponding bit in the memory read latches 1 Manipulation of the corresponding bit in each of the 4 memory planes via other mechanisms is enabled Notes 1 This bit mask applies to any writes to t
276. he upper left corner of the 2D buffer defined in the dest buffer info packet Clipped DR Xmax X coordinate of lower right corner rectangle after being clipped to screen boundary Only the lower 11 bits in U11 format is used by hardware This value is a pixel aligned unsigned integer and reference to the upper left corner of the 2D buffer defined in the dest buffer info packet DR origin Y Origin of the Y coordinate of the drawing rectangle before being clipped to screen boundary The value is S10 in 2 s complement format This value is a pixel aligned and reference to the upper left corner of the 2D buffer defined in the dest buffer packet DR origin X Origin of the X coordinate of the drawing rectangle before being clipped to screen boundary The value is S11 in 2 s complement format This value is a pixel aligned and reference to the upper left corner of the 2D buffer defined in the dest buffer packet 244 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_SCISSOR_ENABLE Only inclusive mode scissoring is supported Pixel Aligned Span Aligned Reference Inclusive Clipping Rectangle Point Defined by the Back Buffer Info Packet Pixel Aligned Drawing Window Drawn Region ej e Scissor Rectangle ID This number must be 0 for this stepping since only one clipping rectangle is allowed More clipping rectangles can be allowed in future expansion 15 2 Reserved 00n 00h
277. hese 8 bits are used to select any one of the CRT controller registers to be accessed via the data port at I O location 3B5h or 3D5h depending upon whether the graphics system is configured for MDA or CGA emulation The data port memory address offsets are 3B5h 3D5h 9 6 3 9 6 4 Intel 815 Chipset Graphics Controller PRM Rev 1 0 CRO00 Horizontal Total Register I O and Memory Offset Address 3B5h 3D5h index 00h Default 00h Attributes Read Write Group 0 Protection This register is used to specify the total length of each scan line This encompasses both the part of the scan line that is within the active display area and the part that is outside of it This register is extended to cover 16x12 resolution using CR35 and CR39 7 0 Horizontal Total This field should be programmed with a value equal to the total number of character clocks within the entire length of a scan line minus 5 CR01 Horizontal Display Enable End Register I O and Memory Offset Address 3B5h 3D5h index 01h Default Undefined Attributes Read Write Group 0 Protection This register is used to specify the end of the part of the scan line that is within the active display area relative to its beginning In other words this is the horizontal width of the active display area Horizontal Display Enable End This field should be programmed with a value equal to the number of character clocks that occur within the part of a scan line that is
278. hich calls OS services for setting host memory type Establish policy for limiting the amount of non local video memory The OS determines the maximum amount of system memory that can be allocated as non local video memory The graphics driver can make a guess on what is likely to be provided by the OS based on the same information that the OS uses to make its decision The graphics driver can query the OS to check the type of memory surface allocation i e system vs local vs non local video memory 27 Intel 815 Chipset Graphics Controller PRM Rev 1 0 2 3 1 4 28 intel 3 After the conclusion of the graphics driver startup code the internal graphics functions will be ready for run time activity and commands can be written into the ring buffer Switching Device modes Under normal conditions the GMCH Device Mode will be switched at most once from AGP to Internal Graphics mode via APCONT 0 when no external AGP graphics device is present This is handled automatically by the system BIOS during system initialization There is no case where the GMCH will be switched from Internal Graphics mode to AGP mode Intel 815 Chipset Graphics Controller PRM Rev 1 0 System Address Map This chapter provides address maps of the graphics controller GC I O and memory mapped registers Individual register bit field descriptions are provided in the following chapters Note that PCI configuration register descriptions are not covere
279. hics Controller PRM Rev 1 0 16 1 3 304 intel PGTBL_ER Page Table Error Register Address Offset 02024h identical functionality in Device 0 at EC EFh Default Value 0000 0000h Access Read Only Size 32 bits This register stores information pertaining to page table error interrupts Invalid physical address implies regions in main memory that have restricted accessibility such as PAM SMM space etc The Display engine speculatively fetches data and may cross 16 GTT mapped pages that are not intended for use To prevent errors from occurring and hanging the display engine the 16 GTT pages adjacent to the contiguous display region must be left unused but marked valid and mapped Once a page table error has been detected the GMCH hardware will operate in an error state but continues to complete host cycles to memory in order to facilitate system debug as opposed to hanging the system In the page table error detected state further read will complete normally whereas write will complete with all byte enables masked The page table error condition within the GMCH can be recovered by software writing a 1 to bit 15 of the Interrupt Identity Register IIR Note that this action is in addition to software clearing the page table error identification bit in the Error Identity Register EIR 4 31 12 11 6 5 3 2 0 Physical Address 31 12 Error Type ae Physical Address This field provides the page table access address
280. hics display or the secondary display active region It allows pixel accurate positioning The Overlay Alpha Blend Window must be programmed to be either equal or within the Overlay Window 15 4 12 1 AWINPOS Alpha Blend Window Position Register Memory Address Offset 70h R W On chip Reg Mem Addr Offset 30170h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 27 26 16 15 11 10 0 Reserved Alpha Blend Vertical top Reserved Alpha Blend Horizontal line left pixel E 26 16 Alpha Blend Vertical top line Determines where on the display screen coordinates the overlay display are alpha blended Alpha Blend Vertical Top in lines 0 begin at display first line 10 0 Alpha Blend Horizontal left pixel Determines where on the display screen coordinates the overlay display are alpha blended Alpha Blend Horizontal Left in pixels 0 begin at display left edge 298 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 12 2 AWINSZ Alpha Blend Window Size Register 15 5 Memory Address Offset 74h R W On chip Reg Mem Addr Offset 30174h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 27 26 16 15 11 10 0 Reserved Alpha Blend Vertical Reserved Alpha Blend Horizontal Size Size Description Reserved Alpha Blend Vertial Size Determines where on the display screen coordinates the overlay display are alpha blended Alpha Blend Ver
281. hine Blocks the Command Parser from parsing further and cleans up the FIFO 0000 ARBIDLE Reset State Waiting for next arbitration request 0001 ARBLOW Low Priority Ring Active 0010 ARBL2ISW Switch from Low Priority Ring to High Priority Ring Initiated by the parser by masking the valid bit 0011 ARBLBAT In Batch Buffer initiated from Low Priority Ring 0100 ARBL2BSW Switch from Low Priority Ring to Batch Buffer Initiated by the parser 0101 ARBINTR Interrupt Active Ring Active 0110 ARBI2ZBSW Switch from Interrupt Ring to Batch Buffer Initiated by the parser 0111 ARBIBAT In Batch Buffer initiated from Interrupt Priority Ring 1000 ARBIZDSW Switch from Interrupt Ring to Idle if a wait for event packet was received parser masks the valid bit CSCPR State Machine Command Parser 0000 CPRIDLE Reset State Parser is in Idle looking at the next header 0001 CPRSW When waiting for engines to go idle either for non pipelined SVs or for engine switch 0010 CPRHDR Clock to get rid of header when not loaded externally 0011 CPRCMD Command State that have data address to load 0100 CPREVT For some Parser events like WT4EVT packet brekapoint interrupt 0101 CPRFLSH If all engines are done request for Local Cache to flush itself 0110 CPRSTDA Store DWord Address report head command also 0111 CPRSTDW Store DWord Data 1000 CPRHLD1 Hold address data for external interface For internal interfac
282. his field takes into account the Overlay pipeline delays for lining up X 0 to the first active pixel When LCD TV is enabled then the overlay active start is controlled by the LCD TV Out Timing Generator and all the bits are used When LCD TV is disabled then the overlay active start is controlled by the VGA Timing Generator and uses bits 15 3 for character clock 17 9 BCLRPAT Border Color Pattern Register Address Offset 60020h Default Value 00000000h Access Read Write Size 32 bits A border is sent if Border Enable is on Also same color will be sent during pseudo border period in LCD no scalar mode In VGA Centering mode the VGA border color will be sent instead of the Flat Panel Border Color HIRes Centering mode will still use the Flat Panel Border color 31 25 24 16 15 8 7 0 342 18 18 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Local Memory Interface DRT DRAM Row Type Address offset 03000h Default value 00h ACCESS Read write Size 8 bit This 8 bit register identifies whether or not the local memory is populated 7 1 0 Reserved DRAM Populated i DRAM Populated DP This bit indicates whether or not the local memory is populated 0 No local memory 1 4 MB local memory 343 Intel 815 Chipset Graphics Controller PRM Rev 1 0 18 2 DRAMCL DRAM Control Low Address offset 03001h Default value 17h Access Read write Size 8 bit Res
283. hoice of which map is accessed is made according to the value of the Plane Mask Register SRO2 Extended Memory Enable This bit must be set to 1 to enable the selection and use of character maps in plane 2 via the Character Map Select Register SRO3 0 Disable processor accesses to more than the first 64KB of VGA standard memory default 1 Enable processor accesses to the rest of the 256KB total VGA memory beyond the first 64KB Reserved Read as Os 89 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 2 7 SRO7 Horizontal Character Counter Reset I O and Memory Offset Address 3C5h index 07h Default 00h Attributes Read Write Writing this register with any data causes the horizontal character counter to be held in reset the character counter output will remain 0 until a write occurs to any other sequencer register location with SRX set to an index of 0 through 6 The vertical line counter is clocked by a signal derived from the horizontal display enable which does not occur if the horizontal counter is held in reset Therefore if a write occurs to this register during the vertical retrace interval both the horizontal and vertical counters will be set to 0 A write to any other sequencer register location with SRX set to an index of 0 through 6 may then be used to start both counters with reasonable synchronization to an external event via software control This is a standard VGA register that was not
284. i e SCLK Note that the Clock Generator must guarantee a clean Host Clock HCLK during this entire transition c Program Intel 815 chipset System Memory Frequency Select bit GMCHCFG 2 to 1 to enable internal System Memory clocking to operate at 133 MHz d Wait at least 0 5 us for the Intel 815 chipset to re synchronize internal clocks before accessing anything other than Intel 815 chipset Configuration registers or the Hub interface ICH interface System BIOS then detects and configures all of system memory and tests enough memory to support a stack and an interrupt area System BIOS should shadow itself and complete system initialization If and only if the Intel 815 chipset is in Internal Graphics Mode APCONT 0 1 pass control to the system BIOS internal graphics mode initialization routines described below System BIOS programs the Intel 815 chipset base addresses using PCI configuration cycles as described in the PCI Local Bus Specification PCI enumeration takes place at this point 14 15 16 17 Intel 815 Chipset Graphics Controller PRM Rev 1 0 During PCI enumeration the system BIOS will identify and initialize the primary display device The selection of the primary display device is typically OEM dependent An OEM may use a BIOS setup question to allow the system user to select the primary display device Intel recommends the system BIOS to give preference to the higher performance
285. ibility of selecting the flat shaded vertex for the first triangle line of a primitive packet The subsequent flat shaded vertices are in incrementing order except in the case of triangle fans with common flat shaded vertex Separate State variables are provided for triangles and lines The following tables show the sequence of flat shaded vertices for triangles and lines Primitive Type Triangle Strip List Triangle Fan Line Strip List Flat Shaded Flat Shading SV Flat Shading SV Flat Shading SV Vertex Sequence 1 4 7 10 13 2 14 i E Triangle Strip Triangle Strip Reverse Winding order 12 3A Deans o x Triangle Fan Polygon Triangle Fan With Common Flat Shaded Vertex Line Strip The Pixelization Rule state variable sets up the hardware to follow correct pixelization rules It should be set in Render Mode i e for GFXPrimitive packet The Small Triangle Filter Enable enables filtering of small triangles Small Triangles are defined as triangles which do not light any pixels It should be set only in Render Mode when Pixelization Rule is enabled and the Horizontal amp Vertical Bias Values are equal and are programmed to either 1000 or 0000 If other bias values are used then the results may be unpredictable The Horizontal amp Vertical Bias values are programmed in the GFXRENDERSTATE_DEST_BUFFER_VARIABLES packet The following table summarizes acceptable values of these SVs Packet Horizontal Bias Ver
286. ies the end of the vertical sync pulse relative to its beginning This 4 bit value should be set to the least significant 4 bits of the result of adding the length of the vertical sync pulse in terms of the number of scan lines that occur within the length of the vertical sync pulse to the value that specifies the beginning of the vertical sync pulse see the description of the Vertical Sync Start Register for more details 123 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 20 CR12 Vertical Display Enable End Register I O and Memory Offset Address 3B5h 3D5h index 12h Default Undefined Attributes Read Write E Vertical Display Enable End Bits 7 0 This register provides the 8 least significant bits of either a 10 bit or 12 bit value that specifies the number of the last scan line within the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 this value is described in 10 bits with bits 6 1 of the Overflow Register CRO7 supplying the 2 most significant bits In extended modes where bit 0 of the I O Control Register CR80 is set to 1 this value is described in 12 bits with bits 3 0 of the Extended Vertical Display Enable End Register CR31 supplying the 4 most significant bits This 10 bit or 12 bit value should be programmed to be equal to the number of the last scan line within in the active display area Since the active display area always starts on
287. if the event is unmasked in the IMR and the interrupt is not enabled through the IER the parser halts until the IIR is cleared In this case the software has to poll the IIR to check for this condition and clear the IIR as an interrupt will not occur a 31 29 Client 000 Instruction Parser 28 23 Opcode 01h Reserved MBZ 11 2 3 GFXCMDPARSER_USER_INTERRUPT This instruction will generate a user defined interrupt if the interrupt is enabled and not masked The parser continues parsing after processing this instruction If a user interrupt is currently outstanding not yet cleared in the IIR this packet has no effect ee oe 31 29 Client 000 Instruction Parser 28 23 Opcode 02h Reserved MBZ 154 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 11 2 4 GFXCMDPARSER_WAIT_FOR_EVENT This instruction can be used to pause instruction stream processing until a specific event occurs Only one event can be specified specifying multiple events is UNDEFINED The effect of the wait operation depends on the source of the instruction If executed from a batch buffer the instruction parser halts and suspend instruction arbitration until the event occurs If executed from a ring buffer further processing of that ring will be suspended although instruction arbitration from other rings will continue 31 29 28 23 3 1 VBLANK If this bit is set and this instruction is executed out of a Batch Buffer
288. igh Register CROC Bits 9 2 of this value are provided by the Start Address Low Register CROD Bits 1 0 of this value are always 0 and therefore not provided It should be further noted that in extended modes the 30 bits from these four registers are double buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance To change the start address in extended modes all four registers must be set for the new value and then bit 7 of the Extended Start Address Register CR40 must be set to 1 Only then will the graphics controller update the start address on the next VSYNC When the update is done the graphics controller sets bit 7 of the Extended Start Address Register CR40 back to 0 138 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 38 CR70 Interlace Control Register I O and Memory Offset Address 3B5h 3D5h index 70h Default 00h Attributes Read Write Interlace CRT Half Line Value Enable 7 Interlace Enable 0 Selects non interlaced CRT output default 1 Selects interlaced CRT output CRT Half Line Value When interlaced CRT output has been selected the value in this register specifies the position along the length of a scan line at which the half line vertical sync pulse occurs for the odd frame This half line vertical sync pulse begins at a position between two horizontal s
289. implemented in Intel 810 chipset 31 24 Reserved Must be Zero 6 BR18 23 00 Destination Transparency Color 7 BR15 31 00 Pattern Address 25 06 are implemented in Intel 810 chipset 12 2 14 FULL_MONO_SRC_BLT 178 The full BLT is the most comprehensive BLT instruction It provides the ability to specify all 3 operands destination source and pattern The source operand is monochrome and the pattern operand is the same bit width as the destination operand The whole color pattern 8 x 8 pixels 8 16 or 48 DWs is read at the beginning of the BLT and stored in the Texture Cache The pattern vertical alignment specifies which scan line of the pattern is used first The destination address specifies the horizontal alignment The only memory accesses required for the remainder of the BLT is destination and sometimes monochrome source accesses since the source is monochrome The monochrome source transparency mode indicates whether to use the source background color or deassert the write enables when the bit in the source is 0 When the source bit is 1 then the source foreground color is used in the ROP operation The ROP value chosen should involve the mono source data in the ROP operation All non text and non immediate monochrome sources are word aligned At the end of a scan line the monochrome source the bits until the next word boundary must be ignored The Monochrome source data bit position field 2 0 indicates which bi
290. ine forgoes the process of reading the pattern data the presumption is made that all of the bits of the pattern data are set to 0 and the pattern operand for all bit wise operations is forced to the background color specified in the Color Expansion Background Color Register X Increment Decrement Select 0 The bytes corresponding to the pixels within each scan line of data are written to the destination starting with the bytes corresponding to the left most pixel of each scan line at the destination being the first to be written and then proceeding in a rightward direction toward the right most pixel The bytes corresponding to the pixels within each scan line of data are written to the destination starting with the bytes corresponding to the right most pixel of each scan line at the destination being the first to be written and then proceeding in a leftward direction toward the left most pixel Monochrome Source Transparency Mode This bit applies only when the source data is in monochrome This bit determines whether or not the byte s at the destination corresponding to the pixel to which a given bit of the source data also corresponds will actually be written if that source data bit has the value of 0 This feature can make it possible to use the source as a transparency mask The BLT Engine is configured to accepted either monochrome or color source data via the opcode field 0 This causes normal operation with regard to the use of the sour
291. initiate the asynchronous execution of GC instruction streams This programming mechanism is direct and synchronous with software execution on the processor Instruction Stream DMA via Instruction Ring Buffers This programming mechanism utilizes the indirect and asynchronous execution of GC instruction streams to control certain GC functions e g all 2D and 3D drawing operations Software writes instructions into an instruction buffer either a Ring Buffer or Batch Buffer and informs the GC that the instructions are ready for execution The Instruction Parser will then at some point read the instructions via DMA and execute them 141 Intel 815 Chipset Graphics Controller PRM Rev 1 0 10 3 10 4 10 4 1 10 4 2 142 intel GC Register Programming All of the GC registers except for the PCI Configuration registers are memory mapped The base address of this 512 KB memory block is programmed in the MMADR PCI Configuration register Note that 2D control registers VGA and Extended VGA registers are also located at their standard I O locations For more information on the registers refer to the System Address Map chapter GC Instruction Streams This section describes how instruction streams can be used to control GC operation and perform GC operations Instruction Use GC instructions are used to control drawing engines and various GC functional units e 3D Instructions 3D instructions are used to prog
292. instruction descriptions e Instruction Parser Instructions These instructions control various GC interface units eg Local Memory Interface Display Interface setting break points etc Instruction Descriptions GFXCMDPARSER_NOP_IDENTIFICATION This instruction effectively provides a no operation instruction that can be used to pad the instruction stream e g in order to pad out a batch buffer to a QWord boundary However there is one operation this instruction can perform If the Enable bit is set the command parser will write the Identification Number field contents into the NOP Identification Register This provides a general purpose instruction stream tagging breadcrumb mechanism One possible use would be for software to use a NOP_IDENTIFICATION instruction to tag a subsequent Breakpoint Interrupt event The GFXCMDPARSER_ NOP IDENTIFICATION instruction format is ee 31 29 Client 000 Instruction Parser 28 23 Opcode 00h Enable 1 write the identification number 0 don t write the identification number Identification Number Reserved MBZ 153 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 11 2 2 GFXCMDPARSER_BREAKPOINT_INTERRUPT This instruction will generate a breakpoint interrupt and cause the parser to stop until the interrupt is cleared by writing the Interrupt Identity Register If the interrupting event is masked through the IMR the parser continues parsing However
293. ion Horizontal Origin An unsigned integer specifying both the upper left pixel of the destination block and the origin of the motion vectors in the reference frame s This value must be a multiple of the width The valid range is 0 1023 15 10 Reserved 00h Vertical Origin An unsigned integer specifying both the upper left pixel of the destination block and the origin of the motion vectors in the reference frame s This value must be a multiple of the height The valid range is 0 1023 31 26 Reserved 00h Height An unsigned integer specifying the height of the destination block and the source block s if required The valid values for this field are dependant on the Block Pattern Format as follows Disabled Valid range 1 1023 used for skipped macroblocks Single Valid values are 2 4 8 Halves Valid values are 2 4 8 Quadrants Valid values are 4 8 16 15 10 Reserved 00h Width An unsigned integer specifying the width of the destination block and the source block s if required The valid values for this field are dependant on the Block Pattern Format as follows Disabled Valid range 1 1023 used for skipped macroblocks Single Valid values are 2 4 8 Halves Valid values are 4 8 16 Quadrants Valid values are 4 8 16 Forward Motion Vector see the Motion Vector Format below Se Backward Motion Vector see the Motion Vector Format below Block Intra coded Correction Data Each double word 32 bits contai
294. ion ensure that neither the Palette Read Index Register DACRX or the Palette Write Index Register DACWX are written to before all three bytes are read or written A write to either of these two registers causes the circuitry that automatically cycles through providing access to the bytes for red green and blue components to be reset such that the byte for the red component is the one that will be accessed by the next read or write operation via this register 9 6 CRT Controller Register The CRT controller registers are accessed by writing the index of the desired register into the CRT Controller Index Register at I O address 3B4h or 3D4h depending on whether the graphics system is configured for MDA or CGA emulation The desired register is then accessed through the data port for the CRT controller registers located at I O address 3B5h or 3D5h again depending upon the choice of MDA or CGA emulation as per MSR 0 For memory mapped accesses the Index register is at 3B4h MDA mode or 3D3h CGA mode and the data port is accessed at 3B5h MDA mode or 3D5h CGA mode Notes 1 Register CR80 enables disables the CRTC Extensions except for register CR41 2 Group 0 Protection In the original IBM VGA CR 0 7 could be write protected by CR11 7 In BIOS code this write protection is set following each mode change Other protection groups have no current use and would not be used going forward by the BIOS or by drivers They are the resu
295. is done will the graphics controller update the start address on the next VSYNC When this update has been performed the graphics controller will set bit 7 of this register back to 0 EE Reserved Read as Os This field must be Os when this register is written Start Address Bits 23 18 This start address is a 16 bit value that specifies the memory address offset from the beginning of the frame buffer or a 32 bit buffer address at which the data to be shown in the active display area begins default is 0 In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the start address is specified with a 16 bit value The eight bits of the Start Address High Register CROC provide the eight most significant bits of this value while the eight bits of the Start Address Low Register CROD provide the eight least significant bits In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the start address is specified with a 32 bit value Bits 31 24 of this value are provided by the Extended Start Address High Register CR42 Bits 23 18 of this value are provided by bits 5 0 of this register Bits 17 10 of this value are provided by the Start Address High Register CROC Bits 9 2 of this value are provided by the Start Address Low Register CROD Bits 1 0 of this value are always 0 and therefore not provided Note that in extended modes these 32 bits from these four registers are double buffered and sy
296. isters The corresponding bits are the mask bits that prevent that bit in the Interrupt Status Register from generating a PCI write cycle Any unmasked interrupt bit set to 0 will allow the Interrupt Status Register to be written to the address specified by the Hardware Status Vector Address Register when the Interrupt Status Register changes state 14 13 10 8 Reserved Pri Dply Reserved Overlay 0 Reserved Detect Flip Flip Error Pending Pending Master 6 5 4 3 2 0 Pri Dply Pri Dply Reserved Reserved Reserved Reserved User Breakpoint VBLANK Event Defined Interrupt Description Interrupt Status Mask Bits 0 Not Masked 1 Masked prevents PCI write cycle 322 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 2 2 IER Interrupt Enable Register Address Offset 020A0h Default Value 0000h Access Read Write Size 16 bits Individual enables for each interrupt described above A disabled interrupt will still appear in the Interrupt Identity Register to allow polling of interrupt sources HW Reserved Pri Dply Sec Dply Overlay 0 Overlay 1 Detect Flip Flip Flip Flip Error Pending Pending Pending Pending Master Rsvd in Rsvd in GMCH GMCH 6 5 4 3 Pri Dply Pri Dply Reserved Reserved Reserved Reserved User Breakpoint VBLANK Event Defined Interrupt i Interrupt Enables See Table 17 1 Enable 0 Disable 323 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16
297. ith the starting and ending pixel offsets from the beginning of the scan line 67 Intel 815 Chipset Graphics Controller PRM Rev 1 0 68 intel This BLT operation does not use the values in the Pattern Address Register the Source Expansion Background Color Register or the Source Expansion Foreground Color Register Figure 24 Results of Example Character Drawing BLT 0 0 1023 0 N Note Drawing is not to scale Scan Lines 128 Through 185 128 128 Destination 135 135 0 767 1023 767 128 128 63 Q 20080h 128th Scan Lin 20480h 129th Scan Lin 20880h 130th Scan Lin 20C80h 131th Scan Lin 21080h 132nd Scan Lir 21480h 133rd Scan Lin 21880h 134th Scan Lin 21C80h 135th Scan Lin 135 135 b_bit12 vsd The above figure shows the end result of performing this BLT operation Only the pixels that form part of the actual letter f have been drawn into the 8x8 destination location on the display leaving the other pixels within the destination with their original gray color Note 7 1 7 2 7 2 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Initialization Registers To function all registers described in this section must be programmed for the Intel 815 chipset family of products The default states of these registers with the exception of registers that deal wit
298. l Memory GPA Card interface so the method used to determine these timing options is entirely up to the OEM One conservative option is to leave the DRAMCL register with its default settings which are the slowest available Another option is to enforce certain minimum timings on any GPA cards used by that OEM and program the DRAMCL with those minimums While not recommended it is also possible to determine optimal timings empirically The following Video BIOS initialization steps only apply if the GMCH is in Internal Graphics Mode Not AGP 1 Video BIOS assumes a VGA monitor type and initializes the 2D display controller in text mode 2 2D Video BIOS should take care to keep track of BIOS changes due to chip version changes 3 The 3D section should be software reset and initialized At this point no 3D operation should be enabled since this is done at the application driver level 2 3 1 3 1 Graphics Driver Startup At this point the GMCH internal graphics controller has been configured and initialized The remainder of the graphics initialization occurs when the operating system calls the graphics driver The graphics driver must initialize the graphics component address re mapping hardware Tasks include 1 Allocate memory for the GTT re mapping table Set the host memory type of graphics memory for both physically local and system memory i e enable Write Combining for local and non local memory OS calls graphics driver w
299. l memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 399 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1152X864_72Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 400 99 199 MHz Dot Clock Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 401 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1152X864_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 C
300. lanking start is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Blanking Start Register CR15 and the most and second most significant bits are supplied by bit 5 of the Maximum Scan Line Register CROQ and this bit of this register respectively In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical blanking start is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Blanking Start Register CR15 and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Blanking Start Register CR33 In extended modes neither this bit nor bit 5 of the Maximum Scan Line Register CRO9 are used This 10 bit or 12 bit value should be programmed to be equal to the number of scan line from the beginning of the active display area to the beginning of the blanking period Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical blanking period begins Vertical Sync Start Bit 8 The vertical sync start is a 10 bit or 12 bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical sync start is specified with a 10 bit value The 8 l
301. layout descriptions certain bits are marked as Reserved When bits are marked as reserved it is essential for compatibility with future devices that software treat these bits as having a future though unknown effect The behavior of reserved bits should be regarded as not only undefined but also unpredictable Software should follow these guidelines in dealing with reserved bits Do not depend on the states of any reserved bits when testing values of registers that contain such bits Mask out the reserved bits before testing Do not depend on the states of any reserved bits when storing to instruction or to a register When loading a register or formatting an instruction always load the reserved bits with the values indicated in the documentation or zero Overview The GC is programmed via three basic mechanisms POST Time Programming of PCI Configuration Registers These registers are programmed once during POST of the video device The PCI Configuration registers are not covered in this PRM For details on accessing the graphics controller s PCI configuration space refer to the Intel 815 Chipset 82815 Graphics and Memory Controller Hub EDS For additional information on accessing non PCI registers refer to the System Address Map chapter Direct Physical I O and or Memory Mapped I O Access of GC Registers Various GC functions can only be controlled via direct register access In addition direct register access is required to
302. ler interface to enable graphics configuration and upgrade flexibility with the Intel 815 chipset The AGP interface and the internal graphics device are mutually exclusive When the AGP port is populated with an AGP graphics card the integrated graphics is disabled thus the display cache interface is not needed The Intel 815 chipset family uses a hub architecture with the Intel 82815 chipset GMCH as the host bridge hub and the I O Controller Hub ICH as the I O hub The Intel 815 chipset supports the 82801AA ICH and the Intel 815E chipset supports the 82801BA ICH2 The ICH is a highly integrated multifunctional I O Controller Hub that provides the interface to the PCI Bus and integrates many of the functions needed in today s PC platforms The GMCH and ICH communicate over a dedicated hub interface 17 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Figure 1 2 1 2 2 18 Intel 815 Chipset System Block Diagram Inteb Pentiune Ill Processor or Inteb Celeron Processor System Bus 66 100 133 MHz 2 AGP Connector AGP Graphics Anaea Ranay i Or 2 IDE Ports Ultra ATA 66 ICH 2 USB Ports ICH Use 4 USB Ports ICH2 A i Video Engine i 1 l 1 Display Cache i i 4 MB SDRAM i 133 MHz Only i i 1 BQH I a LO 1 Ultra ATA 100 He KDH Modem Cod
303. leted 00 Refresh Disabled 01 Refresh Enabed default 11 Reserved 10 Reserved Special Mode Select SMS These bits select special SDRAM modes used for testing and initialization Note that the NOP command must be programmed first before any other command can be issued 000 Normal SDRAM mode Normal default 001 NOP Command Enable NCE This state forces cycles to DRAM to generate SDRAM NOP commands 010 All Banks Precharge Command Enable ABPCE This state forces cycles to DRAM to generate an all banks precharge command 011 Mode Register Command Enable MRCE This state forces all cycles to DRAM to be converted into MRS commands The command is driven on the MA 11 0 lines MA 2 0 correspond to the burst length MA 3 corresponds to the wrap type and MA 6 4 correspond to the latency mode MA 11 7 are driven to 00000 by The GMCH The BIOS must select an appropriate host address for each row of memory such that the right commands are generated on the MA 6 0 lines taking into account the mapping of host addresses to local memory addresses 100 CBR Cycle Enable CBRCE This state forces cycles to DRAM to generate SDRAM CBR refresh cycles 101 Reserved 11X Reserved 345 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 346 19 19 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 I O Control Registers HVSYNC HSYNC VSYNC Contr
304. ll be considered for instruction arbitration and the Head and Tail Offsets will either indicate an empty RB i e Head Tail or will define some number of instructions to be executed Ring Buffer Use Software can write new instructions into the free space of the RB starting at the Tail Offset and up to but not including the QWord prior to the QWord indicated by the Head Offset Recall that software must leave at least one QWord empty in the RB at all times Note that this free space may wrap from the end of the RB back to the start 145 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Software is required to use some mechanism to track instruction execution progress to determine the free space in the RB This can be e A direct read of the Head Pointer register e The automatic reporting of the Head Pointer register e The explicit reporting of the Head Pointer register via the GFXCMDPARSER REPORT HEAD instruction e Some other implicit means by which software can determine how far the IP has progressed in retiring instructions from an RB This could include the use of Store DWORD instructions to write sequencing data to system memory e Once the instructions have been written and padded out to a QWord if necessary software can write the Tail Pointer register to submit the new instructions for execution 10 4 5 Batch Buffers 146 Figure 28 The GC provides for the execution of instruction seq
305. lock of memory BEFORE setting either Bit 5 or Bit 7 of the SMRAM register The memory for TSEG is Stolen first and then the Graphics Local Memory is Stolen An example of this theft mechanism is e TOM equal 64 MB e TSEG selected as 512 KB in size e Graphics Local Memory selected as 1 MB in size e General System RAM available in system 62 5 MB General System RAM Range 00000000h to 03E7FFFFh TSEG Address Range 03F80000h to O3FFFFFFh TSEG Stolen from 03F80000h to O3FFFFFFh Graphics Local Memory Stolen from 03E80000h to 03F7FFFFh 71 Intel 815 Chipset Graphics Controller PRM Rev 1 0 7 3 72 intel Display I O GPIO Clock LCD and Pixel Pipeline Registers These registers are described elsewhere in this document Refer to the appropriate sections of this PRM for detailed bit field descriptions Address Offset Symbol Register Name Instruction and Interrupt Control Registers 020D8h 020DBh FW_BLC FIFO Watermark and Burst Length Control I O Control Registers 05000h 05003h HVSYNC HSYNC VSYNC Control 05010h 05013h GPIOA General Purpose I O Control A 05014h 05017h GPIOB General Purpose I O Control B Clock Control and Power Management Registers 06000h 06003h DCLK_OD Display Clock 0 Divisor g 06004h 06007h DCLK_1D Display Clock 1 Divisor 06008h 0600Bh DCLK_2D Display Clock 2 Divisor g 0600Ch 0600Fh LCD_CLKD LCD Clock Divisor 06010h 06013h
306. low the selection of the common vertex for triangle fan primitive and the third second triangle line vertex for other primitives Please note that this instruction packet affects the following selections e D3D and OGL strip and fan notations selection e D3D and OGL vertex selection on flat shading color e In flat shade mode the value of the first vertex in the primitive is used to determine the value of the face In Gouraud shade mode the value of the face is determined by a linear interpolation between all of the primitive s vertices 239 Intel 815 Chipset Graphics Controller PRM Rev 1 0 ee 31 29 Client 03h Render Processor 28 24 3DState24 02h Z Function State Mask 1 Update 0 Do Not Update Z Function Valid values are 00h Reserved 01h Never never pass 02h Less pass if the source Z is less than the destination Z 03h Equal pass if the source Z is equal to the destination Z 04h Lequal pass if the source Z is less than or equal to the destination Z 05h Greater pass if the source Z is greater than the destination Z 06h Notequal pass if the source Z is note equal to the destination Z 07h Gequal pass if the source Z is greater than or equal to the destination Z 08h Always always pass 15 Line Width State Mask 1 Update 0 Do Not Update 15 Line Width This value specifies the width of lines in pixels The variable is represented as an unsigned value with 2 integer bit
307. lt of an industry trend some years ago to attempt to write protect other groups of registers however all such schemes were chip specific Only the IBM compatible write protection method Group 0 Protection is currently supported The following figure shows display fields and dimensions and the particular CRxx register that provides the control 109 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Figure 25 9 6 1 110 Display Fields and Dimensions CRxx Control Registers CROO Horizontal Total CRO3 Horizontal Blank End CR05 Horizontal Sync End CR04 Horizontal Sync Start CR02 Horizontal Blank Start CRO01 Horizontal Display Enable End Display CR15 Vertical Blank Start _ _ Horizontal Right Border Horizontal Sync CR10 Vertical Sync Stat gt ke CR12 Vertical Display Enable End gt CR16 Vertical Blank End CR11 Vertical Sync End tt CR06 Vertical Total Vertical Bottom Border Blank Vertical Front Porch Vertical Sync Blank Vertical Back Porch crt_reg vsd CRX CRT Controller Index Register I O and Memory Offset Address 3B4h 3D4h Default OUh U Undefined Attributes Read Write The value which can be supported at CRX is likely to be impacted by the X09 register which modifies the meaning of the extended CRxx registers Description CRT Controller Register Index T
308. major order for the left half of the block followed by the data for the right half of the block Chromanance blocks are always considered to be Single blocks using bits 23 and 22 for the Cr and Cb blocks respectively 11 Quadrants Upper left Upper right Lower left Lower right Uses bits 27 24 for the four quadrants of the Luminance block respective Intra coded correction data is delivered in row major order for the four quadrants of the block beginning with the upper left quadrant and proceeding to the upper right lower left and lower right quadrants Chromanance blocks are always considered to be Single blocks using bits 23 and 22 for the Cr and Cb blocks respectively 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bits Description Cb Block Pattern Enable disable intra coded correction data for the Cb block 21 18 Reserved 00h 17 16 Horizontal Motion Vector Precision 00 1 2 pixel 01 1 4 pixel used for 2 1 down sampling 10 1 8 pixel used for 4 1 down sampling 11 Reserved 15 14 Vertical Motion Vector Precision 00 1 2 pixel 01 1 4 pixel used for 2 1 down sampling 10 1 8 pixel used for 4 1 down sampling 11 Reserved 13 12 Prediction Type 00 Intra coded The motion vector fields are ignored The Intra coded values are each 8 bits wide with no padding 01 Forward prediction Only the forward motion vector is used The correction data are signed 16 bit values 10 Backward predicti
309. may be even 8 1022 Map Base Address Virtual memory address which is aligned on 16 byte boundaries Bits 31 4 of a 32 bit byte address are specified Reserved 0h 221 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 8 222 intel GFXRENDERSTATE_MAP_FILTER The Mapping Engine is capable of fetching texels pixels from at most two maps per pixel This instruction specifies the filter settings associated with specified map Figure 35 State Variable Relationships Coordinate Sets lt _ Map Information Texels Blending Stages Anisotropic filtering produces superior image quality with reduced performance Adjusting the LOD bias can contain the aspect ratio of the filter Generally the LOD bias should be set to 1 0 when anisotropic filtering is enabled The Mip Mode Min Mode and Mag Mode Filter state variables continue to have their meanings when anisotropic filtering is enabled The Mip Mode Filter state variable specifies whether mip mapping is enabled If so it also identifies if the nearest mip map should be used for the texture data or texels between the two nearest maps should be dithered together when transitioning between maps LOD dithering provides the ability to offset the map LOD based on the pixel x y location A 4x4 x y matrix provides values which range from 0 to 15 which are scaled and then added to the LOD computation The Min Mo
310. me pattern is loaded from the instruction stream The pattern vertical alignment specifies which scan line of the pattern is used first The destination address specifies the horizontal alignment The only memory accesses required for the remainder of the BLT is destination and monochrome source accesses The monochrome source transparency mode indicates whether to use the source background color or deassert the write enables when the bit in the source is 0 When the source bit is 1 the source foreground color is used in the ROP operation The ROP value chosen should involve the Mono source and Mono pattern All non text monochrome sources are word aligned At the end of a scan line the monochrome source the bits until the next word boundary must be ignored The Monochrome source data bit position field 2 0 indicates which bit position within the first byte should be used as the first source pixel The monochrome pattern transparency mode indicates whether to use the pattern background color or deassert the write enables when the bit in the source is 0 When the source bit is 1 the pattern foreground color is used in the ROP operation The monochrome source transparency mode works identical to the pattern transparency mode The destination pitches can be either sign The pattern direction follows the destination operand de 19 17 Monochrome source data bit position of the first pixel within a byte per scan line 16 08 Reserved Must be Ze
311. ment number and is negative during Y mirroring The low order three bits are always zero The range is 4 KB 277 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 3 15 4 3 1 278 intel Overlay Initial Phase Registers Provides a spatial sub pixel accurate adjustment This value is always a fractional positive number that when combined with the subtract one from initial phase bit the possible range for initial phase becomes 1 lt phase lt 1 There are two separate vertical initial phase registers that are used in field based image processing YRGB_VPH Y RGB Vertical Phase Register Memory Address Offset 1Ch R W On chip Reg Mem Addr Offset 3011Ch RO debug path Default Value 00h Access see address offset above Size 32 bits 31 20 19 16 15 4 3 0 Y RGB Vertical Phase Reserved Y RGB Vertical Phase Reserved Buffer Field 1 Buffer Field 0 J o oo eO Y RGB Vertical Phase Buffer Field 1 This fractional value sets the initial vertical phase In packed formats YUV RGB data buffer 1 when up scaling in frame mode YUV RGB data field 1 when up scaling in field mode In planar YUV formats Y data buffer 1 when up scaling in frame mode Y data field 1 when up scaling in field mode Y RGB Vertical Phase Buffer Field 0 This fractional value sets the initial vertical phase In packed formats YUV RGB data buffer 0 when up scaling in frame mode YUV RGB data field 0 when up scaling in field mode I
312. mode which will be introduced into D3D in DX7 Here color chroma key does not discard pixels it simply modifies the filtered texel color alpha in a way which permits keyed out areas of textures from not contributing to the pixel output Here the application is responsible for programming the pixel pipeline texture blend alpha test alpha blend etc to process keyed non keyed texel pixel results in the intended fashion i e there is no automatic override of pixel pipeline controls For example the application may simply choose to use the filtered texel s alpha value in the Alpha Test stage to discard pixels with zero alpha presumably introduced by the color chroma key function this would effectively emulate the kill pixel mode Another scenario might modulate the filtered texel s color by the filtered texel s alpha and then add the result to the current pixel 233 Intel 815 Chipset Graphics Controller PRM Rev 1 0 234 intel The Intel 810 chipset implementation of Blend color chroma key mode is again different than what Microsoft eventually defined for DX7 DX7 specifies that any contributing texels which match the key must be replaced by black with zero alpha prior to application of the normal texture filter The Intel 810 chipset implements a different function where the output texel has it s alpha value forced to zero if the nearest neighbor texel sample matches the key the color associated with this keye
313. mory Offset Address 40028h Default None Attributes RO DWord accessible 31 26 25 0 Reserved Must Destination Y2 Address Bits 25 0 be Zero ee Reserved Must be Zero The maximum GC graphics address is 64 MBs Debug implementation specific bmtdpix 5 0 Destination Y2 Address Used as the scan line address Destination Y2 Address for BLT instruction TEXT_BLT The address points to the first pixel in a scan line and is compared with the ClipRect Y1 amp Y2 address registers to determine whether the scan line should be written or not The Destination Y2 address is the bottom scan line to be written for text 193 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 12 BR11 BLT Source Pitch Offset or Monochrome Source 194 Quadwords Memory Offset Address 4002Ch Default None Attributes RO DWord accessible 13 0 31 14 Reserved Source Pitch Offset or Monochrome Source Quadwords ee 13 0 Source Pitch Offset or Monochrome Source Quadwords When the color source data is located within the frame buffer or AGP aperture these signed 14 bits store the memory address offset pitch value by which the source address originally specified in the Source Address Register is incremented or decremented as each scan line s worth of source data is read from the frame buffer by the BLT Engine so that the source address will point to the next memory address from which the next scan line s worth of source data is
314. mory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 421 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1600x1200 _85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 422 229 1229 5 MHz Dot Clock OxAF OxAF Intel around the world United States and Canada Intel Corporation Robert Noyce Building 2200 Mission College Boulevard P O Box 58119 Santa Clara CA 95052 8119 USA Phone 800 628 8686 Europe Intel Corporation UK Ltd Pipers Way Swindon Wiltshire SN3 1RJ UK Phone England 44 1793 403 000 Germany 49 89 99143 0 France 33 1 4571 7171 Italy 39 2 575 441 Israel 972 2589 7111 Netherlands 31 10 286 6111 Sweden 46 8 705 5600 Asia Pacific Intel Semiconductor Ltd 32 F Two Pacific Place 88 Queensway Central Hong Kong SAR Phone 852 2844 4555 Japan Intel K
315. ms but not both simultaneously Either the PIPE or the SBA 7 0 mechanism must be selected during system initialization High priority accesses are supported Only memory writes from the hub interface to AGP are allowed No transactions from AGP to the hub interface are allowed 2 2 4 2 2 5 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Display Cache Interface The GMCH supports a Display Cache SDRAM controller with a 32 bit 133 MHz SDRAM array The DRAM type supported is industry standard Synchronous DRAM SDRAM like that of the system memory The local memory SDRAM controller interface is fully configurable through a set of control registers Hub Interface The hub interface is a private interconnect between the GMCH and the ICH Intel 82815 Chipset GMCH Integrated Graphics Support The GMCH includes a highly integrated graphics accelerator Its architecture consists of dedicated multi media engines executing in parallel to deliver high performance 3D 2D and motion compensation video capabilities The 3D and 2D engines are managed by a 3D 2D pipeline preprocessor allowing a sustained flow of graphics data to be rendered and displayed The deeply pipelined 3D accelerator engine provides 3D graphics quality and performance via per pixel 3D rendering and parallel data paths which allow each pipeline stage to simultaneously operate on different primitives or portions of the same primitive The GMCH graphics accelerator engine
316. must be 32B cacheline aligned a Dword Length 09h Must Be One 1 23 16 Raster Operation 15 00 Destination Pitch signed 13 00 are implemented in Intel 810 chipset 1 BR13 Solid Pattern Select 1 solid pattern 0 no solid pattern 30 X Direction 1 written from right to left decrementing backwards 0 incrementing Reserved Must be Zero 28 Mono Pattern Transparency Mode 1 transparency enabled 0 use background Reserved Must be Zero 25 24 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved Intel 815 Chipset Graphics Controller PRM Rev 1 0 DWord Bit Description Destination Height in scan lines 28 16 are es in Intel 810 chipset 3 BR09 31 00 Destination Address Address of the first byte to be written ee are implemented in Intel 810 chipset Source Pitch quadword aligned and signed 13 00 are implemented in Intel 810 chipset 5 BR12 31 00 Source Address 25 00 are implemented in Intel 810 chipset 6 BR18 Reserved Destination Transparency Color 7 BR16 Reserved Must be Zero Pattern Background Color Reserved Must be Zero 8 BR17 Pattern Foreground Color 181 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 16 FULL_MONO_PATTERN_MONO SRC_BLT The full BLT provides the ability to specify all 3 operands destination source and pattern The pattern and source operands are monochrome The monochro
317. n map which may be accessed Values 0 through 10 will force the mip map selection to be between the maximum resolution mip map and the specified value This value must be correctly identified for the current map no assumptions are made about the number of mips associated with a particular map This value must also be greater than the Maximum Mip Level 224 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 10 GFXRENDERSTATE_MAP_LOD_CONTROL The Level of Detail dither weight and bias can be associated with each map using the following instruction Figure 37 State Variable Relationships Coordinate Sets lt _ Map Information Texels Blending Stages a 3129 29 Client 03h Client 03h Rendering Engine ssidY Engine Texture LOD Dither Weight A 4 bit dither value can be added to the computed and biased LOD which softens the transitions between mip maps The position or weight of the dither value is specified as follows 00 Full dither weight the dither value has a range of 0 0 0 9375 01 dither weight the dither value has a range of 0 0 0 4375 10 dither weight the dither value has a range of 0 0 0 1875 11 dither weight the dither value has a range of 0 0 0 0625 3 Texture LOD Bias Mask 0 Do not update 1 Update Texture LOD Bias This is a signed value that is added to the LOD when the L
318. n planar YUV modes Y data buffer 0 when up scaling in frame mode Y data field 0 when up scaling in field mode 15 4 3 3 Intel 815 Chipset Graphics Controller PRM Rev 1 0 UV_VPH UV Vertical Phase Register Memory Address Offset 20h R W On chip Reg Mem Addr Offset 30120h RO debug path Default Value 00h Access see address offset above Size 32 bits 19 16 15 4 31 20 3 0 a UV Vertical Phase 1 This fractional value is only used in YUV planar formats where the UV plane may have a different vertical initial phase from the Y data This field is used with Buffer 1 in frame mode or Field 1 in field mode UV Vertical Phase 0 This fractional value is only used in YUV planar formats where the UV plane may have a different vertical initial phase from the Y data This field is used with Buffer 0 in frame mode or Field 0 in field mode HORZ_PH Horizontal Phase Register Memory Address Offset 24h R W On chip Reg Mem Addr Offset 30124h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 20 19 16 15 4 3 0 Phase ee 31 20 UV Horizontal Phase Sets the initial horizontal phase for the UV data Only used in YUV modes Y RGB Horizontal Phase Sets the initial horizontal phase for both buffers fields Unlike the vertical initial phases this does not change buffer to buffer or field to field YUV modes use a separate initial phase for Y and UV data This value will either
319. nation X1 ANd X22 cece ce eeee eect eeneeeeeeeaeeeeeeaeeeeeenaeeeeeeaas 192 12 3 10 _BRO9 Destination Address and Destination Y1 Address 0 193 12 3 11 BR10 Destination Y2 Address 0 0 0 0 cceceeeeeeeeeeneeeeeeneeeeeenaeeeeeneeeeseaes 193 12 3 12 _BR11 BLT Source Pitch Offset or Monochrome Source Quadwords 194 12 3 13 BR12 Source Address ccccccceecseccececeeeeeeeeceneaeeeeeeeeesencueaeeeeeeeeeeeenaees 195 12 3 14 _BR13 BLT Raster OP Control and Destination Pitch ee 196 12 3 15 BR14 Destination Width amp Height cece eeeeeeeeenneeeeeeneeeeeeaes 198 12 3 16 BR15 Color Pattern Address cc eceeceeeeeeeeeeeneeeeeeeneeeseenaeeeeeeneeeeseaas 199 12 3 17 BR16 Pattern Expansion Background amp Solid Pattern Color 00 200 12 3 18 BR1 7 Pattern Expansion Foreground Color cccccceeseeeeeeeeeeeeneees 200 12 3 19 _BR18 Source Expansion Background and Destination Color 201 12 3 20 _BR19 Source Expansion Foreground Color ccceseeceesteeeeeesteeeeeenaes 201 12 3 21 S SLADD Source Scan Line Address cccceeeeeeeeceeeeeeeeeeeeestaeess 202 12 3 22 D_SLH Destination Scan Line Height eee eeeeeeeneeeeeeenteeeeeeaaes 202 12 3 23 _D_SLRADD Destination Scan Line Read Address 0 eeeees 203 Rendering Engine INStructions 0 cccccceeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeaeeeeeeaeeeseeaeeeseene
320. nchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance To change the start address in extended modes all four registers must be set for the new value and then bit 7 of this register must be set to 1 Only if this is done will the graphics controller update the start address on the next VSYNC When this update has been performed the graphics controller will set bit 7 of this register back to 0 137 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 36 CR41 Extended Offset Register I O and Memory Offset Address 3B5h 3D5h index 41h Default 00h Attributes Read Write 7 4 3 0 oon Reserved Read as 0 s This field must be 0 s when this register is written 3 0 Offset Bits 11 8 of a 12 bit value This register provides the 4 most significant bits of a 12 bit value that specifies the number of words or Dwords of frame buffer memory occupied by each horizontal row of characters Whether this value is interpreted as the number of words or Dwords is determined by the settings of the bits in the Clocking Mode Register SRO1 This 12 bit value should be programmed to be equal to either the number of words or Dwords depending on the setting of the SRO1 register of frame buffer memory that is occupied by each horizontal row of characters The companion offset register CR13 7 0 specifies the 8 least significant bits o
321. nd the complete destination window has not been filled this pixel will be repeated until the end of the destination window intel 15 4 5 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 SWIDQW Source Width In QWords Register Memory Address Offset 38h R W On chip Reg Mem Adar Offset 30138h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 24 23 16 15 9 8 0 Reserved UV Source Width in Reserved Y RGB Source Width in QWs QWs ce UV Source Width in QWords The number of QWs contained in a single line of planar UV source data Minimum size is two QWords Y RGB Source Width in QWords The number of QWs contained in a single line In planar modes this is the Y source width Minimum size is two QWords 283 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 5 3 284 SHEIGHT Source Height Register Memory Address Offset 3Ch R W On chip Reg Mem Addr Offset 3013Ch RO debug path Default Value 00h Access see address offset above Size 32 bits 31 26 25 16 15 11 10 0 E 25 16 UV Source Height In packed formats this is unused For planar YUV formats it indicates the number of lines starting at and including the base address line contained in the UV source data When the last line is reached and the complete destination window has not been filled this line will be repeated until the end of the destination window e A height must not be specified fo
322. neda eet AAEN EEA AE E NEENA 269 15 3 1 1 GAMC 5 0 Gamma Correction RegisterS ccceceeeees 269 15 3 1 2 Mathematical Gamma Correction For Overlay eeeeeeeeeeee 271 15 4 Memory Offset Registers asssessssnesssnnesrrnnassinneasnnnnnstenaatinaaatinnentananataanaetnnnaanannaanan 274 15 4 1 Overlay Buffer Pointer Registers c ceceeeeeeseeeeeeeeneeeeeenaeeeeeetaeeeeeseaaes 274 15 4 1 1 OBUF_O0Y Overlay Buffer 0 Y Pointer Register cee 274 15 4 1 2 OBUF_1Y Overlay Buffer 1 Y Pointer Register ce 275 15 4 1 3 OBUF_OU Overlay Buffer 0 U Pointer Register 275 15 4 1 4 OBUF_O0V Overlay Buffer 0 V Pointer Register cee 276 15 4 1 5 OBUF_1U Overlay Buffer 1 U Pointer Register 276 15 4 1 6 OBUF_1V Overlay Buffer 1 V Pointer Register 277 15 4 2 Overlay Stride Registers ccccesceceessceceeeeneeeeceeneeceeneneeeeeeeneeeeeneneeeeeesaes 277 15 4 2 1 OVOSTRIDE Overlay 0 Stride Register eeeeeeeereeeneees 277 15 4 3 Overlay Initial Phase Registers cc cceceeeseeeeeesneeeeeeneeeeeeeeeeeeseeeeeeaes 278 15 4 3 1 YRGB_VPH Y RGB Vertical Phase Register eeeeeees 278 15 4 3 2 UV_VPH UV Vertical Phase Register ceceeeseeeeeeeetteeeees 279 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 3 3 HORZ_PH Horizontal Phase Register 2 1 eeen 279 15 4 3 4 INIT_PH lInitial Phase Register
323. neeeeeeaas 224 13 10 GFXRENDERSTATE_MAP_LOD_CONTROL eee ceeeeceeeeeeteeeeeenteeeeeeneeeeeeaeeeeneaas 225 13 11 GFXRENDERSTATE_MAP_PALETTE_LOAD e ce eeeeccceeeeneeeeeeeneeeeeeneeeeeenaeeeeeeaas 226 13 12 GFXRENDERSTATE_MAP_COLOR_BLEND_ STAGES seeen 227 13 13 GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES 0 0 eee eeeeeeeenteeeeeenaes 230 13 14 GFXRENDERSTATE COLOR FACTOR eio errr aa I ARRE Ei Er RR EErEE 232 13 15 GFXRENDERSTATE_COLOR_CHROMA_KEV 0 ccccceeeeeeeeeeeeteeeeeetieeeeeenteeeeeaaes 233 13 16 GFXRENDERSTATE_SRC_DST_BLEND_MONO occ eeeeceeeeeeeeeeeetteeeeeeteeeeeeaaes 235 13 17 GFXRENDERSTATE_Z BIAS ALPHA_FUNC_REF 00 ccccceeeeeeeeeeeeeeeeeeeeseeeeeeaas 238 13 18 GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_ MODE o e 239 13 19 GFXRENDERSTATE_BOOLEAN_ENA_1 0c ee eeceeeeeeeeeeeeeeneee teense eeenaeeeeenaeeeeeenaes 241 13 20 GFXRENDERSTATE_BOOLEAN_ENA 2 o ce eeeecceee eee eeeeeeneeeeeeaeeeeeeaeeeeenaeeeeeeaaes 242 13 21 GFXRENDERSTATE FOG COLOR crre arannana aaa Ena EEA RRUA ETET AARRE TEE RERA ARREA 243 13 22 GFXRENDERSTATE_DRAWING_RECTANGLE_INFO sssssesreseeerrssrerrssrerrsse 243 13 23 GFXRENDERSTATE_SCISSOR_ENABLE 0 ccccceeeeeeeeeeeeeneeeeeeeeeeeeeneeeeetaeeeeeaaes 245 13 24 GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO cece eeeeteeeeeeteeeeeenteeeeeaaes 246 13 25 stipple Pattemn E EEE AT eens ee E pete meinen aoe 247 13 26 GFXRENDERSTATE_ANTI_ALIASING 0 000 eeeceeeeeeenteeee
324. nernrnrrseeene 148 10 4 6 4 Instruction Arbitration Rules cccccccscsseeceeeceeeceaeeaseeeeeeeeeeeaaees 148 10 4 6 5 Batch Buffer Protected Mode ccccceesseccceceeeceseeseeeeeeeeeeanensnes 148 10 5 Instr ction F tmataanssrn naa a ba deat a a a a tas 149 10 5 1 Instruction Parser Instructions cccccce se eseecececeeeceaeeseneeeeeeeeseaaeneseeeeeeeas 149 10 5 2 ZDANStRUCTIONS eiaa dacan Shas dadba iottoads a td aae iad aaa aaa 149 10 5 3 SDzINSUHUCHONS i sitchen sedstecds dadecon a a a dadenen aa a addeben a ae aaa 150 11 Instruction Parser INStruUctionS msione i a a a a e a a a 153 IA troduction aae a a a a a a a a a a a a a a 153 1122 Instruction Descriptions mena e dest haloes caches a a E aaas 153 11 2 1 GFXCMDPARSER_NOP_IDENTIFICATION ccccssssseseseseeeeeseeeees 153 11 2 2 GFXCMDPARSER_BREAKPOINT_INTERRUPT cccsssseseeseeeeeees 154 11 2 3 GFXCMDPARSER_USER_INTERRUPT essssssssssseseseseeesseeaeees 154 11 2 4 GFXCMDPARSER_WAIT_FOR_EVENT c esesssesssesssssssssssesseeeees 155 11 2 5 GFXCMDPARSER_FLUSH cccccesesesesesesesceeeeeseeeeeeeseeeseaeseaeaeaeaeaeees 156 11 2 6 GFXCMDPARSER_CONTEXT _ SEL uuu ccc ceeeeeseseseseseteseteeeeeeeeeeeeeeeaeaes 156 11 2 7 GFXCMDPARSER _DEST_BUFFER_INFO c cccccecseseeeeteeeteteeeeeees 157 11 2 8 GFXCMDPARSER _FRONT_BUFFER_INFO c cccccessesesseeeseeeeereees 158 1
325. nges the state of the Mapping Engine cache by flipping the bit Mapping Cache Enable using the 253 Intel 815 Chipset Graphics Controller PRM Rev 1 0 a intel 3D instruction GFXRENDERSTATE BOOLEAN EN 2 To ensure proper hardware operation software must follow up with the GFXCMDPARSER_ FLUSH instruction to cause the hardware to flush the 3D pipeline Color Calculator e Texture blend stage 0 must always be enabled For untextured primitives a select arg operation should be programmed This is equivalent to a pass through operation to the next pipeline stage e When Stage N is enabled Stages 0 N 1 should also be enabled e Current as opposed to accumulator must be selected as output for the last enabled stage e Data must be written to Current output register before it is selected as an input argument for the next stage e Data must be written to Accumulator output register before it is selected as an input argument for a later stage e Replicate a in specular is not allowed e Current o cannot be used for blending Stretch BLT e When doing stretch BLT in YUV 422 format the origin of the source rectangle must be DWord aligned In other words the X coordinate of the origin must be even Texture Color Z Surface Pitch e Texture surface pitch Pitch of tiled region programmed in fence register e Texture surface pitch must be 4 QWs for linear organization of memory i e MAP INFO DW1 3 0 2h e Texture surfa
326. nly the lower 11 bits is used by hardware This value is pixel aligned U11 format and reference to the origin unclipped upper left corner of the drawing rectangle Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 25 Stipple Pattern The stipple pattern is a 4x4 bit memory that serves as pixel write mask When stipple is enabled the frame buffer will only be updated with pixels that have 1 s in their associated stipple pattern memory locations The stipple pattern memory maps to a 4x4 pixel grid The stipple pattern repeats for x and y coordinates on every span 4x4 pixels The purpose of the stipple pattern is mostly for testing This is a non pipeline state variable The stipple pattern pixel enable function can be represented as _ 31 29 29 Client 03h Rendering Engine 28 24 3DStateMWNP Non pipelined 1Dh ES Opcode 83h 150 0 DWORD_LENGTH 0 ret 17 Reserved Enable 1 Enable 0 Disable Ee 0 Stipple Pattern 247 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 26 GFXRENDERSTATE_ANTI_ALIASING The Anti aliasing packet defines the anti aliasing enable bounding box expansion line anti aliasing region polygon anti aliasing region and edge flag enable State variables The anti aliasing enable state variable turns on anti aliasing of polygons and lines The Bounding Box enclosing the triangle or line is expanded in all directions by the bounding box expansion
327. ns packed 8 bit data or 16 bit data depending on the Prediction Type Intra coded Block Four 8 bit values packed in 32 bits The least significant byte contains data for the left most pixel spatially Predicted Block Two 16 bit values packed in 32 bits The least significant word contains data for the left most pixel spatially 212 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 3 1 Motion Vector Format The motion vectors provided in the GFXBLOCK instruction have the following format es e O Horizontal Motion Vector Value The value is signed 2 s complement fixed point with the following formats depending on the Motion Vector Precision bits The range defines the clamp boundaries for the values Precision Format Range 1 2 pixel 14 1 1024 0 1023 5 1 4 pixel 13 2 1024 0 1023 75 Ig pixel 12 3 1024 0 1023 875 Vertical Motion Vector Value The value is signed 2 s complement fixed point with the following formats depending on the Motion Vector Precision bits The range defines the clamp boundaries for the values Precision Format Range 1 3 pixel 14 1 1024 0 1023 5 1 4 pixel 13 2 1024 0 1023 75 1 g pixel 12 3 1024 0 1023 875 13 4 Non pipelined State Variables The GMCH does not optimize on state variables that change infrequently ISVs are asked to group polygons for state changes for performance reasons In the GMCH the following state variables will not be pipeline
328. ntroller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1600x900_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 416 OxAF OxAF Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR12 OxAF CR15 OxAF Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 417 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1600x1200 _65Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local mem
329. o an invalid PTE will result in an interrupt T1T0 01 Physical address targets Local Memory 00 Physical address targets main memory not snooped 11 Physical address targets cacheable main memory results in snoop on processor bus 10 Reserved T1T0 11 is used only if the surface is a Blit soure or destination operand used within the context of a source copy command Note that the 4 KB pages of physical main memory that have been mapped to the graphics aperture through the GTT must be accessed strictly through the aperture The GMCH does not guarantee data coherency if any of these pages are accessed directly using their physical addresses For example a 4 KB page of main memory has been mapped via the GTT to a 4 KB aperture page Although the GMCH still allows this 4 KB page to be accessed directly through its physical memory address the chipset does not guarantee data coherency with respect to accesses through the normal graphics aperture address range This is because a read to the aperture memory can result in prefetching and caching of data while a write to the aperture can result in temporary write data buffering in the graphics controller of the GMCH Accesses to these same memory locations through their physical address take a different logical path through the chipset controller side of the GMCH There is no hardware support for ensuring coherency between these two access paths 43 Intel 815 Chipset Graphics Controller
330. ocal Intel sales office or your distributor to obtain the latest specifications and before placing your product order C is a 2 wire communications bus protocol developed by Philips SMBus is a subset of the PC bus protocol and was developed by Intel Implementations of the 1 C bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Alert On LAN is a result of the Intel IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation www intel com or call 1 800 548 4725 Third party brands and names are the property of their respective owners Copyright Intel Corporation 2000 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 Contents 1 Introduction ranite aa eas Goel ea a eiaa aa a e a aaa adaa aa eaea aa aaa a a ea 15 1 1 Terminologi eli Ana i ll eae 15 1 2 Reference DOCUMENTS esniak enanas aaaea a aaa a daaa iaaa aad aaa 16 Intel 815 Chipset OVERVIOW lt asnadiascced tasesnditaseahddecaaszad dannebdeaasnanadcnauedog ete navad deasabdeaaanancdcuatanazecs neds 17 2 1 VO Controller Hubei a a aaia aiea aaa a anaa a ana a E 18 2 2 Intel 82815 Chipset GMCH OVverview cccccccceececceceeeeeeeeeeaeceeeeeeeseceneaeeeeeeeeeteaeess 18 2 2 1 Host Interface ccccccecececeeceececeee
331. odate discontinuous source data the source and destination pitch registers can be used to specify the offset in bytes from the beginning of one scan line s worth source data to the next Otherwise if the source data is contiguous then an offset equal to the length of a scan line s worth of source data should be specified Monochrome Source Data The opcode of the command packet specifies whether the source data is color or monochrome Since monochrome graphics data only uses one bit per pixel each byte of monochrome source data typically carries data for 8 pixels which hinders the use of byte oriented parameters when specifying the location and size of valid source data Monochrome source data is always supplied through the command stream which avoids the read latency during BLT Engine operation Some additional parameters must be specified to ensure the proper reading and use of monochrome source data by the BLT engine The BLT engine also provides additional options for the manipulation of monochrome source data versus color source data The various bit wise logical operations and per pixel write masking operations were designed to work with color data In order to use monochrome data the BLT engine converts it into color through a process called color expansion which takes place as a BLT operation is performed In color expansion the single bits of monochrome source data are converted into one two three or four bytes depending on the
332. odulate with luminance channel OFh Reserved 10h Linearly Blend using Texel0 s Alpha as the Blend Term 11h Linearly Blend using Texel1 s Alpha as the Blend Term 12h Linearly Blend using Texel0 s Color as the Blend Term 13h Linearly Blend using Texel1 s Color as the Blend Term 14h Subtract Arg1 Arg2 15h 1Fh Reserved 229 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 13 GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES The Rendering Engine supports three map color blend stages for the alpha channel Any of these stages may perform an operation utilizing the alpha channel from up to two texels from the Mapping Engine the iterated alpha and or a constant color Figure 40 State Variable Relationships Coordinate Sets lt m Map Information Texels Blending Stages The following equations are supported by each blending stage Alphaout Arg1 Arg2 Add Alphacut Otterated Arg 1 Olteratea Arg2 230 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel The settings for these stages are specified in the following instruction Come Te fe Alpha Arg1 Valid values are Oh Reserved 1h Alpha Factor 2h Reserved 3h Iterated Alpha 4h Reserved 5h Current Alpha 6h TexelO Alpha 7h Texel1 Alpha Reserved 00h 13 Invert Alpha Arg1 0 Do not Invert Argument 1 Invert
333. of setting of IIR bits when interrupts occur This is only used when the GFXCMDPARSER_FRONT_BUFFER _INFO packet is being used See that instruction for additional information To prevent race conditions the status write occur before the STOREDWORD following the flip packet is written 320 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Overlay 0 Flip Pending Status bit is set to reflect a pending flip when the parser parses a flip packet and cleared when the flip takes place Display VBLANK whereas IIR reflects Flip Occurred which is contrary to the general definition of setting of IIR bits when interrupts occur This is only affected by the use of flip packets not through the manual method or the capture auto flipping To prevent race conditions status register write must occur before the STOREDWORD following the flip packet is written 7 Primary Display VBLANK Set at leading edge of display VBLANK This is actually delayed to allow all internal hardware VBLANK events to occur before the interrupt is generated to eliminate race conditions These events include the update of the display and overlay status bits and loading of the overlay registers EES Primary Display Event Interrupt cause will be determined by reading the display status register and is one of the following e Flat Panel Hot Plug Detect Interrupt e Display VSYNC e Display Line Compare On active going edge of OR of unmasked Display
334. ol and Destination Offset Memory Offset Address 40004h Default 0000 xxxx Attributes RO DWord accessible BRO1 contains the contents of the last Setup instruction DWord 1 It is identical to the BLT Raster OP Control and Destination Offset definition but it is used with the following instructions PIXEL BLT SCANLINE BLT and TEXT BLT 31 30 29 28 27 25 24 23 16 SolPat Rsvd Mono Mono Src Dyn Src Pat Sel Color Raster Operation Trans Trans Mode Depth Enable 15 14 13 0 Destination Pitch Offset Descriptions Solid Pattern Select This bit applies only when the pattern data is monochrome This bit determines whether or not the BLT Engine actually performs read operations from the frame buffer in order to load the pattern data Use of this feature to prevent these read operations can increase BLT Engine performance if use of the pattern data is indeed not necessary The BLT Engine is configured to accept either monochrome or color pattern data via the opcode field 0 This causes normal operation with regard to the use of the pattern data The BLT Engine proceeds with the process of reading the pattern data and the pattern data is used as the pattern operand for all bit wise operations The BLT Engine forgoes the process of reading the pattern data the presumption is made that all of the bits of the pattern data are set to 0 and the pattern operand for all bit wise operations is forced to the background color specified
335. ol CRX 70 Read the current value Clear the interlace enable bit OR in the saved value of the Interlace Control Register Write the result back into the Interlace Control Register Address Mapping GR10 Read the current value of the Address Mapping Register Save only the reserved bits values bits 7 5 OR in the saved value of the Address Mapping Register Write the result back into the Address Mapping Register Now the DRAM refresh can be turned on Read the value of the DRAM CONTROL HI Register Turn off the DRAM REFRESH RATE bits OR in a 60 Hz refresh rate value Write the result back into the DRAM CONTROL HI Register 49 Intel 815 Chipset Graphics Controller PRM Rev 1 0 50 e Other registers that should restore only certain bits from the saved state values Bit Blit Control MM 0x7000c Read the current value of the Bit Blit Control Register Clear the bits pertaining to the Color Expansion Mode bits 5 4 OR in the saved value of the Bit Blit Control Register Write the result back into the Bit Blit Control Register Display Control Field MM 0x70008 Read the current value of the Display Control Register OR in the saved value of the Display Control Register Write the result back into the Display Control Register Pixel Pipeline Configuration 0 Field MM 0x70009 Read the current value of the Pixel Pipeline Configuration 0 Regist
336. ol Register Address Offset 05000h Default Value 00000000h Size 32 bits Attribute R W Bits 19 16 are for DPMS and DDC Sync Select 31 20 19 18 17 16 Reserved VSYNC VSYNC HSYNC HSYNC Control Data Control Data Reserved HSYNC VSYNC En se 31 20 Reserved VSYNC Control Bit 19 a Control and bit 18 VSYNC Data are used by BIOS to take over the sync during DDC1 communication during POST The BIOS can force the VSYNC data at the same time as VSYNC control enables this signal as an output so that the VSYNC pulse occurs on every write by the BIOS This is done to speed up some very slow DDC communications 19 0 Normal VSYNC output 1 Contents of VSYNC Data will go out to VSYNC pin 18 17 5 1 HSYNC Control 0 Normal HSYNC output 1 Contents of HSYNC Data will go out to HSYNC pin 16 HSYNC Data HSYNC VSYNC Enable 0 HSync and VSync are deactivated when the internal DAC is disabled default 1 HSync and VSync remain active when the internal DAC is disabled via the PWR_CLKC register 347 7a _ VSYNG Data Intel 815 Chipset Graphics Controller PRM Rev 1 0 19 2 GPIO Registers 19 2 1 _GPlOA General Purpose I O Control Register A Address offset 05010h Default value 00h 00h OOOUND000b 000U0000b ACCESS Read write Size 32 bit This register controls the general purpose I O pins DDCK and DDDA which are used to create a Display Data Channel DDC serial bus for communication with
337. oller PRM Rev 1 0 6 2 2 58 intel Figure 13 Representation of On Screen 6x4 Array of Pixels in the Frame Buffer 0 0 639 0 270F8h 28100h 28108h 256 256 261 256 270F8h 28100h 256th Scan Line 28108h 257th Scan Line 258th Scan Line 259th Scan Line 270F8h 28100h 28108h 256 259 261 259 270F8h 28100h 28108h Note Drawing is not to scale i 479 639 779 b_blt6 vsd Since there are other pixels on each of the scan lines on which this 6x4 block exists that are not part of this 6x4 block what appears to be a single 6x4 block of pixels on the display must be represented by a discontinuous block of graphics data made up of 4 separate sub blocks of six bytes apiece in the frame buffer at addresses 28100h 28380h 28600h and 28880h This situation makes the task of reading what appears to be a simple 6x4 block of pixels more complex However there are two characteristics of this 6x4 block of pixels that help simplify the task of specifying the locations of all 24 bytes of this discontinuous block of graphics data all four of the sub blocks are of the same length and the four sub blocks are separated from each other at equal intervals The BLT engine is designed to make use of these characteristics of graphics data to simplify the programming required to handle discontinuous blocks of graphics data For such a situation the B
338. oller PRM Rev 1 0 VGA and Extended VGA Registers This chapter describes the registers and the functional operation notations for the observable registers in the 2D section Each register is documented and the various bit settings defined It is important to note that not all combinations of bit settings result in functional operating modes Note that these registers can be accessed via either I O space or memory space The memory space addresses listed are offsets from the base memory address programmed into the MMAPA register PCI configuration offset 14h For each register the memory mapped address offset is the same address value as the I O address General Control amp Status Registers The setup enable and general registers are all directly accessible by the processor A sub indexing scheme is not used to read from and write to these registers I O Memory I O Memory Offset Offset STOO VGA Input Status Register 0 3C2h 3C2h C FCR VGA Feature Control Register 3CAh 3CAh 3BAh 3DAh 3BAh 3DAh MSR VGA Miscellaneous Output 3CCh 3CCh 3C2h 3C2h Register NOTES 1 The address selection for ST01 reads and FCR writes is dependent on CGA or MDA emulation mode as selected via the MSR register ST01 VGA Input Status Register 1 3BAh 3DAh 3BAh 3DAh a a a Various bits in these registers provide control over and the real time status of the horizontal sync signal the horizontal retrace interval the vertical sync signal and the verti
339. olor Bits 3 0 9 Pixel Text amp Graphics Graphics Oh th 2h 3h 4h 5h 6h 7h 8h 0 0 1 Undefined 2 1 3 Undefined 4 2 5 Undefined 6 3 7 Undefined Undefined Undefined SONDOAKRWDND 105 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 4 7 AR14 Color Select Register I O and Memory Offset Address Read at 3C1h and Write at 3COh index 14h Default OUh U Undefined Attributes Read Write 7 4 3 2 1 0 Palette Bits P 7 6 These are the 2 upper most of the 8 bits that are used to map either text attributes 1 0 or pixel color input values for modes that use 16 colors to the 256 possible colors contained in the palette These 2 bits are common to all 16 sets of bits P5 through PO that are individually supplied by Palette Registers 0 F AR 00 0F Alternate Palette Bits P 5 4 These 2 bits can be used as an alternate version of palette bits P5 and P4 Unlike the P5 and P4 bits that are individually supplied by Palette Registers 0 F AR 00 0F these 2 alternate palette bits are common to all 16 of Palette Registers Bit 7 of the Mode Control Register AR10 is used to select between the use of either the P5 and P4 bits that are individually supplied by the 16 Palette Registers or these 2 alternate palette bits 9 5 VGA Color Palette Registers The palette DAC has two main components a palette in which a selection of 256 colors may be stored and a set of three digital to analog D to
340. om memory If an operand is in system cacheable memory and is either small or only accessed once it can be copied directly to the instruction stream versus to graphics accessible memory The IMMEDIATE BLT data MUST transfer an even number of DWs The BLT engine will hang if it does not get an even number of DWs or the exact number of QWs required This BLT instruction performs a monochrome source copy where the only operands involved are a monochrome source and destination The source and destination operands cannot overlap which means that the X direction must always be forward Monochrome source data is sent through the instruction stream BR11 DWO 15 0 4 All non text monochrome sources are word aligned At the end of a scan line the monochrome source the bits until the next word boundary must be ignored The Monochrome source data bit position field 2 0 indicates which bit position within the first byte should be used as the first source pixel The monochrome source transparency mode indicates whether to use the source background color or deassert the write enables when the bit in the source is 0 When the source bit is 1 then the source foreground color is used in the ROP operation The ROP value chosen should involve the Mono source data in the ROP operation The Destination pitch can either be positive or negative to allow mirroring in the Y direction 175 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Coe e e 19
341. on Only the backward motion vector is used The correction data are signed 16 bit values 11 Bi directional Prediction Both the forward and backward motion vectors are used The correction data are signed 16 bit values Reserved 00h Reserved 00h Forward Reference Picture Structure This field overrides the vertical line stride and offset specified in the MAP_INFO instruction 4 00 Frame Vertical stride 1 line 01 Reserved 10 Top Field Vertical stride 2 lines offset 0 lines 11 Bottom Field Vertical stride 2 lines offset 1 line 2 Reserved 00h 1 Backward Reference Picture Structure This field overrides the vertical line stride and offset specified in the MAP_INFO instruction 00 Frame Vertical stride 1 line 01 Reserved 10 Top Field Vertical stride 2 lines offset 0 lines 11 Bottom Field Vertical stride 2 lines offset 1 line 211 7 Destination Picture Structure Specifies the structure of the destination surface for predicting this block The overall structure of the picture may be different as in field frame prediction This field overrides the vertical line stride and offset specified in the DEST_BUFFER_VARIABLES instruction 00 Frame Vertical stride 1 line 01 Reserved 10 Top Field Vertical stride 2 lines 11 Bottom Field Vertical stride 2 lines 5 2 2 6 3 0 Intel 815 Chipset Graphics Controller PRM Rev 1 0 DWord Bits Descript
342. on each new vertex which defines a triangle when processing strips and fans Triangle Edge VO V1 Enable Required only on the first vertex of a triangle and on each new vertex which defines a triangle when processing strips and fans Y Position Required for every vertex Z Position Optional Z Bias Optional Reciprocal of W Optional Diffuse Color Alpha Red Green and Optional Blue Specular Color Fog Factor Optional Texture Coordinate Set 0 Optional Texture Coordinate Set 1 Optional 207 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 1 7 GFXVERTEX Rendering Processor instructions include data per vertex The vertex data format is the same for these instructions GFX VERTEX is not an instruction but a definition of this vertex data format GFXVERTEX does not include an instruction header since it is not an instruction The GFX VERTEX format is X position Relative to origin drawing rectangle or dest buffer Valid data range is 383 to 1663 IEEE float except 19 bit mantissa a Reserved 00h Triangle Edge V2 V0 Enable This flag enables anti aliasing and wireframe capabilities for the triangle edge defined by the third and first vertices 1 enable 0 disable This flag field is valid only in the first vertex of the triangle definition It is reserved otherwise Triangle Edge V1 V2 Enable This flag enables anti aliasing and wireframe capabilities for the triangle edge defined by the second
343. on for details on defining primitive vertex Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 1 6 Variable Length Vertex Formats for Rendering Instructions The GC supports variable length vertex formats These formats are determined by enable bits contained in the variable length vertex format VLVF instructions The following table specifies the attributes associated with each vertex The order of the attributes must be strictly observed For any attribute that is defined as not present the value of the corresponding attribute from the last triangle of last packet will be used for the triangles in this packet However in the case of strip and fan primitives the vertex numbers rotate from one primitive to the next primitive e g the third vertex of one triangle will become the first vertex of the next triangle Therefore the re used attribute value from the last primitive will not be guaranteed to be on the same vertex of the next primitive In this case undesired results may occur It is recommended to turn off features that have the corresponding attributes disabled e g if no texture coordinate is send then turn off texture mapping feature X Position Required for every vertex Triangle Edge V2 V0 Enable Required only on the first vertex of a triangle and on each new vertex which defines a triangle when processing strips and fans Triangle Edge V1 V2 Enable Required only on the first vertex of a triangle and
344. on the Vendorld and ProductId values The driver normally caches this information so that it is accessible by other driver modules when needed The next task of the device driver is to ensure that required resources are present These resources include the minimum memory requirements IO address space requirements and operating system support requirements such as GART support If the driver detects that the operating system or the physical hardware does not meet the driver s minimum requirements the driver should not load The operating system should then be able to make use of the graphics adapter in its VGA and VESA compliant mode If the operating system and hardware support are present the driver should acquire the blocks of memory and IO address space that will be required These blocks should include at least the following e Memory mapped IO address space 512 KB beginning at 0x80000 e Linear frame buffer space 32 or 64 MB beginning at OxFE000000 e Legacy IO addresses to support monochrome or color monitors e VGA IO addresses Frame Buffer Initialization The frame buffer initialization is responsible for setting up the memory that will contain the display data Other objects also can be stored in display memory The following steps should be performed e Map a 0x80000 byte region in memory to the MMIO base address The base address of the memory mapped region should be programmed into the MMADDR register offset 14 in the PC
345. ond most significant bits are supplied by bit 6 and this bit respectively of this register In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical display enable end is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Display Enable End Register CR12 and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Display End Enable Register CR31 In extended modes neither this bit nor bit 6 of this register are used This 10 bit or 12 bit value should be programmed to be equal to the number of the last scan line within in the active display area Since the active display area always starts on the Oth scan line this number should be equal to the total number of scan lines within the active display area minus 1 116 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Vertical Total Bit 8 The vertical total is a 10 bit or 12 bit value that specifies the total number of scan lines This includes the scan lines both inside and outside of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical total is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Total Register CRO6 and the most and second most significant bits are supplied by bit 5 and this bit respectivel
346. onding bit of monochrome pattern data carries the value of 0 The foreground and background colors used in the color expansion of monochrome pattern data can be set in the Pattern Expansion Foreground Color Register and Pattern Expansion Background Color Register Destination Data There are actually two different types of destination data the graphics data already residing at the location that is designated as the destination and the data that is to be written into that very same location as a result of a BLT operation The location designated as the destination must be within the frame buffer or Main memory graphics memory where the BLT engine can read from it and write to it directly The blocks of destination data to be read from and written to the destination may be either contiguous or discontinuous All data written to the destination will have the color depth to which the BLT engine has been set It is presumed that any data already existing at the destination which will be read by the BLT engine will also be of this same color depth the BLT engine neither reads nor writes monochrome destination data The Destination Address Register is used to specify the address of the destination To accommodate discontinuous destination data the Source and Destination Pitch Registers can be used to specify the offset in bytes from the beginning of one scan line s worth of destination data to the next Otherwise if the destination data is con
347. one 1 Intr Ring Empty or Disabled Low Priority Ring Empty or Disabled 16 1 10 NOPID NOP Identification Register Address Offset 02094h Default Value 00000000h Access Read Only Size 32 bits This register contains the value specified by the last GFXCMDPARSER NOP IDENTIFICATION instruction received 31 22 21 0 ee Identification Number Bits 5 0 of this identification number must be zero 313 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 1 11 INSTPM Instruction Parser Mode Register Address Offset 020COh Default Value 00h Access Read Write Size 8 bits The bits in this register control the operation of the Instruction Parser Note Ifan instruction type is disabled the parser will read it out of the instruction batch FIFO but will not send it to its destination Error checking will be performed 3 7 Reserved Enable Disable Disable Disable Disable Disable Sync Mcomp GDI Blitter Render State Render Packet Instrs Instrs 3D Stretc Variable Palette AGP Flush h Instrs Updates Updates Description Reserved Enable Sync AGP Flush Enable pipe and AGP flush Set by software and cleared by the parser on detecting graphics pipe flushed before parsing a subsequent packet 1 Enable 0 Cleared by graphics controller Enable Sync flush Enable pipe flush Set by software and cleared by the parser on detecting graphics pipe flushed before parsing a subsequent packet 1 Enable
348. ong these color data positions This method allows the full range of over 16 million possible colors to be accessible in modes with only 8 or fewer bits per pixel The color data stored in these 256 color data positions can be accessed only through a complex sub addressing scheme using a data register and two index registers The Palette Data Register at I O address 3C9h or memory address offset 3C 1h is the data port The Palette Read Index Register at I O address 3C7h or memory address offset 3C7h and the Palette Write Index Register at I O address 3C8h or memory address offset 3C8h are the two index registers The Palette Read Index Register is used to choose the color data position that is to be read from the data port The Palette Write Index Register is 106 9 5 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 used to choose the color data position that is to be written to through the same data port This arrangement allows the same data port to be used for reading from and writing to two different color data positions Reading and writing the color data at a color data position involves three successive reads or writes since the color data stored at each color data position consists of three bytes To read a color data position the index of the desired color data position must first be written to the Palette Read Index Register Then all three bytes of data in a given color data position may be read at the Palette Data Regi
349. ontal retrace clock 1 The vertical timing counter is clocked by the horizontal retrace clock divided by 2 Select Row Scan Counter 0 A substitution takes place where bit 14 of the 16 bit memory address generated of the memory address counter after the stage at which these 16 bits may have already been shifted to accommodate word or DWord addressing is replaced with bit 1 of the row scan counter at a stage just before this address is presented to the frame buffer address decoder 1 No substitution takes place See following tables Compatibility Mode Support 0 A substitution takes place where bit 13 of the 16 bit memory address generated of the memory address counter after the stage at which these 16 bits may have already been shifted to accommodate word or DWord addressing is replaced with bit 0 of the row scan counter at a stage just before this address is presented to the frame buffer address decoder 1 No substitution takes place See following tables The following tables show the possible ways in which the address bits from the memory address counter can be shifted and or reorganized before being presented to the frame buffer address decoder First the address bits generated by the memory address counter are reorganized if need be to accommodate byte word or DWord modes The resulting reorganized outputs MAOut15 MAOut0 from the memory address counter may also be further manipulated with the substitution of bits from
350. ontroller PRM Rev 1 0 Bit Description Odd Even Mode 0 Addresses sequentially access data within a bit map and the choice of which map is accessed is made according to the value of the Plane Mask Register SRO2 1 The frame buffer is mapped in such a way that the function of address bit 0 is such that even addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and 3 This works in a way that is the inverse of and is normally set to be the opposite of bit 2 of the Memory Mode Register SR02 Read Mode During a processor read from the frame buffer the value returned to the processor is data from the memory plane selected by bits 1 and 0 of the Read Plane Select Register GR04 During a processor read from the frame buffer all 8 bits of the byte in each of the 4 memory planes corresponding to the address from which a processor read access is being performed are compared to the corresponding bits in this register if the corresponding bit in the Color Don t Care Register GRO7 is set to 1 The value that the processor receives from the read access is an 8 bit value that shows the result of this comparison A value of 1 in a given bit position indicates that all of the corresponding bits in the bytes across all 4 of the memory planes that were included in the comparison had the same value as their memory plane s respective bits in this register Reserved Read as Os 1 0 Write Mode 00 Write Mo
351. ontroller PRM Rev 1 0 intel 12 2 7 COLOR_BLT COLOR BLT is the simplest BLT operation It performs a color fill to the destination with a possible ROP The only operand is the destination operand which is written dependent on the raster operation The solid pattern color is stored in the pattern background register e This instruction is optimized to run at the maximum memory write bandwidth e Only a positive destination pitch is allowed e The typical Raster operation code FO which performs a copy of the pattern background register to the destination ee 0 BROO Client 02h 2D Processor Instruction Target Opcode 40h Reserved Must be Zero Dword Length 03h fwon SSS Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 Reserved 23 16 Raster Operation 15 00 Destination Pitch positive 13 00 are implemented in Intel 810 chipset 2 BR14 31 16 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 1500 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BR09 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset 4 BR16 Reserved Must be Zero Solid Pattern Color 170 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 8 PAT_BLT PAT_BLT is used when there is no source and the color pattern is not trivial is not a solid color onl
352. or negative to allow mirroring in the Y direction ee 0 BROO 31 29 29 Client 02h 2D Processor ssi isSSCSCidY 02h 2D Processor Monochrome source data bit position of the first pixel within a byte per scan line Mono Source Transparency Mode 1 transparency enabled 0 use background Must Be One 1 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved 15 00 Destination Pitch signed 13 00 are implemented in Intel 810 chipset 2 BR14 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BR09 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset 174 Intel 815 Chipset Graphics Controller PRM Rev 1 0 DWord Bit Description 4 31 16 Reserved Must be Zero 4 BR11 15 00 Number of Monochrome Source Quadwords 1 1 to 64k Quadwords 64 to 4M bits 5 BR12 31 00 Source Address address of the first byte of the first pixel on the first scan line 25 00 are implemented in Intel 810 chipset 6 Reserved Must be Zero 6 BR18 Source Background Color 7 Reserved Must be Zero 7 BR19 Source Foreground Color 12 2 12 MONO_SRC_COPY_IMMEDIATE_BLT This instruction allows the driver to send data through the instruction stream which eliminates the read latency of reading a source fr
353. or the start address register plus stride Field mode will increment the address by two times the stride as it increments from line to line Initial phase selection is based on the field and the vertical Initial phase select This bit will be overridden by the capture port when autoflipping 0 Frame Mode 1 Field Mode Ignore Buffer and Field When set don t update the buffer and field from command register 0 Use buffer and field data to update buffer field 1 Don t update buffer field Buffer and field Selects on which buffer and field for display This determines which buffer and field will be displayed when the overlay is enabled or when the ignore bit was clear It would otherwise be ignored and the internal buffer field values would be used These are readable through the status register 00 Buffer 0 Field 0 01 Buffer 0 Field 1 10 Buffer 1 Field 0 11 Buffer 1 Field 1 Overlay Enable Changing this bit from a 0 to a 1 will cause the overlay to begin display after the next qualified flip event A disable 1 gt 0 will cause the overlay to stop displaying an image on the next display VBLANK 0 Disable No display or memory fetches 1 Enable 297 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 15 4 12 Overlay Alpha Blend Window Position Size Registers These registers allow for the alpha blending of a subsection of the overlay window positioning of the overlay data relative to the grap
354. orward Backward Reference Picture Structure bits when processing the GFXBLOCK instruction 0 Add no offset top field 1 Add 1 bottom field 15 11 Reserved 00h Utilize Fence Registers If enabled the Tiled Surface Tile Height Tile Walk and Pitch are ignored All request addresses are compared with the fence registers and the parameters associated with any matching fence register are utilized in the tiler Otherwise the specified Tile Walk is utilized 0 Disable Fence Register Utilization 1 Enable Fence Register Utilization Tile Walk The direction of increasing sequential addresses This field is ignored when the fence registers are being utilized or the surface is linear 0 X Major 1 Y Major Reserved 00h For Tile Height Reserved 00h Pitch Logz of the surface pitch is specified in quadwords If the surface resides in a fenced region this value must correspond to the pitch specified when programming the fence registers Tiled Surface Specifies the whether the surface is organized as rectangular memory or as tiled memory This field is ignored when the fence registers are being utilized 0 Linear Rectangular memory 1 Tiled Intel 815 Chipset Graphics Controller PRM Rev 1 0 a Dimensions are Powers of 2 This field specifies whether the following Height and Width fields of the map are specified as the log2 of the actual dimension or as the actual height or width If the actual values are
355. ory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 418 OxAF OxAF Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR12 OxAF CR15 OxAF Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 419 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1600x1200_72Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 420 OxAF OxAF Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR12 OxAF CR15 OxAF Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local me
356. ource and destination of the same bit width The source and destination operands may overlap which means that the X and Y directions can be either forwards or backwards The X direction field applies to both the destination and source operands The source and destination pitches can be either sign Requirements e The Intel 815 chipset hardware has a restriction that the BLT color source and destination operands must not co exist on the same 32 Byte cacheline To work around this issue For BLTs that have sharing of a cacheline for a given scanline the driver must treat this as an overlapping BLT case For linear memory the surfaces allocated must be 32B cacheline aligned e Three instructions are affected by this hardware restriction SRC_COPY BLT FULL BLT and FULL MONO PATTERN BLT Essentially any instruction with Color Source amp Destination will have the above restriction OO 0 BROO Client 02h 2D Processor Instruction Target Opcode 43h Reserved Must be Zero Dword Length 04h 1 BR13 Reserved Must be Zero 30 X Direction 1 written from right to left decrementing backwards 0 incrementing 29 28 Reserved Must be Zero Ooz Reserved Must be Zero Must Be One 1 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved Destination Pitch signed 13 00 are implemented in Intel 810 chipset 2 BR14 Destination Height in scan lines 28 16 are implemente
357. ow scan counter is divided by 2 This is normally used to allow CGA compatible modes that have only 200 scan lines of active video data to be displayed as 400 scan lines each scan line is displayed twice Line Compare Bit 9 This bit provides the most significant bit of a 10 bit value that specifies the scan line at which the memory address counter restarts at the value of 0 Bit 4 of the Overflow Register CRO7 supplies the second most significant bit and bits 7 0 of the Line Compare Register CR18 supply the 8 least significant bits Normally this 10 bit value is set to specify a scan line after the last scan line of the active display area When this 10 bit value is set to specify a scan line within the active display area it causes that scan line and all subsequent scan lines in the active display area to display video data starting at the very first byte of the frame buffer The result is what appears to be a screen split into a top and bottom part with the image in the top part being repeated in the bottom part When used in cooperation with the Start Address High Register CROC and the Start Address Low Register CROD it is possible to create a split display as described earlier but with the top and bottom parts displaying different data The top part will display whatever data exists in the frame buffer starting at the address specified in the two aforementioned start address registers while the bottom part will display whatever dat
358. page e the page number of the mapped page within the particular physical memory address space Although the GTT format permits any logical page to be mapped to any page in the supported physical memory address spaces the GC imposes restrictions on how specific graphics operands buffers etc can be mapped to physical memory The GTT entries must be written via a GTT alias in the graphics device s memory mapped register space 10000h 1FFFFh This allows the GC to snoop GTT entry writes and invalidate graphics TLBs as required The GTT entries must not be written directly in system memory 41 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Figure 8 3 4 2 42 GTT Mapping System Memory 31 ie 4 GB Base om Virtual Graphics Memor Bas Graphics Translation Table GTT o 31 Graphics Engine Address Space 7 64 MB GTT Maps 4KB blocks of Virtual Graphics Memory to 4 KB pages in System Memory Cache GTT Maps 4KB blocks Virtual Graphics Memory to 4 KB pages in Display Cache q gtt vsc Memory Buffers for GC s Instruction Interface The GC provides two Ring Buffer RB mechanisms through which instructions can be passed to the GMCH s Instruction Parser In addition the GC provides for the execution of instruction sequences external to the ring buffers These sequences are called batch buffers and are initiated through the
359. parate regions in the frame buffer that are amongst which pixel color or attributes information is split up and stored in standard VGA planar modes This use of multiple terms for the same subject was considered confusing therefore AR12 is called the Memory Plane Enable Register 104 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 4 6 AR13 Horizontal Pixel Panning Register I O and Memory Offset Address Read at 3C1h and Write at 3COh index 13h Default OUh U Undefined Attributes Read Write 7 4 3 0 Reserved 0000 Horizontal Pixel Shift 3 0 Horizontal Pixel Shift 3 0 This field holds a 4 bit value that selects the number of pixels by which the image is shifted horizontally to the left This function is available in both text and graphics modes In text modes with a 9 pixel wide character box the image can be shifted up to 9 pixels to the left In text modes with an 8 pixel wide character box and in graphics modes other than those with 256 colors the image can be shifted uOp to 8 pixels to the left In standard VGA mode 13h where bit 6 of the Mode Control Register AR10 is set to 1 to support 256 colors bit O of this register must remain set to 0 and the image may be shifted up to only 4 pixels to the left In this mode the number of pixels by which the image is shifted can be further controlled using bits 6 and 5 of the Preset Row Scan Register CR08 Number of Pixels Shifted 8 Pixel Text 256 C
360. pearance To change the start address in extended modes all four registers must be set for the new value and then bit 7 of the Extended Start Address Register CR40 must be set to 1 Only if this is done will the hardware update the start address on the next VSYNC When this update has been performed the hardware will set bit 7 of the Extended Start Address Register CR40 back to 0 120 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 15 CROD Start Address Low Register I O and Memory Offset Address 3B5h 3D5h index 0Dh Default Undefined Attributes Read Write ea Start Address Bits 7 0 or 9 2 This register provides either bits 7 through 0 of a 16 bit value that specifies the memory address offset from the beginning of the frame buffer or bits 9 through 2 of a 32 bit buffer address at which the data to be shown in the active display area begins default is 0 In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the start address is specified with a 16 bit value The eight bits of the Start Address High Register CROC provide the eight most significant bits of this value while the eight bits of this register provide the eight least significant bits In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the start address is specified with a 32 bit value Bits 31 through 24 of this value are provided by the Extended Start Address High Register C
361. peed Watermark for 24 bpp at 133 MHz local memory speed 373 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 640x480_70Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 374 28 128 MHz Dot Clock Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 375 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 640x480_75Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark
362. phics Controller PRM Rev 1 0 12 2 2 SETUP_MONO PATTERN_SL_BLT This setup instruction supplies common setup information including clipping coordinates used exclusively with the following instruction e SCANLINE BLT SLB 1 scan line of monochrome pattern and destination are the only operands allowed Clipping addresses and coordinates are inclusive The BLT Engine performs a trivial reject for this BLT before performing any accesses If any pixels are included within the clipping rectangle then it performs every access but deasserts the byte enables for the pixels that are clipped These are the only instructions that require state There are 4 dedicated registers to contain the state for this instruction The 3 double word registers are DW1 Control DW5 Background color and DW6 Foreground color The ClipRect registers do not need to be saved since they are never used by the interrupt ring buffer Only a positive destination pitch is allowed C 0 BROO Client 02h 2D Processor Instruction Target Opcode 10h Reserved Must be Zero Dword Length 07h Solid Pattern Select 1 solid pattern 0 no solid pattern SLB amp Pixel only 31 30 29 Reserved Must be Zero Mono Pattern Transparency Mode 1 transparency enabled 0 use background Reserved Must be Zero Must Be One 1 25 24 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved 23 16 Raster Operation
363. phics host TLB error should not cause the system to hang TLB error is flagged only for a write For the write cycle with the TLB error and for all subsequent write cycles byte enables are masked If local memory is accessed in UMA system the cycle is forwarded to system memory and completed with masked byte enables For a write TLB error error registers should be appropriately set Graphics memory reads do not cause any side effects Hence all reads with a TLB error are allowed to complete Note that no error condition will be set in the Error registers for a read TLB error Irrespective of the cycle being a read or a write if the location of page table is in a restricted region a page table error will be set This error is not resettable 327 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 2 6 2 328 intel Resetting the Page Table Error The page table error will be reset every time a write cycle is generated to bit 15 of the Interrupt Identity register IIR independent of the setting of the bit in the IMR or the IER Resetting the page table error should cause the subsequent write cycles to be completed without masking of the byte enables Note that a TLB error due to locating a page in system memory can never be cleared Reserved MM LM Display or Reserved Reserved Instruction Refresh Overlay Parser timer error under run Error ooo o o o o e OSOS Reserved MM LM Refresh Timer Error 1 Indicates a r
364. pixel data Software sets bits that it does not want to be included within the comparison to 0 15 4 9 3 SCLRKM Source Color Key Mask Register Memory Address Offset 60h R W On chip Reg Mem Addr Offset 30160h RO debug path Default Value 00h Access see address offset above Size 32 bits SourceCo Reserved Source Key Mask Enables nst a Blend Enable 23 16 15 8 7 0 Constant o Constant a Constant a Red lt 7 0 gt Green lt 7 0 gt Blue lt 7 0 gt 291 Intel 815 Chipset Graphics Controller PRM Rev 1 0 292 J o o e 31 Source Constant Alpha Blend Enable 1 Enable Source Alpha Blending when the logical OR of the Source Key Mask Enables are asserted within the Alpha Blend Window and the comparison indicates that the overlay is to be displayed 0 Disable Source Alpha Blending 26 24 Source Key Mask Enables Each bit enables one channel If the bit is a 1 the comparison result is used otherwise it is ignored Bit 2 Enables Comparison 23 16 Bit 1 Enables Comparison 15 8 Bit 0 Enables Comparison 7 0 23 16 Constant Alpha Red 7 0 This involves three 4 x 8 bit alpha multipliers to be inserted in the Overlay and Primary Display merging logic When the alpha blend is selected the most significant 4 bits of each alpha channel is used as the alpha term If the original 8 bits of the alpha channel FF the alpha channel value is treated as a 1 If alpha 0 1 0 must also be treated as a
365. pointer bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb B Mask 128KB 1B 00000000 00000001 11111111 11111111 B Corrected head pointer 00000000 0000000b bbbbbbbb bbbbbbbb B Note that this error only occurs in autoreport head mode There is not a problem with the instruction parser command GFXCMDPARSER REPORT HEAD Intel 815 Chipset Graphics Controller PRM Rev 1 0 Dword Description Offset 31 21 Reserved 20 3 Tail Pointer Programmable Qword Offset in the ring buffer 20 3 is used by the hardware 2 0 Reserved 31 2 Head pointer Hardware maintained DWord Offset in the ring buffer 20 2 is used by the hardware Bits 31 21 are incremented whenever the head pointer wraps from the end to the start of the ring buffer lt gt Wrap Count 1 0 Reserved 31 26 Reserved 25 12 Starting Address Programmable 4 KB page aligned address of the buffer This is a physical address no GTT translation 11 0 Reserved 20 12 Buffer Length Programmable length of the ring buffer in 4 KB Pages Maximum 2 MB x000 One 4 KB Page 11 3 Reserved 2 1 Automatic Report Head pointer Report happens when the Ring DMA crosses 64 KB or 128 KB boundary XO No report 01 Report every 16 pages 64 KB 11 Report every 32 pages 128 KB Ring Buffer Valid 0 Disabled 1 Enabled 309 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 1 6 310 Note HWS_PGA Hardware Status Page Address Register Address Offse
366. ponding to the pixel to which a given bit of the pattern data also corresponds will actually be written if that pattern data bit has the value of 1 This feature can make it possible to use the pattern as a transparency mask The BLT Engine is configured to accepted either monochrome or color pattern data via the opcode This causes normal operation with regard to the use of the pattern data Wherever a bit in the pattern data has the value of 0 the color specified in the background color register is used as the pattern operand in the bit wise operation for the pixel corresponding to the pattern data bit and the bytes at the destination corresponding to that pixel are written with the result Wher a bit in the pattern data has the value of 0 the byte s at the destination corresponding to the pixel to which the pattern data bit also corresponds are simply not written and the data at those byte s at the destination are allowed to remain unchanged Source Select Mode Configures the BLT Engine data source 0 The BLT Engine reads the source data from the frame buffer at the location specified in the Source Address Register 1 The BLT Engine accepts the source data from instruction stream controller through the IMMEDIATE_BLT instruction The BLT Engine will hang if it doesn t get an even number of DWs Dynamic Color Depth When a SETUP_BLT or SETUP_MONO_PATTERN_SL_BLT is parsed the Color Depth field from these blit commands is reflected in thes
367. pp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 396 Intel 815 Chipset Graphics Controller PRM Rev 1 0 CROO OxA7 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 397 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1152X864_60Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CR05 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 398 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz loca
368. quest length and watermarks to states which would cause the overflow of the sync FIFO For example assume a watermark is set to 33 QW and the request length is set to 32 QWs When the first two requests have been completed 64 QWs will have been written into the sync FIFO During this time only 16 QWs will be drained out of the FIFO to be written to the Display Engine FIFO Since the sync FIFO in the DSI is only 32 QWs deep this will result in 64 16 32 16 QW overflow of the FIFO 31 28 27 24 Overlay Delay Timer1 Overlay Delay Timer0 23 17 12 11 10 8 22 20 19 18 Rsvd MM Dply Burst Reserved MM Display FIFO Rsvd LM Display Burst Length Watermark Length Overlay Watermark Reserved N Oo a 331 Intel 815 Chipset Graphics Controller PRM Rev 1 0 332 C 31 28 Overlay Delay Timer1 Is used to insert waits states in between sets of YUVY requests to MM The value in this register is multiplied by 16 to determine the wait state clock count 27 24 Overlay Delay Timer0 Is used to insert waits states in between any two overlay streamer requests to MM except between sets of YUVY The value in this register is multiplied by 16 to determine the wait state clock count 22 20 MM Display Burst Length Size in QWs of individual requests issued to Memory Use Multiples of 16 QWs for tiled memory 000 8 Qws N A if Trickle Feed is on 001 16 Qws 010 24 Qws 011 32 Qws 100 40 Qws 101 48 Qws 110 56 Qws
369. r lines that are not on the active display e Minimum height is 2 lines or 4 lines for interlaced surfaces Bob 10 0 Y RGB Source Height In packed formats this indicates the number of lines starting at and including the base address line contained in the source data In planar formats it is the number of Y lines This is used to determine where the end of the source is in the vertical direction to handle the edge effects related to the vertical filter When the last line is reached and the complete destination window has not been filled this line will be repeated until the end of the destination window e A height must not be specified for lines that are not on the active display e Minimum height is 2 lines or 4 lines for interlaced surfaces Bob Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 15 4 6 Overlay Scale Factor Registers These registers provide the scaling information that is used to specify the amount of vertical and horizontal scaling In the case of YUV formats there are independent scale factors for Y and UV data to compensate for the various formats that include sub sampled UV data Up or down scaling is set using the bits of the command word In the case of down scaling the integer portion of the scale factor can be up to three in the vertical and is assumed to be one in the horizontal 15 4 6 1 YRGBSCALE Y RGB Scale Factor Register Memory Address Offset 40h R W On chip Reg Mem Addr Of
370. ram the 3D pipeline state and perform 3D rendering operations including StretchBlt operations e Motion Compensation A special GFXBLOCK instruction is used to perform Motion Compensation operations via the Mapping Engine e 2D Instructions BLT These instructions are used to perform BLT operations e Instruction Parser IP Instructions The IP instructions can be used to control and synchronize the instruction stream as well as perform various GC auxiliary functions e g define graphics buffer attributes perform display overlay flips etc Instruction Transport Overview Instructions are not written directly to the GC instead they are placed in memory by software and later read via DMA by the GC s Instruction Parser unit The primary mechanism used to transport instructions is through the use of two ring buffers RB Low Priority RB and Interrupt RB A secondary mechanism for instruction transport is through the use of batch buffers The IP uses a set of rules to determine the order in which instructions are executed Following sections in this chapter provide descriptions of the ring buffers batch buffers and IP rules Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 10 4 3 Instruction Parser The following figure shows a high level diagram of the GC instruction interface The GC s Instruction Parser IP unit is responsible for e Detecting the presence of instructions within the Ring Buffers e Arbit
371. rating the execution of instruction streams e Reading instructions from Ring Buffers and Batch Buffers via DMA e Parsing the common Client destination field of instructions e Execution of Instruction Parser instructions which control IP functionality provide synchronization functions as well as provide miscellaneous GC control functions e Redirection of 2D and 3D instructions to the appropriate destination while following drawing engine concurrency and coherency rules Figure 26 Graphics Controller Instruction Interface Low Priority Ring Graphics Memory 2D Instructions FIFO Interrupt Ring 3D Instructions 3D state Graphics Memory 3D Primitives STRBLT nerian Motion Compensation nstruction 3 pma L 4 Batch Buff Ingtr Instruction po o oo 1 Instruction Parser Instructiong _ parser Control l e g Batch Buffer Instr NOP Sync ID Flush breakpoint y l l Display l Memory Interface Control Engine e g Store DWord to memofy Display Overlay Control g Front Buffer Scan 8 9 gt Overlay Lines Overlay Flip i Engine ee EENE cmd_str vsd l l I I DMA l l l I 143 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 10 4 4 Ring Buffers RB The GC provides two Ring Buffer RB mechanisms through which instructions can be passed to the Instruction Pars
372. re never used by the interrupt ring buffer The Mono source transparency mode flag is maintained although it is always set to one in current driver operation Intel 815 Chipset Graphics Controller PRM Rev 1 0 Pome eee 0 BROO Client 02h 2D Processor Instruction Target Opcode 00h Reserved Must be Zero 0 Dword Length 06h 29 Mono Source Transparency Mode 1 transparency enabled 0 use background TB only Reserved Must be Zero Reserved Must be Zero Must Be One 1 Color Depth All 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved Raster Operation all must CC Hex for TB Destination Pitch positive 13 00 are implemented in Intel 810 chipset SLB amp TB only 2 BRO2 31 00 ClipRect Y1 Address Top 25 00 are implemented in Intel 810 chipset All 3 BROS 31 00 ClipRect Y2 Address Bottom 25 00 are implemented in Intel 810 chipset All 4 BR04 31 16 ClipRect X2 Coordinate Right All 27 16 12 bits are implemented in the Intel 815 chipset 15 00 ClipRect X1 Coordinate Left All 11 00 12 bits are implemented in the Intel 815 chipset Reserved Must be Zero 23 00 00 23 00 Setup Background Color All Reserved Must be Zero 23 00 00 23 00 Setup Foreground Color SLB amp TB only 7 BRO7 31 00 Pattern Address for Color Pattern 25 06 are implemented in Intel 810 chipset SLB only 165 Intel 815 Chipset Gra
373. rea to the start of the vertical sync pulse Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical sync pulse begins 114 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Vertical Display Enable End Bit 9 The vertical display enable end is a 10 bit or 12 bit value that specifies the number of the last scan line within the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical display enable end is specified with a 10 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Display Enable End Register CR12 and the most and second most significant bits are supplied by this bit and bit 1 respectively of this register In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical display enable end is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Display Enable End Register CR12 and the 4 most significant bits are supplied by bits 3 0 of the Extended Vertical Display End Enable Register CR31 In extended modes neither this bit nor bit 1 of this register are used This 10 bit or 12 bit value should be programmed to be equal to the number of the last scan line within in the active display area Since the active display ar
374. ring standard VGA odd even modes modes Oh through 5h Bit 1 of register GRO6 can also program this bit in other modes Note that this bit is always set to 1 by the driver software Clock Select These bits usually select the dot clock source for the CRT interface The bits select the dot clock in standard VGA modes 00 CLKO 25 MHz for standard VGA modes with 640 pixel horizontal resolution default 01 CLK1 28 MHz for standard VGA modes with 720 pixel horizontal resolution 1x CLK2 left reserved in standard VGA used for all extended modes 6 MHz 135 MHz A0000 BFFFFh Access Enable VGA Compatibility bit enables access to local video memory frame buffer at AQOOO BFFFFh When disabled accesses to system memory are blocked in this region by not asserting DEVSEL This bit does not block processor access to the video linear frame buffer at other addresses 0 Prevent processor access to frame buffer default 1 Allow processor access to frame buffer I O Address Select This bit selects 3Bxh or 3Dxh as the I O address for the CRT Controller registers the Feature Control Register FCR and Input Status Register 1 ST01 Presently ignored whole range is claimed but will ignore 3Bx for color configuration or 3Dx for monochrome 0 Select 3Bxh I O address MDA emulation default 1 Select 3Dxh I O address CGA emulation 1 In standard VGA modes bits 7 and 6 indicate which of the three standard V
375. ro 07 05 Pattern Vertical Alignment which scan line of the 8x8 pattern to start on 04 00 Dword Length 0Ah 182 Intel 815 Chipset Graphics Controller PRM Rev 1 0 DWord Bit Description Solid Pattern Select 1 solid pattern 0 no solid pattern Reserved Must be Zero Mono Source Transparency Mode 1 transparency enabled 0 use background Mono Pattern Transparency Mode 1 transparency enabled 0 use background Reserved Must be Zero Must Be One 1 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved 23 16 Raster Operation 15 00 Destination Pitch signed 13 00 are implemented in Intel 810 chipset 2 BR14 31 16 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BROY 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset 4 BR11 Number of Monochrome Source Quadwords 1 1 to 64k Quadwords 64 to 4M bits Reserved Must be Zero 6 BR18 23 00 Source Background Color Reserved Must be Zero 7 BR19 23 00 Source Foreground Color Reserved Must be Zero 8 BR16 23 00 Pattern Background Color Reserved Must be Zero 9 BR17 23 00 Pattern Foreground Color 183 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 12 3 1 184 intel BLT Engine Instruction
376. rrupt Control Status Registers This register set provides interrupt control status for various GC functions Display Interface Control Register This register controls the FIFO watermark and provides burst length control Local Memory Registers 03000h 03FFFh These registers are located in main memory space and provide local memory DRAM control Reserved 04000h 04FFFh Miscellaneous I O Control Registers 05000h O05FFFh This chapter provides miscellaneous I O control register functions Clock Control Registers 06000h 06FFFh This memory address space is the location of the GC clock control and power management registers Reserved 07000h 0FFFFh Page Table Range 10000h 1FFFFh Reserved 20000h 2FFFFh Overlay Registers 30000h 3FFFFh These registers provide control of the GC overlay engine The overlay registers are double buffered with one register buffer located in graphics memory and the other on the GC chip On chip registers are not directly writeable To update the on chip registers software writes to the register buffer area in graphics memory and instructs the GC to update the on chip registers Blitter Status Registers 40000h 4FFFFh For debug purposes only a set of read only registers provide visibility into the BLT engine status Reserved 50000h 5FFFFh Reserved in the Intel 815 chipset LCD TV Out Registers 60000h 6FFFFh This memory address range is used for LCD TV Ou
377. rrupt Ring 318 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 1 17 MEM_MODE Memory Interface Mode Register debug Address Offset 020DCh Default Value 00000000h Access Read Write Size 32 bits 15 8 Reserved Other Local Cache Host Reserved Reserved Graphics Enable Modes Graphics Address Instruction Prefetch Translatio FIFO Enable n Mode Debug Pg Tbl Mode test mode Description Reserved Host Graphics Prefetch Mode 0 Enable 1 Disable Reserved Reserved MUST BE SET TO 1 Graphics Address Translation Mode 0 Graphics Address translated through page table Page Table test mode 1 Graphics address Physical address in Local memory Not supported in the GMCH Instruction FIFO Debug Mode 0 Disable 1 Enable 319 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 2 Interrupt Control Registers The interrupt control registers described below all share the same bit definition The bit definition is as follows 14 13 10 8 HW Reserved Pri Dply Reserved Overlay 0 Rsvd Detect Flip Flip Error Pending Pending Master 6 5 4 3 2 0 Pri Dply Pri Dply Reserved Reserved Reserved Reserved User Breakpoint VBLANK Event Defined Interrupt Table 17 Bit Definition For Interrupt Control Registers Description 15 Hardware Detected Error Master When this status bit is set it indicates that the hardware has detected an error Set on an error condition and
378. rs This section provides a high level register map register groupings per function The memory and I O maps for the GC registers are shown in the following figure The VGA and Extended VGA registers can be accessed via standard VGA I O locations as well as via memory mapped locations In addition the memory map contains allocation ranges for various functions The memory space address listed for each register is an offset from the base memory address programmed into the MMADR register PCI configuration offset 14h Figure 7 Graphics Controller Register Memory and I O Map Memory Space Map Offset From 512 KB allocation Base_Reg Cursor Registers 7FFFFh Display Registers Pixel Pipe Registers 70000h 6FFFFh TVout Registers Misc Multimedia Registers 60000h SFFFFh Reserved 50000h AFFFFh Bit Engine Control Status RO 40000h 3FFFFh Overlay Registdrs 30000h 2FFFFh Reserved Note 20000h 1 Some Overlay registers are 1FFFFh double buffered with an additional address range in graphics memory See Overlay Page Table Range Register Chapter for details 10000h OFFFFh Reserved 07000h O6FFFh Clock Control Registers 06000h OSFFFh Misc I O Control Registers 05000h O4FFFh Test amp Diagnostic Registers 04000h O3FFFh Local Memory Interface Control Registers 03000h vos M Instruction Control Regs aa pacs map Fence Table Registers Standard graphi
379. rs are written to and read from together when accessed from the PCI The GAMCxx registers are not double buffered and should only be updated when the Overlay Engine is disabled During operation the bytes of these registers are read independently These registers are dependent on the R G or B pixel values There are several restrictions when using gamma values The restrictions are e Gamma curve should be always a rising curve e GAMCO cannot have value of 0 e Difference between the two adjacent gamma registers cannot be greater than 0x7F 31 24 23 16 15 8 7 0 Cee Paste eee o Ce fem o 7 0 Used of bit lt 7 6 gt 11 Used of bits lt 7 6 gt 10 Used of bits lt 7 6 gt 01 Used of bits lt 7 5 gt 001 Used of bits lt 7 4 gt 0001 Used of bits lt 7 3 gt 00001 Figure 41 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Mathematical Gamma Correction For Overlay Gamma correction is a function that corrects for non linearity between display phosphor brightness as a function of electron beam current Depending on the actual phosphor used and or whether the event that data streams have been pre gamma corrected for different phosphor characteristics than the display device being used the digital display stream must be corrected to achieve equally spaced increase in brightness on the display for equally spaced increases in color intensity values Gamma correction shall be chiefly implemented via a pi
380. rt Argument Color Arg2 Mask 0 Do not update 1 Update Ee 10 8 Color Arg2 Valid values are Oh All Ones 1h Color Factor 2h Accumulator Color illegal setting for stage 0 3h Iterated Color 4h Specular Color 5h Current Color 6h TexelO Color 7h Texel1 Color Replicate Arg2 Alpha to Color Channels 0 Do not Replicate Alpha to Color Channels 1 Replicate Alpha to Color Channels 228 Dword 0 Intel 815 Chipset Graphics Controller PRM Rev 1 0 es Invert Color Arg2 0 Do not Invert Argument 1 Invert Argument Color Operation Mask 0 Do not update 1 Update Color Operation Valid values are 00h The user must explicitly disable each blend stage that is not used Note The user must ensure that if a blend stage is disabled all higher number blend stages must be disabled too E g It is invalid to disable stage 2 and use only stages 1 and 3 This bit disables enables both the color and the corresponding alpha stage 01h Select Arg1 02h Select Arg2 03h Modulate 04h Modulate and Multiply by 2 05h Modulate and Multiply by 4 06h Add 07h Add Signed 08h Linearly Blend using the Iterated Alpha as the Blend Term 09h Reserved OAh Linearly Blend using the Alpha Factor as the Blend Term OBh Reserved Linearly Blend when a pre multiplied map alpha is present OCh Reserved Pre modulate OCh Reserved Bump Environment Map ODh Reserved Bump pre m
381. ructions past the Head Offset As the GC does not reset the Head Offset when an RB is enabled software must program the Head Offset field before enabling the Ring Buffer Although this allows software to enable an RB with any valid values for Head Tail i e can enable or re enable the RB with instructions already pending it is anticipated that software will initialize the Head Offset to 0 Once the Head Offset reaches the Tail Offset Head Tail the IP considers the RB empty 144 intel Table 12 10 4 4 2 10 4 4 3 Intel 815 Chipset Graphics Controller PRM Rev 1 0 e Head Wrap Count This field is incremented by the IP every time the Head Offset wraps back to the start of the buffer As it is included in the DWord written in the report head process software can use this field to track IP progress as if the RB had a virtual length of 2048 times the size of the actual physical buffer e Tail Offset This is the QWord offset from Start Address where software will write the next instruction After writing instructions into the RB software updates the Tail Offset field in order to submit the instructions for execution by setting it to the QWord offset immediately following the last instruction to be submitted The instructions submitted can wrap from the end of the buffer back to the top in which case the Tail Offset written will be less than the previous value Note that since the RB empty condition is defined as He
382. s Starting Row Scan Count This field provides all 5 bits of a 5 bit value that specifies the number of scan lines in a horizontal row of text This value should be programmed to be equal to the number of scan lines in a horizontal row of text minus 1 118 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 12 CROA Text Cursor Start Register I O and Memory Offset Address 3B5h 3D5h index 0Ah Default O0UU UUUUb U Undefined Attributes Read Write This cursor is the text cursor that is part of the VGA standard and should not be confused with the hardware cursor and popup a k a cursor and cursor 2 which are intended to be used in graphics modes This text cursor exists only in text modes and thus this register is entirely ignored in graphics modes Reserved 00 Text Text Cursor Start Cursor Off Reserved Read as Os 5 Text Cursor Off 0 Enables the text cursor 1 Disables the text cursor Text Cursor Start This field specifies which horizontal line of pixels in a character box is to be used to display the first horizontal line of the cursor in text mode The horizontal lines of pixels in a character box are numbered from top to bottom with the top most line being number 0 The value specified by these 5 bits should be the number of the first horizontal line of pixels on which the cursor is to be shown 9 6 13 _CROB Text Cursor End Register I O and Memory Offset Address 3B5h 3
383. s especially those that ensure that the local memory is idle during the state restore Also much of the work involves reprogramming the registers with the values captured during the save state operation Blank the screen Turn off DRAM refresh Read the value of the DRAM CONTROL HI Register MM 0x3002 Set the DRAM Refresh Rate bits DDR Bits 4 3 to Disable_Refresh value 0 Write the modified value back to the DRAM CONTROL HI Register Write the M N and P i e the Divisor Select value values from the saved state information Restore the 8 bit DAC mode to what it was when the state was saved but preserve the current value of the rest of the register containing this flag Read the Pixel Pipeline Configuration 0 Register Clear the current value of the 8 or 6 bit DAC mode OR in only the value of the DAC 8 BIT from saved register information of the Pixel Pipeline Configuration 0 Register Write the result back to the Pixel Pipeline Configuration 0 Register Restore the generic VGA registers to the values captured at save state time Restore the following registers to their saved state values Vertical Total CRX 30 Vertical Display End CRX 31 Vertical Sync Start CRX 32 Vertical Blank Start CRX 33 Horizontal Total CRX 35 Horizontal Blnk CRX 39 Ext Offset CRX 41 The following registers should restore only certain bits from the saved state values Interlace Contr
384. s and 1 fractional bit Valid values range from 0 0 to 3 5 in 5 increments The default value is 0 2 Feu Shade Mode State Mask 1 Updater 0 Do Norup 8 Fog Shade Mode 1 Flat 0 Gouraud default e Speco shade Mode t Flat 07 Gaueuseeeu 0 2 Cull Mode To support culling of back facing triangles 000 Reserved 001 Cull No Triangle No back face removal 010 Cull CW Triangles Allow CCW triangles 011 Cull CCW Triangles Allow CW triangles 100 Cull Both For performance experiments 101 to 111 Reserved 240 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 13 19 GFXRENDERSTATE_BOOLEAN_ENA_1 Dwor Specular Setup Enable 0 Disable default 1 Enable This SV enables specular gradient calculations in the Setup Unit independent of other specular SVs This bit is currently not used This bit along with it s corresponding mask bit are tied to bits 8 and 9 of this same register 17 Alpha Setup Enable Enable Mask 1 Update 0 Do Not Update Alpha Setup Enable 0 Disable default 1 Enable This SV enables alpha gradient calculations in the Setup Unit independent of other alpha SVs Color Index Key Enable Mask 1 Update 0 Do Not Update Color Index Key Enable 0 Disable default 1 Enable Chromakey Enable Mask 1 Update 0 Do Not Update Chromakey Enable 0 Disable default 1 Enable Source Z Bias Enable Mask 1 Update
385. s mode allows the mapping of the VGA space allocated in main memory non local video memory mode or all of local memory space through the A0000 AFFFF window Using bit 4 of this register which is a 64KB page An internal address is generated using GR11 6 0 as the address line 22 16 extension to A 15 2 0 Disable default 1 Enable 98 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Table 9 VGA Address Range Note 1 Address Range see note 2 A0000 AFFFF Range B0 B8 Ranges No GTT No GTT Std VGA VGA Controller No VGA Controller No xlations Paging Paging Paging and VGA NA xlation not supported No Paging No Bypass VGA No Paging Bypass VGA No Paging VGA xlations Paging No VGA Bypass VGA Paged by Bypass VGA No Paging xlations GR11 No Paging No Bypass VGA No Paging Bypass VGA No Paging VGA xlations Paging No VGA Bypass VGA Paged by Bypass VGA No Paging xlations GR11 No Paging No Bypass VGA No Paging Bypass VGA No Paging VGA xlations Paging No VGA Bypass VGA Paged by Bypass VGA No Paging xlations GR11 NOTES 1 GR10 2 0 must not be programmed to 001 value because the GMCH hardware does not support the paging and VGA translation mode Unpredictable hardware behavior will occur if GR10 2 0 were programmed to 001 value 2 VGA Address Range selected by GRO6 Graphics range selected through Graphics base address register in configuration space Access to V
386. s the use of one set while the second set is being loaded The driver has to ensure that the pipeline is flushed before it changes the USE address The LOAD address does not have the same restriction Only YUV data is supported in Context 1 RGB is not supported Powe ee ee 31 29 Client 000 Instruction Parser 28 23 Opcode 05h 22 18 Reserved Oh 17 16 15 9 7 1 Load Addr Enable 1 Update Load Addr with the value in the Load Addr field 0 Ignore Load Addr Reserved MBZ Load Addr address of the SV set to be loaded 1 State Variable Set 1 0 State Variable Set 0 Reserved MBZ Use Addr address of the SV set to be used 1 State Variable Set 1 0 State Variable Set 0 Use Addr Enable 1 Update Use Addr with the value in the Use Addr field 0 Ignore Use Addr 156 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 11 2 7 GFXCMDPARSER _DEST_BUFFER_INFO The GFXCMDPARSER DEST_BUFFER_INFO instruction is used to specify the information about the destination buffer This is an immediate instruction and therefore software must ensure that the Rendering Engine and the local cache are flushed prior to modifying the destination buffer information The format is A Client 000 Instruction Parser 28 23 23 28 23 Opcode 15h 6 Reserved 00000h 5 0 DWORD_LENGTH 00h 31 26 26 Reserved Base Address This is the base address of the rendered scene in linear space T
387. s to be protected from IRB instruction execution Another requirement for asynchronous instruction generation arises from competing and asynchronous drivers e g user mode driver libraries In this case the desire is to allow these entities to construct instruction sequences in an asynchronous fashion via batch buffers Synchronization is then only required to dispatch the batch buffers via GFXKCMDPARSER BATCH BUFFER instructions inserted into the LPRB Batch buffers can also be initiated from the IRB though in this case the batch buffer is intended more for performance reasons where pre generated or canned instruction streams can be dispatched without having to copy them into the IRB LPRB batch buffers are considered non interruptible for a number of reasons IP complexity GC context management etc To provide some gross limits on IRB latency batch buffers are interruptible at chain points between the GFXCMDPARSER BATCH_ BUFFER which ends a batch and the start of the new batch Using this mechanism software can segment batched instruction sequences into chains of smaller batches Batch buffers initiated from the IRB cannot by definition be interrupted so chaining them is of limited use Wait Instructions The GFXCMDPARSER_ WAIT EVENT instruction is provided to allow instruction streams to be held pending until an asynchronous event occurs When executed directly from a RB the IP will treat the RB as if it were empty until
388. s written when necessary to avoid source data corruption problems when the source and destination locations overlap The command packets provide the ability to change the point at which the BLT engine begins reading and writing data from the upper left hand corner the usual starting point to one of the other three corners The BLT engine may be set to read data from the source and write it to the destination starting at any of the four corners of the panel Correctly Performed BLT with Overlapping Source and Destination Locations Source Destination Source Destination b_blit3 vsd 55 Intel 815 Chipset Graphics Controller PRM Rev 1 0 56 Figure 11 intel The figure below illustrates how this feature of the BLT engine can be used to perform the same BLT operation as was illustrated in the figure above while avoiding the corruption of source data As shown in the figure below the BLT engine reads the source data and writes the data to the destination starting with the right most pixel of the bottom most line By doing this no pixel existing where the source and destination locations overlap will ever be written to before it is read from by the BLT engine By the time the BLT operation has reached step e where two pixels existing where the source and destination locations overlap are about to be over written the source data for those two pixels has alre
389. seas cade smeadvessed lacus sdiacdiasseladeaevnad aiaa aadi aieea aaar deaa aaa 47 5 6 Saving the Hardware Stale esisissr iniseti rannin T N SN E sens 48 5 7 Restoring the Hardware State ec cceeeeeceeeeeeeeeeeeeeeeeeaeeeeeeaeeeeeeaeeeseenaeeeeeeneeeeseaes 49 Bit Engine Programming idsaucieiszzcstetudsaessnsceaetpacsauetiadsaustphedauetatecedstiacsaustiadtadstphudaustanesecstondacuetney 53 6 1 BLT Engine Programming Considerations eesseeesssesssrrsessnnesennasnnnnassannaannnnaenannaannna 53 6 1 1 When the Source and Destination Locations Overlap c ceeeeees 53 6 2 Basic Graphics Data Considerations ccccccccececceceeeeeeeeeeeaeceeeeeeeseceueaeeeeeeeteeenaees 57 6 2 1 Contiguous vs Discontinuous Graphics Data cceeeeeeeeeeeeetteeeeeenaes 57 Intel 815 Chipset Graphics Controller PRM Rev 1 0 6 2 2 Source Dataset ceed ae aes ee ee es 58 6 2 3 Monochrome Source Data secsi arira aAa E EARE A 59 6 2 4 Pattern Data cnns tenian eia r rS EAA 60 6 2 5 Destination Daen a salt iea tibiae ta cedee belie Rae eh tee eee 62 6 3 BLT Programming Examples ccccccccsesssccetecseccneeesseeeeeeseecetenscecaeeesececeenseceeaeesenentenses 63 6 3 1 Pattern Fill A Very Simple BLT 0 cece eeceeeeeeeneeeeeeeteeeeeteeeeeeeaeeeereneeeen 63 6 3 2 Drawing Characters Using a Font Stored in System Memory n 66 7 initialization Regions a ae les tect uees EEA E E AEEA pene ide cg
390. seeeeeeenteeeeenneeeeettaeeeeeeaes 266 Bit Definition For Interrupt Control Registers cccceeeeeeeeeeesteeeeeesteeeeeenaes 320 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Revision History e Initial Release July 2000 13 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 14 1 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Introduction The Intel 815 chipset is a highly flexible chipset designed to extend from the basic graphics multimedia PC platform up to the mainstream performance desktop platform The chipset consists of an Intel 82815 chipset Graphics and Memory Controller Hub GMCH an I O Controller Hub ICH for the I O subsystem and a Firmware Hub FWH For this chipset the graphics capability resides in the Graphics and Memory Controller Hub GMCH chip The GMCH s Graphics Controller GC contains an extensive set of registers and instructions for configuration 2D 3D and Video systems This document describes the Intel 815 chipset registers instructions and provides detailed bit field descriptions This Programmer s Reference Manual PRM is intended for hardware software and Firmware designers who seek to implement or utilize the graphic functions of the Intel 815 chipset Familiarity with 2D and 3D graphics programming is assumed Terminology Term AGP Mode GPA Card CSI GC GFX Mode GMCH Group
391. served DWord Length 01h e 2 Address DWord aligned The hardware only uses bits 31 2 Reserved MBZ a R 11 2 16 GFXCMDPARSER_STORE_DWORD_INDEX This instruction immediately causes a system write of the data word in the packet to the address which is provided in the Hardware Status Page Address Register at offset specified Note All store DWords will invalidate the host graphics prefetch cache ee 31 29 29 Client 000 Instruction Parser 28 23 Instruction Target 21h Reserved 0000h Dword Length 01h Reserved Dword Offset into a page A 11 2 BE Reserved Co oo omw SSS SS 161 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 11 2 17 GFXCMDPARSER_BATCH_BUFFER 162 The GFXCMDPARSER BATCH_ BUFFER instruction is used to inform the input interface to parse an instruction buffer The address on the instruction buffers is in graphics memory that should translate to a physical address in main memory Note that in case of an AGP device batch buffers can be in AGP memory only The batch buffer instruction packet implements a protection ID The protection ID is recorded as protection state by the parser when it starts a Batch buffer instruction executed from one of the rings Chained Batch buffer instructions cannot change the protection state of the parser If a batch buffer is pushed into the stack at a chain point this state has to be stored as well The protection state modifies the parser be
392. set Address 3BAh 3DAh Default 00h Attributes Read Only The address selection is dependent on CGA or MDA emulation mode as selected via the MSR register 7 6 5 4 3 2 1 0 Reserved Reserved Video Feedback Vertical Reserved 00 Display 0 0 Retrace Enable J o o ooe SOS Reserved as per VGA specification Read as Os Reserved Read as 0 Video Feedback 1 0 These are diagnostic video bits that are selected by the Color Plane Enable Register These bits that are programmably connected to 2 of the 8 color bits sent to the palette Bits 4 and 5 of the Color Plane Enable Register AR12 selects which two of the 8 possible color bits become connected to these 2 bits of this register The current software normally does not use these 2 bits They exist for EGA compatibility the start of the vertical retrace interval This ability to generate interrupts at the start of the vertical retrace interval is a feature that is largely unused by current software Reserved Read as Os Display Enable Output 0 DE inactive Active display area data is being drawn on the display Neither a horizontal retrace interval or a vertical retrace interval is currently taking place 3 Vertical Retrace Video 0 VSYNC inactive Indicates that a vertical retrace interval is not taking place 1 VSYNC active Indicates that a vertical retrace interval is taking place Note Bits 4 and 5 of the Vertical Retrace End Register CR11 can program this
393. signed 12 bit value that specifies the horizontal position of cursor Default is 0 10 0 Cursor X Position Magnitude Bits 10 0 These 11 bits provide the signed 12 bit value that specifies the horizontal position of cursor The sign bit is provided by bit 15 of this register Default is 0 362 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Appendix A Mode Parameters This appendix contains the register programming information on a per mode basis Refer to the appropriate table for the specific values to use in order to correctly program the graphics adapter for the desired mode and frequency combination Programming the graphics adapter with values not included in these tables may damage the adapter and any connected output devices 363 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CRO6 CRO7 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 364 25 25 175 MHz Dot Clock Intel 815 Chipset Graphics Controller PRM Rev
394. sor and only while operating in SMM mode HSEG is a Remap of the AB segment at FEEAO000 FEEBFFFF Both of these areas when enabled are usable as SMM RAM 00 TSEG and HSEG are both Disabled 01 TSEG is Disabled HSEG is Conditionally Enabled 10 TSEG is Enabled as 512 KB and HSEG is Conditionally Enabled 11 TSEG is Enabled as 1 MB and HSEG is Conditionally Enabled Note Non SMM Operations SMM processor accesses and all other access that use these address ranges are forwarded to the hub interface Once D_LCK is set these bits becomes read only HSEG is ONLY enabled if LSMM 00 Lower SMM Select LSMM This field controls the definition of the A amp B segment SMM space 00 AB segment Disabled no one can write to it 01 AB segment Enabled as General System RAM anyone can write to it 10 AB segment Enabled as SMM Code RAM Shadow Only SMM Code Reads can access DRAM in the AB segment processor code reads only SMM Data operations and all Non SMM Operations go to either the internal graphics device or are broadcast on the hub interface 11 AB segment Enabled as SMM RAM All SMM operations to the AB segment are serviced by DRAM all Non SMM Operations go to either the internal Graphics Device or are broadcast on the hub interface processor SMM R W can access SMM space When D_LCK is set bit 3 becomes Read Only and bit 2 is Writable ONLY if bit 3 is a 1 When bit 3 is set only the processor can access it
395. source color key 288 Intel 815 Chipset Graphics Controller PRM Rev 1 0 DCLRKM Destination Color Key Mask Register Memory Address Offset 54h R W On chip Reg Mem Adar Offset 30154h RO debug path Default Value 00h Access see address offset above Size 32 bits Dest Color Dest Always Reserved Destination Color Key mask Key En Const a Const a Blend Blend Enable Enable Destination Color Key Enable 1 destination color key is enabled 0 destination color key is disabled 30 Destination Constant Alpha Blend Enable 1 Enable Constant Alpha Blending between the overlay and the primary display when the Destination Color Key does not match and Destination Color Keying is enabled within the Alpha Blend Window 0 Disable Constant Alpha Blending Always Constant Alpha Blend Enable 1 Enable Constant Alpha Blending within the Alpha Blend Window 0 Disable Constant Alpha Blending 23 0 Destination Color Key Mask 0 Bits that are active participants in the compare 1 Bits that are active participants in the compare A mask of all ones will disable the color key as if all colors match 289 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 9 15 4 9 1 290 intel Overlay Source Color Key Registers There is an overlay source key per overlay stream which is used on a pixel basis The Source comparison occurs after the horizontal zooming but in the YUV formats before the color space
396. st BLT instruction This field is used by the BLT Engine state machine to identify the BLT instruction it is to perform The opcode specifies whether the source and pattern operands are color or monochrome Reserved Must be Zero Monochrome Source Start This field indicates the starting monochrome pixel bit position within a byte per scan line of the source operand The monochrome source is word aligned which means that at the end of the scan line all bits should be discarded until the next word boundary Bit Byte Packed Byte packed is for the Windows NT driver 0 Bit 1 Byte Intel 815 Chipset Graphics Controller PRM Rev 1 0 Descriptions Bit Destination Transparency Mode These bits control whether or not the byte s at the destination corresponding to a given pixel will be conditionally written and what those conditions are This feature can make it possible to perform various masking functions in order to selectively write or preserve graphics data already at the destination All four of the sets of conditions that may be chosen as the controlling factor in performing color transparency involve comparing the color that has been specified to be used in the color expansion of any monochrome source data to other colors This background color is in the Source Expansion Background Color Register XX0 No color transparency mode enabled This causes normal operation with regard to writing data to the destination 001
397. ster The first byte read from the Palette Data Register retrieves the 8 bit value specifying the intensity of the red color component while the second and third bytes read are the corresponding 8 bit values for the green and blue color components respectively After completing the third read operation the Palette Read Index Register is automatically incremented so that the data of the next color data position becomes accessible for being read This allows the contents of all 256 color data positions of the palette to be read by specifying only the index of the Oth color data position in the Palette Read Index Register and then simply performing 768 successive reads from the Palette Data Register Writing a color data position entails a very similar procedure The index of the desired color data position must first be written to the Palette Write Index Register Then all three bytes of data to specify a given color may be written to the Palette Data Register The first byte written to the Palette Data Register specifies the intensity of the red color component the second byte specifies the intensity for the green color component and the third byte specifies the same for the blue color component One important detail is that all three of these bytes must be written before the hardware will actually update these three values in the given color data position When all three bytes have been written the Palette Write Index Register is automatically increment
398. ster at a given bit position causes the bits in the corresponding bit positions in the addressed byte in all 4 memory planes to be written with the 4 bits taken from the processor write data to thereby cause the pixel corresponding to these bits to be set to the color value 11 Write Mode 3 During a processor write to the frame buffer the processor write data is logically ANDed with the contents of the Bit Mask Register GR08 The result of this ANDing is treated as the bit mask used in writing the contents of the Set Reset Register GROO are written to addressed byte in all 4 memory planes 95 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 3 8 GRO06 Miscellaneous Register I O and Memory Offset Address 3CFh Index 06h Default OUh U Undefined Attributes Read Write Reserved 0000 Memory Map Mode Chain Graphics Odd Even Text Mode a ed Reserved Read as Os Memory Map Mode These 2 bits control the mapping of the frame buffer into the processor address space as follows Bit 3 2 Frame Buffer Address Range 00 A0000h BFFFFh 01 A0000h AFFFFh 10 B0000h B7FFFh 11 B8000h BFFFFh Notes 1 This function is both in standard VGA modes and in extended modes that do not provide linear frame buffer access 2 Software must set to the proper value Chain Odd Even This bit provides the ability to alter the interpretation of address bit AO so that it may be used in selecting between t
399. supports perspective correct texture mapping trilinear and anisotropic Mip Map filtering Gouraud shading alpha blending fogging and Z buffering A rich set of 3D instructions permit these features to be independently enabled or disabled For the GMCH a Display Cache DC can be used for the Z buffer textures and display buffer s are located only in system memory If the display cache is not used the Z buffer is located in system memory The GMCH integrated graphics accelerator s 2D capabilities include BLT and arithmetic STRBLT engines a hardware cursor and an extensive set of 2D registers and instructions The high performance 64 bit BitBLT engine provides hardware acceleration for many common Windows operations In addition to its 2D 3D capabilities the GMCH integrated graphics accelerator also supports full MPEG 2 motion compensation for software assisted DVD video playback a VESA DDC2B compliant display interface and a digital video out port which may support via an external video encoder NTSC and PAL broadcast standards and via an external TMDS transmitter digital Flat Panel or Digital CRT displays Display Digital Video Out and LCD Flat Panel Digital CRT The GMCH provides interfaces to a standard progressive scan monitor TV Out device and TMDS transmitter These interfaces are only active when running in internal graphics mode e The GMCH directly drives a standard progressive scan monitor up to a resolution of 1600x12
400. t 02080h Default Value 1FFFFOOOh Access Read Write Size 32 bits Hardware status page physical address The programmed address should be 4 KB aligned Bits 11 0 are hardwired to 0 This Page will be used to report hardware status into system memory as follows For the GMCH bits 31 29 must be 0 31 29 28 12 11 0 Must be Os Base Physical Address of Status Os hardwired Page 28 12 Report Interrupt Status Register Report Low Priority Ring Head Pointer ooe Can be Written through indexed store DWord instruction Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 1 7 _IPEIR Instruction Parser Error Identification Register debug Address Offset 02088h Default Value 0000h Access Read Only Size 32 bits This register is used to help identify the instruction packet that generates an invalid instruction interrupt to the processor The IPEIR will contain the origin of the offending packet The Header will be stored in the error header register 2 31 3 1 0 Reserved BATCH RING ID RING Lae 2 BATCH RING The invalid instruction came from either a batch buffer or instruction ring 1 Batch buffer 0 Instruction RING RING ID The invalid instruction came from the Low Priority 00 or the Interrupt 01 ring If the invalid instruction came from a batch buffer this bit identifies which Instruction Ring the batch buffer instruction came from 00 Low Priority 01 Intr ring 1X
401. t control registers Cursor Display and Pixel Pipe Registers 70000h 7FFFFh This memory address range is used for cursor control display and pixel pipe control registers 31 Intel 815 Chipset Graphics Controller PRM Rev 1 0 3 2 GC Register Memory Address Map All GC registers are memory mapped In addition the VGA and Extended VGA registers are I O mapped Table 2 Memory Mapped Registers Address Offset Symbol Register Name Access 00000h 00FFFh VGA and VGA Extended Registers These registers are both memory and I O mapped and are listed in the following table Note that the I O address and memory offset address are the same value for each register Instruction and Interrupt Control Registers 01000h 02FFFh 01000h 01FFFh Reserved Do not write 02000h 0201Fh FENCE 0 7 Graphics Memory Fence Table Register 0 7 R W 02020h 02023h PGTBL_CTL Page Table Control Register R W 02024h 02027h PGTBL_ER Page Table Error Register 02028h 0202Bh PGTBL_ERRMSK Page Table Error Mask Register R W 02030h 0207Fh RINGBUF Ring Buffer Registers R W 02030h 0203Fh Low Priority Ring Buffer 4 DWs 02040h 0204Fh Interrupt Ring Buffer 4 DWs 02050h 0207Fh Reserved HWS PGA RA HWSTAN RW R RWC RW RWG R ER MR SR EIR EMR ESR 32 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel Table 2 Memory Mapped Registers Address Offset Symbol Register Name Access Memory Control Registers 03
402. t be Xmax gt Xmin and Yinax gt Yimin e Drawing Rectangle width and height must be greater than 1 pixel for Rectangle primitives e Drawing Rectangle X amp Y coordinates must be within the screen size The drawing rectangle must be clipped to screen coordinates before send to hardware However the origin of the drawing rectangle can be negative since it is need not be clipped It is the reference point origin of all the primitives and scissor rectangle that belong to the drawing rectangle Xmin Ymin 0 0 Origin of Screen ee ees Scissor Xmax Ymax scissor vsd Small Triangle Filter e Small Triangle Filter can only be enabled if the horizontal and vertical bias values defined in Dest Buffer variable packet are programmed to 0000 0000 or 1000 1000 This is corresponds to the pixel center of 0 0 and 0 5 0 5 respectively Mapping Engine Cache MEC e A Texture palette load must contain all 256 entries Even if only one entry needs to be updated all 256 entries in the Texture palette must be loaded using the texture palette load packet e Color Key and Chroma Key cannot be enabled at the same time e In mult texture Colorkey and Chromkey only compare with Map 0 texels and not on Map 1 texels e Any programming change made to the Mapping Engine Cache Enable state variable must be followed by a 3D pipeline flush otherwise pixel corruption will occur For example software cha
403. t before RGB conversion Bypassing Brightness even for RGB is accomplished by programming this field to 0 OVOCLRC1 Overlay 0 Color Correction 1 Register Memory Address Offset 4Ch R W On chip Reg Mem Addr Offset 3014Ch RO debug path Default Value 00h Access see address offset above Size 32 bits 31 10 9 0 Reserved Saturation CrCb i This unsigned fixed point number is in 3 7 format Saturation CrCb This operates in two modes When YUV data is being operated on the register contains the saturation value When CbCr data is being used it is the sum of the saturation multiplier value added to the CbCr scale factor 128 112 Bypassing Saturation even for RGB is accomplished by programming this field to 1 0 287 Intel 815 Chipset Graphics Controller PRM Rev 1 0 15 4 8 Overlay Destination Color Key Registers Used for YUV sources only Adjustments are made before the RGB conversion 15 4 8 1 _DCLRKV Destination Color Key Value Register Memory Address Offset 50h R W On chip Reg Mem Addr Offset 30150h RO debug path Default Value 00h Access see address offset above Size 32 bits 31 24 23 0 Destination Color Key Value i 23 0 Destination Color Key Value In the format of the destination screen This can only be used when the screen is used as the destination not TV When the overlay is directed to TV output this value replaces pixels that have been suppressed by the
404. t bit and bits 7 0 of the Line Compare Register CR18 supply the 8 least significant bits Normally this 10 bit value is set to specify a scan line after the last scan line of the active display area When this 10 bit value is set to specify a scan line within the active display area it causes that scan line and all subsequent scan lines in the active display area to display video data starting at the very first byte of the frame buffer The result is what appears to be a screen split into a top and bottom part with the image in the top part being repeated in the bottom part When used in cooperation with the Start Address High Register CROC and the Start Address Low Register CROD it is possible to create a split display as described earlier but with the top and bottom parts displaying different data The top part will display what data exists in the frame buffer starting at the address specified in the two aforementioned start address registers while the bottom part will display what data exists in the frame buffer starting at the first byte of the frame buffer 115 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Vertical Blanking Start Bit 8 The vertical blanking start is a 10 bit or 12 bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the vertical b
405. t position within the first byte should be used as the first source pixel The destination pitch can be either sign to allow vertical mirroring of a monochrome source with a pattern which is accessed in the same direction as the destination operand Intel 815 Chipset Graphics Controller PRM Rev 1 0 C OE A E 0 BROO 3129 29 Client 02h 2D Processor i 02h 2D Processor Monochrome source data bit position of the first pixel within a byte per scan line Mono Source Transparency Mode 1 transparency enabled 0 use background Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved 23 16 Raster operation 15 00 Destination Pitch signed 13 00 are implemented in Intel 810 chipset 2 BR14 31 16 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BROY 31 00 Destination Address Address of the first byte to be written ae are implemented in Intel 810 chipset 4 BR11 Number of Monochrome Source Quadwords 1 1 to 64k Quadwords 64 to 4M bits 5 BR12 31 00 Source Address address of the first byte of the first pixel on the first scan line 25 00 are implemented in Intel 810 chipset Reserved Must be Zero 6 BR18 Source Background Color 31 24 Reserved Must be Zero 7 BR19 23 00 Source Foreground Color 8 BR15 31 00 Pattern Address 25 06 are implem
406. t the number of character clocks are required to cause the memory address counter to be incremented as shown below CR14 5 CR17 3 Address Incrementing Interval 0 every character clock every 2 character clocks every 4 character clocks every 2 character clocks Underline Location This field specifies which horizontal line of pixels in a character box is to be used to display a character underline in text mode The horizontal lines of pixels in a character box are numbered from top to bottom with the top most line being number 0 The value specified by these 5 bits should be the number of the horizontal line on which the character underline mark is to be shown 5 Count By 4 0 The memory address counter is incremented either every character clock or every other character 125 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 23 CR15 Vertical Blanking Start Register I O and Memory Offset Address 3B5h 3D5h index 15h Default Undefined Attributes Read Write en Vertical Blanking Start Bits 7 0 This register provides the 8 least significant bits of either a 10 bit or 12 bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area of the screen Whether this value is described in 10 or 12 bits depends on the setting of bit O of the I O Control Register CR80 In standard VGA modes where bit 0 of the I O Control Register CR80 is set to 0 the verti
407. t update 1 Update Reserved 00h Mag Mode Filter Valid values are 0 Nearest 1 Linear Min Mode Filter Mask 0 Do not update 1 Update Reserved 00h Min Mode Filter Valid values are 0 Nearest 1 Linear 223 Intel 815 Chipset Graphics Controller PRM Rev 1 0 13 9 GFXRENDERSTATE_MAP_LOD_LIMITS The limits of the Level of Detail calculation can be controlled within GC for each Map These values are specified in the following instruction as follows Figure 36 State Variable Relationships Coordinate Sets _ Map Information Texels Blending Stages i 31 29 Client 03h Rendering Engine 28 24 3DState16 1Ch 23 19 Opcode 3h Update Map Index The valid range is 0 1 1 Maximum Mip Level Mask 0 Do not update 1 Update map selection Values 1 through 10 will force the mip map selection to be between the specified value and the highest defined mip map the lowest resolution map This value must be less than the Minimum Mip Level 12 5 Maximum Mip Level This is an unsigned 4 4 bit value which defines the highest resolution map which may be accessed A value of 0 equates to no limit on the mip Minimum Mip Level Mask 0 Do not update 1 Update 3 18 17 Reserved 00h Additional Maps 6 15 14 Reserved 00h 3 0 Minimum Mip Level This is an unsigned 4 bit value which defines the lowest resolutio
408. tart to force the loading of the next Overlay x Register Update Address which will take effect after the next displayed overlay frame 265 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Table 16 Overlay Register Instruction Categories Register Instruction Category Mem Address Offset Comment Overlay 0 Register Update Address 30000h e Used to update Overlay 0 registers OVOADD A e Provides physical memory address of buffer area used for updating on chip registers e Write of OVOADD register causes hardware to update on chip registers on next VBLANK Display Overlay 0 Status Register 30008h e Overlay Status bits DOVOSTA Gamma Correction GAMMA 0 5 30010h 30027h e Not part of double buffer scheme Access registers directly Overlay Register Sets 301xxh e xx indicates a particular register address on chip RO regs e Overlay Buffer Pointer p gs e On chip registers are not directly writeable Registers are double buffered buffer in memory and on chip registers e Overlay Stride Baset xxh e Overlay Initial Phase Mem Buffer regs Software sets up buffer in memory Overlay Source Size Software writes to OVOADD Register which provides memory buffer address location and causes hardware Overlay Color Correction to read memory buffer and update on chip registers during next VBLANK Overlay Dest Window Position Size Overlay Scale Factor Overlay Destination Color Key e On chip r
409. te Index The 8 bit index value programmed into this register chooses which of 256 standard color data positions within the palette or which of 8 alternate color data positions depending on the state of a bit in the Pixel Pipeline Control 0 Register are to be made accessible for being written via the Palette Data Register DACDATA The index value held in this register is automatically incremented when all three bytes of the color data position selected by the current index have been written 108 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 5 5 DACDATA Palette Data Register I O and Memory Offset Address 3C9h Default Undefined Attributes Read Write Palette Data This byte wide data port provides read or write access to the three bytes of data of each color data position selected using the Palette Read Index Register DACRX or the Palette Write Index Register DACWX The three bytes in each color data position are read or written in three successive read or write operations The first byte read or written specifies the intensity of the red component of the color specified in the selected color data position The second byte is for the green component and the third byte is for the blue component When writing data to a color data position all three bytes must be written before the hardware will actually update the three bytes of the selected color data position When reading or writing to a color data posit
410. ted through Clip rectangle Y addresses and X coordinates along with scan line starting and ending addresses along with X starting and ending coordinates Pattern Data The color pattern data must exist within the frame buffer or Main memory graphics memory where the BLT engine may read it directly Monochrome pattern data is supplied by the command packet when it is to be used As shown in figure below the block of pattern graphics data always represents a block of 8x8 pixels The bits or bytes of a block of pattern data may be organized in the frame buffer memory in only one of four ways depending upon its color depth which may be 8 16 24 or 32 bits per pixel whichever matches the color depth to which the BLT engine has been set or monochrome Pattern Data Always an 8x8 Array of Pixels Pixel 0 Q Pixel 7 0 LT Tt tT tty LT tT tty ty LT TTT ttt LTT TTT Ty Pixel 0 AE Pixel 7 7 b_blIt7 vsd 63 57 56 48 47 40 39 32 31 24 23 16 15 87 o Pixel 7 0 b_blt8 vsd The Pattern Address Register is used to specify the address of the color pattern data at which the block of pattern data begins The three least significant bits of the address written to this register are ignored because the address must be in terms of quadwords This is because the pattern must always be located on an address boundary equal to its size Monochrome patterns take up 8 bytes or a single quadword of space and are
411. tel Intel 815 Chipset Graphics Controller Programmer s Reference Manual PRM July 2000 Order Number 298237 001 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your l
412. ten to these bits should be set to 0 oo Extended Horizontal Total MSB that extends CR00 9 6 34 CR39 Extended Horizontal Blank Time Register I O and Memory Offset Address 3B5h 3D5h index 39h Default 00h Attributes Read Write 7 1 0 Reserved 0000000 Total eit Description oo Extended Horizontal Total MSB that extends CR5 7 CR3 4 0 136 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 35 CR40 Extended Start Address Register I O and Memory Offset Address 3B5h 3D5h index 40h Default 00h Attributes Read Write Start Addr Reserved Start Address Bits 23 18 Enable 0 Se Extended Mode Start Address Enable This bit is used only in extended modes where bit 0 of the I O Control Register CR80 is set to 1 to signal the graphics controller to update the start address In extended modes the start address is specified with a 30 bit value These 30 bits which are provided by the Start Address Low Register CROD the Start Address High Register CROC the Extended Start Address High Register CR42 and bits 5 0 of this register are double buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of changes in the start address always have a smooth or instantaneous appearance To change the start address in extended modes all three registers must be set for the new value and then this bit of this register must be set to 1 Only if this
413. tern Fill BLT 0 767 128 128 128 191 191 191 Note Drawing is not to scale 128 128 191 128 e 128 191 191 191 20080 20088h 20090h On 20098h 128th 200A0h Scan 200A8h Line 200BOh 200B8h 2FC80 2FC88h 2FC90h On 2FC98h 191th 2FCAOh Scan 2FCA8h Line 2FCBOh 2FCB8 b_blt21 vsc The figure above shows the end result of performing this BLT operation The 8x8 pattern has been repeatedly copied tiled into the entire 64x64 area at the destination 65 Intel 815 Chipset Graphics Controller PRM Rev 1 0 6 3 2 66 intel Drawing Characters Using a Font Stored in System Memory In this example BLT operation a lowercase letter f is to be drawn in black on a display with a gray background The resolution of the display is 1024x768 and the graphics system has been set to a color depth of 8 bits per pixel On Screen Destination for Example Character Drawing BLT 0 0 1023 0 Note Drawing is not to scale Scan Lines 128 Through 185 128 128 Destination I i Sooo oo oo I I 135 135 0 767 1023 767 128 128 63 0 20080h a 128th Scan Lin 20480h petits 129th Scan Lin 20880h L 130th Scan Lin 20C80h LDL _ 131th Scan Lin 21080h LD _ 132nd Scan Lir 21480h LDL _ 133rd Scan Lin 21880h
414. ters for Screen Resolution Refresh Rate 1280x960_85Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed MSR Mask 408 OxA7 OxAO Intel 815 Chipset Graphics Controller PRM Rev 1 0 CR04 0xA5 CR13 0xA0 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at 133 MHz local memory speed Watermark for 16 bpp at 133 MHz local memory speed Watermark for 24 bpp at 133 MHz local memory speed 409 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Parameters for Screen Resolution Refresh Rate 1280x1024 70Hz Dot Clock Value M Value N Value P Value CROO CR01 CR02 CR03 CR04 CRO5 CROG CR07 CRO9 CR10 CR11 CR12 CR13 CR15 CR16 CR30 CR31 CR32 CR33 CR35 CR39 Watermark for 8 bpp at 100 MHz local memory speed Watermark for 16 bpp at 100 MHz local memory speed Watermark for 24 bpp at 100 MHz local memory speed Watermark for 8 bpp at
415. ters occupy the address range specified above Each Fence Table Register has the following format Note that X and Y major tiles are used for Host texture and Blitter source and destination surfaces Display Overlay motion comp source dest surfaces color and Z surfaces if tiled must be X major 31 26 25 19 Reserved Fence Lower Bound Reserved 15 14 13 12 11 10 6 4 3 1 Reserved Fence Pitch Reserved Fence Valid O ih i ah 301 Intel 815 Chipset Graphics Controller PRM Rev 1 0 302 es Tile walk 0 X Major 1 Y Major 10 8 Fence size 000 512 KB 001 1 MB 010 2 MB 011 4 MB 100 8 MB 101 16 MB 110 32 MB 111 Reserved Fence Pitch 000 1 Tile 001 2 Tiles 010 4 Tiles 011 8 Tiles 100 16 Tiles 101 32 Tiles 110 Reserved 111 Reserved Fence Valid 0 Unused 1 Valid Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 1 2 PGTBL_CTL Page Table Control Register Address Offset 02020h Default Value 00000000h Access Read Write Size 32 bits This register enables disables the page table mechanism and when enabled also sets the base address of the 4 KB aligned page table The driver will write this register when it creates the page table at the start of virtual mode A 64 KB physical contiguous region in memory mapped space will be re mapped to the page table located in local memory Driver writes to this memory mapped space
416. th the coordinate and solid pattern supplied for each pixel to be written No non solid patterns nor source operands are allowed 2 SCANLINE BLT SLB 1 scan line of color or mono pattern and destination are the only operands allowed 3 TEXT BLT TB linear monochrome source either through the instruction stream or from graphics memory not cacheable and destination are the only operands allowed Source copy is the only supported operation The raster operation field must CCh Clipping addresses and coordinates are inclusive The BLT Engine performs a trivial reject for all 3 BLT instructions listed above before performing any accesses If any pixels are included within the clipping rectangle then it performs every access but deasserts the byte enables for the pixels that are clipped The source operand TEXT_BLT only never overlaps with the destination Therefore X and Y direction is always positive left to right and top to bottom Only a positive destination pitch is allowed All fields above indicate which instructions require valid state These are the only instructions that require that state be saved between instructions There are 4 dedicated registers to contain the state for these 3 instructions All other BLTs use a temporary version of these The 4 double word registers are DWI Control DW5 Foreground color DW6 Background color and DW7 Pattern address The ClipRect registers do not need to be saved since they a
417. that were written to be internally latched and become active on the next VBLANK event Vertical Chrom Filter Vertical Luminance Filter 23 22 21 19 18 17 16 Horiz Chrom Filter Horizontal Luminance Filter Mirroring Y Adj cont 15 14 13 10 9 8 4 2 2 Byte Order Source Format Flip TV Flip Qual Out Field 8 7 Sel Flip Qual Vert Initial Disp Flip Ignore Buf Reserved Buffer and Field Overlay Cont Phase Sel Type and Field Enable 294 Intel 815 Chipset Graphics Controller PRM Rev 1 0 os Select top overlay Reserved for future implemenations Vertical Chrominance Filter Vertical Chrominance Filter 000 Scaling off 1 1 001 Line Replication 010 Up Interpolation 011 Reserved 100 Reserved 101 Pixel Dropping 110 Down Interpolation 111 Reserved Vertical Luminance Filter Vertical Luminance Filter 000 Scaling off 1 1 001 Line Replication 010 Up Interpolation 011 Reserved 100 Reserved 101 Pixel Dropping 110 Down Interpolation 111 Reserved Horizontal Chrominance Filter Horizontal Chrominance Filter 000 Scaling off 1 1 001 Line Replication 010 Up Interpolation 011 Reserved 100 Reserved 101 Pixel Dropping 110 Down Interpolation 111 Reserved Horizontal Luminance Filter Horizontal Luminance Filter also applies to RGB 000 Scaling off 1 1 001 Line Replication 010 Up Interpolation 011 Reserved 100 Reserved 101 Pixel Dropping 11
418. the Vertical Sync Start Register CR10 and the 2 most significant bits are supplied by bits 7 and 2 of the Overflow Register CRO7 In standard VGA modes these 4 bits of this register are not used In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical display end is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Sync Start Register CR10 and the 4 most significant bits are supplied by these 4 bits of this register This 10 bit or 12 bit value should be programmed to be equal to the number of scan lines from the beginning of the active display area to the start of the vertical sync pulse Since the active display area always starts on the Oth scan line this number should be equal to the number of the scan line on which the vertical sync pulse begins 134 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 9 6 32 CR33 Extended Vertical Blanking Start Register I O and Memory Offset Address 3B5h 3D5h index 33h Default 00h Attributes Read Write 7 4 3 0 Reserved 0000 Vertical Blanking Start Bits 11 8 Reserved Read as Os This field must be Os when this register is written 3 0 Vertical Blanking Start Bits 11 8 The vertical blanking start is a 10 bit or 12 bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area In standard VGA mod
419. the Oth scan line this number should be equal to the total number of scan lines within the active display area minus 1 9 6 21 CR13 Offset Register I O and Memory Offset Address 3B5h 3D5h index 13h Default Undefined Attributes Read Write In High Resolution modes the Start Addresses in CROC CROD CR40 and CR42 must be programmed before CR13 This is not a requirement in VGA mode eT ee Offset Bits 7 0 of a 12 bit value This register provides the 8 least significant bits of a 12 bit value that specifies the number of words or Dwords of frame buffer memory occupied by each horizontal row of characters Whether this value is interpreted as the number of words or Dwords is determined by the settings of the bits in the Clocking Mode Register SRO1 This 12 bit value should be programmed to be equal to either the number of words or Dwords depending on the setting of the SRO1 register of frame buffer memory that is occupied by each horizontal row of characters The companion extended offset register CR41 3 0 specifies the 4 most significant bits of the 12 bit value It is required of software to write both CR41 3 0 and CR13 7 0 to the desired 12 bit offset value for correct hardware operation Where an 8 bit value is desired for example in standard VGA mode software must write 0000 to CR41 3 0 and the desired 8 bit value to CR13 7 0 Note that unlike the operation of the other CRTC extension registers CR80 0
420. the last vertex instruction packet will be used for the triangles in this packet Bias A Z bias value can be included in the vertex instruction packet as a per polygon basis This value is a floating point number that ranges from 1 to 1 The Z bias value is added to the Z value and then clamped to between 0 to before primitive setup calculation In triangle or line primitive type Z bias of the last vertex 3 in triangle 2 in line will be used to add to all the vertices of the primitive and the Z bias value on the other vertices will be ignored In triangle strip and fan the Z bias value on the 3 vertex will be used for the first triangle and the Z bias value on subsequent vertex which defined a triangle will be used for that triangle Primitive Rendering Instruction Format es 31 29 29 Client 03h Client 03h Rendering Engine Engine 28 24 Rendering Primitive 1Fh Reserved 00h 22 18 Primitive Type Oh Triangle or Triangle List 1h Triangle Strip 2h Triangle Strip with Reverse Winding Order 3h Triangle Fan 4h Polygon Triangle Fan with Common Flat Shaded Vtx 5h Line or Line List 6h Line Strip 7h Rectangle or Rectangle List must be axis aligned 8h 1Fh Reserved oo DWord Count T wa _ Primitivefoy vertex o GFXVERTEX fa Primitive 0 Vertex 1 GFXVERTEX Variable N A Primitive n Vertex 2 GFXVERTEX Last DWORD of last vertex of last primitive Refer to GFX VERTEX secti
421. the letter fP will be drawn There is no Source address All scan lines of the glyph are bit packed and the clipping is controlled by the ClipRect registers from the SETUP_BLT command and the Destination Y1 Y2 X1 and X2 registers in the TEXT_BLT command Only the pixels that are within inclusive comparisons the clip rectangle are written to the destination surface The Destination Pitch Register must be programmed with a value equal to the number of bytes in the interval between the first bytes of each adjacent scan line s worth of destination data Since the color depth is 8 bits per pixel and the horizontal resolution of the display is 1024 pixels the value to be programmed into these bits is 400h which is equal to the decimal value of 1024 Since the source data used in this BLT operation is monochrome the BLT engine will not use a byte oriented pitch value for the source data Since the source data is monochrome color expansion is required to convert it to color with a color depth of 8 bits per pixel Since the Setup Pattern Source Expansion Foreground Color Register is selected to specify the foreground color of black to be used in drawing the letter f this register must be programmed with the value for that color With the graphics system set for a color depth of 8 bits per pixel the actual colors are specified in the RAMDAC palette and the 8 bits stored in the frame buffer for each pixel actually specify the index used to s
422. the specific event occurs This will temporarily remove that RB from arbitration Therefore a wait instruction placed in the IRB can allow LPRB activity to start resume even though there may be IRB instructions still pending When executed from a batch buffer the IP will simply wait for the event to occur without performing rearbitration As this basically halts the IP for a length of time the use of wait instructions in batch 147 Intel 815 Chipset Graphics Controller PRM Rev 1 0 10 4 6 3 10 4 6 4 10 4 6 5 148 intel buffers and the impact on latency and performance should be carefully considered by software developers Instruction Arbitration Points The IP performs arbitration for instruction execution at the following points e Continuously when idle i e no pending instructions e Between instructions in the LPRB e After GFXCMDPARSER BATCH_ BUFFER instructions when executed from the LPRB or at the end of an LP batch buffer e Upon execution of a wait instruction in the IRB if a wait is required Software must consider the consequences of the IP redirecting instruction execution at these arbitration points That is software needs to coordinate the use and control of the instruction stream sources such that GC operations proceed in the intended order and with the intended GC state For example software must prevent the case where instructions placed in the IRB interrupt the LP instruction stream and invali
423. tical Bias Pixelization Rule GFXPRIMITIVE 0000 0000 GFXPRIMITIVE 4000 1000 GFXPRIMITIVE GFXPRIMITIVE GFXBLOCK Intel 815 Chipset Graphics Controller PRM Rev 1 0 Eg 12 Small Triangle Filter Enable Mask ia 1 Update 0 Do Not Update Small Triangle Filter Enable If Set then Small Triangles i e triangles which donot cover any pixels and are either vertical or horizontal will be filtered out Note This should be enabled only in GFXPrimitive Mode when Pixelization Rule is enabled and the Horizontal amp Vertical Bias values in the Dest Buffer Packet are both the same and programmed to 1000 or 0000 Pixelization Rule Mask 1 Update 0 Do Not Update Pixelization Rule This bit should be set in GFXPRIMITIVE MODE for following the correct Pixelization Rules Line Strip List Flat Shaded Vertex Select Mask 1 update 0 Do Not Update 7 6 Line Strip List Flat Shaded Vertex Select Oh Vertex 0 1h Vertex 1 2h Reserved 3h Reserved Triangle Fan Flat Shaded Vertex Select Enable Mask 1 update 0 Do Not Update Triangle Fan Flat Shaded Vertex Select Oh Vertex 0 1h Vertex 1 2h Vertex 2 3h Reserved Triangle Strip List Flat Shaded Vertex Select Enable Mask 1 update 0 Do Not Update Triangle Strip List Flat Shaded Vertex Select Oh Vertex 0 1h Vertex 1 2h Vertex 2 3h Reserved 250 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_DEST_BUFFER_
424. tical Size in lines never specifies scan lines off the active display 15 11 Reserved Alpha Blend Horizontal Size Determines where on the display screen coordinates the overlay display are alpha blended Alpha Blend Horizontal Size in pixels never specifies pixels off the active display Client xxh Function Index Instruction Target Register Update Address Do not use the Wait for VBLANK mechanism to force a sequence of overlay flips Use the Wait for Scan Lines mechanism with the scan line set up to be at least 1 scan line after vertical blank start to force the loading of the next Overlay x Register Update Address which will take effect after the next displayed overlay frame For Intel 810 chipset the Overlay Update Address register can be loaded either before or after the Wait for VBLANK primary display VBLANK Future implementations should create a Wait for Overlay Flip Not Pending mechanism if this becomes an issue especially since the Overlay may not use the primary display s timing generator in the future 299 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 300 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 Instruction Memory and Interrupt Control Registers 16 1 Instruction Control Registers 16 1 1 FENCE Graphics Memory Fence Table Registers Address Offset 02000h 0201Fh Default Value 00000000
425. tiguous then an offset equal to the length of a scan line s worth of destination data should be specified intel 6 3 BLT Programming Examples Intel 815 Chipset Graphics Controller PRM Rev 1 0 6 3 1 Pattern Fill A Very Simple BLT In this example a rectangular area on the screen is to be filled with a color pattern stored as pattern data in off screen memory The screen has a resolution of 1024x768 and the graphics system has been set to a color depth of 8 bits per pixel Figure 19 On Screen Destination for Example Pattern Fill BLT C 0 Rectangular i i Area to be Filldd i Destination 0 767 Pa ae a 191 128 Scan Lines 128 Through 191 a 128 191 191 191 Note Drawing is not to scale 20080 20088h 20090h On 20098h 128th 200A0h Scan 200A8h Line 200BOh 200B8h 2FC80I 2FC88h 2FC90h On 2FC98h 191th 2FCAOh Scan 2FCA8h Line 2FCBOh 2FCB8 b_blit20 vsc As shown in the figure above the rectangular area to be filled has its upper left hand corner at coordinates 128 128 and its lower right hand corner at coordinates 191 191 These coordinates define a rectangle covering 64 scan lines each scan line s worth of which is 64 pixels in length in other words an array of 64x64 pixels Presuming that the pixel at coordinates 0 0 corresponds to the byte at address 00h in the frame buffer memory the pixel at 128 128 corresponds to the byte
426. tion where the destination data for the last scan line ended to create a single contiguous block of bytes of destination data at the destination 187 Intel 815 Chipset Graphics Controller PRM Rev 1 0 12 3 3 BRO2 Clip Rectangle Y1 Address Memory Offset Address 40008h Default None Attributes RO DWord accessible BRO2 is loaded by either the SETUP_BLT or SETUP_MONO PATTERN SL _BLT instructions and is used with PIXEL BLT SCANLINE BLT or TEXT BLT instructions 31 26 25 0 Reserved Must Clip Rectangle Y1 Address Bits 25 0 be Zero 31 26 Reserved Must be Zero The maximum GC graphics address is 64 MB 25 0 Clip Rectangle Y1 Address Bits 25 0 These 26 bits specify the top clipping address of the destination data This clip compare is inclusive draw if destination address is greater than or equal to this address This address points to the first address of a scan line The Clip Rectangle X registers take care of the pixel positions within a scan line 12 3 4 BRO3 Clip Rectangle Y2 Address Memory Offset Address 4000Ch Default None Attributes RO DWord accessible BRO3 is loaded by either the SETUP_BLT or SETUP_MONO PATTERN SL _BLT instructions and is used with PIXEL BLT SCANLINE BLT or TEXT BLT instructions 31 26 25 0 Reserved Must Clip Rectangle Y2 Address Bits 25 0 be Zero Reserved Must be Zero The maximum GC graphics address is 64 MBs Debug implementation specific Leftdiscard 11 06
427. to provide it The Destination Pitch Register must be programmed with number of bytes in the interval from the start of one scan line s worth of destination data to the next Since the color depth is 8 bits per pixel and the horizontal resolution of the display is 1024 the value to be programmed into these bits is 400h which is equal to the decimal value of 1024 Bits 31 3 of the Pattern Address Register must be programmed with the address of the pattern data Similarly bits 31 0 of the Destination Address Register must be programmed with the byte address at the destination that will be written to first In this case the address is 20080h which corresponds to the byte representing the pixel at coordinates 128 128 This BLT operation does not use the values in the Source Address Register or the Source Expansion Background or Foreground Color Registers The Destination Width and Height Registers must be programmed with values that describe to the BLT engine the 64x64 pixel size of the destination location The height should be set to carry the value of 40h indicating that the destination location covers 64 scan lines The width should be set to carry the value of 40h indicating that each scan line s worth of destination data occupies 64 bytes All of this information is written to the ring buffer using the PAT BLT command packet intel Figure 21 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Results of Example Pat
428. to the location and format of the map Two different texels can be fetched from the same map Figure 33 State Variable Relationships Coordinate Sets Texels Map Information Blending Stages Table 14 identifies four classes of surface formats for the supported maps in the GC The various attributes of the texels pixels are placed on 4 abstract channels named Fy F3 These channels can be switched into 4 output channels which are delivered by the Mapping Engine to the Color Calculator The switching of these channels ME ME3 is controlled by the Output Channel Selection field described below Table 14 Summary of Source Surface Formats with Filter Output Channel Mappings Attribute Types and Formats Filter Channels Alpha Intensity Luminance Chromanance etc I 8 Source Format a Arbitrary Attribute Alpha Attribute KA Aipha Red Gm Biue 16 ARGB 0505 1555 2444 R elen Alpha and Luminance Chromanance etc AY 88 Certain memory tiling properties are supported directly by this instruction This functionality is provided primarily for discrete graphics devices and for surfaces that do not need transparent processor access such as optimized texture maps Bits 31 26 of the Base Address are used to identify memory access from discrete graphics devices which are intended to bypass the Graphics Translation Table GTT The following t
429. ts This register contains the non persistent value of the signals causing each interrupt These bits are not masked by the Interrupt Mask Register The user interrupt and the breakpoint interrupt last for one clock pulse The corresponding bits in this register will serve no practical purpose due to the short duration of the signal 14 13 10 8 HW Reserved Pri Dply Reserved Overlay 0 Reserved Detect Flip Flip Error Pending Pending Master 6 5 4 3 2 0 Pri Dply Pri Dply Reserved Reserved Reserved Reserved User Breakpoint VBLANK Event Defined Interrupt Description Interrupt Status See Table 17 1 Signal caused interrupt 326 intel 16 2 6 16 2 6 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Error Identity Mask and Status Registers The Error Identity Mask and Status registers have the following bit descriptions The master error bit in the ISR and IIR register will be set when the OR of the unmasked with a zero in the corresponding mask register bits error status bits is true Page Table Error handling in Intel 815 Chipset Page table errors can be caused by accessing graphics aperture space when 1 The page table is not enabled 2 Attempting to access local memory in a UMA system 3 Attempting to access a page table entry which does not have the valid bit set 4 The location of the page table is in restricted region e g SMM space in memory For cycles initiated from the gra
430. ts describe the delay in terms of a number character clocks Bit 6 5 Amount of Delay 00 no delay 01 delayed by 1 character clock 10 delayed by 2 character clocks 11 delayed by 3 character clocks Horizontal Blanking End Bits 4 0 This field provides the 5 least significant bits of a 6 bit value that specifies the end of the blanking period relative to its beginning on a single scan line Bit 7 of the Horizontal Sync End Register CRO5 supplies the most significant bit This 6 bit value should be programmed to be equal to the least significant 6 bits of the result of adding the length of the blanking period in terms of character clocks to the value specified in the Horizontal Blanking Start Register CRO2 9 6 6 CR04 Horizontal Sync Start Register I O and Memory Offset Address 3B5h 3D5h index 04h Default Undefined Attributes Read Write Group 0 Protection This register is used to specify the beginning of the horizontal sync pulse relative to the beginning of the active display area on a scan line eT ee Horizontal Sync Start This field should be set equal to the number of character clocks that occur from beginning of the active display area to the beginning of the horizontal sync pulse on a single scan line 112 intel Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 7 CR05 Horizontal Sync End Register I O and Memory Offset Address 3B5h 3D5h index 05h Default 00h Attributes R
431. ue R W This is the value that should be place on the LTVCK pin as an output This value is only written into the register if LTVCK DATA MASK is also asserted The value will appear on the pin if this data value is actually written to this register and the LTVCK DIRECTION VALUE contains a value that will configure the pin as an output GP1O2 Data Mask R W This is a mask bit to determine whether the LTVCK DATA VALUE bit should be written into the register 0 Do NOT write LTVCK Data Value bit default 1 Write LTVCK Data Value bit LTVCK Direction Value R W This is the value that should be used to define the ouput enable of the LTVCK pin This value is only written into the register if LTVCK DIRECTION MASK is also asserted The value that will appear on the pin is defined by what is in the register for the LTVCK DATA VALUE bit 0 Pin is configured as an input default 1 Pin is configured as an output LTVCK Direction Mask R W This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the register 0 Do NOT write LTVCK Direction Value bit default 1 Write LTVCK Direction Value bit 351 Intel 815 Chipset Graphics Controller PRM Rev 1 0 This page is intentionally left blank 352 20 1 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Display And Cursor Registers The following are cursor display and pixel pipe registers in address range 70000h 7FFFFh
432. uences external to RBs These sequences are called batch buffers and are initiated through the use of GFXCMDPARSER_ BATCH BUFFER instructions that specify the starting address and length of the batch buffers The arbitration rules used by the IP when executing batch buffers differ from those employed when executing RBs and are described later in this chapter When a batch buffer instruction is executed out of a RB a batch buffer sequence is initiated where the GC reads the instructions sequentially via DMA from the batch buffer What happens when the end of the batch buffer is reached depends on the final instruction in the buffer If the final instruction isa GFXKCMDPARSER_ BATCH BUFFER instruction another batch buffer sequence is initiated This process called chaining continues until a batch buffer terminates with an instruction other than GFXCMDPARSER_ BATCH_ BUFFER at which point execution will resume in the RB at the instruction following the initial GFXCMDPARSER BATCH BUFFER Batch Buffer Sequence lt M ___ From Ring Buffer Batch Buff Ingtr Chainin Batch Buff Ingtr gt Return to Ring Bul btch_buf vsd intel 10 4 6 10 4 6 1 10 4 6 2 Intel 815 Chipset Graphics Controller PRM Rev 1 0 Instruction Arbitration The Instruction Parser supports up to four sources of pending instructions two Ring Buffers and two Batch Buffer sequences one batch buffer per ring buffer T
433. uffer 58 Pattern Data Always an 8x8 Array of Pixels 0 0 ceeeeecceeeeeeeeeeeeeeeeeeeeneeeeeeaas 60 8bpp Pattern Data Occupies 64 Bytes 8 quUadwords c ceeeeeeeeeeereeeee 61 16bpp Pattern Data Occupies 128 Bytes 16 quadwords cceeeeeeeeeeees 61 24bpp Pattern Data Occupies 256 Bytes 32 quadwords eeeeeeeeees 61 2bpp Pattern Data Occupies 256 Bytes 32 quadwords ceeeeeeeeneeees 62 On Screen Destination for Example Pattern Fill BLT ccceeeeeeeeteeeeeeees 63 Pattern Data for Example Pattern Fill BLT ccccceceeeeeeeeeceeceeeeeeeeeesnneeeeeees 64 Results of Example Pattern Fill BLT cccccecceseececeeeeeeeesececeeeeeeesenueaeeeeees 65 On Screen Destination for Example Character Drawing BLT eeeeeeee 66 Source Data in System Memory for Example Character Drawing BLT 66 Results of Example Character Drawing BLT csceeeeeseeeeeeeneeeeeeseeeeeeaaes 68 Display Fields and Dimensions CRxx Control Registers 0 cceeeeeeeeee 110 Graphics Controller Instruction Interface cccceececeeeeeeeeeeeeeeteeeeeesnaeees 143 Ring Buffers oe eee ee ceeee ee eeee ee erence ee eaeeeeeseaeeeeeseeeaeeeseaeaeeeseeeaaeeeseeeaeeeeeenaeees 144 Batch Buffer Seguente iiaia a aai a iaaa 146 Instruction Format For First DWord 0 ccceseccececeeeeeeeeaeeeeeeeeeeeeseeseaeeneees 150 Rectangle V
434. update for Overlay 0 cn 267 Intel 815 Chipset Graphics Controller PRM Rev 1 0 a 15 2 268 DOVOSTA Display Overlay 0 Status Register Memory Address Offset 30008h 3000Bh Default Value 0000 5000h Access RO Size 32 bits This read only register indicates the status for the overlay References to display are either the primary timing generator or the secondary timing generator depending on which is currently being used Reg Reserved Update Status Not Active Reserved Not Active Reserved Display Line Status Pixel Video Scan Line Register Update Status All registers latched Flip Pending 0 vblank status bi A A A overlay registers are updated overlay registers are updated overlay update register has been written overlay update register has been written vblank status bi A overlay registers are updated overlay update register has been written 0 overlay registers have been updated 1 overlay update register has been written overlay registers have not been updated Intel 815 Chipset Graphics Controller PRM Rev 1 0 Bit Description Overlay 0 Current Buffer Field This field indicates the Current Buffer Updated at display VBLANK before the interrupt this field is only valid when in field interlaced mode 00 Buffer 0 Field 0 01 Buffer 0 Field 1 10 Buffer 1 Field 0 11
435. upt pin is always an input It is never disabled An internal pull up is active when the pin is configured as an Interrupt When configured as a clock the internal pull up is disabled Lock Dot Clock PLL N M Regs 1 Dot Clock PLL N M registers are locked Use the LCD TV PLL M N registers and ignore the MSR register 0 Dot Clock PLL N M registers are writeable The MSR register controls which PLL M N registers are used When either supporting a TV Encoder or a Flat Panel but not in VESA VGA mode the LCD TV PLL MIN registers must be set up for the proper Dot clock frequency Then this bit is written with a 1 to lock the registers When written with a 1 forces the Dot Clock PLL to only look at the LCD TV PLL M N registers 341 Intel 815 Chipset Graphics Controller PRM Rev 1 0 17 8 OVRACT Overlay Active Register Address Offset 6001Ch Default Value 00000000h Access Read Write Size 32 bits 31 27 26 16 Reserved Overlay Active End 15 12 11 0 Reserved Overlay Active Start 26 16 Overlay Active End This filed takes into account the Overlay pipeline delays for turning off the overlay at the end of a scan line When LCD TV is enabled then the overlay active end is controlled by the LCD TV Out Timing Generator and uses all the bits When LCD TV is disabled then the overlay active end is controlled by the VGA Timing Generator and uses bits 15 3 for character clock resolution 11 0 Overlay Active Start T
436. ure 18 2bpp Pattern Data Occupies 256 Bytes 32 quadwords 63 48 47 32 31 16 15 0 Pixel 7 7 78h b_blt10 vsd As is shown in 24bpp pattern data figure there are four bytes allocated for each pixel on each scan line s worth of pattern data which allows each scan line s worth of 24bpp pattern data to begin on a 32 byte boundary The extra fourth unused bytes of each pixel on a scan line s worth of pattern data are collected together in the last 8 bytes the last quadword of each scan line s worth of pattern data The opcode of the command packet specifies whether the pattern data is color or monochrome The various bit wise logical operations and per pixel write masking operations were designed to work with color data In order to use monochrome pattern data the BLT engine is designed to convert it into color through a process called color expansion which takes place as a BLT operation is performed In color expansion the single bits of monochrome pattern data are converted into one two three or four bytes depending on the color depth to which the BLT engine has been set of color data that are set to carry values corresponding to either the foreground or background color that have been specified for use in this process The foreground color is used for pixels corresponding to a bit of monochrome pattern data that carry the value of 1 while the background color is used where the corresp
437. ure mapping Figure 31 State Variable Relationships Coordinate Sets Map Information Blending Stages es 31 29 Client 03h Rendering Engine 28 24 3DState16 1Ch 23 19 Opcode Oh 5 4 1 4 1 18 16 Reserved 00h Additional Texels Texel 1 State Variable Mask 0 Do not update 1 Update 8 Texel 1 Enable 0 Disable default 1 Enable in Tevet Coordinate Set index Indexto tne Coordinare se Texel 0 State Variable Mask 0 Do not update 1 Update Es La Texel 0 Enable 0 Disable default 1 Enable 5a Reserved oon ional corras OOOO 3 zt Texel 0 Coordinate Set Index Index to the Coordinate Set Reserved 00h Addition Map Information oo Texel 0 Map Information Index Index to the Map Information 1 1 1 7 5 3 2 214 INTel 13 6 Figure 32 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_MAP_COORD_SETS The Mapping Engine is capable of generating at most two map coordinate sets u and v addresses per pixel Each output texel may be related to separate coordinate sets or to the same coordinate set as shown below The vertices of a GFXPRIMITIVE instruction may have 0 1 or 2 map coordinate sets assigned with varying settings associated with each coordinate set A coordinate set may have normalized u v coordinates or un normalized coordinates Normalized coordinates have been
438. used the coordinate set addresses must be non normalized and are clamped they can not be wrapped or mirrored 0 Height Width are the actual dimensions of the map in pixels 1 Height Width are log2 of the actual dimensions of the base map 30 26 Reserved 00h Additional Height Height If the dimensions are to be specified as powers of two as determined by the Power of 2 field this field must contain one of the following values Oh 1 texel high 4h 16 texels high 8h 256 texels high 1h 2 texels high 5h 32 texels high 9h 512 texels high 2h 4 texels high 6h 64 texels high ah 1024 texels high 3h 8 texels high 7h 128 texels high If the dimensions are to be specified as the actual values this field contains the surface height 1 in units of texels The range for this value is 0 1023 15 10 Reserved 00h Width If the dimensions are to be specified as powers of two as determined by the Dimension Power of 2 field this field must contain one of the following values Oh 1 texel wide 4h 16 texels wide 8h 256 texels wide 1h 2 texels wide 5h 32 texels wide 9h 512 texels wide 2h 4 texels wide 6h 64 texels wide Ah 1024 texels wide 3h 8 texels wide 7h 128 texels wide If the dimensions are to be specified as the actual values this field contains the surface width 1 in units of texels The valid range for this value is 0 1023 for all surface formats except 4 2 2 For 4 2 2 surfaces this value
439. value in pixels The line antialiasing region width state variable allows for the specification of the width over which to blend for antialiasing of lines Similarly the polygon antialiasing region width state variable allows for the specification of the width over which to blend for antialiasing of polygon edges The edge flag enable state variable enables all the edge flags of a triangle line overriding the edge flags specified in the vertex format 31 29 Client 03h Rendering Engine 28 24 3DState24 06h 23 14 Reserved 000h Edge Flag Enable Mask 1 Update 0 Do Not Update Edge Flag Enable 1 Enable 0 Disable pn Polygon Antialiasing Region Width Enable Mask 1 Update 0 Do Not Update 10 9 Polygon Antialiasing Region Width Valid values are Oh 0 5 pixels 1h 1 0 pixels 2h 2 0 pixels 3h 4 0 pixels Line Antialiasing Region Width Enable Mask 1 Update 0 Do Not Update Bounding Box Expansion Mask 1 Update 0 Do Not Update Bounding Box Expansion U3 0 format Unsigned with valid values from 0 to 7pixels Anti aliasing Enable Mask 1 Update 0 Do Not Update e 7 6 Line Antialiasing Region Width Valid values are Oh 0 5 pixels 1h 1 0 pixels 2h 2 0 pixels 3h 4 0 pixels ES Anti aliasing Enable 1 Enable 0 Disable 248 Intel 815 Chipset Graphics Controller PRM Rev 1 0 GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION _RULE The provoking vertex state variables provide the flex
440. will be offset into the page table as defined by the page table base The physical address will be the combination of the page table base and page table offset derived from the memory mapped driver write A translation resource access TLB access with the page table disabled results in an interrupt This interrupt only occurs if there is a write through the TLB the page table can be disabled and the display and overlay still runs with no interrupt or error reporting The page table can be disabled when there is no drawing engine render map blitter or high priority stream overlay display active The hardware incorporates several TLBs that cache page table entries Disabling the page table through this register will invalidate all TLBs except the one serving display and overlay The following table lists all the TLBs and their invalidation mechanism Display Refreshed on Vsync Is not affected by bit 0 Overlay Refreshed on Vsync Is not affected by bit 0 11 1 31 12 0 Page Table Base Address Reserved Pg Tbl 4 KB aligned Enable oe 31 12 Page Table Base address 4 KB aligned Has to be within Main Memory This is a physical address no GTT translation under this category 0 Disable 1 Enable Page Table Enable If the graphics memory range is accessed through the graphics translation table when this bit is not set asserts an interrupt event All graphics streams other than cursor and VGA fall 303 Intel 815 Chipset Grap
441. within the active display area minus 1 CR0O2 Horizontal Blanking Start Register I O and Memory Offset Address 3B5h 3D5h index 02h Default Undefined Attributes Read Write Group 0 Protection This register is used to specify the beginning of the horizontal blanking period relative to the beginning of the active display area of a scan line Horizontal Blanking Start This field should be programmed with a value equal to the number of character clocks that occur on a scan line from the beginning of the active display area to the beginning of the horizontal blanking 111 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 5 CR03 Horizontal Blanking End Register I O and Memory Offset Address 3B5h 3D5h index 03h Default 1UUU UUUUb U Undefined Attributes Read Write Group 0 Protection Reserved Display Enable Skew Horizontal Blanking End Bits 4 0 0 Control a e Reserved Values written to this bit are ignored and to maintain consistency with the VGA standard a value of 1 is returned when this bit is read At one time this bit was used to enable access to certain light pen registers At that time setting this bit to O provided this access but setting this bit to 1 was necessary for normal operation Display Enable Skew Control Defines the degree to which the start and end of the active display area are delayed along the length of a scan line to compensate for internal pipeline delays These 2 bi
442. worth of color data that select the foreground color to be used in the color expansion of monochrome pattern or source data for either the SCANLINE_BLT or TEXT_BLT instructions 190 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 8 BR07 Setup Color Pattern Address Memory Offset Address 4001Ch Default None Attributes RO DWord accessible 31 26 25 16 Reserved Must be Zero Setup Color Pattern Address Bits 25 16 15 6 5 0 Setup Color Pattern Address Bits 15 6 Reserved Must be Zero ee 31 26 Reserved Must be Zero The maximum GC graphics address is 64 MBs Pattern Address These 20 bits specify the starting address of the color pattern from the SETUP_BLT instruction This register works identically to the Pattern Address register but this version is only used with the SCANLINE_BLT instruction execution The pattern data must be located on a pattern size boundary The pattern is always of 8x8 pixels and therefore its size is dependent upon its pixel depth The pixel depth may be 8 16 or 24 bits per pixel if the pattern is in color the pixel depth of a color pattern must match the pixel depth to which the graphics system has been set Monochrome patterns require 8 bytes and is supplied through the instruction Color patterns of 8 16 and 24 bits per pixel color depth must start on 64 byte 128 byte and 256 byte boundaries respectively Note In the case of 24 bits per pixel each scan line s worth
443. x3 on the same line can be defined as x3 y3 where y3 is y3 slope x3 xl yl Interpolated Point Value Of Latch Derived Slope Adrs N 1 Adrs N Adrs N 1 _ io l Ideal Curve l Value Of Latch Adrs N gt Value Of LSB s Result Value Of Latch Adrs N Slope LSB s Gamma correction can be bypassed by programming the registers with data values corresponding to a linear curve with slope 1 The register programming for gamma bypassing is as shown below Adrs 8 8 Adrs 64 64 Adrs 16 16 Adrs 128 128 Adrs 32 32 Adrs 192 192 When registers are programmed with the above values output of the gamma unit is the same as the input and no gamma correction occurs Gamma Hardware Implementation Result Adrs 192 0x00 Adrs 192 X 192 lt lt 1 gt gt 7 192 lt X lt 256 Result Adrs 128 Adrs 192 Adrs 128 X 128 lt lt 1 gt gt 7 128 lt X lt 192 Result Adrs 64 Adrs 128 Adrs 64 X 64 lt lt 1 gt gt 7 64 lt X lt 128 Result Adrs 32 Adrs 64 Adrs 32 X 32 lt lt 2 gt gt 7 32 lt X lt 64 Result Adrs 16 Adrs 32 Adrs 16 X 16 lt lt 3 gt gt 7 16 lt X lt 32 Result Adrs 8 Adrs 16 Adrs 8 X 8 lt lt 4 gt gt 7 lt X lt 16 Result 0x00 Adrs 8 0x00 X 0 lt lt 4 gt gt 7 0 lt X lt 8 o0 Consider Adrs 8 8 Adrs 16
444. xel on a scan line 25 00 are implemented in Intel 810 chipset 12 2 4 SCANLINE_BLT The Destination Y Address is compared against the ClipRect Y address registers If the address is within this comparison then the pattern pixels dependent on the Destination X coordinates that fall within the ClipRect X comparisons are written using the raster operation to Destination Y Address Destination X coordinate bytes per pixel The horizontal alignment is relative to the destination from the lower bits of the destination address The pattern vertical alignment indicates which pattern scan line is used this is the least significant three bits of the destination vertical coordinate With color patterns only 1 scan line should be read for this instruction e Solid pattern should use the SETUP_MONO_ PATTERN SL _ BLT instruction we e e 1 BRO8 31 16 Destination X2 Coordinate Ending Right paa Intel 815 chipset implementation supports 27 16 12 bits 15 00 Destination X1 Coordinate Starting Left X2 X1 1 width in pixels inal Intel 815 chipset implementation supports 11 00 12 bits 2 BR09 31 00 Destination Y Address address of the first pixel on a scan line 25 00 is implemented inIntel 810 chipset 167 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 5 TEXT_BLT All monochrome source scan lines and pixels that fall within the ClipRect Y addresses and X coordinates are written i
445. y The whole color pattern 8 x 8 pixels 16 32 or 64 DWs is read at the beginning of the BLT and stored in the Texture Cache The pattern vertical alignment specifies the first scan line of the pattern that is used The horizontal alignment is relative to the destination from the lower bits of the destination address The only memory accesses required for the remainder of the BLT is destination accesses which is dependent on the raster operation Only a positive destination pitch is allowed Coes Te ee 25 24 Color Depth 00 8 bit color 01 16 bit color 10 24 bit color 11 reserved 23 16 Raster Operation 15 00 Destination Pitch positive 13 00 are implemented in Intel 810 chipset 2 BR14 31 16 Destination Height in scan lines 28 16 are implemented in Intel 810 chipset 15 00 Destination Width in bytes 12 00 are implemented in Intel 810 chipset 3 BROY 31 00 Destination Address Address of the first byte to be written 25 00 are implemented in Intel 810 chipset 4 BR15 31 00 Pattern Address 25 06 are implemented in Intel 810 chipset 171 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 2 9 MONO _PAT_BLT MONO _PAT BLT is used when there is no source and the monochrome pattern is not trivial is not a solid color only The monochrome pattern is loaded from the instruction stream and the only memory accesses are for the destination operand which is dependent on the
446. y Size 16 bits 15 6 Reserved MM LM Page Table Display or Reserved Reserved Instruction Refresh Error Overlay Parser timer error under run Error Error Status Bits See Error Identity Mask and Status Register Bit Definitions table a 330 Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 16 3 Display Interface Control 16 3 1 FW_BLC FIFO Watermark and Burst Length Control Address Offset 020D8h Default Value 22 31 73 17h Access Read Write Size 32 bits These control values only apply to HIRes modes of operation VGA modes ignore the settings of these registers in favor of fixed values For VGA Text mode character buffer fetches are performed without regard to the space available in the FIFO since this data is stored in the character buffer not the FIFO Character buffer fetches are performed as a single request of 8 QWs Font data is fetched one QW at a time and will begin when the FIFO has room for 8 character font QWs VGA Graphics modes will perform requests one at a time so long as there is room for 1 QW in the FIFO FIFOs refer to ALL FIFOs in the DSI data path i e The total FIFO space available is the sum of the DSI FIFO depth and the Display Engine FIFO depth Currently this depth is 48 QWs The h w default is an invalid value these quantities should never be programmed to zeros a The hardware depends on these registers being set properly since it is possible to set the re
447. y of this register In extended modes where bit 0 of the I O Control Register CR80 is set to 1 the vertical total is specified with a 12 bit value The 8 least significant bits of this value are supplied by bits 7 0 of the Vertical Total Register CRO6 and the 4 most significant bits are supplied by 3 0 bits of the Extended Vertical Total Register CR30 In extended modes neither this bit nor bit 5 of this register are used This 10 bit or 12 bit value should be programmed to be equal to the total number of scan lines minus 2 9 6 10 CRO amp Preset Row Scan Register I O and Memory Offset Address 3B5h 3D5h index 08h Default OUUU UUUUb U Undefined Attributes Read Write Reserved Byte Panning Starting Row Scan Count 0 Ea Reserved Read as Os Byte Panning This field holds a 2 bit value that selects number of bytes up to 3 by which the image is shifted horizontally to the left on the screen This function is available in both text and graphics modes In text modes with a 9 pixel wide character box the image can be shifted up to 27 pixels to the left in increments of 9 pixels In text modes with an 8 pixel wide character box and in all standard VGA graphics modes the image can be shifted up to 24 pixels to the left in increments of 8 pixels The image can be shifted still further in increments of individual pixels through the use of bits 3 0 of the Horizontal Pixel Panning Register AR13 Number of
448. y graphics device must not be the Intel 815 chipset internal graphics controller or an AGP graphics card These graphics devices can serve only as secondary graphics devices in a multi monitor configuration It is important to understand that there is no support for simultaneous operation of the internal graphics device and an AGP graphics card 23 Intel 815 Chipset Graphics Controller PRM Rev 1 0 To support a PCI graphics device the Intel 815 chipset simply passes all of that device s cycles to the hub interface as it would for any other PCI device Primary Internal AGP Non AGP Non AGP Non AGP Non AGP Graphics Graphics Graphics Graphics Graphics Card Graphics Graphics Device with LM or Card Card PCI PCl Card PCI Card PCI UMA Secondary Internal AGP Non AGP Graphics Graphics with Graphics Graphics Device LM or UMA Card Card PCI 24 Intel 815 Chipset Graphics Controller PRM Rev 1 0 System Startup The Intel 815 chipset has multiple possible device modes The selection of which mode will be auto detected is represented in the following flow chart The software requirements for implementing this high level flow are detailed in the next section Multi monitor configurations are not addressed as that is a function of the operating system when supported System BIOS also provides the ability to select any of the display devices as the primary display device Device Mode Auto Detect Flowchart
449. y the height of the destination data in terms of the number of scan lines This is a working register 15 13 Reserved Must be Zero Destination Byte Width These 13 bits specify the width of the destination data in terms of the number of bytes per scan line The number of pixels per scan line into which this value translates depends upon the color depth to which the graphics system has been set NOTES This is a working register If BR14 is read while the BLT Engine is busy the contents are unpredictable The value contained in this register while the BLT Engine is busy has no relationship to the programmed value that can be read when the BLT Engine is idle Intel 815 Chipset Graphics Controller PRM Rev 1 0 intel 12 3 16 BR15 Color Pattern Address Memory Offset Address 4003Ch Default None Attributes RO DWord accessible 31 26 25 16 Reserved Must be Zero Color Pattern Address Bits 25 16 15 6 5 0 Color Pattern Address Bits 15 6 Reserved Must be Zero E 31 26 Reserved Must be Zero The maximum GC graphics address is 64 MBs Color Pattern Address These 20 bits specify the starting address of the pattern The pattern data must be located on a pattern size boundary The pattern is always of 8x8 pixels and therefore its size is dependent upon its pixel depth The pixel depth may be 8 16 or 24 bits per pixel if the pattern is in color the pixel depth of a color pattern must match the pixel depth to whic
450. ync pulses on the last scan line rather than coincident with the beginning of a horizontal sync pulse at the end of a scan line 9 6 39 CR80 lt 1 O Control I O and Memory Offset Address 3B5h 3D5h index 80h Default 00h Attributes Read Write Reserved 000000 Attr Cntl CRT Cntl Ext Enbl Int Enbl 1 Attribute Controller Extensions Enable Controls whether the attribute registers are accessed with both index and data at 3COh strict VGA mode or whether they are accessed with 3cOh as the index and 3C th is data It is possible that BIOS software or driver software might not use the non VGA mode Either method should work but it needs to be the method the software is using 0 Disable i e strictly VGA compatible mode default 1 Enable Attribute Controller extensions Index and Data of the Attribute Controller registers are accessible at 3COh in standard VGA When the Attribute Controller Extensions are enabled Index and Data are accessible at addresses 3COh and 3C th respectively CRT Controller Interpretation Enable This bit modifies responses functionality to registers CR30 and beyond except for CR41 0 Registers have strict VGA Interpretation default 1 Registers have extended VGA Interpretation i e access to 4G space 139 Intel 815 Chipset Graphics Controller PRM Rev 1 0 9 6 40 CR81 Reserved I O and Memory Offset Address 3B5h 3D5h index 81h Default 00h Attributes Read Write
451. ype 4 is reported by the main memory controller logic of the GMCH Page Table Access done at the main memory controller is done on a QW basis This logic area has no concept of DW accesses i e the high or low DW page entry actually being requested Error reporting for page entries pointing to invalid memory ranges is therefore done for both page entries within the QW assuming both entries are marked valid If one page entry in the QW being accessed points to an illegal address that entry is reported If both entries in the QW being accessed point to invalid addresses the hardware by convention reports the upper entry only When reporting page table error type 4 for addresses mapped to above top of physical memory Page Table Entry 31 29 Reserved lt HW does NOT decode these bits 28 12 Physical Address lt HW is only sensitive to these bits T13 Reserved 2 1 T1TO 0 Valid This means any addresses mapped to range 512 MB and lt 4 GB will be treated by the error detection logic as wrap around at the 512 MB boundary Within the 512 MB block if the address is at or above top of physical memory or above top of physical memory minus TSEG range if TSEG is enabled then a type 4 error will be generated 305 Intel 815 Chipset Graphics Controller PRM Rev 1 0 16 1 4 306 intel PGTBL_ERRMSK Page Table Error Mask Register Address Offset 02028h identical functionality in Device 0 at FO F3h Default Value 0000 0000h

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