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iSimple ISGM11 Satellite Radio User Manual

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1. ignore transitions subtract dne none add one ignore transitions I 1 1 l add n d l l Bi S Clock iOS Dp ee 190 Rabbit 3000 Microprocessor With NRZ NRZI encoding all transitions occur on bit cell boundaries and the data should be sampled in the middle of the bit cell If a transition occurs after the expected bit cell boundary but before the midpoint the DPLL needs to lengthen the count to line up the bit cell boundaries This corresponds to the add one and add two regions shown If a transition occurs before the bit cell boundary but after the midpoint the DPLL needs to shorten the count to line up the bit cell boundaries This corresponds to the subtract one and subtract two regions shown DPLL makes no adjustment if the bit cell bound aries are lined up within one count of the divid
2. Serial Port x Status Register SESR Address OxCB SFSR Address 0xD3 Bit s Value Description HDLC mode only 0 The receive data register is empty 7 1 There 15 a byte in receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 00 The byte in the receive buffer is data 01 The byte in the receive buffer was followed by an Abort 6 4 10 The byte in the receive buffer is the last in the frame with valid CRC 11 The byte in the receive buffer is the last in the frame with a CRC error 0 The receive buffer was not overrun 5 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when 3 1 the transmitter takes a byte from the transmit buffer unless the byte is marked as the last in the frame Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignored is written to this register 00 Transmit interrupt due to buffer empty condition Transmitter finished sending CRC An interrupt is generated at the end of CRC 01 transmission Data written in response to this interrupt will cause only one Flag to be transmitted between frames and no interrupt will be generated by this Flag 2 1 10 Transmitter finished sending an Abort
3. enne eene nnne nnne 91 7 8 Watchdog Timer noroeste RD RD ORE e EDO rar a 93 7 9 System RESET u aa e GON A EAE Se Shak ee MS aie 95 7 10 Rabbit Interrupt Structure eee eee ete oir ue karate ie a den 97 710 1 External Interrupts e er een tto qi i EE E ee 99 7 10 2 Interrupt Vectors INTO EIR OxOO INTI EIR 0xOS Lu esee 100 7 11 Bootstrap Operation sce a ebore etd 101 7 12 Pulse Width Modulator upa aa hu S 103 FAB Input oe iHe Med t e a teen pee Ma AI nci t odis 105 7 4 Quadrature De ode er sse eee rese dee Dre 110 Chapter 8 Memory Interface and Mapping 115 8 1 Interface for Static Memory 0 1 115 82 Memory Mapping Overview u nisus asus Se etti ese iwi eee 117 8 3 Memory Mapping Unit n 117 SA Memory Interface mit eene iet er ee e tet ei 119 Rabbit 3000 Microprocessor 8 5 Memory Bank Control Registers rennen 120 8 5 1 Optional A16 A19 Inversions by Segment CS1 Enable 121 8 6 Allocation of Extended Code and 123 8 7 Instruction and Data Space Suppolt eren enne nennen nennen nennen 124 8 8 How the Compiler Compiles to Mem
4. Serial Port x Extended Register SAER Address 0xC5 SBER Address 0xD5 SCER Address 0xE5 SDER Address 0xF5 SEER Address 0xCD SFER Address 0xDD Bit s Value Description Async mode only 7 5 XXX These bits are ignored in async mode 0 Normal async data encoding 4 1 Enable RZI coding 3 16ths bit cell IIDA compliant 0 Normal Break operation This option should be selected when address bits are expected 3 1 Fast Break termination At the end of Break a dummy character is written to the buffer and the receiver can start character assembly after one bit time 0 Async clock is 16X data rate 2 1 Async clock is 8X data rate 1 0 xx These bits are ignored in async mode 176 Rabbit 3000 Microprocessor Table 12 18 Extended Register Clocked Serial Mode Ports A D only Serial Port x Extended Register SAER Address 0xC5 SBER Address 0xD5 SCER Address 0xE5 SDER Address 0xF5 Bit s Value Description Clocked serial mode only 0 Normal clocked serial operation 1 Timer synchronized clocked serial operation 0 Timer synchronized clocked serial uses Timer B1 1 Timer synchronized clocked serial uses Timer B2 00 Normal clocked serial clock polarity inactive High Internal or external clock 01 Normal clocked serial clock polarity inactive Low Internal clock only di 10 Inverted clocked serial clock po
5. 19 13 8 bit Fast A Register Operations eee 19 14 8 bit Shifts and Rotates a 19 15 Instruction u roe eee edere Rabbit 3000 Microprocessor 19 16 Block Move Instructions neinni i eerte e L ae e halal 19 17 Control Instructions Jumps and n 19 18 Miscellaneous InSfrUuctionSuu u u u as e ha qhu a ug Sa aus las 19 19 Privileged Instructions egere etum eh RR Pre EE Chapter 20 Differences Rabbit vs 280 2180 Instructions 259 Chapter 21 Instructions in Alphabetical Order With Binary Encoding 261 Appendix A The Rabbit Programming Port 269 Use of the Programming Port as a Diagnostic Setup A 2 Alternate Programming Port enne Suggested Rabbit Crystal Frequencies essent enne Appendix B Rabbit 3000 Revisions 273 B 1 Discussion of Fixes and Improvements eene nennen enne enne tenentes terne 1 Rabbit Internal I O Registers 2 Peripheral and ISR Address nennen nre 3 RevisionzEevel ID Register hide rr tct eee ti m nini reip edes dee rete A System User Mode ice nennen bi ERU ORE 5 eere c pneter eto dite prp e DR RT piii eie ERR
6. 40 Zero HLINA CLOCKS u uuu un asada aap 40 3 4 2 Exchanges Not Directly Implemented 40 3 4 3 Manipulation of Boolean Variables 2 emen 40 3 4 4 Comparisons Of IMG SOLS EN 41 3 4 5 Atomic Moves from Memory to I O Space a 43 User s Manual 3 5 o ER ua serine better debe tere 44 3 5 1 Intertupt Priority eee E RE RHODE RE Eo ree erae ERR 44 3 5 2 Multiple External Interrupting Devices sess 46 3 5 3 Privileged Instructions Critical Sections and Semaphores see 46 Critical Sections x ient ere eene tae gil ec e ede eder deeds 47 3 5 5 Semaphores Using Bit B HL Lee nennen enne nennen nennen treten 47 3 5 6 Computed Long Calls and Jumps eese eene eren nennen 48 Chapter 4 Rabbit Capabilities 49 4 1 Precisely Timed Output Pulses 44222 4 2 1 0100000000000000000000 49 4 1 1 Pulse Width Modulation to Reduce Relay Power eene 50 4 2 Open Drain Outputs Used for Key Scan a 51 4 3 Cold a rene eee p e t He te i e de bee i te edt e et 52 4 4 The Slave Port uka Q S es ei ea eae ees 53 4 41 Slave Rabbit ASA Protocol UART
7. Serial F Serial A Serial B Input Capture Serial C PWM Quadrature Decode Serial D Timer Al perclk 2 erclk 8 compare E lt q 10 bits gt Timer 10 bit counter match reg Timer B System Control Timer Synchronized outputs match preload Timer B2 p reg match preload i Figure 11 1 Block Diagram of Timers A and B User s Manual 149 11 1 Timer A Timer A consists of ten separate countdown timers 1 10 as shown in Figure 11 1 Timers A1 and 2 10 are 8 bit countdown registers as shown in Figure 11 2 The reload register can contain any number in the range from 0 to 255 The counter divides by n 1 For example if the reload register contains 127 then 128 pulses enter on the left before a pulse exits on the right If the reload register contains zero then each pulse on the left results in a pulse on the right that is there is division by one 8 bit reload register Clock in load a _ 8 bit down counter pulse on zero count out Input clock
8. 122 319 scillatots crystal frequencies 271 PADR 130 32 768 kHz 80 81 209 design features 9 parallel port alternate func maii G canals 80 209 features 1 HONS aab md m 67 output pins list of advantages 6 PBDDE 131 alternate assignment 90 on chip peripherals 11 PBDR 131 programing port 269 PEDR a ai 132 P revision history 273 216 PORR acon cas toon ti 132 specifications 2 4 PDBxR 133 1 Port D A e E zi PDCR 133 135 PDDCR 133 338 Rabbit 3000 Microprocessor SCER Sy IA bus 166 Saa sua sassa 166 SDAR sonent 167 167 SDDR enr 167 SDLR us aste ees 167 SDSR 1 167 SEAR sede eis 167 SEGR 167 SEDR iss sies 167 SEER is ese 167 serial port address regis csset etre eret mn 168 serial port control regis ters seen 173 174 175 serial port data registers 168 serial port extended asynchro nous registers 176 serial port extended registers clocked serial mode 177 serial port HDLC mode ex tended registers 178 serial port HDLC mode status registers 4 1 172 serial port long stop regis aasan yi ssh qhu 169 serial port status registers
9. 1 0 00 The Serial Port interrupt is disabled 01 The Serial Port uses Interrupt Priority 1 10 The Serial Port uses Interrupt Priority 2 User s Manual 173 Table 12 15 Serial Port Control Register Ports C and D Serial Port x Control Register SCCR Address 0xE4 SDCR Address 0xF4 Bit s Value Description 00 No operation These bits are ignored in the async mode 01 In clocked serial mode start a byte receive operation 7 6 10 In clocked serial mode start byte transmit operation T In clocked serial mode start a byte transmit operation and a byte receive operation simultaneously 0 Enable the receiver input 5 1 Disable the receiver input 4 x This bit is ignored 00 8 bits per character 01 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data Clocked serial mode with external clock 32 10 Serial Port C clock is on Parallel Port PF1 Serial Port D clock is on Parallel Port PFO Clocked serial mode with internal clock 11 Serial Port C clock is on Parallel Port PF1 Serial Port D clock is on Parallel Port PF0 00 The serial port interrupt is disabled 01 The serial port uses Interrupt Priority 1 1 0 10 The serial port uses Interrupt Priority 2 11 The serial port uses Interrupt Priority 3 174 Rabbit 3000 Microprocessor Table 12 16 Serial Port C
10. 0x48000 0x00000 0x40000 Figure B 1 Sample Memory Protection Layout The new memory protection registers are listed in Table B 6 through Table B 11 Table B 6 Write Protect Control Register Write Protect Control Register WPCR Address 0x0440 Bit s Value Description 7 1 These bits are reserved and should be written with zeros write protection in User mode only write protection in System and User modes 284 Rabbit 3000 Microprocessor Table B 7 Write Protect Low Register Write Protect Low Register WPLR Address 0x0460 Bit s Value Description 0 Disable 64K write protect for physical address 0x70000 0x7FFFF H 1 Enable 64K write protect for physical address 0x70000 0x 7FFFF 0 Disable 64K write protect for physical address 0x60000 0x6FFFF 1 Enable 64K write protect for physical address 0x60000 Ox6FFFF 0 Disable 64K write protect for physical address 0x50000 0x5FFFF i 1 Enable 64K write protect for physical address 0x50000 0x5FFFF 0 Disable 64K write protect for physical address 0 40000 I 1 Enable 64K write protect for physical address 0 40000 0 4 0 Disable 64K write protect for physical address 0x30000 0x3FFFF 1 Enable 64Kwrite protect for physical address 0x30000 0x3FFFF 0 Disable 64K write protect for physical address 0x20000 0x
11. 179 spectrum spreader watchdog 238 System User mode 321 eee 80 86 212 225 E updating registers 243 timer and clock use 244 timing issues 225 226 24 L cold boot 2 22 2 52 PCB layout 212 comparison Rabbit 3000 va ee design 210 ow power options 87 Rabbit 2000 259 extended memory LQFP pack compiler 127 I and D space 27 28 L AND l pattern 58 crystal frequencies 271 practical considerations 30 mechanical dimensions 57 Stack segment 29 pinout external bus read and write timing 64 User s Manual 337 M parallel ports 129 Rabbit 3000A conflict between Port A and internal I O registers 327 memory Port E unie 129 141 opcodes 293 16 A19 inversions CS1 Parallel Port 130 Rabbit Semiconductor enable 121 Parallel Port 131 ee ne 1 access time 215 Parallel Port C 132 Z World support 1 access time delays 220 Parallel Port D 133 RAM segment relocation 291 access t
12. Memory Output Enable 0 5 C2 Output Enables 1 Memory Output Enable 1 95 C12 Memory WEO Output Memory Write Enable 0 86 F9 Write Enables wg Output Memory Write Enable 1 99 B11 I O Control BUFEN Output I O Buffer Enable 42 M4 IORD Output I O Read Enable 41 L4 IOWR Output I O Write Enable 40 K4 62 Rabbit 3000 Microprocessor Table 5 1 Rabbit Pin Descriptions continued Pin Pin Pin Group Pin Name Direction Function Numbers Numbers LQFP TFBGA D7 8 8 I O ports PA 7 0 Input Output I O Port A 111 104 C8 D8 A9 B9 C9 I O ports C4 A5 B5 continued PB 7 0 Input Output I O Port B 123 116 C5 D5 A6 B6 C6 L11 M11 66 71 74 MI2 L12 PC 7 0 41n 4 Out I O Port C 75 K12 J10 H12 K7 L7 M7 PD 7 0 Input Output I O Port D 52 59 J8 K8 L8 MS J9 26 31 34 H4 J1 J4 PE 7 0 Input Output I O Port E 35 KLLI L2 B3 4 127 124 B4 A10 PF 7 0 Input Output I O Port F 103 100 B10 All 12 M1 M2 L3 PG 7 0 Input Output I O Port G 9n M3 K9 L9 M9 K10 Power VDDCORE 13 3 8 24 72 D2 E11 H2 processor core 88 J12 Power 1 17 33 AT C10 D6 Processor I O VDDIO 43 3 V 65 81 97 G10 Ring 115 M10 Power Battery AT 3 3 V or battery 51 77 Backup Ground Processor VSSCORE Ground 24 29 13 D3 E10 89 Jil Core Ground 16 32 48 A2 C7 C11 Proces
13. ann i H 10 13 8 2 12 10 Operation SP 1 PCH SP 2 PCL PC mn SP SP 2 B B 1 if B 0 PC PC j PC HL PC IX PC IY if f PC mn PC mn if cc PC PC e PC PC e if e 0 next seq inst is executed SP 1 XPC SP 2 PCH SP 3 PCL XPC xpc PC mn SP SP 3 XPC xpc PC mn PCL SP PCH 5 1 XPC SP 2 SP SP 3 PCL SP PCH SP 1 SP SP 2 if f PCL SP PCH SP 1 SP SP 2 IP SP PCL SP 1 PCH SP 2 SP SP 3 SP 1 PCH SP 2 PCL SP SP 2 PC R v v 10 18 20 28 38 only 19 18 Miscellaneous Instructions Instruction CCF IPSET IPSET IPSET IPSET IPRES LD A EIR LD A IIR LD A XPC LD EIR A LD IIR A LD XPC A NOP POP IP PUSH IP SCF clk KKK KP a a gm aga PND fr fr Operation CF IP IP 5 0 00 IP 5 0 01 IP IP 5 0 10 IP IP 5 0 11 IP IP 1 0 IPI7 21 A EIR A IIR A MMU EIR IIR Operation SP SP 8 1 SP 1 IP SP SP 1 1 User s Manual 257 19 19 Privileged Instructions The privileged instructions are described in this section Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction The three instructions below are privileged LD SP HL load t
14. esses Chapter 18 Other Rabbit Software 18 1 Power Management Support eee 18 2 Reading and Writing I O Registers 2 2 2 18 2 1 Using Assembly Language eee 18 2 2 Using Library Functions eee 18 3 Shadow Registers esses 18 3 1 Updating Shadow Registers 2 2 2 2 18 3 2 Interrupt While Updating Registers 18 3 3 Write only Registers Without Shadow Registers 18 4 Timer and Clock Usage eee Chapter 19 Rabbit Instructions 19 1 Load Immediate 19 2 Load amp Store to Immediate Address 19 3 8 bit Indexed Load and Store 19 4 16 bit Indexed Loads and Stores 19 5 16 bit Load and Store 20 bit Address 19 6 Register to Register Moves sse 19 7 Exchange Instructions 19 8 Stack Manipulation Instructions eese 19 9 16 bit Arithmetic and Logical Ops a 19 10 8 bit Arithmetic and Logical Ops a 19 11 8 bit Bit Set Reset and Test 19 12 8 bit Increment and Decrement
15. RL RLA RLC RLCA RRC RRCA Instruction clk A ISZVC RL HL 10 f b L RL IX d 13 f b L RL IY d 13 f be RL r 4 fr L RLC HL 10 f L RLC IX4d 13 f L RLC IY d 13 f b L RLC r 4 fr L RR HL 10 f b Lk RR IX d 13 f b L RR IY d 13 f b L RR r 4 fr L RRC HL 10 f be RRC IX d 13 f L RRC IY d 13 f L RRC r 4 fr L SLA HL 10 f b Lk SLA IX4d 13 f SLA IY d 13 f b L Operation A A A 0 A cy A a cy A A 6 0 A 7 CY A 7 a cy cy a A 0 AI 7 1 A 0 Operation cv HL H1 CY cv IX d cv I d I d cy cy r r cy HL HL 6 0 HL 71 CY HL 7 IX d 1X d 6 0 rX d 71 IX d 7 rY d 6 0 rY d 71 riv d 7 r r 6 0 r 7 CY rI71 HL CY cv HL IX d cy CY IX d IY d CY r cx cy r HL HL 0 HL 7 11 CY HL 0 IX d IX d 0 IX d 7 11 CY 0 IY d 0 IY d 7 1 CY IY d 0 r 0 r 7 1 CY r 0 HL HL I6 01 0 CY
16. SQ VE 4 Figure 16 13 Reduced Power External Main Oscillator Table 16 8 lists results for the reduced power external oscillator with no current limiting resistors Table 16 8 Current Draw Using Reduced Power External Oscillator 0 Q current limiting resistors Voltage Current incl built in buffer V mA 3 3 0 635 2 5 0 380 1 8 0 252 Design Recommendations e Add current limiting resistors to reduce current without inhibiting oscillator start up e Increase the 1 MQ resistor to improve gain e Minimize loop area to reduce EMI 236 Rabbit 3000 Microprocessor 17 RABBIT BIOS AND VIRTUAL DRIVER When a program 15 compiled by Dynamic C for a Rabbit target the Virtual Driver is auto matically incorporated into the program Virtual Driver is the name given to some initial ization routines and a group of services performed by the periodic interrupt The Rabbit BIOS software that handles startup shutdown and various basic features of the Rabbit is compiled to the target along with the application program Z World provides the full source code for the BIOS and Virtual Driver so the user can modify them and examine details of the operation that are not apparent from the documen tation More details on the BIOS and Virtual Driver software can be found in the Dynamic C User s Manual the Rabbit 3000 Designer s Handbook and the source code in the Dynamic C libraries 17 1 T
17. package quadrature encoder inputs 17 d dimensions separate and I O power register 35 PING anay sayay 18 move 35 bootstrap operation 101 serial ports 11 D 29 44 48 72 97 slave port 14 53 Dynamic 238 system clock 12 external interrupts 99 ClOCkS Lewn 80 209 time date clock 12 interrupt latency 49 32 768 kHz oscillator timed output pulses 49 interrupt service vector 80 81 209 uu uuu 515 addresses 72 clock doubler 83 84 225 design standards interrupt vectors 100 clock speeds 227 programming port 18 multiple interrupts 46 distribution 81 Dynamic M 1 19 on chip peripherals 280 282 low power design 210 BIOS i ie 237 priorities 44 45 97 main clock 80 91 209 library functions 242 priviligeged instructions and oscillator circuits 209 periodic interrupts 238 semaphores 46 power consumption power consumption 241 semaphores 47 iri 85 235 236 virtual drivers 238 serial port
18. in WP Segment x i 1 Enable write protect for address offset 00 0 WP Segment x 0 Disable write protect for address offset OXBO00 0xBFFF in WP Segment x 1 Enable write protect for address offset 0xB000 0xBFFF in WP Segment x 0 Disable write protect for address offset 0x A000 0x AFFF in WP Segment x l 1 Enable write protect for address offset Ox A000 0xAFFF in WP Segment x 0 Disable write protect for address offset 0 9000 0 9 in WP Segment x 1 Enable write protect for address offset 0 9000 0 9 in WP Segment x 0 Disable 4Kwrite protect for address offset 0x8000 0x8FFF in WP Segment x 1 Enable write protect for address offset 0x8000 0x8FFF in WP Segment x 288 Rabbit 3000 Microprocessor B 1 6 Stack Protection Stack overflow and underflow can now be detected Low and high stack limits can be set on 256 byte boundaries When a stack relative memory access occurs within 16 bytes of these limits or outside of them a new Priority 3 stack violation interrupt occurs The 16 byte buffer exists to allow stack protection even if the stack is placed against a memory segment boundary Figure B 2 shows one possible stack layout A 2048 byte stack is set up by setting STKHLR to OxEO STKLLR to OxD8 and SP to OxDFFO Any stack relative memory accesses above OxDFEF i e stack underflow or below OxD810 i e overflow would trigger the stack violation
19. nn rennen nemen 11 2 21 5 V Tolerant Inputs na abs seek b EEEE EEEE TEENE ria 11 2222 ROMS m 11 2 23 12 2 2 4 32 768 kHz Oscillator 2 ettet erret 12 2222 NaCAMnom M M 13 PARET duni PONE 14 pa Veruwalti p 15 PA blu PREX 15 22 9 Input Capture Channels ainiai Q ukata kau qaya 16 2 2 10 Quadrature Encoder Inputs erbe 17 2 2 11 Pulse Width Modulation Outputs 17 2 2 12 Spread Spectrum Clock eian iaio ian iaeiei SAE EEEE EERS 18 2 2 13 Separate Core and I O Power Pins 18 2 3 Design 5 EE E Ee iasi ree ia E Erir te E Ea E 18 2 3 Programming Port ua e EIE REM EET ei ae ee 18 2 3 2 Standard BIOS T u eerte n eri i UHR EE CERE seus SPREA OE A 19 2 4 Dynamic C Support for the Rabbit sese rennen nennen 19 Chapter 3 Details on Rabbit Microprocessor Features 21 Dil 5
20. 01 DE 10 IX 11 SP yy yy Word register select 00 BC 01 DE 10 TY 11 SP 22 22 Word register select 00 BC 01 DE 10 HL 11 AF Logical zero if all four of the most significant bits of the result 0 T Logical one if any of the four most significant bits of the result are 1 262 Rabbit 3000 Microprocessor Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A ISZVC ADC A HL 10001110 fr ADC A IX d 11011101 10001110 d 9 fr sk ADC A IY d 11111101 10001110 d 9 fr sk ADC A n 11001110 n 4 fr k k V ADC A r 10001 r 2 fr k k V ADC HL ss 11101101 01551010 4 fr k V ADD A HL 10000110 5 fr s ADD A IX d 11011101 10000110 d 9 fr sk ADD A IY d 11111101 10000110 d 9 fr sk ADD A n 11000110 4 fr ee V ADD A r 10000 r 2 fr ADD HL ss 00ss1001 2 fr ADD IX xx 11011101 00xx1001 4 f ADD IY yy 11111101 00 1001 4 f ADD SP d 00100111 d 4 f o ALTD 01110110 2 AND HL 10100110 fr L 0 AND IX d 11011101 10100110 d 9 fr s 0 AND IV d 11111101 10100110 d 9 fr s LO AND HL DE 11011100 2 fr L 0 AND IX DE 11011101 11011100 4 f L0 AND IY DE 11111101 11011100 4 f L0 AND n 11100110 n 4 fr L 0 AND r 10100 r 2 fr L0 BIT b HL 11001011 01 b 110 7 f s BIT b IX d 11011101 11001011 d 01 110 10 f
21. 132 Rabbit 3000 Microprocessor 9 4 Parallel Port D Parallel Port D shown in Figure 9 1 has eight pins that can be programmed individually to be inputs or outputs When programmed as outputs the pins can be individually selected to be open drain outputs or standard outputs Port D pins can be addressed by bit if desired The output registers are cascaded and timer controlled making it possible to generate precise timing pulses Port D bits 4 and 5 can be used as alternate bits for Serial Port B and bits 6 and 7 can be used as alternate bits for Serial Port A Alternate serial port bit assignments make it possible for the same serial port to connect to different communi cations lines that are not operating at the same time On reset the data direction register is zeroed making all pins inputs In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with port D are not initialized on reset Table 9 7 Parallel Port D Registers Register Name Mnemonic I O address R W Reset Port D Data Register PDDR 0x60 R W XXXXXXXX Port D Control Register PDCR 0x64 W xx00xx00 Port D Function Register PDFR 0x65 w XXXXXXXX Port D Drive Control Register PDDCR 0x66 w XXXXXXXX Port D Data Direction Register PDDDR 0x67 w 00000000 Port D Bit 0 Register PDBOR 0x68 W XXXXXXX
22. 85112 oad Lad YMS OVI Zad Qus LYI edd 0VS vad LVS Sad 99 N LLV3AV IS SVI 184 HLGOV vid VLQOV 93 94d VZQOV 144 OISSA VSSIO IOE1 A11 A9 A8 A13 A14 VSSCORE VDDCORE A17 IWEO A18 A16 A15 A12 VDDIO VSSIO AT A6 A5 4 PC0 TXD PC1 RXD VSSCORE VDDCORE PC2 TXC PC3 RXC PC4 TXB PC5 RXB PC6 TXA PC7 RXA VDDIO 3 4 5 6 7 8 21 22 23 24 25 26 28 29 VDDIO CLK ICS2 STATUS IOE0 A10 ICS0 VDDCORE VSSCORE A1 A2 A3 VDDCORE VSSCORE 7 PE7 5 5 4 4 Iscs INT1B INTOB OISSA 09 44191 LSd AXL 9d 0dd Lad vad axiv Sad 9 VXLV Gd Z81715 OISSA LSO 13S134 03QOWS yaaouws LNOIGM quor UMOH 9d IAIL S9d 99d 1 29 03d Ol V
23. BIT b IY d 11111101 11001011 d 01 110 10 f BIT b r 11001011 01 b r 4 f ko BOOL HL 11001100 2 fr 00 BOOL IX 11011101 11001100 4 f 00 BOOL IY 11111101 11001100 4 f 00 CALL mn 11001101 n m 12 00111111 2 CP HL 10111110 5 f IX d 11011101 10111110 d 9 f 11111101 10111110 d 9 f CP n 11111110 n 4 f k k V CP r 10111 r 2 f k k V CPL 00101111 2 r DEC HL 00110101 8 f V DEC IX d 11011101 00110101 d 12 f b V DEC IY d 11111101 00110101 d 12 f b V DEC IX 11011101 00101011 4 DEC IY 11111101 00101011 4 DEC r 00 r 101 2 fr V DEC ss 00ss1011 2 r ss 00 BC 01 DE 10 HL 11 SP DJNZ j 00010000 1 2 5 r EX SP HL 11101101 01010100 15 r EX SP IX 11011101 11100011 15 EX SP IY 11111101 11100011 15 User s Manual 263 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A ISZVC EX AF AF 00001000 2 EX DE HL 11101011 2 s mee EX DE HL 11100011 2 s EX DE HL 01110110 11100011 4 EX DE HL 01110110 11100011 4 anpa EXX 11011001 2 INC HL 00110100 8 f b Vv INC IX d 11011101 00110100 d 12 f b V INC IY d 11111101 00110100 d 12 f b V INC IX 11011101 00100011 4 FI om 105 INC IY 11111101 00100011 4 vm um INC
24. Distributed by JAMECO ELECTRONICS www Jameco com 1 800 831 4242 The content and copyrights of the attached material are the property of its owner E Semiconductor RABBIT 3000 AT56C55 A1D2583 0209 Rabbit 30009 Microprocessor User s Manual 019 0108 040731 O Rabbit 3000 Microprocessor User s Manual Part Number 019 0108 040731 0 Printed in U S A 2002 2004 Rabbit Semiconductor rights reserved Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semiconductor Dynamic C is a registered trademark of Z World Inc Rabbit Semiconductor 2932 Spafford Street Davis California 95616 6800 USA Telephone 530 757 8400 Fax 530 757 8402 www rabbitsemiconductor com Rabbit 3000 Microprocessor TABLE OF CONTENTS Chapter 1 Introduction 1 1 1 Features and Specifications Rabbit 3000 u enne nee 2 1 2 Summary of Rabbit 3000 Advantages eene enne nennen trennen nnne 6 1 3 Differences Rabbit 3000 vs Rabbit 2000 essere eene nennen entente 7 Chapter 2 Rabbit 3000 Design Features 9 2 1 The Rabbit 8 bit Processor vs Other Processors enne nennen ennt 10 2 2 Overview of On Chip Peripherals and Features
25. Register Name Mnemonic O Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Real Time Clock Control Register RTCCR 0x0001 W 00000000 Real Time Clock Byte 0 Register RTCOR 0x0002 R W XXXXXXXX Real Time Clock Byte 1 Register RTCIR 0x0003 R XXXXXXXX Real Time Clock Byte 2 Register RTC2R 0x0004 R XXXXXXXX Real Time Clock Byte 3 Register RTC3R 0x0005 R XXXXXXXX Real Time Clock Byte 4 Register RTC4R 0x0006 R XXXXXXXX Real Time Clock Byte 5 Register 5 0 0007 R XXXXXXXX Watchdog Timer Control Register WDTCR 0x0008 W 00000000 Watchdog Timer Test Register WDTTR 0x0009 W 00000000 Global Clock Modulator 0 Register GCMOR 0x000A W 00000000 Global Clock Modulator 1 Register GCMIR 0x000B W 00000000 Secondary Watchdog Timer Register SWDTR 0x000C W 11111111 Global Power Save Control Register GPSCR 0x000D W 00000000 Global Output Control Register GOCR 0 000 W 00000000 Global Clock Double Register GCDR 0x000F W 00000000 Global ROM Configuration Register GROM 0x002C R 0xx00000 Global RAM Configuration Register GRAM 0x002D R 0xx00000 Global CPU Configuration Register GCPU 0 002 R 0 00001 Global Revision Register GREV 0x002F R 0xx00001 MMU Instruction Data Register MMIDR 0x0010 R W 00000000 User s Manual 327 Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset M
26. u A A CIE E EE DUE 21 3 2 Memory Mapping n 23 2 2 1 Extended Code Space eet cade e e pi a Pn 26 3 2 2 Separate I and D Space Extending Data Memory 2 27 3 2 3 Using the Stack Segment for Data Storage 29 3 2 4 Practical Memory Considerations 222 44 4 2 0 00 30 3 3 Instruction Set Outline uu aa Sab dee in ote ideis ros 32 3 3 1 Load Immediate Data to a Register aa 33 3 3 2 Load or Store Data from or to a Constant Address 33 3 3 3 Load or Store Data Using an Index Register nre 34 3 3 4 Register to Register MOVE eerie tree tnn bares eae EL dej aUa E 35 33 9 Register Exchanges Jeter tree erre UR Ee Pte Eee lites teta ele nte 35 3 3 6 Push and Pop Instructions ek ER Ir Dank brem rn 36 3 3 7 16 bit Arithmetic and Logical Ops l enne ener nennen en nennen en 36 3 3 8 Input Output Instructions 0000 ntnnte nte ntennenteetteten te 39 3 4 How to Do It in Assembly Language Tips and
27. Rx Read the data from the SBDR or SBAR Serial Port B Tx Write data to the SBDR SBAR SBLR or write a dummy byte to the SBSR Rx Read the data from the SCDR or SCAR Serial Port C Tx Write data to the SCDR SCAR SCLR or write a dummy byte to the SCSR Rx Read the data from the SDDR or SDAR Lowest Serial Port D Tx Write data to the SDDR SDAR SDLR or write a dummy byte to the SDSR User s Manual 323 C 4 Using the System User Mode The System User mode is designed to work with new features in the Rabbit 3000A memory protection stack protection etc to provide a seamless framework for protection of critical code However there are many levels at which the System User mode can be used some examples are described here C 4 1 Memory Protection Only At the beginning of the user program all necessary peripherals are enabled all peripheral interrupts to be used are set up for the User mode critical memory regions are protected stack limits are set and the various system memory stack violation interrupts are enabled The processor then enters the User mode and remains in the User mode for all operations interrupts can be handled however the user desires Obviously the critical interrupts can be handled in the System mode but at that point the device is typically reset and the error is logged An overview of this level of operation is shown in Figure C 2 System Mode User Mode Application
28. Bus The Rabbit 3000 instruction set supports memory access and 1 access Memory access takes place in a 1 megabyte memory space I O access takes place in a 64K I O space In a traditional microprocessor design the same address and data lines are used for both mem ory and I O spaces Sharing address and data lines in this manner often forces compromises or makes design more complicated Generally the memory bus has more critical timing and less tolerant of additional capacitive loading imposed by sharing it with an I O bus With the Rabbit 3000 the designer has the option of enabling completely separate buses for I O and memory The auxiliary I O bus uses many of the same pins used by the slave port so its operation is mutually exclusive from operation of the slave port Parallel Port A is used to provide 8 bidirectional data lines Parallel Port B bits 2 7 provide 6 address lines the least significant 6 lines of the 16 lines that define the full I O space The auxil iary bus is only active on I O bus cycles The address lines remain in the same state assumed at the end of the previous I O cycle until another I O cycle takes place I O chip selects as well as read and write strobes are available at various other pins so that the 64 byte space defined by the 6 address lines may be easily expanded I O cycles also execute in parallel on the main memory bus when they take place on the auxiliary bus so addi tional address lines can be buffered
29. Clock to Address Output Delay Spectrum Spreader Delay ns Data Setup ns VDD Time Delay N orma ron 30pF 60 90pF ns B no dbl dbl no dbl dbl 3 3 6 8 11 1 3 4 5 4 5 9 2 7 7 10 13 1 5 3 5 5 5 5 5 11 2 5 8 11 15 1 5 4 6 6 12 1 8 18 24 33 3 8 12 11 22 When the spectrum spreader is enabled with the clock doubler every other clock cycle is shortened sometimes lengthened by a maximum amount given in the table above The shortening takes place by shortening the high part of the clock If the doubler is not enabled then every clock is shortened during the low part of the clock period The maxi mum shortening for a pair of clocks combined is shown in the table 216 Rabbit 3000 Microprocessor CLK A 19 0 Memory Read no wait states k 1 2 gt lt T adr OEx ToEgx lt gt lt D 7 0 A 19 0 CSx ANEx D 7 0 gt lt Tosx Tsetup gt lt Tcsx Mar gt lt Memory Write extra wait states Figure 16 2 Memory Read and Write Cycles Figure 16 2 and Figure 16 3 illustrate the memory read and write cycles The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified User s Manual 217 The following memory read time delays were measured Table 16 3 Memory Read Time Delays Output C
30. DE HL N A AN A A N A Gg a a N g ANA A A ANN fr fr fr fr fr H gt t yy yy BC DE SP SP SP d d 0 to 255 HL HL amp DE IX IX amp DE amp DE if HL 0 HL 1 set flags to match HL if IX 0 IX 1 if IY 0 IY 1 IX IX 1 1 ss ss 1 ss BC DE HL SP IX IX 1 IY 1 SS ss 1 ss BC DE HL SP HL BC BC DE signed 32 bit result DE unchanged HL HL DE bitwise or IX IX DE IY IY DE CY DE DE CY left shift with CF HL CX CY HL ix cv CY IX Iv cx cv iv HL HL ss CY cout if gt 1 19 10 8 bit Arithmetic and Logical Ops Instruction ADC A HL ADC A IX d ADC A IY d ADC A n ADC A r ADD A HL ADD A IX d ADD A IY d ADD A n ADD A r AND HL AND IX4d AND IY d AND n AND r CP HL CP IX d CP IY d clk O N g O WO N gB UN PF A fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr f f f m m uH m 4 0E F NI lt 4 lt lt RPRPP RP lt q lt q lt lt lt lt lt lt
31. TOLERANCE AND SOLDER JOINT ANALYSIS Jr 0 29 0 55 mm 0 29 0 604 mm Jg 0 01 0 077 mm Lmin 2 16 85 mm Gmin 13 75 mm 0 28 i Side Fillet Toe Fillet Heel Fillet J Solder fillet min max toe heel and side respectively L Toe to toe distance across chip S Heel to heel distance across chip T Toe to heel distance on pin W Width of pin Figure 5 3 PC Board Land Pattern for Rabbit 3000 128 pin LQFP 58 Rabbit 3000 Microprocessor 5 2 Ball Grid Array Package 5 2 1 Pinout Rabbit 3000 56 55 171 IZ2T 128 pin Thin Map Ball Grid Array TFBGA 10 x 10 Body 0 8 mm pitch LLI x o hat N Lo e e e LLI O O Oz Oz Ox O O amp Os gt x o x u lt 8 Q2 O O QE O O O8 x lt amp 2 2 gt gt ac On OF OF OF OF 2 OF OF UF 08 a a a lt a lt a a gt gt gt gt 2 OZ OF OF OF O2 Os O8 08 Oz Os Os Of Oz OF Oz O OF OF OF OF e Oe O lt x Oz Og O Oz a x x gt N ome O OF Of O n A a gt m m a a Dn Dn n n N Qe Qe Of Os n n Dn n O O O O gt n n n 2 5 O8 O8 OF 8 08 O Og _ 2 lu m o a a E o o u gt gt c z a z Of O OF
32. LO OR HL DE 11101100 2 fr L0 OR IX DE 11011101 11101100 4 f L0 OR IY DE 11111101 11101100 4 f L0 OR n 11110110 n 4 fr L0 OR r 10110 r 2 fr L0 POP IP 11101101 01111110 7 POP IX 11011101 11100001 9 POP IY 11111101 11100001 9 POP zz 11220001 7 r PUSH IP 11101101 01110110 9 PUSH IX 11011101 11100101 12 PUSH IY 11111101 11100101 12 PUSH zz 11220101 10 RES b HL 11001011 10 b 110 10 d RES b IX d 11011101 11001011 d 10 b 110 13 d RES b IY d 11111101 11001011 d 10 b 110 13 d RES b r 11001011 10 b r 4 r RET 11001001 8 RET f 11 f 000 8 2 RETI 11101101 01001101 12 RL HL 11001011 00010110 10 f b L RL IX d 11011101 11001011 d 00010110 13 f b L RL IY d 11111101 11001011 d 00010110 13 f b L RL DE 11110011 2 fr L RL r 11001011 00010 4 fr L RLA 00010111 2 fr RLC HL 11001011 00000110 10 f b L RLC IX d 11011101 11001011 d 00000110 13 f b L RLC IY d 11111101 11001011 d 00000110 13 f b L RLC r 11001011 00000 4 fr L RLCA 00000111 2 fr RR HL 11001011 00011110 10 f b L RR 11011101 11001011 d 00011110 13 f b L RR IY d 11111101 11001011 d 00011110 13 f b L RR DE 11111011 2 fr L RR HL 11111100 2 fr L RR IX 11011101 11111100 4 f L RR IY 11111101 111111
33. adr 0x070 PEFR W alt I7 alt I6 alt I5 alt I4 alt I3 alt I2 alt I1 alt IO adr 0x075 PEDDR W dir dir dir dir dir dir dir dir adr 0x077 out out out out out out out out PEBOR W x x x X X X X PEO adr 0x078 PEBIR W x x x x x x 1 x adr 0x079 PEB2R W x x x x x PE2 x x adr 0x07A PEB3R W X X X X PE3 X X X adr 0x07B PEB4R W x x x PE4 x x x x adr 0x07C PEBSR W x x PE5 x x x x x adr 0x07D PEB6R W x PE6 x x x x x x adr 0x07E PEB7R W PE7 x x x x x x x adr 0 07 Table 9 12 Parallel Port E Control Register adr 0x074 Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 00 clock lower nibble on pclk 2 01 clock on timer A1 01 clock on timer A1 n 10 clock on timer B1 iia 10 clock on timer B1 11 clock on timer B2 11 clock on timer B2 User s Manual 139 9 6 Parallel Port F Parallel Port F is a byte wide port with each bit programmable for data direction and drive These are simple inputs and outputs controlled and reported in the Port F Data Register As outputs the bits of the port are buffered with the data written to the Port F Data Regis ter transferred to the output pins on a selected timing edge The outputs of Timer A1 Timer B1 or Timer B2 can be used for this function with each nibble of the port having separate select field to control this timing
34. e the clock asymmetry is 52 48 resulting in a loss of 4 of the clock period or 1 4 ns The output enable access time is given by access time T min clock low clock to output enable spreader delay asymmetry delay data setup time 34 ns 12 8 ns 5 ns 3 ns 1 36 ns 1 ns 36 5 ns 222 Rabbit 3000 Microprocessor 16 2 I O Access Time Figure 16 6 illustrates the I O read and write cycles External I O Read no extra wait states T1 gt lt Tw gt lt T2 gt ad LI LI D A 15 0 Tadr ICSx Tcsx joe SX gt Tlocsx gt NORD TioRDI BUFEN BUFEN JBUFEN gt setup lt D 7 0 holdi External I O Write no extra wait states T1 gt lt Tw gt lt T2 gt al Lt ty E A 15 0 Tad r Seis T 1 3 LX lt gt Tesx Tcsx hocsx X 21 Tlocsx Tlocsx lt BUFEN TBUFEN TBUFEN gt D 7 0 TpHzv Figure 16 6 I O Read and Write Cycles No Extra Wait States NOTE IOCSx be programmed to be active low default or active high User s Manual 223 The following I O read time delays were measured Table 16 5 I O Read Time Delays Output Capacitance Time Delay 30pF 60pF 90pF Max clock to address delay T a 6 ns 8 ns 11 ns Max clock to memory chip select delay Tcsx 6 ns 8 n
35. ipeo DR ERO Aer U ra DET HERE EEEE 182 12 7 Clocked Serial Timing cider eoo ie eode te eitis 185 12 7 1 Clocked Serial Timing With Internal Clock seen 185 12 7 2 Clocked Serial Timing with External Clock essere 185 12 8 Synchronous Communications on Ports E and 187 12 9 Serial Port Software 8 40100 0 eee etre inen enne trennen 192 12 9 1 Controlling an RS 485 Driver and Receiver essen 193 12 9 2 Transmitting Dummy Characters era een ae o rennen nennen nennen 193 12 9 3 Transmitting and Detecting a Break nennen 194 12 9 4 Using A Serial Port to Generate a Periodic Interrupt esses 194 12 9 5 Extra Stop Bits Sending Parity 9th Bit Communication Schemes sess 194 12 9 6 Parity Extra Stop Bits with 7 Data Bit Characters sese 195 12 9 7 Parity Extra Stop Bits with 8 Data Bit Characters sese 195 12 9 8 Supporting 9th Bit Communication Protocols 196 12 9 9 Rabbit Only Master Slave Protocol n 196 12 9 10 Data Framing Modbus eese nennen eren eee enne enint 196 Chapter 13 Rabbit Slave Port 199 13 1 Hardware Design of Slave Port Interconnection 00422 44 010 204 13 2 Slave Port Registers see eee Ouen ente te
36. l I SPSR reads register register register register register register 13 3 Applications and Communications Protocols for Slaves The communications protocol used with the slave port depends on the application A slave processor may be used for various reasons Some possible applications are listed below Keep in mind that the Rabbit can also be operated as a slave processor via a serial port and some of the protocols will work well via a serial communications connection If a serial connection is used the protocol becomes more complicated if errors in transmission need to be taken into account If the physical link can be controlled so that transmission errors do not occur a realistic possibility if the interconnection environment is controlled the serial protocol is simpler and faster than if error correction needs to be taken into account 13 3 1 Slave Applications e Motion Controller Many types of motion control require fast action may be com pute intensive or both Traditional servo system solutions may be overly expensive or not work very well because of system nonlinearities The basic communications model for a motion controller is for the master to send short messages positioning com mands to the slave The slave acknowledges execution of the commands and reports exception conditions e Communications Protocol Processor Communications protocols may be very com plex may require
37. this line is normally connected to the global I O read strobe IORD e SWR Input If SCS is also low this line causes the data bits on the data bus to be clocked into the register selected by the address lines on the rising edge of SWR or SCS whichever rises first If a Rabbit is used as a master this line is normally con nected to the global I O write strobe IOWR User s Manual 203 e SLAVEATTN This line is set low asserted if the slave writes to the SPDOR register This line is set high if the master writes anything to the slave status register This line is usually connected to cause the master to be interrupted when it goes low The data lines of the slave port are shared with Parallel Port A that uses the same package pins The slave port can be enabled and Parallel Port A be disabled by storing an appro priate code in the slave port control register SCR After the processor is reset all the pins belonging to the slave interface are configured as parallel port inputs unless SMODEI SMODE O are set to 0 1 in which case the slave port is enabled after reset and the slave starts the cold boot sequence using the slave port 13 1 Hardware Design of Slave Port Interconnection Figure 13 4 shows a typical circuit diagram for connecting two slave Rabbits to a master Rabbit The designer has the option of cold booting the slave and downloading the pro gram to RAM on each cold start Another option is to configure the
38. 00000000 Parallel Port G User Enable Register PGUER 0x0348 W 00000000 Input Capture User Enable Register ICUER 0x0358 W 00000000 I O Bank User Enable Register IBUER 0x0380 W 00000000 PWM User Enable Register PWUER 0x0388 W 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0 03 0 W 00000000 Timer B User Enable Register TBUER 0 03 0 W 00000000 Serial Port A User Enable Register SAUER 0 03 0 W 00000000 Serial Port B User Enable Register SBUER 0 3 W 00000000 Serial Port C User Enable Register SCUER 0x3E0 W 00000000 Serial Port D User Enable Register SDUER 0x3F0 W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port F User Enable Register SFUER 0x3D8 W 00000000 User s Manual 319 The I O banks on Port E enabled for the User mode by IBUER have a slightly different operation in the User mode Disabling user access to a given I O bank not only causes writes to the corresponding IBxCR register to be ignored in the User mode but also inhib its the strobe associated with that I O bank Access to the internal I O registers listed in Table C 4 is always denied in the User mode Table C 4 I O Addresses Inaccessible in User Mode Register Name Mnemonic Address Global Con
39. 50 variation since it depends on process parameters temperature and voltage The times given above are for a supply voltage of 3 3 V and a temperature of 25 C The doubled clock low time increases by 20 when the voltage is reduced to 2 5 V and increases by about 40 when the voltage is reduced fur ther to 2 0 V The values increase or decrease by 196 for each 5 C increase or decrease in temperature The doubled clock is created by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a slightly different length Since the duty cycle of the built in oscillator can be as asymmetric as 52 48 the clock generated by the clock doubler will exhibit up to a 4 84 Rabbit 3000 Microprocessor variation in period on alternate clocks This does not affect the no wait states memory access time since two adjacent clocks are always used However the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler The only signals clocked on the falling edge of the clock are the memory and I O write pulses and the early option memory output enable See Chapter 8 for more information on the early output enable and write enable options The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi mum of 3 ns for the normal spreading and 4 5 ns for the strong spreading If the clock dou bler is used this wil
40. A6 from Al yes Serial Port C AT from Al yes Serial Port D no Input Capture A9 none no Pulse Width Modulator A10 none no Quadrature Decoder The control status register for Timer A TACSR is laid out as shown in Table 11 3 Table 11 3 Timer A Control and Status Register Timer A Control and Status Register TACSR Address 0x00A0 Bit s Value Description 7 0 7 counter has not reached its terminal count read 1 7 count done This status bit is cleared by a read of this register 7 0 AT interrupt disabled write 1 A7 interrupt enabled 6 0 A6 counter has not reached its terminal count read 1 count done This status bit is cleared by a read of this register 6 0 A6 interrupt disabled write 1 A6 interrupt enabled 5 0 A5 counter has not reached its terminal count read 1 5 count done This status bit is cleared by a read of this register 5 0 A5 interrupt disabled write 1 A5 interrupt enabled 4 0 A4 counter has not reached its terminal count read 1 A4 count done This status bit is cleared by a read of this register 152 Rabbit 3000 Microprocessor Table 11 3 Timer Control and Status Register continued Timer A Control and Status Register TACSR Address 0x00A0 Bit s Value Description 4 0 A4 interrupt disabled write 1 A4 interrupt enabled 3
41. CLKD Clock for clocked mode bidirectional Serial Port E TXE Serial Transmit Out RXE Serial Transmit In TCLKE Optional external transmit clock RCLKE Optional external receive clock User s Manual 161 Table 12 1 Serial Port Signals continued Serial Port Signal Name Function Serial Port F TXF Serial Transmit Out RXF Serial Transmit In TCLKF Optional external transmit clock RCLKF Optional external receive clock Figure 12 1 shows a block diagram of the serial ports Input to timers perclk or perclk 2 or prescaled Timer 1 Timer A4 Serial Port Timer A5 Serial Port B Timer A6 Serial Port C Timer A7 Serial Port D Timer A2 Timer A3 Serial Port E Serial Port F Figure 12 1 Block Diagram of Rabbit Serial Ports 162 Rabbit 3000 Microprocessor The individual serial ports are capable of operating at baud rates in excess of 500 000 bps in the asynchronous mode and 8 times faster than that in the synchronous mode Either 7 or 8 data bits may be transmitted and received in the asynchronous mode The so called Oth bit or address bit mode of operation is also supported The 9th bit can be set high or low by accessing the appropriate serial port register Alt
42. Critical code interrupts Critical Interrupts Interrupts Figure C 2 System User Mode Setup for Memory Protection Only 324 Rabbit 3000 Microprocessor C 4 2 Mixed System User Mode Operation This mode is similar to the previous mode but with some portions of the program written for the System mode for example peripheral interrupts where latency is critical By keeping the System mode code sections small potential system crashes are still mini mized An overview of this level of operation is shown in Figure C 3 System Mode User Mode Return from interrupts Application Critical code interrupts User defined interrupts Time critical interrupts Critical Interrupts Figure C 3 System User Mode Setup for Mixed Operation User s Manual 325 C 4 3 Complete Operating System This section describes a full use of the System User mode separating all common functions into a System mode operating system while letting the application specific code run in the User mode By default the System mode handles all peripherals and inter rupts as well as high level interfaces such as a flash file system However the processor will be running the application code in the User mode most of the time The application code can request direct access to a peripheral and or interrupt from the System mode If allowed the System mode can create an interrupt vector as described in Section C 3 that will execute the user code
43. Generally the oscillator will not start unless the voltage is about 1 4 V However the oscil lator will continue to run until the voltage drops to about 0 8 V If the oscillator stops the current draw is very much lower than when it is running Below about 1 4 V most of the current draw is used to charge and discharge the capacitive load The current consumed by the battery backed portion of the Rabbit 3000 which is driven by the 32 768 kHz oscillator is given by Lap uA 0 91 x V 104x V V5 L14 V The current is negligible for V 1 14 V a Total Battery Backed m Rabbit 3000 Real Time Clock e Tiny Logic 32 kHz Osc Current pA Q ah 4545 9 7 ah ae 29 us Battery Backup Voltage V Figure 16 12 Current Consumption Real Time Clock and 32 kHz Oscillator Circuit User s Manual 235 16 10 Reduced Power External Main Oscillator The circuit in Figure 16 13 can be used to generate the main clock using less power than with the built in oscillator buffer The power consumption is less because of the current limiting resistors that cannot be used with the built in buffer The 2 2 kQ series resistor must be reduced as the clock frequency increases as must be the current limiting resistors Optional current reducing resistors gt To Rabbit 3000 XTALA1 2 2 33 pF 3 3 V SN74HCT1G04DBVR L 3 68 MHz
44. PEO pulse catcher INTOB PE4 pulse catcher O interrupt acknowledge Figure 7 6 External Interrupt Line Logic The external interrupts take place on a transition of the input which is programmable for rising falling or both edges The pulse catchers are programmable separatelv to detect a rising falling or either edge in the input Each of the interrupt pins has its own catcher device to catch the edge transition and request the interrupt When the interrupt takes place both pulse catchers associated with that interrupt are auto maticallv reset If both edges are detected before the corresponding interrupt takes place because the triggering edges occur nearly simultaneously or because the interrupts are inhibited by the processor priority then there will be only one interrupt for the two edges detected The interrupt service routine can read the interrupt pins via Parallel Port E and determine which lines experienced a transition provided that the transitions are not too fast Interrupts can also be generated by setting up the matching port E bit as an output and toggling the bit External interrupts are cleared automaticallv during the processor Interrupt Acknowledge cvcle The Interrupt Acknowledge cvcle will alwavs immediatelv follow an Instruction Fetch 1 cycle This instruction byte is ignored and will be the first byte fetched upon returning from the interrupt Interrupt
45. SPDIR is used to send or receive data characters or control bytes The line SLAVEATTN is wired to the external interrupt request of the master so that the master is interrupted when the slave writes to SPDOR Typically the slave will write to SPDOR when there is a change of status on one of the serial ports The slave can interrupt the master at any time by storing to SPDOR It will do this every time an enabled transmitter is ready to accept a character or every time an enabled receiver receives a character When it stores to SPDOR it will store a code indicating the reason for the interrupt that is receive or transmit and channel number If the cause is receive the received character will also be placed in SPDIR writable by the slave When the master is interrupted for any reason the master will sneak a peek at SPDOR by reading SPSR If the interrupt is caused by a receive character it will remove the character from SPDIR and read SPDOR to handshake with the slave If the master is interrupted for transmitter ready as determined by the sneak peek it will place the outgoing character in SPDIR and write a code to SPDOR indicating transmit and channel number This will cause the slave to be interrupted and the slave will take the character and handshake by reading SPDOR This handshake does not interrupt the master 208 Rabbit 3000 Microprocessor 14 RABBIT 3000 CLocks The Rabbit 3000 normally uses two clocks the main clock and the
46. The V flag is set when BC transitions from 1 to 0 If the V flag is not set another step is performed for the repeating versions of the instructions Interrupts can occur between dif ferent repeats but not within an iteration equivalent to LDD or LDI Return from the inter rupt is to the first byte of the instruction which is the I O prefix byte if there is one A new LDIR LDDR bug was discovered in September 2002 The problem has to do with wait states and the block move operations With this problem the first iteration of LDIR LDDR uses the correct number of wait states for both the read and the write How ever all subsequent iterations use the number of waits programmed for the memory located at the write address for both the read and the write cycles This becomes a problem when moving a block of data from a slow memory device requiring wait states to a fast memory device requiring no wait states With respect to external I O operations the LDIR or LDDR performs reads with zero wait states independent of the waits programmed for the I O for all but the first iteration The first iteration is correct This bug is automatically cor rected by Dynamic C and will be fixed in future generations of the chip 256 Rabbit 3000 Microprocessor 19 17 Control Instructions Jumps and Calls Instruction CALL mn DJNZ J JP HL JP IX JP IY JP f mn JP mn JR cc e JR e LCALL xpc mn LJP xpc mn LRET RET RET f RETI RST v
47. The peripherals clocked by these timers can generate interrupts but the timers themselves cannot Furthermore these timers cannot be cascaded with Timer A1 11 1 1 Timer A I O Registers The I O registers for Timer A are listed in Table 11 1 Table 11 1 Timer A I O Registers Register Name Mnemonic I O address R W Reset Timer A Control Status Register TACSR 0 R W 00000000 Timer A Prescale Register TAPR OxA1 W XXXXXXX 1 Timer A Time Constant Register TATIR 0 Timer A Control Register TACR OxA4 W 00000000 Timer A Time Constant 2 Register TAT2R OxA5 W XXXXXXXX Timer A Time Constant 8 Register TAT8R OxA6 w XXXXXXXX Timer A Time Constant 3 Register TAT3R OxA7 w XXXXXXXX Timer A Time Constant 9 Register TAT9R 8 W XXXXXXXX Timer A Time Constant 4 Register TAT4R OxA9 W XXXXXXXX Timer A Time Constant 10 Register TATIOR OxAA W XXXXXXXX Timer A Time Constant 5 Register TATSR OxAB w XXXXXXXX Timer A Time Constant 6 Register TAT6R OxAD W XXXXXXXX Timer A Time Constant 7 Register TAT7R OxAF W XXXXXXXX User s Manual 151 The following table summarizes Timer A s capabilities Table 11 2 Timer A Capabilities Timer Cascade Interrupt Dedicated Connection AI none yes Parallel Ports D G Timer B A2 from Al yes Serial Port E A3 from Al yes Serial Port F A4 from Al yes Serial Port A A5 from Al yes Serial Port B
48. Thus the clock speed at 3 3 V will be about 2 3 of the clock speed at 5 V The operating current is reduced in proportion to the operating voltage The Rabbit 3000 does not have a standby mode that some microprocessors have Instead the Rabbit has the ability to switch its clock to the 32 768 KHz oscillator This is called the sleepy mode When this is done the power consumption is decreased dramatically The current consumption is often reduced to the region of 100 u A at this clock speed The Rabbit executes about 6 instructions per millisecond at this low clock speed Generally when the speed is reduced to this extent the Rabbit will be in a tight polling loop looking for an event that will wake it up The clock speed is increased to wake up the Rabbit 210 Rabbit 3000 Microprocessor 15 EMI CONTROL EMI or electromagnetic interference from unintentional radiation is of concern to the microprocessor system designer One concern is passing the tests sometimes required by the U S Federal Communications Commission FCC or by the European EMC Directive For example in the U S the FCC requires that computing devices intended for use in the home or in office environments but not industrial or medical environments not have unintentional electromagnetic radia tion above certain limits of field strength that depend on frequency and whether the device is intended for home or office use This is verified by measuring radiation from the de
49. between their baud rates Thus the receiver full and transmitter empty interrupts will become out of phase with each other assuming that the remote station transmits without gaps between characters A counter is zeroed each time a character is received and the counter is incremented each time a character is transmitted If this counter holds n this indicates that a gap has been detected in the frame the length of the gap is n 1 to n characters The start of frame could be marked by n reaching 3 indicating that the existence of a gap at least two characters long User s Manual 197 198 Rabbit 3000 Microprocessor 13 RABBIT SLAVE PoRT When a Rabbit microprocessor is configured as a slave Parallel Port and certain other data lines are used as communication lines between the slave and the master The slave unit is a Rabbit configured as a slave The master can be another Rabbit or any other type of processor Rabbits configured as slaves can themselves have slaves The master and slave communicate with each other via the slave port The slave port is a physical device that includes data registers a data bus and various handshaking lines The slave port is a part of the slave Rabbit but logically it is an independent device that is used to communicate between the two processors A diagram of the slave port is shown in Figure 13 1 SD0 SD7S Y SA1 A SA0 y SWR SRD SCS SL
50. directly to the memory chips Memory Memory Processor Mapping Interface Unit Unit Figure 8 3 Overview of Rabbit Memory Mapping 8 3 Memory Mapping Unit The 64K 16 bit address space accessed by processor instructions is divided into segments Each segment has a length that is a multiple of 4K Except for the extended code segment the segments have adjustable sizes and some segments can be reduced to zero size and thus vanish from the memory map The four segments are shown in the example in Figure 8 4 The segment size register SEGSIZE determines the boundaries marked in the diagram The extended code seg ment always occupies the addresses 0 0 000 0 The stack segment stretches from the address specified by the upper 4 bits of the SEGSIZE register to OXODFFF For exam ple if the upper 4 bits of SEGSIZE are 0x0D then the stack segment will occupy OxODO00 0xODFFF or If the upper 4 bits of SEGSIZE are greater than or equal to OxOE the stack segment vanishes If these bits are set to zero the two segments below the stack segment will vanish The lower 4 bits of SEGSIZE determine the lower boundary shown in the figure If this boundary is equal to the upper boundary or greater than OxOE the data segment will van ish If this segment is placed at zero the code segment will vanish User s Manual 117 Boundary SEGSIZE 4 7 Boundary SEGSIZE 0 3 XPC STACKS
51. rette RO e iet ue 54 Chapter 5 Pin Assignments and Functions 55 5 1 4 ione ga PHP REPE OR ie 56 SRL Pott on oe uie e c o REO a Rise 56 5 1 2 Mechanical Dimensions and Land Pattern 6 57 2 2 Ball Grid Array Package esee gen L ek 59 29 2 T Pinot us ia B eere perperam opm te 59 5 2 2 Mechanical Dimensions and Land Pattern essent 60 5 3 Rabbit Pin Desc Iptions n a L eene nennen trennen nente SSS nenne trennen A entres 62 DA Bus TIMAS tette ee e ee i e d bici e Ee e e ron tei 64 5 5 Description of Pins with Alternate Functions 65 2 6 DC Characteristics snc e 68 5 7 I O Buffer Sourcing and Sinking Limit n eee 69 Chapter 6 Rabbit Internal I O Registers 71 6 1 Default Values for all the Peripheral Control Registers sees 73 Chapter 7 Miscellaneous Functions 79 7 Y Processor Identification e eet ated ee ntt eate aie A Iti d teen 79 7 2 Rabbit Oscillators and ClocK8 eene trees ree rer eee tes 80 7 3 Clock Doubler genti LI L athe ieee ates 83 7 4 Clock Spectrum Spreaders sasan asiyiiuspa Cr rte Re Ep ES es 86 7 5 Chip Select Options for Low Power a nennen 87 7 6 Output Pins CLK STATUS WDTOUT BUFEN eene ener nennen nennen nenne 90 7 7 Time Date Clock Real Time Clock
52. slave port control register To make the port an output store 0x084 in SPCR Parallel Port A is set up as an input port on reset When the port is read the value read reflects the voltages on the pins 1 for high and 0 for low This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage NOTE Refer to Section 9 6 1 Using Parallel Port A and Parallel Port F for more information 130 Rabbit 3000 Microprocessor 9 2 Parallel Port B Parallel Port B has eight pins that can programmed individually to be inputs and outputs After reset Parallel Port B comes up as six inputs PB 5 0 and two outputs PB7 and PB6 The output value on pins PB6 and PB7 package pins 99 100 will be low Table 9 3 Parallel Port B Registers Register Name Mnemonic 10 address R W Reset Port B Data Register PBDR 0x40 R W 00 Port B Data Direction Register PBDDR 0x47 W 11000000 Table 9 4 Parallel Port B Register Bit Functions Bit7 BitG Bits Bit2 Bit 0 PBDR R W PB7 5 PB4 PB3 PB2 1 adr 0x040 2 dips des ji diez dir dires jir dip adr 2 0x047 out out out out out out out out When the auxiliary I O bus is enabled Parallel Port B bits 2 7 provide 6 address lines the least significant 6 lines of the 16 lines that define the full I O spac
53. the D space is to invert either A16 or A19 for data accesses The inversion may be speci fied separately for the root segment and the data segment Normally A16 is inverted for data accesses in the root segment This causes data accesses to the root segment to be moved 64k higher to a section of flash starting at 20 bit address 64k that is reserved for constant data A19 is normally inverted for data accesses to the data segment causing the data accesses in the data segment to be moved to an address 512k higher in the 20 bit space an address normally mapped to RAM The stack segment and the XPC segment do 28 Rabbit 3000 Microprocessor not have split I and D space and memory accesses to these segments do not distinguish between I and D space The advantage of having more root code space is that root code executes faster because short calls using a 16 bit address are used to call it This compares to long calls that have a 20 bit address for extended code Data located in the root can be more conveniently accessed due to the comparatively limited instructions available for accessing data in the full 20 bit space and the greater overhead involve in manipulating 20 bit addresses in a processor that has 8 and 16 bit registers 3 2 3 Using the Stack Segment for Data Storage Another approach to extending data memory is to use the stack segment to access data placing the stack in the data segment so as to free up the stack segment This approach
54. the Port E function register must be set to 1 for each position Each I O bank is selected by the three most significant bits of the 16 bit I O address Table 10 2 shows the relationship between the I O control register and its corresponding space in the 64K address space Table 10 2 External I O Register Address Range and Pin Mapping Control Register Port E I O Address I O Address Pin A 15 13 Range IBOCR PEO 000 0x0000 0x 1 FFF IBICR 1 001 0x2000 0x3FFF IB2CR PE2 010 0 4000 0 5 IB3CR PE3 011 0x6000 0x7FFF IB4CR PE4 100 0x8000 0x9FFF 5 5 101 0xA000 0xBFFF IB6CR PE6 110 0xC000 0xDFFF IB7CR PE7 111 OxE000 0xFFFF User s Manual 147 148 Rabbit 3000 Microprocessor 11 TIMERS There are two timers Timer A and Timer B Timer A is intended mainly for generating the clock for various peripherals baud clock for the serial ports a periodic clock for clocking Parallel Ports D and E or for generating periodic interrupts Timers A1 A7 are general purpose timers and Timers A8 A10 are dedicated to specific peripherals Timer B can be used for the same functions but it cannot generate the baud clock Timer B is more flexible when it can be used because the program can read the time from a continu ously running counter and events can be programmed to occur at a specified future time Timer A System Serial E
55. 0 Carry flag is cleared 1 Carry flag is set The L V logical overflow flag serves a dual purpose L V is set to 1 for logical operations if any of the four most signif icant bits of the result are 1 and L V is reset to O if all four of the most significant bits of the result are 0 User s Manual 261 Symbols Rabbit Z180 Meaning Bit select 000 bit 0 001 bit 1 b b 010 bit 2 011 bit 3 100 bit 4 101 bit 5 110 bit 6 111 bit 7 Condition code select 00 NZ 01 Z 10 NC 11 C d d 7 bit signed displacement Expressed in two s complement dd ww Word register select destination 00 BC 01 DE 10 HL 11 SP dd Word register select alternate 00 BC 01 DE 10 HL e j 8 bit signed displacement added to PC Condition code select 000 NZ non zero 001 Z zero f f 010 NC non carry 011 C carry 100 LZ logical zero 101 2 LO logical one 110 P sign plus 111 M sign minus m m MSB of a 16 bit constant mn mn 16 bit constant n n 8 bit constant or LSB of a 16 bit constant Byte register select 000 B 001 2 C r g g g 010 D 011 100 101 L 11534 ww Word register select source 00 BC 01 DE 10 HL 11 SP Restart address select M 010 0x0020 011 0x0030 100 0x0040 101 0x0050 111 0x0070 XX XX Word register select 00
56. 11 Zero wait states for accesses in this bank 0 Pass A 19 for accesses in this bank d 1 Invert A 19 for accesses in this bank 0 Pass A 18 for accesses in this bank t 1 Invert A 18 for accesses in this bank 00 and WEO are active for accesses in this bank 01 1 and are active for accesses in this bank 3 2 10 OEO only is active for accesses in this bank i e read only Transactions are normal in every other way T 1 only is active for accesses in this bank i e read only Transactions are normal in every other way 00 CSO is active for accesses in this bank 1 0 01 CS1 is active for accesses in this bank Ix CS2 is active for accesses in this bank Bits 7 6 The number of wait states used in access to this quadrant Without wait states read requires 2 clocks and write requires 3 clocks The wait state adds to these numbers Wait states should only be used for memory data accesses RAM or data flash not for memory from which instructions are executed code memory Bits 5 4 These bits allow the upper address lines to be inverted This inversion occurs after the logic that selects the bank register so setting these lines has no effect on which bank register is used The inversion may be used to install a 1M memory chip in the space normally allocated to a 256K chip The larger memory can then be accessed as 4 pages of 256K each There is no effect outside the quadrant that the memory bank contr
57. 17 71 lt gt Tsu SCS i Th SCS SA1 SAO Tsu SA Th SA SRD LL 3 gt Tw SRD I I SD 7 0 Ten SRD I amp gt Tdis SRD I ao Ta SRD SWR Tsu SWR SRD Slave Port Write Cycle SCS _ r lt gt Tsu SCS I lt Th SCs SA1 SAO X Z q Tsu SA s Th SA SWR mwa SA p gt Tw SWR SD 7 0 i gt Tsu SD SRD TENER Tsu SRD SWR Figure 13 2 Slave Port R W Sequencing 200 Rabbit 3000 Microprocessor The following table explains the parameters used in Figure 13 2 Symbol Parameter ase Tsu SCS SCS Setup Time 9 Th SCS SCS Hold Time 0 Tsu SA SA Setup Time 5 Th SA SA Hold Time 0 Tw SRD SRD Low Pulse Width 40 Ten SRD SRD to SD Enable Time 0 Ta SRD SRD to SD Access Time 30 Tdis SRD SRD to SD Disable Time 15 Tsu SRW SRD SWR High to SRD Low Setup Time 40 Tw SWR SWR Low Pulse Width 40 Tsu SD SD Setup Time 10 Th SD SD Hold Time 5 Tsu SRD SWR SRD High to SWR Low Setup Time 40 The two SPDOR registers have special functionality not shared by the other data registers If the master writes to SPDOR an inbound interrupt flip flop is set If slave port interrupts are enabled the slave processor will take a slave port interrupt If the slave writes to the other SPDOR register th
58. 3 5 Register Exchanges Exchange instructions are very powerful because two or more moves are accomplished with one instruction The following register exchange instructions are implemented EX af af exchange af with af EXX exchange HL DE BC with HL DE BC EX DE HL exchange DE and HL The following instructions are unique to the Rabbit EX DE HL 1 byte 2 clocks EX DE HL 2 bytes 4 clocks EX DE HL 2 bytes 4 clocks The following special instructions Rabbit and Z180 Z80 exchange the 16 bit word on the top of the stack with the HL register These three instructions are each 2 bytes and 15 clocks EX SP HL EX SP IX EX SP IY User s Manual 35 3 3 6 Push and Pop Instructions There are instructions to push and pop the 16 bit registers AF HL DC BC IX and IY The registers AF HL DE and BC can be popped Popping the alternate registers is exclusive to the Rabbit and is not allowed on the Z80 Z180 Examples POP HL PUSH BC PUSH IX PUSH af POP DE POP DE POP HL 3 3 7 16 bit Arithmetic and Logical Ops The HL register is the primary 16 bit accumulator IX and IY can serve as alternate accu mulators for many 16 bit operations The Z180 Z80 has a weak set of 16 bit operations and as a practical matter the programmer has to resort to combinations of 8 bit operations in order to perform many 16 bit operations The Rabbit has many new op codes for 16 bit op
59. B A gt B A B 2 gt 12 lt C v 2 If A is in HL and B is in DE these operations be performed as follows assuming that the object is to set HL to 1 or 0 depending on whether the compare is true or false compute HL DE unsigned integers EX DE HL uncomment for DE lt HL OR a Clear carry SBC HL DE C set if HL DE SBC HL HL HL HL C 1 if carry set BOOL HL Set to 1 if carry else zero else result O0 unsigned integers compute HL gt DE or DE gt HL check for IC EX DE HL uncomment for DE lt HL OR a Clear carry SBC HL DE 1 if HL gt DE SBC HL HL HL HL C zero if no carry 1 if C INC HL 14 16 clocks total if C after first SBC result 1 else O 0 if C 1 if IC compute HL DE OR a clear carry SBC HL DE zero is equal BOOL HL force to zero 1 DEC HL invert logic BOOL HL 12 clocks total logical not 1 for inputs equal r User s Manual 41 Some simplifications are possible if one of the unsigned numbers being compared is a constant Note that the carry has a reverse sense from SBC In the following examples the pseudo code in the form LD DE 65535 B does not indicate a load of DE with the address pointed to by 65535 B but simply indicates the difference between 65535 the 16 bit unsigned integer B test for HL gt B B is constant LD DE 65535 B ADD HL DE carry set if HL gt B SBC HL HL
60. C User Enable Register PCUER 0x0350 W 00000000 Input Capture User Enable Register ICUER 0x0358 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x0370 W 00000000 328 Rabbit 3000 Microprocessor Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset I O Bank User Enable Register IBUER 0x0380 w 00000000 PWM User Enable Register PWUER 0x0388 w 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0x03A0 W 00000000 Timer B User Enable Register TBUER 0x03BO W 00000000 Serial Port A User Enable Register SAUER 0x03CO W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port B User Enable Register SBUER 0 03 w 00000000 Serial Port F User Enable Register SFUER 0x03D8 w 00000000 Serial Port C User Enable Register SCUER 0x03E0 w 00000000 Serial Port D User Enable Register SDUER 0x03F0 W 00000000 Enable Dual Mode Register EDMR 0x0420 W 00000000 Slave Port Data 0 Register SPDOR 0x0020 R W XXXXXXXX Slave Port Data 1 Register SPDIR 0x0021 R W XXXXXXXX Slave Port Data 2 Register SPD2R 0x0022 R W XXXXXXXX Slave Port Status Register SPSR 0x0023 R 00000000 Slave Port Control Register SPCR 0x00
61. C is set if A lt B if the oper ation or virtual operation is A B Carry is cleared if A gt B SUB outputs carry in opposite sense from SBC and CP 19 11 8 bit Bit Set Reset and Test Instruction BIT b HL BIT b IX d BIT b IX d BIT b r RES b HL RES b IX d RES b IY d RES b r SET b HL SET b IX d SET b IY d SET b r 19 12 8 bit Increment and Instruction DEC HL DEC IX4d DEC IY d DEC r INC HL INC IX d INC IY d INC r clk 7 10 10 4 10 13 13 4 10 13 13 4 clk 8 12 12 2 8 12 12 2 Fh Fh Fh h P Fh Fh Fh Fh Fh fr m m m H a CoO OH oo NH Operation HL amp bit IX d amp bit IY d amp bit r amp bit HL IX d IY d rer amp bit HL HL bit IX d IX d I d IV4d r bit HL amp bit IX d amp IX d amp r Decrement C Operation HL HL 1 IX d IX d IY d IY d rs rf 2 HL HL 1 IX d IX d 1 IY d IY d 1 r 1 1 1 NI lt lt lt lt lt lt r bit bit bit bit 254 Rabbit 3000 Microprocessor 19 13 8 bit Fast A Register Operations Instruction ISZVC CPL 2 r NEG 4 fr k V RLA 2 fr RLCA 2 fr 2 fr RRCA 2 fr 19 14 8 bit Shifts and Rotates
62. Count value 22 1 Output pulse Figure 11 2 Reload Register Operation The timer systems can be driven by the peripheral clock or peripheral clock divided by two This clock is always the same as the processor clock or it is faster than the processor clock by a factor of eight The output pulses are always one clock long Clocking of the counters takes place on the negative edge of this pulse When the counter reaches zero the reload register is loaded on the next input pulse instead of a count being performed The reload registers may be reloaded at any time since the peripheral clock is synchronous with the processor clock Timers A2 A3 A4 A5 A6 and A7 always provide the baud clock for Serial Ports E F A B C and D respectively Except for very low baud rates clock A1 does not need to be used to prescale the input clock for timers A2 A7 For example if the system clock is 11 0592 MHz and the timer A4 divides by 144 an asynchronous baud rate of 2400 bps can be achieved in one step assuming that the timer is clocked by peripheral clock divided by two The clock input to the serial port can be 8 or 16 times the baud rate for asynchronous mode and 8 times the baud rate for synchronous mode The maximum asynchronous baud rate with a 11 0592 MHz clock would be 11 059 200 1 8 1 382 400 150 Rabbit 3000 Microprocessor For seven of the counters A1 A7 the terminal count condition is reported in a status r
63. F 0 0038 0 003 interrupts Parallel Port B 0x0040 0x0047 No interrupts Parallel Port G 0x0048 0x004F No interrupts Parallel Port C 0 0050 0 0055 interrupts Input Capture 0x0056 0x005F IIR 7 1 1 OxAO Parallel Port D 0x0060 0x006F No interrupts Parallel Port E 0 0070 0 007 interrupts External Control 0x0080 0x0087 No interrupts Pulse Width Modulator 0 0088 0 008 interrupts Quadrature Decoder 0x0090 0x0097 HR 7 1 1 0 90 INTO EIR 0 00 External Int t 0x0098 0x009F xternal Interrupts x INTI EIR 0x10 Timer 0 00 0 0 00 7 1 0 0 0 Timer B 0x00B0 0x00BF IIR 7 1 0 OxBO Serial Port A async cks 0 00 0 0 00 7 IIR 7 1 0 0 Serial Port E async HDLC 0 00 8 0 00 1 1 0 Serial Port async cks 0x00D0 0x00D7 HR 7 1 0 OxDO Serial Port F async HDLC 0x00D8 0x00DF 7 1 1 OxDO Serial Port C async cks 0 00 0 00 7 HR 7 1 0 OxEO Serial Port D async cks 0x00F0 0x00F7 HR 7 1 0 OxFO RST 10 instruction n a UIR 7 1 0 0x20 RST 18 instruction n a UIR 7 1 0 0x30 RST 20 instruction n a UIR 7 1 0 0x40 RST 28 instruction n a UIR 7 1 0 0x50 280 Rabbit 3000 Microprocessor Table B 4 Rabbit 3000 I O Address Ranges and Interrupt Service Vec
64. HL HL C result 1 if carry set else zero BOOL HL 14 total clocks true if HL gt B HL gt B B is constant not zero LD DE 65536 B ADD HL DE SBC HL HL BOOL HL 14 clocks HL gt B B is zero LD HL 1 6 clocks HL B B is a constant not zero if B 0 always false LD DE 65536 B ADD HL DE not carry if HL B SBC HL HL 1 if carry else 0 INC HL 14 clocks 0 if carry else 1 if no carry HL lt B B is constant not zero LD DE 65535 B ADD HL DE C if HL B CCF C if true SBC HL HL if C 1 else O INC HL 16 clocks 1 if true else 0 HL lt B B is zero true if HL 0 BOOL HL result in HL HL B and B is a constant not zero LD DE 65536 B ADD HL DE zero if equal BOOL HL INC HL RES 1 1 16 clocks HL B and B BOOL HL INC HL RES 1 1 8 clocks For signed integers the conventional method to look at the zero flag the minus flag and the overflow flag Signed 8 bit integers span the range 128 to 127 0x80 to Ox7F Signed 16 bit integers span the range 32768 to 32767 0x8000 to Ox7FFF The sign and zero flag tell which is the larger number after the subtraction unless the overflow is set in which case the sign flag needs to be inverted in the logic that is it is wrong 42 Rabbit 3000 Microprocessor A gt B 18 amp V amp Z v S amp V A B 8 amp V v 18 amp V amp Z B A gt B A lt B Another method of doing signed compa
65. LDDR are used interrupts can take place between successive itera tions Word stores to I O space can be used to set two I O registers at adjacent addresses with a single noninterruptable instruction User s Manual 43 3 5 Interrupt Structure When an interrupt occurs on the Rabbit the return address is pushed on the stack and con trol is transferred to the address of the interrupt service routine The address of the inter rupt service routine has two parts the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt as shown in Table 6 1 There are separate registers for internal interrupts IIR and external interrupts EIR to specify the high byte of the interrupt service routine address These registers are accessed by special instructions LD A IIR LD IIR A LD A EIR LD EIR A Interrupts are initiated by hardware devices or by certain 1 byte instructions called reset instructions RST 10 RST 18 RST 20 RST 28 RST 38 The RST instructions are similar to those on the Z80 and Z180 but certain ones have been removed from the instruction set 00 08 30 The RST interrupts are not inhibited regard less of the processor priority The user is advised to exercise caution when using these instructions as they are mostly reserved for the use of Dynamic C for debugging Unlike the Z80 or Z180 the IIR register contributes the upper byte of the service routine address for
66. Long Stop Register SDLR OxF2 W XXXXXXXX Serial Port D Status Register SDSR OxF3 R 0xx00000 Serial Port D Control Register SDCR OxF4 w xx000000 Serial Port D Extended Register SDER OxF5 W 00000000 Table 12 6 Serial Port E Registers Register Name Mnemonic Address R W Reset Serial Port E Data Register SEDR 0 8 R W XXXXXXXX Serial Port E Address Register SEAR 0xC9 W XXXXXXXX Serial Port E Long Stop Register SELR OxCA W XXXXXXXX Serial Port E Status Register SESR OxCB R 0xx00000 Serial Port E Control Register SECR 0 000000 Serial Port E Extended Register SEER 0xCD W 000x000x Table 12 7 Serial Port F Registers Register Name Mnemonic Address R W Reset Serial Port F Data Register SFDR OxD8 R W XXXXXXXX Serial Port F Address Register SFAR 0 9 W XXXXXXXX Serial Port F Long Stop Register SFLR OxDA W XXXXXXXX Serial Port F Status Register SFSR OxDB R 0xx00000 Serial Port F Control Register SFCR OxDC W xx000000 Serial Port F Extended Register SFER OxDD W 000x000x User s Manual 167 Table 12 8 Data Register Ports Serial Port x Data Register SADR Address 0xC0 SBDR Address 0xD0 SCDR Address 0xE0 SDDR Address 0xF0 SEDR Address 0xC8 SFDR Address 0xD8 Bit s Value Description Read Returns the contents of the receive buffer 7 0 Write Loads the transmit buffer with a data byte for transmission Table 12 9 Address
67. O functions to other pins The following alternate connections were introduced in the Rabbit 3000A for these peripherals and are indicated by an asterisk in Table 5 2 e Slave port CS ASCS Alternate slave port chip select input e Serial Ports E F ARXE Alternate Serial Port E receive ARCLKE Alternate Serial Port E receive clock HDLC ARXF Alternate Serial Port F receive ARCLKF Alternate Serial Port F receive clock HDLC e PWM outputs APWM3 Alternate PWM output bit 3 APWM2 Alternate PWM output bit 2 APWMI Alternate PWM output bit 1 Alternate PWM output bit 0 316 Rabbit 3000 Microprocessor APPENDIX C SYSTEM USER MopE The Rabbit 3000A is the first Rabbit microprocessor to incorporate a system user mode The purpose of the System User mode is to provide two tiers of control in the CPU sys tem which provides full access to all processor resources and user a more restricted mode Table C 1 describes the essential differences between the System mode and the User mode The System mode 15 essentially the same as the normal operation of the Rabbit 3000 and earlier processors Table C 1 Differences Between System and User Modes System Mode User Mode All peripherals accessible No peripherals accessible by default All processor control registers available No processor control registers available All interrupt priorities available Interrupt Priority 3 not allowed IDET opcode caus
68. Opcodes The LDxR family of block move opcodes has been expanded In the Rabbit 3000 proces sor block copy operations could only be done between memory addresses or from mem to an I O address In addition the destination 1 address would increment or decrement if using LDDR after each byte making the block copy opcodes effectively useless for repeated reads or writes to a peripheral for example a device on the external I P bus Six new block copy opcodes were added to the Rabbit 3000 revision These opcodes can copy from an I O address as well as to one and either the source or destination address can remain fixed instead of changing after each byte The new opcodes are described in Table B 19 Table B 19 Rabbit 3000 Revision Block Copy Opcode Effects r Destination Opcode hn ud 1 LDDR destination LDIR destination LDDSR none destination LDISR none destination LSDR E source LSIR source LSDDR none source LSIDR none source 294 Rabbit 3000 Microprocessor B 1 10 Expanded I O Memory Addressing In the Rabbit 3000 only the lower 8 bits of an I O address were decoded To provide room for new peripherals this was expanded to 16 bits To ensure backwards compatibility the processor always comes up in 8 bit I O address mode the 16 bit I O address mode needs to be enabled in the MMIDR register by setting bit 7
69. Os Os Os OF O O O OF Ot Ot O OF Os OF O O O O8 O Of Os OF O O LLI a o 22 oc e a a gt Os Oe OF OF 5 n o o a A T s O8 O Og O Os O Os O OF Os O lt m 0 f ul lb d I Figure 5 4 Ball Grid Array Pinout Looking Through the Top of Package 59 User s Manual Table 5 2 Ball and Land Size Dimensions 5 2 2 Mechanical Dimensions and Land Pattern Nominal Ball Tolerance Ball Pitch Nominal Land Land Diameter Variation Diameter Variation mm mm mm mm mm 0 3 0 35 0 25 0 8 0 25 0 25 0 20 The design considerations in Table 5 3 are based on 5 mil design rules and assume single conductor between solder lands Table 5 3 Design Considerations all dimensions in mm Key Feature Recommendation A Solder Land Diameter 0 254 0 010 B NSMD Defined Land Diameter 0 406 0 016 C Land to Mask Clearance min 0 050 0 002 D Conductor Width max 0 127 0 005 E Conductor Spacing typ 0 127 0 005 F Via Capture Pad max 0 406 0 016 G Via Drill Size max 0 254 0 010 ale Land and Trace 60 Rabbit 3000 Microprocessor BOTTOM VIEW TOP VIEW lt OOOOPO O O 0000 O 000000
70. PCDR 0x50 R W x0x1x1x1 Port C Function Register PCFR 0x55 W x0x0x0x0 Port D Data Register PDDR 0x60 R W XXXXXXXX Port D Control Register PDCR 0x64 W xx00xx00 Port D Function Register PDFR 0x65 W XXXXXXXX Port D Drive Control Register PDDCR 0x66 W XXXXXXXX Port D Data Direction Register PDDDR 0x67 W 00000000 Port D Bit 0 Register PDBOR 0x68 W XXXXXXXX Port D Bit 1 Register PDBIR 0x69 W XXXXXXXX Port D Bit 2 Register PDB2R 0x6A W XXXXXXXX Port D Bit 3 Register PDB3R 0x6B w XXXXXXXX Port D Bit 4 Register PDB4R 0x6C W XXXXXXXX Port D Bit 5 Register PDB5R 0 6 w XXXXXXXX Port D Bit 6 Register PDB6R 0 6 w XXXXXXXX Port D Bit 7 Register PDB7R Ox6F W XXXXXXXX Port E Data Register PEDR 0x70 R W XXXXXXXX Port E Control Register PECR 0x74 xx00xx00 Port E Function Register PEFR 0x75 W 00000000 Port E Data Direction Register PEDDR 0 77 00000000 Port E 0 Register 0x78 w XXXXXXXX Port E Bit 1 Register PEBIR 0x79 W XXXXXXXX Port E Bit 2 Register PEB2R Ox7A W XXXXXXXX Port E Bit 3 Register PEB3R 0 7 Port E 4 Register PEB4R 0x7C w XXXXXXXX Port E Bit 5 Register 5 0x7D w XXXXXXXX Port E Bit 6 Register PEB6R Ox7E W XXXXXXXX 74 Rabbit 3000 Microprocessor Table 6 2 Rabbit Internal l O Registers continued Register Name Mnemonic l O Address R W Reset Port E Bit 7 Register PEB7R Ox7F W XXX
71. State Vian or V Ioz Output Current e 10 10 Vpp Vpp max pull up absolute worst case all buffers 68 Rabbit 3000 Microprocessor 5 7 Buffer Sourcing and Sinking Limit Unless otherwise specified the Rabbit I O buffers are capable of sourcing and sinking 6 8 mA of current per pin at full AC switching speeds The limits are related to the maxi mum sustained current permitted by the metallization on the die User s Manual 69 70 Rabbit 3000 Microprocessor 6 RABBIT INTERNAL l O REGISTERS User s Manual 71 Table 6 1 Rabbit 3000 Peripherals and Interrupt Service Vectors On Chip Peripheral ISR Starting Address System Management UIR 7 1 0 0x00 Memory Management No interrupts Slave Port UIR 7 1 0 0x80 Parallel Port A No interrupts Parallel Port F No interrupts Parallel Port B No interrupts Parallel Port G No interrupts Parallel Port C No interrupts Input Capture IIR 7 1 1 OxAO Parallel Port D No interrupts Parallel Port E No interrupts External I O Control No interrupts Pulse Width Modulator No interrupts Quadrature Decoder UIR 7 1 1 0x90 External Interrupts INTO EIR 0x00 INTI EIR 0x10 Timer A 7 1 0 OxAO Timer 7 1 0 OxBO Serial Port A async cks IIR 7 11 0 0 Serial Port E async hdlc 7
72. Trigger x Register Input Capture Trigger x Register ICT1R Address 0x58 ICT2R Address 0x5C Bit s Value Description 7 6 00 Disable the counter 01 The counter runs from the Start condition until the Stop condition 10 The counter runs continuously 11 The counter runs continuously until the Stop condition 5 4 00 Disable the count latching function 01 Latch the count on the Stop condition only 10 Latch the count on the Start condition only 11 Latch the count on either the Start or Stop condition 3 2 00 Ignore the starting input 01 The Start condition is the rising edge of the starting input 10 The Start condition is the falling edge of the starting input 11 The Start condition is either edge of the starting input 1 0 00 Ignore the ending input 01 The Stop condition is the rising edge of the ending input 10 The Stop condition is the falling edge of the ending input 11 The Stop condition is either edge of the ending input 108 Rabbit 3000 Microprocessor Table 7 22 Input Capture Source x Register Input Capture Source x Register ICS1R Address 0x59 ICS2R Address 0x5D Bit s Value Description 7 6 00 Parallel Port C used for Start condition input 01 Parallel Port D used for Start condition input 10 Parallel Port F used for Start condition input 11 Parallel P
73. a holding register until read from the ICMxR In the first mode the counter starts counting at the Start condition and stops counting at the Stop condition This mode is useful for pulse width measurement if the Start condition and Stop condition are assigned to the same pin The Input Capture inputs were chosen to take maximum advantage of this mode to allow baud rate detection for the serial ports and rotational speed measurement for the Quadrature Decoder channels Using this mode with different inputs for the Start and Stop condition allows time delay measurements between two signals This is the mode to use for high speed pulse measurement because only one count latch is available and it may be overwritten if the processor is not able to read the latched value quickly enough When the counter starts from a known count only the stop count is necessary to determine the pulse width In the second mode the counter runs continuously and the Start and Stop conditions merely latch the current count This mode is useful for time stamping the input conditions against the time reference of the counter If the time stamp feature is not needed this mode gives the Rabbit 3000 up to four more external interrupt inputs This mode works well for slower speed pulse measurement where the processor has enough time to read the count latched by the Start condition before the Stop condition occurs and latches a new count In the third mode the counter runs conti
74. a major cause of EMI If all the EMI suppression features of the Rabbit 3000 are properly utilized and low EMI design techniques are used on the printed circuit board system EMI will likely be reduced to a very low level probably much lower than is necessary to pass government tests User s Manual 211 15 1 Power Supply Connections and Board Layout Refer to Technical Note TN221 PC Board Layout Suggestions for the Rabbit 3000 Microprocessor for recommendations on laying out a PC board to minmize EMI emsis sions 15 2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 dB This is a very large reduction since it is common to struggle to reduce EMI by 5 dB in order to pass government tests ISdB a Strong Spreading 10 Y Normal Spreading 5 y 50 100 150 200 250 300 350 MHz Figure 15 1 Peak Spectral Amplitude Reduction from Spectrum Spreader The spectrum spreader modulates the clock so as to spread out the spectrum of the clock and its harmonics Since the government tests use a 120 kHz bandwidth to measure EMI spreading the energy of a given harmonic over a wider bandwidth will decrease the amount of EMI measured for a given harmonic The spectrum spreader not only reduces the EMI measured in government tests but it will also often reduce the interference cre ated f
75. addition to the normal NRZ they are NRZI Biphase Level Manchester Biphase Space FM0 and Biphase Mark FM1 Examples of these encodings are shown in the Figure below Note that in NRZI Biphase Space and Biphase Mark the signal level does not convey information Rather it is the placement of the transitions that determine the data In Biphase Level it is the polarity of the transition that determines the data 188 Rabbit 3000 Microprocessor Serial Clock NRZ Data NRZI N N NRZI N N Biphase Level ANECA NASN Z ey NS U Z i P VU uA NU UNO NOU AU AN7A E O S NANEN SANS Biph se Mark ONY NJS NIN NSN N data 1 0 1 1 0 0 1 0 In HDLC mode the internal clock comes from the output of Timer A2 This timer output is divided by sixteen to form the transmit clock and is fed to the Digital Phase Locked Loop DPLL to form the receive cloc
76. and provided if needed By connecting I O devices to the auxiliary bus the fast memory bus is relieved of the capacitive load that would otherwise slow the memory For core modules based on the Rabbit 3000 fewer pins are required to exit the core module since the slave port and the I O bus can share the same pins and the memory bus no longer needs to exit the module to provide I O capability Because the I O bus has less activity and is slower than the memory bus it can be run further physically without EMI and ground bounce problems 5 V signals can appear on the I O bus since the Rabbit 3000 inputs are 5 V tolerant 5 V signals could easily cause problems on the main bus if non 5 V tolerant 3 3 V memories are connected 2 2 8 Timers The Rabbit has several timer systems The periodic interrupt is driven by the 32 768 kHz oscillator divided by 16 giving an interrupt every 488 us if enabled This is intended to be used as a general purpose clock interrupt Timer A consists of ten 8 bit countdown and reload registers that can be cascaded up to two levels deep Each countdown register can be set to divide by any number between 1 and 256 The output of six of the timers is used to provide baud clocks for the serial ports Any of these registers can also cause interrupts and clock the timer synchronized parallel output ports Timer B consists of a 10 bit counter that can be read but not written There are two 10 bit match registers and comparators If t
77. bit cell and the DPLL operation is adjusted accordingly Decoding Biphase Mark or Biphase Space encoding requires that the data be sampled by both edges of the recovered receive clock An optional IRDA Infrared Data Association compliant encode and decode function is available in both asynchronous mode and HDLC mode The encoder sends an active High pulse for a zero and no pulse for a one In the asynchronous 16x mode this pulse is 3 16ths of a bit cell wide while in the asynchronous 8x mode it is 1 8th of a bit cell wide In HDLC mode the pulse is 1 4th of a bit cell wide In all modes the decoder watches for active Low pulses which are stretched to one bit time wide to recreate the normal asyn chronous waveform for the receiver Enabling the IRDA compliant encode decode modi fies the transmitter in HDLC mode so that there are always two opening Flags transmitted User s Manual 191 12 9 Serial Port Software Suggestions The receiver and transmitter share the same interrupt vector but it is possible to make the receive and transmit interrupt service routines ISRs separate by dispatching the interrupt to either of two different routines This is desirable to make the ISR less complex and to reduce the interrupt off time No interrupts will be lost since distinct interrupt flip flops exist for receive and transmit The dispatcher can test the receiver data register full bit to dispatch If this bit is on the interrupt is dispatched for r
78. by bits in an I O control register associated with the hard ware that creates the interrupt The 8 bit interrupt register IP holds the processor priority in the least significant 2 bits When an interrupt takes place the IP register is shifted left 2 positions and the lower 2 bits are set to equal the priority of the interrupt that just took place This means that an interrupt service request ISR can only be interrupted by an interrupt of higher priority unless the priority is explicitly set lower by the programmer The IP register serves as a 4 word stack of 2 bit words to save and restore interrupt priori ties It can be shifted right restoring the previous priority by a special instruction IPRES Since only the current processor priority and 3 previous priorities can be saved in the inter rupt register instructions are also provided to PUSH and POP IP using the regular stack A new priority can be pushed into the IP register with special instructions IPSET 0 IPSET 1 IPSET 2 IPSET 3 Table 3 1 Effect of Processor Priorities on Interrupts Processor MOS Effect on Interrupts Priority 0 All interrupts priority 1 2 and 3 take place after execution of current non privileged instruction 1 Only interrupts of priority 2 and 3 take place 2 Only interrupts of priority 3 take place 3 All interrupt are suppressed except RST instruction User s Manual 45 3 5 2 Multiple External Interrupting Devi
79. code that must be run periodically If hits to the hardware watchdog are scattered through a program then it may be possible for the code to enter an endless loop where the watchdog is hit and therefore rendered useless for detecting the endless loop condition If no virtual watchdogs are used an undetected endless loop con dition could still occur since the periodic interrupt can still hit the hardware watchdog If any of the virtual watchdogs times out then hits are withheld from the hardware watch dog and it times out resulting in a hardware reset Virtual watchdogs may be allocated deallocated enabled and disabled The advantage of the virtual watchdogs is that if any of them fail an error is detected The Dynamic C Users s Manual chapter on the Virtual Driver provides more details on virtual watchdogs User s Manual 239 240 Rabbit 3000 Microprocessor 18 OTHER RABBIT SOFTWARE 18 1 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism This is done by changing the clock speed or the clock doubler The range of control is quite wide the speed can vary by a factor of 16 when the main clock is driving the processor In addition the main clock can be switched to the 32 768 kHz clock In this case the slowdown is very dramatic a factor of perhaps 500 In this ultra slow mode each clock takes about 30 us and a typical instruction takes 150 us to execute A
80. command must be issued by writing to bits 7 6 of the control register for each byte sent or received One command is for sending a byte a different command is for receiving a byte and yet another command can initiate a transmit and receive at the same time for full duplex commu nication Alternatively a read or write to the Serial Ports A D Address registers SxAR elim inates the need to issue separate receive and transmit commands In clocked serial mode reading the data from the corresponding SxAR register automatically causes the receiver to start a byte receive operation eliminating the need for software to issue the Start Receive command Any data contained in the receive buffer will be read first before being replaced 182 Rabbit 3000 Microprocessor with new incoming data Similarly writing the data to the SxAR register causes the trans mitter to start a byte transmit operation eliminating the need for the software to issue the Start Transmit command The effect of these codes is different depending on whether the mode is internal clock or external clock To transmit in internal clock mode the user must first load the data register which must be empty and then store the send code When the shift register finishes sending the cur rent character if any the data register will be loaded into the shift register and transmitted by an 8 clock burst One character can be in the process of transmitting while another character is wai
81. count formed from the eight MSBs of the pulse width register Pulse Width LSBs 1st 2nd 3rd 4th 00 n 4 1 n 4 n 4 n 4 01 n A 1 n 4 n 4 1 n 4 10 n 4 1 n 4 1 n 4 1 n 4 11 n 4 1 n 4 1 n 4 1 n 4 1 The diagram below shows a PWM output for several different width values for both modes of operation Operation in the spread mode reduces the filtering requirements on the PWM output in most cases User s Manual 103 d l n 255 normal 256 counts i n 255 spread 64 counts 64 counts 64 counts 64 counts n 256 spread 65 counts 64 counts 64 counts 64 counts n 257 spread 65 counts 64 counts 65 counts 64 counts n 258 spread 65 counts 65 counts 65 counts 64 counts n 259 spread 65 counts 65 counts 65 counts 65 counts T n 259 normal 260 counts Table 7 17 PWM LSB Register PWM LSB x Register PWLOR Address 0x88 PWL1R Address 0x8A PWL2R Address 0x8C PWL3R Address 0x8E Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 1 These bits ignored 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle Table 7 18 PWM MSB x Register PWM MSB x Register PWMOR Address 0x89 PWM1R Address 0x8B PWM2R Address 0x8D Address
82. four most significant bits of the result are 1 User s Manual 249 19 1 Load Immediate Data Instruction LD IX mn LD IY mn LD dd mn LD r n clk 186 Z V Operation IX mn IY mn dd mn ren 19 2 Load amp Store to Immediate Address Instruction LD mn A LD A mn LD mn HL LD mn IX LD mn IY LD mn ss LD HL mn LD IX mn LD IY mn LD dd mn clk 10 9 13 15 15 15 11 13 13 13 A m m m m o o aH Operation mn A A mn mn L mn 1 H mn IXL mn 1 IXH mn IYL mn 1 mn ssl mn 1 ssh L mn H mn 1 mn IXH mn 1 IYL mn IYH mn 1 ddl mn ddh mn41 19 3 8 bit Indexed Load and Store Instruction LD A BC LD A DE LD BC A LD DE A LD HL n LD HL r LD r HL LD IX d n LD IX d r LD r IX d LD IY d n LD IY d r LD r H uaan p 0 mn p p O p mn aH Operation A BC A DE BC A DE A HL n HL r r HL IX d n IX d r r IX d IY d Iy d r IY d n w m 19 4 16 bit Indexed Loads and Stores Instruction LD HL d HL LD HL HL d LD SP n HL LD SP n IX LD SP n IY LD HL SP n LD IX SP n LD IY SP n LD IX d HL LD HL IX d LD IY d HL LD HL IY d clk 13 11 11 13 13 9 11 11 11 9 13 11 A 186 Z V L Operation
83. interrupt after the last bit is sent A so called address bit can be transmitted as either high or low after the last data bit The address bit if used is followed by a high stop bit This facility can be used to transmit 2 stop bits or a parity bit if desired The ability to directly transmit a high voltage level address bit was not included in the original revision of the Rabbit 2000 processor Serial ports A B C and D can be operated in the clocked serial mode In this mode a clock line synchronously clocks the data in or out Either the Rabbit serial port or the remote device can supply the clock When the Rabbit provides the clock the baud rate can be up to 1 2 of the system clock frequency When the clock is provided by another device the maximum data rate is system clock divided by 6 due to the need to synchronize the externally supplied clock with the internal clock The clocked serial mode may be used to support SPI bus devices Serial Port A has special features It can be used to cold boot the system after reset Serial Port A is the normal port that is used for software development under Dynamic C All the serial ports have a special timing mode that supports infrared data communications standards 2 2 3 System Clock The main oscillator uses an external crystal with a frequency typically in the range from 1 8 MHz to 26 MHz The processor clock is derived from the oscillator output by either doubling the frequency using the fr
84. interrupt handler When the application code wants to perform an action that is controlled by the System mode it can request the particular action by loading the appropriate value into HL and executing SYSCALL This requires generating a list of all the actions that the application code would want to do assigning values to each action and implementing a SYSCALL handler in the System mode that parses the value passed to it and calls the appropriate function Write protection should be enabled User mode only for all blocks containing system code and data as well as any critical memory regions If any critical interrupts occur stack limit violation system mode violation write protec tion violation the System mode handlers can perform any of a number of operations restart the application code signal another device halt operation and so on An overview of this level of operation is shown in Figure C 4 System Mode User Mode Return from interrupts Interrupt Application handlers code Flash file User defined System interrupts SYSCALL handler Interrupts SYSCALL RST Figure C 4 System User Mode Setup for Operating System 326 Rabbit 3000 Microprocessor APPENDIX D RABBIT 3000A INTERNAL I O REGISTERS Table D 1 provides a list of all the Rabbit 3000A internal I O registers Table D 1 Rabbit 3000A Internal I O Registers
85. is on the chip The cycle starts at the start of the final 64 us clock of the memory cycle and can be set to enable chip select for a period in the range of 70 to 200 ns The data are clocked in early at the end of the delay driven cycle The chip select duty cycle is very small about 0 2 128 1 600 User s Manual 87 When operating in the 32 KHz mode it is also possible to further divide the clock to a fre quency as low as 2 kHz further reducing execution speed and current consumption Global Power Save Control Register GPSCR Address 0x0D Bit s Value Description 000 Self timed chip selects are disabled 001 This bit combination is reserved and should not be used 01x This bit combination is reserved and should not be used 43 5 100 296 ns self timed chip selects 192 ns best case 457 ns worst case 101 234 ns self timed chip selects 151 ns best case 360 ns worst case 110 171 ns self timed chip selects 111 ns best case 264 ns worst case 111 109 ns self timed chip selects 71 ns best case 168 ns worst case 0 Normal Chip Select operation 1 Short Chip Select timing when dividing main oscillator by 4 6 or 8 3 x This bit is reserved and should not be used 000 The 32 kHz clock divider is disabled 001 This bit combination is reserved and should not be used 01 This bit combination is reserved and should not be used 2 0 100 32 kHz oscillator divided by two
86. lt Q O O O O O RS X Operation gt p p p p p IX d CF 1 4 CF n CF r CF HL IX d IY d n r HL IX d IY d pp p p p p pp p pr mm m m m m H HL IX d IY d User s Manual 253 CP m CP r OR HL OR IX d OR IY d OR n OR r SBC IX d SBC IY d SBC A HL SBC A n SBC A r SUB HL SUB IX d SUB IY d SUB n SUB r XOR HL XOR IX4d XOR IY d XOR n XOR r N gH O Ul N g HO WU Ul N O ON gt Ul N gs f f fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr s F FH HF S LO A frs LO amp amp amp n A amp r LO A LO A n V A r LO HL LO IX d LO IY d KLO A A n KLO IX d HL CY V A A n CY cout if r CY gt A V A A r CY cout if r CY A HL V IX d V V A A r LO A amp HL l A amp HL l A amp IX d l A IY d A amp n A amp r SBC and CP instruction output inverted carry
87. of Phys ical Memory Separate I amp D Space Model on page 126 In this figure n is the number of 4k pages devoted to D space constants In the figure it is assumed that the lower 512k of memory is entirely composed of flash memory and the upper 512K is entirely RAM This does not have to be the case For example if a low cost 32K x 8 RAM is used and mapped to the 3rd quadrant using CS1 the RAM memory will begin at 512K and will be repeated 8 times in the 3rd quadrant from addresses 512K to 768K Since the memory repeats it can be considered to start at any address and continue for 32K At least 4K of RAM is needed for the stack segment so if a 32K RAM is used a maximum of 28K would be available for storing data variables If more stack segments are needed the amount of data variable space would be corresponding reduced User s Manual 125 64k 4 n 64k alloc s ads 512k 4 n 512k 52k ees E 512k xdata vars Root e I Space alloc consts lt q allocate vars Constant Variable D Space D Space Flash memory available Ram memory available for extended code constant data Figure 8 6 Use of Physical Memory Separate amp D Space Model In Figure 8 6 arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds Each of these arrows starts at a constant location in physical memory This is important because t
88. or HL LD LD LD LD LD LD LD LD LD LD LD HL SP d SPrd HL HL HL d HL HL d HL d HL IX d HL HL IX d HL IX d IY d HL HL IY d HL IY d r r r r r r d is an offset from 0 to 255 16 bits are fetched to HL HL corresponding store d is an offset from 128 to 127 uses original HL value for addressing 1 4 h HL d 1 store HL at address pointed to by IX plus 128 to 127 offset store HL at address pointed to by IY plus 128 to 127 offset 34 Rabbit 3000 Microprocessor 3 3 4 Register to Register Move Any of the 8 bit registers A B C D E H and L can be moved to any other 8 bit regis ter for example LD A c LD d b LD 1 The alternate 8 bit registers can be a destination for example LD a c LD d b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of the required prefix byte Instructions such as LD A d or LD d e are not allowed Several 16 bit register to register move instructions are available Except as noted these instructions all require 2 bytes and four clocks The instructions are listed below LD dd BC where dd is any of HL DE BC 2 bytes 4 clocks LD dd DE LD IX HL LD IY HL LD HL IY LD HL IX LD SP HL l byte 2 clocks LD SP IX LD SP IY Other 16 bit register moves can be constructed by using 2 byte moves 3
89. rate interrupt request flip flop for the receiver and transmitter If either of these flip flops is set a serial port interrupt is requested The flip flops are set by a rising edge only The flip flops are cleared by a pulse generated by an I O read or write operation as shown in Figure 12 3 When an interrupt is requested it will take place immediately when priorities allow and an instruction execution is complete The interrupt is lost if the request flip flop is cleared before the interrupt takes place If the flip flop is not cleared in the interrupt another interrupt will take place when priorities are lowered Transmitter IRQ Transmitter Data Request Interrupt Buffer Empty or Transmitter not Busy Write Transmitter Data Register or Write Status Register Receiver IRQ Receiver Data Buffer Full Read Receiver Data Register Figure 12 3 Generation of Serial Port Interrupts The receive interrupt request flip flop is set after the stop bit is sampled on receive nomi nally 1 2 of the way through the stop bit Data bits are transferred on this same clock from the receive shift register to the receive data register The transmit interrupt request flip flop is set on the leading edge of the start bit for data register empty and at the trailing edge of the stop bit for shift register empty transmitter idle Unless the data register is empty on this trailing edge of t
90. receiver service routine might appear as follows below The byte at bufptr is used to address the buffer where data bits are stored It is necessary to save and increment this byte because characters could be han dled out of order if two receiver interrupts take place in quick succession receive PUSH HL 10 save HL PUSH DE 10 save DE LD HL struct 6 LD A HL 5 get in pointer LD E A 2 save in pointer in E INC HL 2 point to out pointer CMP A HL 5 see if in pointer out pointer buffer full JR Z roverrun 5 go fix up receiver over run INC A 2 incement the in pointer AND A mask 4 mask such as 11110000 if 16 buffer locs DEC HL 52 192 Rabbit 3000 Microprocessor LD HL A 6 update the in pointer IOI LD A SCDR ll get data register port C clears interrupt request IPRES 4 restore the interrupt priority 68 clocks to here to level before interrupt took place more interrupts could now take place but receiver data is in registers now handle the rest of the receiver interrupt routine LD HL bufbase 5 LD D 0 6 ADD HL DE 2 location to store data LD HL A 6 put away the data byte POP DE 3009 end POP AF 27 27 RET 8 from interrupt 117 clocks to here This routine gets the interrupts turned on in about 68 clocks or 3 5 us at a clock speed of 20 MHz Although two characters may be handled out of order this will be invisible to a higher level routine check
91. side and then lower the interrupt priority and conduct the rest of the transaction as a polled transaction On the master side the entire transaction can be a polled transaction In this case the entire transaction takes place in the interrupt routine on the slave but other interrupts are not inhibited since the priority has been lowered A typical slave system consists of a Rabbit microprocessor and a RAM memory con nected to it The clock can be provided either by connecting a crystal or crystals to the slave or by providing an external clock which could be the master s clock The reset line of the slave would normally be driven by the master At system startup time the master resets the slave and cold boots it via the slave port The SMODE pins must be configured User s Manual 207 for this Once the software is loaded into the slave the slave can begin to perform its function As a simple example suppose that the slave is to be used as a four port UART It has the capability to send or receive characters on any of its four serial ports Leaving aside the question of setup for parameters such as the baud rate we could define a protocol as fol lows SPDOR readable by master is a status register with bits indicating which of the four receivers and four transmitters is ready that is has a character received or is ready to send a character SPDOR writable by the master is a control register used to send commands to the slave
92. strobe and the number of wait states that will be inserted in the I O bus cycle Writes can also be suppressed for any of the strobes The types of strobes are shown in Figure 10 1 Each of the eight I O strobes is active for addresses occupying 1 8th of the 64K external I O address space ADDR write data write strobe read data read strobe chip select strobe External I O Timing with 1 wait state Figure 10 1 External I O Bus Cycles User s Manual 145 Table 10 1 shows how the eight 1 bank control registers are organized Table 10 1 I O Bank x Control Register 10 Bank x Control Register IBOCR Address 0x0080 IB1CR Address 0x0081 IB2CR Address 0x0082 IB3CR Address 0x0083 IB4CR Address 0x0084 IB5CR Address 0x0085 IB6CR Address 0x0086 IB7CR Address 0x0087 Bit s Value Description 7 6 00 Fifteen wait states for accesses in this bank 01 Seven walt states for accesses in this bank 10 Three wait states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The Ix signal is an I O chip select 01 The Ix signal is an I O read strobe 10 The Ix signal is an I O write strobe 11 The Ix signal is an I O data read or write strobe 0 Writes are not allowed to this bank Transactions are no
93. the data rate will slow to 44 444 bytes per second If it can answer in 2 5 clocks or 6 25 us the data rate slows to 40 000 bytes per second If it can answer in 3 5 clocks or 8 75 us the data rate will slow to 36 363 bytes per second and so forth If two way half duplex communication is desired the clock can be turned around so that the receiver always provides the clock This is slightly more complicated since the receiver cannot initiate a message If the receiver attempts to receive a character and the transmitter is not transmitting the last bit sent will be received for all eight bits 184 Rabbit 3000 Microprocessor 12 7 Clocked Serial Timing 12 7 1 Clocked Serial Timing With Internal Clock For synchronous serial communication the serial clock can be either generated by the Rabbit or by an external device The timing diagram in Figure 12 6 below can be applied to both full duplex and half duplex clocked serial communication where the serial clock is generated internally by the Rabbit Other SPI compatible clock modes supported by the Rabbit 3000 are shown in Figure 12 5 With an internal clock the maximum serial clock rate 15 perclk 2 CYCLE 1 2 3 4 5 6 7 8 CLKA TxA LSB Y BiT 1 BI 2 BI 4 BIT 5 X 6 MSB RxA LSB Y BIT 1 Y BIT2 Y BITS Y BITS X BIT6 MSB wees E POPE Pd Figure 12 6 Full Duplex Clocked Serial Timing Diagram wit
94. the 16 bit register DE to the 16 bit accumulator HL For many operations IX or IY can substitute for HL as accumulators The register marked F is the flags register or status register It holds a number of flags that provide information about the last operation performed The flag register cannot be accessed directly except by using the POP AF and PUSH AF instructions Normally the flags are tested by conditional jump instructions The flags are set to mark the results of arithmetic and logic operations according to rules that are specified for each instruction There are four unused read write bits in the flag register that are available to the user via the PUSH AF and POP AF instructions These bits should be used with caution since new generation Rabbit processors could use these bits for new purposes The registers IX IY and HL can also serve as index registers They point to memory addresses from which data bits are fetched or stored Although the Rabbit can address a megabyte or more of memory the index registers can only directly address 64K of mem ory except for certain extended addressing LDP instructions The addressing range is expanded by means of the memory mapping hardware see Memory Mapping on page 23 and by special instructions For most embedded applications 64K of data mem ory as opposed to code memory is sufficient The Rabbit can efficiently handle a mega byte of program space The register SP points to the stack
95. the 48 bit RTC holding register is returned Writing to the transfers the current count of the to six holding Write l registers while the RTC continues counting Table 7 11 Real Time Clock Control Register RTCCR adr 0x01 Bit s Value Description 7 0 0x00 Writing a 0x00 to the RTCCR has no effect on the RTC counter However depending on what the previous command was writing a 0x00 may either 1 disable the byte increment function or 2 cancel the RTC reset command If the 0 command is followed by a 0x00 command only the byte increment function will be disabled The RTC reset will still take place Ox40 Arm RTC for a reset with code 0x80 or reset and byte increment function with code 0x0C0 0x80 Resets all six bytes of the RTC counter to 0x00 if proceeded by arm command 0x40 0xCO Resets all six bytes of the RTC counter to 0x00 and enters byte increment mode precede this command with 0x40 arm command 7 6 01 This bit combination must be used with every byte increment write to increment clock s register corresponding to bit s set to 1 Example 01001101 increments registers 0 2 3 The byte increment mode must be enabled Storing 0x00 cancels the byte increment mode 5 0 No effect on the RTC counter Increment the corresponding byte of the RTC counter 92 Rabbit 3000 Microprocessor 7 8 Watchd
96. the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 This bit is ignored and should be written with zero 2 1 00 Pulse Width Modulator interrupts are disabled 01 Pulse Width Modulator interrupts use Interrupt Priority 1 10 Pulse Width Modulator interrupts use Interrupt Priority 2 11 Pulse Width Modulator interrupts use Interrupt Priority 3 0 PWM output High for single block 1 Spread PWM output throughout the cycle Table B 26 PWM LSB 1 Register PWMLSB 1 Register PWL1R Address 0x008A Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 This bit is ignored and should be written with zero 2 1 00 Normal PWM interrupt operation 01 Suppress PWM interrupts seven out of eight iterations of PWM counter 10 Suppress PWM interrupts three out of four iterations of PWM counter 11 Suppress PWM interrupts one out of two iterations of PWM counter 0 PWM output High for single block i 1 Spread PWM output throughout the cycle 312 Rabbit 30
97. the output bits on the next match pulse It is neces sary to keep a shadow register for the parallel port unless the bit addressable feature of Ports D and E is used If you wish to read the time from the Timer B counter either during an interrupt caused by the match pulse or in some other interrupt routine asynchronous to the match pulse you will have to use a special procedure to read the counter because the upper 2 bits are in a different register than the lower 8 bits The following method is suggested 1 Read the lower 8 bits read TBCLR register 2 Read the upper 2 bits read TBCMR register 3 Read the lower 8 bits again read TBCLR register 4 If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits there has been a carry to the upper 2 bits In this case read the upper 2 bits again and decre ment those 2 bits to get the correct upper 2 bits Use the first read of the lower 8 bits This procedure assumes that the time between reads can be guaranteed to be less than 256 counts This can be guaranteed in most systems by disabling the priority 1 interrupts which will normally be disabled in any case in an interrupt routine It is inadvisable to disable the high priority interrupts levels 2 and 3 as that defeats their purpose If speed is critical the three reads of the registers can be performed without testing for the carry The three register values can be saved and the carry test can be perfo
98. the static memory chip in standby mode The RESOUT pin is also held high while the processor is powered down and bat tery power is supplied to VBAT This allows the RESOUT pin to be used to control power to the processor and the static RAM chip via a transistor It is also possible to force CS1 to be enabled at all times This is convenient if an external battery backup device is used that might slow down the transition of CS1 during the memory cycle Most users will not use this feature 3 3V FDV302P Main Power p channel 5ko f 100 kO nanmi EUM ICS Rabbit 3000 Rabbit 3000 VBAT SRAM RESOUT VDD Figure 8 1 Battery Backup Circuit User s Manual 115 DATA LINES 8 Rabbit 3000 P STATIC MEMORY ADDRESS LINES 20 FLASH 5 CS0 O o ics1 b 0 1 52 O WE OE1 WEO O O STATIC MEMORY RAM Figure 8 2 Typical Memory Chip Connection 116 Rabbit 3000 Microprocessor 8 2 Memory Mapping Overview See Section 3 2 Memory Mapping for a discussion of Rabbit memory mapping Figure 8 3 shows an overview of the Rabbit memory mapping The task of the memory mapping unit is to accept 16 bit addresses and translate them to 20 bit addresses The memory interface unit accepts the 20 bit addresses and generates control signals applied
99. the trailing edge of the write signal divide by 8 nnde Figure B 12 Short Chip Select Timing CLK 8 Write Operation User s Manual 305 T1 TWA T2 oscillator 1111111111111111 11111111 1111 clock spor DATA CSx WEx divide by 6 mode Figure B 13 Short Chip Select Timing CLK 6 Write Operation oscillator divide by 4 mode Figure B 14 Short Chip Select Timing CLK 4 Write Operation 306 Rabbit 3000 Microprocessor oscillator divide by 2 mode Figure B 15 Short Chip Select Timing CLK 2 Write Operation User s Manual 307 The timing diagrams below illustrate the actual timing for the 32KHz cases of write cycles In these cases the chip selects are active for one clock cycle before and one clock cycle after the trailing edge of the write signal Figure B 16 Short Chip Select Timing 2 kHz Write Operation Figure B 17 Short Chip Select Timing 4 kHz Write Operation 308 Rabbit 3000 Microprocessor 8 kHz operation Figure B 18 Short Chip Select Timing 8 kHz Write Operation 16 kHz operation Figure B 19 Short Chip Select Timing 16 kHz Write Operation User s Manual 309 32 kHz operation Figure B 20 Short Chip Select Timing 32 kHz Write Operation 310 Rabbit 3000 Microprocessor B 1 13 Pulse Width Modulat
100. timer is running when there is a need to do so Timers that are not used should be driven from the output of Al and the reload register should be set to 255 This will cause counting to be as slow as possible and consume minimum power As for general purpose timers Timer A has seven separate subtimer units Al and A2 A7 that are also referred to as timers Most likely if a serial port is going to be used and a timer is needed to provide the baud clock that timer will be set up to be driven directly from the clock and the interrupt associated with that timer will be disabled Serial port interrupts are generated by the serial port logic The value in the reload register can be changed while the timer is running to change the period of the next timer cycle When the reload register is initialized the contents of the count down counter may be unknown for example during power up initialization If interrupts are enabled then the first interrupt may take place at an unknown time Similarly if the timer output is being used to drive the clock for a parallel port or serial port the first clock may come at a random time If a periodic clock is desired it is probably not important when the first clock takes place unless a phase relationship is desired relative to a different timers A phase relationship between two timers can be obtained in several ways One way is to set both reload registers to zero and to wait long enough for both timers t
101. to 1 The updated MMIDR register is listed in Table B 20 NOTE Bits 7 was always written with a zero in the original Rabbit 3000 chip Table B 20 MMU Instruction Data Register MMU Instruction Data Register MMIDR Address 0x010 Bit s Value Description 0 8 bit internal I O addresses address range 0x0000 0x00FF 7 1 15 bit internal I O addresses address range 0x0000 0x 7FFF required to access internal I O addresses of 0x0100 and higher 6 0 This bit is ignored and will always return zero when read 0 Enable A16 and A19 inversion independent of instruction data 5 1 Enable A16 19 inversion controlled by bits 0 3 for data accesses only This enables the instruction data split for the separate I and D space 0 Normal CS1 operation 4 Force CS1 always active This will not cause any conflicts as long as the 1 memory using CS1 does not also share an Output Enable or Write Enable with another memory 0 Normal operation 1 For a DATASEG access invert A19 before MBxCR bank select decision 0 Normal operation 1 For a DATASEG access invert A16 0 Normal operation 1 For root access invert A19 before MBxCR bank select decision 0 Normal operation 1 For root access invert A16 User s Manual 295 B 1 11 External I O Improvements Three new features have been added to the external I O strobes the ability to invert the strobe signal the ab
102. to 40 and power to 20 compared to 3 3 V Naturally this complicates the selection of memories especially at 1 8 V It is important to know that the lowest speed crystal will not always give the lowest power consumption because when the crystal is divided internally the short chip select option can be used to reduce the chip select duty cycle of the flash memory or fast RAM greatly reducing the static current consumption associated with some memories In sleepy mode power consumption consists of the processor core the external recom mended external tiny logic 32 kHz oscillator and the memory The oscillator consumes 17 uA at 3 3 V and this drops rapidly to about 2 at 1 8 V The processor core con sumes between 3 and 50 uA at 3 3 V as the frequency is throttled from 2 kHz to 32 kHz and about 40 as much at 1 8 V If the flash memory specified above is used for memory and a self timed 106 ns chip select is used then the memory will consume 22 uA at 32 MHz and 1 4 uA at 2 KHz In addition to these items a low power reset controller may consume about 8 and CMOS leakage may consume several u A increasing with higher temperatures The graph below shows current consumption including the tiny logic core but not including memory or the reset controller 80 70 60 1 8V 50 2 22 40 27v z 3 0V cw X 3 3V 20 i 0 E 2 048 4 096 8 192 16 384 32 768 C
103. where the multiplier is 255T5 38 Rabbit 3000 Microprocessor 3 3 8 Input Output Instructions The Rabbit uses an entirely different scheme for accessing input output devices Any memory access instruction may be prefixed by one of two prefixes one for internal I O space and one for external 1 space When so prefixed the memory instruction is turned into an I O instruction that accesses that 1 space at the I O address specified by the 16 bit memory address used For example IOI LD A 0x85 loads A register with contents of internal I O register at location 0x85 LD IY 0x4000 IOE LD HL IY 5 get word from external I O location 0x4005 By using the prefix approach all the 16 bit memory access instructions are available for reading and writing I O locations The memory mapping is bypassed when I O operations are executed I O writes to the internal I O registers require only two clocks rather than the minimum of three clocks required for writes to memory or external I O devices User s Manual 39 3 4 How to Do It in Assembly Language Tips and Tricks 3 4 1 Zero HL in 4 Clocks BOOL HL 2 clocks clears carry HL is 1 or 0 RR HL 2 clocks 4 total get rid of possible 1 This sequence requires four clocks compared to six clocks for LD HL 0 3 4 2 Exchanges Not Directly Implemented HL lt gt HL eight clocks EX DE HL 2 clocks EX DE HL 4 clocks EX DE HL 2 clocks 8 total DE lt gt D
104. 0 0000 Kk O O OOOO 0000 01 OO00000 000 Q9 Q ttm O a I x gt gt 0 80 _ 10 00 0 05 L Ball Pitch 0 80 mm Ball Diameter 0 3 mm 0 25 0 35 4 060 020 Figure 5 5 BGA Package Outline 61 User s Manual 5 3 Rabbit Pin Descriptions Table 5 1 lists all the pins on the device along with their direction function and pin num ber on the package Table 5 1 Rabbit Pin Descriptions Pin Pin Pin Group Pin Name Direction Function Numbers Numbers LQFP TFBGA Hardware CLK Output Internal Clock 2 Bl CLK32K Input 32 kHz Oscillator In 49 L6 RESET Input Master Reset 46 M5 RESOUT Output Reset Output 50 M6 Main Oscillator In if an external clock is used this pin should be driven by XTALA1 Input the external clock see 113 B7 Technical Note TN235 for more information on external oscillator circuits XTALA2 Output Main Oscillator Out 114 7 CPU Buses ADDR 19 0 Output Address Bus various TET 10 15 18 D4 1 4 DATA 7 0 Bidirectional Data Bus 19 FI F4 GO Status Control WDTOUT Output WDT Time Out 43 J5 STATUS Output Instruction Fetch First 4 Cl Byte SMODE 1 0 Input Bootstrap Mode Select 44 45 K5 L5 CS0 Output Memory Chip Select 0 7 DI Memory CUP Output Memory Chip Select 1 47 J6 Selects 52 Memory Chip Select 2 3 B2 Memory
105. 0 A3 counter has not reached its terminal count read 1 A3 count done This status bit is cleared by a read of this register 3 0 A3 interrupt disabled write 1 A3 interrupt enabled 2 0 A2 counter has not reached its terminal count read 1 A2 count done This status bit is cleared by a read of this register 2 0 A2 interrupt disabled write 1 A2 interrupt enabled 1 0 1 counter has not reached its terminal count read 1 1 count done This status bit is cleared by a read of this register 1 0 1 interrupt disabled write 1 A interrupt enabled 0 0 Disable Timer A main clock perclk 2 write only 1 Enable Timer main clock perclk 2 User s Manual 153 The control register TACR is laid out as shown in Table 11 4 Table 11 4 Timer A Control Register Timer A Control Register TACR Address z 0x00A4 Bit s Value Description 0 Timer A7 clocked by the main Timer A clock i 1 Timer A7 clocked by the output of Timer 1 0 Timer clocked by the main Timer clock i 1 Timer A6 clocked by the output of Timer A1 0 Timer A5 clocked by the main Timer A clock 1 Timer 5 clocked by the output of Timer 1 0 Timer A4 clocked by the main Timer A clock i 1 Timer A4 clocked by the output of Timer 1 0 Timer A3 clocked by the main Timer A clock 1 Timer clocked by the output of Timer 1 0 Timer A2 clocked by the main T
106. 0 Quadrature Decoder interrupts are disabled 01 Quadrature Decoder interrupt use Interrupt Priority 1 i 10 Quadrature Decoder interrupt use Interrupt Priority 2 11 Quadrature Decoder interrupt use Interrupt Priority 3 Table 7 27 Quadrature Decoder Count Register Quad Decode Count Register QDC1R Address 0x94 QDC2R Address 0x96 Bit s Value Description 7 0 read The current value of the Quadrature Decoder counter is reported User s Manual 113 114 Rabbit 3000 Microprocessor 8 MEMORY INTERFACE AND MAPPING 8 1 Interface for Static Memory Chips Static memory chips generally have address lines data line a chip select line an output enable line and a write enable The Rabbit 3000 has these same lines that can connect directly to a number of static memory chips The chip selects are not completely inter changeable because certain chip selects have special functions When the processor starts up not in cold boot mode execution starts at address zero in the memory attached to CSO A static RAM should be connected to CS1 because Dynamic C development tools assume a static RAM connected to CS1 In addition CS1 has special features that support battery backing of static RAM When the processor power is removed but battery power is supplied to the battery power pin VBAT GSI is held in a high impedance state This allows a pull up resistor to the bat tery backup power to hold CS1 high and thus hold
107. 00 4 f L 266 Rabbit 3000 Microprocessor Instruction Byte 1 RR 11001011 00011111 RRC HL 11001011 RRC IX d 11011101 RRC IY d 11111101 RRC r 11001011 RRCA 00001111 RST v 11 111 SBC IX d 11011101 SBC IY d 11111101 SBC A HL 10011110 SBC A n 11011110 SBC A r 10011 r SBC HL ss 11101101 SCF 00110111 SET b HL 11001011 SET b IX d 11011101 SET b IY d 11111101 SET b r 11001011 SLA HL 11001011 SLA IX d 11011101 SLA IY d 11111101 SLA r 11001011 SRA HL 11001011 SRA IX d 11011101 SRA IY d 11111101 SRA r 11001011 SRL HL 11001011 SRL IX d 11011101 SRL IY d 11111101 SRL r 11001011 SUB HL 10010110 SUB IX d 11011101 SUB IY d 11111101 SUB n 11010110 SUB r 10010 r XOR HL 10101110 XOR IX d 11011101 XOR IY d 11111101 XOR n 11101110 XOR r 10101 r ZINTACK interrupt Byte 2 00011 r 00001110 11001011 11001011 00001 r v22 3 10011110 10011110 n 01ss0010 11 b 110 11001011 11001011 11 b r 00100110 11001011 11001011 00100 r 00101110 11001011 11001011 00101 r 00111110 11001011 11001011 00111 r 10010110 10010110 10101110 10101110 Byte 3 22524852 oo Byte 4 clk 00001110 13 00001110 13 4 2 4 5 7 only 8 adco 9 d 9 5 4 2 4 2 10 ba d 11 b 110 13 4 10 d 00100110 13 d 00100110 13 4 10 d 00101110 13 d 0
108. 00 Microprocessor Table B 27 PWM LSB 2 and 3 Registers PWM LSB x Register PWL2R Address 0x008C PWL3R Address 0x008E Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 1 These bits are ignored and should be written with zero 0 PWM output High for single block 1 Spread PWM output throughout the cycle User s Manual 313 B 1 14 Quadrature Decoder Improvements The quadrature decoder counters can now be expanded to 10 bits instead of 8 bits This is controlled by bit 5 in QDCR listed in Table B 28 The additional two bits can be read in the QDCxHR registers listed in Table B 29 NOTE Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip Table B 28 Quadrature Decoder Control Register Quadrature Decoder Control Register QDCR Address 0x0091 Bit s Value Description 7 6 00 Disable Quadrature Decoder 2 inputs Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement 01 This bit combination is reserved and should not be used 10 Quadrature Decoder 2 inputs from P
109. 000 0x4FFF in WP Segment x 0 Disable write protect for address offset 0x3000 0x3FFF in WP Segment x 1 Enable write protect for address offset 0x3000 0x3FFF in WP Segment x 0 Disable 4K write protect for address offset 0x2000 0x2FFF in WP Segment x 1 Enable 4K write protect for address offset 0x2000 0x2FFF in WP Segment x 0 Disable write protect for address offset 0x 1000 0x 1 FFF in WP Segment x 1 Enable write protect for address offset 0 1000 0 1 in WP Segment x 0 Disable write protect for address offset 0x0000 0x0FFF in WP Segment x l 1 Enable write protect for address offset 0x0000 0xOFFF in WP Segment x User s Manual 287 Table B 11 Write Protect Segment x High Register Write Protect Segment x High Register WPSAHR Address 0x0482 WPSBHR Address 0x0486 Bit s Value Description 0 Disable write protect for address offset OXF000 0xFFFF in WP Segment x 1 Enable write protect for address offset OxFOOO OxFFFF in WP Segment x 0 Disable write protect for address offset 0 000 in WP Segment x 1 Enable write protect for address offset 0 000 in WP Segment x 0 Disable write protect for address offset OXD000 0xDFFF in WP Segment x i 1 Enable write protect for address offset OxD000 OxDFFF in WP Segment x 0 Disable write protect for address offset 0 000 0
110. 0000 Interrupt 1 Control Register 0 0099 w xx000000 Timer A Control Status Register TACSR 0x00A0 R W 00000000 Timer A Prescale Register TAPR 0 00 1 XXXXXXX Timer A Time Constant 1 Register TATIR 0x00A3 w XXXXXXXX Timer A Control Register TACR 0x00A4 W 00000000 Timer A Time Constant 2 Register TAT2R 0x00A5 W XXXXXXXX Timer A Time Constant 8 Register TAT8R 0x00A6 W XXXXXXXX Timer A Time Constant 3 Register TAT3R 0x00A7 W XXXXXXXX Timer A Time Constant 9 Register TATOR 0x00A8 W XXXXXXXX Timer A Time Constant 4 Register TAT4R 0x00A9 W XXXXXXXX Timer A Time Constant 10 Register 10 0x00AA W XXXXXXXX Timer A Time Constant 5 Register TATSR 0 00 Timer A Time Constant 6 Register TAT6R 0 00 Timer A Time Constant 7 Register TAT7R 0 00 Timer B Control Status Register TBCSR 0x00B0 R W xxxxx000 Timer B Control Register TBCR 0 00 1 W xxxx0000 Timer B MSB 1 Register TBMIR 0x00B2 W XXXXXXXX Timer B LSB 1 Register TBLIR 0 00 3 W XXXXXXXX Timer B MSB 2 Register TBM2R 0 00 4 W XXXXXXXX Timer B LSB 2 Register TBL2R 0 00 5 W XXXXXXXX Timer B Count MSB Register TBCMR 0 00 R XXXXXXXX Timer B Count LSB Register TBCLR 0x00BF R XXXXXXXX Serial Port A Data Register SADR 0x00C0 R W XXXXXXXX Serial Port A Address Register SAAR 0x00C1 W XXXXXXXX Serial Port A Long Stop Register SALR 0x00C2 W XXXXXXXX Serial Port A Status Register SASR 0x00C3 R 0xx00000 Serial Port
111. 0000 Timer A Time Constant 2 Register TAT2R 5 W XXXXXXXX Timer A Time Constant 8 Register TAT8R OxA6 W XXXXXXXX Timer A Time Constant 3 Register TAT3R OxA7 W XXXXXXXX Timer A Time Constant 9 Register TATOR OxA8 w XXXXXXXX Timer A Time Constant 4 Register TAT4R 0 9 Timer A Time Constant 10 Register TATIOR OxAA w XXXXXXXX 76 Rabbit 3000 Microprocessor Table 6 2 Rabbit Internal l O Registers continued Register Name Mnemonic I O Address R W Reset Timer A Time Constant 5 Register TATSR OxAB w XXXXXXXX Timer A Time Constant 6 Register TAT6R OxAD W XXXXXXXX Timer A Time Constant 7 Register TAT7R OxAF W XXXXXXXX Timer B Control Status Register TBCSR OxBO R W XXxxx000 Timer B Control Register TBCR OxB1 W xxxx0000 Timer B MSB 1 Register TBMIR 0xB2 W XXXXXXXX Timer B LSB 1 Register TBLIR OxB3 W XXXXXXXX Timer B MSB 2 Register TBM2R OxB4 W XXXXXXXX Timer B LSB 2 Register TBL2R OxB5 W XXXXXXXX Timer B Count MSB Register TBCMR OxBE R XXXXXXXX Timer B Count LSB Register TBCLR OxBF R XXXXXXXX Serial Port A Data Register SADR 0xCO R W XXXXXXXX Serial Port A Address Register SAAR 0 1 R W XXXXXXXX Serial Port A Long Stop Register SALR 0xC2 R W XXXXXXXX Serial Port A Status Register SASR 0xC3 R 0xx00000 Serial Port A Control Register SACR 0xC4 W xx000000 Serial Port A Extended Register SAER 0xC5 w 00000000
112. 00000 Memory Timing Control Register MTCR 0x0019 W xxxx0000 00000000 Breakpoint Debug Control Register BDCR 0 001 W Oxxxxxxx 00000000 I O Bank 0 Control Register IBOCR 0x0080 W 000000xx 00000000 I O Bank 1 Control Register IBICR 0x0081 W 000000xx 00000000 I O Bank 2 Control Register IB2CR 0x0082 W 000000xx 00000000 I O Bank 3 Control Register IB3CR 0x0083 W 000000xx 00000000 I O Bank 4 Control Register IB4CR 0x0084 W 000000xx 00000000 I O Bank 5 Control Register 5 0 0085 W 000000xx 00000000 Bank 6 Control Register IB6CR 0x0086 W 000000xx 00000000 I O Bank 7 Control Register IB7CR 0x0087 W 000000xx 00000000 PWM LSB 0 Register PWLOR 0x0088 W XXXXXXXX 00 PWM LSB 1 Register PWLIR 0 008 W xxxxx00x PWM LSB 2 Register PWL2R 0x008C W XXXXXXXX 00 PWM LSB 3 Register PWL3R 0 008 W XXXXx00x Quad Decode Control Register QDCR 0x0091 W 00 0000 00000000 User s Manual 279 B 1 2 Peripheral and ISR Address Table B 4 Rabbit 3000 Address Ranges and Interrupt Service Vectors On Chip Peripheral I O Address Range ISR Starting Address System Management 0 0000 0 000 7 1 0 0 00 Memory Management 0 0010 0 001 and 0x0400 0x04FF No interrupts Slave Port 0 0020 0 002 UIR 7 1 0 0 80 Parallel Port A 0 0030 0 0037 interrupts Parallel Port
113. 0101110 13 4 10 d 00111110 13 d 00111110 13 4 5 9 4 9 4 2 5 i s 9 9 4 2 10 fr fr rh fr fr fr fr fr fr fr fr Fh Fh Fh H fr Fh Fh fr Fh fr fr fr fr fr fr fr fr fr fr fr m 9 9 9 39 39 39 39 HF 39 OF m m 2 9 39 9 39 9 39 9 9 9 39 9 t lt q lt lt lt lt pP pP DP E E t D D t Ht p e ox o O O O O O User s Manual 267 268 Rabbit 3000 Microprocessor APPENDIX THE RABBIT PROGRAMMING The programming port provides a standard physical and electrical interface between a Rabbit based system and the Dynamic C programming platform A special interface cable and converter connects a PC serial port to the programming port The programming port is implemented by means of a 10 pin standard 2 mm connector Of course the user can change the physical implementation of the connector if he so desires With this setup the PC can communicate with the target reset it and reboot it The DTR line on the PC serial interface is used to drive the target reset line which should be drivable by an external CMOS driver The STATUS pin is used to by the Rabbit based target to request attention when a breakpoint
114. 0111 12 ns nominal low time ii 1000 13 ns nominal low time 1001 14 ns nominal low time 1010 15 ns nominal low time 1011 16 ns nominal low time 1100 17 ns nominal low time 1101 18 ns nominal low time 1110 19 ns nominal low time 1111 20 ns nominal low time The clock doubler uses an on chip delay circuit that must be programmed by the user at startup if there is a need to double the clock Table 7 8 lists the recommended delays for the Global Clock Double Register for various oscillator frequencies Table 7 8 Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value Frequency Range 15 lt 7 3728 MHz 13 7 3728 11 0592 MHz 9 11 0592 16 5888 MHz 6 16 5888 20 2752 MHz 3 20 2752 52 8384 MHz 0 252 8384 MHz User s Manual 83 When the clock doubler is used and there is no subsequent division of the clock the output clock will be asymmetric as shown in Figure 7 2 Oscillator Oscillator delayed and inverted Doubled clock Delay gt time Address CS Example Write Cycle Data out write pulse early write pulse option Address CS X Example Read Cycle output enb data out from mem N V early output enb option Figure 7 2 Effect of Clock Doubler The doubled clock low time is subject to wide
115. 01550011 n m 15 d LD SP n HL 11010100 n 11 LD SP n IX 11011101 11010100 n 13 EE LD SP n IY 11111101 11010100 n 13 s 264 Rabbit 3000 Microprocessor Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I LD A BC 00001010 6 r s LD A DE 00011010 6 r LD A mn 00111010 n m 9 r s LD A EIR 11101101 01010111 4 fr LD A IIR 11101101 01011111 4 fr LD A XPC 11101101 01110111 4 r LD dd mn 11101101 01441011 n m 13 r s LD dd BC 11101101 01dd1001 4 LD dd DE 11101101 01dd0001 4 LD mn 00dd0001 m 6 r LD bc mn 00000001 LD de mn 00010001 LD hl mn 00100001 LD sp mn 00110001 LD EIR A 11101101 01000111 4 LD HL HL d 11011101 11100100 d 11 r s LD HL IX d 11100100 d 9 r s LD HL IY d 11111101 11100100 d 11 r s LD HL mn 00101010 n m 11 r s LD HL SP n 11000100 9 r LD HL IX 11011101 01111100 4 LD HL IY 11111101 01111100 4 LD 11101101 01001111 4 LD mn 11011101 00101010 n 13 s LD IX SP n 11011101 11000100 n 11 LD IX HL 11011101 01111101 4 LD IX mn 11011101 00100001 n m 8 LD IY mn 11111101 00101010 n m 13 s LD SP n 11111101 11000100 n 11 LD IY HL 11111101 01111101
116. 0R 0x0089 w XXXXXXXX PWM LSB 1 Register PWLIR 0x008A w xxxxx00x PWM MSB 1 Register PWMIR 0x008B w XXXXXXXX PWM LSB 2 Register PWL2R 0x008C w 00 PWM MSB 2 Register PWM2R 0x008D W XXXXXXXX PWM LSB 3 Register PWL3R 0 008 W 00 PWM MSB 3 Register PWM3R 0x008F w XXXXXXXX Input Capture Ctrl Status Register ICCSR 0x0056 R W 00000000 Input Capture Control Register ICCR 0x0057 w 00 Input Capture Trigger 1 Register ICTIR 0x0058 W 00000000 Input Capture Source 1 Register ICSIR 0x0059 W XXXXXXXX Input Capture LSB 1 Register ICLIR 0x005A R XXXXXXXX Input Capture MSB 1 Register ICMIR 0x005B R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0x005C W 00000000 Input Capture Source 2 Register ICS2R 0x005D W XXXXXXXX Input Capture LSB 2 Register ICL2R 0x005E R XXXXXXXX Input Capture MSB 2 Register ICM2R 0x005F R XXXXXXXX Quad Decode Ctrl Status Register QDCSR 0x0090 R W XXXXXXXX Quad Decode Control Register QDCR 0x0091 W 00000000 Quad Decode Count 1 Register QDCIR 0x0094 R XXXXXXXX Quad Decode Count High Register QDCIHR 0x0095 R XXXXXXXX Quad Decode Count 2 Register QDC2R 0x0096 R XXXXXXXX Quad Decode Count 2 High Register QDC2HR 0x0097 R XXXXXXXX User s Manual 331 Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Interrupt 0 Control Register IOCR 0x0098 W xx00
117. 0x0388 W 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 User s Manual 277 Table B 2 Reset State of New Rabbit 3000A I O Registers continued Register Name Mnemonic A R W Reset External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0x03A0 W 00000000 Timer B User Enable Register TBUER 0x03B0 W 00000000 Serial Port A User Enable Register SAUER 0x03C0 W 00000000 Serial Port B User Enable Register SBUER 0x03DO W 00000000 Serial Port C User Enable Register SCUER 0x03E0 W 00000000 Serial Port D User Enable Register SDUER 0x03F0 W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port F User Enable Register SFUER 0x03D8 W 00000000 Enable Dual Mode Register EDMR 0x0420 W 00000000 Quad Decode Count High Register QDCIHR 0x0095 Quad Decode Count 2 High Register QDC2HR 0x0097 278 Rabbit 3000 Microprocessor Table B 3 Reset State of I O Registers Modified Rabbit 3000A VO Rabbit Rabbit Register Name Mnemonic Address R W 3000 3000A Reset Reset Global Power Save Control Register GPSCR 0x000D W 0000x000 00000000 Global Revision Register GREV 0x002F R 0xx00000 0xx00001 MMU Expanded Code Register MECR 0x0018 R W xxxxx000 000
118. 0x8F Bit s Value Description The most significant eight bits for the Pulse Width Modulator count are stored 7 0 write With a count of n the PWM output will be High for n 1 clocks out of the 1024 clocks of the PWM counter 104 Rabbit 3000 Microprocessor 7 13 Input Capture The two channel Input Capture can be used to time input signals from various port pins Each Input Capture channel consists of a sixteen bit counter that is clocked by the output of Timer A8 and can be connected to one or two out of sixteen parallel port pins The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt The programmed conditions can also be used to start and stop the counter Register Name Mnemonic Address R W Reset Input Capture Ctrl Status Register ICCSR 0x56 R W 00000000 Input Capture Control Register ICCR 0x57 W 00 Input Capture Trigger 1 Register ICTIR 0x58 W 00000000 Input Capture Source 1 Register ICSIR 0x59 W XXXXXXXX Input Capture LSB 1 Register ICLIR 0 5 R XXXXXXXX Input Capture MSB 1 Register ICMIR 0x5B R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0x5C W 00000000 Input Capture Source 2 Register ICS2R 0 5 w XXXXXXXX Input Capture LSB 2 Register ICL2R 0 5 R XXXXXXXX Input Capture MSB 2 Register ICM2R Ox5F R XXXXXXXX Because the Input Capture channels synchroniz
119. 1 1 0 0 Serial Port B async cks HR 7 1 0 OxDO Serial Port F async hdlc 7 1 1 OxDO Serial Port C async cks HR 7 1 0 OxEO Serial Port D async cks IIR 7 11 0 OxFO RST 10 instruction UIR 7 1 0 0x20 RST 18 instruction UIR 7 1 0 0x30 RST 20 instruction IIR 7 1 0 0x40 RST 28 instruction IIR 7 1 0 0x50 RST 38 instruction UIR 7 1 0 0x70 72 Rabbit 3000 Microprocessor 6 1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6 2 The registers within the CPU affected by reset are the Stack Pointer SP the Program Counter PC the IIR register the EIR register and the IP register The IP register is set to all ones disabling all interrupts while all of the other listed CPU registers are reset to all zeros Table 6 2 Rabbit Internal I O Registers Register Name Mnemonic l O Address R W Reset Global Control Status Register GCSR 0x00 R W 11000000 Global Clock Modulator 0 Register GCMOR 0x0A W 00000000 Global Clock Modulator 1 Register GCMIR 0x0B W 00000000 Global Power Save Control Register GPSCR 0x0D w 0000x000 Global Output Control Register GOCR OxOE W 00000000 Global Clock Double Register GCDR OxOF W 00000000 MMU Instructio
120. 10 written to bits 3 2 enables the slave port disabling Parallel Port A and vari ous other port lines Bits 3 2 are automatically set to a 10 if a cold boot is done via the slave port If bit 3 is 0 then bit 2 controls whether Parallel Port A is an input bit 2 0 or an output bit 2 1 A 11 written to bits 3 2 enables the Auxilliary I O bus User s Manual 205 Bits 1 0 This 2 bit field sets the priority of the slave port interrupt The interrupt is disabled by 0 0 Table 13 3 describes the slave port status register The status register has 6 bits that are set if the particular register is full That means that the register has been written by the processor that can write to it but it has not been read by the processor that can read it The bits for SPDOR are used to control the slave interrupt and the handshaking lines as shown in Figure 13 3 Table 13 3 Slave Port Status Register SPSR adr 0x023 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 set by ist setby 1 setby 1 set by 222865 set by 1 61 by save UM master master master PR IL slave write slave write Men ite t write to write to write to to SPDOR to SPD2R to SPDIR SPD0R We O SPD2R SPDIR SPDOR 5 Cleared Cleared SPD0R Cleared by Cleared Cleared Cleared Cleared when when Cleared by master when when slave when slave when slave master master slave Walle ds reads reads reads reads master toSPSR
121. 16 384 kHz 101 32 kHz oscillator divided by four 8 192 kHz 110 32 kHz oscillator divided by eight 4 096 kHz 111 32 kHz oscillator divided by sixteen 2 048 kHz Itis anticipated that these measures would reduce operating current consumption to as low as 20 uA plus some additional leakage that would be significant at high operating temperatures 88 Rabbit 3000 Microprocessor MEMCSxB MEMOExB MEMCSxB MEMOExB Figure 7 5 Self Timed Chip Select Memory Read Cycle User s Manual 89 7 6 Output Pins CLK STATUS WDTOUT BUFEN Certain output pins can have alternate assignments as specified in Table 7 9 Table 7 9 Global Output Control Register GOCR OxOE Bit s Value Description 00 CLK pin is driven with peripheral clock 01 CLK pin is driven with peripheral clock divided by 2 sa 10 CLKpinislow 11 CLK pin is high 00 STATUS pin is active low during a first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge Du 10 STATUS pin is low 11 STATUS pin is high 1 WDTOUTB pin is low 1 cycle minimum 2 cycles maximum of 32 kHz 0 WDTOUTB pin follows watchdog function 2 x This bit is ignored 00 BUFEN pin is active low during external I O cycles 01 BUFEN pin is active low during data memory accesses 10 BUFEN pin is low 11 BUFEN pin is high 90 Rabbit 3000 Microprocesso
122. 170 167 SEAR ere 167 SFERA iii 167 SEDR usss 167 SEER oss 167 167 SESR is siti 167 shadow registers 243 SPCR 22022 130 204 205 SPDXR 204 204 206 stack pointer 22 status register 22 SIKER oem 290 STKHLR 290 STKLLR eem 290 SWDTR i22 292 System User mode 319 TACR 151 154 TACSR 151 152 151 154 TATXR sig iet ita 151 TBELR usa 156 158 TBCMR 156 TBER iesu 156 157 TBCSR 156 157 TBLXR 2 156 158 TBMXR 156 158 WDTCR mm 93 202 WDTTR 94 etn 284 WPHR tii si i e a 285 WPLR 284 WPSXR 286 WPxHR 287 WPXLR sss 286 XPC register 26 27 scd eA 95 96 revision history 273 2776 alternate output port connec tion for numerous peripher als ue RR 276 UJ aes i bete 276 external I O interface enhance Tents au besi pass 276 ID registers for version 276 integrated Schmitt trigger 276 internal I O address space 276 interrupt after I O with short CSx enabled bug fix 276 IrDA bug fix 276 LDIR LDDR with wait states bug fix eee 276 memory protection 276 multiply add and multiply SUbtr ct 276 p
123. 18 sleepy mode 231 233 I O bank control 145 write time delays 218 power management 241 IBxCR 146 152 154 157 296 memory interface 25 119 power usage standby mode 210 ICER 105 108 battery backup 115 programming port 269 ICOSR 105 107 T alternate programming port 105 109 typical connections 160 V 270 1 105 109 memory mapping 117 use as diagnostic port 270 ICSxR 105 109 memory mapping unit 23 24 PWM modulator 103 311 oh ies 105 108 memory protection 284 PWM outputs 17 50 index registers 22 memory timing 122 internal I O registers 271 memory mapping unit 117 Q interrupt priority register 22 ModDUS eie 196 A ocn 110 interrupts 44 ncoderanur eet MBOCR G 319 MBECR ce n saat aaa 120 cese tete ens 293 R MECR 40 4 122 revision block effects 294 memory bank control 120 System User mode 318 Rabbit 00 memory mapping seg A iae 51 block diagram munas 5 ments 118 oscillator 209 comparison With Rabbit 2000 MMIDR 121 124 295 a 209 sss 259 MTCR
124. 2 Bits 1 0 Write Only Read Only Write Only Write Only 00 disable slave port port A is a byte wide input port 00 no slave 01 disable slave port port A erupt 0 obey SMODE Reads SMODE is a byte wide output port pus pins m 10 enable the slave port pp enable slave 1 ignore SMODE mode1 smode0 11 Enable the auxilliary I O interrupt pins bus Parallel Port A is used 01 priority 1 for the data bus and Parallel 10 priority 2 Port B 7 2 is used for the 11 priority 3 address bus The functionality of the bits is as follows Bit 7 If set to 0 the cold boot feature will be enabled Normally this bit is set to a 1 after the cold boot is complete The cold boot for the slave port is enabled automatically if SMODE1 SMODEO lines are set to 0 1 after the reset ends This features disables the normal operation of the processor and causes commands to be accepted via the slave port register SPDOR These commands cause data to be stored in memory or I O space When the master that is managing the cold boot has finished setting up memory and I O space the SMODEI SMODEO pins are changed to code 0 0 which causes execution to start at address zero Typically this will start execution of a secondary boot program At some point bit 7 will be set to a 1 so that the SMODEX pins can be used as normal input pins Bits 6 5 be used to read the input pins SMODE SMODEO Bits 3 2 A
125. 24 R W 0xx00000 Port A Data Register PADR 0x0030 R W XXXXXXXX Port B Data Register PBDR 0x0040 R W 00 Port B Data Direction Register PBDDR 0x0047 w 11000000 Port C Data Register PCDR 0x0050 R W x0x1x1x1 Port C Function Register PCFR 0x0055 W x0x0x0x0 Port D Data Register PDDR 0x0060 R W XXXXXXXX Port D Control Register PDCR 0x0064 w xx00xx00 Port D Function Register PDFR 0x0065 W XXXXXXXX Port D Drive Control Register PDDCR 0x0066 W XXXXXXXX Port D Data Direction Register PDDDR 0x0067 W 00000000 Port D Bit 0 Register PDBOR 0x0068 W XXXXXXXX Port D Bit 1 Register PDBIR 0x0069 W XXXXXXXX User s Manual 329 Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Port D Bit 2 Register PDB2R 0x006A w XXXXXXXX Port D Bit 3 Register PDB3R 0x006B w XXXXXXXX Port D Bit 4 Register PDB4R 0x006C W XXXXXXXX Port D Bit 5 Register PDB5R 0x006D W XXXXXXXX Port D Bit 6 Register PDB6R 0 006 w XXXXXXXX Port D Bit 7 Register PDB7R 0x006F w XXXXXXXX Port E Data Register PEDR 0x0070 R W XXXXXXXX Port E Control Register PECR 0x0074 W xx00xx00 Port E Function Register PEFR 0x0075 W 00000000 Port E Data Direction Register PEDDR 0x0077 W 00000000 Port E Bit 0 Register PEBOR 0x0078 W XXXXXXXX Port E Bit 1 Register PEBIR 0x0079 W XXXXXXXX Port E Bit 2 Register PEB2R 0x007A W XXXXXXXX Port E Bit 3 Register PE
126. 2FFFF l 1 Enable 64K write protect for physical address 0x20000 0x2FFFF 0 Disable 64K write protect for physical address 0x 10000 0 1FFFF 1 Enable 64K write protect for physical address 0 10000 0 1 0 Disable 64K write protect for physical address 0x00000 0xOFFFF 1 Enable 64K write protect for physical address 0 00000 0 User s Manual 285 Table B 8 Write Protect High Register Write Protect High Register WPHR Address 0x0461 Bit s Value Description 0 Disable 64K write protect for physical address OXF0000 0xFFFFF 1 Enable 64K write protect for physical address 0xF0000 0xFFFFF 0 Disable 64K write protect for physical address 0 0000 1 Enable 64K write protect for physical address OXE0000 0xEFFFF 0 Disable 64K write protect for physical address 0xD0000 0xDFFFF 1 Enable 64K write protect for physical address 0xD0000 0xDFFFF 0 Disable 64K write protect for physical address 0xC0000 0xCFFFF 1 Enable 64K write protect for physical address 0xC0000 0xCFFFF 0 Disable 64K write protect for physical address 0 0000 1 Enable 64K write protect for physical address 0xBO000 OxBFFFF 0 Disable 64K write protect for physical address 0x A0000 0x AFFFF 1 Enable 64K write protect for physical address 0x A0000 0x AFFFF 0 Disable 64K write protect for physical address 0
127. 3 V 40 C to 85 C Adr Bus 60 pF Clock Period Clock Doubler Memory Address Memory Output Frequency Nominal Delay Access Enable Access MHz ns ns ns ns 18 43 54 20 97 60 22 11 45 20 78 51 24 00 42 19 72 45 25 80 39 17 66 43 29 49 34 16 56 37 44 24 22 5 10 33 5 22 All important signals on the Rabbit 3000 are output synchronized with the internal clock The internal clock is closely synchronized with the external clock CLK that may be optionally output from pin 2 of the TQFP package The delay in signal output depends on the capacitive load on the output lines In the case of the address lines which are critically important for establishing memory access time requirements the capacitive loading is usually in the range of 25 100 pF and the load is due to the input capacitance of the mem ory devices and PC trace capacitance Delays are expressed from the waveform midpoint in keeping with the convention used by memory manufacturers User s Manual 215 Figure 16 1 illustrates the parameters used to describe memory access time _ capacitive lt loading _f lag setup time data to clock X Figure 16 1 Parameters Used to Describe Memory Access Time Table 16 2 lists the delays in gross memory access time for several values of Vpp Table 16 2 Data and Clock Delays Vpp 10 Temp 40 C 85 C maximum
128. 32 768 kHz clock The 32 768 kHz clock is needed for the battery backable clock the watchdog timer and the cold boot function The main oscillator provides the run time clock for the microproces sor Figure 14 1 shows the main oscillator circuit TN235 External 32 768 kHz Oscillator Circuits provides further information on the 32 768 kHz oscillator circuit and selecting the values of components to use in the oscillator circuit XTALB2 33 pr 11 XTALB1 Main Oscillator Circuit Figure 14 1 Rabbit 3000 Main Oscillator Circuit NOTE You may have to adjust resistors and capacitors for various frequencies and crystal load capacitances The 32 768 kHz oscillator is slow to start oscillating after power on For this reason wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure If the clock is battery backed there will be no startup delay since the oscillator is already oscillating The startup delay may be as much as 5 seconds Crys tals with low series resistance R lt 35 will start faster User s Manual 209 14 1 Low Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage Thus operating at 3 3 V instead of 5 V will reduce the power consump tion by a factor of 10 9 25 or 43 of the power required at 5 V The clock speed 15 reduced proportionally to the voltage at the lower operating voltage
129. 4 LD IY mn 11111101 00100001 n m 8 LD r HL 01 r 110 5 r s LD r IX d 11011101 01 r 110 d 9 x 8 LD r 11111101 01 r 110 d 9 r s LD r g 01 r g 2 r EE LD r n 00 r 110 n 4 r LD SP HL 11111001 2 LD SP IX 11011101 11111001 4 LD SP IY 11111101 11111001 4 LD XPC A 11101101 01100111 4 LDD 11101101 10101000 10 d LDDR 11101101 10111000 6 7i d LDI 11101101 10100000 10 LDIR 11101101 10110000 6 7i d LDP HL HL 11101101 01100100 12 LDP IX HL 11011101 01100100 12 LDP IY HL 11111101 01100100 12 LDP mn HL 11101101 01100101 n m 15 LDP mn IX 11011101 01100101 n m 15 LDP mn IY 11111101 01100101 n m 15 User s Manual 265 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A ISZVC LDP HL HL 11101101 01101100 10 LDP HL IX 11011101 01101100 10 LDP HL IY 11111101 01101100 10 LDP HL mn 11101101 01101101 n 13 LDP IX mn 11011101 01101101 n 13 LDP IY mn 11111101 01101101 n 13 LJP nbr mn 11000111 n m nbr 10 LRET 11101101 01000101 13 MUL 11110111 12 NEG 11101101 01000100 4 fr V NOP 00000000 2 OR HL 10110110 5 fr L 0 OR IX d 11011101 10110110 d 9 fr s LO OR IY d 11111101 10110110 d 9 fr s
130. 4 writes 305 306 307 308 309 310 watchdog timer 93 secondary watchdog timer 292 writes short chip select timing 297 X XPC register 26 340 Rabbit 3000 Microprocessor
131. 55 8 bit Shifts and Rotates on page 255 Instruction Prefixes on page 256 Block Move Instructions on page 256 Control Instructions Jumps and Calls on page 257 Miscellaneous Instructions on page 257 Privileged Instructions on page 258 Instructions in Alphabetical Order With Binary Encoding on page 261 User s Manual 247 Spreadsheet Conventions ALTD A Column Symbol Key Flag Description f ALTD selects alternate flags fr ALTD selects alternate flags and register r ALTD selects alternate register s ALTD operation is a special case IOI and IOE 1 Column Symbol Key Flag Description b IOI and IOE affect source and destination d IOI and IOE affect destination s IOI and IOE affect source Flag Register Key S Z LVv c Description Sign flag affected Sign flag not affected Zero flag affected Zero flag not affected L LV flag contains logical check result flag contains arithmetic overflow result 0 LV flag is cleared LV flag is affected Carry flag is affected Carry flag is not affected 0 Carry flag is cleared 1 Carry flag is set The L V logical overflow flag serves a dual purpose L V is set to 1 for logical operations if any of the four most significant bits of the result are 1 and L V is reset to 0 if all four of the mos
132. 6 Stack Protection o ae eontra teer er EORR TA RAM Segment Relocation eter te ei eee nt 8 secondary Watchdog TIME dispensi ettet e RR dei etes re rtg 9 New Opcodes 5 bte Pepe e UO petente 10 Expanded I O Memory Addressing 2 11 External T O Improvements nn n uu nennen trennen etre tnter eren nne 12 Short Chip Select Timing for Writes 13 Pulse Width Modulator Improvements eeeceeeeeeceseeeeecaeeseecaeceaecseceaeeecnseeeeeees 14 Quadrature Decoder Improvements enne eene nennen entente ins with Alternate FUNCTIONS 2 ua EERE rN Enss wol s S s w m Appendix C System User Mode 317 1 System User Mode Op od S eese eene nnne neret nenne etre nee 72 System User Re sisters 4 III SR DR a C 3 1 Peripheral Interrupt Prioritization 2 C 4 Using the System User CAT Memory Protection Only te a 4 2 Mixed System User Mode Operation 2 40422 2221 120 00 00000000000000 eere nennen C 4 3 Complete Operating System eee prune pi tre Appendix D Rabbit 3000A Internal I O Registers 327 Notice to Users 335 Index 337 U
133. 90000 0 9 i 1 Enable 64K write protect for physical address 0x90000 0x9FFFF 0 Disable 64K write protect for physical address 0x80000 0x8FFFF j 1 Enable 64K write protect for physical address 0x80000 0x8FFFF Table B 9 Write Protect Segment x Register Write Protect Segment x Register WPSAR Address 0x0480 WPSBR Address 0x0484 Bit s Value Description 7 4 These bits are reserved and should be written with all zeros 3 0 When these four bits match bits 19 16 of the physical address write protect that 64K range in 4K increments using WPSxLR and WPSxHR 286 Rabbit 3000 Microprocessor Table B 10 Write Protect Segment x Low Register Write Protect Segment x Low Register WPSALR Address 0x0481 WPSBLR Address 0x0485 Bit s Value Description 0 Disable write protect for address offset 0x7000 0x7FFF in WP Segment x 1 Enable write protect for address offset 0x7000 0x7FFF in WP Segment x 0 Disable write protect for address offset 0x6000 0x6FFF in WP Segment x 1 Enable write protect for address offset 0x6000 0x6FFF in WP Segment x 0 Disable write protect for address offset 0x5000 0x5FFF in WP Segment x 1 Enable write protect for address offset 0x5000 0x5FFF in WP Segment x 0 Disable write protect for address offset 0 4000 in WP Segment x 1 Enable write protect for address offset 0x4
134. A Control Register SACR 0x00C4 W xx000000 Serial Port A Extended Register SAER 0 00 5 00000000 Serial Port B Data Register SBDR 0x00D0 R W XXXXXXXX 332 Rabbit 3000 Microprocessor Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Serial Port B Address Register SBAR 0x00D1 W XXXXXXXX Serial Port B Long Stop Register SBLR 0x00D2 W XXXXXXXX Serial Port B Status Register SBSR 0x00D3 R 0xx00000 Serial Port B Control Register SBCR 0x00D4 W xx000000 Serial Port B Extended Register SBER 0x00D5 W 00000000 Serial Port C Data Register SCDR 0 00 R W XXXXXXXX Serial Port C Address Register SCAR 0 00 1 W XXXXXXXX Serial Port C Long Stop Register SCLR 0x00E2 W XXXXXXXX Serial Port C Status Register SCSR 0x00E3 R 0xx00000 Serial Port C Control Register SCCR 0 00 4 W xx000000 Serial Port C Extended Register SCER 0x00E5 w 00000000 Serial Port D Data Register SDDR 0x00F0 R W XXXXXXXX Serial Port D Address Register SDAR 0x00F1 W XXXXXXXX Serial Port D Long Stop Register SDLR 0x00F2 W XXXXXXXX Serial Port D Status Register SDSR 0x00F3 R 0 00000 Serial Port D Control Register SDCR 0x00F4 000000 Serial Port D Extended Register SDER 0x00F5 W 00000000 Serial Port E Data Register SEDR 0x00C8 R W XXXXXXXX Serial Port E Address Register SEAR 0 00 9 S
135. ATURES The Rabbit 3000 is an evolutionary design The processor and instruction set are nearly identical to the immediate predecessor processor the Rabbit 2000 Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180 Compared to the Z180 the instruction set has been augmented by a sub stantial number of new instructions Some obsolete or redundant Z180 instructions have been dropped to make available efficient 1 byte opcodes for important new instructions see Chapter 20 Differences Rabbit vs Z80 Z180 Instructions The advantage of this evolutionary approach is that users familiar with the Z80 or Z180 can immediately under stand Rabbit assembly language Existing Z80 or Z180 source code can be assembled or compiled for the Rabbit with minimal changes Changing technology has made some features of the Z80 Z180 family obsolete and these features have been dropped in the Rabbit For example the Rabbit has no special support for dynamic RAM but it has extensive support for static memory This is because the price of static memory has decreased to the point that it has become the preferred choice for medium scale embedded systems The Rabbit has no support for DMA direct memory access because most of the uses for which DMA is traditionally used do not apply to embedded systems or they can be accomplished better in other ways such as fast inter rupt routines external
136. AVEATTN Figure 13 1 Rabbit Slave Port The slave port has three data registers for each direction of communication Three regis ters named SPDOR SPDIR and SPD2R can be written by the master and read by the slave Three different registers also named SPDOR SPDIR and SPD2R can be written by the slave and read by the master The same names are used for different registers since it is usually clear from the context which register is meant If it is necessary to distinguish between registers we will refer to the registers as SPDOR writable by the slave or SPDOR writable by the master User s Manual 199 A status register can be read by either the slave or the master The status register has full empty bits for each of the six registers A data register is considered full when it is written to by whichever side is capable of writing to it If the same register is then read by either side it is considered to be empty The flag for that register is thus set to a 1 when the reg ister is written to and the flag is set to a 0 when the register is read The registers appear to be internal I O registers to the slave To the master at least for a Rabbit master the registers appear to be external I O registers The figure below shows the sequence of events when the master reads writes the slave port registers Slave Port Read Cycle SCS 3222
137. Acknowledge cycles are always followed by two memory writes to push the contents of the PC onto the stack Execution then begins at the appropriate interrupt vector location User s Manual 99 Table 7 16 Control Registers for External Interrupts Reg Name Reg Address Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 IOCR 10011000 XX INTOB PE4 INTOA PEO Enb INTO 10011001 XX INTIB PES INTIA 1 Enb INTI edge triggered edge triggered interrupt 00 disabled 00 disabled 00 disable 10 rising 10 rising 01 1 01 falling 01 falling 10 pri 2 11 both 11 both 11 pri 3 7 10 2 Interrupt Vectors INTO EIR Ox00 INT1 0 08 When it is desired to expand the number of interrupts for additional peripheral devices the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou tines Each additional interrupting device will have to signal the processor that it is requesting an interrupt A separate signal line is needed for each device so that the proces sor can determine which devices are requesting an interrupt The following code shows how the interrupt service routines can be written External interrupt Routine 0 programmed priority could be 3 int2 PUSH IP IPSET 1 Save interrupt priority set to priority really desired 1 insert body of interrupt routine here r OPP IP IPRES get back entry priority restore interrupted rout
138. An interrupt is generated at the end of an Abort transmission T The transmitter finished sending a closing Flag Data written in response to this interrupt will cause at least two Flags to be transmitted between frames 0 The byte in the receiver buffer is 8 bits 0 1 The byte in the receiver buffer is less than 8 bits 172 Rabbit 3000 Microprocessor Table 12 14 Serial Port Control Register Ports and B Serial Port x Control Register SACR Address 0xC4 SBCR Address 0xD4 Bit s Value Description 7 6 00 No operation These bits are ignored in the Async mode 01 In clocked serial mode start a byte receive operation 10 In clocked serial mode start a byte transmit operation In clocked serial mode start a byte transmit operation and a byte receive 11 AUFS operation simultaneously 5 4 00 Parallel Port C is used for input 01 Parallel Port D is used for input Ix Disable the receiver input 3 2 00 Async mode with 8 bits per character Async mode with 7 bits per character In this mode the most significant bit of a 01 E byte is ignored for transmit and is always zero in receive data Clocked serial mode with external clock 10 Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port PBO Clocked serial mode with internal clock 11 Serial Port clock is on Parallel Port 1 Serial Port B clock is on Parallel Port
139. B3R 0x007B W XXXXXXXX Port E Bit 4 Register PEB4R 0x007C W XXXXXXXX Port E Bit 5 Register PEB5R 0x007D W XXXXXXXX Port E Bit 6 Register PEB6R 0 007 w XXXXXXXX Port E Bit 7 Register PEB7R 0x007F w XXXXXXXX Port F Data Register PFDR 0x0038 R W XXXXXXXX Port F Control Register PFCR 0x003C w xx00xx00 Port F Function Register PFFR 0x003D w XXXXXXXX Port F Drive Control Register PFDCR 0x003E W XXXXXXXX Port F Data Direction Register PFDDR 0x003F W 00000000 Port G Data Register PGDR 0x0048 R W XXXXXXXX Port G Control Register PGCR 0x004C W xx00xx00 Port G Function Register PGFR 0x004D W XXXXXXXX Port G Drive Control Register PGDCR 0x004E W XXXXXXXX Port G Data Direction Register PGDDR 0x004F W 00000000 I O Bank 0 Control Register IBOCR 0x0080 W 00000000 I O Bank 1 Control Register IBICR 0x0081 W 00000000 330 Rabbit 3000 Microprocessor Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset I O Bank 2 Control Register IB2CR 0x0082 W 00000000 I O Bank 3 Control Register IB3CR 0x0083 W 00000000 I O Bank 4 Control Register IB4CR 0x0084 W 00000000 I O Bank 5 Control Register IB5CR 0x0085 W 00000000 I O Bank 6 Control Register IB6CR 0x0086 W 00000000 I O Bank 7 Control Register IB7CR 0x0087 W 00000000 PWM LSB 0 Register PWLOR 0x0088 W 00 PWM MSB 0 Register PWM
140. CFR Parallel Port C Function Register identify whether the data register or the serial port transmit lines were driving the pins Table 9 5 Parallel Port C Registers Register Name Mnemonic I O address R W Reset Port C Data Register PCDR 0x50 R W xOx1x1x1 Port C Function Register PCFR 0x55 W x0x0x0x0 Table 9 6 Parallel Port C Register Bit Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCDR r Echo Echo Echo Echo adr 0x050 PC7 in drive PC5 in PC3 in drive PCl in drive PCDR COR PC6 x PCA x PC2 x PCO adr 0x050 PCFR w Drive 2 Drive Drive Drive adr 0x055 TXA TXC TXD Parallel Port C shares its pins with serial ports A D The parallel port inputs can be config ured as serial port inputs while the dedicated outputs as serial port outputs When serving as serial inputs the data lines can still be read from the Parallel Port C data register The parallel port outputs can be selected to be serial port outputs by setting the corresponding bit positions in the Port C Function register PCFR When a parallel port output pin is selected to be a serial port output the value stored in the data register is ignored On reset the active even numbered function register bits are zeroed resulting in Port C to behave as an I O port Bit 6 of the Port C data register is zeroed while the remaining even numbered bits are set to 1
141. DB4R W x x x PD4 x x x x adr 0x06C PDBSR W x x PD5 x x x x x adr 0x06D PDB6R W x PD6 x x x x x x adr 0 06 PDB7R W PD7 x x x x x x x adr 0 06 Table 9 9 Parallel Port D Control Register adr 0x064 Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 00 clock lower nibble on pclk 2 01 clock on timer Al 01 clock on timer Al nt 10 clock on timer B1 M 10 clock on timer B1 11 clock on timer B2 11 clock on timer B2 User s Manual 135 The following registers are described in Table 9 8 and in Table 9 9 e PDDR Parallel Port D data register Read Write e PDDDR Parallel Port D data direction register 1 makes the corresponding pin output Write only e PDDCR Parallel Port D drive control register A 0 makes the corresponding pin regular output A 1 makes the corresponding pin an open drain output Write only e PDFR Parallel Port D function control register This port may be used to make port positions 4 and 6 be serial port outputs Write only e PDBxR These eight registers may be used to set outputs on individual port positions e PDCR Parallel Port D control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero 136 Rabbit 3000 Microprocessor 9 5 Parallel Por
142. E six clocks EX DE HL 2 clocks EX DE HL 2 clocks EX DE HL 2 clocks 6 total BC lt gt BC 12 clocks EX DE HL 2 clocks EX DE HL 4 EX DE HL 2 EXX 2 EX DE HL 3222 Move between IX IY and DE DE IX TY gt DE DE gt IX TY IX IX gt DE EX DE HL LD HL IX IY LD IX IY HL EX DE HL 8 clocks total DE IX IY EX DE HL LD IX IY HL EX DE HL 8 clocks total 3 4 3 Manipulation of Boolean Variables Logical operations involving HL when HL is a logical variable with a value of 1 or 0 this is important for the C language where the least bit of a 16 bit integer is used to repre sent a logical result Logical not operator invert bit 0 of HL in four clocks also works for IX IY in eight clocks DEC HL 1 goes to zero zero goes to 1 BOOL HL 1 to 1 zero to zero 4 clocks total Logical xor operator xor HL DE when HL DE are 1 or 0 ADD HL DE RES 1 1 6 clocks total clear bit 1 result of if 1 1 2 40 Rabbit 3000 Microprocessor 3 4 4 Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation The zero flag is set if the numbers are equal With the sBc instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from 8 bit unsigned integers span the range 0 255 16 bit unsigned integers span the range 0 65535 OR a Clear carry SBC HL DE HL A and DE
143. EG DATASEG 00 Extended code 44 XPC segment 8K Stack segment 4K typ 7 ba segment Root segment 16 bit address 20 bit address Figure 8 4 Memory Segments The memory management unit accepts a 16 bit address from the processor and translates it into a 20 bit address The procedure to do this works as follows It is determined which segment the 16 bit address belongs to by inspecting the upper 4 bits of the address Every address must belong to one of the possible 4 segments 2 Each segment has an 8 bit segment register The 8 bit segment register is added to the upper 4 bits of the 16 bit address to create a 20 bit address Wraparound occurs if the addition would result in an address that does not fit in 20 bits Table 8 1 Segment Registers Segment Register Function XPC Locates extended code segment in physical memory Read and written by processor instructions 14 a xpc ld xpc a 1 11 lret 11 STACKSEG 0x11 Locates stack segment in physical memory DATASEG 0x12 Locates data segment in physical memory Table 8 2 Segment Size Register Bits 7 4 Bits 3 0 SEGSIZE 0x13 Boundary address stack segment Boundary address data segment 118 Rabbit 3000 Microprocessor 8 4 Memory Interface Unit The 20 bit memory addresses generated by the memory mapping
144. HL 7 IX d IX d 6 0 0 IX d 7 IY d I d 6 01 0 CY IY d 7 User s Manual 255 SLA r 4 fr L x r 6 0 0 CY r 7 SRA HL 10 f b L HL HL 7 HL 7 1 HL 0 SRA IX d 13 f b L IX d IX d 7 IX d 7 1 CY IX d 0 SRA IY d 13 f b L IY d 7 7 11 CY IY d 0 SRA r 4 fr L r 7 r 7 1 CY r 0 SRL HL 10 f b L HL 0 HL 7 1 CY HL 0 SRL IX d 13 f b L IX d 0 zX d 7 1 CY IX d 0 SRL IY4d 13 f b L 0 rY d 7 11 IY d 0 SRL r 4 fr L xr 0 r 7 1 cy r 0 19 15 Instruction Prefixes Instruction A 6 2 Operation ALTD 2 alternate register destinatIn for next Instruction IOE 2 I O external prefix 2 I O internal prefix 19 16 Block Move Instructions Instruction clk 6 2 Operation LDD 10 d DE HL BC BC 1 DE DE 1 HL HL 1 LDDR 6 7i d if BC 0 repeat LDI 10 d DE HL BC BC 1 DE 1 HL HL 1 LDIR 647i d if BC 0 repeat If any of the block move instructions are prefixed by an I O prefix the destination will be in the specified I O space Add 1 clock for each iteration for the prefix if the prefix is IOI internal I O If the prefix is IOE add 2 clocks plus the number of I O wait states enabled
145. HL d L HL d 1 H L HL d H HL d 1 SP n L SP n 1 H SP n IXL SP n 1 SP n IYL SP n 1 L SP n H SP n 1 IXL SP n IXH SP n 1 IYL SP n SP n 1 IX d L IX d 1 H L IX d IX d 1 L IY d 1 H IY d 1 IXH IYH 250 Rabbit 3000 Microprocessor B C D E H L A 19 5 16 bit Load and Store 20 bit Address Instruction LDP HL HL LDP IX HL LDP IY HL LDP HL HL LDP HL IX LDP HL IY LDP mn HL LDP mn IX LDP mn IY LDP HL mn LDP IX mn LDP IY mn clk 12 12 12 10 10 10 15 15 15 13 13 13 A I s V Operation HL L HL 1 H Adr 19 16 3 0 IX L IX 1 H Adr 19 16 3 0 L IY 1 H Adr 19 16 3 0 L HL H HL 1 Adr 19 16 3 0 L IX H IX 1 Adr 19 16 3 0 L IY H IY 1 Adr 19 16 3 0 mn L mn 1 H Adr 19 16 3 0 mn IXL mn 1 IXH Adr 19 16 3 0 mn IYL mn 1 Adr 19 16 3 0 L mn mn41 Adr 19 16 3 0 IXL mn IXH mn 1 Adr 19 16 3 0 IYL mn mn 1 Adr 19 16 A 3 0 Note that the LDP instructions wrap around on a 64K page boundary Since the LDP instruc tion operates on two byte values the second byte will wrap around and be
146. In order to translate between 5 V and 3 3 V HCT family parts powered from 5 V can be used and are often the best solution There is also the LVT family of parts that operate from 2 0 V to 3 3 V but that have 5 V tolerant inputs and are available from many suppli ers True level translating parts are available with separate 3 3 V and 5 V supply pins but these parts are not usually needed and have design traps involving power sequencing Many charge pump chips that perform DC to DC voltage conversion at low cost have been introduced in recent years These are convenient for systems with dual voltage requirements 2 2 2 Serial Ports There are six serial ports designated ports A B C D E and F All six serial ports can operate in an asynchronous mode up to a baud rate equal to the system clock divided by 8 The asynchronous ports use 7 bit or 8 bit data formats with or without parity A 9th bit address scheme where an additional bit is set or cleared to mark the first byte of a mes sage is also supported The serial port software driver can tell when the last byte of a message has finished trans mitting from the output shift register correcting an important defect of the Z180 This is User s Manual 11 important for RS 485 communication because a half duplex line driver cannot have the direction of transmission reversed until the last data bit has been sent In many UARTS including those on the Z180 it is difficult to generate an
147. Input Output 77777777 77777777 7 0 Input Output 77777777 77777777 7 0 Input Output 77777777 77272727 PG 7 0 Input Output 722772272 72272727 A low is recognized internally by the processor after a reset T The default state of the I O ports after the completion of the reset and initializa tion sequences 96 Rabbit 3000 Microprocessor 7 10 Rabbit Interrupt Structure An interrupt causes a call to be executed pushing the PC on the stack and starting to exe cute code at the interrupt vector address The interrupt vector addresses have a fixed lower byte value for all interrupts The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively There are only two external interrupts generated by transitions on certain pins in Parallel Port E The interrupt vectors are shown in Table 6 2 The interrupts differ from most Z80 or Z180 interrupts in that the 256 byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16 bit pointer to the routine The interrupt vectors are spaced 16 bytes apart so that the entire code will fit in the table for very small interrupt routines Interrupts have priority 1 2 or 3 The processor operates at priority 0 1 2 or 3 If an inter rupt is being requested and its priority is higher than the priority of the processor the interrupt will take place after the
148. LKE ARXE yes PG4 TCLKE TCLKE ARCLKE PG3 APWM0 RXF PG2 TXF PG1 RCLKF ARXF PG0 TCLKF TCLKF ARCLKF Introduced with Rabbit 3000A chip 66 Rabbit 3000 Microprocessor The alternate output functions identified in Table 5 2 are configured by setting the appro priate bits in the Paralle Port x Function Register Table 5 3 Parallel Port x Alternate Functions Parallel Port x Function Register PCFR Address 0x0055 PDFR Address 0x0065 PEFR Address 0x0075 PFFR Address 0x003D PGFR Address 0x004D Bit s Value Description 0 The corresponding port bit functions normally The corresponding port bit carries its alternate signal as an output See Table 5 4 7 0 1 below Only the bits that have alternate functions listed in Table 5 4 actually have a control bit in these registers That is there are four in Port C four in Port D eight in Port E four in Port F and eight in Port G Table 5 4 Parallel Port x Alternate Functions Control Bits Alternate Output Function Bit Port B Port C Port D Port E Port F Port G 7 SLAVEATTN IA5 APWM3 I7 PWM3 APWMI 6 16 PWM2 TXE 5 IA3 APWM2 I5 PWMI RCLKE 4 IA2 TXB ATXB I4 PWMO TCLKE 3 APWMO 2 IAO TXC D TXF 1 CLKA RCLKF 0 CLKB TXD 10 CLKD TCLKF User s Manual 67 5 6 DC Characteristics Table 5 5 Rabbit 3000 Absolute Maxim
149. MHz The static part of the current is computed using 3 5 x chip select duty cycle The dynamic part is computed using 0 5 x f in mA where f is the bus speed in MHz At 0 46 MHz 3 68 MHZ 8 and using a short chip select the duty cycle is about 10 giving a static current of about 0 35 mA The dynamic current is 0 25 mA for a total cur rent of 0 6 mA Added to the approximately 2 5 mA operating current gives a total current of 3 1 mA at 0 46 MHz In sleepy mode with a self timed chip select of 106 ns and a clock speed of 32 kHz the duty cycle will be 0 106 66 1 600 and the static current will be 3 5 600 6 u A If the clock is divided down by a factor of 2 then the static current is reduced to 3 HA The dynamic current will be 16 uA at 32 kHz 1000x0 5xf and 8 uA at 16 kHz 234 Rabbit 3000 Microprocessor 16 9 Battery Backed Clock Current Consumption When using the suggested tiny logic oscillator the oscillator and clock consume current as shown in Figure 16 12 below Normally a resistor is placed in the battery circuit to limit the current to about 3 u A which results in a voltage setpoint of about 1 7 V When operat ing at 3 3 V in sleepy mode the current of the oscillator and the real time clock about 12 uA must be added Using the suggested tiny logic oscillator circuit the external 32 768 kHz oscillator con sumes the following current in uA where V is the operating voltage Iose HA 0 35 x V 0 31 x V
150. OLNI bad LI Figure 5 1 Package Outline Pin Rabbit 3000 Microprocessor 56 5 1 2 Mechanical Dimensions and Land Pattern Figure 5 2 shows the mechanical dimensions of the Rabbit 3000 LQFP package 16 00 0 25 mm 14 00 0 10 mm 14 00 0 10 mm 16 00 0 25 mm 64 lt 0 18 0 05 mm 1 40 0 05 mm 21 Y 0 40 0 10 0 05 The same dimensions apply along the x axis and the y axis 0 10 mm lt 0 60 _ 0 15 Figure 5 2 Mechanical Dimensions Rabbit LQFP Package User s Manual 57 Figure 5 3 shows the PC board land pattern for the Rabbit 3000 chip in a 128 pin LQFP package This land pattern is based on the IPC SM 782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pat tern Standard IPC Northbrook IL 1999 16 85 mm max 13 75 mm min 13 75 mm min 16 85 mm max 0 28 mm max gt 12 4 mm 1 55 mm Y 12 4 mm 15 3 mm
151. PC serial port to the Rabbit based target system or by performing software development and debugging over a network or the Internet using interfaces and tools provided by Rabbit Semiconductor User s Manual 1 1 Features and Specifications Rabbit 3000 128 pin LQFP package Operating voltage 1 8 V to 3 6 V Clock speed to 54 MHz All specifications are given for both industrial and commercial temperature and voltage ranges Rabbit microprocessors are low cost Industrial specifications are for 3 3 V 10 and a temperature range from 40 C to 85 C Modified commercial specifications are for a voltage variation of 5 and a temperature range from 40 C to 70 C l megabvte code data space allows C programs with 50 000 lines of code The extended Z80 style instruction set is C friendly with short and fast opcodes for the most important C operations Four levels of interrupt priority make a fast interrupt response practical for critical applications The maximum time to the first instruction of an interrupt routine is about 0 5 us at a clock speed of 50 MHz Access to I O devices is accomplished by using memory access instructions with an I O prefix Access to I O devices is thus faster and easier compared to processors with a distinct and narrow I O instruction set As an option the auxiliary I O bus can be enabled to use separate pins for address and data allowing the I O bus to have a greater physical extent with less EMI and less confl
152. R 0x000C W 11111111 RAM Segment Register RAMSR 0x0448 W 00000000 Write Protect Control Register WPCR 0x0440 W 00000000 Stack Limit Control Register STKCR 0x0444 W 00000000 Stack Low Limit Register STKLLR 0x0445 W XXXXXXXX Stack High Limit Register STKHLR 0x0446 W XXXXXXXX Write Protect Low Register WPLR 0x0460 W 00000000 Write Protect High Register WPHR 0x0461 W 00000000 Write Protect Segment Register WPSAR 0x0480 W 00000000 Write Protect Segment A Low Register WPSALR 0x0481 W 00000000 Write Protect Segment A High Register WPSAHR 0x0482 W 00000000 Write Protect Segment B Register WPSBR 0x0484 W 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Parallel Port A User Enable Register PAUER 0x0330 W 00000000 Parallel Port B User Enable Register PBUER 0x0340 W 00000000 Parallel Port C User Enable Register PCUER 0x0350 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x0370 W 00000000 Parallel Port F User Enable Register PFUER 0x0338 W 00000000 Parallel Port G User Enable Register PGUER 0x0348 W 00000000 Input Capture User Enable Register ICUER 0x0358 W 00000000 I O Bank User Enable Register IBUER 0x0380 W 00000000 PWM User Enable Register PWUER
153. ROCESSOR FEATURES 3 1 Processor Registers The Rabbit s registers are nearly identical to those of the 7180 or the Z80 The figure below shows the register layout The XPC and IP registers are new The EIR register is the same as the 780 I register and is used to point to a table of interrupt vectors for the exter nally generated interrupts The IIR register occupies the same logical position in the instruction set as the Z80 R register but its function is to point to an interrupt vector table for internally generated interrupts 8 16 bit registers XPC A 8 bit accumulator F flags register HL 16 bit accumulator IX IY Index registers alt accum s Alternate Registers SP stack pointer PC program counter 512 extension of program counter F flag register layout IIR internal interrupt register S sign Z zero V overflow C carry EIR external interrupt register Bits marked x are read write IP interrupt priority register Figure 3 1 Rabbit Registers User s Manual 21 The Rabbit and the Z80 Z180 processor has two accumulators the A register serves as an 8 bit accumulator for 8 bit operations such as ADD or AND The 16 bit register HL regis ter serves as an accumulator for 16 bit operations such as ADD HL DE which adds
154. RRD RLD CPI CPIR CPD CPDR Most of these op codes deal with I O devices and thus do not represent transportable code The only opcodes that are not processor I O related are SP DAA RRD RLD CPI CPIR CPD and CPDR MLT SP is not a practical op code The codes that are concerned with decimal arithmetic DAA RRD and RLD could be simulated but the simulation is very inefficient The bit in the status register used for half carry is available and can be set and cleared using the PUSH AF and POP AF instructions to gain access Usually code that uses these instructions should be rewritten The instructions CPI CPIR CPD and CPDR are repeating compare instructions These instructions are not very useful because the scan stops when equal compare is detected Unequal compare would be more useful They are difficult to simulate efficiently so it is suggested that code using these instructions be rewritten which in most cases should be quite easy The following op codes are dropped RST 0 RST 8 RST 0x30 The remaining RST instructions are kept but the interrupt vector is relocated to a variable location the base of which is established by the EIR register RST can be simulated by a call instruction but this is not done automatically by the assembler since most of these instructions are used for debugging by Dynamic C The following instruction has had its op code changed EX SP HL old opcode 0 0 3 opcode OxOED 0
155. RST interrupts Since interrupt routines do not affect the XPC interrupt routines must be located in the root code space However they can jump to the extended code space after saving the XPC on the stack 3 5 1 Interrupt Priority The Z80 and Z180 have two levels of interrupt priority maskable and nonmaskable The nonmaskable interrupt cannot be disabled and has a fixed interrupt service routine address of 0x66 The Rabbit in contrast has three levels of interrupt priority and four priority lev els at which the processor can operate If an interrupt is requested and the priority of the interrupt is higher than that of the processor the interrupt will take place after the execu tion of the current instruction is complete except for privileged instructions Multiple interrupt priorities have been established to make it feasible for the embedded systems programmer to have extremely fast interrupts available Interrupt latency refers to the time required for an interrupt to take place after it has been requested Generally inter rupts of the same priority are disabled when an interrupt service routine is entered Some times interrupts must stay disabled until the interrupt service routine is completed other times the interrupts can be re enabled once the interrupt service routine has at least dis abled its own cause of interrupt In any case if several interrupt routines are operating at 44 Rabbit 3000 Microprocessor the same prio
156. Register Ports Serial Port x Address Register SAAR Address 0xC1 SBAR Address 0xD1 SCAR Address 0xE1 SDAR Address 0xF1 SEAR Address 0xC9 SFAR Address 0xD9 Bit s Value Description Returns the contents of the receive buffer In Clocked Serial mode reading the data from this register automatically causes the receiver to start a byte receive Read SP ERU operation the current contents of the receive buffer are read first eliminating the need for software to issue the Start Receive command 7 0 Loads the transmit buffer with an address byte marked with a zero address bit for transmission In HDLC mode the last byte of a frame must be written to this register to enable subsequent CRC and closing Flag transmission In Clocked Write Serial mode writing the data to this register causes the transmitter to start byte transmit operation eliminating the need for the software to issue the Start Transmit command 168 Rabbit 3000 Microprocessor Table 12 10 Long Stop Register Ports Serial Port x Long Stop Register SALR Address 0xC2 SBLR Address 0xD2 SCLR Address 0xE2 SDLR Address 0xF2 SELR Address 0xCA SFLR Address 0xDA Bit s Value Description Read Returns the contents of the receive buffer 7 0 Write Loads the transmit buffer with an address byte marked with a one address bit for transm
157. Register Mnemonic Internal External Address Address Slave Port Data 0 Register SPDOR 0x20 0 Slave Port Data 1 Register SPDIR 0x21 1 Slave Port Data 2 Register SPD2R 0x22 2 Slave Port Status Register SPSR 0x23 3 Slave Port Control Register SPCR 0x24 N A 204 Rabbit 3000 Microprocessor If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register the user should be aware that all the bits might not change at the exact same time when the result changes and a transitional value could be read from the register where some bits have changed to the new value and others have not To avoid being confused by a transitional value the user can read the register twice and make sure both values are the same before accepting the value or the user can test only one bit for a change The transitional value can only exist for one read of the register and each bit will have its old value change to the new value at some point without wavering back and forth The existence of a transitional value could be very rare and has the potential to create a bug that happens often enough to be serious but so infrequently as to be difficult to diagnose Thus the user is cautioned to avoid this situa tion Table 13 2 describes the slave port control register Table 13 2 Slave Port Control Register SPCR adr 0x024 Bit 7 Bits 6 5 Bit 4 Bit 3
158. SEER 0xCD W 00000000 Serial Port F Data Register SFDR OxD8 R W XXXXXXXX Serial Port F Address Register SFAR OxD9 R W XXXXXXXX Serial Port F Long Stop Register SFLR OxDA R W XXXXXXXX Serial Port F Status Register SFSR 0xDB R 0xx00000 Serial Port F Control Register SFCR 0xDC W xx000000 Serial Port F Extended Register SFER OxDD W 00000000 Watchdog Timer Control Register WDTCR 0x08 W 00000000 Watchdog Timer Test Register WDTTR 0x09 W 00000000 78 Rabbit 3000 Microprocessor 7 MISCELLANEOUS FUNCTIONS 7 1 Processor Identification Four read only registers are provided to allow software to identify the Rabbit micropro cessor and recognize the features and capabilities of the chip Five bits in each of these registers are unique to each version of the chip One register is reserved for the on chip flash memory configuration GROM one register is reserved for the on chip RAM mem ory configuration GRAM one register identifies the CPU GCPU and the final register is reserved for revision identification GREV The Rabbit 3000 does not contain on chip SRAM or flash memories Table 7 1 Global ROM Configuration Register Global ROM Configuration Register GROM Address 0x2C Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 ROM identifier for this version of t
159. Serial Port B Data Register SBDR 0xD0 R W XXXXXXXX Serial Port B Address Register SBAR OxD1 R W XXXXXXXX Serial Port B Long Stop Register SBLR 0xD2 R W XXXXXXXX Serial Port B Status Register SBSR 0xD3 R 0xx00000 Serial Port B Control Register SBCR 0xD4 w xx000000 Serial Port B Extended Register SBER 0xD5 w 00000000 Serial Port C Data Register SCDR OxEO R W XXXXXXXX Serial Port C Address Register SCAR 0 1 R W XXXXXXXX Serial Port C Long Stop Register SCLR OxE2 R W XXXXXXXX Serial Port C Status Register SCSR OxE3 R 0xx00000 Serial Port C Control Register SCCR OxE4 W xx000000 Serial Port C Extended Register SCER 0 5 00000000 Serial Port D Data Register SDDR OxFO R W XXXXXXXX User s Manual 77 Table 6 2 Rabbit Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Serial Port D Address Register SDAR OxF1 R W XXXXXXXX Serial Port D Long Stop Register SDLR OxF2 R W XXXXXXXX Serial Port D Status Register SDSR OxF3 R 0xx00000 Serial Port D Control Register SDCR OxF4 W xx000000 Serial Port D Extended Register SDER OxF5 W 00000000 Serial Port E Data Register SEDR 0xC8 R W XXXXXXXX Serial Port E Address Register SEAR 0xC9 R W XXXXXXXX Serial Port E Long Stop Register SELR OxCA R W XXXXXXXX Serial Port E Status Register SESR OxCB R 0xx00000 Serial Port E Control Register SECR 0 000000 Serial Port E Extended Register
160. Shadow Global Control Status Register char GOCRShadow Global Output Control Register char GCDRShadow Global Clock Doubler Register If the port is a write only port the shadow register can be used to find out the port s con tents For example GCSR has a number of write only bits These can be read by consult ing the shadow provided that the shadow register is always updated when writing to the register k GCSRShadow 18 3 1 Updating Shadow Registers If the address of a shadow register is passed as an argument to one of the functions that write to the internal or external I O registers then the shadow register will be updated as well as the specified I O register A NULL pointer may replace the pointer to a shadow register as an argument to WrPortI and WrPortE the shadow register associated with the port will not be updated A pointer to the shadow register is mandatory for BitWrPortI and BitWrPortE 18 3 2 Interrupt While Updating Registers When manipulating I O registers and shadow registers the programmer must keep in mind that an interrupt can take place in the middle of the sequence of operations and then the interrupt routine may manipulate the same registers If this possibility exists then a solution must be crafted for the particular situation Usually it is not necessary to disable the interrupts while manipulating registers and their associated shadow registers 18 3 2 1 Atomic Instruction As an e
161. Stop condition has not occurred read 1 The Input Capture 1 Stop condition has occurred 4 0 The corresponding Input Capture 1 Stop interrupt is disabled write 1 The corresponding Input Capture 1 Stop interrupt is enabled 3 0 The Input Capture 2 counter has not rolled over to all zeros read 1 The Input Capture 2 counter has rolled over to all zeros 3 0 No effect on Input Capture 2 counter This bit always reads as zero write 1 Reset Input Capture 2 counter to all zeros and clears the rollover latch 2 0 The Input Capture 1 counter has not rolled over to all zeros read 1 The Input Capture 1 counter has rolled over to all zeros 2 0 No effect on Input Capture 1 counter This bit always reads as zero Write 1 Reset Input Capture 1 counter to all zeros and clears the rollover latch 1 0 0 Normal Input Capture operation 0 Normal Input Capture operation T Reserved for test The Input Capture counter increments at both bit 0 and bit 8 There is no carry from lower byte to higher byte User s Manual 107 Table 7 20 Input Capture Control Register Input Capture Control Register ICCR Address 0x57 Bit s Value Description 7 2 These bits ignored 1 0 00 Input Capture interrupts are disabled 01 Input Capture interrupt use Interrupt Priority 1 10 Input Capture interrupt use Interrupt Priority 2 11 Input Capture interrupt use Interrupt Priority 3 Table 7 21 Input Capture
162. T 11211141 1 No appears before it always does LD E E RDMODE 2 4 1 1 1 15 50 0 Yes 318 Rabbit 3000 C 2 System User Mode Registers Table C 3 lists the new I O registers added to support the System User mode The Enable Dual Mode Register EDMR is used to enable and disable the System User mode All other I O registers listed in the table are User mode enable registers for each peripheral On startup User mode access is not allowed to all the peripherals all writes to I O registers for that peripheral are ignored but can be enabled by writing to the appropri ate register Note that User mode writes to all other I O registers are always ignored Table C 3 System User Mode I O Registers Register Name Mnemonic A E R W Reset Enable Dual Mode Register EDMR 0x0420 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Parallel Port A User Enable Register PAUER 0x0330 W 00000000 Parallel Port B User Enable Register PBUER 0x0340 W 00000000 Parallel Port C User Enable Register PCUER 0x0350 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x0370 W 00000000 Parallel Port F User Enable Register PFUER 0x0338 W
163. These inputs and outputs are also used for access to other peripherals on the chip As out puts the Parallel Port F outputs can carry the four Pulse Width Modulator outputs As inputs Parallel Port F inputs can carry the inputs to the quadrature decoders When Serial Port C or Serial Port D is used in the clocked serial mode two pins of Parallel Port F are used to carry the serial clock signals When the internal clock is selected in these serial ports the corresponding bit of Parallel Port F is set as an output The Parallel Port F registers and their functions are described in Table 9 14 and in Table 9 15 Table 9 13 Parallel Port F Registers Register Name Mnemonic I O address R W Reset Port F Data Register PFDR 0x38 R W XXXXXXXX Port F Control Register PFCR 0x3C W xx00xx00 Port F Function Register PFFR 0x3D W XXXXXXXX Port F Drive Control Register PFDCR 0 3 Port F Data Direction Register PFDDR 0x3F w 00000000 Table 9 14 Parallel Port F Register Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REDE PF7 PF6 PF5 PF4 PF3 PF2 1 PF0 adr 0x038 PFFR W adr 0x03D pwm 3 pwm 2 1 pwm 0 x x sclk_c sclk d PFDCR W out out out out out out out out dr 0x03E open open open open open open open open 2 drain drain drain drain drain drain drain drain PFDDR W dir dir dir dir dir dir dir dir adr OxO3F o
164. WLOR 0x88 W XXXXXXXX User s Manual 75 Table 6 2 Rabbit Internal l O Registers continued Register Name Mnemonic I O Address R W Reset PWM MSB 0 Register PWMOR 0x89 W XXXXXXXX PWM LSB 1 Register PWLIR Ox8A w XXXXXXXX PWM MSB 1 Register PWMIR Ox8B W XXXXXXXX PWM LSB 2 Register PWL2R Ox8C W XXXXXXXX PWM MSB 2 Register PWM2R 0 8 PWM LSB 3 Register PWL3R Ox8E W XXXXXXXX PWM MSB 3 Register PWM3R Ox8F W XXXXXXXX Quad Decode Ctrl Status Register QDCSR 0x90 R W XXXXXXXX Quad Decode Control Register QDCR 0x91 w 00xx0000 Quad Decode Count 1 Register QDCIR 0x94 R XXXXXXXX Quad Decode Count 2 Register QDC2R 0x96 R XXXXXXXX Interrupt 0 Control Register IOCR 0x98 W xx000000 Interrupt 1 Control Register 0 99 w xx000000 Real Time Clock Control Register RTCCR 0x01 W 00000000 Real Time Clock Byte 0 Register RTCOR 0x02 R W XXXXXXXX Real Time Clock Byte 1 Register RTCIR 0x03 R XXXXXXXX Real Time Clock Byte 2 Register RTC2R 0x04 R XXXXXXXX Real Time Clock Byte 3 Register RTC3R 0x05 R XXXXXXXX Real Time Clock Byte 4 Register RTC4R 0x06 R XXXXXXXX Real Time Clock Byte 5 Register RTCSR 0x07 R XXXXXXXX Timer A Control Status Register TACSR 0 R W 00000000 Timer A Prescale Register TAPR OxA1 w XXXXXXX Timer A Time Constant 1 Register TATIR 0 Timer A Control Register TACR OxA4 W 0000
165. X Port D Bit 1 Register PDBIR 0x69 W XXXXXXXX Port D Bit 2 Register PDB2R 0 6 Port D 3 Register PDB3R 0x6B w XXXXXXXX Port D Bit 4 Register PDB4R 0x6C Port D Bit 5 Register PDB5R 0x6D w XXXXXXXX Port D Bit 6 Register PDB6R 0x6E w XXXXXXXX Port D Bit 7 Register PDB7R Ox6F w XXXXXXXX User s Manual 133 PAN PI inputs 2 f Ti Al Driver optional open drain Timer 1 Timer B2 perclk 2 _ Timer A1 Timer B1 Timer B2 Figure 9 1 Parallel Port D Block Diagram 134 Rabbit 3000 Microprocessor Table 9 8 Parallel Port D Register functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDIS PD7 PD6 PD5 PD4 PD3 PD2 PDI PDO adr 0x060 PDDCR W out out out out out out out out adr 0x066 open open open open open open open open drain drain drain drain drain drain drain drain PDFR W adr 0x065 x alt TXA x alt TXB x x x x PDDDR W dir dir dir dir dir dir dir dir adr 0x067 out out out out out out out out PDBOR W x x x x x x x PD0 adr 0x068 PDBIR W x x x x x x PDI x adr 0x069 PDB2R W x x x x x PD2 x x adr 0 06A PDB3R W X x x x PD3 x x x 0 06 P
166. XXXXX Port F Data Register PFDR 0x38 R W XXXXXXXX Port F Control Register PFCR 0 3 00 00 Port F Function Register PFFR 0x3D w XXXXXXXX Port F Drive Control Register PFDCR 0x3E W XXXXXXXX Port F Data Direction Register PFDDR Ox3F W 00000000 Port G Data Register PGDR 0x48 R W XXXXXXXX Port G Control Register PGCR 0 4 xx00xx00 Port G Function Register PGFR 0x4D w XXXXXXXX Port G Drive Control Register PGDCR Ox4E W XXXXXXXX Port G Data Direction Register PGDDR Ox4F W 00000000 Input Capture Ctrl Status Register ICCSR 0x56 R W 00000000 Input Capture Control Register ICCR 0x57 W 00 Input Capture Trigger 1 Register ICTIR 0x58 w 00000000 Input Capture Source 1 Register ICSIR 0x59 w XXXXXXXX Input Capture LSB 1 Register ICLIR 0 5 R XXXXXXXX Input Capture MSB 1 Register ICMIR 0 58 R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0x5C W 00000000 Input Capture Source 2 Register ICS2R 0 5 W XXXXXXXX Input Capture LSB 2 Register ICL2R 0 5 R XXXXXXXX Input Capture MSB 2 Register ICM2R Ox5F R XXXXXXXX I O Bank 0 Control Register IBOCR 0x80 W 000000xx I O Bank 1 Control Register IBICR 0x81 W 000000xx I O Bank 2 Control Register IB2CR 0x82 W 000000xx I O Bank 3 Control Register IB3CR 0x83 W 000000xx I O Bank 4 Control Register IB4CR 0x84 W 000000xx I O Bank 5 Control Register 5 0 85 w 000000xx I O Bank 6 Control Register IB6CR 0x86 W 000000xx I O Bank 7 Control Register IB7CR 0x87 W 000000xx PWM LSB 0 Register P
167. XXXXXX Port E Bit 7 Register PEB7R Ox7F W XXXXXXXX The following registers are described in Table 9 11 and in Table 9 12 PEDR Port E data register Reads value at pins Writes to port E preload register PEDDR Port E data direction register Set to 1 to make corresponding pin an out put This register is zeroed on reset PEFR Port E function register Set bit to 1 to make corresponding output an I O strobe The nature of the I O strobe is controlled by the I O bank control registers IBxCR The data direction must be set to output for the I O strobe to work PEBxR These are individual registers to set individual output bits on or off PECR Parallel Port E control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero On reset the data direction register and function register are zeroed making all pins inputs and disabling the alternate output functions In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with Port E are not initialized on reset 138 Rabbit 3000 Microprocessor Table 9 11 Parallel Port E Register functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDR R W PE7 PE6 PES PE4 PE3 PE2 1
168. able Dual Mode Register EDMR is set to one two operating modes System and User become available The System mode is just like the normal operating mode but the User mode restricts program access to the hardware and to the System mode Individ ual peripherals may be enabled for User mode access in the User Enable registers listed below When enabled for User mode access a peripheral interrupt if it is capable of gen erating an interrupt can only be requested at interrupt priority level 2 or 1 and it is assumed that the interrupt service routine will be executed by User mode code Note that the processor automatically enters the System mode when entering the ISR area in response to an interrupt and the User mode must be specifically entered before continuing with the interrupt service routine The System User mode is discussed in great detail in Appendix C User s Manual 283 B 1 5 Memory Protection The ability to inhibit writes to physical memory was added The sixteen 64 KB physical memory blocks can be individually protected and two of those blocks can additionally be subdivided and protected at a granularity of 4 KB When a write is attempted a new Priority 3 write protection interrupt request is generated The write protection can be enabled for the User mode only or for all modes see Appendix C for more information WPHR 0x85 WPSAR 0x04 WPLR 0x6C WPSAHR 0x07 OxFFFFF WPSALR 0 Ox4FFFF
169. ad the data from the SEDR or SEAR Serial Port E Tx Write data to the SEDR SEAR SELR or write a dummy byte to the SESR Rx Read the data from the SFDR or SFAR Serial Port F Tx Write data to the SFDR SFAR SFLR or write a dummy byte to the SFSR Rx Read the data from the SADR or SAAR Serial Port A Tx Write data to the SADR SAAR SALR or write a dummy byte to the SASR Rx Read the data from the SBDR or SBAR Serial Port B Tx Write data to the SBDR SBAR SBLR or write a dummy byte to the SBSR Rx Read the data from the SCDR or SCAR Serial Port C Tx Write data to the SCDR SCAR SCLR or write a dummy byte to the SCSR Rx Read the data from the SDDR or SDAR Lowest Serial Port D Tx Write date to the SDDR SDAR SDLR or write a dummy byte to the SDSR In the case of the external interrupts the only action that will clear the interrupt request is for the interrupt to take place which automatically clears the request A special action must be taken in the interrupt service routine for the other interrupts 98 Rabbit 3000 Microprocessor 7 10 1 External Interrupts There are two external interrupts Each interrupt has 2 input pins that can be used to trig ger the interrupt The inputs have a pulse catcher that can detect rising falling or either ris ing or falling edges INTIA PE1 pulse euet 2 l INTIB PES pulse catcher 1 interrupt acknowledge INTOA
170. akes place in conjunction with the external interrupt line The interrupt line can be programmed to interrupt on either rising falling or both edges To capture the time of the edge the interrupt routine can read the Timer B counter The execution time of the interrupt routine up to the point where the timer is read can be subtracted from the timer value If no other interrupt is of the same or higher priority then the uncertainty in the position of the edge is reduced to the variable time of the interrupt latency or about one half the execution time of the longest instruc tion This uncertainty is approximately 10 clocks or 0 5 us for a 20 MHz clock This enables pulse width measurements for pulses of any length with a precision of about 1 us If multiple pulses need to be measured simultaneously then the precision will be reduced but this reduction can be minimized by careful programming 4 1 1 Pulse Width Modulation to Reduce Relay Power Typically relays need far less current to hold them closed than is needed to initially close them For example if the driver is switched to a 75 duty cycle using pulse width modu lation after the initial period when the relay armature is picked the holding current will be approximately 75 of the full duty cycle current and the power consumption will be about 56 as great 50 Rabbit 2000 Microprocessor 4 2 Open Drain Outputs Used for Key Scan The Parallel Port D outputs can be individually progr
171. al configuration of the proces sor Processors are expected to have RAM connected to CS1 WEI and OE1 Flash is expected to be connected to 50 WEO and OEO See the Rabbit 3000 Designer s Handbook Memory Planning chapter if you want to design a board with RAM only The crystal frequency is expected to be n 1 8432 MHz The Rabbit 3000 Designer s Handbook has a chapter on the Rabbit BIOS with more details 17 2 Virtual Driver The Virtual Driver is compiled with the user s application It includes support for the fol lowing services e Hitting the hardware watchdog timer e Decrementing software watchdog timers e Synchronizing the system timer variables with the real time clock and keeping them updated e Driving uC OS II multi tasking e Driving slice statement multi tasking 17 2 1 Periodic Interrupt The periodic interrupt that drives the Virtual Driver occurs every 16 clocks or every 488 us If the 32 768 kHz oscillator is absent it is possible to substitute a different periodic interrupt This alternative is not supported by Z World since the cost of connecting a crys tal is very small The periodic interrupt keeps the interrupts turned off that is the proces sor priority is raised to 1 from zero for about 75 clocks so it contributes little to interrupt latency The periodic interrupt is turned on by default before main is called It can be disabled if needed The Dynamic C Users s Manual chapter on the Virtua
172. ammed to be open drain This is use ful for scanning a switch matrix as shown in Figure 4 2 A row is driven low then the col umns are scanned for a low input line which indicates a key is closed This is repeated for each row The advantage of using open drain outputs is that if two keys in the same col umn are depressed there will not be a fight between a driver driving the line high and another driver driving it low Figure 4 2 Using Open Drain Outputs for Key Scan User s Manual 51 4 3 Cold Boot Most microprocessors start executing at a fixed address often address zero after a reset or power on condition The Rabbit has two mode pins SMODE0 SMODE1 see Figure 5 1 The logic state of these two pins determines the startup procedure after a reset If both pins are grounded then the Rabbit starts executing instructions at address zero On reset address zero is defined to be the start of the memory connected to the memory control lines CSO and OEO However three other startup modes are available These alternate methods all involve accepting a data stream via a communications port that is used to store a boot program in a RAM memory which in turn can be used to start any further second ary boot process such as downloading a program over the same communications port For a detailed description see Section 7 11 Bootstrap Three communication channels may be used for the
173. and code 0x54 below only 0 52 Clock the most significant byte of the watchdog timer from the peripheral clock Intended for chip test and code 0x54 below only 0 53 Clock both bytes of the watchdog timer in parallel from the peripheral clock Intended for chip test and code 0x54 below only 7 0 Disable the watchdog timer This value by itself does not disable the watchdog timer Only a sequence of two writes where the first write is 0x54 0x51 0x52 or 0x53 followed by a write of 0x54 actually disables the watchdog timer The watchdog timer will be re enabled by any other write to this register c Normal clocking 32 kHz oscillator for the watchdog timer This is the condition after reset The code to do this may also hit the watchdog with a 0 25 second period to speed up the reset Such watchdog code must be written so that it is highly unlikely that a crash will incorporate the code and continue to hit the watchdog in an endless loop The following suggestions will help 1 Place a jump to self before the entry point of the watchdog hitting routines This pre vents entry other than by a direct call or jump to the routine 2 Before calling the routine set a data byte to a special value and then check it in the rou tine to make sure the call came from the right caller If not go into an endless loop with interrupts disabled 3 Maintain data corruption flags and or checksums If these go wrong go into an e
174. and cold boot the target a Rabbit based microprocessor board e If the Rabbit is used as a slave processor the master processor can cold boot it over via the slave port This means the slave can operate without any nonvolatile memory Only RAM is required 52 Rabbit 2000 Microprocessor 4 4 The Slave Port The slave port allows a Rabbit to act as a slave to another processor which can also be a Rabbit The slave has to have only a processor chip a RAM chip and clock and reset sig nals that can be supplied by the master The master can cold boot and download a program to the slave The master does not have to be a Rabbit processor but can be any type of pro cessor capable of reading and writing standard registers For a detailed description see Chapter 13 Rabbit Slave Port The slave processor s slave port is connected to the master processor s data bus Commu nication between the master and the slave takes place via three registers implemented in the Rabbit for each direction of communication for a total of six data registers In addi tion there is a slave port status register that can be read by either the master or the slave see Figure 13 1 Two slave address lines are used by the master to select the register to be read or written The registers that carry data from the master to the slave appear as write registers to the master and as read registers to the slave The registers that operate in the opposite direction app
175. ansmitting 0x0D6 Tx with 9th bit zero 0 1 al Start Bit 9th bit Stop Bit Signals Shown at Microprocessor Tx Pin Figure 12 2 Functional Block Diagram of a Serial Port 164 Rabbit 3000 Microprocessor The clock input to the serial port unit must be 8 or 16 selectable times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used Timers A2 A7 supply the input clock for Serial Ports A F These timers can divide the frequency by any number from 1 to 256 see Chapter 11 The input frequency to the timers can be selected in different ways described in the documentation for the timers One choice is the peripheral clock with that choice and a well chosen crystal frequency for the main oscillator the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescaling timer AO at the highest Rabbit clock fre quencies see Section A 3 in Appendix A User s Manual 165 12 2 Serial Port Registers Each serial port has 6 registers shown in the tables below The status control and extended registers may have somewhat different formats for different serial ports Table 12 2 Serial Port A Registers Register Name Mnemonic Address R W Reset Serial Port A Data Register SADR 0xC0 R W XXXXXXXX Se
176. any IrDA encoded pulses enough to look like NRZ data but not so much as to interfere with real NRZ data When a bootstrap is performed using Serial Port A the TXA signal is not needed since the bootstrap is a one way communication After the reset ends and the bootstrap mode begins TXA will be low reflecting its function as a parallel port output bit that is cleared by the reset This may be interpreted as a break signal by some serial communication devices TXA can be forced high by sending the triplet 0x80 0x50 0x40 which stores 0x40 in Parallel Port C An alternate approach is to send the triplet 0x80 0x55 0x40 which will enable the TXA output from bit 6 of Parallel Port C by writing to the Parallel Port C function register 0x55 The transfer rate in any bootstrap operation must not be too fast for the processor to exe cute the instruction stream The Write Empty signal acts as an interlock when using the Slave Port for bootstrap operation because the next byte should not be written to the Slave Port until the Write Empty signal is active No such interlock exists for the clocked serial and asynchronous bootstrap operation In these cases remember that the processor clock starts out in divide by eight mode with four wait states and limit the transfer rate accord ingly In asynchronous mode at 2400 bps it takes about 4 ms to send each character so no problem is likely unless the system clock is extremely slow 102 Rabbit 3000 Mic
177. ap tured In this case the start and stop conditions lose the connection with starting or stop ping the counter and simply become capture conditions that may be specified for 2 independent edge detectors The counter can also be cleared and started under software control and then have its value captured in response to an input If desired the capture counter can synchronized with Timer B outputs used to synchro nously load parallel port output registers This makes it possible to generate an output sig nal precisely synchronized with an input signal Usually it will be desired to synchronize one of the input capture counters with the Timer B counter The count offset can be mea sured by outputting a pulse at a precise time using Timer B to set the output time and cap turing the same pulse Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B The minimum time delay needed is probably less than 10 microseconds if the software is done carefully the clock speed is rea sonably high 2 2 10 Quadrature Encoder Inputs A quadrature encoder is a common electromechanical device used to track the rotation of a shaft or in some cases to track the motion of a linear follower These devices are usually implemen
178. apacitance Time Delay 30pF 60pF 90pF Max clock to address delay T a 6ns 8 ns 11 ns Max clock to memory chip select delay Tcs 6 ns 8 ns 11 ns Max clock to memory read strobe delay 6 ns 8 ns 11 ns Min data setup time T etup 1 ns Min data hold time Ons The measurements were taken at the 50 points under the following conditions e T 40 C to 85 C V 3 3 V e Internal clock to nonloaded CLK pin delay lt 1 ns 85 C 3 0 V The following memory write time delays were measured Table 16 4 Memory Write Time Delays Output Capacitance Time Delay 30pF 60pF 90pF Max clock to address delay 6 ns 8 ns 11 ns Max clock to memory chip select delay Tcsx 6 ns 8 ns 11 ns Max clock to memory write strobe delay Twex 6 ns 8 ns 11 ns Max high Z to data valid rel to clock Tpgzy 10 ns 12 ns 15 ns Max data valid to high Z rel to clock Tpygz 10 ns 12 ns 15 ns The measurements were taken at the 5096 points under the same conditions that the mem ory read delays were measured See Table 16 2 for delays at other voltages 218 Rabbit 3000 Microprocessor A 19 0 Memory Read no wait states CSx EE Jl OEx E Togx I lt ToEx D 7 0 A 19 0 CSx ANEx D 7 0 gt Tos gt lt Tcsx Figure 16 3 Memory Read and Write Cycles Early Output Enable an
179. arallel port alternate func TOMS sissioni 316 Port A decode bug fix 276 PWM improvements 276 quadrature decoder improve MENS 276 RAM segment relocation 276 secondary watchdog timer 276 stack protection 276 System User mode 276 variants of block move op COGS site 276 User s Manual 339 s secondary watchdog timer 292 serial ports 11 161 9th bit protocols 196 address registers 168 baud rates 163 breaks 4 see 194 clocked serial ports Ports D iii ten 182 clocked serial timing 185 control registers Ports A B E 173 control registers Ports C D 174 control registers Ports E F 175 controlling RS 485 driver and receiver aspasia 193 data and parity bits 163 data registers 168 dummy characters 193 extended asynchronous mode registers ee 176 extended registers clocked se rial mode Ports A D 177 extra stop bits parity 194 HDLC mode extended regis ters Ports E F 178 HDLC mode status registers Ports 172 interrupt service routines 192 Interrupts 179 long stop registers 169 master slave protocol 196 Modbus 196 periodic interr
180. armonics at a given frequency by 6 dB or more The effect of pure harmonic noise on an FM station is to either completely block out a sta tion near the harmonic frequency or to disturb reception of that station If the spectrum spreader is engaged then interference will be spread across the band but will generally be User s Manual 213 so low as to be undetectable except perhaps for extremely weak stations The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station s band If the spreader is engaged the pattern will disappear unless the station is very weak in which case the interference will be seen as noise distrib uted over the screen 214 Rabbit 3000 Microprocessor 16 AC TIMING SPECIFICATIONS The Rabbit 3000 processor be operated at voltages between 1 8 V and 3 6 V and at temperatures from 40 C to 85 C with use possible use over the extended range 55 C to 105 C For long it is desirable not to exceed a die temperature of 125 C Most users will operate the Rabbit at 3 3 V 16 1 Memory Access Time Required memory address and output enable access time for some important typical cases are given in the table below It is assumed that the clock doubler is used that the clock spreader is enabled in the normal mode that the memory early output enable is on and that the address bus has 60 pF load Table 16 1 Memory Requirements at 3
181. asy to do so for byte formats that use only 7 data bits in which case the 9th bit or parity bit is actually an 8th bit Sending a 9th low bit is supported by hardware Sending a 9th bit as a high value requires a write to the Serial Port A F Long Stop Register SxLR which is the same as two stop bits 194 Rabbit 3000 Microprocessor Figure 12 9 illustrates the standard asynchronous serial output patterns stop bit start bit data bits 9th bit low Character with 9th bit low stop bit 0 7 startbit Character w o 9th bit low 0 7 Character w 9th bit high start bit 5 9th bit high Generated by a Write to SxLR Signal shown at output pin on processor 1 is high Figure 12 9 Asynchronous Serial Output Patterns 12 9 6 Parity Extra Stop Bits with 7 Data Bit Characters If only 7 data bits are being sent sending an additional parity or signal bit is easily solved by sending 8 bits and always setting bit 7 the eighth bit of the byte to 1 or 0 depend ing on what is desired No special precautions are needed if two stop bits are to be received If parity is received with 7 data bits receive the data as 8 bits and the parity will be in the high bit of the byte 12 9 7 Parity Extra Stop Bits with 8 Data Bit Characters In order to receive parity with 8 data bits a check is made on each characte
182. avs return zeros when read 0 Enable A16 and A19 inversion independent of instruction data 5 Enable A16 and A19 inversion controlled by bits 0 3 for data accesses only This enables the instruction data split This is separate I and D space 0 Normal CS1 operation 4 Force CS1 always active This will not cause any conflicts as long as the 1 memory using CS1 does not also share an Output Enable or Write Enable with another memory 0 Normal operation 1 1 For a DATASEG access invert A19 before MBxCR bank select decision 0 Normal operation 1 For a DATASEG access invert 16 0 Normal operation 1 For root access invert 19 before MBxCR bank select decision 0 Normal operation 1 For root access invert A16 See Table B 20 for information on bit 7 for Rabbit 3000A and later versions User s Manual 121 Table 8 5 MMU Expanded Code Register MECR 0x018 MMU Expanded Code Register MECR Address 0x018 Bit s Value Description 7 3 These bits are ignored for write and return zeros when read Oxx Normal operation 100 For an XPC access use MBOCR independent of A19 A18 2 0 101 For an XPC access use MB1CR independent of A19 A18 110 For an XPC access use MB2CR independent of A19 A18 111 For an XPC access use MB3CR independent of A19 A18 The Memory Timing Control Register MTCR enables the extended timing for the memory o
183. because the details are handled by the Dynamic C development system Except for a handful of special instructions see Section 19 5 16 bit Load and Store 20 bit Address the Rabbit instructions directly address a 64K data memory space This means that the address fields in the instructions are 16 bits long and that the registers that may be used as pointers to memory addresses index registers IX IY program counter and stack pointer SP are also 16 bits long Because Rabbit instructions use 16 bit addresses the instructions are shorter and can exe cute much faster than if for example 32 bit addresses were used The executable code is very compact The Rabbit memory mapping unit is similar to but more powerful than the Z180 mem ory mapping unit Figure 3 2 illustrates the relationship among the major components related to addressing memory Memory Memory Memo Mapping Interface lt gt Chips E Unit Processor 20 bits plus control Figure 3 2 Addressing Memory Components The memory mapping unit receives 16 bit addresses as input and outputs 20 bit addresses The processor except for certain LDP instructions sees only a 16 bit address space That is it sees 65536 distinctly addressable bytes that its instructions can manipulate Three segment registers are used to map this 16 bit space into a 1 megabyte space The 16 bit space is divided into four separate zones Eac
184. begin a cold boot process at the end of the slave reset 202 Rabbit 3000 Microprocessor Master Rabbit First Slave Rabbit D0 D7 SD0 SD7 IORD ISRD ISWR A0 SA0 Al 1 SMODEO CLK XTALBI portout RESET SMODEI INTOA SLAVEATTN 17 ISCS INTIA 16 Second Slave Rabbit Reset Pulldown SMODEO SLAVEATIN MODEL SCS Figure 13 4 Typical Connection Slave Rabbit to Master Habbit The slave port lines are shown in Figure 13 1 The function of these lines is described below e SDO SD7 These are bidirectional data lines and are generally connected to the data bus of the master processor Multiple slaves can be connected to the data bus The slave drives the data lines only when SCS and SRD are both pulled low e SA1 SAO0 These are address lines used to select one of the four data registers of the slave interface Normally these lines are connected to the low order address lines of the master The master always drives these lines which are always inputs to the slave e SCS Input Slave chip select The slave ignores read or write requests unless the chip select is low If a Rabbit is used as a master this line can be connected to one of the master s programmable chip select lines 10 17 e SRD Input If SCS is also low this line pulled low causes the contents of the register selected by the address lines to be driven on the data bus If a Rabbit is used as a master
185. bootstrap either Serial Port A in asyn chronous mode at 2400 bps Serial Port A in synchronous mode with an external clock or the parallel slave port The cold boot protocol accepts groups of three bytes that define an address and a data byte Each triplet causes a write of the data byte to either memory or to internal I O space The high bit of the address is set to specify the I O space and thus writes are limited to the first 32K of either space The cold boot is terminated by a store to an address in I O space which causes execution to begin at address zero Since any memory chip can be remapped to address zero by storing in the I O space RAM can be temporarily be mapped to zero to avoid having to deal with the more complicated write protocol of flash memory which is the usual default memory located at address zero The following are the advantages of the cold boot capability e Flash memory can be soldered to the microprocessor board and programmed via a serial port or a parallel port This avoids having to socket the part or program it with a BIOS or boot program before soldering e Complete reprogramming of the flash memory can be accomplished in the field This is particularly useful during software development when the development platform can perform a complete reload of software regardless of the state of the existing software in the processor The standard programming cable for Dynamic C allows the development platform to reset
186. bort command takes effect on the next byte boundary and causes the transmission of an OxFE a zero fol lowed by seven ones after which the transmitter will send the idle line condition The Abort command also purges the transmit FIFO The idle line condition may be either Flags or all ones Both the receiver and transmitter contain four bytes of buffering for the data Status bits are buffered along with the data in both receiver and transmitter The receiver automati cally generates an interrupt at the end of a received frame and the transmitter generates an interrupt at the end of CRC transmission at the end of the transmission of an Abort sequence and at the end of the transmission of a closing Flag The transmitter is not capable of sending an arbitrary number of bits but only a multiple of bytes However the receiver can receive frames of any bit length If the last byte in the frame is not eight bits the receiver sets a status flag that is buffered along with this last byte Software can then use the table below to determine the number of valid data bits in this last byte Note that the receiver transfers all bits between the opening and closing Flags except for the inserted zeros to the receiver data buffer Last Byte Bit Pattern Valid Data Hits bbbbbbbO 7 bbbbbb01 6 bbbbb011 5 bbbb0111 4 bbb01111 3 bb011111 2 b0111111 1 Several types of data encoding are available in the HDLC mode In
187. byte transferred automatically resets the watchdog timer However the watchdog timer still operates and bytes must be transferred often enough to prevent the watchdog timer from timing out Bootstrap operation is terminated when the SMODE pins are set to zero The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program If the SMODE pins are zero instructions are fetched from normal memory starting at address 0x0000 The Slave Port Control register allows the bootstrap operation to be terminated remotely Writing a one to bit 7 of this register causes the bootstrap operation to terminate immediately So the sequence 0x80 0x24 and 0x80 will terminate bootstrap operation Bootstrap operation is not restricted to the time immediately after reset because the boot ROM is addressed by only the four least significant bits of the address So any time that the address ends in four zeros if the SMODE pins are non zero and bit 7 of the SPCR is Zero the bootstrap program will begin execution This allows in line downloading from the selected bootstrap port Upon completion of the bootstrap operation either by return ing the SMODE pins to zero or setting the bit in the SPCR execution will continue from where it was interrupted for the bootstrap operation The Slave Port is selected for bootstrap operation when SMODEI SMODEO 0 1 In this case the pins of Parallel Port A are used for a byte wide data bus and se
188. c 5 fii R W Reset Timer B Control Status Register TBCSR OxBO R W xxxxx000 Timer B Control Register TBCR OxB1 w xxxx0000 Timer B MSB 1 Register TBMIR 0xB2 W XXXXXXXX Timer B LSB 1 Register TBLIR OxB3 W XXXXXXXX Timer B MSB 2 Register TBM2R OxB4 W XXXXXXXX Timer B LSB 2 Register TBL2R OxB5 W XXXXXXXX Timer B Count MSB Register TBCMR OxBE R XXXXXXXX Timer B Count LSB Register TBCLR OxBF R XXXXXXXX 156 Rabbit 3000 Microprocessor The control status register for Timer B TBCSR is laid out as shown in Table 11 7 Table 11 7 Timer B Control and Status Register Timer B Control and Status Register TBCSR Address 0x00BO Bit s Value Description 753 These bits always read as zero 0 Timer B2 comparator has not encountered a match condition en 1 Timer B2 comparator has encountered a match condition This status bit and the Timer B2 interrupt but not interrupt enable are cleared by a read of this register 2 0 Timer B2 interrupt disabled write 1 Timer B2 interrupt enabled 0 Timer B1 comparator has not encountered a match condition 2 1 Timer 1 comparator has encountered a match condition This status bit and the Timer interrupt but not interrupt enable are cleared by a read of this register 1 0 Timer B1 interrupt disabled write 1 Timer B1 interrupt enabled 0 Disable the main clock for Timer B 1 Enable the main clock for Timer B The control register f
189. ceive and transmit cases then the fastest external serial clock fre quency would be limited to perc1k 6 186 Rabbit 3000 Microprocessor 12 8 Synchronous Communications on Ports E and F Serial Port E and F are a dual function serial ports that can be used in either asynchronous or HDLC mode Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead An interrupt is generated whenever at least one byte is avail able in the receiver buffer and every time a byte is removed from the transmitter buffer Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3 In asynchro nous mode this clock can be either sixteen the default or eight times the data rate In HDLC mode this clock is sixteen times the data rate Note that the fastest output from Timer A2 or A3 is the same frequency as the peripheral clock Thus the maximum data rate is the peripheral clock frequency divided by eight in async mode and divided by six teen in HDLC mode The HDLC receiver employs a Digital Phase Locked Loop DPLL to generate a synchro nized receive clock for the incoming data stream HDLC mode also allows for an external 1 same speed as the data rate clock for both the receiver and the transmitter HDLC receive and transmit clocks can be input or output as appropriate via the specified pins When using an external clock the maximum data rate is one sixth of the peripheral clock rate In asyn
190. ces The Rabbit 3000 has two distinct external interrupt request lines If there are more than two external causes of interrupts then these lines must be shared between multiple devices The interrupt line is edge sensitive meaning that it requests an interrupt only when a rising or falling edge whichever is specified in the setup registers takes place The state of the interrupt line s can always be read by reading Parallel Port E since they share pins with Parallel Port E If several lines are to share interrupts with the same port the individual interrupt requests would normally be or ed together so that any device can cause an interrupt If several devices are requesting an interrupt at the same time only one interrupt results because there will be only one transition of the interrupt request line To resolve the situation and make sure that the separate interrupt routines for the different devices are called a good method is to have a interrupt dispatcher in software that is aided by providing separate attention request lines for each device The attention request lines are basically the inter rupt request lines for the separate devices before they are or ed together The interrupt dis patcher calls the interrupt routines for all devices requesting interrupts in priority order so that all interrupts are serviced 3 5 3 Privileged Instructions Critical Sections and Semaphores Normally an interrupt happens at the end of the instruction c
191. chronous mode the port can send and receive seven or eight bits and has the option of appending and recognizing an additional address bit On transmit the address bit is automatically appended to the data when this data is written to the address register or long stop register Writing to the address register appends an zero address bit to the data while writing to the long stop register appends an one address bit to the data The address bit is followed by a normal stop bit Normal data is written to the data register to be transmitted On receive a status bit distinguishes normal data from address data This status bit is set to one if a zero address bit is received In non address bit applications this indicates a framing error This status bit can also indicate a received break if the accompanying data is all zeros this is the definition of break Asynchronous mode oper ates full duplex Either the receive data available transmit buffer empty or transmit idle conditions can be programmed to generate an interrupt The HDLC mode allows full duplex synchronous communication Either an internal or external clock may be selected for both the receiver and the transmitter HDLC mode encapsulates data within opening and closing Flags and sixteen bits of CRC precedes the closing Flag All information between the opening and closing Flag is zero stuffed That is if five consecutive ones occur independent of byte boundaries a zero
192. ck on timer B2 The following registers are described in Table 9 17 and in Table 9 18 PGDR Port G data register Reads value at pins Writes to port G preload register PGCR Parallel Port G control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero PGFR Port G function register Set bit to 1 to enable alternate output function Bits 6 and 2 enable the asycnhronous or SDLC HDLC serial ports E and F outputs And bits 5 4 and 1 0 enable the SDLC HDLC transmit and receive clock outputs for serial ports E and F PGDCR Parallel Port G drive control register A 0 makes the corresponding pin a regular output 1 makes the corresponding pin an open drain output Write only PGDDR Port G data direction register Set to 1 to make corresponding pin an out put This register is zeroed on reset On reset the data direction register is zeroed making all pins inputs In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with port G are not initialized on reset 144 Rabbit 3000 Microprocessor 10 I O BANK CONTROL REGISTERS The pins of Port E can be set individually to be I O strobes Each of the eight possible I O strobes has a control register that controls the nature of the
193. controls which of the 256 4K pages the 8K window aligns with The 16 bit PC controls the address of the instruction usually in the region E000 to FFFF The advantage of paged access is that most instructions continue to use 16 bit addressing Only when an out of range transfer of control is made does a 20 bit transfer of control need to be made The beauty of having a 4K minimum step in page alignment while the size of the page is 8K is that code can be compiled continuously without gaps caused by change of page When the page is moved by 4K the previous end of code is still visible in the window provided that the midpoint of the page was crossed before moving the page alignment As the compiler compiles code in the extended code window it checks at opportune times to see if the code has passed the midpoint of the window or F000 When the code passes F000 the compiler slides the window down by 4K so that the code at F000 x becomes resident at E000 x This results in the code being divided into segments that are typically 4K long but which can very short or as long as 8K Transfer of control can be accom plished within each segment by 16 bit addressing 20 bit addressing is required between segments User s Manual 127 128 Rabbit 3000 Microprocessor 9 PARALLEL PORTS The Rabbit has seven 8 bit parallel ports designated A B C D E F and G The pins used for the parallel ports are also shared with numerous other functions as shown
194. d 204 13 3 Applications and Communications Protocols for Slaves sess 206 13 3 1 Slave Applications v eee oe eq enr pe HT 206 13 3 2 Master Slave Messaging Protocol n eene ene 207 User s Manual Chapter 14 Rabbit 3000 Clocks 1451 Low Poweft DeSISn ee au aa tee Chapter 15 EMI Control 15 1 Power Supply Connections and Board Layout 15 2 Using the Clock Spectrum Chapter 16 AC Timing Specifications 16 1 Memory Access Time 16 2 I O Access Time iion 16 3 Further Discussion of Bus and Clock Timing 16 4 Maximum Clock Speeds 2 16 5 Power and Current Consumption see 16 6 Current Consumption Mechanisms esses 16 7 Sleepy Mode Current Consumption eese 16 8 Memory Current Consumption 16 9 Battery Backed Clock Current Consumption 16 10 Reduced Power External Main Oscillator Chapter 17 Rabbit BIOS and Virtual Driver IT l The BIOS a ananassa maaa atakay 17 11 BIOS Services saa al e eee 17 1 2 BIOS Assumptions esee 17 2 Virtual Drivers eee err eee rete rs 17 2 1 Periodic Interrupt veesii 17 2 2 Watchdog Timer Support
195. d Write Enable Timing User s Manual 219 Figure 16 4 illustrates the sources that create memory access time delays clock period shortening due to spectrum spreader clock address data clock to address data in setup time output lt q memory 85 4 time output enable early 4 memory output enable time Figure 16 4 Sources of Memory Access Time Delays The gross memory access time is 2T where T is the clock period To calculate the actual memory access time subtract the clock to address output time the data in setup time and the clock period shortening due to the clock spectrum spreader from 2T Example clock 29 49 MHz 234ns operating voltage is 3 3 V bus loading is 60 pF address to output time 8 ns see Table 16 2 data setup time 1 ns the spectrum spreader is on in normal mode resulting in a loss of 3 ns The access time is given by access time 2T clock to address data setup spreader delay 68 ns 8 ns 1 ns 3 ns 56 ns 220 Rabbit 3000 Microprocessor The required memory output enable access time is more complicated since it is affected by the clock doubler delays The clock doubler setup register creates a nominal delay time ranging from 6 to 20 ns resulting in a nominal clock low time ranging from 6 to 20 ns The clock low time depends on internal delays and is sub
196. d according to Table C 5 322 Rabbit 3000 Microprocessor Table C 5 Interrupts Priority and Action to Clear Requests Priority Interrupt Source Action required to clear the interrupt Highest System Mode Violation Automatically cleared by the interrupt acknowledge Stack Limit Violation Automatically cleared by the interrupt acknowledge Write Protection Violation Automatically cleared by the interrupt acknowledge Secondary Watchdog Restart the Secondary Watchdog by writing to WDTCR External 1 Automatically cleared by the interrupt acknowledge External 0 Automatically cleared by the interrupt acknowledge Periodic 2 kHz Read the status from the GCSR Quadrature Decoder Read the status from the QDSR Timer B Read the status from the TBSR Timer A Read the status from the TASR Input Capture Read the status from the ICCSR PWM Write any PWM register Rd Read the data from the SPDOR SPD1R or SPD2R Slave Port Wr Write data to the SPDOR SPDIR SPD2R or write a dummy byte to the SPSR Rx Read the data from the SEDR or SEAR Serial Port E Tx Write data to the SEDR SEAR SELR or write a dummy byte to the SESR Rx Read the data from the SFDR or SFAR Serial Port F Tx Write data to the SFDR SFAR SFLR or write a dummy byte to the SESR Rx Read the data from the SADR or SAAR Serial Port A Tx Write data to the SADR SAAR SALR or write a dummy byte to the SASR
197. d or Store Data Using an Index Register on page 34 Register to Register Move on page 35 Register Exchanges on page 35 Push and Pop Instructions on page 36 16 bit Arithmetic and Logical Ops on page 36 Input Output Instructions on page 39 these include a fix for a bug that manifests itself if an I O instruction prefix IOI or IOE is followed by one of 12 single byte op codes that use HL as an index register In the discussion that follows we give a few example instructions in each general category and contrast the Z80 Z180 with the Rabbit For a detailed description of every instruction see Chapter 19 Rabbit Instructions The Rabbit executes instructions in fewer clocks then the Z80 or Z180 The Z180 usually requires a minimum of four clocks for 1 byte opcodes or three clocks for each byte for multi byte op codes In addition three clocks are required for each data byte read or writ ten Many instructions in the Z180 require a substantial number of additional clocks The Rabbit usually requires two clocks for each byte of the op code and for each data byte read Three clocks are needed for each data byte written One additional clock is required if a memory address needs to be computed or an index register is used for addressing Only a few instructions don t follow this pattern An example is mul a 16 x 16 bit signed two s complement multiply mul is a 1 byte op code but requires 12 clocks to execute Compared to t
198. data Using Stack Segment Using Data Segment for for a Data Window a Data Window Code must be copied to RAM on startup Figure 3 7 Schemes for Data Memory Windows A third approach is to place the data and root code in RAM in the root segment freeing the data segment to be a window to extended memory This requires copying the root code to RAM at startup time Copying root code to RAM is not necessarily that burdensome since the amount of RAM required can be quite small say 12K for example The XPC segment at the top of the memory can also be used as a data segment by pro grams that are compiled into root memory This is handy for small programs that need to access a lot of data 3 2 4 Practical Memory Considerations The simplest Rabbit configurations have one flash memory chip interfaced using CSO and one RAM memory chip interfaced using CS1 Typical Rabbit based systems use 256K of flash and 128 K of RAM but smaller or larger memories may be used Although the Rabbit can support code size approaching a megabyte it is anticipated that the majority of applications will use less than 250K of code equivalent to approximately 10 000 20 000 C statements This reflects both the compact nature of Rabbit code and the typical size of embedded applications Directly accessible C variables are limited to approximately 44K of memory split between data stored in flash and RAM This will be more than adequate for
199. de in the XPC segment is called Functions located in the root have an efficiency advantage because a long call and a long return require 32 clocks to execute but a short call and a short return require only 20 clocks to execute The differ ence is small but significant for short subroutines Compiler notices that Compiler inserts code has passed F000 long jump in code XPC segment Stack segment 8 short calls Data segment terng XPC N XPC N 1 PC F000 K PC E000 K 4 E000 Root segment Illustration of sliding XPC window Figure 3 5 Use of XPC Segment 3 2 2 Separate and D Space Extending Data Memory In the normal memory model the data space must share a 64K space with root code the stack and the XPC window Typically this leaves a potential data space of 40K or less The XPC requires 8K the stack requires 4K and most systems will require at least 12K of root code This amount of data space is sufficient for many embedded applications One approach to getting more data space is to place data in RAM or in flash memory that is not mapped into the 64K space and then access this data using function calls or in assembly language using the LDP instructions that can access memory using a 20 bit address This greatly expands the data space but the instructions are less efficient than instructions that access the 64k space using 16 bit addresses The Rabbit 3000 suppo
200. ditions for the various revisions of the Rabbit 3000 Table B 1 Summary of Rabbit 3000 Improvements and Fixes Rabbit Rabbit Description 3000 3000A ILIT IZ1T IL2T IZ2T ID Registers for version revision identification X X System User mode Memory protection scheme Stack protection RAM segment relocation Secondary watchdog timer Multiply add and multiply subtract Variants of block move opcodes 16 bit internal I O address space External I O interface enhancements Expanded low power capability PWM improvements Quadrature decoder improvements Integrated Schmitt trigger for 32 kHz oscillator input Alternate output port connection for numerous peripherals Port A decode bug fix LDIR LDDR with wait states bug fix Interrupt after I O with short CSx enabled bug fix W w x w w X w X IrDA bug fix 276 Rabbit 3000 Microprocessor B 1 1 Rabbit Internal I O Registers Table B 2 summarizes the reset state of the new I O registers added in the Rabbit 3000A revision Table B 3 summarizes the reset state of the existing I O registers with new features Table B 2 Reset State of New Rabbit 3000A I O Registers Register Name Mnemonic A ET R W Reset Secondary Watchdog Timer Register SWDT
201. e When the slave port is enabled parallel port lines PB2 PB7 are assigned to various slave port functions However it is still possible to read 5 using the Port B data register even when lines PB2 PB7 are used for the slave port It is also possible to read the signal driving PB6 and PB7 this signal is on the signaling lines from the slave port logic Regardless of whether the slave port is enabled PBO reflects the input of the pin unless Serial Port B has its internal clock enabled which causes this line to be driven by the serial port clock PB 1 reflects the input of the pin unless Serial Port A has its internal clock enabled e PBDR Parallel Port B data register Read Write e PBDDR Parallel Port B data direction register A 1 makes the corresponding pin an output This register is write only User s Manual 131 9 3 Parallel Port C Parallel Port C shown in Table 9 6 has four inputs and four outputs The even numbered ports PCO PC2 PC4 and PC6 are outputs The odd numbered ports PC1 PC3 5 and PC7 are inputs When the data register is read bits 1 3 5 7 return the value of the volt age on the pin Bits 0 2 4 6 return the value of the signal driving the output buffers The signal driving the output buffers and the value of the output pin are normally the same Either the Port C data register is driving these pins or one of the serial port transmit lines is driving the pin The bits set in the P
202. e by sixteen counter The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up With Biphase Level encoding there is a guaranteed clock transition at the center of every bit cell and optional data transitions at the bit cell boundaries The DPLL only uses the clock transitions to track the bit cell boundaries by ignoring all transitions occur ring outside a window around the center of the bit cell This window is half a bit cell wide Additionally because the clock transitions are guaranteed the DPLL requires that they always be present If no transition is found in the window around the center of the bit cell for two successive bit cells the DPLL is not in lock and immediately enters the search mode Search mode assumes that the next transition seen is a clock transition and immedi ately synchronizes to this transition No clock output is provided to the receiver during the search operation Decoding Biphase Level data requires that the data be sampled at either the quarter or three quarter point in the bit cell The DPLL here uses the quarter point to sample the data Biphase Mark and Biphase space encoding are identical as far as the DPLL is concerned and are similar to Biphase Level The primary difference is the placement of the clock and data transitions With these encodings the clock transitions are at the bit cell boundary and the data transitions are at the center of the
203. e largest unsigned number OxOFFFF Once the numbers have been converted the com parision can be done as for unsigned numbers This procedure is faster than using a jump tree that requires testing the sign and overflow bits example test for HL gt DE where HL and DE are signed numbers invert sign bits on both ADD HL HL shift left CCF invert carry RR HL rotate right RL DE CCF RR DE invert DE sign SBC HL DE no carry if HL gt DE generate boolean variable true if HL gt DE SBC HL HL zero if no carry else 1 INC HL 1 if no carry else zero BOOL use this instruction to set flags if needed User s Manual 37 The sBc instruction can also be used to perform a sign extension extend sign of 1 to HL LD A 1 rla sign to carry SBC A a a is all 1 s if sign negative LD h a Sign extended The multiply instruction performs a signed multiply that generates a 32 bit signed result MUL Signed multiply of BC and DE result in HL BC 1 byte 12 clocks If a 16 bit by 16 bit multiply with a 16 bit result is performed then only the low part of the 32 bit result BC is used This counter intuitively is the correct answer whether the terms are signed or unsigned integers The following method can be used to perform a 16 x 16 bit multiply of two unsigned integers and get an unsigned 32 bit result This uses the fact that if a negative number is multiplied the sign causes the other multiplier to be sub tract
204. e slave attention line SLAVEATTN pin 100 is asserted driven low by the slave processor This line can be used to create an interrupt in the master Either side that is interrupted can clear the signal that is causing an interrupt request by writ ing to the slave port status register The data bits are ignored but the flip flop that is the source of the interrupt request is cleared Figure 13 3 shows a logical schematic of this func tionality User s Manual 201 Master writes SPDOR Slave inbound interrupt requested Visible in status register Slave writes status register Slave writes SPDOR SLAVEATTN PB7 Visible in status register Master writes status register Figure 13 3 Slave Port Handshaking and Interrupts Figure 13 4 shows a sample connection of two slave Rabbits to a master Rabbit The mas ter drives the slave reset line for both slaves and provides the main processor clock from its own clock There is no requirement that the master and slave share a clock but doing so makes it unnecessary to connect a crystal to the slaves Each Rabbit in Figure 13 4 has to have RAM memory The master must also have flash memory However the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program In order for this to happen the SMODEO and SMODEI pins must be properly configured as shown in Figure 13 4 to
205. e their inputs to the peripheral clock fur ther divided by Timer 8 there is some delay between the input transition and when an interrupt is requested as shown below The status bits in the ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR Peri Clock Timer A8 Interrupt Each Input Capture channel has two inputs called the Start condition and the Stop condi tion Each of these two inputs can be programmed to come from one of four bits bits 1 3 5 or 7 in Parallel Port C D F or G The two inputs can come from the same or different pins and are edge sensitive Each input can be disabled rising edge sensitive falling edge sensitive or responsive to either edge polarity Either or both inputs can generate an Input Capture interrupt and either or both inputs can cause the current count to be latched User s Manual 105 Each Input Capture counter operates in one of three modes or can be disabled The counter is never automatically reset but must be reset by a software command Although it does not generate an interrupt there is a status bit which is set when the counter over flows counts from OxFFFF to 0x0000 so that software can recognize this condition To prevent potential stale data problems whenever the LSB of the latched count is read from the ICLxR the corresponding MSB of the latched count is transferred to
206. ear as read registers to the master and as write registers to the slave These registers appear as read write registers on both sides but are not true read write reg isters since different data may be read from what is written The master provides the clock or strobe to store data in the three write registers under its control The master also can do a write to the status register which is used as a signaling device and does not actually write to the status register The three registers that the master can write appear as read reg isters to the slave Rabbit The master provides an enable strobe to read the three read data registers and the status register These registers are write registers to the Rabbit The first register or the three pairs of registers is special in that writing can interrupt the other processor in the master slave communications link An output line from the slave is asserted when the slave writes to slave register zero This line can be used to interrupt the master Internal circuits in the slave can be setup up to interrupt the slave when the master writes to slave register zero The status register that is available to both sides keeps score on all the registers and reports if a potential interrupt is requested by either side The status register keeps track of the full empty status of each register A register is considered full when one side of the link writes to it It becomes empty if the other side reads it In this way
207. eceive otherwise for transmit The receiver receives first consideration because it must be serviced attentively or data could be lost The dispatcher might look as follows interrupt PUSH AF 10 IOI LD A SCSR 7 get status register serial port C JP m receive 7 go service the receive interrupt i else service transmit interrupt The individual interrupts would assume that register AF has been saved and the status reg ister has been loaded into Register A The interrupt service routines can as a matter of good practice and obtaining optimum performance remove the cause of the interrupt and re enable the interrupts as soon as pos sible This keeps the interrupt latency down and allows the fastest transmission speed on all serial ports All the serial ports will normally generate priority level 1 interrupts In exceptional circum stances one or more serial ports can be configured to use a higher priority interrupt There is an exception to be aware of when a serial port has to operate at an extremely high speed At 115 200 bps the highest speed of a PC serial port the interrupts must be serviced in 10 baud times or 86 us in order not to lose the received characters If all six serial ports were operating at this receive speed it would be necessary to service the interrupt in less than 21 5 us to assure no lost characters In addition the time taken by other interrupts of equal or higher priority would have to be considered A
208. ed Serial Ports Ports A D can operate in clocked mode The data line and clock line are driven as shown in Figure 12 4 The data and clock are provided as 8 bit bursts with the LSB shifted out and or received first By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock The serial port can generate the clock or the clock can be provided externally The clock polarity is programmable in clocked serial mode according to Figure The clocked serial transfer may also be synchronized to the output of either of the match conditions in Timer B to give precisely timed transfers To enable the clocked serial mode a code must be in bits 3 2 of the control register enabling the clocked serial mode with either an internal clock or an external clock The transition between the external and the internal clock should be performed with care Normally a pullup resistor is needed on the clock line to prevent spurious clocks while neither party is driving the clock CLK Mode 00 LIT LE LIE LIE LIL CLK Mode 10 ss ETE apenas l l C l l l l en X m Figure 12 5 Clock Polarities Supported in Clocked Serial Mode In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications However to initiate basic sending or receiving a
209. ed for asynchronous or SDLC HDLC communication Parallel Ports D G behave in the same manner when used as digital I O NOTE There may be a conflict in using Parallel Port A and Parallel Port F Either Paral lel Port A can be used as inputs in which case Parallel Port F has full function or if Parallel Port A cannot be used as inputs use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled Refer to Section 9 6 1 Using Parallel Port A and Parallel Port E for more information User s Manual 129 9 1 Parallel Port A Parallel Port A has a single read write register Table 9 1 Parallel Port A Registers Register Name Mnemonic I O address R W Reset Port A Data Register PADR 0x30 R W XXXXXXXX Slave Port Control Register SPCR 0x24 R W 0xx00000 Table 9 2 Parallel Port A Data Register Bit Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PADR R W PA7 PA6 PAS PA4 PA3 PA2 0 030 This register should not be used if the slave port 1 bus is enabled The slave port control register is used to control whether Parallel Port A is configured as slave databus auxiliary I O data bus parallel Input or parallel output To make the port an input store 0x080 in the SPCR
210. ed from the product The method shown below adds double the number subtracted so that the effect is reversed and the sign bit is treated as a positive bit that causes an addition LD BC n1 LD HL BC save BC in HL LD DE n2 LD A b Save sign of BC MUL form product in HL BC OR a test sign of BC multiplier JR 1 if plus continue ADD HL DE adjust for negative sign in BC 1 RL DE test sign of DE JR nc x2 if not negative Subtract other multiplier from HL EX DE HL ADD HL DE x2 final unsigned 32 bit result in HL BC This method can be modified to multiply a signed number by an unsigned number In that case only the unsigned number has to be tested to see if the sign is on and in that case the signed number is added to the upper part of the product The multiply instruction can also be used to perform left or right shifts A left shift of n positions can be accomplished by multiplying by the unsigned number 2 n This works for n 15 and it doesn t matter if the numbers are signed or unsigned In order to do a right shift by n 0 n 16 the number should be multiplied by the unsigned number 2 16 n and the upper part of the product taken If the number is signed then a signed by unsigned multiply must be performed If the number is unsigned or is to be treated as unsigned for a logical right shift then an unsigned by unsigned multiply must be per formed The problem can be simplified by excluding the case
211. egis ter and can be programmed to generate an interrupt There is one interrupt vector for Timer A and a common interrupt priority A common status register TACSR has a bit for each timer that indicates if the output pulse for that timer has taken place since the last read of the status register When the status register is read these bits are cleared No bit will be lost Either it will be read by the status register read or it will be set after the status register read is complete If a bit is on and the corresponding interrupt is enabled an interrupt will occur when priorities allow However a separate interrupt is not guaranteed for each bit with an enabled interrupt If the bit is read in the status register it is cleared and no further interrupt corresponding to that bit will be requested It is possible that one bit will cause an interrupt and then one or more additional bits will be set before the status register is read After these bits are cleared they cannot cause an interrupt If any bits are on and the corresponding interrupt is enabled then the interrupt will take place as soon as priorities allow However if the bit is cleared before the interrupt is latched the bit will not cause an interrupt The proper rule to follow is for the interrupt routine to handle all bits that it sees set Although timers A8 A10 are part of Timer A they are dedicated to the input pulse cap ture PWM and quadrature decoder peripherals respectively
212. either side can test if the other side has modified a register or whether either side has even stored the same informa tion to a register The master slave communication link makes possible set and forget communication protocols Either side can issue a command or request by storing data in some register and then go about its business while the other side takes care of the request according to its own time schedule The other side can be alerted by an interrupt that takes place when a store is made to register zero or it can alert itself by a periodic poll of the status register User s Manual 53 Of the three registers seen by each side for each direction of communication the first reg ister slave register zero has a special function because an interrupt can only be generated by a write to this register which then causes an interrupt to take place on the other side of the link if the interrupt is enabled One type of protocol is to store data first in registers 1 and 2 and then as the last step store to register 0 Then 24 bits of data will be available to the interrupt routine on the other side of the link Bulk data transfers across the link can take place by an interrupt for each byte transferred similar to a typical serial port or UART In this case a full duplex transfer can take place similar to what can be done with a UART The overhead for such an interrupt driven trans fer will be on the order of 100 clocks per byte transfer
213. el Port A register which will have a spurious effect on the operation of the Rabbit 3000 chip User s Manual 141 The functionality of the Parallel Port F pins is not affected for pulse width modulation out puts and serial clock outputs except that the Parallel Port F function and direction regis ters should be set up before a conflicting function on Parallel Port A is in use since writing to these registers also writes to the Parallel Port A output register 9 6 1 1 Summary Parallel Port A Parallel Port F e Parallel Inputs e Full Functionality e Parallel Outputs e Parallel Inputs PWM Serial Port Clocks e Slave Port e Parallel Inputs PWM Serial Port Clocks e Auxiliary I O Bus e Full Functionality e If you enable the auxiliary I O bus which uses Parallel Port A then the bug does not manifest itself and you can use the full functionality of Parallel Port F e If you use Parallel Port A as inputs then the bug does not manifest itself and the full functionality of Parallel Port F is available e f you use Parallel Port A as outputs then you cannot use Parallel Port F pins as outputs too except that you can use the PWM and clock outputs provided that you are aware that writing to the control registers of Parallel Port F will also write to the data output register of Parallel Port A A simple way to resolve this is to leave Parallel Port A as an input until you complete the setup of Parallel Port F and t
214. emory Bank 0 Control Register MBOCR 0x0014 W 00001000 Memory Bank 1 Control Register MBICR 0x0015 W XXXXXXXX Memory Bank 2 Control Register MB2CR 0x0016 W XXXXXXXX Memory Bank 3 Control Register MB3CR 0x0017 W XXXXXXXX MMU Expanded Code Register MECR 0x0018 R W 00000000 Memory Timing Control Register MTCR 0x0019 W 00000000 Breakpoint Debug Control Register BDCR 0x001C W 00000000 RAM Segment Register RAMSR 0x0448 W 00000000 Write Protect Control Register WPCR 0x0440 W 00000000 Stack Limit Control Register STKCR 0x0444 W 00000000 Stack Low Limit Register STKLLR 0x0445 W XXXXXXXX Stack High Limit Register STKHLR 0x0446 W XXXXXXXX Write Protect Low Register WPLR 0x0460 W 00000000 Write Protect High Register WPHR 0x0461 W 00000000 Write Protect Segment A Register WPSAR 0x0480 W 00000000 Write Protect Segment A Low Register WPSALR 0x0481 W 00000000 Write Protect Segment A High Register WPSAHR 0x0482 W 00000000 Write Protect Segment B Register WPSBR 0x0484 W 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Parallel Port A User Enable Register PAUER 0x0330 W 00000000 Parallel Port F User Enable Register PFUER 0x0338 W 00000000 Parallel Port B User Enable Register PBUER 0x0340 W 00000000 Parallel Port G User Enable Register PGUER 0x0348 W 00000000 Parallel Port
215. ents in 1 and 2 above All of the above currents can be combined according to the following formula mA 0 32 x V x f 0 23 x Ve x f 0 30 x Vc 0 029 x V x fc 0 025 x Vc x fc where V the operating voltage of the Rabbit 3000 V V x V 2 0 7 f frequency of crystal oscillator in MHz and f clock frequency in MHz 232 Rabbit 3000 Microprocessor 16 7 Sleepy Mode Current Consumption In sleepy mode the unit operates from the 32 768 kHz clock which may be divided down to as slow as 2 048 kHz The current consumption is given by HA 0 32 x V x f 0 23 x Vox f 5x Ve where f is in kHz V is the operating voltage and V V x V 2 0 7 Leakage the standby current of the reset generator the current consumption of the oscilla tor and the real time clock and the current consumption of memories must be added to the sleepy mode current consumption Generally the self timed chip select mode is used to reduce memory current consumption User s Manual 233 16 8 Memory Current Consumption Since there are many different memories available let s look at an example using one of the recommended flash and SRAM memories Flash memory SST part SST39LF512020 256K x 8 45 ns access time Standby current nil e Static Current chip select low 3 5 mA 3 3 V e Dynamic Current 7 mA at 14 7 MHz bus speed and 3 3 V The total current is 10 mA at a clock speed of 29 49 MHz or a bus speed of 5
216. equency directly or dividing the frequency by 2 4 6 or by 8 The processor clock can also be driven by the 32 768 kHz real time clock oscilla tor for very low power operation in which case the main oscillator can be shut down under software control 2 2 4 32 768 kHz Oscillator Input The 32 768 kHz oscillator input is designed to accept a 32 768 kHz clock A suggested low power clock circuit using tiny logic parts is documented and low in cost The 32 768 kHz clock is used to drive a battery backable there is a separate power pin internal 48 bit counter that serves as a real time clock RTC The counter can be set and read by software and is intended for keeping the date and time There are enough bits to keep the date for more than 100 years The 32 768 kHz oscillator input is also used to drive the watchdog timer and to generate the baud clock for Serial Port A during the cold boot sequence 12 Rabbit 3000 Microprocessor 2 2 5 Parallel I O There are 56 parallel input output lines divided among seven 8 bit ports designated A through G Most of the port lines have alternate functions such as serial data or chip select strobes Parallel Ports D E F and G have the capability of timer synchronized outputs The output registers are cascaded as shown in Figure 2 1 Load Data Output Port Load Clock gt Timer Clock Figure 2 1 Cascaded Output Registers for Parallel Ports D and E Sto
217. er is built into the Rabbit 3000 that may be used to implement the main processor oscillator Figure 7 1 For lowest power an external oscillator may be substi tuted for the built in oscillator circuit An oscillator implemented using the built in buffer accepts crystals up to a frequency of 27 MHz first overtone crystals only This frequency may be then doubled by the clock doubler The component values shown in the figure for the oscillator circuits are subject to adjustment depending on the crystal used and the oper ating frequency The Rabbit 3000 has a spectrum spreader unit that modifies the clock by shortening and lengthening clock cycles The effect of this is to spread the spectral energy of the clock harmonics over a fairly wide range of frequencies This limits the peak energy of the har monics and reduces EMI that may interfere with other devices as well as reducing the readings in government mandated EMI tests The spectrum spreader has two operating modes normal spreading and strong spreading The spreader can also be turned off 80 Rabbit 3000 Microprocessor 32 768 kHz Clock The 32 768 kHz clock is primarily used to clock the on chip real time clock In addition it is also used to support remote cold boot via Serial Port A driving the 2400 baud commu nications used to initiate the cold boot Another function of the 32 768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce p
218. er must set the receive code for the first byte and then store the receive code for the next byte after each byte is removed from the data register Since the receive code must be stored before the transmitter sends the next byte the receiver must service the interrupt within 1 2 baud clock to maintain full speed transmission This is usually not practical unless a flow control arrangement is made or the transmitter inserts gaps between the clock bursts In order to carry on high speed communication the best arrangement will usually be for the receiver to provide the clock When the receiver provides the clock the transmitter should always be able to keep up because it is double buffered and has a full character time to answer the transmitter data register empty interrupt The receiver will answer interrupts that are generated on the last clock rising edge If the interrupt can be serviced within 1 2 clock there will be no pause in the data rate If it takes the receiver longer to answer then there will be a gap between bytes the length of which depends on the inter rupt latency For example if the baud rate is 400 000 bps then up to 50 000 bytes per sec ond could be transmitted or a byte every 20 us No data will be lost if the transmitter can User s Manual 183 answer its interrupts within 20 us There will be no slow down if the receiver can answer its interrupt within 1 2 clock or 1 25 us If it can answer within 1 5 clocks or 2 75 us
219. erations removing some of this weakness The basic Z80 7180 16 bit arithmetic instructions are ADD HL ww where ww is HL DE BC SP ADC HL ww ADD and ADD carry SBC HL ww sub and sub carry INC ww increment the register without affecting flags In the above op codes IX or IY can be substituted for HL The ADD and ADC instructions can be used to left shift HL with the carry An alternate destination prefix AL TD may be used on the above instructions This causes the result and its flags to be stored in the corre sponding alternate register If the AL TD flag is used when IX or IY is the destination regis ter then only the flags are stored in the alternate flag register The following new instructions have been added for the Rabbit Shifts RR HL rotate HL right with carry 1 byte 2 clocks note use ADC HL HL for left rotate or add HL HL if no carry in is needed RR DE 1 byte 2 clocks RL DE rotate DE left with carry 1 byte 2 clocks RR IX rotate IX right with carry 2 bytes 4 clocks RR IY rotate IY right with carry Logical Operations AND HL DE 1 byte 2 clocks AND IX DE 2 bytes 4 clocks AND IY DE OR HL DE 1 byte 2 clocks OR IX DE 2 bytes 4 clocks OR IY DE 36 Rabbit 3000 Microprocessor The BOOL instruction is a special instruction designed to help test the HL register BOOL sets HL to the value 1 if HL is non zero otherwise if HL is zero its value is not changed The flags a
220. erial Port E Long Stop Register SELR 0x00CA W XXXXXXXX Serial Port E Status Register SESR 0 00 R 0xx00000 Serial Port E Control Register SECR 0x00CC w xx000000 Serial Port E Extended Register SEER 0x00CD W 00000000 Serial Port F Data Register SFDR 0x00D8 R W XXXXXXXX Serial Port F Address Register SFAR 0x00D9 W XXXXXXXX Serial Port F Long Stop Register SFLR 0x00DA w XXXXXXXX Serial Port F Status Register SFSR 0x00DB R 0xx00000 Serial Port F Control Register SFCR 0x00DC w xx000000 Serial Port F Extended Register SFER 0x00DD W 00000000 User s Manual 333 334 Rabbit 3000 Microprocessor TO USERS RABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COM PONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS UNLESS A SPECIFIC WRITTEN AGREE MENT REGARDING SUCH INTENDED USE IS ENTERED INTO BETWEEN THE CUSTOMER AND RABBIT SEMICONDUCTOR PRIOR TO USE Life support devices or systems are devices or systems intended for surgical implantation into the body or to sustain life and whose failure to perform when prop erly used in accordance with instructions for use provided in the labeling and user s manual can be reason ably expected to result in significant injury No complex software or hardware system is perfect Bugs are always present in a system of any size In order to prevent danger to life or property it is the responsibility of the system designer to incorporate redundant protective mechanisms appropriate to the risk invol
221. es Priority 3 system mode IDET opcode has no effect rere violation interrupt No write protection when 0x00 is written to Write to protected segment causes Priority 3 WPCR write protection in User mode only write protection violation interrupt Difficult to enter system mode requires Easy to enter user mode SETUSR opcode interrupt SYSCALL or RST opcode The main intent of the System User mode is to protect critical code for example code that performs remote firmware updates data and the current processor state memory setup peripheral control etc from inadvertent changes by the user s standard code By remov ing access to the processor s I O registers and preventing memory writes to critical regions the user s code can run without the danger of locking up the processor to the point where it cannot be restarted remotely and or new code uploaded User s Manual 317 C 1 System User Mode Opcodes Seven new opcodes have been added to support the System User mode and are listed in Table C 2 All but IDET are placed in previously empty opcode table assignments IDET shares the value of LD E E in the opcode table and will perform that operation when the System User mode is disabled or when it is enabled and in the System mode In addition if the ALTD prefix appears before the opcode LD E E is always executed instead The processor keeps a one byte stack called the SU register
222. esirable to use up an external interrupt for this purpose The serial port may be used if desired During program load because there is no conflict with the user s program at compile load time However the user s program will conflict during debugging The nature of the transmissions during debugging is such that the user program starts at a break point or otherwise wants to get the attention of the PC The other type of message is when the PC wants to read or write target memory while the target is running The target toggling the clock can simply send a clocked serial message to get the attention of the PC The intermediate communications board can accept these unsolicited messages using its clocked serial port To prevent overrunning the receiver the target can wait for a handshake signal on one of the SMODE lines or there can be suitable pre arranged delays If the PC wants attention from the target it can set a line to request attention SMODE The target will detect this line in the periodic interrupt routine and handle the complete message in the periodic interrupt routine This may slow down target execution but the interrupts will be enabled on the target while the message is read The intermediate board could split long messages into a series of shorter messages if this is a problem A 3 Suggested Rabbit Crystal Frequencies Table A 1 provides a list of suggested Rabbit operating frequencies The numbers in Table A 1 are based on the fo
223. ets Timer Output Setup Register Figure 4 1 Timed Output Pulses The timer output in Figure 4 1 is periodic As long as the interrupt routine can be com pleted during one timer period an arbitrary pattern of synchronous pulses can be output from the parallel port The interrupt latency depends on the priority of the interrupt and the amount of time that other interrupt routines of the same or higher priority inhibit interrupts The first instruc tion of the interrupt routine will start executing within 30 clocks of the interrupt request for the highest priority interrupt routine This includes 19 clocks for the longest instruction to complete execution and 10 clocks for the interrupt to execute Pushing registers requires 10 12 clocks per 16 bit register Popping registers requires 7 9 clocks Return from inter rupt requires 7 clocks If three registers are saved and restored and 20 instructions averag ing 5 clocks are executed an entire interrupt routine will require about 200 clocks or 10 us with a 20 MHz clock Given this timing the following capabilities become possible User s Manual 49 Pulse width modulated outputs The minimum pulse width is 10 us If the repetition rate is 10 ms then a new pulse with 1000 different widths can be generated at the rate of 100 times per second Asynchronous communications serial output Asynchronous output data can be gener ated with a new pulse every 10 us Th
224. fast responses or may be compute intensive e Graphics Controller The Rabbit can be used to perform operations such as drawing geometric figures and generating characters e Digital Signal Processing Although the Rabbit is not a speciality digital signal pro cessor it has enough compute speed to handle some types of jobs that might otherwise 206 Rabbit 3000 Microprocessor require a speciality processor The slave processor can process data to perform pattern recognition or to extract a specific parameter from a data stream 13 3 2 Master Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message The protocol can be polled or interrupt driven Generally the master sends a message that has a message type code perhaps a byte count and the text of the message The slave responds with a similar message as an acknowledgement Nothing happens unless the master sends a message The slave is not allowed to initiate a message but the slave could signal the master by using a parallel port line other than SLAVEATN or by placing data in one of the registers the master can read without interfering with the mes sage protocol The master sends a message byte by storing itin SPDOR The slave notices that SPDOR is full and reads the byte When the master notices that SPDOR is empty because the slave read it the master stores the next byte in SPDOR Either side can tell if any regis
225. fer was not overrun 5 This bit is set if the receiver is overrun This happens if the shift register and the data 1 register are full and a start bit is detected This bit is cleared when the receiver data register is read 4 0 This bit is always zero in async mode 0 The transmit buffer is empty Transmitter data buffer full This bit is set when the transmit data register is full that is a byte is written to the serial port data register It is cleared when a byte is 3 transferred to the transmitter shift register or FIFO or a write operation is 1 performed to the serial port status register This bit will request an interrupt on the transition from 1 to 0 if interrupts are enabled Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignored is written to this register 0 The transmitter is idle Transmitter busy bit This bit is set if the transmitter shift register is busy sending data It is set on the falling edge of the start bit which is also the clock edge that 2 transfers data from the transmitter data register to the transmitter shift register 1 The transmitter busy bit is cleared at the end of the stop bit of the character sent This bit will cause an interrupt to be latched when it goes from busy to not busy status after the last character has been sent there are no more data in the transmitter data register 1 0 00 These bits are always zero in a
226. for either of the two channels A 16 bit counter is used to record the time at which the event takes place The counter is driven by the output of Timer and can be set to count at a rate ranging from full clock speed to 1 256 the clock speed Two events are recognized a start condition and a stop condition The start condition may be used to start counting and the stop condition to stop counting However the counter may also run continuously or run until a stop condition is encountered The start and stop conditions may also be used to latch the current time at the instant the condition occurs rather than actually start or stop the counter The same pin may be used to detect the start 16 Rabbit 3000 Microprocessor and stop condition for example a rising edge could be the start condition and a falling edge the stop condition However optionally the start and stop condition can be input from separate pins The input capture channels can be used to measure the width of fast pulses This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse In this case the maximum error in the measurement is approxi mately 2 periods of the clock used to count the counter If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on either start or stop conditions or both and cause an interrupt each time the count is c
227. g speeds from the same crystal frequency In addition the 32 768 kHz oscillator the drives the bat tery backable clock can be used as the main processor clock and to save the substantial power consumed by the fast oscillator the fast oscillator can be turned off This scenario is called the sleepy mode with a clock speed in the range of 2 kHz to 32 kHz and with an operating system current consumption in the range of 10 to 120 uA depending on fre quency and voltage Up to an operating speed of 29 5 MHz a SST39LF512020 256K x 8 45 ns access time flash memory combined with any of several 55 ns low power SRAMs is assumed for cal culating the current consumption estimates below A crystal frequency of 3 6864 MHz is a good choice for a low power system consuming between 2 and 18 mA at 3 3 V as the clock frequency is throttled between 0 46 MHz and 7 37 MHz The required memory access time is about 250 ns however a faster memory may result in less power since a short chip select cycle can then be used A crystal frequency of 11 0592 MHz is a good choice for a medium power system con suming between 5 and 50 mA at 3 3 V as the clock frequency is throttled between 1 4 MHz and 22 MHz The required memory access time is 70 ns A crystal frequency of 14 7456 MHz is a good choice for a faster medium power system consuming between 6 and 65 mA at 3 3 V as the clock frequency is throttled between 1 8 and 29 5 MHz The required memory access time is 55 n
228. g the bit to indicate ownership of the resource No interrupt can be allowed between the test of the bit and the setting of the bit as this might allow two different program to both think they own the resource User s Manual 47 3 5 6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or Jump can be made This would be done by the following sequence LD xpc a JP HL In this case A has the new XPC and HL has the new PC This code should normally be executed in the root segment so as not to pull the memory out from under the JP HL instruction A call to a computed address can be performed by the following code A xpc IY address LD A newxpc LD IY newaddress LCALL DOCALL call utility routine in the root The DOCALL routine DOCALL LD xpc a SET xpc JP IY go to the routine 48 Rabbit 3000 Microprocessor 4 RABBIT CAPABILITIES This chapter describes the various capabilities of the Rabbit that may not be obvious from the technical description 4 1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock This is shown in Figure 4 1 Timer Output Parallel Port Output Parallel Port Output Latency Interrupt routine s
229. h Internal Clock Mode 00 12 7 2 Clocked Serial Timing with External Clock In a system where the Rabbit serial clock is generated by an external device the clock sig nal has to be synchronized with the internal peripheral clock perc1k before data can be transmitted or received by the Rabbit Depending on when the external serial clock is gen erated in relation to perc1k it may take anywhere from 2 to 3 clock cycles for the exter nal clock to be synchronized with the internal clock before any data can be transferred Figure 12 7 shows the timing relationship among 1 the external serial clock and data transmit peck 777 072 222 435 SA 2 SN lc we CLKA ext TxA Figure 12 7 Synchronous Serial Data Transmit Timing with External Clock Mode 00 User s Manual 185 Figure 12 8 shows the timing relationship among perc1k the external serial clock and data receive Note that is sampled by the rising edge of 1 peck 2 A f Nf NO CLKA 7 Ext RxA 125023 m Figure 12 8 Synchronous Serial Data Receive Timing with External Clock Mode 00 When clocking the Rabbit externally the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit percik If we sum the maximum number of percik cycles required to perform clock synchroniza tion for each of the re
230. h zone except the first or root zone has a segment register that is added to the 16 bit address within the zone to create a 20 bit address The segment register has eight bits and those eight bits are added to the upper four bits of the 16 bit address creating a 20 bit address Thus each separate zone in the 16 bit memory becomes a window to a segment of memory in the 20 bit address space The relative size of the four segments in the 16 bit space is controlled by the SEGSIZE register This is an 8 bit register that contains two 4 bit registers This controls the bound ary between the first and the second segment and the boundary between the second and the third segment The location of the two movable segment boundaries is determined by a 4 bit value that specifies the upper four bits of the address where the boundary is located These relationships are illustrated in Figure 3 3 User s Manual 23 XPC register STACKSEG register DATASEG register XPC segment stack segment data segment D SEGSIZE register root segment 16 bit address space 20 bit address space Figure 3 3 Example of Memory Mapping Operation The names given to the segments in the figure are evocative of the common uses for each segment The root segment is mapped to the base of flash memory and contains the startup code as well as other code that may happen to be stored there T
231. he match register matches the counter a pulse is output Thus the timer can be programmed to output a pulse at a predetermined count in the future This pulse can be used to clock the timer synchronized parallel port output registers as well as cause an interrupt Timer B is convenient for creating an event at a precise time in the future under program control Figure 2 4 illustrates the Rabbit timers User s Manual 15 Timer A System Serial E Serial F Serial Serial B Input Capture Serial C PWM Quadrature Decode Serial D Timer A1 perclk 2 pu 10 bit counter erclk 8 compare E lt q 10 bits gt Timer B1 match reg Timer B System Control Timer Synchronized outputs match preload Timer_B2 v reg match preload Figure 2 4 Rabbit Timers A and 2 2 9 Input Capture Channels The input capture channels are used to determine the time at which an event takes place An event is signaled by a rising or falling edge or optionally by either edge on one of 16 input pins that can be selected as input
232. he BIOS The BIOS provided with Dynamic C will work with all Z World and Rabbit Semiconduc tor Rabbit board products The BIOS is compiled separately from the user s application It occupies space at the bot tom of the root code segment When execution of the user s program starts at address zero on power up or reset it starts in the BIOS When Dynamic C cold boots the target and downloads the binary image of the BIOS the BIOS symbol table is retained to make its entry points and global data available to the user application Board specific drivers are compiled with the user s program after the BIOS is compiled 17 1 1 BIOS Services The BIOS includes support for the following services e System startup including setup of memory wait states and clock speed e Writing to flash Writes to the primary code memory require turning off interrupts for up to 20 ms or so To protect the System Identification Block see the Rabbit 3000 Designer s Handbook for more information on the System ID Block the flash driver will not write to that block A routine that can actually write this block is not included in the BIOS to make it hard to accidently corrupt this block e Run time exception handling and logging to handle fatal errors and watchdog time outs error logging not implemented in older versions e Debugging and PC target communication User s Manual 237 17 1 2 BIOS Assumptions The BIOS makes certain assumptions concerning the physic
233. he Dynamic C debugging monitor needs to keep a small number of constants and variable in data space and it needs to be able to access these regardless of the state of the user program The Dynamic C debugger vari ables are kept at the top of the data segment starting at 52k and working down in memory The user program variables are allocated by the compiler starting just below the Dynamic C debugger data The Dynamic C constants start at address zero User constants are allo cated stating at a low address just above the Dynamic C constants 126 Rabbit 3000 Microprocessor 8 8 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants It allocates space for data variables but does not generate data bits to be stored in memory In any but the smallest programs most of the code is compiled to extended memory This code executes in the 8K window from E000 to FFFF This 8K window uses paged access Instructions that use 16 bit addressing can Jump within the page and also outside of the page to the remainder of the 64K space Special instructions particularly long call long jump and long return are used to access code outside of the 8K window When one of these transfer of control instructions is executed both the address and the view through the 8K window or page are changed This allows transfer to any instruction in the IM memory space The 8 bit XPC register
234. he Z180 not only does the Rabbit require fewer clocks but in a typical situ ation it has a higher clock speed and its instructions are more powerful The most important instruction set improvements in the Rabbit over the Z180 are in the following areas e Fetching and storing data especially 16 bit words relative to the stack pointer or the index registers IX IY and HL e 16 bit arithmetic and logical operations including 16 bit and s or s shifts and 16 bit multiply e Communication between the regular and alternate registers and between the index reg isters and the regular registers is greatly facilitated by new instructions In the Z180 the alternate register set 1s difficult to use while in the Rabbit it is well integrated with the regular register set e Long calls long returns and long jumps facilitate the use of of code space This removes the need in the Z180 to utilize inefficient memory banking schemes for larger programs that exceed 64K of code 32 Rabbit 3000 Microprocessor e Input output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access to an I O space There are two I O spaces internal peripherals and external I O devices Some 780 and 7180 instructions have been deleted and are not supported by the Rabbit see Chapter 20 Differences Rabbit vs Z80 Z180 Instructions Most of the deleted instructions are obsolete or are little used i
235. he chip Table 7 2 Global RAM Configuration Register Global RAM Configuration Register GRAM Address 0x2D Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 RAM identifier for this version of the chip User s Manual 79 Table 7 3 Global CPU Register Global CPU Register GCPU Address 0x2E Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00001 CPU identifier for this version of the chip Table 7 4 Global Revision Register Global Revision Register GREV Address 0x2F Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 Revision identifier for this version of the chip 7 2 Rabbit Oscillators and Clocks The Rabbit 3000 usually requires two separate clocks The main clock normally drives the processor core and most of the peripheral devices and the 32 768 kHz clock drives the battery backable time date clock and other circuitry Main Clock An oscillator buff
236. he data segment usage varies depending on the overall strategy for setting up memory It may be an extension of 24 Rabbit 3000 Microprocessor the root segment or it may contain data variables The stack segment is normally 4K long and it holds the system stack The XPC segment is normally used to execute code that is not stored in the root segment or the data segment Special instructions support executing code that is visible in the XPC segment The memory interface unit receives the 20 bit addresses generated by the memory map ping unit The memory interface unit conditionally modifies address lines A16 A18 and A19 The other address lines of the 20 bit address are passed unconditionally The mem ory interface unit provides control signals for external memory chips These interface sig nals are chip selects CSO CS1 CS2 output enables OEO OE1 and write enables WEO WE1 These signals correspond to the normal control lines found on static mem ory chips chip select or CS output enable or OE and write enable or WE In order to generate these memory control signals the 20 bit address space is divided into four quad rants of 256K each A bank control register for each quadrant determines which of the chip selects and which pair of output enables and write enables if any is enabled when a memory read or write to that quadrant takes place For example if a 512K x 8 flash mem ory is to be accessed in the first 512K of
237. he stack pointer LD SP IY LD SP IX The instructions to load the stack are privileged so that they can be followed by an instruc tion to load the stack segment SSEG register without the danger of an interrupt taking place with and incorrect association between the stack pointer and the stack segment reg ister For example LD SP HL LD STACKSEG A The following instructions are privileged IPSET 0 Shift IP left and set priority 00 in bits 1 0 IPSET 1 IPSET 2 IPSET 3 IPRES rotate IP right 2 bits restoring previous priority POP IP pop IP register from stack The instructions to modify the IP register are privileged so that they can be followed by a return instructions that is guaranteed to execute before another interrupt takes place This avoids the possibility of an ever growing stack RETI pops IP from stack and then pops return address The instruction reti can be used to set both the return address and the IP in a single instruction If preceded by a LD XPC a complete jump or call to a computed address can be done with no possible interrupt LD A XPC get and set the XPC LD XPC A The instruction LD XPC A is privileged so that it can be followed by other code setting interrupt priority or program counter without an intervening interrupt BIT B HL test a bit in memory The instruction bit B HL is privileged to make it possible to implement a semaphore without disabling interrupts The following se
238. he stop bit the transmitter does not become idle The transmitter becomes idle only if the data register is empty at the trailing edge of the stop bit The serial port interrupt vectors are shown in Table 6 1 User s Manual 179 12 4 Transmit Serial Data Timing On transmit if the interrupts are enabled an interrupt is requested when the transmit regis ter becomes empty and in addition an interrupt occurs when the shift register and trans mit register both become empty that is when the transmitter becomes idle The shift register is empty when the last bit is shifted out When the transmit data register contains data and the shift register finishes sending data the data bits are clocked from the transmit register to the shift register and the shift register is never idle The interrupt request is cleared either by writing to the data register or by writing to the status register which does not affect the status register The data register normally is clocked into the shift register each time the shift register finishes sending data leaving the data register empty This causes an interrupt request The interrupt routine normally answers the interrupt before the shift register runs dry 9 to 11 baud clocks depending on the mode of operation The interrupt routine stores the next data item in the data register clearing the interrupt request and supplying the next data bits to be sent When all the characters have been sent the interr
239. hen switch Parallel Port A to be an output You can always use pins on Parallel Port F as inputs e f you enable the slave port then you cannot use Parallel Port F as parallel outputs but you can still use the other output functions of Parallel Port F following the precautions regarding setup described above The easiest approach to avoid any problem when there is a conflict is to assign inputs and outputs in such a manner as to avoid the bug Either Parallel Port A can be used as inputs in which case Parallel Port F has full function or if Parallel Port cannot be used as inputs use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled 142 Rabbit 3000 Microprocessor 9 7 Parallel Port G Parallel Port G is a byte wide port with each bit programmable for data direction and drive These are simple inputs and outputs controlled and reported in the Port G Data Reg ister As outputs the bits of the port are buffered with the data written to the Port G Data Register transferred to the output pins on a selected timing edge The outputs of Timer A1 Timer B1 or Timer B2 can be used for this function with each nibble of the port having a separate select field to control this timing These inputs and outputs are also used for access to other peripherals on the chip As out puts Port G can carr
240. hough Parity and multiple stop bits are not directly supported by the hardware the 9th bit can be used to issue an extra stop bit 9th bit high or toggled to indicate parity User s Manual 163 12 1 Serial Port Register Layout Figure 12 2 shows a functional block diagram of a serial port Each serial port has a data register a control register and a status register Writing to the data register starts transmis sion The least significant bit LSB is always transmitted first This is true for both asyc nchronous and synchronous communication If the write is performed to an alternate data register address the extra address bit or 9th bit 8th bit if 7 data bits is sent When data bits have been received they are read from the data register LSB first The control regis ter is used to set the transmit and receive parameters The status register may be tested to check on the operation of the serial port long stop register Read Data Write Data Data Reg 9th bit m bit Data Out Reg Zero ne alternate data out registe fifo ports E F only l 4 bytes deep fifo ports E F only 4 bytes deep address register Input Shift Reg output shift reg Rx serial data in LSB First Tx serial data out LSB First Bit O stop Tx Transmitting 0x0D6 Start Bit Stop Bit stop Tr
241. ia two select lines that form the register address and a read strobe that causes the register contents to be output by the port These same registers can be written as I O registers by the Rabbit slave Three additional registers transmit data in the opposite direction They are written by the master by means of the two select lines and a write strobe Figure 2 3 shows the data paths in the slave port Rabbit 3000 Master Processor Input Register Output Registers Control lt Slave Interface Registers Figure 2 3 Slave Port Data Paths The slave Rabbit can read the same registers as I O registers When incoming data bits are written into one of the registers status bits indicate which registers have been written and an optional interrupt can be programmed to take place when the write occurs When the slave writes to one of the registers carrying data bits outward an attention line is enabled so that the master can detect the data change and be interrupted if desired One line tells the master that the slave has read all the incoming data Another line tells the master that new outgoing data bits are available and have not yet been read by the master The slave port can be used to signal the master to perform tasks using a variety of communication protocols over the slave port 14 Rabbit 3000 Microprocessor 2 2 7 Auxiliary 1
242. ict with the requirements of the fast mem ory bus Further described below Hardware design is simple Up to six static memory chips such as RAM and flash memory connect directly to the microprocessor with no glue logic A memory access time of 55 ns suffices to support up to a 30 MHz clock with no wait states with a 30 ns memory access time a clock speed of up to 50 MHz is possible with no wait states Most I O devices may be connected without glue logic The memory read cycle is two clocks long The write cycle is 3 clocks long A clean memory and I O cycle completely avoid the possibility of bus fights Peripheral I O devices can usually be interfaced in a glueless fashion using the common IORD and IOWR strobes in addition to the user configurable IO strobes on Parallel Port E The Parallel Port E pins can be configured as I O read write read write or chip select when they are used as I O strobes EMI reduction features reduce EMI levels by as much as 25 dB compared to other sim ilar microprocessors Separate power pins for the on chip I O buffers prevent high fre quency noise generated in the processor core from propagating to the signal output pins A built in clock spectrum spreader reduces electromagnetic interference and facil itates passing EMI tests to prove compliance with government regulatory requirements As a consequence the designer of a Rabbit 3000 based system can be assured of pass ing FCC or CE EMI tests as long as
243. ide periodic interrupts every 488 us Typical battery current consumption is about 3 uA Numerous timers and counters can be used to generate interrupts baud rate clocks and timing for pulse generation Two input capture channels can be used to measure the width of pulses or to record the times at which a series of events take place Each capture channel has a 16 bit counter and can take input from one or two pins selected from any of 16 pins Two quadrature decoder units accept input from incremental optical shaft encoders These units can be used to track the motion of a rotating shaft or similar device User s Manual e A built in clock doubler allows 1 frequency crystals to be used e The built in main clock oscillator uses an external crystal or a ceramic resonator Typical crystal or resonator frequencies are in the range of 1 8 MHz to 30 MHz Since precision timing is available from the separate 32 768 kHz oscillator a low cost ceramic resonator with 1 2 percent error is generally satisfactory The clock can be doubled or divided down to modify speed and power dynamically The I O clock which clocks the serial ports is divided separately so as not to affect baud rates and timers when the processor clock is divided or multiplied For ultra low power operation the processor clock can be driven from the separate 32 768 kHz oscillator and the main oscillator can be powered down This allows the processor to operate at approximate
244. igh impedance during reset and during power down when only VBAT is pow ered to allow an external RAM connected to CS1 to be powered by VBAT This is possi ble because the CS1 pin is powered by VBAT In this case an external pull up resistor to VBAT is required on CS1 to keep the RAM deselected during power down If the exter nal RAM connected to CS1 is not powered by VBAT so that any information held within it is lost during power down no pull up resistor on CS1 is appropriate as this would add leakage through the protection diode to drain VBAT The RESOUT signal which is High during reset and power down can be used to control an external power switch to dis connect VDD from supplying VBAT The default selection for the memory control signals consists of CSO and OEO and writes are disabled This selection can also be immediately programmed to match the hardware configuration A typical sequence would be to speed up the clock to full speed followed by selection of the appropriate number of wait states and the chip select signals output enable signals and write enable signals At this point software would usually check the system status to determine what type of reset just occurred and begin normal opera tion The default values for all of the peripheral control registers are shown with the following register listing The registers within the CPU affected by reset are the Stack Pointer SP the Program Counter PC the IIR regi
245. ility to shorten a read strobe by one clock and the ability to direct a strobe to either the alternate I O bus Gf enabled or the memory bus The new control bits for the external I O strobes are listed in Table B 21 NOTE Bits 1 0 were always written with zero in the original Rabbit 3000 chip Table 21 I O Bank x Control Register 10 Bank x Control Register IBOCR Address 0x0080 IB1CR Address 0x0081 IB2CR Address 0x0082 IB3CR Address 0x0083 IB4CR Address 0x0084 IB5CR Address 0x0085 IB6CR Address 0x0086 IB7CR Address 0x0087 Bit s Value Description 7 6 00 Fifteen wait states for accesses in this bank 01 Seven walt states for accesses in this bank 10 Three wait states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The Ix signal is an chip select 01 The Ix signal is an I O read strobe 10 The Ix signal is an I O write strobe 11 The Ix signal is an I O data read or write strobe 0 Writes are not allowed to this bank Transactions are normal in every other way 3 only the write strobe is inhibited 1 Writes are allowed to this bank 0 Active Low Ix signal 2 1 Inverted active High Ix 0 Normal I O Transaction timing 1 1 Shorten read strobe by one clock cycle Transaction length remains the same 0 Use I O bus if enabled 0 1 Always use memory data bus 296 Rabbit 3000 Micro
246. imer A clock 1 Timer A2 clocked by the output of Timer 1 00 Timer interrupts are disabled 01 Timer A interrupts use Interrupt Priority 1 m 10 Timer A interrupts use Interrupt Priority 2 11 Timer interrupts use Interrupt Priority 3 The Timer A Prescale Register TAPR specifies the main clock for Timer A This will affect all of the timer countdown timers By default Timer 15 clocked by peripheral clock divided by two The prescale register TAPR is laid out as shown in Table 11 5 Table 11 5 Timer A Prescale Register Timer A Prescale Register TAPR Address 0x00A1 Bit s Value Description 7 1 These bits ignored 0 The main clock for Timer is the peripheral clock 1 The main clock for Timer is the peripheral clock divided by two 154 Rabbit 3000 Microprocessor The time constant register for each timer TATxR is simply an 8 bit data register holding a number between 0 and 255 This time constant will take effect the next time that the Timer A counter counts down to zero The timer counts modulo divide by n 1 where n is the programmed time constant The time constant registers are write only The time constant registers are listed in Table 11 1 11 1 2 Practical Use of Timer A Timer A is disabled bit O in control and status register on power up Timer A is normally set up while the clock is disabled but the timer setup can be changed while the
247. imes with clock Parallel Port E 137 registers isses 21 doubler 221 Parallel Port F 140 accumulators 22 allocation of extended code Parallel Port G 143 alternate registers 22 and data space 123 pin descriptions 62 123 breakpoint debug control alternate functions 65 clocked serial port status ler 123 pinout registers ooo 171 compiler operation 127 BGA package 59 default values 73 data and clock delays 216 LQFP package 56 GODR 83 I and D space 125 ports 213 319 access time 223 Rabbit slave port 199 80 282 319 I O read time delays 224 slave port lines 203 GES nuyu 82 write time delays 224 slave port registers 204 iere ets 90 instruction and data space power consumption 85 229 88 297 SUPPORT s 25 CLOCK A 235 236 GRAM configuration 79 power consumption Dynamic 241 GREV 80 282 read 5 cycles d mechanisms 232 GROM configuration 79 states memory 234 At 298 read time delays 2
248. in Dynamic C access the HTML Function Reference or Function Lookup options To read internal I O registers there are two functions int RdPortI int PORT returns PORT high byte zero int BitRdPortI int PORT int bitcode bit code 0 7 To write internal I O registers there are two functions void WrPortI int PORT char PORTShadow int value void BitWrPortI int PORT char PORTShadow int value int bitcode The external registers are also accessible with Dynamic C functions int RdPortE int PORT returns PORT high byte zero int BitRdPortE int PORT int bitcode bit code 0 7 int WrPortE int PORT char PORTShadow int value int BitWrPortE int PORT char PORTShadow int value int bitcode In order to read a port the following code could be used k RdPortI PADR returns Port A Data Register 242 Rabbit 3000 Microprocessor 18 3 Shadow Registers Many of the registers of the Rabbit s internal I O devices are write only This saves gates on the chip making possible greater capability at lower cost Write only registers are eas ier to use if a memory location called a shadow register is associated with each write only register To make shadow register names easy to remember the word shadow is appended to the register name For example the register GOCR Global Output Control register has the shadow GOCRShadow Some shadow registers are defined in the BIOS source code as shown below char GCSR
249. in Table 5 2 The important properties of the ports are summarized below Port A Shared with the slave port data interface and auxiliary I O data bus Port B Shared with control lines for slave port auxiliary I O address bus and clock I O for clocked serial mode option for Serial Ports A and B Port C Shared with serial port data I O Port D 4 bits shared with alternate I O pins for Serial Ports A and B 4 bits not shared Port D can be configured as open drain outputs Port D also contains output preload registers that can be clocked into the output registers under timer control for pulse gen eration Port bits of Port E can be configured as I O strobes 4 bits of port E can be used as external interrupt inputs One bit of port E is shared with the slave port chip select Port E has output preload registers that can be clocked into the output registers under timer control for pulse generation Port F As outputs Port F can be configured as open drain outputs Alternatively Par allel Port F outputs can carry the four Pulse Width Modulator outputs As inputs Paral lel Port F inputs can carry the inputs to the two channels of the quadrature decoders Port F pins can also be configured to be used as clock pins for clocked Serial Ports C and D Port G As outputs Port G can be configured as open drain outputs Port G inputs and outputs are also used for access to other serial peripherals on the chip such as those us
250. ine s priority return from interrupt 2 etc 100 Rabbit 3000 Microprocessor 7 11 Bootstrap Operation The device provides the option of bootstrap from any of three sources from the Slave Port from Serial Port in clocked serial mode or from Serial Port in asynchronous mode This is controlled by the state of the SMODE pins after reset Bootstrap operation is disabled if SMODEI SMODEO 0 0 Bootstrap operation inhibits the normal fetch of code from memory and instead substi tutes the output of a small internal boot ROM for program fetches This bootstrap program reads groups of three bytes from the selected peripheral device The first byte is the most significant byte of a 16 bit address followed by the least significant byte of a 16 bit address followed by a byte of data The bootstrap program then writes the byte of data to the downloaded address and jumps back to the start of the bootstrap program The most significant bit of the address is used to determine the destination for the byte of data If this bit is zero the byte is written to the memory location addressed by the downloaded address If this bit is one the byte is written to the internal peripheral addressed by the downloaded address Note that all of the memory control signals continue to operate nor mally during bootstrap Execution of the bootstrap program automatically waits for data to become available from the selected peripheral and each
251. ing the User mode interrupt handler An example of both system and user interrupt handling is shown in Figure C 1 INTERRUPT UNDER SYSTEM CONTROL ISR system Application code user Application code user INTERRUPT UNDER USER CONTROL ISR system Application ISR user Application code user Application code user Figure C 1 Interrupt Handing in System User Mode Some sample code for both System mode interrupts and User mode interrupts is shown below system isr jumped to from interrupt vector table handle interrupt sures reenter previous mode ret user isr jumped to from interrupt vector table push su preserve current SU stack setusr enter user mode handle interrupt pop su restore previous SU stack sures reenter previous mode ret User s Manual 321 C 3 1 Peripheral Interrupt Prioritization Most interrupts can be programmed to occur at any of three priority levels but several are restricted to Level 3 the highest priority only The interrupts restricted to Level 3 are sys tem mode violation stack limit violation write protection violation and the secondary watchdog In addition any interrupt assigned to User mode is prevented by hardware from requesting a Level 3 interrupt If a user assigned interrupt is programmed to occur at Level 3 the hardware will automatically modify the request to occur at Level 2 Within a given interrupt priority level the interrupts are prioritize
252. ing the status of the input buffer because all the interrupts will be completed before the higher level routine can perform a check on the buffer status A typical way to organize the buffers is to have an in pointer and an out pointer that incre ment through the addresses in the data buffer in a circular manner The interrupt routine manipulates the in pointer and the higher level routine manipulates the out pointer If the in pointer equals the out pointer the buffer is considered full If the out pointer plus 1 equals the in pointer the buffer is empty All increments are done in a circular fashion most easily accomplished by making the buffer a power of two in length then anding a mask after the increment The actual memory address is the pointer plus a buffer base address 12 9 1 Controlling an RS 485 Driver and Receiver RS 485 uses a half duplex method of communication One station enables its driver and sends a message After the message is complete the station disables the driver and listens to the line for a reply The driver must be enabled before the start bit is sent and not dis abled until the stop bit has been sent The transmitter idle interrupt is normally used to disable the RS 485 driver and possibly enable the receiver 12 9 2 Transmitting Dummy Characters It may be desired to operate the serial transmitter without actually sending any data Dummy characters are transmitted to pass time or to measure time The out
253. intended as a safety net for the peri odic interrupt and would normally be restarted in the service routine for the periodic inter rupt Although the hardware was intended to primarily be used by an operating system when the System User mode is enabled it can be used as a configurable periodic interrupt as well Table B 16 Watchdog Timer Control Register Updated Watchdog Timer Control Register WDTCR Address 0x0008 Bit s Value Description 7 0 Ox5A Restart the watchdog timer with a 2 second time out period 0x57 Restart the watchdog timer with a 1 second time out period 0x59 Restart the watchdog timer with a 500 ms time out period 0x53 Restart the watchdog timer with a 250 ms time out period Ox5F Restart the secondary watchdog timer other No effect on watchdog timer or secondary watchdog timer Table B 17 Secondary Watchdog Timer Register Secondary Watchdog Timer Register SWDTR Address 0x000C Bit s Value Description The time constant for the secondary watchdog timer is stored This time constant will take effect the next time that the secondary watchdog counter counts down 7 0 to zero The timer counts modulo n 1 where n is the programmed time constant The secondary watchdog can be disabled by writing the sequence 0 5 0 52 0 44 to this register 292 Rabbit 3000 Microprocessor B 1 9 New Opcodes Eight new opcodes were added
254. interrupt TKHLR 0xE0 Stack access this 0 000 region triggers interrupt OxDFFO OxDFEF Stack access in this region is allowed OxD810 OxD80F OxD800 Stack access in this region triggers an interrupt TKLLR OxD8 Figure B 2 Simple Stack Protection Lavout User s Manual 289 The stack protection registers are listed in Table B 12 Table B 13 and Table B 14 Table B 12 Stack Limit Control Register Stack Limit Control Register STKCR Address 0x0444 Bit s Value Description 7 1 These bits are reserved and should be written with zeros 0 Disable stack limit checking l 1 Enable stack limit checking Table B 13 Stack Low Limit Register Stack Low Limit Register STKLLR Address 0x0445 Bit s Value Description Lower limit for stack limit checking If a stack operation or stack relative 7 0 memory access is attempted at an address less than STKLLR 0x10 a stack limit violation interrupt is generated Table B 14 Stack High Limit Register Stack High Limit Register STKHLR Address 0x0446 Bit s Value Description Upper limit for stack limit checking If a stack operation or stack relative 7 0 memory access is attempted at an address greater STKHLR OxOEF a stack limit violation interrupt is generated 290 Rabbit 3000 Microprocessor B 1 7 RAM Segment Relocation Normally
255. ions in design and software it is possible to use Serial Port A as both a programming port and as a user defined serial port although this will not be nec essary in most cases Rabbit Semiconductor supports the use of the standard programming port and the standard programming cable as a diagnostic and setup port to diagnosis problems or set up systems in the field 2 3 2 Standard BIOS Rabbit Semiconductor provides a standard BIOS for the Rabbit The BIOS is a software program that manages startup and shutdown and provides basic services for software run ning on the Rabbit 2 4 Dynamic C Support for the Rabbit Dynamic C is Z World s interactive C language development system Dynamic C runs on a PC under Windows 32 bit operating systems Dynamic C provides a combined compiler editor and debugger The usual method for debugging a target system based on the Rabbit is to implement the 10 pin programming connector that connects to the PC serial port via a standard converter cable Dynamic C libraries contain highly perfected software to control the Rabbit These includes drivers utility and math routines and the debugging BIOS for Dynamic C In addition the internationally known real time operating system uC OS II has been ported to the Rabbit and is available with Dynamic C on a license free royalty free basis for use in Rabbit based products User s Manual 19 20 Rabbit 3000 Microprocessor 3 DETAILS ON RABBIT MICROP
256. is automatically inserted by the transmitter and automatically deleted by the receiver This allows a Flag byte 0x07E to be unique within the serial bit stream The standard CRC CCITT polyno 12 mial x 4 x 4 x 1 is implemented with the generator and checker preset to all ones Both receive and transmit operation are essentially automatic In the receiver each byte is marked with status to indicate end of frame short frame and CRC error The receiver automatically synchronizes on Flag bytes and presets the CRC checker appropriately If User s Manual 187 the current receive frame is not needed because it is addressed to a different station for example a Flag Search command is available This command forces the receiver to ignore the incoming data stream until another Flag is received In the transmitter the CRC gener ator is preset and the opening Flag is transmitted automatically after the first byte is writ ten to the transmitter buffer and CRC and the closing flag are transmitted after the byte that is written to the buffer through the Address Register If no CRC is required writing the last byte of the frame to the Long Stop Register automatically appends a closing flag after the last byte If the transmitter underflows either an Abort or a Flag will be transmit ted under program control A command is available to send the Abort pattern seven con secutive ones if a transmit frame needs to be aborted prematurely The A
257. is corresponds to a baud rate of 100 000 bps Asynchronous communications serial input To capture asynchronous serial input the input must be polled faster than the baud rate a minimum of three times faster with five times being better If five times polling is used then asynchronous input at 20 000 bps could be received Generating pulses with precise timing relationships The relationship between two events can be controlled to within 10 us to 20 us Using a timer to generate a periodic clock allows events to be controlled to a precision of approximately 10 us However if Timer B is used to control the output registers a preci sion approximately 100 times better can be achieved This is because Timer B has a match register that can be programmed to generate a pulse at a specified future time The match register has two cascaded registers the match register and the next match register The match register is loaded with the contents of the next match register when a pulse is gener ated This allows events to be very close together one count of Timer B Timer B can be clocked by sysc1k 2 divided by a number in the range of 1 256 Timer B can count as fast as 10 MHz with a 20 MHz system clock allowing events to be separated by as little as 100 ns Timer B and the match registers have 10 bits Using Timer B output pulses can be positioned to an accuracy of c1k 2 Timer B can also be used to capture the time at which an external event t
258. is encountered in the target under test The SMODE pins are pulled up by a 5 3 V level from the interface They should be pulled down on the board when the interface is not in use by approximately 5 kQ resistors to ground The target under test provides the 5 V or 3 V to the interface cable which is used to power the RS 232 driver and receiver PROGRAMMING PORT PIN ASSIGNMENTS Rabbit LOFP pins are shown in parenthesis 50 kO 1m e 1 66 e 2 GND 50 Ale o 3 CKLKA 117 NAAV 4 5 V 3 V Oke EZ d 9 5 AAA 6 TXA 67 MG Programming Port 8 STATUS output 4 Pin Numbers 9 SMODE0 45 NYv GND 10 SMODE1 44 AA A GND Figure A 1 Rabbit Programming Port User s Manual 269 A 1 Use ot the Programming Port as a Diagnostic Setup Port The programming port which is already in place can serve as a convenient communica tions port for field setup diagnosis or other occasional communication need for example as a diagnostic port There are several ways that the port can be automatically integrated into the user s software scheme If the purpose of the port is simply to perform a setup function that 15 write setup information to flash memory then the controller can be reset through the programming port followed by a cold boot to start execution of a special pro gram dedicated to this functi
259. ise that is communicated to the outside of the package via the power pins The I O buffers have slower switching times and mostly operate at much lower frequencies than the core logic The Rabbit has separate power and ground pins for the core and I O ring This allows the designer to feed clean power to the I O ring filtered to be free of the noise generated by the core switching This minimizes high frequency noise that would other wise appear on output pins driven by buffers in the I O ring The result is lower EMI 2 3 Design Standards The same functionality can often be accomplished in more than one way with the Rabbit 3000 By publishing design standards or standard ways to accomplish common objec tives software and hardware support become easier Refer to the Rabbit 3000 Microprocessor Designer s Handbook for additional information 2 3 1 Programming Port Rabbit Semiconductor publishes a specification for a standard programming port see Appendix A The Rabbit Programming Port and provides a converter cable that may be used to connect a PC serial port to the standard programming interface The interface is implemented using a 10 pin connector with two rows of pins on 2 mm centers The port is connected to Rabbit Serial Port A to the startup mode pins on the Rabbit to the Rabbit 18 Rabbit 3000 Microprocessor reset pin and to a programmable output pin that is used to signal the PC that attention is needed With proper precaut
260. ission In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission User s Manual 169 Table 12 11 Status Register Asynchronous Mode Only All Ports Serial Port x Status Register SASR Address 0xC3 SBSR Address 0xD3 SCSR Address 0 SDSR Address 0xF3 SESR Address 0 SFSR Address 0xDB Bit s Value Description Async mode only 0 The receive data register is empty no input character is ready There is a byte in the receive buffer The transition from 0 to 1 sets the 7 receiver interrupt request flip flop The interrupt FF is cleared when the 1 character is read from the data buffer The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer 0 The byte in the receive buffer is data received with a valid Stop bit Address bit or 9th 8th bit received This bit is set if the character in the receiver data register has a 9th 8th bit This bit is cleared and should be checked before 6 reading a data register since a new data value with a new address bit may be 1 loaded immediately when the data register is read The byte in the receive buffer is an address or a byte with a framing error If an address bit is not expected If the data in the buffer is all zeros this may be a Break 0 The receive buf
261. ject to variation arising from process variation operating voltage and temperature Minimum and maximum clock low times for various doubler settings are given in the formulas and in the graph below Max delay 9 3 3 V 26 14 1 21 n 6 nis the nominal delay 6 20 ns Min delay 3 3 V 3 7 0 75 n 6 Max delay 2 5 V 7 6 1 67 n 6 Min delay 2 5 V 4 7 1 03 n 6 Max delay 1 8 V 12 2 2 7 n 6 Min delay 1 8 V 6 6 1 44 n 6 60 0 50 0 40 0 3 3 m 2 5 V A1 8 V 30 0 Delay ns 20 0 10 0 0 0 0 5 10 15 20 25 Nominal Delay ns Figure 16 5 Clock Doubler Max Min Clock Low Times User s Manual 221 The following factors have to be taken into account when calculating the output enable access time required e The gross output enable access time is T minimum clock low time it is assumed that the early output enable option is enabled This is reduced by the spectrum spreader loss the time from clock to output for the output enable signal the data setup time and a correction for the asymmetry of the original oscillator clock Example e Clock 29 49 MHz e T 34ns e operating voltage is 3 3 V e the clock doubler has a nominal delay of 16 ns resulting in a minimum clock low time of 12 8 ns e the spectrum spreader is on in normal mode resulting in a loss of 3 ns e clock to output enable is 5 ns assuming 20 pF load
262. jor problem that the IBM PC uarts can support the 9th bit only by using special drivers 12 9 9 Rabbit Only Master Slave Protocol If only Rabbit microprocessors are connected the 9th bit low can be set on the address byte and the remaining bytes can be transmitted in the normal 8 bit mode This is more efficient than other 9th bit protocols because only the first byte requires 11 baud times the remaining bytes are transmitted in 10 baud times 12 9 10 Data Framing Modbus Some protocols for example Modbus depend on a gap in the data frame to detect the beginning of the next frame The 9th bit protocol is another way to detect the start of a data frame The Modbus protocol requires that data frames begin with a minimum 3 5 character quiet time The receiver uses this 3 5 character gap to detect the start of a frame In order for 196 Rabbit 3000 Microprocessor the receiving interrupt service routine to detect this gap it is suggested that dummy char acters be transmitted to help detect the gap This can be done in the following manner The transmitter starts transmitting dummy characters when the first character interrupt is received Each time there is an interrupt either receiver data register full or transmitter data register empty a dummy character is transmitted if the transmitter data register 15 empty Although the transmitter and receiver operate at approximately the same baud rate there can be a difference of up to about 5
263. k The DPLL is basically just a divide by 16 counter that uses the timing of the transitions on the receive data stream to adjust its count The DPLL adjust the count so that the output of the DPLL will be properly placed in the bit cells to sample the receive data To work properly then transitions are required in the receive data stream NRZ data encoding does not guarantee transitions in all cases a long string of zeros for example but the other data encodings do NRZI guarantees transitions because of the inserted zeros and the Biphase encodings all have at least one transition per bit cell The DPLL counter normally counts by sixteen but if a transition occurs earlier or later than expected the count will be modified during the next count cycle If the transition occurs earlier than expected it means that the bit cell boundaries are early with respect to the DPLL tracked bit cell boundaries so the count is shortened either by one or two counts If the transition occurs later than expected it means that the bit cell boundaries are late with respect to the DPLL tracked bit cell boundaries so the count is lengthened either by one or two counts The decision to adjust by one or by two depends on how far off the DPLL tracked bit cell boundaries are This tracking allows for minor differences in the transmit and receive clock frequencies With NRZ and NRZI data encoding the DPLL counter runs continuously and adjusts after every receive data
264. k Select Field of GCSR Clock Select CPU Clock Peripheral Main 22 Bits 4 2 GCSR Clock Oscillator GPSCR 000 osc 8 osc 8 on short CS option 001 osc 8 osc on short CS option 010 osc osc on none 011 osc 2 osc 2 on short CS option self timed option 100 32 kHz or fraction 32 kHz or fraction on short CS option 1 self timed option 101 32kHzorfraction 32KHz or fraction off l short CS option 110 osc 4 osc 4 on short CS option 111 osc 6 osc 6 on short CS option 298 Rabbit 3000 Microprocessor B 1 12 2 Short Chip Select Timing When short chip selects are enabled for read cycles the chip select signals are active only for the last part of the bus cycle Wait states are inserted between T1 and 2 so this will have no effect on the duration of the chip select signals in this mode The timing diagrams below illustrate the actual timing for the different divided cases In these cases the chip selects are two clock cycles of the fast oscillator long T1 T2 oscillator clock para CSx OEx divide by 8 mode Figure B 3 Short Chip Select Timing CLK 8 Read Operation User s Manual 299 T1 T2 oscillator clock v 21 00 DATA ea CSx OEx divide by 6 mode Figure B 4 Short Chip Select Timing CLK 6 Read Operation oscillator divide by 4 mode Figure B 5 Short Chip Select Timing CLK 4 Read Operation 300 Rabbit 3000 Microp
265. l Driver provides more details on the periodic interrupt The Rabbit 3000 microprocessor requires the 32 kHz oscillator in order to boot via Dynamic C unless a custom loader and BIOS are used 17 2 2 Watchdog Timer Support A microprocessor system can crash for a variety of reasons A software bug or an electri cal upset are common reasons When the system crashes the program will typically settle into an endless loop because parameters that govern looping behavior have been cor rupted Typically the stack becomes corrupted and returns are made to random addresses The usual corrective action taken in response to a crash is to reset the microprocessor and reboot the system The crash can be detected either because an anomaly is detected by pro 238 Rabbit 3000 Microprocessor gram consistency checking or because a part of the program that should be executing peri odically 15 not executing and the watchdog times out The Virtual Driver s periodic interrupt hits the hardware watchdog timer with a 2 second time out If the periodic interrupt stops working then the watchdog will time out after 2 seconds The Virtual Driver provides a number of additional virtual watchdog timers for use in other parts of the code that must be entered periodically The user program must hit each virtual watchdog periodically The best practice is to let the periodic interrupt hit the hardware watchdog exclusively and use virtual watchdogs for other
266. l cause an additional asymmetry between alternate clock cycles The power consumption is proportional to the clock frequency and for this reason power can be reduced by slowing the clock when less computing activity is taking place The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme User s Manual 85 7 4 Clock Spectrum Spreader When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies The spectrum spreader has a normal and a strong setting With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz For lower frequencies the strong spreading has a greater effect in reducing the peak spectral strength as shown in the figure below 154 3 Strong Spreading 10 _ Normal Spreading 50 100 150 200 250 300 350 MHz Figure 7 3 Reduction in Peak Spectral Strength from Spectrum Spreader In the normal spectrum spreading mode the maximum shortening of the clock cycle is 3 nanoseconds at 3 3 V and 25 C In the strong spreading mode the maximum shortening of a clock cycle under the same conditions is 4 5 ns The reduction in peak spectral strength is roughly independent of the clock frequency Special precautions must be follo
267. larity inactive Low Internal or external clock 11 Inverted clocked serial clock polarity inactive High Internal clock only 3 2 XX These bits are ignored in clocked serial mode 0 No effect on transmitter 1 Terminate current clocked serial transmission No effect on buffer 0 No effect on receiver l 1 Terminate current clocked serial reception User s Manual 177 Table 12 19 Extended Register HDLC Mode Ports E and F only Serial Port x Extended Register SEER Address 0xCD SFER Address 0xDD Bit s Value Description HDLC mode only 000 NRZ data encoding for HDLC receiver and transmitter 010 NRZI data encoding for HDLC receiver and transmitter 7 5 100 Biphase Level Manchester data encoding for HDLC receiver and transmitter 110 Biphase Space data encoding for receiver and transmitter 111 Biphase Mark data encoding for HDLC receiver and transmitter 0 Normal HDLC data encoding 4 1 Enable RZI coding 1 4th bit cell IRDA compliant This mode can only be used with internal clock and NRZ data encoding 0 Idle line condition is Flags 1 Idle line condition is all ones 0 Transmit Flag on underrun 1 Transmit Abort on underrun 1 0 xx These bits are ignored in HDLC mode 178 Rabbit 3000 Microprocessor 12 3 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts There is a sepa
268. lected pins of Parallel Ports B and E are used for the Slave Port control signals Only Slave Port Data Register 0 is used for bootstrap operation and any writes to the other data registers will be ignored by the processor and can actually interfere with the bootstrap operation by mask ing the Write Empty signal User s Manual 101 Serial Port 15 selected for bootstrap operation as a clocked serial port when SMODE 10 In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock Note that the serial clock must be externally supplied for boot strap operation This precludes the use of a serial EEPROM for bootstrap operation Serial Port A is selected for bootstrap operation as an asynchronous serial port when SMODE 11 In this case bit 7 of Parallel Port C is used for the serial data and the 32 kHz oscillator is used to provide the serial clock A dedicated divide circuit allows the use of the 32 KHz signal to provide the timing reference for the 2400 bps asynchronous transfer Only 2400 bps is supported for bootstrap operation and the serial data must be eight bits for proper operation In the case of asynchronous bootstrap Serial Port A accepts either regular NRZ data or IrDA encoded data RZI coding with 3 16ths bit cell automatically The hardware contians a monostable multivibrator triggered by the falling edge of serial data into the data path The one shot stretches
269. led 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 32 kHz oscillator divided by two 16 384 kHz 101 32 kHz oscillator divided by four 8 192 kHz 110 32 kHz oscillator divided by eight 4 096 kHz 111 32 kHz oscillator divided by sixteen 2 048 kHz User s Manual 297 B 1 12 1 Clock Select and Power Save Modes Table B 24 outlines the power save modes available in the Rabbit 3000A The GCSR is shown in Table B 23 for reference Table B 23 Global Control Status Register Global Control Status Register GCSR Address 0x00 Bit s Value Description 00 No reset or watchdog timer time out since the last read 01 The watchdog timer timed out These bits are cleared by a read of this 7 6 register rd only 10 This bit combination is not possible 11 Reset occurred These bits are cleared by a read of this register 0 No effect on the periodic interrupt This bit will always be read as zero 5 1 Force a periodic interrupt to be pending 4 2 XXX See table below for decode of this field 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 1 0 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 Table B 24 Cloc
270. lity to write protect 64 KB physical memory blocks was added with the option of further protecting two of the 64 KB blocks in 4 KB segments Attempts to write to a protected block triggers a Priority 3 write protection interrupt c Stack protection was added Writing outside set stack boundaries triggers a Priority 3 stack violation interrupt d RAM segment relocation was added This feature allows a 1 2 or 4 KB segment of the logical memory space to be mapped as data or for program execution when separate I D space is enabled e Secondary watchdog timer added The secondary watchdog timer was added to function as a safety net for the periodic interrupt f Two new opcodes were added to support multiply and add and multiply and subtract operations on large unsigned integers These operations can be used to speed up public key calculations g Six new opcodes were added to support block copy operations from I O addresses to memory addresses and vice versa h The I O address space has been expanded to 16 bits to make room for new peripherals i Two new features were added to further expand the external I O interface capabilities of the processor First an option was added to enable or disable the auxiliary I O bus interface for a given I O bank If the auxiliary I O bus is dis abled for a given external I O bank the processor uses the memory bus for external I O transactions The second feature is the addition of an optio
271. llowing assumptions e spectrum spreader set to normal doubler in use 52 48 duty cycle and e a combined 6 ns for clock to address and data setup times The crystal can be half the operating frequency if the clock doubler is used up to 27 MHz Beyond this operating clock speed it is necessary to use an X1 crystal or an external oscil lator because asymmetry in the waveform generated by the oscillator becomes a variation in the clock speed if the clock speed is doubled User s Manual 271 Table A 1 Preliminary Crystal Frequencies Memory Access Times and Baud Rates Frequency Frequency Period Access Time Divisor for MHz MHz ns 2 1 8432 3 6864 271 522 4 3 6864 7 3728 136 257 8 7 3728 14 7456 68 124 16 9 216 18 432 54 97 20 11 0592 22 1184 45 79 24 12 9024 25 8048 39 67 28 14 7456 29 4912 34 57 32 18 432 36 864 27 44 40 22 1184 44 2368 23 35 48 25 8048 51 6096 19 29 56 Non Stock Crystals 20 2752 40 5504 25 39 44 21 1968 42 3936 24 37 46 23 04 46 08 22 33 50 23 9616 47 9232 21 32 52 24 8832 49 7664 20 30 54 26 7264 53 4528 19 27 58 272 Rabbit 3000 Microprocessor APPENDIX B RABBIT 3000 REVISIONS Since its release the Rabbit 3000 microprocessor has gone through one revision The revi sion reflects bug fixes improvements and the introduction of new features All Rabbit 3000 revisions are pin compatible and transparentl
272. lock Frequency kHz Figure 16 11 Sleepy Mode Current Consumption User s Manual 231 16 6 Current Consumption Mechanisms The following mechanisms contribute to the current consumption of the Rabbit 3000 while it is operating 1 A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances At 3 3 V see 2 below approximately 57 of the current is due to charging and 43 is due to crossover current 2 A crossover current that is proportional to clock frequency and to the overdrive voltage Ve V x 2 0 7 where V is the operating voltage of the Rabbit 3000 The cross over current results from a brief short circuit when both the P and N transistors of a CMOS buffer are turned on at the same time This component drops as the voltage drops and becomes negligible at 1 4 V 3 The current consumed by the built in main oscillator when turned on This current is also proportional to and is equal to 1 mA at 3 3 V 4 The current drawn by the logic that is driven at the oscillator crystal frequency This is considered distinct because it varies with the crystal frequency but is not reduced when the clock frequency is divided This current becomes zero when the main oscillator is turned off and is 2 5 mA at 3 3 V when the crystal frequency is 14 7 MHz This current is divided between capacitive and crossover components in the same manner as the cur r
273. ly the clock doubler the clock spectrum spreader and the PC board layout advice or processor core modules that we provide Low EMI is a huge timesaver for the designer pressed to meet schedules and pass government EMI tests of the final product Execution speed with the Rabbit is usually a pleasant surprise compared to other pro cessors This is due to the well chosen and compact instruction set partnered with and excellent compiler and library We have many benchmarks comparing the Rabbit to 186 386 8051 Z180 and ez80 families of processors that prove the point The Rabbit memory bus is an exceptionally efficient and very clean design No external logic is required to support static memory chips Battery backed external memory is supported by built in functionality During reduced power slow clock operation the memory duty cycle can be correspondingly reduced using built in hardware resulting in low power consumption by the memories The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles This has many advantages compared to a single clock design and on closer examination the advantages of the single clock system turn out to be mostly chimerical The advantages include easy design to avoid bus fights clean write cycles with solid data and address hold times flexibility to have memory output enable access times greater than gt of the bus cycle and the ability to use an asymmetric clock generated by a clock d
274. ly between 20 and 100 u A and still execute instructions at the rate of up to 10 000 instructions per second The 32 768 kHz clock can also be divided by 2 4 8 or 16 to reduce power This sleepy mode is a pow erful alternative to sleep modes of operation used by other processors e Processor current requirement is approximately 65 mA at 30 MHz and 3 3 V The cur rent is proportional to voltage and clock speed at 1 8 V and 3 84 MHz the current would be about 5 mA and at 1 MHz the current is reduced to about 1 mA e To allow extreme low power operation there are options to reduce the duty cycle of memories when running at low clock speeds by only enabling the chip select for a brief period long enough to complete a read This greatly reduces the power used by flash memory when operating at low clock speeds e The excellent floating point performance is due to a tightly coded library and powerful processing capability For example a 50 MHz clock takes 7 us for a floating add 7 us for a multiply and 20 us for a square root In comparison a 386EX processor running with an 8 bit bus at 25 MHz and using Borland C is about 20 times slower e There is a built in watchdog timer e The standard 10 pin programming port eliminates the need for in circuit emulators A very simple 10 pin connector can be used to download and debug software using Z World s Dynamic C and a simple connection to a PC serial port The incremental cost of the programmi
275. many embed 30 Rabbit 3000 Microprocessor ded applications Some applications may require large data arrays or tables that will require additional data memory For this purpose Dynamic C supports a type of extended data memory that allows the use of additional data memory even extending far beyond a megabyte Requirements for stack memory depend on the type of application and particularly whether preemptive multitasking is used If preemptive multitasking is used then each task requires its own stack Since the stack has its own segment in 16 bit address space it is easy to use available RAM memory to support a large number of stacks When a pre emptive change of context takes place the STACKSEG register can be changed to map the stack segment to the portion of RAM memory that contains the stack associated with the new task that is to be run Normally the stack segment is 4K which is typically large enough to provide space for several typically four stacks It is possible to enlarge the stack segment if stacks larger than 4K are needed If only one stack is needed then it is possible to eliminate the stack segment entirely and place the single stack in the data seg ment This option is attractive for systems with only 32K of RAM that don t need multiple stacks User s Manual 31 3 3 Instruction Set Outline Load Immediate Data to a Register on page 33 Load or Store Data from or to a Constant Address on page 33 Loa