Home

Intel 820E Personal Computer User Manual

1. 2 D Y NS 7 E 0730 91 01 000c 0c 4 E 06996 NOSTOA 3 i ALIO 0061 Pui 48 NOISAG 904 1 e 0 1 Aad Z 13SdIHO 3028 4 T31NI STL a 3901 z unz 2 14001 92vo M 50 6009 90 7 99 ord sid lt ec ALSH 96 lt 1 20 13039400A ehh 41303HOOA z3 59 228 887 WOLY 6199 THLOMAIS 23 T 5 1 X O 13599 e 12897 E s1Sundo 5 968 ged lt S 8 6 LEM ToHndo 091d lt s 8 gion x 0 eer r109ldv r lt gt 868 p ry ELON x 89 1 1 88911160 5 v1vasws r 8 4599 8 8 88781116 3805 V1vasws 69N 02 anes ser gt 3865 358NS py 108AS 5 C000 eV T g 1 x en mg ezaasad py 000v 921
2. 71095 o 4 1fnOW10H zy 1DnO IH siav o 6 2 a ASSE inowoH 1f ow ou 815 7H o 915 1 9 orav 9 61H sav 9 81H 10 o o St gt 91H sav 9 0026 1135 SH vav eav o 20 10 9 Faro 00 9 ve 01H 01H lo lav 960 HOW ov 8 20 71 0002 02 6 MS Q3siA3 1891 06986 VINHOdIIVO WOS104 2 ALIO 006 1 90 WIG Z LASdIHO 3028 91 3111L 820199 I N amp 0 J3ugnH 120199 fray E 1 2 149 pue HOW Wld 220149 ids orm 9 ZHOLISH NASLSH Nv1 60199717 1910 9080 9 ZHOIOHO NYT 55 NVI 020149 020149 610199 610190 40 20 NYT 14 Na 810199 fory 810149 pit ai NYT 24 NYT iav m NYT NVI rx FU 210199 NYT VIX 80149 Old NYT haxa 10149 91 en gt 7999 Pin Day SOLID 5
3. 9 sz d 500A ey 3 ov 05 5 01 0002 02 6 036 18 1 05996 NOS 103 3v 00d ALIO 006 A8 1634 99d 9 90 S1HOd 131935 v9d94J 2 LASdIHO 3028 H 131NI 3 111 uod pejqeo e 10 Japeay e ZWOO ZL OOA 9 evy ova 0AH 2199A 99 2829119 901 ey A a T 2N7002LT1 2 19 6 8890 29001 8890 29001 180 239001 180 239001 QNO iu a oxi siu E usa We aod b 200 90 MIS 680 5 229109 Q A8S EDDA vn jeueg Ov 40 16 t 91 01 0002 02 6 5 15 1 2 90 99d 3 06986 VINHOJI1VO INOS 104 ALIO 006 2110 1534 WHOd1Vld 90d
4. Layout Recommendations Yes No Comments 1 Board impedance must be 60 x 10 2 Traces must be routed 5 mils wide with 20 mils spacing 3 In order to break out of the MCH and ICH2 package the hub interface signals can be routed 5 on 5 Signals must be separated to 5 on 20 within 300 mils of the package 4 Max trace length is 8 inches 5 Data signals must be matched within 0 1 inch of the STB diff pair 6 Each strobe signal must be the same length 7 HUBREF divider should be placed no more than 4 inches away from MCH or ICH2 If so then separate resistor divider must be placed locally Table 44 IDE Interface Layout Recommendations Yes No Comments 1 5 mils wide and 7 mil spaces 2 Max trace length is 8 inches 3 Shortest trace length must be 0 5 inch shorter than longest trace length Table 45 USB Layout Recommendations Yes No Comments 1 Characteristic impedance of individual signal lines P Zo 45 Q 90 differential 2 Stack up 9 mils wide 25 mil spacing between differential pairs 3 Trace characteristics Line delay 160 2 ps Capacitance 3 5 pF e Inductance 7 3 nH Res at 20 C 53 9 mQ 4 15 series resistor placed lt 1 inch from ICH2 5 47 pF parallel caps should be placed as close as possible to the ICH2 6 15 kQ 5 pull down resistors must be present on the connector side of the series resistor 7 Stub length due to 15 kQ pull downs should be as sh
5. X 300 ful 2 X 5 4815 y 8 43NN9I lt x 5 0 4597 9 868 ceove 8884 6LOAHSH Hio 018 gt INIH esoy ze NHNO F R 8 gt BLNVOINIT 9IOAHSH Heem ger PIS SLGAYSY Hog X 5 LOQAHSH X A e gt 24181049 OBHY 8 x ait daNHSHI M 5 daWH3HI rod HIW A8SE 8 719418 SOYO ransu Ss 027 20 NGWHSHL zzii UNGNNHSHI x d IH LINHSH L Seo xp X 1 n LQAHSH o X 86 lt poua rs Nx Lg 1 b 000 1195 Misi 19 MOOS N 0 6 2089 i WHA serv X x dE yii S o 8 gt HSM4 a seo o 8 4 950 2499 2 159 SQVH LENY 83 2 lt gt 5 x 159 lt gt 5 LENG 559 e is LIH KAA 0 1 9 WLIH sev 8164 9 189 NLIH eV Cer 4 95 2 7 1001 4 _ 2 81 2 269 Wy 91 93430 99354 AOL TSH 5 489 1591 e A 1581 et 5 SAQUIH ScNV
6. vHINOd m 9 zr 8692 Z INOd vC 8652 lt 089 8892 0 1 6 VINO 9101d9 Cz VEINS 149 Pay gt lt 928292 309 lod 7x ET 869292 D 8 9252 and 869242 LAA 5 154104 mE 49 92 30 ve cV 11 0 89 9252 avd 9262 3018 3015 8 9262 SAQHL 869252 CX 92 avid 869252 Sasa 889292 86 gt G Oaud sO3u tao3u iOldo 86 ME orgy 8892 gt eroau 982032 089 ge sz zy 8 ee SaaS Ten 0189 a lt gt I QOlav 224 00019 2 12214 15519 gt 1 8528 89292 869252 HOI 0 620 944 40100 Bras O OUld gg m 925202 ord 2494 8692622 66 53 20 010 8 LODA SA LN9A SA SQ SL Su 8LH 8Ld 09A 8If 8eLH 8LO eLJ eL3 ZL3 0L3 SL3 PL 3 e 39 9 z 39 9 1 39 9 0 39 9 eig 0 z
7. AG seu 900 10 6 A8S EDDA 6 Si 856 EDDA 159 59 9920 97116 vi sin Mec N 158 53 LSZH amp ASE EDDA pesn si HNS ON 3jnioo 8260 9859 MS NISISH JOYS WHA UO p300 81 0 wyo 022 5 MOMd nd9 uo 0 9 wyo 065 1353480 lt v 802 17 5 JNYVONT E o Wi 1 ef ASE EDDA ANYVONTL t A8S EDDA AS Seu VrLOATPZ A8SE 404 WHA V802N VANS uong 1eseu amp E 6 8 v JNVVONTEL 4 51 1 en et ace vL sin 9553 A8S 5 ASE 766 55 MOMd NAINO AS seu 900 17 5 900 148 ZLOOA A8SSOO J0joeuuoo X1V OOA 2199 3NO 5 A8SE EDOA JOJOSUUND 0730 26 5 t 91 01 0002 02 6 5 15 1 2 90 99d 06986
8. gt 946 AOS UAM 3H zgor nod gt 126 40 98 OHS 33 zazobnoHs ds lt 16 2 8 9 0 3Au3sa3d eV 8 6 9820 oaxy NYT 00 880 UNO NYT 8sn HNO QXH NYI NVI m 2 2 400 8501 uNO SN e 85 UNO NYI PERPE SU M BOXEO UNO NVI 8 roar 338X END 2 13599 OV 2 1 8 2605 NASIS YNO NVI HNO INIVIVGS OV 8 22 ONI V1vOS 18086 Le AO NI 91 uw x UNO ONIV1VdS OV zu 1nO v1vas 2699 HNO o 1nOVIVOS OV AS UNO ONAS OV 18 ov 6 SODA ABSSOOA ase 899 HN2 49514 WOMEN puy 0730 91 62 01 0002 02 L3aus 1Sv1 06996 NOSTOA 200860 3v 00d QvOH ALIO 0061 103r0dd N9IS3A 908 90 SNOILdO 5 60V WIG 13 41 3028 H T31NI JILL 8 zz lt 8 NYT 2 EE
9. ALVOM SVIVOM 4315 sla 05 09101 sizaoa 2510 2514 scusa 1000 Liu 1519 1519 Sed9 eX1ul vEdO cxuul 31vo0ev 158087 SOW X109 194 081985 09991 135991 oavi cavi tavi ZHWYL OIS 1350 3LVOM 3315 410 0850 HENAGAYG Oumas 922198 2 6 our Brod os 219 315804 8 29252 22141 01 89 1 21016 0 00 1 21016 21016 0 1 21016 1 21016 oer juo Bngap 104 241 4120 3807 39047 0260 31vo0cv 15887 es ZX19d OIS 081835 lt gt 88982218 6 241 09991 15194 lt 429252 22110 89 2 6 0 1 21016 lt gt 21016 lt gt eV0V 6 21016 HMd Qv 1 847 SODA 4adns 3 ov L 91 01 0002 02 6 prie 1597 06966
10. ui pepiAoJd se 141 si 1 Aue asimsaujo 0169 Aq JO sseJdxe ON sjonpoud uonoeuuoo pepi oJd si 141 u uoge woju SSTdNVS HO NOILVOIJIO3dS WSOdOud 40 LNO ONISIHV 3SIMH3HIO ALNVHHVM HO YVINOILYVd SSANLIS ALETISV LENVHOH3IN HO ALNVHHVM H3A3OSLIVHM S3ILNVHHVM ON SI SV SOILVIN3HOS 3S3HL eBueuo o pue soneuieuos 164 SION Ly OV 66 86 16 96 GE ve c Le 0 8c 16 92 44 c 24140861 829161 01 6 8 2 c oDeg KJ01SIH UOISIA8H Dujdnooeg SNAN VY su 1 11V 10108 09 19 WHA Swed 1404 Addoj4 asnoy pseoghey 5404 1219 GSN 5 S10128UU02 101994409 dO V wa sks 19915 5194206 HOW Jeziseuju S 420 9 201290000 105592044 yoo 19945 19409 L 90 NOISIAAY SOLLVIN3HOS 434 CHOI WINIH L3SdIHO 3028
11. 1405104 ALIO 006 U 1534 WHOd1Vld 90d 1 110v v9d94J 2 LASdIHO 3028 H 131NI 3 111 98 LHIH 158 80 LESH 8 VH HEO3UH 03YH 45400 1H SAQUIH HIVH SHEVH Sci VH 9s VH odse 4444 4444 odie oee le Lel vH uogeuiuue 119v 2 ov 85 91 01 0005 05 85 SMS Q3siA3 1891 06986 VINHOdIIVO 104 2 ALIO 006 1 90 SNMOdTInd samind doviiod QuvOS Z L3SdIHO 3028 H 131NI 3111L MNIIWS eiu 19 5 1431Y 9 15 PAN 3809 viva8Ws cen 3800 MONS 546 546 42 yzg 910 3 Wr lt secu 191507 lt gt 92218 gt 92 92 2 8 088160 lt ae gt 9252928 alvoozv lt ue v LNOd eitlNOd amp 1NOd O LNDd 150 08150 24 vel
12. A8SE NYI 9601 41122070 e 9920 Sol 909 6168 ASE EDDA NVI 29828 33715 suuo 0 186 1422 2060 pue 1620 ZA 1329528 suuoizi i8e u 1428 2060 620 GA noway 29928 avid 1329928 H3z9sz8 10 suond o eX M10 NYI Ov JO 22 5 90 ALIO 008 1630 50d 1L3SdIHO 3028 H T31NI 311LL A8S WOud3 199 deo 0 18 z sjeubis peeds pue peoe d eq pinous sdeo jn 0 pue ujejeuuey punoue epis peojed eq jn p sde2 yng 1 SALON Wa3 L329S28 33715 IN3 L3c9S828 ANY AINO QV IID 33715 H3c9S28 33715 09 0730 62 5 t LE LE 000c 02 5 15 1 2 90 99d v9d94J WIG 2 LASdIHO 3028 1 1 31 1 3 06966 VINHO4ITV9 NOSTOA 2
13. ALIO 006 2110 1534 WHOd1Vld 90d 90 v9d94J 2 LASdIHO 3028 H 131NI 3 111 SJSUMO jo Auedoud pue 0002 jeu eonou Aue je suonduosep pue 911 e qej reAe pezuoejoeJeuo paysijqnd jonpoud eui Se UMOUY 510418 9 urejuoo Aew 1esdiuo 408828 919 94 eonou Aue suonduosep 1onpoud pue 05 sye w suoneoidde Buriurejsns ui esn zou sjonpoud 19 u 1406 Auedoaud 1 19430 1u8u doo Aue jo ApiqejueuoJe uu esodund 1e nonaed e 10 sseuy Guipnjour syonpoud jo esn Jo pue aes 86 4 Aue 914 pue ou seuinsse sjonpoJd 10 JO suomnipuo pue
14. 0 1816 1 sindino 0 8001 661135 5959 HNIS ON 910790840 l Peigeug ar 12945 pads n 4 t4 QNS 9 1nOW10H 00 001 L snawvu sns IS gt LSOH oozy 08 sz 4 NV 81 HET Ln 91 19 aoe i ETIN Ter Onn wbno 9 v ooa 89015 884018 961 6 NOHMd zi ooud z CLKTM RD oi11xeu 959 Wld o lt o 8 e E 9615 8020 7959 9 9 52 coon 7M0SH8H lt 0145 0130W 8 8 LOOA 10 m 6 EDDA m N 2 8 199 yg ANC TESTA 0 OIS 9 200 Ost 22 ZHN OHI m AE 7 8 lagz 99310 1931 66 99H9 1531 sjueuoduioo 10 G ASN SNU OY ALTO DUE x E 20 614 99 19 VV VH 9910 2 99 deo jueuoduioo je pejdnooep uo uid ex d pinoys Id 99x10 HOW 66 ee star 9 NNOO 049 n 994
15. 10 pesn eq pinous 11 AS sjueuoduioo 3160 Aue eAup jou pjnous euejd 941 5 AS t 094086 SHOL 0002 02 5 157 05996 NOSTOA 2 ALIO 006 1 meni NDISAG 99d 50 5 1 v9d94J Z L3SdIHO 3028 H 131NI 31111 QNO VZ0ONTPZNS t 19 mM ec eo 25 dn 143 Ae AIS 200 1 5 A8S EDDA 1UF X7R 2979 22 59 99 028 AGSE 00 AGSE Fav Kase POV 92 2 2 69500 Q y 99 962918 89 17 9 ES 2 25 s USL Tis 9 YHOLVINDAY ADVLIOA 15 81 ASSSOOA 00978 A8S8 LSONOA A8SE EDDA 4 2 A8SE 3SN3SOA ASE EDDA dSN3S AGSE 3SN3S AGSE A8SS 220 A8SE EQOA 9628 11 2620 HNIS jou oq 490001 6620 2629 Y A8S 98 AGSE EDDA IZ
16. 1591 06986 VINHO4IVO NOSTOA 5 2 00d VOY ALIO 006 2110 1534 WHOd1Vld 90d 5 80 v9d04 WIG 13SdIHO 3088 H 131NI 15 090 804 91H SH 81H 9195 H 915 1 61H 1H Jjdug8nH 99410 1531 HOLO3NNOO38OHd juo 104 1012euuo eoeypeiu qnH
17. CFM Design Guide 2 7 2 1 Figure 13 InteP 820E Chipset RSL Routing The RSL signals enter the first RIMM on the left side propagate through the RIMM and exit on the right The signal continues through the rest of the existing RIMMs until it is terminated at unpopulated slots must have continuity modules in place to ensure that the signals propagate to the termination RSL Routing Dimensions MCH to first RIMM to RIMM to RIMM RIMM Termination 8 route To maintain a nominal 28 Q trace impedance the RSL signals must be 18 mils wide To control crosstalk and odd even mode velocity deltas there must be a 10 mil ground isolation trace routed between adjacent RSL signals The 10 mil ground isolation traces must be connected to ground with a via every 1 inch A 6 mil gap is required between the RSL signals and the ground isolation trace These signals must be length matched to 10 mils in line section A and to 2 mils in line section B using the trace length matching methods in Section To ensure uniform trace lines trace width variation must be uniform on all RSL signals at every neckdown for each line section All RSL signals must have the same number of vias It may be necessary to place vias on RSL signals where they are not necessary to meet this via loading requirement 1 e dummy vias Table 3 Placement Guidelines for Motherboard Routing Lengths Design Guide Trace De
18. nna v9d04 WIG Z 13SdIHO 3028 H 131NI 3789 7559 Buidnooeg A8SE 1 ysg wyo 9 sdeo 41001 e eld WINIH uoee deo 3M 1 0 1858 15 8 92614 0589 LEED 1920 2 20 9929 9419 8419 10 1819 8620 8810 vezo 920 7620 20 sezo 2222 9222 2222 8222 6022 6620 8SZ9 1969 9520 9720 6980 0520 7810 022 2223 89 6129 ISLO 89 0 219 A8S8 LSOWOA A8SS 200 A8SS 200 919 Buidnooeqwiid 86 0 90 0 29 0 919 5010 2910 vSIO 1969 2119 0155 9129 SZIA 659 8 220 EDDA Buidnooeg 6 EDDA 2 v 093402 9101 0002 02 6 prn d3sl 3d 18 1 06956 NOS10d A 3v 00d ALIO 006 2110 1o3rodd 1534 99d lt 0 AHOISIH NOISIA3H ASH v9d04 Z 13SdIHO 3028 H 131NI a 9 L 2 14 9 9 2 8 09 30
19. 4 09402 81 6 0002 62 5 d3siAau 1591 06986 WOS704 2 3v 50d avos ALIO 0061 3 A8 1534 WHO31V1d 908 9 WvHOVIG 0018 NNIG Z 13SdIHO 3028 4 T3INI 4111 Si 1 pe aov wow ga ew Ium toros v1va auaav 194 PCI CONN 4 PCI CONN 3 PCI CONN 2 PCI CONN 1 JHLNO 04 7 N N sng dov ESO lt 208590014 wesbeig 0730 6 91 01 0002 02 6 1JJHS 2 1891 06986 VINHOdIIVO WOS104 LO3roud 90 ALIO 006 l Sen 1630 IWHOd1v 1d 908 Pl HOLO3NNOO 305539084 v9d94J Z LASdIHO 3028 H 131NI 3 111 ue 9LLASdH SL LASdH llASdH LLASdH ZLLASAY LLLAS3H sen Sen 0LLAS3H X 5 xq 94 x 6299 reac 1090 934 x sev 2430 S 1620 1434 52 0 3
20. 469 966 429252221109 526 9 8 ge ve 6 9e ee ev 6 Lr LINI a ANNOI ay 8853 zz 4824 m ziv 918049 iav WRUZV oav ein i v NA 9 9 8 07406 5 01 0002 02 6 aside ev 06966 NOSTOA A ALIO 006 U gt 599 inovivas ov Lo3rotid 1634 4 4 90d 20 ms o 3ON3H343U 13SdlHO 3028 H 331NI STULL OL odl OHS er ga O S EL ied ozn 33 1251 Sig or inoa 33 avuls 1noas ov 5 e 7 douMd WHA gen Ns 33 33 A8SE lt ES 8933 SO 33 Los v OANTINS 22 2 gt 5 saas ao EN US 200 gt Q 82 O WMS sraas 8 8 i ziaas 5 6 090 iw 0800 E
21. 99d 9 T lt 0 5133005 Quvos WIIG Z LASdIHO 3028 H 131NI JILL 8228 JMS jou oq 49 92 9272 20189 gt pisulod O 20 90A anro 679 5 vaaAs l13S3H vTAdSH 13S3H rAHSH 3nro anro anro dMS dMS gt 861 11 69 6910 9910 OSLO Sn 3809 5 lt 8651467 86611169 3809 vivasWs vas vas 3809 vivas 798 avs 15 38005H98NNS Lvs sca tvs ovs g 098 EEDA HNLOH Hey vWWiog 18y 108 INAJ Fesa SNI W3ou 8439A 8439A e iu 9 ON 3UVdS ASH ON dX3 ASH INWIHS ASH 098 2Gg qN5 9 A8SS ZIDA A8S8 ISOWOA B79 RSV EXP H NIS OIS S 72968 96 lt yos sev 51 65 weal veg 0 01 S gt Fr sio goa 199 Nb zig 1807 A35 A37 B35 B37 41 42 54 58 841 842 854 858 GND A1 A3 45 A7 A9 A11 A13 15 A17 A29 A21 A23 25 A27 A19 A31 A33 A39 GND A52 A60 A62 A64 A66 A68 A70 A72 A74 A76 A78 A80 A82 A84 A86 A88 A90 A92 54 NIS OIS AST QWO1 eg NC A38 A40 B40 RSV SPARE A101 NDOT d 1 011
22. zev lev 1815 av 9 ano oey 6ev 82 2 cav 8eavo Siavo lt gt 92628 lt 861 lt 861 861 lt gt 9ravo Loy 9 9ev Sev vov EDDA X vy 0 ASIH 12 gt 61 vas vas 81585 81 9 815 85 evas H 91 Ivas 143 21 H nv 01 Hadid us ev LN99 s1Sulod dovasn HASH VLNI v asn V s3u 139391 ov 99 438 j3HdOV HOW SE 798 0 9 2 208 Savo 20 099 0819 QV cc 899 0915 4 861 avo 80 9 010 9 210 9 99355 478 88389 39 29 8 8 81 16 asaya E cba 9 ON ovg zva 195 3 95 oed FAGHIO 9 2 38 09 LLavo 6ravo seg 4 O00 Izavo 758 QV 81509 GL lea oeg 129 2 61d 815 88
23. ALIO 006 FLL 1534 WHOd1Vld 90d WALSAS VLOOA1PZNS INO 091857920145 lt 9 10 015 sindino eL AISE EDDA 80109 949 037 NNI 2 A8SE ond as VZ0ONTPZNS A8SE 09 A8SE 3 2607 QHVOSNO tds NNOO Nd 1N3 umivaas lt ror Q31u3MOd A3 MS H3MOd 5 60821 28 7062844 9en 92 84 ____ c o 12 02 x er Ns gi 0814 48 o x SL el 3400 lA3M 3807 M vL 9959 3ALOV 104 joy uo 5 qpueis y sejeorpui 037 preoquo 80 031 Ags A8S EDDA NS VLODATPLNS 4928 uxiH 28 __ 1891 04 401 nis ON 4920 6 5 M eounogep pue seu HO ze 1581 104 nis ON 8 5 6 5 ie 00 17 65 z lt L 9 99 20 t
24. NOSTOA A 5 4 ALIO 006 lU NOISAG 904 80 3 Quvos WIG Z LASdIHO 3028 H 131NI 3 111 00 ANVI 3O01L 110 19 pane 2 19 ANVI L 812 OdN 4d0zz 619 OdN 4d0zz 2 119 5 2 z WX OV 1 1 LA 3nro 910 oT 4 VREF NI 1 OV FILT R C CX3D C 27 AC lt 0015 lt dava 2 30 XTL IN XTL OUT VREF 33 RX3D_C FILT R H FILT L H2 2 3 vREFOUT 28 Tino V 100 Ni TINO Wi L V 1n0 ing ymsoN 22 5 8 100 ANT 0015 8 210 no ONOW 780 HNS ON 3NOHd 19 NIVHO 050 H xy 059 760 Txnv gg _ 189 n 18 pe OV ov 9 1891 ao ONAS OV H ONAS ov OF ONAS Tao 399 09 0 1 06 OV WNivivasov vivas waa 1novivas ov inovivas oy _ 9 100 1 06 13534 Ov U ISH NMG iHd IT 19838 LOIN sesodind 159 10 61018150 seueg d338 od 16 21 uMdS 60 0 0 9 gt 91 9 6 6 gt NI OIN TN ANN 980 Anko
25. ddlp 5720 14429 diaasn Ntagsn LODA 0 1 0 099 ALS 8801 er 0985 doaasn Noagsn lt lt 81 _ VAS 2088 doaasn 8 5 8 didasn Nidasn didasn 6 Nidasn 5 96 31 WN ered 1 51 feel YS 180 660 860 1 1 4089 4 euMdasn 200 00 dOV O 2100 NI 404850 Noaasn d iuMdasn anvo Ou 0400 lt HNO 00 8501 3 5 GSN 3 15 07 6c 91 01 0002 02 6 2085 0381 9 18 1 06956 VINHOJI1VO 05704 5 3v 00d ALIO 006 A8 1530 99d 9 90 1909 v9d94J WIG 2 LASdIHO 3028 H 131NI 3 111 180 3408 HVd 4715 NNS 9 1804 Old ved 21 Sed Eld 318 68d 9r
26. AddO14 ASNOW GHVOSAS v9d94J 2 LASdIHO 3028 H 131NI 3 111 S0HOMSQ 14S0H ALVOM SVIVOM 3315 0850 OffH LIN X30NI ddo 4 81 GND KBMS FB S z Sd pa z Sd aiSon 83 83 X108 sf LO 84 vagy SWay SOOA Addoj4 esnoy pseogkey Ot JO 26 13948 dasiau 1597 0 996 VINHO4I1V9 NOS103 ALIO 0061 NSIS3d 90d 90 1HOd 3AVO V9d2d WIG Z 13SdIHO 3028 4 T31NI 3111L e Ajuo SSAV OIS 0 pue uod NI iai ALAO m 2 iy Y 1nO IAIN 968 zen XLAOP p MIS ancsial 3 F 094066 51201 000
27. Connect APICCLK to CK133 with a 20 to 33 0 series termination resistor If the APIC is not used on UP systems APICCLK can either be tied to GND or connected to CK133 but cannot be left floating Pull APICD 0 1 to GND through 10 pull down resistors Use pull downs for each APIC signal Do not share a resistor to pull up signals 127 Inte 820E Chipset 128 Table 32 GPIO intel Checklist Items Recommendations Reason Effect GPIO pins GPIO 0 7 These pins are in the main power well Pull ups must use the 3 3 V plane Unused core well inputs must either be pulled up to VCC3 3 or be pulled down These inputs must not be allowed to float GPIO 1 0 be used as GPIO 1 also can be used as PCI REQ 5 These signals are 5 V tolerant GPIO 8 amp 11 13 These pins are in the resume power well Pull ups must use the VCCSUS3 3 plane Unused resume well inputs must be pulled up to VCCSUS3 3 These are the only GPls that can be used as ACPI compliant wake events These signals are not 5 V tolerant GPIO 16 23 Fixed as output only Can be left NC In the main power well GPIO22 is open drain GPIO 24 25 27 28 pins Can be left NC From resume power well Ensure that unconnected signals are outputs only These are the only GPI signals in the resume well with associated status bits in t
28. TW pM TI ew vA 088 61VH 21 6L 0H SHYH yy pR OL VH 91 0H SEM SHVH E zn el 0H en 218 ZM OLIVH O1 GH 6 VH 60H TA 6 0H 8 VH 88 TM 3 0H LINH 18 VH 9 9 0H TK SH TI LEE mw oe m m Sd 0H Ie teli vH rut u vH HGH 8910 Bg 22 6 8 Fa gt 486 UE m lo coliaH anro anro d d j seo How 2 o 5 c 5 E 5 9919 2 64 2 HOW 020 1610 2 5 961 001 lt PZ 610 WV NNOO Bors uuand lt 8 2 v 6 9 2 8 F e 0 402 20 71 0002 02 6 DS 351 3 18 1 06956 WOS104 2 ALIO 006 1 mcn 1530 99d 9 T 90 HON ASH WIIG Z LASdIHO 3028 91 JILL 815 85 815 85 915 av
29. dO8S 6ev 8 v Lev 868 288 95 968 45400 1d 8692528 14SA30 8692528 sev Seg AQUI 8692528 lt eeg eso d3NOQS 8692528 8835 lt 8692528 86925298 88018 gt 8692528 8692528 zev 8iav bev zeg led 42107 8iav oey oeg 60 ozay 824 Lov 628 829 ozay eeav 428 eav 9 92 Sev vey 928 528 5 98 9 92 szav 924 tov 2 eov 12 eza cea 420 29 62av 10 90 92 e W 4085 3005 E 7a018 4081 5 52928 lt 10 vitO3H 8 ozy 61 81 029 618 98 4292652 2210 89 amp iSuiod OLLY HNIS ON LN 91 stv zs sig 10 SitO3ud Leay gt 8 8 108 lt S 429252 22171 0 89 15194 df 1431 OulH3Sg ely ea zia AN 9528 eitlNOd OulH3S 862128 6ngep 40 OulH3S
30. 0 67 ns ft Equation 12 Effective Propagation Speed Serr So x 1 Cp ns ft Equation 13 Effective Impedance Zerr Zo 1 Q Equation 14 Distributed Trace Capacitance Co So Zo pF ft Equation 15 Distributed Trace Inductance Lo 12 Zo x So nH ft The symbols for Equations 8 15 are as follows Design Guide So Speed in ns ft of the signal on an unloaded PCB This is referred to as the board propagation constant So MICROSTRIP 90 STRIPLINE Speed in ns ft of the signal on an unloaded microstrip or stripline trace on the PCB Zo Intrinsic impedance of the line This is a function of the dielectric constant line width line height and line space from the plane s The equations for Zo are not included in this document For these equations see the MECL System Design Handbook by William R Blood Jr Distributed trace capacitance of the network in pF ft Lo Distributed trace inductance of the network 1n nH ft Cp Sum of the capacitance of all devices and stubs divided by the length of the network s trunk not including the portion connecting the end agents to the termination resistors in pF ft Serr and Effective propagation constant and impedance of the PCB when the board is loaded with the components 155 Inte 820E Chipset intel 3 4 2 Effective Impedance and Tolerance Variation The impedance of the PCB
31. 91 01 0002 02 6 Q3siA3 1597 06986 VINHOdIIVO 08103 3v 599 ALIO 006 2110 0730 vc 5 0 39 09 4 gt pPI 90 YOLOANNOO v9d94J WIG Z L3SdIHO 3028 H 131NI 9 99v S9v v9v cavo cov vavo cov v 19 9avo 09v pav 861 0438 00 osarsav 697 0815 89 p eavo 99 JjdudOV 0 58 2 11120023 2 L el 80 es Sey 22 961 108 gt 8 8692528 1303dAL HOW 0 eq 349 4292522171 701 89 ssv esv 10 29 uvdo ANd 10d gt 40150 osy 8vv grav o Lev AQHLOD 9 bev LA 6ev 8iavo gev Lev iav grav 9 0cavo 9ev eeavo Sev gzav 39 99
32. onxa E 98 fj 3SN3SOA 9620 e 18008 6 15008 zi 9OMNI HU AGSE EOOA 3 vr MS SS Nnd NNW 866 COON IIS 91 2809 0800 gi 000 4932915 ezl 961 001 NANN 624 8 51710515 VCC3 3SBY L 1070 o ANA OED HNIS jou oq 5254 LL AQSevels A8S 00 T MS AGSE A8S EDDA S 4 919 Ov JO 96 5 F 4 ES 06986 NOSTOA 2 90 5 1577 3v 909 0061 11 1534 WHOd1Vld 90d H3MOd v9d94J 2 L3SdIHO 3028 H 131NI 3 1L 166611 pue e Kuo 1581 104 gnis ON EZ Xisuwsu 9 g 143 1581 104 gms N900X0 NS vL 020 v 6 8 ANI 3OHMd e ASE EDDA N900X0 NS oen
33. 189 gt 001 gt OINOd dii wes LINY ung 2 48 4 a 55555555 lo SENV 8 5 Sera y 956 vd amp isuda 20 Ope iaszuaa 75 802 6H Cl zd amp 18Hrld9 isundo 9 289 ser 2194 Ba LIAS 988 825 gt MES e see R lt lt B NE visu gt 112 9670 vtvo zero 8 38 gg 2 8 T 82 8 m 5 9 anro anro g E E m 4 amp d 91 9 5 UOI 10 59 Vile 97 9 anro 159 suid 106892044 jo siu 005 401 0 SOWOA LEYI S LIA 5 222 222 nos 22 pem E S LLLA S LSOWOA 8 L 2 9 9 2 8 3 t 0940 9 20 71 0002 02 6 d3siA3u 157 06956 VINHOJI1VO 05704 3v 59 QVOH ALIO 0061 jul lo3rodd Aa NOISSG 908 90 YAZISAHLNAS 49010 i v9d94J WIG L3SdIHO 3028 H 131NI JILIL sesodind 158 10 peuinbei eq jou 114 ZHI N8t ZH WEEL PAO 11d ZH W8t ZHWEE L v peueseu 9pow 1591 9 9 114 ZHINOOL annoy 114 2 ZHWOOL ANOV 0
34. 3 3 V Core ie Iw 909 1 8 r1 6000200202202020 ES oOo 9 gt OO O U m 2602020220 oom o goo oo 2 2 eoo D O C x 206202 606022 20202 ojo coocoo 2 206202 L1 20202 2 0202 o0 2 ede ooh oo 6060022 2 e Oxo o 200002020202 1 8 V Standby eu go OG gt 2060020202020 DIL EE 3 3 V Standby 1 8 V Standby 3 3 V Cor 1 2 decoupling The previous figure shows the layout of the ICH2 decoupling capacitors for various power planes around the ICH2 The decoupling caps are circled with an arrow pointing to the power plane trace to which they are connected Design Guide 123 Inte 820E Chipset intel 2 23 FWH Flash BIOS Guidelines The general compatibility guidelines and the design recommendations for supporting the FWH Flash BIOS device are discussed next Most changes will be incorporated into the BIOS Refer to the FWH Flash BIOS specification or equivalent 2 23 1 In Circuit FWH Flash BIOS Programming All cycles destined for the FWH Flash BIOS appear on PCI The I
35. 87 R2 390 high spd cmos term SIO Routing The SIO signal must be routed from RIMM to RIMM as shown in Figure 34 The SIO signal requires a 2 2 to 10 terminating resistor on the SOUT pin of the last RIMM SIO is routed with a standard 5 mil wide 60 trace The motherboard routing lengths for the SIO signal are the same as those for RSL signals See Figure 34 SIO Routing Example Design Guide 6 SOUT 2 2KQ 10KQ 0 4 0 45 sio_route vsd 55 Inte 820E Chipset 2 7 4 2 intel Suspend to RAM Shunt Transistor When an Intel 820E chipset system enters or exits Suspend to RAM power will be ramping to the MCH 1 it will be powering up or powering down While power is ramping the states of the MCH outputs are not guaranteed Therefore the MCH could drive the CMOS signals and issue CMOS commands One of the commands the only one the RDRAMs will respond to is the power down exit command avoid the MCH inadvertently taking the out of power down because the CMOS interface 15 driven during power ramp the SCK CMOS clock signal must shunted to ground when the 15 entering and exiting Suspend to RAM This shunting can be accomplished using the NPN transistor shown in the circuit in The transistor should have a Cogo of 4 pF or less 1 MMBT3904LTI In addition to match the electrical characteristics on the SCK signal the CMD signal needs a
36. 9vod WH3L SvOG WH3L gt gt N vvOG WHaL N evoa WHaL et Se gt 25 N N evOG WH3L WH3l eun lo slvod War Ov 30 Ob 5 t 71 01 0002 02 6 5 15 1 Zoulweg 1O3roud 90 99d 3 06986 VINHOJI1VO INOS 104 QvOH ALIO 0061 1534 WHOd1Vld 90d eu v9d94J 2 LASdIHO 3028 H 131NI 111 200 17 5 oo X 8 ven X 9 V20ONTPZNS lt 69 QNO m SON 8 o VLODATPLNS e o 5 8 5 9 ein VLODATPLNS o LL a ein 00 1 5 2 aNd OON Bu 9 ANS VLOOATbLNS 4 26 9 9 COM NS A8S EDDA anro 9979 ANFO e ANFO 9SvO 4970 e Anko e anro e ANFO 1990 c9vO 6970 S99 1979 cSvO 6400 vSYO 9970 0979 anro e anro 8990 6SvO nA 9493 08 6vvO 8 A8SE 8 x6 99
37. 002 Minor edits for clarity July 2000 0 Revised ICH2 sections May 2001 12 Design Guide 1 1 Design Guide InteP 820E Chipset Introduction The Intel 820E Chipset Design Guide provides design recommendations for systems using the Intel 820E chipset This includes motherboard layout routing guidelines system design issues system requirements debug recommendations and board schematics In addition to providing motherboard design recommendations e g layout and routing guidelines this document also addresses system design issues such as thermal requirements for Intel 820E chipset based systems The design recommendations should be used during system design The guidelines have been developed to provide maximum flexibility to board designers while reducing the risk of board related issues The Intel board schematics in Appendix Reference Design Schematics Uniprocessor implement Intel PGA370 architecture and are intended for use as references by board designers While the schematics included cover specific designs the core schematics for each chipset component remain the same for most Intel 820E chipset platforms The appendix provides a set of reference schematics for each chipset component in addition to common motherboard options Additional flexibility 15 possible via other permutations of these options and components About This Design Guide This design guide is intended for hardware designers who are
38. 8 VEINO ua ASE EDDA O A8SE EDDA IGP 10 018 68 1531 19 Hiit LNSHd 20 1531 108 gt 92 869252928 869252 28 8v 98 g OUld 86926528 vitOuld 8692628 lt 4 9v M 728 98 9252 Sv sa 1914 9252 lt SWid ev ev va ea 9252 15 14 88902014 y 1seuuny eq jsnu 6f 2199A 809 Ww NOO 9 er 21005 10d SODA 2120A 869252928 92 ce INSud gt 92 Le 1NSHd ge 9z sz e 8v 86926228 8692628 lt 9252 4 9v vitOuld Sv 9268 92 42 1914 SW1d ev ev 15 14 SODA 89 orr 21015 10d SIDA 2150 SJOJOBUUOD 528 gt 528 8 Ot JO ZZ 1JJHS 2 06966 NOSTOA 1O3roud 90 5 1577 Jv 59 ALIO 0061 11 1534 WHOd1Vld 90d SHOLO3NNOO WIIG Z 13SdIHO 3028 H 131NI 70 v 5 23 217 308 158194 9
39. Intersymbol Interference Intersymbol interference ISI refers to the distortion or change in the waveform shape caused by the voltage and transient energy on the network when the driver begins its next transition Intersymbol interference occurs when transitions in the current cycle interfere with transitions in subsequent cycles ISI can occur when the line is driven high low and high in consecutive cycles The opposite case also 18 valid When the driver drives high on the first cycle and low on the second cycle the signal may not settle to the minimum Vo before the next rising edge is driven This results in improved flight times in the third cycle Intel performed ISI simulations for the topology given in this section by comparing flight times for the first and third cycles ISI effects do not necessarily span only 3 cycles so it may be necessary to simulate beyond 3 cycles for certain designs After simulating and quantifying the ISI effects adjust the timing budget accordingly to take into consideration these conditions 149 Inte 820E Chipset 3 2 5 2 3 2 5 3 3 2 6 3 2 6 1 3 2 6 2 150 Intel Crosstalk Analysis AGTL crosstalk simulations can consider as non coupled the processor core package the Intel 82820 MCH package and the Intel PGA370 socket Simulate the traces as lossless for worst case crosstalk and lossy where more accuracy is needed Evaluate both odd mode and even mode crosstalk conditions
40. t 3 094021 61 01 000z 02 gr 18 1 06996 NOSTOA 2 SV 59d avouALO 006 A8 1530 99d 9 90 83415 v9d94J 2 LASdIHO 3028 H 131NI 3 111 wrs 2 320 0 10 SSeJppe OI 10 dOSAS uo 140848 9 gt AAO INOLINGer 2NOLINGIF INS 041 uid sdeo eoe d J3HA 01 1xeu eoe d 1 3022 ANFO ANFO 4010 6060 ELED 1289 8759 6089 ee NNS 1408 5 249 eid eedo 9 4 1249 1114 0249 91 9 ALP ISLdD e8er 49 ido 1817 0199 904 100 10 9249 NI laiWSszdo LHOWL NvA Ledo ZHOWL 4 0649 INS 249 zaavi9do 1937 0949 2 1HOd WWIYAS 1HOd 1 5 904 d9 INV 390915 40V suouua MOV Asna X4eazvod1l 1078 OIS vad Sad 90 NILOIS 3SW Q8AM LHOd T3 TIVHVd LINI HVd 9079 Zeo SVIVOH 0281
41. wel LN99 961 011 AWN lt gt voL 1 15 1 29 ved WOL 81585 gt 24 Li oa te 92528 9935 gt 92428 8838 92 52 8 922 3015 uvdo 840189 was 92528 5 d sav udo susmi dade 92528 LG9lav 92528 88859 1 99399 13SA309 AGHID a Ould OitOuld HOSSdOOHd gt 92528 gt 92528 0730 66 5 F 91 01 0002 02 157 06996 NOSTOA 90 ALIO 006 l penne Nosa Boa el 1 v9d94J 2 L3SdIHO 3028 H 131NI 3 111 e e 19 gt gt MOS WHAL 26 06 1 606 Sl sjeubis 7 deo 0 euo es S1ON 7100 100 WH3L 2100 WH3L 1109 WHal 0109 WHAL 0 100 WHaL ZWOH WH3L 1 WYL 0 WH3L 0 2 WHAL 1 021 WH3L 1900 9 0 WH3l WH3L vgod WH3L egoa WNH3L zgod WH3L 1800 WH3l Wual Svod WHSL
42. 98 99N ain lt 9e se ve e V LV 0L 8 9 15194 20 uonoetep 6018 10 49 0 eq ULO 10813800015 Pue 193130014 81606260 HNIS ou uonoejep epis 1509 104 8160 6860 HMS uonoerep opis 104 c 6 z 6 6 std 1ovaal 5 5205 6 2 5005 S0dd ovas 10931300014 9108 10931400015 585 8 6 Sf AQuOIS 6 6 3HOldS 5 3 molas 91009 vlddd Eldad 5 LSH 15104 15104 K ISulod SJo0j2euuo 401 Ov 40 82 5 t 91 01 0002 02 6 5 15 1 1O3roud 90 99d v9d94J WIG 2 LASdIHO 3028 H 131NI 3 111 3 06966 VINHO4ITV9 NOSTOA VOY ALIO 0065 2110 1534 WHOd1Vld 9 SYHOLOANNOO SN sdeo pue 1581 10 79 689 ddvasn gt erdt 159 dovasn HOI JO sdeo 4 pue 8 018 89 uiuo 91
43. AGTL crosstalk simulation involves the following cases e ntragroup AGTL crosstalk e Intergroup AGTL crosstalk Non AGTL to AGTL crosstalk Monte Carlo Analysis Perform a Monte Carlo Analysis on the extracted baseboard Vary all parameters recommended for pre layout Monte Carlo Analysis within the regions in which they are expected to vary The ranges for some parameters will be reduced relative to those in the pre layout simulations For example baseboard lengths L1 through L7 should no longer vary across the full minimum and maximum ranges in the final baseboard design Instead baseboard lengths should now have an actual route with length tolerances specified by the baseboard fabrication manufacturer Validation Build systems and validate the design and simulation assumptions Measurements Note that the AGTL specification for signal quality is at the component pad The expected method of signal quality determination is to run analog simulations for the pin and the pad Then correlate the simulations at the pin with actual system measurements at the pin Good correlation at the pin leads to confidence that the simulation at the pad 1s accurate Controlling the temperature and voltage to correspond with the I O buffer model extremes should enhance the correlation between simulations and the actual system Flight Time Simulation As defined in Section flight time is the time difference between a signal crossing
44. s 9 80 024 jndu 28 10 759 ANVL 3QL aN 9 NI 83 NI OIN L 6 siaa 8d 9110 2 83 dH 2 0 10PF NPO C11 mf 10PF NPO C24 1 1 ro afno LO dH dH 1no oeueis oipny 26 9 3 0730 SI 95 71 0002 0 ad qasi 3u 1691 06956 VINHOJI1VO IWOS103 2 ALIO 006 1 mno NOIS3Gd 9Od 90 8 HASTY MHOMLAN ANY v9d94J WWIG Z L3SdIHO 3028 H 131NI 731111 80 SO 33 2 1538 OV E 8 6 SO 33 L 9 oL 9 8 xoi vl QNO 9 QNO LL QNS QNO GND 6 QNO 8 QNS 0 QNO 9v v 5 01 P 6 3AU3S3H E 8 3AH3S3H vea 4 3AH3S3u as 9 VOS ans vivdSWs lt 881569 3 u3s3u TOS ans 5 lt 881189 3 d3s3H 50 33 5957 lt 4 6 25 ezv 80 33 3Au3s3u Xe AOS s 29
45. v o3HH 2 0088 OdUH SHV OKO3HH 08038 nd 89 5 SON 58 o su OdlA 1 SERSVH 4 VESVH ce VH 2 O VH 6c VH 8c VH Le VH 9c VH SC VH LostVH 1 6 1 2 9HtVH 2 9 2 eHtVH 1 OL WH 1 68 92 VH LINH 1 9s VH S VH 1 ADDA ADDA AOO ADDA ADDA SEA ZEVV 7EM v LA vcHV 26QV G 2 0 46 96 ZEC 9EC 9EH 9EH YEA 7Z7E EHV VER VEj VEM PEAY vEJV CEH 9EM 9Ed 9EL 9EX 9EAV IENV VEC VEH HEN VEY PEA VEZ 268 264 28d QNO 828 82 920 ery 92 vea 4 20 erv zeIWv aNO 02802 61 6 9 81 4 88 73 7n v 9IWV ONO 90 8180 0 HAY ETV ZA ZH 8LOZN ZA ZZ QNO LENY LZ TV 9 DIV OZHV S LLLA 222 zEHV CEWV 0Eg 0 J vexv eca eerv sciWv 9cJ veca serv veWv a 98 90 24 81 95 24 21 ZAV ZAV ZAV 092604 224 0280 Lerv ozWv eLg Z r3 ZIev serv eLwv eLe era erev zHwv org ea erv siWv a 1HVd 1339085 0 6 lo e9 aH
46. 1 1 FWH Flash BIOS sys isa 820E 18 Design Guide InteP 820 Chipset Figure 3 Intel 820E Chipset Platform Dual Processor Performance Desktop Block Diagram Intel Pentium III Intel Pentium III Processor Processor Intel 820E Chipset w Intel 82820 Memorv cu AGP20 Controller Hub _ Memory gt 1 Controller MCH Direct RDRAM Hub PCI Slots e D Interface 4 IDE Drives UltraATA 100 66 33 2 4 USB Ports 2 AC 97 Codecs 97 2 1 optional Controller Hub Power Management Intel 82801BA 2 LAN Connect Clock Generators Other ASICs Super 1 0 System Management optional I 1 SMBus I C T FWH Flash BIOS sys bk 2P 820 Design Guide 19 Inte 820E Chipset 1 4 1 4 1 1 4 2 1 4 3 1 4 4 20 Platform Initiatives Direct Rambus RAM RDRAM The Direct Rambus RAM RDRAM initiative provides the memory bandwidth necessary to obtain optimal performance from the Pentium III processor as well as a high performance AGP graphics controller The MCH RDRAM interface supports
47. 45 2607 anro 9560 anro 412 8660 HMS ON so QNO 99 Ast SOA 1Q9S0IN8 9N oipny 16 99 Ov JO vL 1JJHS 91 01 0002 02 6 5 1577 99d 2 06986 INOS 104 ALIO 006 1534 WHOd1Vld 90d 9 raul a 90 v9d94J WIG 2 L3SdIHO 3028 H 131NI 3 1L n 4 baeo e eiu rudo AAA beant 9 484 12d _ ant 99 2 ALY VVV 652 A QNOV C22 xc 10PF NPO 1 o 5 LS ANL Y TINNI e at A 83 1 INT o iN NT 2 LR anl ven dcin fx AX ki gp 81 893 3N17 9 Y 620 gt El L Nx E Boyeuy uy eur u OT WINI c LNO IANI dde INYL 4N L 9 8NI SSVdA8 SSVdA8 OV use 4 81019 uuww Se WNT 47 d vino 99 ogg b a z o lt 81 dH t 8 LAO SOOA vd 2
48. AVggr AVggr has a value of 100 mV which accounts for the following noise sources Motherboard coupling Vrr noise noise 3 5 2 Ringback Levels The example topology covered in this guideline assumes a ringback tolerance allowed to within 200 mV of 2 3 Since is specified with an approximate total tolerance of 11 this implies a 2 3 Vrer range from approximately 0 89 V to 1 11 V This sets the absolute ringback limits as follows e 1 3 V 1 1 V 200 mV for rising edge ringback 0 69 V 0 89 V 200 mV for falling edge ringback A violation of these ringback limits requires flight time correction as documented in the Intel Pentium Processor Developer s Manual 3 5 3 Overdrive Region The overdrive region is the voltage range at a receiver from Vggr to Vrer 200 mV for a low to high going signal and from to 200 mV for a high to low going signal The overdrive regions encompass the guard band so when is shifted by for timing measurements the overdrive region does not shift by AV rer Figure 84 kepicts this relationship Corrections for edge rate and ringback are documented in the Intel Pentium II Processor Developer s Manual However there is an exception to the documented correction method The Intel Pentium Ill Processor Developer s Manual states that extrapolations should be made from the last crossing of the overdrive re
49. Chipset intel Figure 56 USB Data Signals Motherboard Trace Driver Optional d Motherboard Trace 2 Transmission Line USB Twisted Pair Cable Recommended USB trace characteristics Impedance Zo 45 4 Q Line delay 160 2 ps Capacitance 3 5 pF Inductance 7 3 nH e Resistance at20 C 53 9 2 14 3 Disabling the Native USB Interface of ICH2 The ICH2 native USB interface can be disabled This can be done when an external PCI based USB controller is being implemented in the platform To disable the native USB Interface ensure the differential pairs are pulled down thru 15 kQ resistors ensure the OC 3 0 signals are de asserted by pulling them up weakly to VCC3SBY and that both function 2 and 4 are disabled via the D31 FO FUNC_DIS register Ensure that the 48 MHz USB clock is connected to the 2 and is kept running This clock must be maintained even though the internal USB functions are disabled 2 15 ISA Support Implementations that require ISA support can benefit from the enhancements of the ICH2 while 15 less designs are not burdened with the complexity and cost of the ISA subsystem For an implementation of an ISA design contact external suppliers Design Guide 93 Inte 820E Chipset 2 16 2 17 94 intel APIC Design Recommendation UP systems not using the integrated I O APIC should comply with the following recomm
50. The most common physical layer design and layout mistakes in LAN on motherboard designs are as follows 1 Unequal length of the two traces within a differential pair Inequalities create common mode noise which will distort the transmit or receive waveforms 2 Lack of symmetry between the two traces within a differential pair For each component and or via that one trace encounters the other trace must encounter the same component or a via at the same distance from the PLC Asymmetry can create common mode noise and distort the waveforms 3 Excessive distance between the PLC and the magnetics or between the magnetics and the RJ 45 11 connector Beyond a total distance of about 4 inches it can become extremely difficult to design a spec compliant LAN product If they are long traces on FR4 fiberglass epoxy substrate will attenuate the analog signals Also longer traces will increase the impedance mismatch see mistake 9 The magnetics should be as close to the connector as possible lt 1 inch 4 Routing any other trace parallel to and close to one of the differential traces Crosstalk on the receive channel will degrade the long cable BER Crosstalk on the transmit channel can cause excessive emissions resulting in FCC test failure and can result a low transmission BER on long cables Other signals should be kept at least 0 3 inch from the differential traces 5 Routing the transmit differential traces next to the recei
51. intel InteP 820E Chipset Table 2 AGP 2x Data Strobe Association 2 6 2 7 AD 15 0 and C BE 1 0 AD STBO AD 31 16 and 3 2 AD STB1 SBA 7 0 SB STB In this example the lower address signals AD 15 0 are sampled on the rising and falling edges of AD STBO while the upper address signals AD 31 16 are sampled on the rising and falling edges of AD STBI When routing strobes and their associated data lines trace length mismatch is very important in addition to noise immunity The primary benefit of source synchronous strobing is that the data and the strobe arrive simultaneously at the receiver Thus a strobe and its associated data signals have very critical length mismatch requirements With well matched trace lengths as well as matched impedance the propagation delays for the strobe and the data will be very close Hence the strobe and the data arrive simultaneously at the receiver For some interfaces the trace length mismatch requirement 15 less than 0 25 inch Differential Clocking Strobing AGP 2x timings are referenced at a particular level on the rising or falling strobe edge while 4x timings are referenced to the crossover point of the differential strobes The crossover is targeted to be at 0 5 Vppo Direct RDRAM Interface The Direct RDRAM channel is a multi symbol interconnect Because of the length of the interconnect and the frequency of operation this bus is designed to allow multipl
52. operation Note that full power operation includes both the full on operating state and the S1 processor Stop Grant state state Suspend During suspend operation power is removed from some components on the operation motherboard The customer reference board supports two suspend states Suspend to RAM 53 and Soft Off S5 Power rails An ATX power supply has 6 power rails 5 V 5 V 12 V 12 V 43 3 V and 5 In addition to these power rails several other power rails are created with voltage regulators on the Intel 820E chipset reference board Core power rail These power rails are on only during full power operation These power rails are on when the PSON signal is asserted to the ATX power supply The following core power rails are distributed directly from the ATX power supply 5 V 12 V and 13 3 V Standby power rail These power rails are on during the suspend operation These rails also are on during full power operation These rails are on at all times when the power supply 18 plugged into AC power The only standby power rail that is distributed directly from the power supply is 5 5 V standby Other standby rails are created with voltage regulators on the motherboard Derived power rail A derived power rail is any power rail generated from another power rail using an on board voltage regulator For example 3 3 usually is derived on the motherboard fr
53. E s y pesn un A8S 81909150 HMS ON episxoeg d JO epis uo 1 205 0 6 9 eui utum ezis 9021 eq sjojoedeo Iv 2 220 6 10 vEIO 2600 86102 89 4610 9819 9819 2620 8920 880 220 6520 ABSE EDDA 5 1 Em Bujdnooeg 68628 Bujdnooeg 599 ux aiqissod se HOW 01 se OGGA 4 310 AGSSOOA AGSE EDDA JNVVONTZ SIA 09 ejqeino ji jeuonippe jo 41070 ppe osje SI eoi ep jo 4 10 0 pue 410 asn 1esdiuo 104 1619 1229 HNIS episyoeg 9519 29 2020 752 E 1920 6920 4910 2129 EN 8 LIDA HOW 8 190 HOW 3 F 094019 1 0 000z 02 157 06996 NOSTOA A ALIO 006 I j 3 moe 1530 99d 9 T 50
54. Example batteries are the Duracell 2032 2025 or 2016 or equivalent which provide many years of operation Batteries are rated by storage capacity The battery life can be calculated by dividing the capacity by the average current required For example if the battery storage capacity is 170 mAh assumed usable and the average current required is 3 A the battery life will be at least 170 000 3 56 666 h 6 4 years The battery voltage can affect the RTC accuracy In general when the battery voltage decays the RTC accuracy also decreases High accuracy can be obtained when the RTC voltage is within the range 3 0 V to 3 3 V The battery must be connected to the ICH2 via an isolation Schottky diode circuit The Schottky diode circuit allows the ICH2 RTC well to be powered by the battery when system power is unavailable but by system power when it is available For this purpose the diodes are set to be reverse biased when system power is unavailable The following figure is an example diode circuit Figure 60 Diode Circuit Connecting RTC External Battery VCC3_3SBY 1kQ VccRTC 1 0 RTC ext diode circ 98 Design Guide InteP 820 Chipset intel A standby power supply should be used in a desktop system to provide continuous power to the RTC when available which will significantly increase the RTC battery life and thereby increase the RTC accuracy 2 19 5 External RTCR
55. HUBREF hub IF ref div 2 The resistor values R1 and R2 must be rated at 1 tolerance The selected resistor values ensure that the reference voltage tolerance is maintained over the input leakage specification A 0 1 uF capacitor C1 in the previous circuits should be placed close to and R2 Also a 0 01 bypass capacitor C2 in the previous circuits should be placed within 0 25 inch of each HUBREF pin The trace length from the divider circuit to the HLREF pin must be no longer than 3 5 inches Design Guide intel 2 9 1 4 Table 17 2 9 1 5 2 10 Design Guide InteP 820E Chipset 8 Bit Hub Interface Compensation The hub interface uses a compensation signal to adjust buffer characteristics to the specific board characteristic The hub interface requires resistive compensation RCOMP The guidelines are as follows shown in the following table 8 Bit Hub Interface RCOMP Resistor Values Component Hub Interface Trace RCOMP Resistor Value Resistor Buffer Mode Impedance Tied to ICH2 Normal Single 600 15 400 2 39 0 196 VCC1 8 Normal Local 60 1596 30 0 196 Vss 50 10 25 Q 196 Vss MCH NormalSingle 60 15 40 2 39 1 VCC1 8 Normal Local 60 1596 30 0 196 Vss 50 1096 25 0 196 Vss The MCH also has a hub interface compensation pin This signal HLCOMP also requires the RCOMP method described f
56. Intel 820E Chipset Platform Clock Clock Symbols see Relationship Figure 86 Pin to Pin ps Pin NEL E Board ps Total ps PGA370 HCLK to PGA370 175 175 125 4125 300 300 HCLK DP only A leads E and or C leads E PGA370 HCLK to MCH HCLK DP only pum device AGPCLK L leads another L PCICLK to PCICLK 500 500 1500 1500 2000 2000 or L leads H 2 Fleas leads ICH2 66 to 66 CLK66 to CLK66 250 125 375 375 Worst case skew Worst case FWHCLK 500 1500 1500 2000 2000 between H L M and LPCCLK PCICLK N B leads D processor PICCLK leads 250 250 125 125 375 375 processor PICCLK B leads G and processor PICCLK leads ICH2 APICCLK NOTES 1 DP only 2 UP MCH and processor clock drivers are tied together to eliminate pin to pin skew 175 and 175 pin to pin skew apply only to DP UP only Clock drivers tied together to eliminate pin to pin skew The skew between any PCICLK clocks on any two inputs in the system The skew between any APIC clocks on any two inputs in the system If SSC is enabled an additional 40 ps must be added to the pin to pin skew If SSC is enabled an additional x60 ps must be added to the pin to pin skew Design Guide 165 Inte 820E Chipset 166 The following figure shows the Intel 820E chipset clock length routing guidelines Figure 87
57. Nc CNR Connector Circuit Notes 1 While it is possible to disable down codecs as shown above in Figure 53 it is recommended against for reasons cited in the ICHx AC 97 White Paper including avoidance of shipping redundant and or non functional audio jacks 2 All CNR designs include resistor The value of Rg is either 1 or 100 depending on the intended functionality of the CNR whether or not it intends to be the primary controlling codec 3 Any CNR with two codecs must implement with value 1 If there is one codec use 100 pull up resistor A CNR with zero codecs must not stuff Rg If implemented Rg must be connected to the same power well as the codec so that it is valid whenever the codec has power A motherboard with one or more codecs down must implement R with a value of 10 DN ENAB signal must be run to GPI so that the BIOS can sense the state of the signal DN is required to be connected to GPI a connection to GPIO is strongly recommended for testing purposes Table 18 Signal Descriptions DN ENAB When low indicates that the codec on the motherboard is enabled and primary on the AC 97 Interface When high indicates that the motherboard codec s must be removed from the AC 97 Interface held in reset because the CNR codec s will be the primary device s on the AC 97 Interface AC97_RESET Reset signal from the AC
58. REQ GNT pair RTC The ICH2 contains a real time clock RTC with 256 bytes of battery backed SRAM The internal RTC module provides two key functions keeping the date and time and storing system data in its RAM when the system 18 powered down This section will discuss the recommended hookup for the RTC circuit for the ICH2 This circuit is not the same as the circuit used for the PILX4 Design Guide intel 2 19 1 InteP 820E Chipset RTC Crystal The ICH2 RTC module requires an external 32 768 kHz oscillating source connected on the RTCX1 and RTCX2 pins The following figure shows the external circuitry that comprises the oscillator of the ICH2 RTC Figure 59 External Circuitry for the ICH RTC 2 19 2 Design Guide VCC3 3SBY VCCRTC RTCX2 LL 32768 Hz R1 Vbatnte Xtal 10 gt 4 x RTCX15 C1 B 0 047 uF 1 R2 cx 10 MO VBIAS C2 4 vss cir NOTES 1 The exact capacitor value must be based on the crystal maker s recommendation This circuit is not the same as the one used for VCOnrc Power for well RTCX2 Crystal input 2 Connected to the 32 768 kHz crystal RTCX1 Crystal input 1 Connected to the 32 768 kHz crystal VBIAS RTC bias voltage This pin is used to provide a reference voltage and this DC voltage sets a current that is mirrored throughout the oscillator and buffer circuitry Vss Groun
59. Setup Time Tsu CLKskew CLKurren Map lt Clock period Equation 5 Hold Time gt CLKskew Symbols used in these two equations Tco Max clock to output specification see Note Tsu MN Min required time specified to setup before the clock see Note clock edge to edge variation Max variation between components receiving the same clock edge Max flight time as defined in Section B I Trt mw Min flight time as defined in Section 1 Multi bit adjustment factor to account for SSO push out or pull in Tco Min clock to output specification see Note Min specified input hold time Note clock to output and setup to clock timings are both measured from the signal s last crossing of with the requirement that the signal does not violate the ringback or edge rate limits See the respective processor s datasheet and the Pentium Processor Developer s Manual for more details Solving these equations for yields the following equations Equation 6 Maximum Flight Time Clock period Tco Tsu CLKyitter Equation 7 Minimum Flight Time gt CLKskew Multiple cases must be considered Note that while the
60. Table 16 the HUBREF voltage specifications for normal and enhanced buffer modes and the associated resistor recommendations for the voltage divider circuit Design Guide 75 Inte 820E Chipset 76 Table 16 8 Bit Hub Interface HUBREF Generation Circuit Specifications Buffer Mode HUBREF Voltage Specification V Recommended Resistor Values for the HUBREF Divider Circuit Q Normal Single 1 2 Vcc 1 8 2 R1 R2 150 1 2 3 Vcc 1 8 2 R1 150 196 R2 301 196 The single HUBREF divider should not be located more than 4 inches away from either or 2 If the single HUBREF divider is located more than 4 inches away then the locally generated hub interface reference dividers should be used instead The reference voltage generated by a single HUBREF divider should be bypassed to ground at each component with a 0 0 uF capacitor located close to the component HUBREF pin If the reference voltage is generated locally the bypass capacitor must be close to the component HUBREF pin Example HUBREF divider circuits are shown in the following figures Figure 43 8 Bit Hub Interface with a Shared Reference Divider Circuit Normal Single Mode MCH ICH2 HLREF A HUBREF hub IF ref div 1 Figure 44 8 Bit Hub Interface with Locally Generated Reference Divider Circuits Normal Local Mode 1 8V 1 8 1 8 V 1 8V 2 HLREF
61. at the input pin of the receiver and the output pin of the driver crossing assuming it drives a test load The timings in the tables and topologies discussed in this guideline assume that the actual system load is 50 and is equal to the test load Although the DC loading of the AGTL bus in a DP mode is closer to 25 AC loading is approximately 29 since the driver effectively sees 56 termination resistor in parallel with a 60 Q transmission line on the Intel PGA370 socket Design Guide intel InteP 820E Chipset Figure 76 Test Load vs Actual System Load V Buffer IT Riest lt Test load Vcc Driver pad Driver pin Vit Buffer Actual system load R Vcc Driver pad Receiver pin TELIGHTSYSTEM test actual load The previous figure shows the different configurations for testing and flight time simulation The flip flop represents the logic input and driver stage of a typical AGTL buffer Tco timings are specified at the driver pin output usually is reported by a simulation tool as the time from the driver pad starting its transition to the time when the receiver s input pin sees a valid data input Since both timing numbers include propagation time from the pad to the pin it is necessary to subtract this time from the reported flight time to avoid double counting Trepp is defined as th
62. 0iSvigu ox NV1 i27 da B NYI 12 02 61 lt 0261 lt gg 030v 9i Wau VOV NIE 24 46 NYT ID 27 lt 9 GS NVI 13101 i 9 aar NYT SE T 9 10X9 NYT 9 oaxe NYT yrs 120261 lt E NYI ozer 998 NVI Sh WoL 13e3ur lt 4 9 96 92 L 9 2 Sc 00 dar NYT A8SE A8SE NO SLN3NOdMWOO T1V ALdWA NOILVYNDISNOO NY 13INOH HOS 310 IN3 L329828 NVI 2 Or 6L 0002 02 6 s 06966 NOSTOA ALIO 006 NMYHd 1634 908 0 v9d9J WWI Z L3SdIHO 3028 H 131NI QN5 oQH 120281 Wad ON ON JON NYT 120281 VON 03703395 NR AU nan 066 0281 lt pon aan qa3novNvi WoL NYT VON sot Nv1 df 100 6 0 028 21 gt A8S EDDA A8SE 02821 Qa 429628 104 1179 2 Or 02 99 91 0
63. 28 shows the use of CTABs on the top and bottom layer for bottom layer RSL and clocking signals routed between RIMMs Figure 28 Bottom Layer CTABs Split across the Top and Bottom Layer to Achieve an Effect Cerf 1 35 pF 2 7 2 5 RSL Signal Layer Alternation RSL signals must alternate layers as they are routed through the channel If a signal is routed on the primary layer from the MCH to the first RIMM socket it must be routed on the secondary layer from the first RIMM to the second RIMM as shown in Figure 29 signal B If a signal is routed on the secondary layer from the MCH to the first RIMM socket it must be routed on the primary side from the first RIMM to the second RIMM as shown in Figure 29 signal A Signals can be routed on either layer from the last RIMM to the termination resistors Design Guide 49 Inte 820E Chipset Figure 29 RSL Signal Layer Alternation Signal B Signal on secondary side om om om Signal on primary side Signal A Signal A y Route on EITHER layer MCH Ground isolation is REQUIRED Signal B sig lay alter vsd Table 7 RSL Routing Layer Requirements 2 7 2 6 50 to 1st RIMM 1st RIMM to 2nd RIMM Method 1 Secondary side Length Matching Methods To allow for greater routing flexibility the RSL signals require pad to pin length matching between the MCH and the
64. 3 3 V 806 0 022 rx pn rx tx n Phone modem 8 Shield ground lO subsys 82562EH term The filter and magnetics component T integrates the required filter network high voltage impulse protection and transformer to support the HomePNA LAN interface One RJ 11 jack labeled LINE in the previous figure allows the node to be connected to the phone line and the second jack labeled PHONE in the previous figure allows other down line devices to be connected at the same time This second connector is not required by the HomePNA However typical PCI adapters and PC motherboard implementations are likely to include it for user convenience A low pass filter set up in line with the second RJ 11 jack also is recommended by the HomePNA to minimize interference between the HomeRun connection and a POTS voice or modem connection on the second jack This restricts the type of devices connected to the second jack because the pass band of this filter is set at approximately 1 1 MHz Please refer to the HomePNA website for up to date information and recommendations regarding the use of this low pass filter to meet HomePNA certifications 113 Inte 820 Chipset 2 22 3 5 intel Critical Dimensions As shown in the following figure there are three dimensions to consider during layout Distance B from the line RJ11 connector to the magnetics module distance
65. 6 325 inches long 63 Inte 820E Chipset intel The strobe signals AD STBO AD STB0OZ AD STB1 AD 5 15 SB STB and SB STB act as clocks on the source synchronous AGP interface Therefore special care must be taken when routing these signals Because each strobe pair 1s truly a differential pair the pair should be routed together For example AD STBO STBO should be routed next to each other The two strobes in a strobe pair should be routed on 5 mil traces with at least 20 mils of space 1 4 between them This pair should be separated from the rest of the AGP signals and all other signals by at least 20 mils 1 4 The strobe pair must be length matched to less than 0 1 inch 1 a strobe and its complement must be the same length within 0 1 inch Interfaces The 2 4 timing domain signals be routed with 5 mil spacing when breaking out of the The routing must widen to the documented requirements within 0 3 inch of the MCH package When matching the trace length for the AGP 4x interface all traces should be matched from the ball of the MCH to the pin on the AGP connector It is not necessary to compensate for the length of the AGP signals on the MCH package Reduce line length mismatch to ensure added margin To reduce trace to trace coupling crosstalk separate the traces as much as possible signals in a signal group should be routed on the same layer The tr
66. 97 Digital Controller ICH2 SDATA_INn AC 97 serial data from an AC 97 compliant codec to an AC 97 compliant controller i e the ICH2 Design Guide 89 Inte 820E Chipset intel Valid Codec Configurations Table 19 Codec Configurations Valid Codec Configurations Invalid Codec Configurations AC Primary X any other type of codec MC Primary AMC Primary AMC Secondary AMC Primary AMC Primary MC Secondary AC Primary MC Secondary AC Primary AC Secondary AC Primary AMC Secondary 2 13 2 Communication and Networking Riser CNR Related Documents Communication Network Riser Specification Revision 1 1 available at http developer intel com technology cnr The Communication and Networking Riser CNR Specification defines a hardware scalable Original Equipment Manufacturer OEM motherboard riser and interface This interface supports multi channel audio V 90 analog modem phone line based networking and 10 100 Ethernet based networking The CNR specification defines the interface which should be configured prior to shipment of the system Standard I O expansion slots such as those supported by the PCI bus architecture are intended to continue serving as the upgrade medium The CNR mechanically shares a PCI slot Unlike the AMR the system designer will not sacrifice a PCI slot if they decide not to include a
67. C from the phone RJ11 to the LPF if implemented and distance from the Intel 82562 component to the magnetics module Figure 71 Critical Dimensions for Component Placement 114 Line RJ11 Phone FN e IO subsys crit dim comp plac Intel amp Magnetics module 82562EH Hi EEPROM ome 0 2 22 3 5 1 Distance from Magnetics Module to Line RJ11 Distance B should be given highest priority and should be less then 1 inch Regarding trace symmetry route differential pairs with consistent separation and with exactly the same lengths and physical dimensions Asymmetry and unequal length in differential pairs contribute to common mode noise This can degrade the receive circuit performance and contribute to radiated emissions from the transmit side 2 22 3 5 2 Distance from Intel 82562EH Component to Magnetics Module Due to the high speed of signals present distance between the Intel 82562 component and the magnetics also should be less than 1 inch but it should be second priority relative to the distance from the connects to the magnetics module In general any trace section intended for use with high speed signals should comply with the proper termination practices Proper signal termination can reduce reflections caused by impedance mismatches between devices and trace routes A signal s reflection may contain a high frequency component that may contrib
68. Circuit Board PCB Test Methodology Document order 298179 should be used to ensure boards are within the 28 10 requirement The Intel Controlled Impedance Design and Test Document should be used for the test coupon design and implementation These documents can be found 178 rdram htm Select Application Notes Design Guide InteP 820 Chipset intel 5 1 4 Recommended Stack Up Though numerous stack up variations are possible the following starting point is recommended W 18 mils H 4 5 mils T 2 0 1 ply 2116 prepreg For other possibilities see the following table and the following figures Table 61 28 Stack Up Examples 61 0 5 1 5 Inner Layer Routing Inner layer routing also has many possible stack ups For inner layer routing it is advisable to use the following starting point W 13 5 mils 7 mils H2 5 1 2 If these parameters are used the initial should fall within the acceptable limit 28 10 Figure 98 khows examples of both stripline and microstrip cross sections 179 Design Guide Inte 820E Chipset 5 1 6 180 Figure 98 Microstrip a and Stripline b Cross Section for 28 O Trace a Microstrip cross section for 28 O trace 10 mils 18 mils 6 15 2 1 mils b Stripline cross section for 28 O trace 13 5 mils 5 mils 2 9 gt 4 2 mils 1 2 mils 4 x sect
69. Layout Recommendations Yes No Comments 20 Isolate I O signals from high speed signals To minimize crosstalk 21 Place the 82562ET EM part more than 1 5 inches This minimizes the potential of EMI from any board edge radiation problems 22 Verify the EEPROM size Thelntel 82562EM requires a larger EEPROM to store the alert 82562ET 64 word envelope and other configuration 82562EM 256 word information 23 Place at least one bulk capacitor 2 4 7 uF is OK Research and development has on each side of the 82562ET EM shown that this is a robust design 24 Place decoupling caps 0 1 uF as close as possible to the 82562ET EM 25 RBIAS10 and RBIAS100 resistors should have 1 These biasing resistors require 1 values accuracy Note that the values shown on the reference schematic are the recommended starting values Fine tuning via IEEE conformance testing is required for each new design Layout Recommendations Yes No Comments 1 Zo 97 60 Q 1596 2 5 mil trace width 5 mil spacing between traces 3 Max trace length ICH2 codec CNR 14 inches CH2 Decoupling Layout Recommendations Yes No Comments 1 3 3Vcore Six 0 1 caps 2 3 3VSBY One 0 1 uF cap 3 CPUI F VCCcore One 0 1 uF 4 1 8Vcore Two 0 1 uF caps 5 1 8VSBY One 0 1 uF cap 6 5VREF One 0 1 cap 7 5VREFSBY One 0 1 uF cap 8 Place decoupling caps as close as possible to the Design Guide InteP 820 Chipset intel Table 49
70. Note Note 186 intel 2 5 VBSY The 2 5 power plane is used to power the RDRAM core and the VCMOS rail on the RDRAMs The RDRAM core requires an approximately 4 5 maximum average DC current at 2 5 V In the Intel 820E chipset reference board the 2 5 plane is derived from the 5 V dual power plane using switching regulator During the maximum load step of 2 A the maximum voltage fluctuation must be less than 50 mV The maximum tolerance for 2 5 V is 125 mV However during any 10 period the voltage cannot fluctuate more than 50 mV The high frequency bypassing requirements are satisfied using capacitors on the RIMM itself Low frequency bypass requirements vary depending on the voltage regulator used By using a switching regulator with a relatively slow response time the low frequency bypass recommendation is eight 100 uF bulk capacitors 0 1 ESR near the RIMM connectors By using a linear regulator with a substantially faster response time the low frequency bypass requirement could be reduced The VCMOS rail requires a maximum of 3 mA at 1 8 V This rail must be powered during Suspend to RAM Therefore the VCMOS rail cannot be connected to the MCH core power Because the current requirements of VCMOS so low a resistor divider can be used to generate VCMOS from 2 5 Vsgy The resistor divider should be 36 Q top 100 Q bottom Additionally it should be bypassed with a 0 1 chip capacitor
71. Slots PCI Bus 1 1 1 97 Codec s AC 97 2 1 Power Management optional Controller v e BA Clock Generators LAN Connect Other ASICs 1 System Management optional 5 Super FWH Flash BIOS sys 820E Figure 2 Intel 820E Chipset Platform Performance Desktop Block Diagram with ISA Bridge Intel Pentium 9 III Processor 820E Chipset 1 Main Direct RDRAM 4x AGP Graphics Controller 1 1 Intel 82820 Memory Controller Hub MCH PCI Slots Hub Interface 4 IDE Drives 12 PCI Bus UltraATA 100 66 33 Le 1 1 1 1 1 1 1 1 1 1 1 1 1 ISA Bridge ISA 4USBPots 2HC 1 optional Slots 1 A 1 1 1 1 1 1 1 1 1 1 1 1 97 9724 optional 1 Controller Hub Power Management 1 Intel 82801 ICH2 LAN Connect Clock Generators 1 Other ASICs Super 1 0 4 System Management optional 1 1 SMBus l 2 LPCIF 1
72. The Intel reference board uses a switching regulator from 5 V dual It may be possible to use a linear regulator to regulate from 3 3 However the thermal characteristics must be considered Additionally a low dropout linear regulator would be necessary If 2 5 is regulated from 3 3 Vsp the 3 3 regulator must be able to supply enough current for all the 3 3 device requirements as well as the 2 5 Vspy requirements Refer to the 1 8 V power plane information for 1 8 V and 2 5 V power sequencing requirements This regulator is required in all designs However in systems that do not support STR the 2 5 V rail is powered from either the 3 3 V or 5 V core well 1 8V The 1 8 V plane powers the core the ICH2 hub interface s I O buffers and the RDRAM termination resistors This power plane has a total power requirement of approximately 1 7 A The 1 8 V plane should be decoupled with a 0 1 uF and 0 01 uF chip capacitor at each corner of the and with a single 1 uF and 0 1 uF capacitor at the ICH2 This regulator is required in all designs Power must not be applied to the RDRAM termination resistors before applying power to the RDRAM core 2 5 Vspy in this design This can be guaranteed by placing a Schottky diode between 1 8 V and 2 5 V as shown in the Design Guide intel InteP 820E Chipset Figure 102 1 8 V and 2 5 V Power Sequencing Schottky Diode Note Note Design G
73. This 1 ns includes skew and jitter that originates on the motherboard add in card and clock synthesizer Clock skew must be evaluated not only at a single threshold voltage but at all points on the clock edge that fall within the switching range The 1 ns skew budget is divided such that the motherboard is allotted 0 9 ns of clock skew The motherboard designer determines how the 0 9 ns are allocated between the board and the synthesizer For the Intel 820E chipset platform s AGP clock routing guidelines refer to Chapter lelctocking General AGP Routing Guidelines The following routing guidelines are recommended for the optimal system design The main focus of these guidelines is the minimization of signal integrity problems on the interface of the Intel 820 chipset s MCH The following guidelines are not intended to replace thorough system validation on Intel 820E chipset based products Recommendations Decoupling For decoupling at least six 0 01 capacitors are required of which at least four must be within 70 mils of the outer row of balls on the See Figure 37 Evenly distribute the placement of decoupling capacitors in the AGP interface signal field Usealow ESL ceramic capacitor e g 0603 body type X7R dielectric naddition to the minimum decoupling capacitors bypass capacitors should be placed at vias that transition AGP signals from one reference signal plane to another In a typic
74. am 7 128 620 lev 9 anro Eno osve a 2809 028 1 reav 028 5 rey mod 1 6v era 29278 FANE elv era 5 81 81 anro 210 828 gt HiNOd 8 4 pede sed phan aod TER m 099 sivc Si e vea LOLI awe viv viv vig ely 26 ev bd ziv 5 A8SE 4 92 4 52 VVV olv 018 oiv 018 e N 24085 mS 4 6v 68 6v 6a EY e e edaNods 8 92 92 8 ev 8 V OUld 92529 92 92 8 38 2550500 e mw ra oua Djs Ta 5 ec oz az ve g a Ould 9v 98 orm 9v 98 ZI occ 58 2 sa amp e 9292 lt ort 1014 orgy 4 Wig 2 e mzz 9262 SOON UE zv wold ae zv za 17 17 608 608 gt 82323418 5 06104 eon 0195 104 uoneoyioeds 22 10410 ees 104 BOOK 5 5 L 2 v ZN 6 9 8 Ov 30 92 193 t
75. clock signals CTM CTM and CFM CFM must be 14 mil wide and routed as shown in For all other sections B and C the clock signals must be routed with 18 mil wide traces A 22 mil ground isolation trace must be routed around the clock differential pair signals The 22 mil ground isolation traces must be connected to ground with a via every 1 inch A 6 mil gap Is required between the clock signals and the ground isolation traces For section A in the previous 0 021 inch of CLK per 1 inch of RSL trace length must be added to compensate for the clock s faster trace velocity as described in Section The and the CFM CFM differential signal pairs must be length matched to 2 mils in line section A For line section B use the trace length methods in Section For section D the trace length matching for is 2 mils and for section C 2 mil trace length matching is required for the signals The signals must be ground referenced with a continuous ground island plane from the DRCG to the last RIMM Trace Length For section in Figure 90 first RIMM to to first RIMM CTM CTM and CFM CFM must be length matched within 2 mils Exact trace length matching is recommended Package trace compensation as described in Section 72 1 via compensation and RSL signal layer alternation must also be completed on the clock signals Additionally 0 021 inch of CLK per
76. configured with an external weak pull down SPKR Pin Consideration The effective impedance of the speaker and codec circuitry on the SPKR signal line must be greater than 50 Otherwise the TCO Timer Reboot function will be disabled erroneously is used both as the output signal to the system speaker and as a functional strap The strap function enables or disables the TCO Timer Reboot function depending on the state of the SPKR pin on the rising edge of POWEROK When enabled the ICH2 sends an SMI to the processor when a TCO timer timeout occurs The status of this strap is readable via the REBOOT bit bit 1 D31 FO offset D4h The SPKR signal has a weak integrated pull up resistor which is enabled only during boot reset Therefore its default state when the pin is a no connect is a logical one or enabled To disable this feature a jumper can be populated to pull the signal line low see Figure 62 The value of the pull down must be such that the voltage divider caused by the pull down and integrated pull up resistors will be read as a Design Guide intel InteP 820E Chipset logic low When the jumper is not populated a low can still be read on the signal line if the effective impedance due to the speaker and codec circuit is equal to or less than that of the integrated pull up resistor Therefore it is strongly recommended that the effective impedance be greater than 50 and the pull down resistor b
77. cost of the Intel 820E chipset platform Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip Glue Chip 3 is designed to integrate some or all of the following functions into a single device By integrating much of the required glue logic into a single device the overall board cost can be reduced Features PWROK signal generation Control circuitry for Suspend to RAM Power supply power up circuitry RSMRST generation e Back feed cutoff circuit for Suspend to RAM e 5 V reference generation Flash INIT circuit HD single color LED driver e IDE reset signal generation PCIRST buffers e Voltage translation for audio MIDI signal e Audio disable circuit e Voltage translation for DDC to monitor e Tri state buffers for test 193 Inte 820E Chipset More information regarding this component is available from the vendors listed in the following table Table 64 Glue Chip Vendors Vendor Intel Contact Information Fujitsu Microelectronics Customer Response Center 3545 North 1st Street M S 104 San Jose CA 95134 1804 Phone 1 800 866 8600 Fax 1 408 922 9179 E mail fmicrc Dfmi fujitsu com Mitel Semiconductor Mitel Semiconductor 1735 Technology Drive Suite 240 San Jose CA 95110 Phone 408 451 4723 Fax 408 451 4710 URL mitelsemi car 194 Design Guide intel InteP 820E Chipset Appendix A Reference Design Schematics Uniprocessor D
78. determined that the amount of capacitance needed for RSL traces depends on the lengths that the signals have to travel though the RIMM connector pin 1 a signal on the bottom layer has to travel through more of the RIMM connector pin than a signal on the top layer As a result of the travel through the pin signals routed on the bottom layer have a larger inductance at the connector which causes a larger impedance discontinuity resulting in a possible reduction of voltage and timing margin on those signals As a result RSL traces on the bottom layer need more capacitive compensation than RSL traces routed on the top layer RSL signals routed on the bottom layer need 0 55 pF more compensation than signals routed on the top layer To compensate for the inductance of the connector approximately 0 65 pF to 0 85 pF compensating capacitive tabs C TAB are required for each topside RSL trace and approximately 1 20 pF 1 4 pF is required for each bottom side RSL trace Table 5 RSL and Clocking Signal RIMM Connector Capacitance Recommendations Design Guide RSL and Clocking Signal Routing Layer Capacitance pF Top 0 65 0 85 Bottom 1 20 1 40 47 Inte 820E Chipset intel The copper tab area for the recommended stack up was determined by means of simulation The amount of capacitance required is determined by the layer on which the RSL or clocking signal is routed The copper tabs can be placed on any sig
79. dummy transistor This transistor s base should be tied to ground 1 always turned off To minimize impedance discontinuities the traces for CMD and SCK must have a neckdown from 18 mil traces to 5 mil traces for 175 mils on either side of the SCK CMD attach point as shown in Figure 35 Figure 35 RDRAM CMOS Shunt Transistor 56 18 mils wide 18 mils 5 mils wide wide VCC5SBY 1175 mils 175 mils 2N3904 PWROK wf 2N3904 SCK 5 mils 18 mils wide 18 mils wide wide 175 175 mils mils 2N3904 CMD Tdram cmos shunt tran v Design Guide intel 2 7 5 2 7 6 InteP 820 Chipset Direct RDRAM Clock Routing Refer to Chapter Clocking the Intel 820E chipset platform s Direct RDRAM clock routing guidelines Direct RDRAM Design Checklist Use the following checklist as a final check to ensure that the motherboard incorporates solid design practices This list is only a reference For correct operation all of the design guidelines within this document must be followed Table 9 Signal List Design Guide RSL Signals High Speed Serial Clocks CMOS Signals CMOS Signal DQA 8 0 SIO 0818 0 SCK RQ 7 0 Ground isolation well grounded Via to ground every 0 5 inch around edge of isolation i
80. electrical characteristics between a dummy via and a real via Refer to the following section for more information on via compensation Via Compensation As described in Section all signals must have the same number of vias As a result each trace will have one via near the BGA pad because some RSL signals must be routed on the bottom of the motherboard Therefore it is necessary to place a dummy via on all signals that are routed on the top layer Because the electrical characteristics of a dummy via do not exactly match the electrical characteristics of a real via additional compensation must be performed for each signal that has a dummy via Each signal with a dummy via must have 25 mils of additional trace length That is Real via Dummy via 25 mils of trace length This 25 mils of additional trace length must be added to each signal routed on the top layer after length matching as documented in Section Figure 31 Dummy Via vs Real Via 2 7 2 8 Note 52 DUMMY Via REAL Via NN NN N Trace dum_vias_vs_real v Length Matching and Via Compensation Example Table 8 can be used to ensure that the RSL signals are the correct length 2000 mils was chosen as an example nominal RSL length Design Guide intel Table 8 Line Matching and Via Compensation Example Design Guide InteP 820E Chipset 1 2 3 4 5 6 7 8 9 10 Ball on Nominal Package Mother
81. euo 1528 je 105 4 14 21 yoo D e 9 093409 20 0002 02 6 prem GASIASH 1597 06966 VINHO4ITV9 NOSTOA 2 3v 59 ALIO 006 FLL 1534 99d 90 HOW Z 13SdIHO 3028 4 TALNI STL cad ff 20 I980H 2 01 HOW S O sso 081 pue ez 8 44004911531 zin 09 0H nn 65 v dWOOTH 8080 pr 42 9e Sc ve aV LOL 71 SOO WHO NILSH 99999555 8S GH 818804 024 82846388 ZTA ZS 0H 8258 988 ETA 988 bio E ES 229 328 MOHON 82535009 Ss OH erm x 49 aba 8535928 PS AH TETI 8 2 viO3HH z gts 6880 zw 8 SUSLER ZHO3HH om sza 9 gt vo Os 0H
82. host so the signal will rise more slowly as the capacitor charges The drive can detect the difference in rise times and will report the cable type to the BIOS when it sends the IDENTIFY DEVICE packet during the system boot as described in the ATA 66 specification 82 Design Guide intel InteP 820E Chipset 2 12 4 Primary IDE Connector Requirements Figure 48 Connection Requirements for Primary IDE Connector PCIRST_BUF 22 47 0 PCIRST gt Reset PDD 15 0 PDA 2 0 PDCS1 PDCS3 PDIOR PDIOW PDDREQ 3 3V 3 3 V 4 7 KQ 5 8 2 10 Primary IDE Connector PIORDY IRQ14 PDDACK GPIOx PDIAG CBLID 10 CSEL Pins 32 amp 34 ICH2 Due to ringing PCIRST must be buffered IDE primary conn require NOTES 1 Design Guide 22 to 47 series resistors are required on RESET The correct value should be determined for each unique motherboard design based on the signal quality 2 An 8 2 kO to 10 kO pull up resistor is required on IRQ14 and IRQ15 to VCC3 3 4 A 4 7 pull up resistor to VCC3 is required on PIORDY and SIORDY Series resistors can be placed on the control and data lines to improve signal quality The resistors are place as close as possible to the connector Values are determined for each unique motherboard design A 10 pull down resistor to ground is required on the PDIAG CBLID signal This prevents the pin fro
83. is the largest flight time a network will experience under all variations of conditions Maximum flight time 15 measured at the appropriate guard band boundary Minimum Flight Time is the smallest flight time a network will experience under all variations of conditions Minimum flight time 15 measured at the appropriate Veer guard band boundary GTL GTL 4 the bus technology used by the Pentium Pro processor is an incident wave switching open drain bus with pull up resistors that provide both the high logic level and termination It is an enhancement of GTL Gunning Transceiver Logic technology Network Trace of a printed circuit board PCB that completes an electrical connection between two or more components Network length Distance between extreme bus agents on the network It does not include the distance of the connection between the end bus agents and the termination resistors Overdrive region Voltage range at a receiver located above and below for signal integrity analysis Overshoot Maximum voltage allowed for a signal at the processor core pad See each processor s datasheet for the overshoot specification Pad A feature of a semiconductor die contained within an internal logic package used to connect the die to the package bond wires A pad is only observable in simulation Pin A feature of a logic package used to connect the package to an internal substrate
84. must be controlled when the PCB is fabricated The best impedance control specification method for each situation must be determined The use of stripline transmission lines where the trace is between two reference planes is likely to yield better results than microstrip where the trace is on an external layer using an adjacent plane for reference with solder mask and air on the other side of the trace This is due partly to the difficulty of precisely controlling the dielectric constant of the solder mask as well as the difficulty of limiting the plated thickness of microstrip conductors which can substantially increase crosstalk The recommended effective line impedance Zerr is 60 Q 15 where Zerr is defined by Effective Impedance 3 4 3 Power Reference Planes PCB Stack Up and High Frequency Decoupling 3 4 3 1 Power Distribution Designs using the Pentium processor require several different voltages The following paragraphs describe some effects of two common methods used to distribute the required voltages Refer to the Flexible Motherboard Power Distribution Guidelines for more information on power distribution The most conservative method of distributing these voltages is for each of them to have a dedicated plane If any of these planes is used as an AC ground reference for traces to control trace impedance on the board then the plane must be AC coupled to the system ground plane This method may require mo
85. of a modem codec Several system options exist when implementing AC 97 The ICH2 integrated digital link allows several external codecs to be connected to the ICH2 The system designer can provide audio with an audio codec a modem with a modem codec or an integrated audio modem codec Figure 4C The digital link is expanded to support two audio codecs or a combination of an audio and modem codec Figures 4A and 4B The modem implementations for different countries must be taken into consideration because telephone systems may vary By using a split design the audio codec can be on board and the modem codec can be placed on a riser Intel is developing an AC 97 digital link connector With a single integrated codec or AMC both audio and modem can be routed to a connector near the rear panel where the external ports can be located The digital link in the ICH2 is compliant with Revision 2 1 of the AC 97 specification so it supports two codecs with independent PCI functions for audio and modem Microphone input and left and right audio channels are supported for a high quality two speaker audio solution Wake on Ring from Suspend also 18 supported with the appropriate modem codec The ICH2 expands the audio capability with support for up to six channels of PCM audio output full AC3 decode Six channel audio consists of Front Left Front Right Back Left Back Right Center and Woofer for a complete surround sound effect ICH2 has expanded
86. pull down resistors should be placed on the USB Connector side of the series resistors on the USB data lines P0 P3 and are REQUIRED for signal termination by USB specification The length of the stub should be as short as possible The trace impedance for the P0 P3 signals should be 45 ohms to ground for each USB signal P or P Using the stackup recommended in section 6 1 USB requires 9 mils traces The impedance is 90 Q between the differential signal pairs P and P to match the 90 Q USB twisted pair cable impedance Note that twisted pair characteristic impedance of 90 Q is the series impedance of both wires resulting in an individual wire presenting a 45 Q impedance The trace impedance can be controlled by carefully selecting the trace width trace distance from power or ground planes and physical proximity of nearby traces USB data lines must be routed as critical signals The P P signal pair must be routed together parallel to each other on the same layer and not parallel with other non USB signal traces to minimize crosstalk Doubling the space from the P P signal pair to adjacent signal traces will help to prevent crosstalk Do not worry about crosstalk between the two P P signal traces The P P signal traces must also be the same length This will minimize the effect of common mode current on EMI Lastly do not route over plane splits s the recommended USB schematic 92 Design Guide InteP 820
87. radiated noise levels To reduce coupling noisy logic grounds should be separated from analog signal grounds Noisy logic grounds sometimes can affect sensitive DC subsystems such as analog to digital conversion operational amplifiers etc All ground vias should be connected to every ground plane Similarly every power via should be connected to all power planes at equal potential This helps reduce circuit inductance It also is recommended to physically locate grounds so as to minimize the loop area between a signal path and its return path Rise and fall times should be as slow as possible Because signals with fast rise and fall times contain many high frequency harmonics significant radiation can result The most sensitive signal returns closest to the chassis ground should be connected This results in a smaller loop area and reduces the likelihood of crosstalk The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software Terminating Unused Connections In Ethernet designs it is common practice to terminate unused connections on the RJ 45 connector and the magnetics module to ground Depending on overall shielding and grounding design grounding may be to the chassis ground signal ground or a termination plane Care must be taken when using various grounding methods to insure that emission requirements are met The method most often implemented is use of a floating termination plane wh
88. separately The maximum allowable length of the AGP interface is 7 25 inches Interfaces 6 Inches If the interface is less than 6 inches a minimum 1 3 trace spacing is required for 2 4 lines data and strobes These 2x 4x signals must be matched to their associated strobe within 40 5 inch These guidelines are for designs that require less than 6 inches between the AGP connector and the MCH For example if a set of strobe signals e g AD STBO and AD_STBO are 5 3 inches long the data signals associated with those strobe signals e g AD 15 0 and C BE 2 0 can be 4 8 inches to Design Guide InteP 820 Chipset 5 8 inches long Another strobe set e g SB STB and SB_STB could be 4 2 inches long and the data signals associated with those strobe signals e g SBA 7 0 can be 3 7 inches to 4 7 inches long The strobe signals AD STBO AD STB0Z AD STB1 AD STBI SB STB and SB STB act as clocks on the source synchronous AGP interface Therefore special care must be taken when routing these signals Because each strobe pair 18 truly a differential pair the pair should be routed together For example AD STBO STBO should be routed next to each other The two strobes in a strobe pair should be routed on 5 mil traces with at least 15 mils of space 1 3 between them This pair should be separated from the rest of the AGP signals and all other signals by at least 20 mils 1 4 The strobe pair
89. should be minimized The maximum trace length 15 500 mils 4 2 2 1 to DRCG Processor div2 VddIR Used as a reference for 2 5 V signaling Figure 88 CK133 to DRCG Routing Diagram 6 mils 6 mils 6 mils 6 mils 6 mils 9 gt Ground Ground CPU div2 Ground 1 4 mils 6 mils 6 mils 6 mils 6 mils 4 5 mils Ground Power Plane 1 4 mils Ck133 drcg route VddIR and CPU div2 must be routed as shown in Note that the VddIR pin can be connected directly to 2 5 V near the DRCG if the 2 5 V plane extends near the DRCG However if a 2 5 V trace must be used it should originate at the CK133 and be routed as shown 168 Design Guide intel InteP 820E Chipset 4 2 3 MCH to DRCG PclkM PclkN VddIPD Figure 89 MCH to DRCG Routing Diagram 6 mils 6 mils 6 mils 6 mils 6 mils 6 mils gt gt gt 4 gt 4 5 mils Ground Power Plane 1 4 mils drog route Hclkout and VddIPD should be routed as shown in Note that the VddIPD pin can be connected directly to 1 8 V near the DRCG if the 1 8 V plane extends near the DRCG However if a 1 8 V trace must be run it should originate at the MCH and be routed as shown The maximum length for Hclkout and Rclkout is 6 inches Additionally Hclkout and Rclkout must be length ma
90. signal or SDIN signal OR gate will be erroneous going to the CNR connector If there is no codec on the system board then both AC SDIN 1 0 should be pulled down externally with resistors to ground No extra pull down resistors are required When nothing is connected to the link the BIOS must set a shut off bit for the internal keeper resistors to be enabled At that point pull ups pull downs are not required on any of the link signals AC SYNC No extra pull down resistors are required Some implementations add termination for signal integrity Platform specific Design Guide intel Table 39 Miscellaneous Signals InteP 820E Chipset Checklist Items Recommendations Reason Effect SPKR No extra pull up resistors Has integrated pull up with a resistance between 18 and 42 The integrated pull Effective impedance due to speaker and up is enabled only during boot reset for codec circuitry must be greater than 50 strapping functions At all other times the pull kQ ora means to isolate the resistive up is disabled load from the signal while PWROK is low must be found A low effective impedance may cause the TCO Timer Reboot function to be erroneously disabled TP 0 Requires external pull up resistor to This signal is used for BATLOW in mobile but VCCSUS3 3 it is not required for desktop FS 0 Route to a test point ICH2 contains an integrated pull up for
91. support for two audio codecs on the AC 97 digital link 23 Inte 820E Chipset Figure 4 A C AC 97 Connections 4A AC 97 with Audio Codecs 4 Channel Secondary AC 97 Digital Link 0000 2 360 EBGA Audio Port 0000 Audio Port 4B AC 97 with Modem and Audio Codecs Modem Port AC 97 Modem AC 97 Digital Codec ICH2 360 Link EBGA gt L AC97 Audio lt gt Codec gt Audio Port 4C AC 97 with Audio Modem Codec Modem Port AC 97 Digital ICH2 360 Link EBGA Audio Port AC97 conn 24 Design Guide intel 1 4 10 Design Guide InteP 820E Chipset Low Pin Count LPC Interface In the Intel 820E chipset platform the super I O component has migrated to the Low Pin Count LPC interface Migration to the LPC interface enables lower cost super I O designs The LPC super I O component requires the same feature set as traditional super I O components It should include a keyboard and mouse controller floppy disk controller and serial and parallel ports In addition to the super I O features an integrated game port is recommended because the AC 97 interface does not provide support for a game port In systems with ISA audio the game port typically existed on the audio card The fifteen pin game port connector provides for two joysticks and a two wire MPU 401 MIDI interface Consult your super I O vendor for a comprehens
92. suspend power pins The 3 3 Vaux requirement states that during suspend the system must deliver 375 mA to each wake enabled card and 20 mA to each non wake enabled card During full power operation the system must be able to supply 375 mA to each card Therefore the total current requirement is as follows Full power operation 375 mA x number of PCI slots e Suspend operation 375 20 x number of PCI slots 1 In addition to the PCI 3 3 Vaux the ICH2 suspend well power requirements must be considered as shown in Error Reference source not found This regulator is required in all designs 187 Inte 820E Chipset 6 1 3 188 intel 1 8 VSB The 1 8 Vsg plane powers the logic to the resume well of the ICH2 This should not be used for VCMOS The VCMOS described in the 2 5 Vsgy section should be powered down S5 However the 1 8 requires power in S5 Refer to the 2 5 section for information regarding powering the VCMOS 1 8 V rail 2 5V The 2 5 V plane supplies power to the CK133 and the DRCG system clock generator components ICH2 1 8 V 3 3 V Power Sequencing The ICH2 has two pairs of associated 1 8 V and 3 3 V supplies These are 8 Vcc3 3 VccSusl_8 VecSus3_ 3 The ICH2 m has a third pair VccLANI 8 VccLAN3 3 These pairs are assumed to power up and power down together The difference between the two associated supplies must never be greater than 2 0 V The
93. to SB STB pull up to Vppo AD STB 1 0 pull down to ground SB STB Z pull down to ground The trace stub to the pull up pull down resistor on 2x 4x timing domain signals should be kept to less than 0 1 inch to avoid signal reflections from the stub The pull up pull down resistor value requirements are shown in the following table 4 16 recommended pull up pull down resistor value is 8 2 Design Guide InteP 820E Chipset intel 2 8 10 1 Signal Voltage Tolerance List The following signals on the AGP interface are 3 3 V tolerant during a 1 5 V operation e INTA INTB e GPERR GSERR e CLK e RST The following signals on the AGP interface are 5 V tolerant refer to the USB specification e USB e USB OVRCNT The following signal is a special AGP signal which is either grounded or not connected on card TYPEDET Note All other signals on the AGP interface are in the group They are not 3 3 V tolerant during a 1 5 V AGP operation 2 8 11 Motherboard Add in Card Interoperability Currently there are three AGP connectors e 3 3 V AGP connector e 1 5 V connector Universal AGP connector To maximize add in flexibility it is highly advisable to implement the universal connector in an Intel 820 chipset based system add in cards are either 3 3 V or 1 5 V cards Due to timings 4x
94. trace Ringback Voltage that a signal rings back to after achieving its maximum absolute value Ringback may be due to reflections driver oscillations etc See the respective processor s datasheet for the ringback specification Settling limit Defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition See the respective processor s datasheet for the settling limit specification Setup window Time between the beginning of Setup to Clock Tsu and the arrival of a valid clock edge This window may differ for each type of bus agent in the system Design Guide 3 2 Design Guide InteP 820E Chipset Term Definition Simultaneous Difference in electrical timing parameters and degradation in signal quality caused switching by multiple signal outputs simultaneously switching voltage levels e g high to output SSO low in the direction opposite to a single signal e g low to high or in the same effects direction e g high to low These are respectively called odd mode switching and even mode switching This simultaneous switching of multiple outputs creates higher current swings that may cause additional propagation delay or push out or a decrease in propagation delay or pull in These SSO effects may affect the setup and or hold times and are not always taken into account by simulations Syst
95. voltages It can be tied to RESUMEPWROK on desktop platforms Table 35 Processor Signals Checklist Items Recommendations Reason Effect 20 CPUSLP IGNNE INIT INTR NMI SMI STPCLK Internal circuitry has been added to the ICH2 External pull up resistors are not needed Push pull buffers now drive the output signals FERR Requires a weak external pull up resistor For specific values refer to the to VCCcore processor documentation for the processor that the platform utilizes RCIN Pull up signals to Vcc 3 3 through a 10 kQ Typically driven by an open drain resistor external microcontroller A20GATE CPUPWRGD Connect to the processor PWRGOOD For specific values refer to the input Requires a weak external pull up resistor to VCCcore processor documentation for the processor that the platform utilizes Design Guide 129 Inte 820E Chipset 130 Table 36 System Management intel Checklist Items Recommendations Reason Effect SMBDATA Requires external pull up resistors to 3 3 V Value of pull up resistors is determined SMBCLK or 3 3 V standby by the line load Open drain signal in resume well SMBALERT See GPIO section if SMBALERT not GPIO 11 implemented SMLINK 1 0 Requires external pull up resistors to 3 3 V Open drain signal in resume well INTRUDER Pull signal to Vgar if not needed Signal in VCCRTC well
96. 0 A Intel 82562ET 0 5 to 7 3 to 10 A Dual footprint 0 5 to 6 5 3 5 to 10 A Intel 82562ET EH card see 0 5 to 6 5 2 5 to 9 A 0 5 to 3 Note Note The total trace length should not exceed 13 inches Additional guidelines for this configuration are as follows e Stubs due to the resistor pack should not be present on the interface The resistor pack value can be 0 or 22 O LAN on motherboard PLC can have a dual footprint configuration Signal Routing and Layout LAN connect signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface specification The following are general guidelines that should be followed It is recommended that the board designer simulate the board routing to verify that the specifications are met for flight times and skews resulting from trace mismatch and crosstalk On the motherboard the length of each data trace is either equal to or up to 0 5 inch shorter than the LAN trace should always be the longest motherboard trace in each group See 105 Inte 820E Chipset Figure 67 LAN CLK Routing Example 2 22 1 5 2 22 1 6 2 22 1 7 106 he Crosstalk Consideration Crosstalk induced noise must be carefully minimized Crosstalk is the principal cause of timing skews and is the largest part of the amp skew parameter I
97. 002 02 6 GIAN iVi 06966 NOSTOA 2954 ALIO 006 1634 908 0 v9d9J WIG Z L3SdIHO 3028 H 131NI GL AAA Ga3uov NVI vet NVI Xu DNIH dXH dIHO dQH EDDA BON VON BON ELON o Alei an ro NYT vL f 609 91 31INOOVuV 8E11H 420 Merl lt 618 dal NYI 6559 31 jou oq 310 68141 5 gain IN3 L329828 404 Sey 0730 12 t 16 1170002 02 6 5 15 1 90 99d v9d94J 2 LASdIHO 3028 4 TSLNI JILI L 3 06966 VINHO4ITV9 NOSTOA 2 ALIO 006 1534 WHOd1Vld 90d 02 61 81 TOV 1329928 100 62280 Wa29S28 100 1 50 1929928 100 28750 329928 026181 1313 NOLLdO WOHd33 4 16 80 SO 33 MIOHS 33 LNOd
98. 01 NDOT 391 lt 4 018 Waw1o1 01001 01007 1001 zza 11001 21091 21091 1091 71001 gt 4 0MOH1 Io ghoo1 MOHT Sig zwou1 1004 21008 21008 07008 0MOHH 1004 27004 21008 09H 07008 0MOHuH NC A16 A77 B14 6La vla ZZv 9L v100H 21008 V 21008 V L109H 01008 V V IMOHH OMOHY VCMOS1 85 1 8 S 8 V Sev 0109 WH3I pzy 91091 1109 221 1091 7100 zw 2091 5109 WHIL 1091 c 1001 0 702 Wear MOHT lt 88868 19889 VCC2 5SBY 88084 s v 880QH 48088 48008 800 Hoy 97 980949 ssa 78008 557 28008 798 y Zea 28008 v igoau V 8 08 8099 v H 1 voas 16g WH3L 9vOQU 7 IgOd 18001 oad VINOUM svody eed 7 08007 v svody 0800 WHAL Sodi Hey v wiodd 299 vou ei 8900 WH3L vOQH 288 188 2 v evoau WHSL vogi 9voai S8V evoau 58 9vod1 ev
99. 05 7 paad 1 181 18 LXOLY y gt AdHOIS 21 AGHOIS 12 p 5 p 020 s1SuOlu zy ISHOLY 5 2 lt 2100 8 1 X M E 5 5 3MOldd HAANHLNI Jen ES OL 1V8A r Mus Trac HOUId SOId Dg XE HI 22 c poi 6191 90109 90199 INS Odi 5 i ovaas 2180 19005 W31SAS ae ul L914 mE 321 1831V8WS L0Id9 Hay SS 167 238 o3uds sig 03499 TOSS 3H09 5 Bo R R 8 5 5 zzo VIVOBWS pp t i 19808 W jar SO OLY a vas grg 993 ivissns W 8 18 aN twas twas LSHWSH SISUWSU lt 9868 5 2 ovas owas Huy 25 2 223 fe SNISHMd SNISHMd df isd OlH 613 WSH 91 gisuwsu drea Bide UO 1V8A 0 04 20 468 418 358 dS 3 lt 5505 5005 8 Hes aS 3s Ju gt 98968 18 lt isda 5130 9009 5 HNBHL uy lt 8 42 6545 150 815908 amp 5 20199 Se d 18 5 5 EN 5 7 E 195004 rea 13998 22 2 9 gt gt 920199 lt gt S ein 28 SBE Ye 1 2 ZI E RON 8
100. 1 8 V supply may come up before the 3 3 V supply without violating this rule Although this generally is not practical in a desktop environment since the 1 8 V supply is typically derived from the 3 3 V supply by means of a linear regulator One serious consequence of violating this 2 V Rule is electrical overstress of oxide layers resulting in component damage Most ICH2 I O buffers are driven by the 3 3 V supplies but are controlled by logic powered by the 1 8 V supplies Thus another consequence of faulty power sequencing arises if the 3 3 V supply comes up first In this case the I O buffers will be in an undefined state until the 1 8 V logic is powered up Some signals defined as input only actually have output buffers that are disabled normally and the ICH2 may unexpectedly drive these signals if the 3 3 V supply is active while the 1 8 V supply is not Figure 103 8 an example power on sequencing circuit that ensures the 2 V Rule is obeyed This circuit uses a NPN Q2 and PNP Q1 transistor to ensure the 1 8 V supply tracks the 3 3 V supply The NPN transistor controls the current through PNP from the 3 3 V supply into the 1 8 V power plane by varying the voltage at the base of the PNP transistor By connecting the emitter of the NPN transistor to the 1 8 V plane current will not flow from the 3 3 V supply into 1 8 V plane when the 1 8 V plane reaches 1 8 V Design Guide intel InteP 820E Chipset Figure 103 Example 1 8
101. 1 inch of RSL trace length must be added to compensate for the clock s faster trace velocity as described in Section For line section B Figure 90 RIMM to RIMM the clock signals must be matched within 2 mils to the trace length of every RSL signal Exact length matching is preferred Design Guide intel For line section D DRCG to last RIMM the CTM CTM must be length matched within 4 InteP 820E Chipset 2 mils Exact matching is recommended For section C 4 signals Note signal trace sections A B is 4 2 mils 2 mil trace length matching is required for the The total trace length matching for the entire CTM CTM signal trace sections A B D and for the Exact length matching is recommended Figure 91 Differential Clock Routing Diagram Sections A C amp D 22 mils 14 mils 14 mils 22 mils Ground CLOCK 4 Ground 2 1 mils 6 mils 6 mils 6 mils 4 5 mils 4 5 mils Ground Power Plane t 1 4 mils diff clk routing Figure 92 Non Differential Clock Routing Diagram Section B 10 mils 18 mils 10 mils 4 Ground CLOCK CLOCK Ground 2 1 mils 6 mils 6 mils 4 5 mils 4 5 mils Ground Power Plane 1 1 4 mils non diff routing The differential pair signals require termination using either 27 Q 1 or 28 Q 2 resi
102. 10 HOW u Dod ois 212194 OIS 21199 OIS yer t 073 E os EE jo 21099 ras maS 8 gy Prod Veo sav3uds 59704 9 eyd cei EEO t 901549 84015049 t M 19d valu Diod 84015194 84018104 4d E 3001 66 138 001185 v 77 Av t XT9HON ee H prias zz SEN 1 7 1 SENA NLX nappa PUE 91 ndo 5 3401 3901 e qissod se uoys se s ndjno pesnun uo 54118 zoldv e eoldv esio 8 Chornooav 0219 2 L v E flao5nooiav 9 lt e 1 A NIX 55199 Z ste 2 9 z 5 z sr 2 REM 95 20 8610 9810 6222 9120 2020 1419 6610 2612 0619 0810 84 85159 S ZOOA 84 66130 uid 1e od deo Duidnooep 4 0
103. 191 av 08818 av 081 av 81585 81585 150 088150 08150 216 Hs 015 1171706819 ano7 308 SIRO TIAS NDOT 9919 LO WDHOi 4 99 INDD 208 074 D 303H6 IMONT ory 909 D uvda lt 4015 9 0MOU1 V di 840159 10 01 1 9 2819 tou 5 21091 195 71097 lod 01001 eragio 9 6638 00 8800 AHOWSIN ado 9 HOI 0 aiqissod se esojo se 60 pue 010 1800 HIN 3999 9979 HOW 1171706518 MMBT3904LT1 ASSSOO sjulod 60 01916 5 GZ 10 5 0 GWOT YOST 39 9 9 0f38 00 goa lo eliag oo reay em egoa 9 zagoa szav 9 zav 9 42 8 8 007 nn 492 8voa szav o VLOOATPLNS anol veav 9 4 TRU 9voa ezav lt lt 9 v6 6 8 E 1912 MOUMd et e 2IOHMd VOTI 99 yin VOGI VOG 9 12479 evoa pro vOa ozav 0205 zvoa 610 o i voa O 2 810 9 ASE EDDA
104. 2 9 1 3 Refer to Section 2 9 1 4 for the specific resistor value 8 Bit Hub Interface Data Signals The 8 bit hub interface data signal traces should be routed 5 mils wide with 20 mils trace spacing 5 on 20 These signals can be routed 5 on 15 for navigation around components or mounting holes To break out of the MCH and ICH2 package the hub interface data signals can be routed 5 on 5 The signal must be separated to 5 on 20 within 300 mils of the package The maximum hub interface data signal trace lengths the normal and enhanced buffer modes are 8 inches and 14 inches respectively Each data signal must be matched within 0 1 inch of the STB differential pair There is no explicit matching requirement between the individual data signals 8 Bit Hub Interface Strobe Signals The hub interface strobe signals should be routed 5 mils wide with 20 mils trace spacing 5 on 20 This strobe pair should have a minimum of 20 mils spacing from any adjacent signals The maximum length for the strobe signals in normal mode is 8 inches and in enhanced mode is 14 inches Each strobe signal must be the same length and each data signal must be matched within 0 1 inch of the strobe signals 8 Bit Hub Interface HUBREF Generation Distribution HUBREF is the hub interface reference voltage Depending on the buffer mode 1 normal or enhanced buffer mode the HUBREF voltage requirement must be set appropriately for proper operation See
105. 266 MHz 300 MHz 356 MHz and 400 MHz operation The latter delivers 1 6 GB s of theoretical memory bandwidth which is twice the memory bandwidth of 100 MHz SDRAM systems Coupled with the greater bandwidth the heavily pipelined RDRAM protocol provides substantially more efficient data transfer The RDRAM memory interface can utilize more than 95 of the 1 6 GB s theoretical maximum bandwidth In addition to the RDRAM s performance features the new memory architecture provides enhanced power management capabilities The powerdown mode of operation allows Intel 820E chipset based systems to provide cost effective support of Suspend to RAM Streaming SIMD Extensions The Pentium processor provides 70 new streaming SIMD single instruction multiple data extensions The Pentium lll processor s new extensions are floating point SIMD extensions Intel MMX technology provides integer SIMD extensions The Pentium processor s new extensions complement the Intel MMX technology SIMD extensions and provide a performance boost to floating point intensive 3D applications 2 0 In combination with Direct RDRAM memory technology the AGP 2 0 interface allows graphics controllers to access main memory at over 1 GB s which is twice the AGP bandwidth of previous AGP platforms AGP 2 0 provides the infrastructure necessary for photorealistic 3D In conjunction with Direct RDRAM and the Pentium III processor s new streaming SIMD extensions
106. 4 Vppo However during 1 5 2 0 operation Vrer must be 0 5 This requires a flexible voltage divider for Various methods of accomplishing this exist such as the example in the following figure Figure 39 2 0 Vrer Generation and Distribution Design Guide Notes VrefCG 12 V R7 Note 2 12 V R7 Note 2 iko 92 R9 VDDQ 1 5 V AGP Card 300 Q 1 TYPEDET R11 VrefGC rei 200 01 500 pF R6 R5 U6 voa 1 820 T REF GMCH C10 0 1 pF R2 38 1kQ 820 L ect e 2 500 Place C10 close to 1 The resistor dividers should be placed near the GMCH The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals 2 R7 is the same resistor as R1 in the figure AGP VDDQ Generation Example Circuit 1kQ 83 3 3 V Card 300014 VDDQ 4 R11 VrefGC 200 Q 1 500 pF R6 R5 06 vona 1kQ 820 He REF GMCH MOSFET 1 C10 0 1 uF 4 31 uo um c9 Em 500 10 1 VrefCG Notes 1 The resistor dividers should be placed near the GMCH The AGPREF signal must be 5 mils wide and routed 25 mils from adjacent signals 2 R7 is the same resistor as R1 in the figure AGP VDDQ Generation Example Circuit 2 Vref gen dist The flexible divider show
107. 40 pin IDE cable The wires in the cable alternate as follows ground signal ground signal ground signal ground All ground wires are tied together on the cable and they are tied to ground on the motherboard through the ground pins in the 40 pin connector This cable conforms to the Small Form Factor Specification SFF 8049 which is obtainable from the Small Form Factor Committee To determine if the ATA 66 or ATA 100 mode can be enabled the Intel 820E chipset requires that the system software attempt to determine the type of cable used in the system If the system software detects an 80 conductor cable it may use any Ultra DMA mode up to the highest transfer mode supported by both the chipset and the IDE device If a 40 conductor cable is detected the system software must not enable modes faster than Ultra DMA Mode 2 Ultra ATA 33 Intel recommends that cable detection be performed using a combination host side device side detection mechanism Note that host side detection cannot be implemented on an NLX form factor system since this configuration does not define the interconnect pins for the PDIAG CBLID from the riser containing the ATA connectors to the motherboard These systems must rely only on the device side detection mechanism Combination Host Side Device Side Cable Detection Host side detection described in the ATA ATAPI 4 Standard Section 5 2 11 requires the use of two GPI pins one for each IDE channel The proper
108. 5 Sig amp go N59 70 ang g 5 e po DO S 1SOWOA 99A 5 E amp SOON SEDO 29929 ABSE L 2 v ZN 6 9 2 8 Ov JO OL 1JJHS 91 01 0002 02 6 5 1577 99d 2 06986 INOS 104 QvOU ALIO 0061 1534 WHOd1Vld 90d 90 v9d94J 2 LASdIHO 3028 1 1 31 1 72 c 0 00 1 92 92 eHMd eav1 42 HMd QV1 LINIH 82 ez 05 Te 2 EN 5 2 ve i ce 85 66 MOT 907 901 L0 H 90 H S0EH rOEH HNS uonoejep epis soy 104 90 HNS ON ZOEY HNIS uonoejep epis 104 M0 AAA 42 0 90 H 103130004 15104 lt 429252 221 VVV ddA 8628 07 6629 soey 10931400015 42 044 10 EQOA 01 pen eq en jou o 3 F 093011 6201 000z 02 de uS 157 06996 NOSTOA 2 ALIO 006 1 1530
109. 7 esa RN 32328 29 298 80 0838 0 x 298 80 NS m 92529 T e T e oA E 60 n era orav E 8rd orav Hav Te 798 Te 798 2 ova bd ova GE sea vray 90 va Hao va Hd o z eva eva dig 9034 end A E NEL 9 pms EEA Me 24085 ma 1 sc mL 13085 121 a a oj end Msc On Fora 1494095 Fora Puad 8692929 xz gt 5 2 5001 9 LI ey 9 ind Msz 4015 Sev 368 azeze 015 sev sea EA LA 269 ars 2 zev 269 POLL eid ind Msz aeg 1 981 36V aeg SEV Gea SEV Gea ES NEM 5 veg veg eed 0 eed 2338 5 grav zea zea grav 197 Ica 80 197 olay 9 27 Slav 62 eza 20 629 rev 2207 828 220 828 2 PE nm Zev 228 20 ee 22 Zev 228 92 928 10 92 928 M ved Szav 9 47 ved Szav 1 8204 eza 1804 3zav eza Zeav anro 2219 zav Zev zea zav Zev zea e
110. 8 2 to 10 pull up Open drain outputs from drive resistor to 3 3 V No extra series termination resistors IDERST The PCIRST signal should be buffered 132 Design Guide InteP 820 Chipset Checklist Items Recommendations Reason Effect Cable Detect Host Side Device Side Detection Connect the IDE pin PDIAG CBLID to an ICH2 GPIO pin Connect a 10 resistor to GND on the signal line Device side detection Connect a 0 04 capacitor from the IDE pin PDIAG CBLID to GND No ICH2 connection The 10 resistor to GND prevents from floating if no devices are present on either IDE interface Allows the use of 3 3 V GPIOs that are not 5 V tolerant Note ATA66 100 drives can detect cables See See Eure 27 Note Table 42 ISA Bridge Checklist The maximum trace length from the ICH2 to the ATA connector is 8 inches Design Guide Checklist Items Recommendations 2 GPO 21 ISA Connect ICH2 GPO 21 to ISA NOGO input NOGO input GPO 21 is not available on the ICH2 any other that defaults high in the system can be used GPO 21 is the only ICH2 GPO that defaults high ICH2 AD22 ISA Connect ICH2 AD22 to the ISA IDSEL input IDSEL input 133 Inte 820E Chipset 2 25 ICH2 Layout Checklist Table 43 8 Bit Hub Interface
111. 84 81688 zwi A8SE oe soon 918 99 d 68 861 48 NNOO 049 sa asn dovasn lt gt 82 876 9 V ea a 00 499 02 nXrdov cL gt 82 8692528 10128uu02 dOV m z B 7 5 5 5 ur BM MA 08956 NOSTOA 1016107 228 3v 599 ALIO 006 211 N9IS3 WHOdlVid 90d 1 uec 20 2 SHOLOSNNOO 194 3ON3H343U 3028 H 73111 zov 298 29 298 19 198 19 198 09 088 Pav 8 88 Mose 09 099 9 v e 65V 658 65V 658 00 89 858 00 89 858 18V 758 18V 758 95v 958 cav 95 958 vay 99 ssa Sav vay 99 ssa Sav v68 90 v68 557 esa 55
112. 91 Inte 820E Chipset 6 2 ICH2 Power Plane Split The following example shows the power plane splits for the ICH2 Figure 106 Example of ICH2 Power Plane Split 192 B t na gt Ks am 9 E 14 06000000 90 Fa 28 m LJ s 8 9 2 5 5 o BR wa REF Design Guide InteP 820 Chipset Thermal Design Power The thermal design power is the estimated maximum possible expected power generated in a component by a realistic application It is based on extrapolations of both hardware and software technology over the life of the product It does not represent the expected power generated by a power virus For thermal design considerations regarding the Pentium processor using the Intel PGA370 socket refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Ill Processor for the PGA370 Socket These guidelines can be downloaded from the Intel website at http developer intel com design chipsets designex 298178 htm The thermal design power numbers for the MCH and the ICH2 are listed in the following table Table 63 Intel 820E Chipset Component Thermal Design Power Thermal Design Power 133 400 MHz 6 4 Design Guide ICH2 1 5 W 15 Glue Chip 3 Intel 820E Chipset Glue Chip To reduce the component count and BOM
113. 91 01 0002 02 6 03S1A34 1577 90d 2 08996 VINHOJIIVO 108104 2 ALIO 0061 WHOdlVld 99d 90 WIG Z LASdIHO 3028 H T131NI 3 111 5 SHOLO3NNOO 194 ANA we e zi Mrz 57 ORE we e assu ng vna 92 92 9 0 vnd eng ROV 92 92 anro 9z NSHd anro 9 9 92 anro 1219 92 anro 29 89 Td3NOGS 92 4V940V m 92 lo relay lo el 3a m 92 9c 9 oav oav tav tav 9av sav sav 9av 40 sav Lev 9 878 orav sav 478 978 uvd sva orav tva tva Wado org 8835 8838 92 vlav re
114. AGP 2 0 delivers the next level of 3D graphics performance Hub Interface As the I O speed has increased the demand placed on the PCI bus by the I O bridge has become significant With the addition of AC 97 and ATA 100 coupled with the existing USB I O requirements will begin to affect PCI bus performance The Intel 820E chipset s hub interface architecture ensures that the I O subsystem both PCI and the integrated I O features IDE AC 97 USB etc will receive adequate bandwidth By placing the I O bridge on the hub interface instead of the PCI the hub architecture ensures that both the I O functions integrated into the ICH2 and the PCI peripherals will obtain the bandwidth necessary for peak performance In addition the hub interface s lower pin count allows a smaller package for the MCH and ICH2 Design Guide 1 4 6 1 4 7 1 4 8 Design Guide InteP 820E Chipset Integrated LAN Controller The ICH2 component incorporates an integrated LAN Controller Its bus master capabilities enable the component to process high level commands and perform multiple operations which lowers processor utilization by off loading communication tasks from the processor The ICH2 functions with several options of LAN connect components allowing the targeting of the desired market segment The Intel 82562EH component provides HomePNA 1 Mbit sec connection The Intel 82562ET component provides a basic Ethernet 10 100 connection The Int
115. Also Intel does not support access to the ICH2 s SMBus slave interface by the ICH2 s SMBUS host controller The following table describes the pull up requirements for different implementations of the SMBus and SMLink signals Table 20 Pull Up Requirements for SMBus and SMLink Signals SMBus SMLink Use Implementation Alert on LAN signals 4 7 pull up resistors to 3 3 Vsg are required GPIOs Pull up resistors to 3 3 and the signals must be allowed To change states on power up For example during power up the ICH2 will drive heartbeat messages until the BIOS programs these signals as GPIOs The values of the pull up resistors depend on the loading on the GPIO signal 4 7 pull up resistors to 3 3 Vsg are required Design Guide 95 Inte 820 Chipset 2 18 intel PCI The ICH2 provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2 2 The implementation is optimized for high performance data streaming when the ICH2 acts as either the target or the initiator on the PCI bus For more information on the PCI Bus interface refer to the PCI Local Bus Specification Revision 2 2 The ICH2 supports six PCI Bus masters excluding the ICH2 by providing six REQ GNT pairs In addition the ICH2 supports two PC PCI REQ GNT pairs one of which is multiplexed with a PCI Figure 58 PCI Bus Layout Example 2 19 Note 96 2 PCI bus layout
116. CG device Two modifications were made to the DRCG 1 The DRCG Mult 0 1 select table was changed to modify two of the multiplier ratios The DRCG will support 133 356 MHz using a 66 MHz DRCG input clock and 16 3 multiplier An additional 9 2 multiplier allows 133 300 MHz not supported by the Intel 820E chipset Support for the 300 MHz and 400 MHz memory bus is unchanged The following table lists the DRCG ratios 8 1 2 The Intel 820E chipset supports the following ratios and can be supported by the DRCG and DRCG or derivative devices Contact your DRCG vendor for information on DRCG DRCG and derivative products 100 MHz Host Bus 133 MHz Host Bus mm 3 The jitter timing specifications were expanded to encompass both the component specification for DRCG or derivative products and the channel specification Follow the component specification when measuring jitter at the DRCG output resistor Follow the channel jitter guidelines when measuring jitter at the or at the termination for CFM CFM on the RDRAM interface Output Frequency Component Jitter Channel Jitter MHz Specification Guidelines 175 Inte 820E Chipset intel 4 9 2 DRCG Frequency Selection Schematic The DRCG frequency can be selected using two GPIOs connected to the MULT 0 1 pins as shown in the following figure This allows selection of all frequencies support
117. CH2 hub interface to PCI bridge puts all processor boot cycles out on the PCI before sending them out on the FWH Flash BIOS interface If the 2 is set for subtractive decode these boot cycles be accepted by positive decode agent out on the PCI This enables booting from a PCI card that positively decodes these memory cycles To boot from a PCI card it is necessary to keep the ICH2 in the subtractive decode mode If a PCI boot card is inserted and the ICH2 is programmed for positive decode two devices will positively decode the same cycle In systems with a PCI to ISA bridge it also is necessary to keep the NOGO signal asserted when booting from a PCI ROM Note that it is not possible to boot from a ROM behind a PCI to ISA bridge After booting from the PCI card it is possible to program the FWH Flash BIOS in circuit and program the ICH2 CMOS 2 23 2 FWH Flash BIOS VPP Design Guidelines The VPP on the FWH Flash BIOS is used for programming the flash cells FWH Flash BIOS supports a VPP of 3 3 V or 12 V If VPP is 12 V the flash cells will program about 50 faster than at 3 3 V However the FWH Flash BIOS only supports 12 V VPP for 80 hours The 12 V VPP is useful in a programmer environment which is typically an event that occurs very infrequently much less than 80 hours The VPP pin must be tied to 3 3 V on the motherboard 124 Design Guide 2 Design Checklist InteP 820E Chipset This checklist high
118. CH2 looks for the processor to fetch the first instruction after reset If the processor does not fetch the first instruction the ICH2 will reboot the system at the safe mode frequency multiplier ECC Error Reporting After detecting an ECC error the MCH can send one of several messages to the ICH2 The MCH can instruct the ICH2 to generate either SMIZ NMI SERR or TCO interrupt 21 Inte 820E Chipset 22 intel Function Disable ICH2 provides the ability to disable the following functions AC 97 Modem AC 97 Audio IDE USB or SMBus Once disabled these functions no longer decode I O memory or PCI configuration space Also no interrupts or power management events are generated by the disabled functions Intruder Detect The ICH2 provides an input signal INTRUDER that can be attached to a switch that is activated when the system case is opened The ICH2 can be programmed to generate an SMI or TCO interrupt resulting from an active INTRUDER signal SMBus The ICH2 integrates an SMBus controller The SMBus provides an interface to manage peripherals such as serial presence detection SPD on RIMMs and thermal sensors The slave interface allows an external microcontroller to access system resources The Intel 820E chipset platform integrates several functions designed to expand the capability of interfacing several components to the system Interrupt Controller The interrupt capabilities of the Intel 820
119. CK SKS Clocking Layout Recommendations Yes No Comments 1 CLK 33 goes to ICH2 FWH FLASH BIOS and SIO Clock chip to series resistor 0 5 inch and from Series resistor to receiver 15 inches max Routed on one layer 2 PCI 33 goes to PCI device or PCI slot There are 5 clocks Clock chip to series resistor 0 5 inch and from series resistor to receiver 13 inches max Routed on one layer 3 CLK 66 goes to ICH2 and MCH Clock chip to series resistor 0 5 inch and from series resistor to receiver 14 inches max Routed on one layer 4 66 goes to connector Clock chip to series resistor 7 0 5 inch and from series resistor to receiver 11 inches max Routed on one layer Table 50 RTC Layout Recommendations Yes No Comments 1 lead length lt 0 25 inch max Minimize capacitance between Xin and Xout Put GND plane underneath crystal components Don t route switching signals under external components unless on other side of board Design Guide 137 Inte 820 Chipset This page is intentionally left blank 138 Design Guide 3 1 Design Guide InteP 820E Chipset Advanced System Bus Design Section 10 describes the recommendations for designing Intel 820E chipset based platforms This section discusses in more detail the methodology used to develop the advanced system bus guidelines These layout cons
120. CNR in a particular build It is required that the CNR 0 2 pins be set to a unique address so that the CNR EEPROM can be accessed See CNR specification Figure 55 indicates the interface for the CNR connector Refer to the appropriate section of this document for the corresponding design and layout guidelines The Platform LAN Connection PLC can either be an Intel 82562EH or Intel 82562EM component Refer to the CNR specification for additional information Figure 55 CNR Interface AC 97 Interface LAN Interface Core Logic Communication and Controller Networking Riser SMBus P up to 2 AC 97 codecs amp one PLC Device Reserved Connector 90 Design Guide intel 2 13 3 Design Guide InteP 820E Chipset AC 97 Routing To ensure the maximum performance of the codec proper component placement and routing techniques are required These techniques include properly isolating the codec associated audio circuitry analog power supplies and analog ground planes from the rest of the motherboard This includes plane splits and proper routing of signals not associated with the audio section Contact your vendor for device specific recommendations The basic recommendations are as follows Special consideration must be given for the ground return paths for the analog signals Digital signals routed in the vicinity of the analog audio signals m
121. CTM The DRCG generates one pair of differential Direct RDRAM clocks CTM from the reference clock generated by the CK 133 In addition the DRCG uses phase information provided by the to phase align the Direct RDRAM clock with the processor clocks This phase alignment information is provided to the DRCG via the SYNCLKN and PCLKM pins Figure 86 Intel 820E Chipset Platform Clock Distribution CPUCLK APIC CPUCLK APIC CPUCLK 3V66 CPU DIV2 3V66 APIC PCICLK 3V66 CK133 REF 48Hz PCICLK PCICLK PCICLK A Processor B CLK PICCLK Processor o Kj l o CLK PCI SLOTS CLK PCI SLOTS CLK PCI SLOTS CLK PCI SLOTS The free running PCI clock should be connected to the ICH uk RDRAM RDRAM RDRAM RDRAM PICCLK RCLK TCLK RCLK TCLK TCLK 4 4 L e gt e gt MCH CTM gt E er PHASEINFO PHASEINFO gt REFCLK DRCG CLK APICCLK PCICLK N CLK66 gt Flash BIOS CLK48 LPC clock dist Design Guide InteP 820 Chipset intel Table 56
122. E chipset platform expands support for up to eight PCI interrupt pins and PCI 2 2 message based interrupts In addition the ICH2 supports system bus interrupt delivery FWH Flash BIOS The Intel 820E chipset based system platform supports firmware hub BIOS memory sizes up to 8 MB for increased system flexibility Alert on LAN The ICH2 supports Alert on LAN In response to a TCO event intruder detect thermal event processor not booting the ICH2 sends a message over ALERTCLK and ALERTDATA to alert the network manager Design Guide intel 1 4 9 Design Guide InteP 820E Chipset AC 97 The Audio Codec 97 AC 97 specification defines a digital interface that can be used to attach an audio codec AC a modem codec MC an audio modem codec AMC or both an AC and an MC The AC 97 specification defines the interface between the system logic and the audio modem codec known as the AC 97 Digital Link The Intel 820E chipset platform s 97 with the appropriate codecs not only replaces ISA audio modem functionality but also improves overall platform integration by incorporating the 97 digital link The use of the ICH2 integrated 97 digital link reduces cost and eases migration from ISA By using an audio codec the AC 97 digital link allows for cost effective high quality integrated audio on an Intel 820E chipset based platform In addition an 97 soft modem can be implemented with the use
123. IC INTIN PIN 20 PIRQE Internal LAN device 6 IOAPIC INTIN PIN 21 PIRQF 7 IOAPIC INTIN PIN 22 PIRQG 8 IOAPIC INTIN PIN 23 USB controller 2 101 Inte 820E Chipset intel Interrupts B D E and H service devices internal to the ICH2 Interrupts A C F and G are unused and can be used by PCI slots The following figure shows an example of IRQ line routing to the PCI slots Figure 63 Example PCI IRQ Routing 2 22 102 INTA PIRQA PIRQB PIRQC PIRQD ICH2 PIRQE PIRQF PIRQG Slot 1 Slot 2 Slot 3 Slot 4 PCI Device 0 PCI Device 5 PCI Device 6 PCI Device C AD16 to IDSEL AD21 to IDSEL AD22 to IDSEL AD28 to IDSEL PCI IRQ routing ex The PCI IRQ routing in the previous figure allows the ICH2 s internal functions to have a dedicated IRQ assuming add in cards are single function devices and use INTA If a P2P bridge card or a multifunction device uses more than INTn pin on the ICH2 PCI bus the ICH2 s internal functions will start sharing IRQs Figure 63 is one example It is up to board designers to route these signals most efficiently for their particular systems A PCI slot can be routed to share interrupts with any of the ICH2 s internal device functions LAN Layout Guidelines The ICH2 provides several options for integrated LAN capability The platform supports several components depending on the t
124. Id 2 968 1968 81 lt 2 9 ZX 0 128 Zisal 1531 85 lt gt 8h SNId 1061 026181 03144348 NVT TT 0031 ai 026181 Gai NYT FO oan 3191081 1631 xu XH 5 Ree Na XL rax ld c oum QJ N XIXH iz avilo 4 OQXL NYT lt 9 d XL XH c axu axu NTMOTXL NYT eroj XL X10 NYI 8 91 2 axy d MOT XL dux ONAS1SH 13S3H NYI gt 8191 39Vd SIHL SLNANOdWOD TY 33715 NOILVYNDISNOO NY 13INOH HOH 3LON e 28 25 0 9 enba I SNWN eoueisiseg A8SE 329628 0730 81 62 01 0002 02 6 2 3v 55d 0061 1534 99d 90 1329528 Nv1 WINIG Z L3SdIHO 3028 131 311LL 8 86 0 SS 5 9 2 55 5 87 3187 85 95555 vc 55 6 55 1 02 455 5 ec 1001 Losi 619 81 31 31 SNId TOSI 4 001584 gt 2
125. Intel 820E Chipset Clock Routing Guidelines Y CPUCLK to SC242 Y lt 5 3 CPUCLK to MCH 9 0 Note Tie CPUCLK for the MCH to CPUCLK to the SC242 to eliminate pin to pin skew 3V66 clock for 2 gt slot l PCI clock for 2 pem gt TBD PCI slots 66 clock for 2 sd 0 and ICH 2 4 PCI clock for ICH J9 0 5 PCI clock for on board 2 TBD devices excluding ICH Note 1 Tie 3V66 clock for MCH to 3V66 clock for AGP connector to eliminate pin to pin skew 2 These calculations are based on 150 ps in trace velocity 3 TBD value derived from PCI Revision 2 2 Specification which allows for max 2 ns clock skew 820 clk route Design Guide InteP 820 Chipset intel Table 57 Intel 820E Chipset Platform System Clock Cross Reference www mme NOTES 1 Differential clocking pair 2 driven by Design Guide 167 Inte 820E Chipset intel 4 2 Component Placement and Interconnection Layout Requirements The layout requirements for each interconnection are explained in detail in the following sections Crystal to CK133 e CK133 to DRCG MCH to DRCG DRCG to RDRAM channel 4 2 1 14 318 MHz Crystal to CK133 The distance between the crystal and the CK133
126. K M sio go Laxd Nv1 SOT Nv1 569 22 oaxd NYT AAA OXY NYT NYT AA ZHON NYT LAXI NYI A NYT 2 0 Nv1 MIO NYI 10 3115 Joy uondo Buyynis 410 NYI 158 NV1 YNO es UNO OGXE NVT 84 NVI SL n HNO AXL YND UNO 40 115 20 3115 969 M0 Raw 14 1 05 ov 2 LNOVLVGS ONAS OV ONAS OV 0 1 06 OV HNO 10 uodo 81 Sk lt SL gt HNO LNOVLVGS OV ONAS OV ANIT 2607 NO 58715 ONIVLVGS J OL SWHO 22 UNO 10 311 SNOILdO ONISSNLS ANY Z69V 3 F 094011 6201 0002 02 157 06996 NOSTOA 2 ALIO 006 1 1530 99d 9 T 50 329528 Nv1 WIG Z 13SdIHO 3028 H 131NI JILL 109 8 ra xd 1931 0 84 xu 0 1631 v 7 1N
127. NO SDATA IN1 To AC 97 Digital Controller Ne CNR Connector As shown in Figure 51 when a single codec is located on the motherboard the resistor RA and the circuitry AND and NOT gates shown inside the dashed box must be implemented on the motherboard This circuitry is required in order to disable the motherboard codec when a CNR is installed which contains two AC 97 codecs or a single AC 97 codec which must be the primary codec on the AC Link By installing resistor 1 on the the codec on the motherboard becomes disabled held in reset and the codec s on the CNR take control of the AC Link One possible example of using this architecture is a system integrator installing an audio plus modem CNR in a system already containing an audio codec on the motherboard The audio codec on the motherboard would then be disabled allowing all of the codecs on the CNR to be used The architecture shown in Figure 52 has some unique features These include the possibility of the being used as an upgrade to the existing audio features of the motherboard by simply changing the value of resistor Rg on the CNR to 100 An example of one such upgrade is increasing from two channel to four or six channel audio Both Figure 52 and Figure 53 show a switch on the CNR board This is necessary to connect the CNR board codec to the proper SDATA INn line as to not conflict with the motherboard codec s Design G
128. Rs VERY short Rp 51 Keep from to Rp short Decoupling Cap 0 1uF Place VERY Near DRCG 3 3V Pin Decoupling Cap 0 1uF Place VERY Near DRCG 3 3V Pin 3 3V DRCG Flood Flood 3 3V DRCG on the top layer around DRCG Flood MUST include 4 DRCG Power Pins 4 0 1uF Capacitors 1 10uF Bulk Capacitor 1 Isolation Ferrite Bead Decoupling Cap 0 1uF Decoupling Cap Place VERY Near DRCG 3 3V Pin Place VERY Near DRCG 3 3V Pin Bulk Decoupling Cap 10uF Place Near DRCG Ferrite Bead L22 in Reference Schematics AGP Clock Routing Guidelines The AGP clock must be routed with 20 mil spacing to all other signals and it must meet the length guidelines in Clock Routing Guidelines for Intel PGA370 Designs For the Intel 820E chipset FC PGA clock routing guidelines refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Processor for the PGA370 Socket These guidelines can be downloaded from the Intel website at fhttp developer intel com design chipsets desig Series Termination Resistors for CK133 Clock Outputs used outputs require series termination resistors The recommended resistor values are defined by simulations The stub length to the CK 133 of these resistors be compromised to make room for decoupling caps As rule keep all resistor stubs within 250 mils of the CK 133 If routing rules allow Rpacks can be used if
129. ST Circuit The 2 RTC requires additional external circuitry The RTCRST signal is used to reset the RTC well The external capacitor and the external resistor between RTCRST and the RTC battery were selected to create an RC time delay such that RTCRST will go high some time after the battery voltage becomes valid The RC time delay should be within the range 10 ms 20 ms When RTCRST is asserted bit 2 PWR 575 in the GEN PMCON 3 General PM Configuration 3 register is set to 1 and remains set until cleared by software As a result when the system boots the BIOS knows that the RTC battery has been removed Figure 61 RTCRST External Circuit for ICH2 RTC VCC3 3SBY Diode Battery Circuit ircui ika VccRTC 1 RTCRST 2 2 uF RTCRST Circuit rtc rtcrst ich This RTCRST circuit is combined with the diode circuit Figure 60 Diode Circuit Connecting RTC External Battery which allows the RTC well to be powered by the battery when system power is unavailable Figure 59 jis an example of the circuit used in conjunction with the external diode circuit Design Guide 99 Inte 820E Chipset 2 19 6 2 19 7 2 19 8 2 20 100 intel RTC Routing Guidelines All RTC OSC signals RTCX1 RTCX2 VBIAS should be routed with trace lengths of less than 1 inch The shorter the better e Minimize the capacitance
130. STB and SB STB When the term data is used it refers to one of the three sets of data signals When the term strobe is used it refers to one of the strobes as it relates to the data in its associated group The routing guidelines for each group of signals 1x timing domain signals 2x 4x timing domain signals and miscellaneous signals will be discussed separately 1x Timing Domain Routing Guidelines The AGP Ix timing domain signals have a maximum trace length of 7 5 inches Refer to signal groups listed previously This maximum applies to all signals listed as 1x timing domain signals in the Signal Groups section AGP 1x timing domain signals can be routed with 5 mil minimum trace separation There are no trace length matching requirements for 1x timing domain signals 2x 4x Timing Domain Routing Guidelines These trace length guidelines apply to all signals listed as 2x 4x timing domain signals These signals should be routed using 5 mil 60 2 traces The maximum line length and length mismatch requirements depend on the routing rules used on the motherboard These routing rules were created to allow design freedom by making tradeoffs between signal coupling trace spacing and line lengths The maximum length of the AGP interface defines which set of routing guidelines must be used Guidelines for short AGP interfaces e g 6 inches and long interfaces e g gt 6 inches and 7 25 inches are documented
131. TCLK and is derived from a 24 576 MHz crystal or oscillator Refer to the primary codec vendor for the crystal or oscillator requirements BITCLK 15 a 12 288 MHz clock driven by the primary codec to the digital controller ICH2 and any other codec present This clock is used as the time base for latching and driving data The ICH2 supports Wake on Ring from 51 55 via the AC 97 link The codec asserts SDATAIN to wake the system To provide wake capability and or caller ID standby power must be provided to the modem codec The ICH2 has weak pull downs pull ups that are enabled only when the AC Link Shut Off bit in the ICH2 is set This keeps the link from floating when the AC link is off or when no codec is present If the shut off bit is not set it implies that there is a codec on the link Therefore BITCLK and AC SDOUT will be driven by the codec and ICH2 respectively However SDINO and SDINI may not be driven If the link 15 enabled it can be assumed that there is at least one codec If there is one or no codec on board then the unused AC SDINx pin s should have a weak 10 pull down to keep it from floating AC 97 Audio Codec Detect Circuit and Configuration Options The following provides general circuits to implement a number of different codec configurations Please refer to Intel s White Paper Recommendations for ICHx AC 97 Audio Motherboard and Communication and Network Riser for Intel s recommended codec configur
132. TT on processor Intel PGA370 socket 1 Termination resistance RTT on processor Intel PGA370 socket 2 e 70 of traces on processor Intel PGA370 socket 1 e ZO of traces on processor Intel PGA370 socket 2 50 of traces on processor Intel PGA370 socket 1 50 of traces on processor Intel PGA370 socket 2 Z0 of traces on baseboard 50 of traces on baseboard Fast and slow corner processor I O buffer models for Intel PGA370 socket 1 Fast and slow corner processor I O buffer models for Intel PGA370 socket 2 Fast and slow package models for processor Intel PGA370 socket 1 e Fast and slow package models for processor Intel PGA370 socket 2 Fast and slow corner Intel 82820 I O buffer models e Fast and slow Intel 82820 package models Simulation Criteria Accurate simulation requires that the actual range of parameters be used in the simulation Intel has consistently measured the cross sectional resistivity of PCB copper to be approximately 1 Q mil inch not the 0 662 Q mil inch value for annealed copper that is published in reference material Using the 1 Q mil inch value may increase the accuracy of lossy simulations Positioning drivers with faster edges closer to the middle of the network typically results in more noise than positioning them towards the ends However Intel has shown that drivers located in all positions given appropriate variations in the other network parameters can generate the wo
133. Table 37 RTC Checklist Items Recommendations Reason Effect and use 12 pF decoupling caps at each signal RTCX1 may optionally be driven by external oscillator instead of a crystal These signals are 1 8 V only and must not be driven by a 3 3 V source VBIAS The VBIAS pin of the ICH2 is connected For noise immunity on VBIAS signal to a 0 047 cap See RTCX1 Connect a 32 768 kHz crystal oscillator The ICH2 implements new internal oscillator RTCX2 across these pins with a 10 MO resistor circuit as compared with the to reduce the power consumption The external circuitry shown in Figure 59 required to maintain RTC accuracy The circuitry is required because the new RTC oscillator is sensitive to step voltage changes in VCCRTC and VBIAS A negative step voltage change of more than 100 mV will temporarily shut off the oscillator for hundreds of milliseconds Table 38 AC 97 Checklist Items Recommendations Reason Effect AC_SDOUT Requires a jumper to 8 2 kQ pull up This pin has a weak internal pull down To resistor Should not be stuffed for default properly detect a safe_mode condition a operation strong pull up is required to override this internal pull down AC SDIN 1 Requires pads for weak 10 pull AC SDIN 1 0 are inputs to an internal OR SDIN O downs Stuff resistor for unused gate If a pin is left floating the output of the AC SDIN
134. V 3 3V Power Sequencing Circuit 3 3V e e 220 Q2 4 mo NPN 470 When analyzing systems that may be marginally compliant with the 2 V Rule pay close attention to the behavior of the ICH2 s RSMRST PWROK also LAN PWROK in ICH2 m signals since these signals control the internal isolation logic between the various power planes as follows RSMRST controls the isolation between the RTC well and the resume wells PWROK controls the isolation between the resume wells and main wells LAN PWROK controls the isolation between the LAN wells and the resume wells applies only to ICH2 m If one of these signals goes high while one of its associated power planes is active and the other is not a leakage path will exist between the active and inactive power wells This could result in high possibly damaging internal currents 6 1 4 3 3V V5REF Sequencing Design Guide VSREF is the reference voltage for 5 V tolerance on inputs to the ICH2 VSREF must be powered up before or simultaneously to Vcc3 3 It must also power down after or simultaneous to Vcc3 3 The rule must be followed in order to ensure the safety of the ICH2 If the rule is violated internal diodes will attempt to draw power sufficient to damage the diodes from the Vcc3 3 rail Figure 104 bhows a sample implementation of how to satisfy the VSREF 3 3V sequencing rule This rule also applies to the stand by
135. a ground layer as the single reference plane Figure 79 One Signal Layer and One Reference Plane Signal Layer A S Ground Plane 1lay_1ref plane When it is not possible to route the entire AGTL signal on a single Vss referenced layer there are methods of reducing the effects of layer switches The best alternative is to allow the signals to change layers while staying referenced to the same plane see Figure 80 Figures 81 through 83 show other methods of minimizing layer switch discontinuities but they may be less effective than the following figure In this case the signal still references the same type of reference plane 1 ground In such a case it is important to stitch 1 connect the two ground planes together with vias in the vicinity of the signal transition via Figure 80 Layer Switch with One Reference Plane Design Guide Signal Layer A _____ Signal Layer B lay_sw_1refplane 157 Inte 820E Chipset Figure 81 Layer Switch with Multiple Reference Planes Same Type Signal Layer A Ground Plane n 50 Pp Ground Plane Signal Layer B lay sw mult refplane When routing and stack up constraints require that an AGTL signal reference or multiple planes special care must be taken to minimize the SSO effect on timing and noise margin The best method of reducing adverse effects is to add high frequency decoupling w
136. ace length and trace spacing requirements must not be violated by any signal Trace length mismatch for all signals within a signal group should be as close to zero as possible to provide timing margin 2 8 4 AGP 2 0 Routing Summary Table 11 AGP 2 0 Routing Summary Maximum Trace Spacing Length Relative To Length 5 mil Traces Mismatch inches inches 5 mils No N A None requirement 20 mils 0 125 AD 5 0 and AD 5 0 and AD STBOZ AD STBO Z must be the same length 20 mils 0 125 5 1 AD 5 1 and AD 5 1 AD STB1 2 must be the same length 1x Timing Domain 2 4 Timing Domain Set 1 2 4 Timing Domain Set 2 2 4 Timing Domain Set 1 15 mils 0 5 AD_STBO and AD_STBO and AD_STBO AD_STBO must be the same length 15 0 5 AD_STB1 and AD_STB1 and AD_STB1 AD_STB1 must be the same length 15 mils 0 5 SB STBand SB_STB SB_STB must Domain Set 3 SB_STB be the same length NOTES 1 Each strobe pair must be separated from other signals by at least 20 mils 2 These guidelines apply to board stack ups with 10 impedance tolerance 2x 4x Timing Domain Set 2 2x 4x Timing 3 Domain Set 3 SB 5 be the same length 55 p 64 Design Guide 2 8 6 2 8 6 1 Note Design Guide InteP 820E Chipset AGP Clock Routing The maximum total AGP clock skew between the MCH and the graphics component is 1 ns for all data transfer modes
137. ained in the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Processor for the PGA370 Socket Regarding special case AGTL signals for simulation there are six AGTL signals that can be driven simultaneously by more than one agent These signals may require extra attention during the layout and validation portions of the design When a signal 1s asserted driven low by two agents on the same clock edge the two falling wavefronts will meet at some point on the bus This can create a large undershoot followed by ringback which may violate the ringback specifications This wired OR situation should be simulated for the following signals AERR BERR BINIT BNR HIT and IDE Interface This section contains guidelines for connecting and routing the ICH2 IDE interface The ICH2 has two independent IDE channels This section provides guidelines for IDE connector cabling and motherboard design including component and resistor placement and signal termination for both IDE channels The 2 has integrated the series resistors typically required on the IDE data signals PDD 15 0 and SDD 15 0 running to the two ATA connectors Intel does not anticipate requiring additional series termination but OEMs should verify motherboard signal integrity through simulation Additional external 0 Q resistors be incorporated into the design to address possible noise issues on the motherboard The additional resisto
138. air For the 8 bit hub interface HL 7 0 are associated with STB and 5 No pull ups or pull downs are required on the hub interface Each signal must be routed so as to meet the guidelines documented for the signal group to which it belongs Figure 42 Hub Interface Signal Routing Example HL STB HL 10 0 74 CLK synthesizer hub sig route Design Guide intel 2 9 1 InteP 820E Chipset 8 Bit Hub Interface Routing Guidelines This section documents the routing guidelines for the 8 bit hub interface This hub interface connects the ICH2 to the This interface supports two buffer modes normal and enhanced The ICH2 uses its HLCOMP pin to set the buffer mode and the MCH uses its HLA_ENH pin to configure its 8 bit hub interface buffers Both devices must be configured for the same buffer mode When the buffers are configured for normal mode the trace impedance must equal 60 10 In the enhanced buffer mode the trace impedance can be 50 10 or 60 15 Table 15 8 Bit Hub Interface Buffer Configuration Setting Component Hub Interface Buffer Mode Trace Impedance Strap ICH2 Normal Single 600 HLCOMP pulled to Vcc 1 8 see Note Normal Local 50 or 60 Q HLCOMP pulled to GND see Note MCH Normal Single 60 Q Default Normal Local 50 or 60 Q HLA_ENH pulled to GND via a 100 resistor Note 2 9 1 1 2 9 1 2
139. al four layer PCB design the signals transition from one side of the board to the other One extra 0 01 UF capacitor is required per 10 vias The capacitor should be placed as close as possible to the center of the via field Ensure that the AGP connector is well decoupled as described in the AGP Design Guide Revision 1 0 Section 1 5 3 3 To add the decoupling capacitors as close as possible to the MCH and or close to the vias the trace spacing may be reduced as the traces go around each capacitor The narrowing of the space between traces should be minimal and for as short a distance as possible 1 inch max 65 Inte 820E Chipset Figure 37 Top Signal Layer sae n 4 lat e Wo OW y sels 14 m aen od 2 a ALES al S Ground Reference It is strongly recommended that at a minimum the following critical signals be referenced to ground from the to AGP connector or to an AGP video controller if implemented as a down solution utilizing minimum number of vias on each net AD 5 AD STBOZ AD STBI AD STBI Z SB STB SB STBZ GTRY IRDYZ GNT and ST 2 0 In addition to the minimum signal set listed previously it is strongly recommended that half of all AGP signals be referenced to ground depending on
140. al power rail Figure 101 Intel 820E Chipset Power Delivery Example 5VSB 5 3 3V 12V 5V Dual Regulator ATX PIS with 5 gt Switch 2 5VSBY Regulator CK133 2 5 2 5V gt CK133 3 3 3 3V 1 8V Regulator Y PGA370 Core VID 22A 50 51 70 VTT 1 5V 2 7A 50 51 MBR 2 0 82562EH 12V 3 8 82562ET PHY 3 3VSB 5V gt Modem Codec 50 51 5VDUAL iodem Codec 53 55 CPU CMOS P Us 1 5V MCH Core 1 8V Hub I F 1 0 1 8V 950mA SO S1 VDDQ 1 5V 3 3V 2A 50 S1 EN ICH2 VccCPU VRM 10 50 51 Vcc1 8 Hub I F I O 1 8V 300mA SO 1 V5Ref 5V lt 10uA 50 51 USB Cable Power 5V AC 97 Audio Codec 5V Vcc3 3 3 3V lt 300 SO S1 20 50 51 300uA 53 55 VccSus3 3 ICH Resume VCC2_5 Voltage Y Regulator 2 5V 3 3V VccSus1 8 ICH Resume 1 8V 210mA 50 S120mA 53 55 saec PCI 3 3Vaux 3 3V 1 5A 50 51 435ma 53 S5 LPC Super 3 3V VccRTC ICH RTC Vbat lt 50 51 S3 55 FWH Flash BIOS V5RefSus 5VSB lt 10uA 50 51 53 55 gt Core 3 3V 67 50 S1 LEGEND Dod ATX Powe
141. allation The AGP interconnect design requires that the AGP card be retained so as to limit card back out within the AGP connector to 0 99 mm 0 039 in max For this reason new cards should have an additional mechanical keying tab notch which provides an anchor point on the card for interfacing with the AGP RM The RM s round peg engages with the or AIMM card s retention tab thereby preventing the card from disengaging during dynamic loading The additional notch in the mechanical keying tab is required for 1 5 V AGP cards and is recommended for the new 3 3 V cards Figure 40 AGP Left Handed Retention Mechanism Design Guide intel Figure 41 Design Guide InteP 820E Chipset AGP Left Handed RM Keep Out Information 46791 KESA ese 1181 DD Meo bis NK Lees uM mn Ri F nmn MR EUN EJAM 11580 Tik adt Pisa aed i TOLERANCES 127 0051 FREE 3 COMPONENT OF 178 Lorn a rex COMPONENT HEIGHT OF uen COMPONENT HIGHT DE Sig 12001 c Rp ne HEIDHT OF 508 STAYDUT OPTIONAL Recommended for all AGP cards the AGP RM is detailed in Engineering Change Request No 48 48 which details approved changes to
142. ance 2 5 0 4 mil e tolerance 5 0 2 e Stack up requirement 28 Q 10 Figure 97 28 Q Trace Geometry Design Guide 28 trace geo 177 Inte 820E Chipset 5 1 2 Design Process To meet the tight tolerances required a good design process is as follows Specify the material to be used Calculate the board geometries for the desired impedance or use the example stack up provided Build test boards and coupons Measure the board impedance using TDR and follow Intel s Impedance Test Methodology Document located on the site Measure geometries with cross section Adjust design parameters and or material as required Build a new board and remeasure the key parameters Be prepared to generate one or two board iterations This process will require iteration as follows design build test modify build test 5 1 3 Test Coupon Design Guidelines To deliver reliable systems at increased bus frequencies it is critical to characterize and understand the trace impedance Incorporating a test coupon design into the motherboard makes testing simpler and more accurate The test coupon pattern must match the probe type being used The test coupon location is listed in order of preference as follows Ist choice ideal location Memory section of the motherboard 2nd choice Any section of the motherboard 3rd choice Separate location in the panel The Intel Printed
143. ane is not 5 V The resistive drop through the 5 V dual switch must be considered Therefore no components should be connected directly to the 5 V dual plane On the ICH2 reference board only the voltage regulators for lower voltage regulation are connected to the 5 V dual plane This switch is not required in an Intel 820E chipset based system that does not support Suspend to RAM STR VCCVID This power plane is used to power the Intel PGA370 socket processor Refer to the latest revisions of the following documents e VRM 8 4 DC DC Converter Design Guidelines For the Intel 820E chipset FC PGA Vcc vid requirements refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium IIl Processor for the PGA370 Socket These guidelines can be from the Intel website at This regulator is required in all designs VTT This power plane is used to power the AGTL dual ended termination and the 1 5 V power delivery to the Intel PGA370 socket processor Refer to the latest revision of the following document For the Intel 820E chipset FC PGA VTT requirements refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Processor for the PGA370 Socket These guidelines can be downloaded from the Intel website at This regulator is required in all designs VCC 2 5 The Pentium III processor for the Intel PGA370 socket does not use this signal 185 Inte 820E Chipset
144. ant of prepreg material Thickness of prepreg stack up dependent Length Width Dimensions in mils of copper plate to be added Factor of 1 1 accounts for fringe capacitance Based on the stack up requirement in Section 5 copper tab area should be 2800 to 3600 square mils Different stack ups require different copper tab areas The following table lists example copper tab areas 41 Inte 820E Chipset 42 Table 4 Copper Tab Area Calculation Signal Trace and i i C TAB Area Copper Tab A sq mils 140 L x 20 W 70Lx40W Based on Equation 1 the tab area 1s 2800 sq mils where amp 1s 4 2 and D is 4 5 These values are based on 2116 prepreg material Note that more than one copper tab shape may be used The tab dimensions are based on the copper area over the ground plane The actual length and width of the tabs may differ as a result of routing constraints e g if the tab must extend to center of hole or antipad However each copper tab should have the equivalent area For example the copper tabs in Top the following dimensions when measured tangentially to the antipad Inner C TAB 140 length x 20 width Outer C TAB 70 length x 40 width Figures 21 through 25 show a routing example of tab compensation capacitors Note that ground floods around the RIMM pins must not be interrupted by the capacitor tabs and they must be connected to avoid discontinuity in the ground plane as show
145. arget market These guidelines use the Intel 82562ET to refer to both the Intel 82562ET and the Intel 82562EM Intel 82562EM is specified in those cases where there 1 a difference LAN Connect Component Connection Features Intel 82562 Advanced 10 100 Ethernet AOL amp Ethernet 10 100 connection Intel 82562 10 100 Ethernet Ethernet 10 100 connection Intel 82562 1 Mbit HomePNA LAN 1 Mbit HomePNA connection Intel developed a dual footprint for the Intel 82562 and Intel 82562EH components to minimize the required number of board builds A single layout with the specified dual footprint allows the OEM to install the LAN connect component appropriate for the market need Design guidelines are provided for each required interface and connection Refer to Figure 64 and Table 22 for the corresponding section of the design guide Design Guide intel InteP 820E Chipset Figure 64 ICH2 LAN Connect Section Table 22 2 22 1 Design Guide ICH2 Intel 2 82562 82562 2 module Dual footprint Refer to Intel 82562 82562 section ICH2 LAN connect LAN Design Guide Section Reference Layout Section Previous Design Guide Section Figure Reference ICH2 LAN interconnect A CH2 LAN Interconnect Guidelines General routing guidelines B C D 2 22 2 LAN Routing Guidelines and C
146. artbeat and event messages as well as to access the ICH2 SMBus slave interface The slave interface function allows an external microcontroller to perform various functions For example the slave write interface can reset or wake a system generate SMI or interrupts and send a message The slave read interface can read the system power state read the watchdog timer status and read system status bits Both the SMBus host controller and the SMBus slave interface obey the SMBus protocol so the two interfaces can be externally wire OR d together to allow an external management ASIC e g Intel 82550 to access targets on the SMBus as well as the ICH2 slave interface This is done by connecting SMLink 0 to SMBCLK and SMLink 1 to SMBDATA See Since SMBus and SMLINK are pulled up to VCCSUS3 3 system designers must be sure to properly isolate any device that may be powered down while VCCSUS3 3 is still active e g thermal sensors Design Guide InteP 820E Chipset intel Figure 57 SMBUS SMLink Interface Host controller SPD data slave interface Network 0000 0000 Temperature interface thermal sensor card on PCI SMBCLK 23 7 Microcontroller 82801BA SMBDATA ICH2 Pod i SMLink SMLinkO SMLink1 Wire OR Intel optional 8255 Motherboard LAN controller smbus smlink Note Intel does not support external access to the ICH2 s integrated LAN controller via the SMLink interface
147. ations To support more than two channels of audio output the ICH2 allows for a configuration where two audio codecs work concurrently to provide surround capabilities To maintain data on demand capabilities the ICH2 97 controller when configured for 4 or 6 channels will wait for all the appropriate slot request bits to be set before sending data in the SDATA OUT slots This allows for simple FIFO synchronization of the attached codecs It is assumed that both codecs will be programmed to the same sample rate and that the codecs have identical or at least compatible FIFO depth requirements It is recommended that the codecs be provided by the same vendor upon the certification of their interoperability in an audio channel configuration The following circuits shown in Figure 51 through Figure 54 show the adaptability of a system with the modification of RA and Rg combined with some basic glue logic to support multiple codec configurations This also provides a mechanism to make sure that only two codecs are enabled in a given configuration and allows the configuration of the link to be determined by the BIOS so that the correct PnP IDs can be loaded Design Guide InteP 820E Chipset intel Figure 51 CDC DN ENAB Support Circuitry for a Single Codec on Motherboard Motherboard CNR Board rd From AC 97 Controller AC97_RESET To General Purpose Input DN SDATA I
148. ations and before placing your product order is a two wire communications bus protocol developed by Philips SMBus is a subset of the bus protocol and was developed by Intel Implementations of the PC bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Alert on LAN is a result of the Intel IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents that have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation www intel com or call 1 800 548 4725 Intel Pentium Pentium Il PentiumPro Celeron and MMX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others 2 Design Guide InteP 820 Chipset intel Contents Design Guide 3 Inte 820E Chipset 4 Design Guide InteP 820 Chipset Design Guide 5 Inte 820E Chipset 6 Design Guide InteP 820 Chipset Stack Up Requir Design Guide 7 Inte 820E Chipset Figures 8 Design Guide Design Guide InteP 820E Chipset Inte 820E Chipset 4 5 mil Stack Up Tables 10 Design Guide Design Guide InteP 820E Chipset 11 Inte 820E Chipset Revision History e o9 01009 Initial Release June 2000
149. be 97 2 1 compliant Please contact your codec IHV for information on 2 1 compliant products 97 2 1 specification 1s on the following Intel web page The AC link is a bi directional serial PCM digital stream It handles multiple input and output data streams as well as control register accesses employing a time division multiplexed TDM scheme The AC link architecture provides for data transfer through individual frames transmitted serially Each frame is divided into 12 outgoing and 12 incoming data streams or slots The architecture of the ICH2 AC link allows a maximum of two codecs to be connected The following figure shows a two codec topology of the AC link for the ICH2 Figure 50 ICH2 AC 97 Codec Connection Design Guide Digital AC 97 2 1 controller AC MC AMC RESET SDOUT SYNC BIT_CLK 101 AC 97 2 1 controller section of ICH2 Primary codec Secondary codec ICH2 AC97 codec conn The AC 97 interface can be routed using 5 mil traces with 5 mil space between traces The maximum length from ICH2 to CODEC CNR is 14 inches in a tee topology This assumes that a CNR riser card implements its audio solution with a maximum trace length of 4 inches for the AC link The trace impedance should be as follows Zo 60 Q 15 85 Inte 820E Chipset 2 13 1 86 intel Clocking is provided from the primary codec on the link via BI
150. between and RTCX2 in the routing Optimally there would be a ground line between them e Puta ground plane under all external RTC circuitry Do not route any switching signals under the external components unless on the other side of the ground plane VBIAS DC Voltage and Noise Measurements The steady state VBIAS is a DC voltage of approximately 0 38 V 0 06 V When the battery is inserted the VBIAS is kicked to approximately 0 7 V 1 0 V but it will return to its DC value within a few ms Noise on VBIAS must be minimized at lt 200 mV e VBIAS is very sensitive and cannot be probed directly It can be probed through a 0 01 capacitor Excess noise on VBIAS can cause the ICH2 internal oscillator to misbehave or even stop completely To minimize VBIAS noise it is necessary to implement the routing guidelines described previously and the required external RTC circuitry RTC Well Input Strap Requirements All RTC well inputs RSMRST RTCRST INTRUDER must be either pulled up to VCCRTC or pulled down to ground while in G3 state RTCRST when configured as shown in ligure 6 nets this requirement RSMRST should have a weak external pull down to ground and INTRUDER should have a weak external pull up to VCCRTC This will prevent these nodes from floating in G3 and correspondingly will prevent ICCRTC leakage that can cause excessive coin cell drain The PWROK input signal should also be
151. board Trace Motherboard Trace Recommended MCH Dimension Length When Length When Routing mils Routed on Bottom Routed on Top i e Real i e Min Min Bu rw mils FomuaB Rao ar 2000 17949 181051 183051 183551 185551 Top Bo 2000 7170 19 830 193830 194930 1963 30 Top Rae mo 2000 12220 186781 188781 189281 1972 81 Top cio 2000 000 1996 00 2010 00 2015 00 203500 Botom Sorc FoRMULAD NOTES 1 Signals connecting to side A of the RIMM connector i e A1 A2 A3 etc should be routed on the top primary side of the motherboard Signals connecting to side B of the RIMM connector should be routed on the bottom solder side Clock trace lengths include the 1 021 trace velocity factor Formula A min Motherboard trace Nominal RSL length package dimension 10 mils Formula A max Motherboard trace Nominal RSL length package dimension 10 mils Formula B min Motherboard trace Nominal RSL length package dimension 10 mils 25 mil Formula B max Motherboard trace Nominal RSL length package dimension 10 mils 25 mils Formula C Motherboard trace Nominal RSL length package dimension x 1 021 0 Formula D Motherboard trace Nominal RSL length package dimension 25 mils x 1 021 These trace lengths apply only f
152. conduct routing analysis These quadrant layouts are designed for use during component placement 27 Inte 820E Chipset Figure 5 324 Ball CSP Quadrant Layout Top View Pin 1 N System bus O0000000000000 OOO000000000000 N 5 206609 2 00000 00000 o 324 Ball 5 5 5 9 UBGA CSP 66000 00000 t 5 I Direct RDRAM mch quad Figure 6 ICH2 360 Ball EBGA Quadrant Layout Top View Hub interface ce mimm ERIS O00016 eic o 000010000 0 dio 0000000 000 00 010 i 94 gt OI serrate alll r i SM bus AC 97 O O OIO O O10 O OIO LPC 0000000060 quad 28 Design Guide intel InteP 820E Chipset 2 3 Intel 820E Chipset Component Placement Notes 1 ATX and NLX placements and layouts shown in the following figure are recommended for sing
153. d AARON N External Capacitors To maintain RTC accuracy the external capacitor C1 must have a capacitance of 0 047 uF and the external capacitor values C2 and C3 should be chosen to provide the manufacturer s specified load capacitance Croan for the crystal when combined with the parasitic capacitance of the trace socket if used and package When the external capacitor values are combined with the capacitance of the trace socket and package the closer the capacitor value can be matched to the actual load capacitance of the crystal used the more accurate the RTC will be The following equation can be used to choose the external capacitance values C2 and C3 Croan C2 x C3 C2 C3 can be chosen such that C3 gt C2 Then C2 can be trimmed to obtain the 32 768 kHz 97 Inte 820E Chipset 2 19 3 Layout Considerations Minimize the RTC lead lengths Approximately 0 25 inch is sufficient Minimize the capacitance between Xin and Xout in the routing Puta ground plane under the XTAL components Do not route switching signals under the external components unless on the other side of the board The oscillator Vcc should be clean Use a filter e g an RC low pass or a ferrite inductor 2 19 4 RTC External Battery Connection The RTC requires an external battery connection to maintain its functionality and its RAM while the ICH2 is not powered by the system
154. d The power island should be at least 50 mils wide This voltage need not be supplied during Suspend to RAM Figure 17 Direct RDRAM Termination RSL Signals Terminator R packs direct rdram term Note It is necessary to compensate for the slight difference in electrical characteristics between a dummy via and a real via Refer to Section 2 7 2 7 for more information on via compensation 38 Design Guide intel InteP 820E Chipset Figure 18 Direct RDRAM Termination Example 2 7 2 3 Design Guide Vterm Capacitors Clock Termination GND CMD SCK Termination Vterm Direct RDRAM Ground Plane Reference RSL signals must be referenced to GND to provide the optimal current return path The Direct RDRAM ground plane reference must be continuous to the capacitors The ground reference island under the RSL signals must be continuous from the last RIMM to the back of the termination capacitors Choose a reference island shape that does not compromise power delivery to the components The return current will flow through the capacitors into the ground island and under the RSL traces Any split in the ground island will provide a suboptimal return path In a four layer board this will require the island to be on an outer layer The island should always be placed on the top layer 39 Inte 820E Ch
155. d return and produces the minimum current path loop area The parallel ground trace will have lower inductance than the ground plane because of the mutual inductance of the current in the clock trace For the Intel 820E chipset FC PGA clock routing guidelines refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Processor for the PGA370 Socket These guidelines can be downloaded from the Intel website at http developer intel com desig Definitions of Flight Time Measurements Corrections and Signal Quality Acceptable signal quality must be maintained over all operating conditions to ensure reliable operation Signal quality is defined by four parameters overshoot undershoot settling limit and ringback Timings are measured at the pins of the driver and receiver while signal integrity is observed at the receiver chip pad When signal integrity at the pad violates the following guidelines and adjustments must be made to flight time the adjusted flight time obtained at the chip pad can be assumed to have been observed at the package pin usually with a small timing error penalty Design Guide InteP 820E Chipset intel 3 5 1 Guard Band To account for noise sources that may affect the way AGTL signal becomes valid at a receiver is shifted by for measuring the minimum and maximum flight times The guard band region is bounded by and
156. daSN 7 o o 69951 886 01005 9005 asn a LES ids o SIX 6008 220 6005 zdasn x lt SIM 8006 req 8005 719851 Nidasn dd 1008 023 pide S 2 19851 Stay didasn ae mn 9445 2 lt lt 0d8sn gt 8 lt lt 8t saas 5045 c 0dasn Noden 8 epo m ozy raas lt dodasn saas EZ 054 SHM4 5121 zaas 4 Gay SANG SVE 2 01 rags 445 310801 841 odas gra 0005 08081 zi grav HMd av1 8 a Staad 9 009 2HMd eQv stay E IHM LOVI IHM3LQVA gt 510 iaad d 00 1 4 00 1 21 e taad 393 tds i 5 iaad INIGS OV UNO INIVIVOS OV Zedwine e yms 10N s im tn ONIGS OV ZH ONIVIVGS OV lt g OPNE sepnau 104 0610 6210 160v 1noas ZHOl 110 1708 OV 7 OW ov B et saad ONAS ferd 09 07 8 s L 189 OV RZA 13538 ov vaad pz 2602 0 2 Edad al 2 2 2008 id 99319 vq 99315 5 7 radd zza C M 10
157. decoupling capacitors should be close to the IC pins or positioned for the shortest connections to pins with wide traces to reduce impedance resistors in the signal path or on the voltage reference should be metal film Carbon resistors can be used for DC voltages and the power supply path where the voltage coefficient temperature coefficient and noise are not factors Regions between analog signal traces should be filled with copper which should be electrically attached to the analog ground plane Regions between digital signal traces should be filled with copper which should be electrically attached to the digital ground plane Locate the crystal or oscillator close to the codec Clocking is provided from the primary codec on the link via BITCLK and it is derived from a 24 576 MHz crystal or oscillator Refer to the primary codec vendor for the crystal or oscillator requirements BITCLK 15 a 12 288 MHz clock driven by the primary codec to the digital controller ICH2 and by any other codec present The clock is used as the time base for latching and driving data 91 Inte 820E Chipset intel 2 13 4 Motherboard Implementation The following design considerations are provided for the implementation of an ICH2 platform using AC 97 These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues These recommendations are not the only implementat
158. dependent NOTES 1 All times in nanoseconds 2 Processor values specified in this table are examples only Refer to the appropriate processor datasheet for the specification values Determine the Desired General Topology Layout and Routing After calculating the timing budget determine the approximate location of the processor and the chipset on the baseboard see Section p 10 Pre Layout Simulation Methodology Analog simulations are recommended for high speed system bus designs Start simulations prior to layout Pre layout simulations provide a detailed picture of the working solution space that satisfies the flight time and signal quality requirements The layout recommendations in the previous sections are based on pre layout simulations conducted at Intel By basing board layout guidelines on the solution space the iterations between layout and post layout simulation can be reduced Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis However simulation results at the device pins may later be used to correlate simulation performance against actual system measurements Sensitivity Analysis Pre layout analysis includes a sensitivity analysis using parametric sweeps Parametric sweep analysis involves varying one or two system parameters while all others e g driver strength package Zo So are held constant This allows the sensitivity of the proposed b
159. drop below the specified limits To avoid such a situation ensure that the appropriate amount of bulk capacitance is added in parallel with the voltage input pins It is recommended that the developer use the number of decoupling capacitors specified in the following table to ensure that the component maintains stable supply voltages The capacitors should be placed as close as possible to the package Refer to Figure 78 a layout example For prototype board designs it is recommended that the designer include pads for extra power plane decoupling caps Table 25 Decoupling Capacitor Recommendation Power Plane Pins Decoupling Capacitor Value Capacitors 3 3 V 6 0 1 3 3 V standby 1 0 1 processor 1 3 2 5 V 1 0 1 1 8 V core 2 0 1 1 8 V standby 1 0 1 5 V reference 1 0 1 5 V reference standby 1 0 1 Design Guide InteP 820E Chipset intel Figure 78 Decoupling Capacitor Layout momo 2 O
160. dual footprint for this particular solution uses a SSOP footprint for the Intel 82562 component and TQFP footprint for the Intel 82562 component The combined footprint for this configuration is shown in Figure 76hind Figure 76 Dual Footprint LAN Connect Interface Inte 82562 8 LAN CL LAN RSTSY LAN RXDI2 LAN TXD 2 4 Tl IO subsys dual footprint LAN conn Design Guide intel InteP 820E Chipset Figure 77 Dual Footprint Analog Interface Design Guide Intel 82562EH 82562ET Tip Intel TDP 82562EH TDN Ringi config Magnetics 4 RDP module TXP Intel 82562ET RDN TXN RJS config lO su bsys dual footprint analog Additional guidelines for this configuration are as follows L 0 5 inch to 6 5 inches Stub 0 5 inch Either the Intel 82562 or Intel 82562ET 82562EM component can be installed Not both Pins 28 29 and 30 of the Intel 82562ET component overlap pins 17 18 and 19 of the Intel 82562 component Overlapping pins are tied to ground No other signal pads should overlap or touch Signal lines LAN LAN RSTSYNC LAN RXD 0 LAN TXD 0 RDP RDN RXP Ring and RXN Tip are shared by the Intel 82562EH and Intel 82562ET component configurations No stubs should be present when the Intel 82562 component is installed The packages
161. e 29 EEPROM Interface Checklist Items Recommendations Reason Effect DOUT of EEPROM connector EE DOUT Prototype boards should include a Connected to EEPROM data input placeholder for a pull down resistor on this signal Input from EEPROM perspective signal line but should not populate the and output from ICH2 perspective resistor Connect to EE DIN of EEPROM or CNR connector EE DIN No extra circuitry is required Connect to ICH2 contains integrated pull up resistor for this signal Connected to EEPROM data output signal Output from EEPROM perspective and input from ICH2 perspective Table 30 FWH Flash BIOS Interface Checklist Items Recommendations Reason Effect FWH 3 0 LAD 3 0 LDRQ 1 0 No extra pull ups required Connect straight to FWH Flash BIOS ICH2 Integrates 24 kO resistors on these signal lines 126 Design Guide intel Table 31 Interrupt Interface Design Guide InteP 820E Chipset Checklist Items Recommendations Reason Effect PIRQ D A These signals require a pull up In a non APIC mode the PIRQx signals can be resistor A 2 7 kO pull up resistor routed to interrupts 3 4 5 6 7 9 10 11 12 14 or to Vcc 5 V or an 8 2 pull up 15 Each PIRQx line has a separate Route Control resistor to Vcc 3 3 V is Register recommended In the APIC mode these signals are connected
162. e Measurement 3 6 162 Receiver Pin Driver pin into test load Veer 200 mV Veer 100 mV VREF Veer 100 mV Tflight max Tflight min rising_edge_flight Conclusion AGTL routing requires a significant amount of effort Planning ahead and allocating the necessary time for correctly designing a board layout will give the designer the best chance of avoiding the more difficult task of debugging inconsistent failures caused by poor signal integrity Intel recommends planning a layout schedule that allows time for each of the tasks outlined in this document Design Guide 4 1 Table 55 Design Guide InteP 820E Chipset Clocking Clock Generation Two clock generator components are required in an Intel 820E chipset based system The Direct RDRAM clock generator generates clock for the Direct RDRAM interface while the CK 133 component generates clocks for the rest of the system Clock synthesizers that meet the Intel CK98 Clock Specification are suitable for an Intel 820E chipset based system The CK133 generates the clocks listed in the following table Intel 820E Chipset Platform System Clocks Name on CK133 Routed to Name on Frequency Voltage Receiver CPUCLK 0 3 system bus clock bus clock 2 2 processors 100 133 MHz MHz 25v 2 2 f nce 2722 EITH PCI LPC FWH Flash ICH2 ELM BIOS b
163. e better coupling of the electromagnetic fields to the board For noise free and stable operation place the crystal and associated discretes as close as possible to the Intel 82562ET or Intel 82562EM component keeping the trace length as short as possible Do not route any noisy signals in this area Intel 82562ET Intel 82562EM Component Termination Resistors The 120 Q 1 resistor used to terminate the differential transmit pairs TDP TDN and the 100 1 receive differential pairs RDP RDN should be placed as close as possible to the LAN connect component Intel 82562ET or Intel 82562 component The reason is that these resistors terminate the entire impedance seen at the termination source 1 Intel 82562 component including the wire impedance reflected through the transformer Figure 72 Intel 82562ET 82562EM Component Termination 2 22 4 4 116 LAN connect interface Magnetics Intel amp 82562 module Place termination resistors as close as possible to Intel 82562ET lO subsys 82562ET 82562EM term Critical Dimensions As shown in Figure 73 two dimensions must be considered during layout distance from the line RJ45 connector to the magnetics module and distance A from the Intel 82562ET or Intel 82562 component to the magnetics module Design Guide intel Figure 73 Caution Note Design Guide InteP 820E Chipset Cri
164. e command and data packets to be present on a signal wire at any given instant The driving device sends the next data out before the previous data has left the bus Figure 12 RIMM Diagram Design Guide The nature of the multi symbol interconnect forces many requirements on the bus design and topology First and foremost a drastic reduction in reflected voltage levels 15 required The interconnect transmission lines must be terminated at their characteristic impedance or the reflected voltage resulting from an impedance mismatch will degrade the signal quality These reflections will reduce noise and timing margins and will reduce the maximum operating frequency of the bus The reflections could create data errors 33 Inte 820E Chipset 2 7 1 2 7 2 34 intel Because of the tolerances of components such as PCBs connectors and termination resistors there will be some reflected voltage on the interconnect In this multi symbol interconnect timings are pattern dependent because the reflections interfere with the next transfer Additionally coupled noise can greatly affect the performance of high speed interfaces Just as in source synchronous designs the odd and even mode propagation velocity change creates a skew between the clock and data or command lines which reduces the maximum operating frequency of the bus Efforts must be made to significantly decrease the crosstalk as well as the other sources of s
165. e less than 7 3 Figure 62 SPKR Circuit 2 21 Integrated pull up 18 42 Effective impedance due to speaker and codec circuit Repr gt 50 Stuff jumper to O disable timeout lt lt feature 1 1 1 1 eee a el ee spkr_circ It should be noted that this is not the only solution to this problem Board designers can also isolate the load from the SPKR pin until POWEROK is in a stable high state This would allow a weak effective load to be implemented ICH2 Routing This section deals with the routing of the four added PCI IRQ signals implemented with the ICH2 The PCI interrupt request signals E H are new to the ICH2 These signals have been added to lower the latency caused by the presence of multiple devices on one interrupt line These new signals allow each PCI slot to have an individual PCI interrupt request line assuming that the system has four PCI slots The following table shows how the ICH2 uses the PCI IRQ when the I O APIC is active Table 21 Usage of APIC Interrupt Inputs 16 through 23 Design Guide No IOAPIC INTIN PIN Function in ICH2 using the PCI IRQ in IOAPIC 1 IOAPIC INTIN PIN 16 PIRQA 2 IOAPIC INTIN PIN 17 PIRQB AC 97 modem and SMBUS 3 IOAPIC INTIN PIN 18 PIRQC 4 IOAPIC INTIN PIN 19 PIRQD USB controller 1 5 IOAP
166. e time required for the driver output pin to reach the measurement voltage starting from the beginning of the driver transition at the pad Tre must be generated using the same test load for Tco Intel provides this timing value in the AGTL I O buffer models In this manner the following valid delay equation is satisfied Equation 8 Valid Delay Equation 3 2 6 3 Design Guide Valid delay Trucur svs TREF TFLIGHT MEASURED This valid delay equation yields the total time from when the driver sees a valid clock pulse to the time when the receiver sees a valid data input Flight Time Hardware Validation When a measurement is made in the actual system Tco and flight time do not need correction since these are the actual numbers These measurements include all of the effects pertaining to the driver system interface and the same is true for Tco Therefore the sum of the measured and the measured flight time must be equal the valid delay calculated previously 151 Inte 820E Chipset 3 3 3 3 1 3 3 2 152 Theory AGTL AGTL is the electrical bus technology used for the processor bus This is an incident wave switching open drain bus with external pull up resistors that provide both the high logic level and termination at each load The processor AGTL drivers contain a full cycle active pull up device to improve system timings The speci
167. ed by the Intel 820E chipset Figure 96 DRCG Frequency Selection U DRCG 2 REFCLK 12 PWRD 11 STOPB 15 MULTO 141 MULT1 24 so 23 1 13 GND 6 PCLKM SYNCLKN GPO1 GPO2 drcg freq sel 176 Design Guide 5 1 5 1 1 InteP 820 Chipset System Manufacturing Stack Up Requirement The Intel 820E chipset platform requires a board stack up with a 4 5 mil prepreg This change in dimension previously typically 7 mils is required because of the signaling environment used for the Direct RDRAM 2 0 and hub interface The RDRAM channel 15 designed for 28 O and mismatched impedance will cause signal reflections that will reduce the voltage and timing margins For example with a 2x clock during 400 MHz operation which equals a 1 25 ns sampling window only 100 ps is allotted for the total channel timing error Channel error results not only from PCB impedance but also from and 2 process variation Therefore it is critical to attain the required 28 impedance PCB Materials PCB tolerances determine Zo variation These tolerances include the trace width prepreg thickness plating thickness and dielectric constant The prepreg type affects the tolerance and including single ply 2 ply and resin content To design to the correct Zp variation the PCBs typically must meet the following specs see Table 62 Height tolerance 10 0 4 mil Width toler
168. el 82562 component provides an Ethernet 10 100 connection with the added flexibility of Alert on LAN More advanced LAN solutions can be implemented with the Intel 82550 or other PCI based product offerings Ultra ATA 100 Support The ICH2 82801BA component supports the IDE controller with two sets of interface signals primary and secondary that can be enabled independently tri stated or driven low The component supports UltraATA 100 Ultra ATA 66 UltraATA 33 and multiword p modes for transfers of up to 100 Mbytes sec Expanded USB Support The ICH2 component contains two USB host controllers Each host controller includes a root hub with two separate USB ports each for a total of four USB ports The addition of a USB host controller expands the functionality of the platform Manageability The Intel 820E chipset platform integrates several functions designed to manage the system and lower the system s total cost of ownership TCO These system management functions are designed to report errors diagnose the system and recover from system lock ups without the aid of an external microcontroller TCO Timer The ICH2 integrates a programmable TCO timer which is used to detect system locks The first expiration of the timer generates an SMI which the system can use to recover from a software lock The second expiration of the timer causes a system reset to recover from a hardware lock Processor Present Indicator The I
169. em timing budgets should include margin for SSO effects Stub Branch from the trunk terminating at the pad of an agent Test load Intel uses a 50 O test load for specifying its components Trunk The main connection excluding interconnect branches terminating at agent pads Undershoot Maximum voltage a signal may extend below Vss at the processor core pad See the respective processor s datasheet for the undershoot specifications Victim A network that receives a coupled crosstalk signal from another network is called the victim network guard guard band AVpegr defined above and below to provide a more realistic band model accounting for noise such as crosstalk noise and noise AGTL Design Guidelines The following step by step guideline was developed for systems based on two processor loads and one Intel 82820 MCH load Systems using custom chipsets will require timing analysis and analog simulations specific to those components The guideline recommended in this section is based on experience accumulated at Intel while developing many different systems based on the Intel Pentium Pro processor family and the Pentium processor First perform an initial timing analysis and topology definition Then perform pre layout analog simulations for a detailed picture of a working solution space for the design These pre layout simulations help define the routing rules prior to placement and rout
170. endations Onthe ICH2 Connect PICCLK directly to ground Connect PICDO and PICDI to ground through 10 resistor On the processor must be connected from the clock generator to the PICCLK pin on the processor Connect PICDO to 2 5 V through 10 resistors Connect PICDI to 2 5 V through 10 resistors SMBus SMLink Interface The SMBus interface on the ICH2 is the same as that on the ICH It uses two signals SMBCLK SMBDATA to send and receive data from components residing on the bus These signals are used exclusively by the SMBus host controller which resides inside the ICH2 If the SMBus is used only for the Rambus SPD one on each both signals should be pulled up to 3 3 V with a 4 7 kQ resistor The ICH2 incorporates new SMLink interface supporting Alert on LAN AOL AOL2 and slave functionality It uses two signals SMLINK 1 0 SMLINK 0 corresponds to an SMBus clock signal and SMLINK 1 corresponds to an SMBus data signal These signals are part of SMB slave interface For AOL functionality the ICH2 transmits heartbeat and event messages over the interface When the Intel 82562 LAN connect component is used the ICH2 s integrated LAN controller will claim the SMLink heartbeat and event messages and will send them out over the network An external AOL2 enabled LAN controller 1 Intel 82550 connects to the SMLink signals to receive he
171. er the minimum and maximum impedance of a trace based on the switching of neighboring traces This trace to trace coupling can be minimized by using wider spaces between the traces In addition these wider spaces reduce crosstalk and settling time Coupling between two traces is a function of the coupled length the distance separating the traces the signal edge rate and the degree of mutual capacitance and inductance To minimize the effects of trace to trace coupling the routing guidelines documented in this chapter should be followed In addition the PCB should be fabricated as documented in Section Except where noted all recommendations in this chapter assume 5 mil wide traces If the trace width 1s greater than 5 mils then the trace spacing requirements must be adjusted accordingly and linearly For example this chapter recommends routing most AGP signals with 5 mil traces on 20 mil spaces 1 4 If 6 mil traces are used then 24 mil spaces must be used also 1 4 Using a wider trace and therefore wider spaces will make routing more difficult Additionally these routing guidelines are created using the stack up described in Section If this stack up is not used extremely thorough simulations of every interface must be completed Using a thicker dielectric prepreg will make routing very difficult or impossible Component Quadrant Layout The quadrant layouts shown are approximate and the exact ball assignments should be used to
172. erized and budgeted appropriately for each design 143 Inte 820E Chipset 144 intel The following two tables were derived assuming the following CLKskew 0 2 ns Note This assumes that clock driver pin to pin skew is reduced to 50 ps by tying two host clock outputs together ganging at the clock driver output pins and the PCB clock routing skew 15 150 ps The system timing budget must assume 0 175 ns of clock driver skew if outputs are not tied together and a clock driver that meets the CK98 clock driver specification is being used 0 250 ns Some clock driver components may not support ganging the outputs Be sure to verify with your clock component vendor before ganging the outputs See the appropriate Intel 820E chipset documentation for details regarding the clock skew and jitter specifications Refer to Section 7 2 Chapter host clock routing details Table 52 Example Calculations for 133 MHz Bus Receiver CIk Tco Clkskew Period Processor Processor 750 50 120 20 020 20 0 250 250 0 40 40 2 75 J 82820 MCH Processori Sete te oe poe 0 40 40 NOTES All times in nanoseconds 2 BCLK period 7 50 ns 133 33 MHz 3 The flight times in this column include margin to account for the following phenomena that Intel has obse
173. erminated with 300 to 330 resistors For Intel 820E chipset FC PGA APIC PICD 1 0 routing guidelines refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Ill Processor for the PGA370 pode These g idelines can be downloaded from the Intel website at Design Guide intel InteP 820E Chipset Figure 74 PICD 1 0 Uniprocessor Topology Figure 75 PICD 1 0 Dual Processor Topology 3 2 5 3 2 5 1 Design Guide 1 5 Intel PGA370 Z 60 Q 15 picd uniprocessor topo pov 1 5 V 300 330 Intel PGA370 Intel PGA370 300 3300 2 60 Qt 15 picd dual processor topo Post Layout Simulation After layout extract the interconnect information for the board from the CAD layout tools Run simulations to verify that the layout satisfies the timing and noise requirements A small amount of tuning may be required Experience at Intel has shown that sensitivity analysis dramatically reduces the amount of tuning required Post layout simulations should take into account the expected variation for all interconnect parameters Intel specifies signal integrity at the device pads and therefore recommends running simulations at the device pads for signal quality However Intel specifies core timings at the device pins so simulation results at the device pins should be used later to correlate the simulation performance with actual system measurements
174. ers that allow their outputs to be tied together Intel strongly recommends running analog simulations to ensure that each design has adequate noise and timing margins Layout and Route Board Route the board satisfying the estimated space and timing requirements Also stay within the solution space set from the pre layout sweeps Estimate the printed circuit board parameters from the placement and other information including the following general guidelines e Distribute with a power plane or a partial power plane If this cannot be accomplished use as wide a trace as possible and route the trace with the same topology as the AGTL traces Keep the overall length of the bus as short as possible but do not forget the minimum component to component distances required to meet hold times Plan to minimize crosstalk with the following guidelines developed for the example topology given Signal spacing recommendations were based on fully coupled simulations Spacing may be decreased based upon the amount of coupled length Use a spacing to line width to dielectric thickness ratio of at least 3 1 2 If 4 5 this should limit coupling to 3 4 Minimize the dielectric process variation used in PCB fabrication Eliminate parallel traces between layers not separated by a power or ground plane able 54 ontains the trace width space ratios assumed for this topology The crosstalk cases considered in this guideli
175. esign Guide This chapter provides the schematic diagrams for the Reference Board Uniprocessor design Reference Design Feature Set Intel 820E chipset Memory controller hub MCH controller hub ICH2 FWH Flash BIOS Support for Coppermine FC PGA processors 100 MHz and 133 MHz system bus frequency Debug port IOAPIC integrated into ICH2 Direct RDRAM memory interface 300 MHz 356 MHz and 400 MHz Direct RDRAM support 2 RIMM sockets 5 PCI add in slots 5 REQ GNT pairs ICH2 supports 6 REQ GNT pairs Added 4 PCI interrupts total of 8 AGP universal connector 3 3 V 1 2x signaling 1 5 V 1x 2x signaling 2 IDE connectors with Ultra ATA 100 66 33 BMIDE PIO support ICH2 2 USB controllers total of 4 ports ATX power connector LPC Ultra Floppy disk controller 1 parallel port 1 serial port Keyboard controller Communications networking riser CNR Support for up to 6 channel audio WfM support Integrated system management SMBus slave interface access via SMLink Integrated power management Rev 1 0 compliant Rev 1 2 compliant Integrated LAN controller VRM 8 4 compliant voltage regulator Four layer design 195 Inte 820 Chipset This page is intentionally left blank 196 Design Guide 3 t 09401 81 6 0002 62 58 Q3siA3d 1891 06986 VINHOdIIVO WOS104
176. ever trace length matching requirements only must be met within each set of 2x 4x timing domain signals Design Guide Signal Groups Design Guide 1 timing domain 3 3 V WBF ST 2 0 REQ GNT PAR FRAME IRDY TRDY STOP DEVSEL 2 4 timing domains Set 1 15 0 C BE 1 0 AD STBO AD 5 used in 4x mode only Set 2 AD 31 16 C BE 3 2 AD STBI AD STBI used in 4x mode only Set 3 SBA 7 0 SB STB SB STB used in 4x mode only Miscellaneous async USB USB OVRCNT PME TYPDET PERR SERR INTA InteP 820 Chipset 61 Inte 820E Chipset 2 8 2 2 8 3 62 Table 10 AGP 2 0 Data Strobe Associations Associated Strobe in 1x Associated Associated Strobes Strobe in 2x in 4x AD 15 0 and Strobes not used in 1x mode All data is AD STBO AD 5 0 AD 5 C BE 1 0 sampled on rising clock edges AD 31 16 Strobes are not used in 1x mode All data is AD_STB1 AD_STB1 AD_STB1 and sampled on rising clock edges C BE 3 2 5 7 0 Strobes are not used 1x mode All data is SB STB SB STB SB STB sampled on rising clock edges Throughout this chapter the term data refers to AD 31 0 C BE 3 0 and SBA 7 0 The term strobe refers to AD STB 1 0 AD STB2 1 0 SB
177. experienced with PC architectures and board design This design guide assumes that the designer has a working knowledge of the vocabulary and practices of PC hardware design Chapter Introduction This chapter introduces the designer to the purpose and organization of this design guide and provides a list of references of related documents This chapter also provides an overview of the Intel 820E chipset Chapter 2 Layout Routing Guidelines This chapter provides a detailed set of motherboard layout and routing guidelines for designing an Intel 820E chipset based platform The motherboard s functional units are discussed e g chipset component placement system bus routing system memory layout display cache interface hub interface IDE AC 97 USB interrupts SMBUS PCD LPC FWH Flash BIOS and RTC Chapter 4 Advanced System Bus Design This chapter discusses the AGTL guidelines and theory of operation It also provides more details about the methodologies used to develop these guidelines Chapter 4 Clocking This chapter provides the motherboard clocking guidelines e g clock architecture routing capacitor sites clock power decoupling and clock skew Chapter 5 System Manufacturing This chapter includes the board stack up requirements Chapter 6 System Design Considerations This chapter includes the guidelines for power delivery decoupling thermal and power sequencing Appendix A Reference Des
178. f Direct RDRAM 4x 1 5 V interface 3 3 V 1x 2x and 1 5 V 1x 2x devices also supported Downstream hub interface for access to the ICH2 In addition the MCH provides arbitration buffering and coherency management for each of these interfaces Refer to Chapter p Layout Routing Guidelines for more information regarding these interfaces Controller Hub 2 ICH2 The ICH2 provides the I O subsystem with access to the rest of the system Additionally it integrates many functions The ICH2 integrates Upstream hub interface for access to the MCH Two channel Ultra ATA 100 bus master IDE controller Two USB controllers expanded capabilities for 4 ports O APIC e SMBus controller e FWH interface FWH Flash BIOS e LPC interface e AC 97 2 1 interface e PCI 2 2 interface e Integrated system management controller e Alert on LAN e Integrated LAN controller The ICH2 also contains the arbitration and buffering necessary to ensure efficient utilization of these interfaces Refer to Section more information on these interfaces 16 Design Guide 1 3 2 InteP 820 Chipset FWH Flash BIOS The FWH Flash BIOS component is a key element in providing a new security and manageability infrastructure for the PC platform The device operates under the FWH Flash BIOS interface and protocol The hardware features of this device include a unique Random Number Generator RNG register based
179. ferential pair Keep the signal trace lengths of a differential pair equal to each other Keep the total length of each differential pair under 4 inches Many customer designs with differential traces longer than 5 inches have had one or more of the following issues IEEE phy conformance failures excessive EMI and or degraded receive BER Do not route the transmit differential traces closer than 100 mils from the receive differential traces Do not route any other signal trace both parallel to the differential traces and closer than 100 mils from the differential traces 300 mils recommended Keep the maximum separation between differential pairs to 7 mils For high speed signals the number of corners and vias should be minimized If a 90 bend is required two 45 bends should be used instead Refer to Traces should be routed away from board edges by a distance greater than the trace height above the ground plane This allows the field around the trace to couple more easily to the ground plane rather than to adjacent wires or boards Do not route traces and vias under crystals or oscillators This will prevent coupling to or from the clock And as a general rule place traces from clocks and drives at a minimum distance from apertures at a distance greater than the largest aperture dimension Figure 68 Trace Routing Design Guide 107 Inte 820E Chipset intel 2 22 2 1 1 Trace Geometry and Length The ke
180. fication defines the following Termination voltage Receiver reference voltage as a function of termination voltage Processor termination resistance Rrr Input low voltage Input high voltage NMOS on resistance PMOS on resistance RONp Edge rate specifications Ringback specifications Overshoot undershoot specifications Settling limit Timing Requirements The system timing for AGTL depends on many things The following elements combine to determine the maximum and minimum frequencies supportable by the AGTL bus Timing range for each agent in the system Clock to output Tco Note that the system load is likely to differ from the specification load so the Tco observed in the system might differ from the of the specification Minimum required setup time to clock Tsu min for each receiving agent Range of flight time between each component including Propagation velocity for the loaded printed circuit board Board loading effect on the effective in the system Amount of skew and jitter in system clock generation and distribution Changes in flight time due to crosstalk noise and other effects Design Guide InteP 820 Chipset intel 3 3 3 Crosstalk Theory AGTL signals swing across a smaller voltage range and have a correspondingly smaller noise margin than technologies traditionally used in personal computer des
181. first connector If the trace lengths are matched between the balls of the MCH and the pin of the RIMM connector the length mismatch between the pad on the die and the ball has not been taken into account However given the package dimension which represents the length from the pad to the ball the routing can compensate for this package mismatch Therefore the board length mismatch can be increased The RSL channel requires the matching of the trace lengths from pad to pin within 10 mils Given the following definitions Package dimension Representation of length from pad to ball Board trace length Trace length on board Nominal RSL length Length to which all signals are matched Note There is not necessarily a trace that is exactly to nominal length but all RSL signals must be matched to within 10 mils of the nominal length The nominal RSL length is an arbitrary length within the limits of the routing guidelines to which all the RSL signals will be matched within 10 mils Design Guide intel InteP 820E Chipset RSL signals must satisfy the following equation Equation 2 RDRAM RSL Signal Trace Length Calculation Package dimension board trace length Nominal RSL length 10 mils Figure 30 Example of RDRAM Trace Length Matching Note L1 L2 Package dimensions L3 L4 Board trace length L1 45 23 Package R
182. gion back to Simulations performed on this topology should extrapolate back to the appropriate guard band boundary and not to So for maximum rising edge correction extrapolate back to For maximum falling edge corrections extrapolate back to AVper Figure 84 Overdrive Region and Vref Guard Band VREF 100 mV Overdrive Region 200 mV A REF Guardband VREF Veer 100 mV Overdrive Region 200 mV overdrive vref guard Design Guide 161 Inte 820E Chipset 3 5 4 intel Flight Time Definition and Measurement Timing measurements consist of minimum and maximum flight times to take into account the fact that devices turn on or off anywhere in guard band region This region is bounded by Veer and AVggr The minimum flight time for a rising edge is measured from the time the driver crosses when terminated to a test load to the time when the signal first crosses Vrer at the receiver see Figure 85 Maximum flight time 1s measured to the point where the signal first crosses assuming that the ringback edge rate and monotonicity criteria are met Similarly minimum flight time measurements for a falling edge are taken at the Veer crossing and maximum flight time is taken at the crossing Figure 85 Rising Edge Flight Tim
183. group associated differential pairs Note Over the length of a trace run each differential pair should be at least 0 3 inch from any parallel signal trace Physically group all components associated with one clock trace to reduce the trace length and radiation solate I O signals from high speed signals to minimize crosstalk which can increase EMI emission and susceptibility to EMI from other signals Avoid routing high speed LAN or phone line traces near other high frequency signals associated with a video controller cache controller processor or similar device 2 22 2 2 Power and Ground Connections Rules and guidelines for power and ground connections include the following All Vcc pins should be connected to the same power supply All Vas pins should be connected to the same ground plane Four to six decoupling capacitors including two 4 7 uF capacitors are recommended Place decoupling as close as possible to power pins 2 22 2 2 1 General Power and Ground Plane Considerations To properly implement the common mode choke functionality of the magnetics module the chassis or output ground secondary side of transformer should be physically separated from the digital or input ground primary side by at least 100 mils 108 Design Guide intel InteP 820E Chipset Figure 69 Ground Plane Separation 010 inches minimum separator Ground plane 1 Separate Chassis Ground Plane Good gr
184. h no ground isolation between the serpentines RSL traces do not cross power plane splits RSL signals also must not be routed next to a power plane split For example the RSL signals on the 4 layer cannot be routed directly below the ground isolation split on the 3 layer At all times uniform ground isolation flood 15 exactly 6 mils from the RSL signals ALL RSL CMD SCK and signals have CTABs on each RIMM connector pin Design Guide Design Guide InteP 820E Chipset RSL signals are routed adjacent to a ground reference plane This includes all signals from the last RIMM to the termination If signals are routed on the bottom from the last RIMM to the termination the ground reference plane on the 34 layer must extend under these signals and include the ground side of the decoupling capacitors CTABs must not cross or be on top of power plane splits They must be entirely referenced to ground At least 10 mils of ground flood isolation is required around all RSL signals Ground isolation must be exactly 6 mils from RSL signals Ground flood 18 recommended for isolation This ground flood should be as close as possible to the and the first RIMM If possible connect the flood to the ground balls pins on the MCH connector Clean routing Ensure a 1 x 0 1 capacitor on at each connector Use a 10 mil wide trace 6 mils minimum Do not route
185. hat supports Ultra DMA modes higher than 2 If ID Word 93 bit 13 is 1 then an 80 conductor cable is present If this bit is 0 then a legacy slave Device 1 is preventing proper cable detection and the BIOS should configure the system as though a 40 conductor cable were present and notify the user of the problem 81 Inte 820E Chipset intel 2 12 3 Device Side Cable Detection For platforms that must implement device side detection only e g NLX platforms a 0 047 uF capacitor is required on the motherboard as shown in the following figure This capacitor should not be populated when implementing the recommended combination host side device side cable detection mechanism described previously Figure 47 Device Side IDE Cable Detection IDE drive IDE drive 5V 10 ICH2 PDIAGHI PDIAG PDIAGH CBLID 0 047 pF T IDE drive IDE drive 5V 10 80 conductor IDE cable ICH2 PDIAGE PDIAG PDIAG CBLID 0 047 F IDE dev cable det This mechanism creates a resistor capacitor RC time constant The ATA mode 3 4 or 5 drive will drive PDIAG CBLID low and then release it pulled up through 10 resistor The drive will sample the signal after releasing it In an 80 conductor cable PDIAG CBLID is not connected through to the host so the capacitor has no effect In a 40 conductor cable the signal is connected to the
186. he Application Notes have schematics that illustrate the proper termination for unused RJ pins and the magnetics center taps 9 Incorrect differential trace impedances It is important to have an approximately 100 Q impedance between the two traces within a differential pair This becomes even more important as the differential traces become longer It is very common to see customer designs with differential trace impedances between 75 Q 85 even when the designers think they have designed for 100 Q To calculate differential impedance many impedance calculators only multiply the single ended impedance by two This does not take into account edge to edge capacitive coupling between the two traces When the two traces within a differential pair are kept close to each other see Note the edge coupling can lower the effective differential impedance by 5 Q to 20 Q A 10 Q to 15 Q drop in impedance is common Short traces will have fewer problems if the differential impedance is a little off 10 Use of an excessively large capacitor between the transmit traces and or excessive capacitance from the magnetics transmit center tap on the Intel 82562ET component s side of the magnetics to ground The use of capacitors with capacitances of more than a few pF in either of these locations can slow the 100 Mbps rise and fall time to such a degree that they fail the IEEE rise time and fall time specs will cause the return loss to fail at highe
187. he GPE1 STS register Table 33 USB Interface Checklist Items Recommendations Reason Effect USBP 3 0 P USBP 3 0 N See Figure 56 the circuitry needed each differential pair Design Guide intel Table 34 Power Management InteP 820E Chipset Checklist Items Recommendations Reason Effect THRM Connect to temperature sensor Input to 2 cannot float THRM Pull up if not used polarity bit defaults THRM to active low so pull up SLP_S3 No pull up pull down resistors needed Signal driven by ICH2 Signals driven by ICH2 SLP_S5 PWROK This signal should be connected to power Timing requirement monitoring logic and should go high no sooner than 10 ms after both Vcc 3_3 and Vcc 1_8 have reached their nominal voltages PWRBTN No extra pull up resistors This signal has an integrated pull up of 9 RI does not have an internal pull up An If this signal is enabled as a wake event 8 2 pull up resistor to the resume well is it is important to keep it powered during recommended the power loss event If this signal goes low active when power returns the STS bit will be set and the system will interpret that as a wake event RSMRST This signal should be connected to power Timing requirement monitoring logic and it should go high no sooner than 10 ms after both VccSus3 3 and VccSus1 8 have reached their nominal
188. he GPIO can disable the LAN microcontroller Figure 75 Intel 82562ET EM Disable Circuit VCC3 SBY RSM PWROK MMBT3906 GPIO LAN ENABLE Intel 82562ET EM Disable LAN Disable Circuit Design Guide 119 Inte 820 Chipset 120 intel There are four pins which are used to put the Intel 82562ET EM controller in different operating states Test Isol_Tck Isol Ti and Isol Tex The table below describes the operational disable features for this design Test En Isol Tck Isol Ti Isol Tex State 0 0 0 0 Enabled 0 1 1 1 Disabled w Clock low power 1 1 1 1 Disabled w out Clock lowest power The four control signals shown in the above table should be configured as follows Test En should be pulled down thru a 100 Q resistor The remaining 3 control signals should each be connected thru 100 Q series resistors to the common node 82652 Disable of the disable circuit 2 22 6 Intel 82562ET and Intel 82562EH Components Dual Footprint Guidelines These guidelines explain the proper layout for a dual footprint solution This configuration allows the developer to install either the Intel 82562 or Intel 82562 82562 component with only one motherboard design The following guidelines are for the Intel 82562 82562 components dual footprint option The guidelines called out in Sections 2 22 1 and 2 22 4 apply to this configuration The
189. herever the transitions occur as shown in the following two figures Again such decoupling should be in the vicinity of the signal transition via and should use capacitors with minimal effective series resistance ESR and effective series inductance ESL When placing the caps it is advisable to space the Vss and vias as closely as possible and or use dual vias since the via inductance may sometimes exceed the actual capacitor inductance Figure 82 Layer Switch with Multiple Reference Planes Signal Layer A r lt ea Signal Layer B lay_sw_mult_refplane r lt 158 Design Guide intel Figure 83 One Layer with Multiple Reference Planes Signal Layer A 3 4 3 3 Design Guide InteP 820E Chipset 1lay Mult refplane High Frequency Decoupling This section contains several high frequency decoupling recommendations that will improve the return path for an AGTL signal These design recommendations will very likely reduce the amount of SSO effects Just as layer switching and multiple reference planes can create discontinuities in an AGTL signal return path discontinuities also may occur when a signal transitions between the baseboard and cartridge Therefore providing adequate high frequency decoupling across and ground within the Intel PGA370 socket cavity and mounted on the primary side of the motherboard will minimize discontinui
190. ich is cut out of a power plane layer This floating plane acts as plate of a capacitor with an adjacent ground plane The signals can be routed through 75 resistors to the plane The stray energy on unused pins is then carried to the plane 2 22 4 6 1 Termination Plane Capacitance The recommended minimum termination plane capacitance is 1500 pF This helps reduce the amount of crosstalk on the differential pairs TDP TDN and RDP RDN from the unused pairs of the RJ45 Pads may be placed for additional capacitance to chassis ground which may be required if the termplane capacitance 18 not high enough to pass EFT Electrical Fast Transient testing To meet EFT requirements used discrete capacitors should be rated at 1000 Vac minimum Design Guide InteP 820E Chipset intel Figure 74 Termination Plane r TDP O N C L aud TDN i RDP CI EES RJ 45 RDN O Magnetics Module Termination Plane peer oe Additional capacitance that may need to be added for EFT testing term plane 2 22 5 Intel 82562ET EM Disable Guidelines To disable the Intel 82562 the device must be isolated disabled prior to reset PWROK asserting Using a GPIO such as GPO28 to be LAN Enable enabled high LAN will default to enabled on initial power up and after an AC power loss This circuit shown below will allow this behavior BIOS by controlling t
191. iderations apply to Intel 820E chipset FC PGA designs The design guidelines for the Pentium processor for the Intel PGA370 socket are found in the Intel 820 Platform Design Guide Addendum Revision 0 95 Section B 2 discusses specific system guidelines This is a step by step methodology that Intel has successfully used to design high performance desktop systems Section B 3 introduces the theories applicable to this layout guideline Section B 4 contains more details and insights Section 4 part of the rationale for the recommendations in the step by step methodology This section also includes equations that may be used for reference Terminology and Definitions Term Definition Aggressor The network that transmits a coupled signal to another network is called the aggressor network AGTL The processor system bus uses a bus technology called AGTL Assisted Gunning Transceiver Logic AGTL buffers are open drain and require pull up resistors for providing the high logic level and termination The processor s AGTL output buffers differ from the GTL buffers with the addition of an active pMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Bus agent Component or group of components that when combined represent a single load on the AGTL bus Corner Describes how a component performs when all parameters that could affect performa
192. ig o 0438 o lo cls3g 6 LW ELIW ZLW LLWOLW GTELTELT2LTELTOLTOXONO PIXELA LA EH LC LC LLC 010763 83 73 93 0N5 70 20 20 68 228 Leg eg zg 0Lg LA ZZY Lov V LV QNO rea Igav osav 080 6 gogy 8204 E KAM 9204 szav 2 veav ezav 61H 99 61H cgay zeav 8H LH ey 41H ogay 9H NH 610 610 s SH SIH 8109 iu 9 0 uey 559 86 1 TH 78 ETH yg EH SH 910 zH 21H siav m D 1H vIGV wy OH a 9287 1 gt Jivoy 31v902v Olav 15887 tid SNIOH 710415 0194 119915 sav INS zie 5 AN 104 152 LINT OLNIT Tro BANI sav ay 215 ANNO i va zen ty 015 H zy 905 ais H 9v 815 1H dI LIH 55 FH 75 961 2 09 E 68 100 A8SS 200 9 220 66 EDDA 158 80 158549 15194 95 416 865 475 qouMd WHA L zeav ieav eav Lav eevv Levv evv Lvv ed vLd eLd eLd LLd OLd eN PLN ELN ZLN
193. ign Schematics Uniprocessor This appendix provides a set of schematics for uniprocessor designs It also provides a feature list for board design 13 Inte 820E Chipset intel 1 2 Reference Documents Intel 820 Chipset Family 82820 Memory Controller Hub MCH Datasheet document number Intel 820 Chipset Design Guide Addendum for the Intel Pentium III Processor for the PGA370 Socket document number 298718 PCI Local Bus Specification Revision 2 2 Universal Serial Bus Specification Revision 1 0 Further information regarding the Pentium III processor can be found at http developer intel com design Pentiumlll 14 Design Guide Design Guide InteP 820E Chipset System Overview The Intel 820E chipset is designed for Intel Pentium Ill microprocessors and is the first chipset to support the integrated LAN capability and expanded USB capability It supports the 4x capability of the 2 0 Interface Specification and it supports the 400 MHz Direct RDRAM interface The 400 MHz 16 bit double clocked Direct RDRAM interface provides 1 6 GB s access to main memory To provide more efficient communication between chipset components the hub interface component interconnect is designed into the Intel 820E chipset Support of AGP 4x 400 MHz Direct RDRAM and the hub interface provides a balanced system architecture for the Pentium III processor minimizing bottlenecks and increasing system
194. igns so designers using AGTL must be more aware of crosstalk than they may have been in previous designs Crosstalk is caused through capacitive and inductive coupling between networks Crosstalk appears as both backward and forward crosstalk Backward crosstalk creates an induced signal in a victim network that propagates in a direction opposite to that of the aggressor s signal Forward crosstalk creates a signal that propagates in the same direction as the aggressor s signal On the AGTL bus a driver on the aggressor network is not at the end of the network Therefore it sends signals in both directions on the aggressor s network Figure 77 shows a driver on the aggressor network and a receiver on the victim network neither of which is at a network end The signal propagating in each direction causes crosstalk on the victim network Figure 77 Aggressor and Victim Networks Signal propagates in both directions on aggressor line Aggressor aggres victim Figure 78 Transmission Line Geometry A Microstrip B Stripline Signal lines Signal lines A AC ground plane A Microstrip B Stripline trans line geom Design Guide 153 Inte 820E Chipset 3 3 3 1 154 intel Additional aggressors are possible in the z direction if adjacent signal layers are not routed in mutually perpendicular directions Because crosstalk coupling coefficients decrease rapidly with inc
195. ime not the clock cycle time During 2 operation data is sampled twice during a 66 MHz clock cycle Therefore the data cycle time is 7 5 ns To allow for these high speed data transfers the 2x mode of AGP operation uses source synchronous data strobing Refer to Source Synchronous Strobing section During 4x operation the AGP interface uses differential source synchronous strobing With data cycle times as small as 3 75 ns and setup hold times of 1 ns the propagation delay mismatch is critical In addition to reducing propagation delay mismatch it is important to minimize noise Noise on the data lines will cause the settling time to be long If the mismatch between a data line and the associated strobe is too great or if there is noise on the interface incorrect data will be sampled The low voltage operation on AGP 1 5 V requires even more noise immunity For example during 1 5 V operation 18 570 mV Without proper isolation crosstalk could create signal integrity issues AGP Interface Signal Groups The signals on the AGP interface are broken into three groups 1x timing domain signals 2x 4x timing domain signals and miscellaneous signals Each group has different routing requirements In addition within the 2x 4x timing domain signals there are three sets of signals All signals in the 2 4 timing domains must meet minimum and maximum trace length requirements as well as trace width and spacing requirements How
196. iming Domain Routing Guidelines 2x 4x Timing Domain Routing Guidelines Ensure that each clock pair is length matched within 2 mils When clock signals serpentine they must serpentine together to maintain differential 14 6 routing 22 mil ground isolation is required on each side of the differential pair 59 Inte 820E Chipset 2 8 2 8 1 60 intel AGP 2 0 For detailed AGP interface functionality e g protocols rules signaling mechanisms refer to Revision 2 0 of the latest AGP Interface Specification obtainable from hittp www agpforum org This document focuses only on specific Intel 820E chipset platform recommendations Revision 2 0 of the AGP Interface Specification enhances the functionality of the original AGP Interface Specification Rev 1 0 by allowing 4x data transfers 4 data samples per clock and 1 5 V operation In addition to these major enhancements additional performance enhancement and clarifications e g fast write capability are included in the AGP Interface Specification Rev 2 0 The Intel 820E chipset supports the enhanced features of AGP 2 0 The 4 operation of the interface provides for quad pumping of the AD address data and SBA side band addressing buses That is data is sampled four times during each 66 MHz AGP clock This means that each data cycle is of a 15 ns 66 MHz clock or 3 75 ns It is important to realize that 3 75 ns 18 the data cycle t
197. imized to fit in a very small space Crystals and Oscillators To minimize the effects of EMI clock sources should not be placed near I O ports or board edges Radiation from these devices may be coupled onto the I O ports or out of the system chassis Crystals should also be kept away from the HomePNA magnetics module to prevent communication interference The crystal s retaining straps if they exist should be grounded to prevent possible radiation from the crystal case and the crystal should lie flat against the PC board to provide better coupling of the electromagnetic fields to the board Design Guide 2 22 3 4 70 Design Guide InteP 820E Chipset For noise free and stable operation place the crystal and associated discretes as close as possible to the Intel 82562EH component keeping the length as short as possible Do not route any noisy signals in this area Phoneline HPNA Termination The transmit receive differential signal pair 15 terminated with a pair of 51 1 0 196 resistors This parallel termination should be placed close to the Intel 82562 component The center common point between the 51 1 Q resistors is connected to a voltage divider network The opposite end of one 806 resistor is tied to VCCA 3 3V and the opposite end of the other 806 resistor and the cap are connected to ground The termination is shown in the following figure Intel 82562EH Component Termination
198. impedance OEMs should verify the actual trace impedance and adjust their layout accordingly If the actual impedance is consistently low a target of 105 110 Q should compensate for second order effects 117 Inte 820E Chipset 2 22 4 5 2 22 4 6 118 intel 2 22 4 4 2 Distance from the Intel 82562ET Component to the Magnetics Module Distance in Figure 73 also should be designed to be less than 1 inch between devices The high speed nature of the signals propagating through these traces requires that the distance between these components be observed closely Generally speaking any trace section intended for use with high speed signals should comply with proper termination practices Proper signal termination can reduce reflections caused by impedance mismatches between a device and the traces Reflected signals may have a high frequency component that may contribute more EMI than the original signal itself For this reason these traces should be designed with a 100 Q differential value These traces also should be symmetric and of equal length within each differential pair Reducing Circuit Inductance The following guidelines explain how to reduce circuit inductance in both backplanes and motherboards Traces should be routed over a continuous ground plane with no interruptions If there are vacant areas on a ground or power plane the signal conductors should not cross them This increases inductance and associated
199. ing After routing extract the interconnect database and perform post layout simulations to refine the timing and signal integrity analysis Validate the analog simulations when actual systems become available The validation section describes a method for determining the flight time in the actual system Guideline Methodology nitial timing analysis Determine general topology layout and routing Pre layout simulation Sensitivity sweep Monte Carlo Analysis Place and route board Estimate component to component spacing for AGTL signals Lay out and route board Post layout simulation Interconnect extraction Intersymbol interference ISI crosstalk and Monte Carlo Analysis e Validation Measurements Determining flight time 141 Inte 820E Chipset intel 3 2 1 Initial Timing Analysis Perform an initial timing analysis of the system using the following two equations which are the basis for timing analysis To complete the initial timing analysis values for clock skew and clock jitter are needed along with the component specifications These equations contain a multi bit adjustment factor to account for multi bit switching effects e g SSO push out or pull in that often are hard to simulate These equations do not take into consideration all signal integrity factors that affect timing Additional timing margin should be budgeted to allow for these sources of noise Equation 4
200. intel Intel 820E Chipset Design Guide May 2001 Document Number 298187 003 Inte 820 Chipset Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 820E Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specific
201. ion or a complete checklist but they are based on the ICH2 platform Components such as FET switches buffers or logic states should not be implemented on the AC link signals except for AC_RST Doing so would potentially interfere with timing margins and signal integrity The ICH2 supports wake on ring from 51 54 states via the 97 link The codec asserts SDATAIN to wake the system To provide wake capability and or caller ID standby power must be provided to the modem codec If no codec is attached to the link internal pull downs will prevent the inputs from floating so external resistors are not required The ICH2 does not wake from the S5 state via the AC 97 link should be routed through the audio codec Care should be taken to avoid the introduction of a pop when powering the mixer up or down 2 14 USB 2 14 1 Using Native USB Interface The following are general guidelines for the USB interface e Unused USB ports should be terminated with 15K pull down resistors on both P P data lines e 15 ohm series resistors should be placed as close as possible to the ICH2 lt 1 inch These series resistors are required for source termination of the reflected signal e An optional 47 pF cap may be placed as close to the USB connector as possible on the USB data lines 0 P1 P2 P3 This can be used for signal quality rise fall time and to help minimize EMI radiation e 15K 5
202. ion 28 Do not forget ground floods and stitching Impedance Calculation Tools 3D field solvers such as those by HP Ansoft Sonnet and Polar are most accurate when calculating the impedance Z calculators based on equations zcalc also are fairly accurate The differences are listed in the following table Table 62 3D Field Solver vs ZCALC Design Guide InteP 820E Chipset intel 5 1 7 Testing Board Impedance The Intel Printed Circuit Board Test Methodology document order 298179 001 should be used to ensure boards are within the 280 10 requirement This document be found at http developer intel com 5 1 8 Board Impedance Stack up Summary 1 7628 cloth 1 ply 0 007 inch when cured with 40 resin is the most popular and highest volume PCB production today This stack up will make routing impossible Fab construction 4 layers e Z 70 0t 15 Figure 99 7 mil Stack Up Not Routable Component side layer 0 5 oz 7 mil prepreg Ground layer 2 1 oz C Not Routable Total thickness 62 mils Ground layer 3 1 oz Cu 7 mil prepreg Solder side layer 4 0 5 oz Cu 7mil_stackup 2 2116 cloth 1 ply 0 0045 inch when cured with 53 resin is the second highest volume cloth in production today Because of the impedance and layout requirements of traces for Direct RDRAM AGP 2 0 and the hub interface this
203. ipset Figure 19 Incorrect Direct RDRAM Ground Plane Referencing 1 8 V Plane 3 3 V Plane 6000000000000000000 0000 60000000000000000000000 60000000000000000000000 06060000000000000000000 06000000000000000005050000 060060000000006000000000 e0000000000000000000000 00000000000000000000000 00000000000000000000009 0000000000000000000 8 e000000000000000000000 60000000000000000000000 dir Rambus gnd plane ref incorrect Figure 20 Direct RDRAM Ground Plane Reference Required gt o RIMM1 GND Plane PRG 0 9 RIMM2 9090909090909090909090 990809035 ob o 9 0000000000000000000 o SO 60 0000909090990 VTERM resistors Extend GND plane VTERM capacitors reference island beyond Vterm layer shown VTERM capacitors dir Rambus gnd plane ref The ground reference island under the RSL signals MUST be connected to the ground pins on the RIMM connector and the ground vias used to connect the ground isolation on the first and fourth layers 40 Design Guide 2 7 2 4 InteP 820 Chipset four layers of the motherboard require correct grounding between the RSL signals on the motherboard as follows a
204. irection on the network This causes backward crosstalk from segments on two sides of a driver The pulses from the backward crosstalk travel toward each other meet and add at certain moments and positions on the bus This can double the voltage 1 e noise from crosstalk Potential Termination Crosstalk Problems It may not be suitable to utilize commonly used pull up resistor networks for AGTL termination These networks have a common power or ground pin at the extreme end of the package shared by 13 to 19 resistors for 14 pin and 20 pin components These packages generally have too much inductance to maintain the voltage current needed at each resistive load Intel recommends using discrete resistors resistor networks with separate power ground pins for each resistor or working with a resistor network vendor to obtain resistor networks that have acceptable characteristics Design Guide intel InteP 820E Chipset 3 4 More Details and Insight 3 4 1 Textbook Timing Equations The textbook equations used to calculate the propagation rate of a are the basis for spreadsheet calculations of timing margin based on the component parameters These equations are as follows Equation 9 Intrinsic Impedance Zo Lo Co Q Equation 10 Stripline Intrinsic Propagation Speed So 1 017 ns ft Equation 11 Microstrip Intrinsic Propagation Speed So microstrip 1 017 0 475 x
205. irectly to the 3 3 V DRCG power flood on the top layer Use 2 vias on the ground side of each Good DRCG output network layout Series resistors 39 Q should be very near pins Parallel resistors 51 should be very near series resistors should be 18 mils wide from the CTM CTM pins to the resistors should be 14 on 6 routed differentially as close as possible after the resistor network When not 14 on 6 the clocks should be 18 mils wide Ensure that CTM CTM ground referenced and the ground reference is connected to the ground plane every 0 5 inch to 1 inch Ensure that are ground isolated and the ground isolation 18 connected to the ground plane every 0 5 inch to 1 inch Ensure that 15 pF EMI capacitors to ground are removed The pads are not necessary and removing the pads provides more space for better placement of other components Ensure the that 4 pF EMI capacitor is implemented but do not assemble the capacitor Good RSL transmission lines RSL traces are 18 mils wide When RSL traces neck down to exit the MCH BGA the minimum width is 15 mils and the neckdown is no longer than 25 mils in length RSL traces do not neck down when routing into the RIMM connector If tight serpentining is necessary 10 mil ground isolation must be between serpentine segments 1 an RSL signal cannot serpentine so tightly that the signal 1s adjacent to itself wit
206. ive list of devices offered and features supported In addition depending on system requirements a device bay controller and USB hub could be integrated into the LPC super I O component For systems requiring ISA support ISA IRQ to serial IRQ converter is required This converter could be integrated into the super I O 25 Inte 820 Chipset 26 This page is intentionally left blank Design Guide Caution 2 1 2 2 Design Guide InteP 820E Chipset Layout Routing Guidelines This chapter documents the motherboard layout and routing guidelines for Intel 820E chipset based systems This chapter does not discuss the functional aspects of any bus or the layout guidelines for an add in device If the guidelines in this document are not followed it is very important to complete thorough signal integrity and timing simulations for each design Even if the guidelines are followed critical signals still should be simulated to ensure proper signal integrity and flight time As bus speeds increase it is imperative that the guidelines documented be followed precisely Any deviation from these guidelines must be simulated General Recommendations The trace impedance typically noted 1 60 10 15 the nominal trace impedance That is it is the impedance of a trace when not subjected to the fields created by changing the current in neighboring traces When calculating flight times it is important to consid
207. kew To achieve these bus requirements the Direct RDRAM channel is designed to operate as a transmission line All components including the individual RDRAMs are incorporated into the design to create uniform bus structure that can support up to 33 devices including the running at 800 megatransfers second MT s Stack Up The perfect matching of transmission line impedance and a uniform trace length is essential for the Direct RDRAM interface to work properly Maintaining 28 1096 loaded impedance for every RSL Direct RDRAM Signaling Level signal has changed the requirements for trace width and prepreg thickness for the Intel 820E chipset platform Refer to Section Achieving a 28 nominal impedance with a traditional 7 mil prepreg requires 28 mil wide traces These traces are too wide to break out of the two rows of RSL balls on the MCH To reduce the trace width a 4 5 mil thick prepreg is required This thinner prepreg allows 18 mil wide traces to meet the 28 10 nominal impedance requirement Refer to Section for detailed stack up requirements Direct RDRAM Layout Guidelines The signals on the Direct RDRAM channel are broken into three groups RSL signals CMOS signals and clocking signals as follows RSL signals 8 01 8 0 RQ 7 0 CMOS signals CMD high speed CMOS signal SCK high speed CMOS signal SIO Clocking signals CTM
208. le UP Intel 820E chipset based system design 2 The trace length limitation between critical connections will be discussed later in this document 3 figure 15 for reference only Figure 7 Sample ATX and NLX MCH ICH2 Component Placement a Sample ATX MCH ICH2 Component Placement b Sample NLX MCH ICH2 Component Placement RDRAM Termination Direct RDRAM RDRAM Termination CPU Host Bus atx mch ich2 place CPU Host Bus nix mch ich2 place Note Actual ICH2 placement may vary Design Guide 29 Inte 820E Chipset 2 4 Core Chipset Routing Recommendations The following two figures show MCH core routing examples Figure 8 Primary Side MCH Core Routing III i a 8 LI eI z i HH i Le 1 m es if Ke 30 Design Guide intel Figure 9 Secondary Side MCH Core Routing Example ATX InteP 820E Chipset T TET e Design Guide 31 Inte 820E Chipset 2 9 intel Source Synchronous Strobing A technology used in AGP 4x Direct RDRAM and the hub interface source synchronous strobing allows very high data transfer rates As buses become faster and cycle times become shorter the propagation delay becomes a limiting factor in the bus speed Source synchronous strobi
209. lights design considerations that should be reviewed before manufacturing an Intel 820E chipset based motherboard that implements an ICH2 The entries in this checklist should provide the important connections to these devices and any critical supporting circuitry This is not a complete list and it doesn t guarantee that a design will function properly This list is only a reference For correct operation all design guidelines within this document must be followed Table 26 PCI Interface Design Guide Checklist Items Recommendations Reason Effect FYI Inputs to the ICH2 must not be left floating Many GPIO signals are fixed inputs that must be pulled up to different sources See the GPIO section for recommendations PERR SERR PLOCK STOP DEVSEL TRDY IRDY FRAME REQ 4 0 GPIO 1 0 THRM These signals require a pull up resistor 8 2 pull up resistor to Vcc 3 3 V or a 2 7 pull up resistor to Vcc 5 V is See the PCI 2 2 Component Specification Pull up recommendations for Vcc 3 3 V and 5V recommended PCIRST The PCIRST signal should be Improves signal integrity buffered to for the IDERST signal 33 Q series resistor to IDE connectors PCIGNT No external pull ups are required These signals are actively driven by the on PCI GNT signals However if ICH2 external pull ups are implemented they must be pulled up to Vcc 3 3 V PME No extra pull up resi
210. locking and hardware based locking ISA Bridge For legacy needs ISA support is an optional feature of the Intel 820E chipset Implementations that require ISA support can benefit from the enhancements of the Intel 820E chipset while ISA less designs are not burdened with the complexity and cost of the ISA subsystem The Intel 820E chipset platform with optional ISA support takes advantage of an external component supplier s ISA bridge which is a PCI to ISA bridge that resides on the PCI bus of the ICH2 Bandwidth Summary The following table provides a summary of the bandwidth requirements for the Intel 820E chipset Table 1 Intel 820E Chipset Platform Bandwidth Summary Design Guide Clock Speed Samples Data Rate Data Width Bandwidth MHz Per Clock megasamples s Bytes MB s RDRAM 266 300 356 400 533 600 711 800 1066 1200 1422 1600 17 Inte 820E Chipset 1 3 3 System Configuration The following figures show typical platform configurations using the Intel 820E chipset Figure 1 Intel 820E Chipset Platform Performance Desktop Block Diagram Intef Pentiurfi Processor m 820E Chipset 1 1 Intel 82820 Main 4x a Memory Graphics 20 ___ Controller Hub Direct RDRAM Controller Hub Interface 4 IDE Drives 100 66 33 7
211. lzrr lt cg 0 22253 Pace 288 7 822 2864 58 Se HSH 28 E 3 1 58 10 ae 5 gt 086 0868 34 ex lo zl sy 52 560 Of ES 8565 OZ 8 gt PAL 2506 of gg 1 HOW eeu 43H dOV HOW 9oeld 48 ain goin or f 8 199A 2 S x gn 99 HOW pud 0 gm OvstGH a m lg na H pod 5 56 PH GERGH 3807 5 p 03330 24 883430 ZI SC Sasa bs po Asaa 1 80H 29 Rea des pp flud8 SERQH La 2120 ley S 0H x gt 5 53 S 0H pis gt p 90 veHOH ex vEROH eius 2 15990 yg 818849 7n 640H S ZM Le VH Le 0H o a bo Le VH SW 91 L 0H 150 1SOH 58 258 0 TN IM OE 0H kl 9 m NE i eve cu c 206 920 928 PI S2 VH SI Ren 9 NT
212. m floating if a device is not present on the primary IDE interface 83 Inte 820E Chipset 2 12 5 Secondary IDE Connector Requirements Figure 49 Connection Requirements for Secondary IDE Connector PCIRST_BUF 22 47 Q PCIRST gt Reset SDD 15 0 SDA 2 0 SDCS1 SDCS3 SDIOR SDIOW SDDREQ 3 3 V 3 3 V 4 7 KQ 5 8 2 10 Secondary IDE Connector SIORDY IRQ15 SDDACK GPIOy PDIAG CBLID 10 CSEL N C Pins 32 amp 34 Due to ringing PCIRST 7 gt must be buffered IDE secondary conn require NOTES 1 22 Q to 47 series resistors are required on RESET The correct value should be determined for each unique motherboard design based on the signal quality 2 An 8 2 to 10 pull up resistor is required on IRQ14 and IRQ15 to VCC3 3 4 7 pull up resistor to VCC3 is required on PIORDY and SIORDY 4 Series resistors can be placed on the control and data lines to improve signal quality The resistors are place as close as possible to the connector Values are determined for each unique motherboard design 5 A 10 pull down resistor to ground is required on the PDIAG CBLID signal This prevents the GPI pin from floating if a device is not present on the secondary IDE interface 84 Design Guide InteP 820 Chipset AC 97 The ICH2 implements an 97 2 1 compliant digital controller Any codec attached to the ICH2 AC link also must
213. mpedances Motherboard impedances should be controlled to minimize the effect of any mismatch between the motherboard and an add in card An impedance of 60 Q 15 is strongly recommended Otherwise the signal integrity requirements may be violated Line Termination Line termination mechanisms are not specified for the LAN connect interface Slew rate controlled output buffers provide acceptable signal integrity by controlling signal reflection overshoot undershoot and ringback 33 series resistor can be installed at the driver side of the interface if the developer has concerns about overshoot undershoot Note that the receiver must allow for any drive strength and board impedance characteristic within the specified ranges Design Guide intel InteP 820E Chipset 2 22 2 General LAN Routing Guidelines and Considerations 2 22 2 1 General Trace Routing Considerations Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on board sections where high speed signals exist Signal traces should be kept as short as possible to decrease interference from other signals including those propagated through the power and ground planes Comply with the following suggestions to help optimize board performance The maximum mismatch between the length of the clock trace and the length of any data trace is 0 5 inch Maintain constant symmetry and spacing between the traces within a dif
214. multaneously by more than one agent These signals may require more attention during the layout and validation portions of the design When a signal is asserted 1 driven low by two or more agents on the same clock edge the two falling edge wavefronts will meet at some point on the bus and can sum to form a negative voltage The ringback from this negative voltage can easily cross into the overdrive region The signals are AERR BERR BINIT BNR HIT and HITM This document addresses AGTL layout for both one way and two way 133 MHz 100 MHz processor Intel 820E chipset systems Power distribution and chassis requirements for cooling connector location memory location etc may constrain the system topology and component placement location thereb constraining the board routing These issues are not addressed directly in this document Section l 2 contains a listing of several documents that address some of these issues Host Clock Routing For Intel 820E chipset FC PGA clock routing guidelines refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium III Processor for the PGA370 Socket These guidelines can be downloaded from the Intel website at http developer intel com design chipsets designex 298178 htm APIC Data Bus Routing Intel recommends using the in line topology shown in the following two figures for the APIC data signals PICD 1 0 For dual processor systems the network should be dual end t
215. must be length matched to less than 0 1 inch That 15 a strobe and its complement must be the same length within 0 1 inch Figure 36 AGP 2x 4x Routing Example for Interfaces 6 Inches Design Guide 5 mil trace BE d 2 signal 15 mils 2 signal 5 mil trace 2 5 2 signal 20 d 2 signal 5 mil trace 5 AGP STB 15 STB 5 mil trace 3 AGP STB 20 21 STB 5 mil trace 2 signal 15 mie 2 signal v 2 4 signal 2 signal STB STB length Associated AGP 2 data signal length Min Max AGP_2x 4x_routing Interfaces gt 6 Inches and lt 7 25 Inches Longer lines have more crosstalk Therefore to reduce skew longer line lengths require a greater amount of spacing between traces For line lengths greater than 6 inches and less than 7 25 inches 1 4 routing is required for all data lines and strobes For these designs the line length mismatch must be less than 0 125 inch within each signal group between all data signals and the strobe signals For example if a set of strobe signals e g AD STBO and AD_STBO are 6 5 inches long the data signals associated with those strobe signals e g AD 15 0 and C BE 2 0 can be 6 475 inches to 6 625 inches long Another strobe set e g SB STB and SB_STB could be 6 2 inches long and the data signals associated with those strobe signals e g SBA 7 0 can be 6 075 inches to
216. n Design Guide InteP 820 Chipset 7 UB SEN ERE 226 gm es uet Figure 21 Connector Compensation Example 43 Design Guide Inte 820E Chipset 44 Figure 22 Section A See Note Top Layer intel ES je ee 34 44 4 44 4 4 Note Refer to For clarity the ground flood was removed from the picture Design Guide InteP 820 Chipset intel Figure 23 Section A See Note Bottom Layer bi OHS Ot HA HO 9 O44 OOF GOO ERE 1 1 1 ke 15221 E 51 1 2 MSS S 74 Note Referto For clarity the ground flood was removed from the picture 45 Design Guide Inte 820E Chipset Figure 24 Section B See Note Top Layer Note Refer to For clarity the ground flood was removed from the picture 46 Design Guide intel InteP 820E Chipset Figure 25 Section B See Note Bottom Layer Note 2 t 11311110 AAN 00000200002 dob b RR to o 4 ll 21 i Refer to For clarity the ground flood was removed from the picture 2 7 2 4 1 Direct RDRAM Channel Connector Compensation Enhancement Recommendation From further analysis it was
217. n external component supplier The Intel 820E chipset contains two core components the Memory Controller Hub and the I O Controller Hub 2 ICH2 The MCH integrates the 133 MHz processor system bus controller an AGP 2 0 controller a 400 MHz Direct RDRAM controller and a high speed hub interface for communication with the ICH2 The ICH2 integrates an Ultra ATA 100 controller two USB host controllers an LPC interface controller an FWH Flash BIOS interface controller a PCI interface controller an AC 97 digital controller an integrated LAN controller and a hub interface for communication with the MCH The Intel 820E chipset provides the data buffering and interface arbitration required to ensure that the system interfaces operate efficiently and provide the system bandwidth necessary to obtain peak performance with the Pentium processor 15 Inte 820 Chipset intel 1 3 1 Chipset Components The Intel 820E chipset consists of the Intel 82820 Memory Controller Hub MCH and the Intel 82801 Controller Hub ICH2 Additional functionality can be provided through the use of PCI to ISA bridge Memory Controller Hub MCH The MCH provides the interconnect between the Direct RDRAM and the system logic It integrates the following functions e Support for single or dual Intel PGA370 processors with a 100 MHz or 133 MHz system bus 256 MHz 300 MHz 356 MHz or 400 MHz Direct RDRAM interface supporting 1 GB o
218. n in the preceding figure uses an FET switch to switch between the locally generated for 3 3 V add in cards and the source generated for 1 5 V add in cards Use of the source generated at the receiver is optional and is a product implementation issue beyond the scope of this document 69 Inte 820E Chipset 2 8 9 2 8 10 70 intel Compensation The MCH AQP interface supports resistive buffer compensation RCOMP Tie the GRCOMP pin to a 40 Q 2 or 39 Q 1 pull down resistor to ground via a 10 mil wide very short lt 0 5 inch trace AGP Pull Ups AGP control signals require pull up resistors to Vppo on the motherboard to ensure that they maintain stable values when no agent is actively driving the bus The signals requiring pull up resistors are e 1 timing domain signals FRAME TRDY IRDY DEVSEL STOP SERR PERR RBF PIPE REQ WBF GNT ST 2 0 It is critical that these signals be pulled up to not 3 3 V The trace stub to the pull up resistor on 1x timing domain signals should be kept at less than 0 5 inch to avoid signal reflections from the stub The strobe signals require pull up pull downs on the motherboard to ensure that they maintain stable values when no agent is driving the bus INTA and INTB should be pulled to 3 3 V not Vppo e 2x Ax timing domain signals AD 5 1 0 pull up
219. n n Ball n n 13 e e ER VOX MERE t t V r t e X 2 14 m L1 L3 Nominal RSL length 10 mils L2 L4 Nominal RSL length 410 mils rdram tr len vsd Refer to the Intel 820 Chipset Family 82820 Memory Controller Hub Datasheet for the component package dimensions The RDRAM clocks and must be longer than the RDRAM signals due to their increased trace velocity because they are routed as a differential pair To calculate the length for each clock the following formula should be used Equation 3 RDRAM Clock Signal Trace Length Calculation Design Guide Clock length Nominal RSL signal length package board x 1 021 This formula yields clock signals 21 mils inch longer than the nominal length The lengthening of the clock signals to compensate for their trace velocity change only applies to routing between the MCH and the first RIMM The clock signal lengths should be matched to the RSL signals between RIMMs For more detailed clock routing guidelines refer to Chapter Clocking The high speed CMOS signals must be length matched to the RSL signals within 1200 mils 1 2 inches as the result of a timing requirement between the CMOS and RSL signals during NAP Exit and PDN Exit 51 Inte 820E Chipset 2 7 2 T intel It is necessary to compensate for the slight difference in
220. nal layer independently of the layer on which the RSL signal is routed The following example calculation uses Equation 1 Approximate Copper Tab Area Calculation ffor a board with an of 4 2 and a prepreg thickness of 4 5 mils Note that these numbers vary with the difference in prepreg thickness Table 6 Copper Tab Area Calculation Layer Dielectric Separation Min Air Gap Compensating CTAB Area Thickness Between Ground between Capacitance in sq mils Signal Traces Flood Signal amp Cplate pF amp Copper Tab GND Flood Top 4 5 6 10 6 0 65 0 85 2810 3680 4 5 6 10 6 1 20 1 40 5194 6060 Note that more than one copper tab shape may be used as shown in The dimensions are based on the copper area over the ground plane The actual length and width of the tabs may differ due to routing constraints e g if tab must extend to center of hole or anti pad Figures 26 through 28 show a tab compensation capacitor routing example Note that the capacitor tabs must not interrupt ground floods around the RIMM pins and they must be connected to avoid discontinuity in the ground plane as shown Figure 26 Top Layer CTAB with RSL Signal Routed on the Same Layer 0 8 pF Figure 27 48 Design Guide InteP 820 Chipset intel The CTAB can be implemented on the multiple layers to minimize routing and space constraints
221. nce are adjusted to have the same effect on performance Examples of these parameters include variations in the manufacturing process the operating temperature and the operating voltage The resulting performance of an electronic component that may change as a result of corners includes but is not limited to the following clock to output time output driver edge rate output drive current and input drive current A slow corner means a component operating at its slowest weakest drive strength performance Conversely a fast corner means a component operating at its fastest strongest drive strength performance Operation or simulation of a component at its slow and fast corners should bound the extremes between slowest weakest performance and fastest strongest performance Crosstalk The reception on a victim network of a signal imposed by an aggressor network s through inductive and capacitive coupling between the networks Backward crosstalk Coupling that creates a signal in a victim network that travels in the direction opposite to the aggressor s signal Forward crosstalk Coupling that creates a signal in a victim network that travels in the same direction as the aggressor s signal Even mode crosstalk Coupling from multiple aggressors when all aggressors switch in the direction in which the victim is switching Odd mode crosstalk Coupling from multiple aggressors when all aggressors switch in the direction opposi
222. nce should be controlled to To meet timing and signal quality 100 0 requirements 13 For high speed signals the number of corners and To meet timing and signal quality vias should be minimized If a 90 bend is required requirements itis advisable to use two 45 bends 14 Traces should be routed away from board edges by This allows the field around the a distance greater than the trace height above the trace to couple more easily to the ground plane ground plane rather than to adjacent wires or boards 15 Do not route traces and vias under crystals or This will prevent coupling to or oscillators from the clock 16 Ration of trace width to height above the ground To control trace EMI radiation plane should be between 1 1 and 3 1 17 Traces between decoupling and 1 filter capacitors Long and thin lines are more should be as short and wide as practical inductive and would reduce the intended effect of decoupling capacitors 18 Vias to decoupling capacitors should have sufficient To decrease series inductance diameter 19 Avoid routing high speed LAN or phone line traces To minimize crosstalk near other high frequency signals associated with a video controller cache controller CPU or similar devices 135 Inte 820E Chipset 136 Table 47 AC 97 Table 48 I intel ICH2 200 mils
223. ne involve three types intragroup AGTL intergroup AGTL and AGTL to non 147 Inte 820E Chipset intel AGTL Intragroup AGTL crosstalk involves interference between AGTL signals within the same group See Section 3 4 for a description of the different AGTL group types Intergroup AGTL crosstalk involves t erference of AGTL signals in a particular group with AGTL signals in different group An example of AGTL to non AGTL crosstalk is when CMOS and AGTL signals interfere with each other Table 54 Trace Width Space Guidelines 3 2 4 3 3 2 4 4 148 Crosstalk Type Trace Width Space Ratio Intragroup AGTL same group AGTL 5 10 or 6 12 Intergroup AGTL different group AGTL 5 15 or 6 18 AGTL to non AGTL 5 20 or 6 24 The spacing between the various bus agents causes variations in trunk impedance and stub locations These variations cause reflections that can cause constructive or destructive interference at the receivers Noise may be reduced by providing minimal spacing the agents Unfortunately tighter spacing results in reduced component placement options and lower hold margins Therefore adjusting the inter agent spacing may be one way to change the network s noise margin but mechanical constraints often limit the usefulness of this technique Always be sure to validate signal quality after making any changes in agent locations or changes to inter agent spacing Six AGTL signals can be driven si
224. near high speed signals RSL routing signals must length matched within 10 mils of the nominal RSL length Note Use the table in the Intel 820 Chipset Family 82820 Memory Controller Hub MCH Datasheet to verify the trace lengths Ensure that signals with a dummy via are compensated correctly ALL RSL signals must have one via near the MCH BGA pad Signals routed on the secondary side of the MB will have a real via while signals routed on the primary side will have dummy via Additionally all signals with a dummy via must have an additional trace length of 25 mils B side RIMM connector signals are routed on the secondary side of the motherboard A side RIMM connector signals are routed on the primary side of the motherboard Signals must alternate layers as shown in the following table If Signal Routed from MCH Then Route Signal from 1st RIMM to 1st RIMM on to Next RIMM on Clock routing Clock signals must be routed as a differential pair The traces must be 14 mils wide and 6 mils apart with no ground isolation when they are routed as a differential pair For very short sections under the MCH and under the first RIMM it will not be possible to route as a differential pair In these sections the clocks signals must neck up to 18 mils and be ground isolated with at least 10 mils ground isolation Clock signals must be length compensated using the 1 021 length factor mentioned in Section 4 T
225. necessary to use tighter spacings when routing between component pins Avoid parallelism between signals on adjacent layers Since AGTL is a low signal swing technology it is important to isolate AGTL signals from other signals by at least 0 025 inch This will avoid coupling from signals with larger voltage swings such as 5 V PCI Select a board stack up that minimizes the coupling between adjacent signals Route AGTL address data and control signals in separate groups to minimize crosstalk between groups The Pentium processor in the FC PGA package uses a split transaction bus In a given clock cycle the address lines and corresponding control lines could be driven by a different agent than the data lines and their corresponding control lines Design Guide intel 2 12 Design Guide InteP 820E Chipset Additional Considerations Distribute with a wide trace 0 050 inch minimum trace is recommended to minimize DC losses Route the trace to all components on the host bus Be sure to include decoupling capacitors Guidelines for distribution and decoupling are contained in the Intel 820 Chipset Design Guide Addendum for the Intel Pentium III Processor for the PGA370 Socket PVrer should be generated with one voltage divider between the and the processor for all pins Be sure to include decoupling capacitors Guidelines for distribution and decoupling are cont
226. nected directly to island 100 uF tantalum capacitors must have at least 2 vias cap to ground island should be 50 75 mils wide island should not be broken 57 Inte 820E Chipset 58 intel If any RSL signals are routed even for a short distance out of the last RIMM towards termination on the bottom side ensure that the ground reference plane on the third layer is continuous under the termination resistors capacitors Ensure that the current path for power delivery to the MCH does not go through the Island routed properly are routed differentially from DRCG to last RIMM are ground isolated from DRCG to last RIMM are ground referenced from DRCG to last RIMM Vias are placed in ground isolation and ground reference every 0 5 inch When serpentine together they MUST maintain exactly 6 mils of spacing Clean DRCG power supply 3 3 V DRCG power flood on the top layer should connect to each high frequency 0 1 uF capacitor to the 10 uF bulk tantalum capacitor and to the ferrite bead High frequency 0 1 capacitors are near the DRCG power pins with one capacitor next to each power pin 10 bulk tantalum capacitor near DRCG connected directly to the 3 3 V DRCG power flood on the top layer The ferrite bead isolating the DRCG power flood from the 3 3 V main power also connects d
227. ng is used to minimize the effect of propagation delay Tprop on maximum bus frequency A source synchronous strobed interface uses strobe signals instead of the clock to indicate that data is valid Refer to the following example figure Figure 10 Data Strobing Example data str For a source synchronous strobed interface it is very important that the strobe signals be routed carefully These signals must be very clean i e free of noise Data signals typically are latched on the rising or falling edge of the strobe signal or both If there is noise on these signals it could cause an extra edge to be detected thus latching incorrect data Refer to the following example figures Figure 11 Effect of Crosstalk on Strobe Signal 32 a Correct Strobing Example no noise b Effect of Cross Talk on Strobe Signal Data incorrectly Data correctly latched as 1 latched as 0 Clock data i e crosstalk Threshold Threshold 1 Strobe Strobe strobing example Some buses have more than one strobe 1 The 1 0 specification 1x and 2x modes employs three strobe signals each of which is used to strobe different data signals 1 each strobe has an associated set of data signals The associations for AGP 1 0 AGP 2x are listed in the following table Refer to Section bs for more information on AGP 2 0 AGP 4x 1 5 V Design Guide
228. no 89 17 ABS HIN YOLVINDAY 959 209A HII ASSS 209A ei uay pue sdeo jndjno 01 9HA C161 1UF X7R C159 2904 1 74 89 17 SYA YOLVINDAY 39v L10A 299 ve 13Q3dAL 1171706519 1171706518 3ni000 AASL 8919 NWN W 1 1H OQGAN 24 3901 919 NMOGLNHS HA OQQA ASES 5 A 29 OOA cery 7 8 117706518 ES 1159 HNIS ON m et YOLVINDAY ADVLIOA OQGA 9 d 1Vn3929 lt BAAN 1UF X7R C268 rav 8411 8HA YOLVINDAY 871 1UF X7R C104 3 7589111 vYA ADVLIOA 81 LLA LGA e 99N ASSSOOA 5 5 A8S l pue jndui AG Sey 00 17 5 A8SS09 Sjueuno 10 Jou 81 144 ay jo uospd juejsuoo JOU an ayy seue d amod jo
229. ns Power and ground connection rules include the following For optimal performance place decoupling capacitors on the backside of the PCB directly under the Intel 82562 component with equal distance from both pins of the capacitor to power ground The analog power supply pins for the Intel 82562 VssA should be isolated from the digital and Vss through the use of ferrite beads In addition adequate filtering and decoupling capacitors should be provided between and Vss as well as and Vss4 power supplies Guidelines for Intel 82562EH Component Placement Component placement can affect the signal quality emissions and temperature of a board design This section discusses guidelines for component placement Careful component placement provides the following benefits Decreases potential problems directly related to electromagnetic interference EMI which could result in failure to meet FCC specifications e Simplifies the task of routing traces To some extent component orientation affects the trace routing complexity The overall objective is to minimize turns and crossovers between traces It is important to minimize the space needed for the HomePNA LAN interface because all other interfaces will compete for physical space on a motherboard near the connector edge As with most subsystems the HomePNA LAN circuits must be as close as possible to the connector Thus all designs must be opt
230. o when a 3 3 V add in card is placed in the system the regulator must use a low Rps ox FET 1 0 modified 3 3 to 3 1 V When power supply is used the 3 3 is 3 168 V Therefore 68 mV of drop is allowed across the FET at 2 A This corresponds to an FET with an Rps on of 34 mW How does the regulator switch The feedback resistor divider is set to 1 5 V When a 1 5 V card is placed in the system the transistor 15 off and the regulator regulates to 1 5 V When a 3 3 V card 15 placed in the system the transistor is on and the feedback 1 pulled to ground When this happens the regulator drives the gate of the FET to nearly 12 V This turns on the FET and passes 33V 2Ax Rps oN to 67 Inte 820E Chipset 2 8 8 68 Figure 38 Vppa Generation Example Circuit 3 3V vios 12V c2 panas 47 uF Ul 111575 1 5 SHDN IPOS H 50 5 rs c3 ra 2 VIN INEG N R1 GND 7 4 1 ra 5 1yF ali 10 pF 4 C5 R5 7 47 pF 7 5 R3 3010 TYPEDET R4 1 21 agp vddq generation vs id Vrer Generation for 2 0 2x and 4 Varr generation for AGP 2 0 will differ depending on the AGP card type used The 3 3 AGP cards generate locally i e
231. ock skew and clock jitter were used Clock skew and clock jitter values depend on the clock components and distribution method chosen for a particular design and must be budgeted into the initial timing equations as appropriate for each design Intel highly recommends adding margin as shown in the Map column to offset the degradation caused by SSO push out and other multi bit switching effects The Recommended column contains the recommended maximum flight time after incorporating the Map value If the edge rate ringback and monotonicity requirements are not met flight time correction must first be performed as documented in the Intel Pentium II Processor Developer s Manual with the additional requirements noted in Section The commonly used textbook equations used to calculate the expected signal propagation rate of a board are included in Section Simulation and control of baseboard design parameters can ensure that the signal quality and maximum and minimum flight times are met Baseboard propagation speed is highly dependent on the transmission line geometry configuration stripline vs microstrip dielectric constant and loading This layout guideline includes high speed baseboard design practices that may improve the amount of timing and signal quality margin The magnitude of Mapyis highly dependent on the baseboard design implementation stack up decoupling layout routing reference planes etc and must be charact
232. ogi VOQU og v ivodu S88 008 svom WH3l 0 vodi va evod Weal 11097018 1nos ois 1 eH tog ZvOG Weal vod zvod zyoqi odi TEREE NOI 66 lt 0700 0091 gt lo slvoa1 z 4 e gt 4 88001 vg sog 48041 8001 S8907 98007 8001 E 88007 19001 98007 98007 59047 8 lt 2808 WHIL Ev 9900 WHAL 800 WH3L 580 WHAL 28007 81 83 85 87 89 811 813 815 817 829 821 823 825 827 819 831 833 839 GND B52 B60 B62 B64 B66 B68 B70 B72 B74 B76 B78 B80 B82 B84 B86 B88 B90 B92 43 44 45 46 47 48 49 50 843 844 845 846 847 848 849 850 RSV_SRIMM Lev eL v Z2V SeV eev Lov 62V LL V SL V eL V LLV 6v 6 88 28 8128628 186 86 8 118 68 28 08 8 8 cev 06v eev ogv vev cav OBv g V O V OZ V G9v 99 cO V 4 268 068 888 988 288 088 828 928 728 228 028 898 998 798 2981 o lt 0Sg 6rg erg Zvg org Srg rvd crg Osv 6rv evv OPW Cv V o elaoa 1 8 SWWNIH SY 5195205
233. om 5 using a voltage regulator On the Intel 820E chipset reference board 3 3 1s derived from 5V DUAL Dual power rail A dual power rail is derived from different rails at different times depending on the power state of the system Usually a dual power rail is derived from a standby supply during the suspend operation and is derived from a core supply during full power operation Note that the voltage on a dual power rail may be misleading 183 Inte 820E Chipset 6 1 2 184 Board intel Power Delivery of Intel 820E Chipset Customer Reference Figure 101 shows the power delivery architecture for the Intel 820E Chipset Reference Board This power delivery architecture supports the Instantly Available PC Design Guidelines via the Suspend to RAM STR state During STR only the necessary devices are powered These devices include main memory the ICH2 resume well PCI wake devices via 3 3 Vayx and USB USB can be powered only if sufficient standby power is available To ensure that enough power is available during STR a thorough power budget must be completed The power requirements must include each device s power requirements both in the suspend and full power states The power requirements must be compared with the power budget available from the power supply Due to the requirements of main memory and PCI 3 3 Vaux and possibly other devices in the system it is necessary to create a du
234. onent placement can affect the signal quality emissions and temperature of a board design This section provides guidelines for component placement Careful component placement has the following benefits Decreases potential problems directly related to electromagnetic interference EMI which could result in failure to meet FCC and IEEE test specifications e Simplifies the task of routing traces To some extent component orientation affects the trace routing complexity The overall objective is to minimize turns and crossovers between traces It is important to minimize the space needed for the Ethernet LAN interface because all other interfaces will compete for physical space on a motherboard near the connector edge As with most subsystems the Ethernet LAN circuits must be as close as possible to the connector Thus all designs must be optimized to fit in a very small space 115 Inte 820E Chipset 2 22 4 2 2 22 4 3 intel Crystals and Oscillators To minimize the effects of EMI clock sources should not be placed near I O ports or board edges Radiation from these devices may be coupled onto the I O ports or out of the system chassis Crystals also should be kept away from the Ethernet magnetics module to prevent communication interference The crystal s retaining straps if they exist should be grounded to prevent possible radiation from the crystal case and the crystal should lie flat against the PC board to provid
235. onsiderations Intel 82562EH B ntel 82562EH Home PNA Guidelines Intel 82562ET 82562EM C ntel amp 82562ET Intel 82562EM Component Dual footprint layout D ntel 82562ET and Intel 82562EH Components Dual Footprint Guidelines ICH2 LAN Interconnect Guidelines This section contains guidelines for the design of motherboards and riser cards that comply with LAN connect The guidelines should not be treated as a specification and the system designer must ensure via simulations or other techniques that the system meets the specified timings Special care must be taken when matching the LAN traces to those of the other signals as discussed next The following guidelines for the ICH2 to LAN component interface The following signal lines are used on this interface LAN CLK LAN RSTSYNC LAN RXD 2 0 and LAN TXD 2 0 This interface supports both Intel 82562 and Intel 82562 82562 components Signal lines LAN LAN RSTSYNC LAN RXD 0 and LAN 0 are shared by both components Signal lines RXD 2 1 and LAN TXD 2 1 not connected when the Intel 82562 component is installed The AC characteristics of this interface are discussed in the Intel 82801BA I O Controller ICH2 Datasheet Dual footprint guidelines are found in Section 103 Inte 820E Chipset 2 22 1 1 2 22 1 2 Bus Topologies The LAN Connect Interface can be configured in several to
236. ontroller s requirements The graphics controller may only power I O buffers with the power pins The TYPEDET signal indicates whether the 2 0 interface operates at 1 5 V or 3 3 V If is floating i e no connect on an AGP add in card the interface is 3 3 V If TYPEDET is shorted to ground the interface is 1 5 V Table 12 TYPDET Vppq Relationship Design Guide TYPEDET on Add in Card Vppo Supplied by GND 1 5V N C 3 3 V As a result of this requirement the motherboard must provide a flexible voltage regulator This regulator must supply the appropriate voltage to the Vppo pins on the AGP connector For specific design recommendations refer to the schematics in generation and generation must be considered together Before developing Vppo generation circuitry refer to the AGP 2 0 Interface Specification Figure 38 klemonstrates one way to design the Vppo voltage regulator This regulator is a linear regulator with an external low Rps on FET The source of the FET is connected to 3 3 V This regulator will convert 3 3 V to 1 5 V or pass 3 3 V depending on the state of TYPEDET If a linear regulator is used it must draw power from 3 3 V not 5 V to control thermals 1 e 5 V regulated down to 1 5 V with a linear regulator will dissipate approximately 7 W at 2 A Because it must draw power from 3 3 V and in some situations must simply pass that 3 3 V t
237. or the ICH2 8 Hub Interface Decoupling Guidelines To improve power delivery use two 0 1 uF capacitors per component i e the 2 and These capacitors should be placed within 150 mils of each package adjacent to the rows that contain the hub interface If the layout allows wide metal fingers running on the Vss side of the board should connect the 8 side of the capacitors to the VCC1_8 power pins Similarly if the layout allows metal fingers running on the VCCI 8 side of the board should connect the ground side of the capacitors to the power pins System Bus Design Pentium Processor for the Intel PGA370 Socket Layout Guidelines The Pentium III processor in the FC PGA package is the next member of the P6 family in the Intel IA 32 processor line The processor uses the same core and offers the same performance as the Pentium III processor in the S E C C 2 package but utilizes a new package technology called Flip Chip Pin Grid Array or FC PGA This package utilizes the same 370 pin zero insertion force socket Intel PGA370 used by the Intel Celeron processor Thermal solutions are attached directly to the back of the processor core package without the use of a thermal plate or heat spreader The Intel PGA370 design requires additional termination at the chipset for the AGTL signals In addition the platform power delivery requirements are different for the Intel PGA370 design compared
238. ort as possible 134 Design Guide intel Table 46 LAN Connect I F Design Guide InteP 820E Chipset Layout Recommendations Yes No Comments 1 Stack up 5 mils wide 10 mil spacing 2 Zo 60 1596 Signal integrity requirement 3 LAN max trace length ICH2 to CNR To meet timing requirements L 3 inches to 9 inches 0 5 inch to inches on card 4 Stubs due to R pak CNR LOM stuffing option To minimize inductance should not be present 5 Max trace lengths ICH2 to 82562EH ET EM To meet timing requirements L 4 5 inches to 8 5 inches 6 Max mismatch between length of a clock trace and To meet timing and signal quality length of any data trace is 0 5 inch requirements 7 Maintain constant symmetry and spacing between To meet timing and signal quality the traces within a differential pair requirements 8 Keep the total length of each differential pair less Issues found with traces longer than 4 inches than 4 inches IEEE phy conformance failures excessive EMI and or degraded receive BER 9 Do not route the transmit differential traces within To minimize crosstalk 70 mils of the receive differential traces 10 Distance between differential traces and any other To minimize crosstalk signal line is 70 mils 11 Keep max separation between differential pairs at To meet timing and signal quality 7 mils requirements 12 Differential trace impeda
239. ounding requires the minimization of inductance levels in the interconnections EMI radiation can be reduced significantly by keeping ground returns short signal loop areas small and power inputs bypassed to signal return Rules that help reduce backplane and motherboard circuit inductance include the following Design Guide Route traces over a continuous plane with no interruptions 1 e don t route over a split plane If there is a vacant area on a ground or power plane avoid routing signals over it This would increase inductance and EMI radiation levels To reduce coupling separate noisy digital grounds from analog grounds Noisy digital grounds may affect sensitive DC subsystems ground vias should be connected to every ground plane and every power via should be connected to all power planes at equal potential This helps reduce circuit inductance Physically locate grounds between a signal path and its return This minimizes the loop area Avoid fast rise fall times whenever possible Signals with fast rise and fall times contain many high frequency harmonics which can radiate EMI The ground plane beneath the filter transformer module should be split The RJ45 and or connector side of the transformer module should have a chassis ground beneath it Splitting the ground planes beneath the transformer minimizes noise coupling between the primary and secondary sides of the transformer and between the adjacent coils in
240. performance By increasing memory bandwidth to 1 6 GB s by means of 400 MHz Direct RDRAM and by increasing the graphics bandwidth to 1 GB s by means of AGP 4x the Intel 820E chipset delivers the data throughput necessary to take advantage of the high performance provided by the powerful Pentium lll processors In addition the Intel 820E chipset architecture enables security and manageability infrastructures through the Firmware Hub FWH component The ACPI compliant Intel 820E chipset platform can support the Full On Stop Grant Suspend to RAM Suspend to Disk and Soft Off power management states Through the use of the integrated LAN functions the Intel 820E chipset also supports Wake on LAN for remote administration and troubleshooting The Intel 820E chipset architecture eliminates the need for the ISA expansion bus traditionally integrated into the I O subsystem of Intel chipsets This eliminates many conflicts experienced when installing hardware and drivers into legacy ISA systems The elimination of ISA provides true plug and play for the Intel 820E chipset platform Traditionally the ISA interface was used for audio and modem devices The addition of AC 97 allows the OEM to use software configurable AC 97 audio and modem encoders decoders codecs instead of traditional ISA devices The 82801BA ICH2 component expands the support of AC 97 to include up to 6 channel audio The ISA bus can be implemented with a PCI to ISA bridge from a
241. pologies as follows Direct point to point connection between the ICH2 and the LAN component Dual footprint see Section 22 6 LOM CNR implementation Point to Point Interconnect The following are guidelines for a single solution motherboard Either the Intel 82562 component Intel 82562ET component or CNR is installed Figure 65 Single Solution Interconnect 2 22 1 3 104 LAN CLK RSTSYNC Platform LAN ICH2 LAN RXD 2 0 Connect ps IO subsys single sol interconn Length requirements for Figure 65 Intel 82562EH L 4 5 inches to 10 0 inches Signal lines LAN RXD 2 1 and LAN TXDJ 2 1 not connected Intel 82562ET L 3 5 inches to 10 0 inches 3 0 inches to 9 0 inches 0 5 inch to 3 0 inches on card LOM CNR Interconnect The following guidelines enable an all inclusive motherboard solution This layout combines the LOM dual footprint and CNR solutions The resistor pack ensures that either a CNR option or a LAN on motherboard option can be implemented at one time The following figures show a model of this The recommended trace routing lengths are shown in Table 23 Design Guide intel InteP 820E Chipset Figure 66 LOM CNR Interconnect PLC card IO subsys LOM CNR intercomm Table 23 Length Requirements for Figure 66 2 22 1 4 Design Guide Configuration A B D Intel 82562EH 0 5 to 6 4 to 1
242. power dissipation is not exceeded for the Rpack 173 Inte 820E Chipset intel 4 7 Unused Outputs All unused clock outputs must be tied to ground through a series resistor that has approximately the impedance of the output buffer shown in the following table These resistors are designed to terminate unused outputs to eliminate EMI Table 60 Unused Output Termination Buffer Name Vcc Range Impedance If Unused Output V 0 Termination to Vss Q CPU CPU Div2 IOAPIC 2 375 2 625 13 5 45 30 48 MHz REF 3 135 3 465 20 60 40 PCI 3V66 3 135 3 465 12 55 33 4 8 Decoupling Recommendation for CK133 DRCG Some CK133 vendors may integrate the XTAL IN and XTAL OUT frequency adjust capacitors However pads should be placed on the board for these external capacitors for testing debug To further reduce jitter and voltage supply noise it is advisable to add a ferrite filter with 2 caps 10 pF and 0 1 uF on both the 2 5 V and 3 3 V planes close to the clock devices This applies to both DRCG and CK 133 174 Design Guide intel 4 9 4 9 1 Design Guide InteP 820E Chipset DRCG Frequency Selection and the DRCG DRCG Frequency Selection Table and Jitter Specification To provide additional flexibility in board design Intel has enabled a variation of the DRCG called the DRCG The device has the same specifications pinout and form factor mentioned in the document for the existing DR
243. r Planes 5VSB 5V 3 3V 12V Intel 820E Chipset also connects to the AGP connector 2A is the TOTAL VDDQ current requirement Refer to the Pentium processor datasheet for power requirement considerations for PGA370 designs The Pentium processor datasheet can be found at http developer intel com design Pentiumlll datashts Shaded regulators components are on in S3 S5 Note RDRAM core and VCC CMOS must be OFF in S5 Power Planes 5V Dual VCCVID VTT 2 5VSBY 1 8V VDDQ 3 3VSB 2 5V 1 8VSB Delivery Design Guide Note Note Note Design Guide InteP 820E Chipset This design guide provides only examples Many power distribution methods achieve similar results When deviating from these examples in any way it is critical to consider the effects of the change In addition to the power planes provided by the power supply an instantly available Intel 820 chipset based system using Suspend to RAM requires that seven power planes be generated on the board The requirements for each power plane are documented in this section In addition to on board voltage regulators the Intel 820E chipset reference board has a 5 V dual switch 5 V Dual Switch This switch powers the 5 V dual plane from the 5 V core ATX supply during full power operation During Suspend to RAM the 5 V dual plane will be powered from the 5 V standby power supply Note The voltage on the 5 V dual pl
244. r frequencies and will degrade the transmit BER performance Caution is required if a cap is put in either of these locations If a cap is used it almost certainly should have a capacitance below 22 pF 6 pF to 12 pF values have been used in past designs with reasonably good success Unless there is some overshoot in the 100 Mbps mode these caps are unnecessary Note It is important to keep the two traces within a differential pair close to each other which increases their immunity to crosstalk and other sources of common mode noise Keeping them close means lower emissions 1 FCC compliance from the transmit traces as well as an improved receive BER for the receive traces Close should be considered to be less than 0 030 inches between the two traces within a differential pair 0 007 inches trace to trace spacing is recommended Design Guide 111 Inte 820E Chipset 2 22 3 Intel 82562EH Home PNA Guidelines Table 24 Related Documents 2 22 3 1 2 22 3 2 2 22 3 3 112 Title Doc Intel 82562EH HomePNA 1 Mbit s Physical Layer Interface Product OR 2183 Preview Datasheet 5 82562 1 Mbit s Home PNA LAN Connect Option Application OR 2182 Note For correct LAN performance designers must follow the general guidelines outlined in Section Additional guidelines for implementing an Intel 82562 Home PNA LAN connect component are provided in the following sections Power and Ground Connectio
245. r layout increases flexibility by offering stuffing options at a later date The IDE interface can be routed with 5 mil traces on 7 mil spaces and must be less than 8 inches long from ICH2 to IDE connector Additionally the shortest IDE signal on a given IDE channel must be less than 0 5 inch shorter than the longest IDE signal on that channel Cable e Length of cable Each IDE cable must be lt 18 inches e Capacitance Less than 30 pF Placement A maximum of 6 inches between drive connectors on the cable If a single drive is placed on the cable it should be placed at the end of the cable If a second drive is placed on the same cable it should be placed on the connector next closest to the end of the cable 6 inches away from the end of the cable Grounding Provide a direct low impedance chassis path between the motherboard ground and the hard disk drives ICH2 placement The ICH2 must be placed lt 8 inches from the ATA connector s 79 Inte 820E Chipset 2 12 1 2 12 2 80 intel Cable Detection for Ultra 66 and Ultra 100 The ICH2 IDE controller supports PIO multiword 8237 style DMA and Ultra DMA modes 0 through 5 The ICH2 must determine the type of cable present to configure itself for the fastest possible transfer mode that the hardware can support An 80 conductor IDE cable is required for Ultra ATA 66 and Ultra 100 This cable uses the same 40 pin connector as the old
246. rails but in most platforms the VccSus3 3 rail is derived from the 5 and therefore the VccSus3 3 rail will always come up after the VccSus5 rail As a result VSREF Sus will always be powered up before VccSus3 3 In platforms that do not derive the VecSus3 3 rail from the VccSus5 rail this rule must be comprehended in the platform design As an additional consideration during suspend the only signals that are 5V tolerant are USBOC If these signals are not needed during suspend 5 Sus can be hooked to the VccSus3 3 rail 189 Inte 820E Chipset Figure 104 Example 3 3V 5V REF Sequencing Circuitry VCC Supply 3 3 V 5 V Supply 1 UF 1 9 System VREF To System 6 1 5 Excessive Power Consumption by 64 72 Mbit RDRAM 6 1 5 1 Note 190 Some 64 72 Mbit RDRAM devices interpret non broadcast device directed commands as broadcast commands These commands are the SET FAST CLOCK SET RESET and CLEAR RESET commands RDRAM devices consume more current during these initialization steps than during normal operation If these devices accept device directed commands as broadcast commands the device cannot be reset initialized serially All devices must be reset initialize simultaneously This will result in excessive current draw during the initialization of memory The amount of excessive current will depend on the number of devices and the frequency used The worst case current draw 15 7 5 A in a sys
247. re total layers in the PCB than other methods Copper with a thickness of 1 ounce ft is recommended for all power and reference planes A second method of power distribution is to use partial planes in the immediate area needing power and to place these planes on a routing layer on an as needed basis These planes still must be decoupled to ground to ensure stable voltages for the components being supplied This method has the disadvantage of reducing the area that can be used to route traces These partial planes also may change the impedance of adjacent trace layers For instance the impedances may have been calculated for microstrip geometry and adding a partial plane on the other side of the trace layer may turn the microstrip into a stripline 156 Design Guide InteP 820 Chipset Reference Planes and PCB Stack Up It is strongly recommended that baseboard stack up be arranged such that AGTL signals referenced to a ground Vss plane and that AGTL signals do not traverse multiple signal layers Deviating from either guideline can create discontinuities in the signal s return path that can lead to large SSO effects that degrade the timing and noise margin Designing an AGTL platform incorporating discontinuities will subject the platform to a risk that is highly unpredictable in pre layout simulation The following figure shows the ideal case where a particular signal is routed entirely within the same signal layer with
248. reasing separation it is rarely necessary to consider aggressors at least five line widths away from the victim The maximum crosstalk occurs when all aggressors are switching in the same direction at the same time The crosstalk that occurs internally in the IC packages also can affect the signal quality Backward crosstalk is present in both stripline and microstrip geometry s see Figure 78 Stripline geometry differs from microstrip geometry in that the former requires stripping a layer away to see the signal lines The backward coupled amplitude is proportional to the backward crosstalk coefficient the aggressor s signal amplitude and the coupled length of the network up to a maximum that depends on the rise fall time of the aggressor s signal Backward crosstalk reaches a maximum and remains constant when the propagation time on the coupled network length exceeds one half of the rise time of the aggressor s signal Assuming the ideal ramp on the aggressor to be from 0 to 100 voltage swing and the fall time on an unloaded coupled network then Length for max backward crosstalk x fall time Board delay per unit length The following example calculation results when the fast corner fall time is 3 V ns and the board delay is 175 ps inch 2 1 ns foot Fall time 1 5 V 3 V ns 0 5 ns Length for max backward crosstalk V5 0 5 ns x 1000 ps ns 175 ps in 1 43 inches Agents on the AGTL bus drive signals in each d
249. rolled as tightly as possible with sampling of the allowable Z0 and SO simulated The Intel PGA370 socketed Pentium lll processor s nominal effective line impedance 15 60 15 Intel recommends a baseboard nominal effective line impedance of 60 15 the recommended layout guidelines to be effective Intel also recommends both running uncoupled simulations using the Zo of the package stubs as well as performing fully coupled simulations if increased accuracy is needed or desired Accounting for crosstalk within the device package by varying the stub impedance was investigated and was not found to be sufficiently accurate This led to the development of full package models for the component packages Place and Route Board Estimate Component to Component Spacing for AGTL Signals Estimate the number of layers that will be required Then determine the expected interconnect distances between each component on the AGTL bus Using the estimated interconnect distances verify that the placement can support the system timing requirements The required bus frequency and the maximum flight time propagation delay on the PCB determine the maximum network length between the bus agents The minimum network length is independent of the required bus frequency Table 52 and Table 53 assume values for CLKSKEW and CLKJITTER parameters that are controlled by the system designer To minimize the system clock skew Intel recommends clock buff
250. rom the to the first RIMM All signals must match exactly from RIMM to Inte 820E Chipset intel 2 7 3 Direct RDRAM Reference Voltage The Direct RDRAM reference voltage RAMREF must be generated as shown in The RAMREF should be generated from a typical resistor divider using 2 tolerance resistors Additionally the RAMREF must be decoupled locally at each RIMM connector at the resistor divider and at the Finally as shown in Figure 32 100 series resistor 15 required near the The RAMREF signal should be routed with a 10 mil wide trace Figure 32 RAMREF Generation Example Circuit V TERM MCH R1 160 02 RAMREFA RAMREFB ramref generation vsd 2 7 4 High Speed CMOS Routing e The high speed CMOS signals CMD amp SCK must be routed using 28 traces Using the recommended stack up these signals will be 18 mils wide The high speed CMOS signals must be length matched to the RSL signals within 1200 mils 1 2 inches because of a timing requirement between CMOS and RSL signals during NAP Exit and PDN Exit The high speed CMOS signals require termination as shown in as a result of the buffer strengths in the MCH The resistors must be 91 pull up and 39 Q pull down and they must be 2 or better for S3 mode reliability The trace impedances remain 28 54 Design Guide intel InteP 820E Chipset Figure 33 High Speed CMOS Termination 2 7 4 1
251. rst case noise margin Therefore Intel recommends simulating the networks from all driver locations and analyzing each receiver for each possible driver Analysis has shown that both fast and slow corner conditions must be run for both rising edge and falling edge transitions The fast corner is needed because the fast edge rate creates the most noise The slow corner is needed because the buffer s drive capability will be minimum causing the Vo to shift up which may cause the noise from the slower edge to exceed the available budget Slow corner models may produce minimum flight time violations on rising edges if the transition starts from a higher So Intel highly recommends checking for minimum and maximum flight time violations with both the fast and slow corner models The fast and slow corner I O buffer models are contained in the processor and Intel 820 chipset electronic models provided by Intel Design Guide 3 2 4 3 2 4 1 3 2 4 2 Design Guide InteP 820E Chipset The transmission line package models must be inserted between the output of the buffer and the net it is driving Likewise the package model must also be placed between a net and the input of a receiver model This is performed generally by editing the simulator s net description or topology file Intel has found wide variation in noise margins when varying the stub impedance and the PCB s 20 and S0 Intel therefore recommends that PCB parameters be cont
252. rved when multiple bits are switching simultaneously These multi bit effects can adversely affect flight time and signal quality and are sometimes not accounted for in simulation Accordingly maximum flight times depend on the baseboard design and additional adjustment factors or margins are recommended a SSO push out or pull in b Rising edge or falling edge rate degradation at the receiver caused by inductance in the current return path requiring extrapolation that causes additional delay c Crosstalk on the PCB and internal to the package can cause variation in the signals Additional effects may not necessarily be covered by the multi bit adjustment factor and should be budgeted as appropriate to the baseboard design Examples include a Effective board propagation constant SEFF which is a function of Dielectric constant of the PCB material Type of trace connecting the components stripline or microstrip Length of the trace and load of components on trace Note that the board propagation constant multiplied by the trace length is a component of the flight time but not necessarily equal to the flight time Processor values specified in this table are examples only Refer to the appropriate processor datasheet for the specification values Design Guide intel Table 53 3 2 2 3 2 3 3 2 3 1 3 2 3 2 Design Guide InteP 820E Chipset Example Calculations Frequency In
253. same trace connects two components component A and component B the minimum and maximum flight time requirements for component A driving component B as well as component B driving component A must be met The cases to be considered are Processor driving processor Processor driving chipset Chipset driving processor 142 Design Guide intel Table 51 Design Guide InteP 820E Chipset A designer using components other than those listed previously must evaluate additional combinations of driver and receiver AGTL Parameters for Example Calculations Pentium Ill Processor Core at 133 MHz Bus NOTES 1 All times in nanoseconds 2 Numbers in table are for reference only These timing parameters are subject to change Please check the appropriate component documentation for the valid timing parameter values 3 Tsu_min 1 9 ns assumes the Intel 82820 sees a minimum edge rate equal to 0 3 V ns 4 The Pentium processor substrate s nominal impedance is set to 65 15 Future Pentium processor substrates may be set at 60 0 15 able 51 lists the AGTL component timings of the processors and Intel 82820 defined at the pins These timings are for reference only able 52 gives an example AGTL initial maximum flight time and Table 53 contains an example minimum flight time calculation for a 133 MHz 2 way Pentium III processor Intel 820E chipset system bus Note that assumed values for cl
254. same values are valid assumptions Each processor s datasheet specifies the clock signal quality requirements To help meet these specifications comply with the following general guidelines e Tie the clock driver outputs if the clock buffer supports this mode of operation Match the electrical length and type of traces on the PCB Microstrip and stripline may have different propagation velocities Maintain consistent impedance for the clock traces Minimize the number of vias in each trace Minimize the number of different trace layers used to route the clocks Keep other traces away from clock traces Lump the loads at the end of the trace 1f multiple components are to be supported by a single clock output Have equal loads at the end of each network The ideal way to route each clock trace is on the same single inner layer next to a ground plane isolated from other traces with the same total trace length to the same type of single load with an equal length ground trace parallel to it and driven by a zero skew clock driver When deviations from the 1deal are required a good compromise is to go from a single layer to a pair of layers adjacent to power ground planes The fewer number of layers on which the clocks are routed the smaller the impedance difference between each trace is likely to be Maintaining an equal length and parallel ground trace for the total length of each clock ensures a low inductance groun
255. scription Maximum Trace Length in MCH to first RIMM connector 0 to 3 50 RIMM to RIMM 0 4 to 0 45 35 Inte 820E Chipset intel The following figure shows a top view of the trace width spacing requirements for the RSL signals Figure 14 RSL Routing Diagram 18 mils 6 mils 10 mils 6 mils 18 mils 6 mils 10 mils 6 mils lt gt RSL Signal Trace RSL Signal Trace route dia The following two figures show the top view of an example RSL breakout and route Figure 15 Primary Side RSL Breakout Example 36 Design Guide InteP 820 Chipset intel Figure 16 Secondary Side RSL Breakout Example Design Guide 37 Inte 820 Chipset intel 2 7 2 2 RSL Termination RSL signals must be terminated to 1 8 V using 27 1 or 28 2 resistors at the end of the channel opposite the MCH Resistor packs are acceptable must be decoupled using high speed bypass capacitors one 0 1 uF ceramic chip capacitor per two RSL lines near the terminating resistors Additionally bulk capacitance is required Assuming a linear regulator with an approximately 20 ms response time two 100 uF tantalum capacitors are recommended The trace length between the last RIMM and the termination resistors should be less than 3 inches Length matching in this section of the channel 18 not require
256. sland Via to ground every 0 5 inch between RIMMs Via to ground every 0 5 inch between signals from MCH to first RIMM Via between every signal within 100 mils of the MCH edge and the connector edge No unconnected ground floods ground isolation at least 10 mils wide Ground isolation fills between serpentines Ground isolation not broken by C TABs Ground isolation connects to the ground pins in the middle of the RIMM connectors Ground isolation vias connect on all 4 layers and should not have thermal reliefs Ground pins in RIMM connector connect on all 4 layers layout yields low noise Solid island 18 top layer Do not split this plane Ground island for ground side of caps is on top Termination resistors connect directly to the island on the top layer without vias Decoupling is critical Decoupling capacitors connect directly to top layer island and top layer ground island See the layout example Use at least 2 vias per decoupling capacitor in the top layer ground island Use 2 x 100 uF tantalum capacitors to decouple Aluminunyelectrolytic capacitors are too slow High frequency decoupling capacitors must be spread out across the termination island so that all termination resistors are near high frequency capacitors 100 uF tantalum capacitors should be at each end of the island 100 uF tantalum capacitors must be con
257. stack up is recommended for Intel 820E chipset platform design e Fab construction 4 layers e Z 60 2 10 Figure 100 4 5 mil Stack Up Component side layer 0 5 oz Cu 4 5 mil prepreg Ground layer 2 1 oz 1 3 Q o NAN ASS Total thickness 62 mils DW NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI SNNNNNNNN NNNNNNNNI NNNNNNNN NNNNNNNN NNNNNNNN NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NNNNNNNNI NAN ASS E o 3 a 3 102 4 5 mil prepreg Solder side layer 4 0 5 oz Cu 4 5 stackup vsd Design Guide 181 Inte 820 Chipset This page intentionally left blank 182 Design Guide Design Guide InteP 820E Chipset System Design Considerations Power Delivery Terminology and Definitions Term Definition Suspend to In the STR state the system state is stored in main memory and all unnecessary RAM STR system logic is turned off Only main memory and logic required to wake the system remain powered This state is used in the Customer Reference Board to satisfy the S3 ACPI power management state Full power During full power operation all components on the motherboard remain powered
258. stors and a 0 1 uF capacitor as shown in the following figure Figure 93 Termination for Direct RDRAM Clocking S ignals CFM CFM CFM CFM R1 28 02 or 2721 C1 0 1pF rambus clk term Design Guide 171 Inte 820E Chipset 4 3 172 intel DRCG Impedance Matching Circuit The external DRCG impedance matching circuit is shown in the following figure The values for the elements are listed Table 59 Figure 94 DRCG Impedance Matching Network 3 3V To 3 3 V DRCG supply connection FBead D V pp D DRCG q Vbp PP b H drcg imped match Table 59 External DRCG Component Values oem meme e a mammam NOTES 1 The ferrite bead and 10 pF bulk cap combination improves jitter and helps to keep the clock noise away from the rest of the system 2 For DRCG decoupling 0 1 capacitors are better than 0 01 uF or 0 001 UF caps The circuit in Figure 94 must match the impedance of the DRCG to the 28 channel impedance For more detailed information refer to the Direct Rambus Clock Generator Specification Design Guide intel 4 3 1 InteP 820E Chipset DRCG Layout Example Figure 95 DRCG Layout Example 4 4 4 5 4 6 Design Guide Cmid 100pF EMI Cap 4 Do Not Stuff route on bottom layer Rs 39 Keep trace from DRCG to
259. stors This signal has an integrated pull up of 9 3 External weak 8 2 pull up Open drain signal resistor to Vcc 3 3 V is recommended GNT A GPIO 16 GNT B GPIO 17 No extra pull up is needed These signals have integrated pull ups of 24 GNT A has an added strap function of top block swap The signal is sampled on the rising edge of PWROK The default value is high or disabled due to the pull up A jumper to a pull down resistor can be added to manually enable the function 125 Inte 820E Chipset Table 27 Hub Interface intel Checklist Items Recommendations Reason Effect 39 1 pull up resistor to 1 8 V via a 10 mil wide very short 0 5 inch trace HL 11 No pull up resistor is required Use a no stuff or a test point to put the ICH2 into NAND chain mode testing HL COMP Tie the COMP pin to a 40 0 196 or 296 ZCOMP no longer supported Table 28 LAN Interface Checklist Items Recommendations Reason Effect LAN RSTSYNC connect device LAN CLK Connect to platform LAN connect device LAN RXD 2 0 Connect to LAN RXD on platform LAN ICH2 contains integrated 9K pull up connect device resistors on interface LAN TXD 2 0 Connect to TXD on platform LAN LAN connect interface can be left NC if not used Input buffers are terminated internally Tabl
260. tched to each other within 50 mils These signals should be routed on the same layer If the signals must switch layers then both signals should change layers together If VddIPD is connected to the 1 8 V plane using a e g if a trace is not run from Hclkout and Relkout must still be routed differentially and ground isolated Figure 90 Direct RDRAM Clock Routing Dimensions Design Guide A CTM CTM RIMM to to RIMM B RIMM to RIMM for Clocks RIMM 0 RIMM 1 C RIMM to Termination 4 D DRCG to RIMM CFM CFM CTM CTM DRCG Term rambus clk route 169 Inte 820E Chipset 4 2 4 4 2 5 170 intel DRCG to RDRAM Channel The Direct RDRAM clock signals CTM CTM and CFM CFM are high speed impedance matched transmission lines Direct RDRAM clocks begin at the end of the Direct RDRAM channel and propagate to the controller as CTM CTM see Figure 90 where they loop back as The following table lists the placement guidelines Table 58 Placement Guidelines for Motherboard Routing Lengths Direct RDRAM Clock Routing Length Guidelines Clock To Length inches Section see Note CTM CTM DRCG Last RIMM connector 0 000 6 000 enmon 7 omecssm 9 NOTES Refer to Trace Geometry In Sections and D previous figure the
261. te to that in which the victim is switching 139 Inte 820E Chipset 140 intel Term Definition Flight time Flight time is a timing equation term that includes the signal propagation delay any effects of the system on the of the driver plus any adjustments to the signal at the receiver needed to guarantee the setup time of the receiver More precisely flight time is defined as the time difference between a signal at the input pin of a receiving agent crossing adjusted to meet the receiver manufacturer s conditions required for AC timing specifications i e ringback etc and the output pin of the driving agent crossing if the driver was driving the test load used to specify the driver s AC timings The Vggr guard band takes into account sources of noise that may affect the way signal becomes valid at the receiver See the definition of the guard band Maximum and Minimum Flight Time Flight time variations can be caused by many different parameters Obvious causes include variation of the board dielectric constant changes in the load condition crosstalk noise noise variation of the termination resistance and differences in I O buffer performance as a function of temperature voltage and the manufacturing process Less obvious causes include the effects of Simultaneous Switching Output SSO and packaging effects Maximum Flight Time
262. tem with 32 devices and a frequency of 400 MHz There are two potential solutions 1 Reduce the clock frequency during initialization Section 6 1 5 1 2 Increase the current capability of the 2 5 V voltage regulator Section Option 1 Reduce the Clock Frequency During Initialization Tie a single core well GPO with a default high state to both the SO and S1 pins of the DRCG 1 tie SO and S1 together and then connect to a GPO as shown in Figure 105 When the core power supply to the system is turned on the DRCG enters a test mode and the output frequency will match the input REFCLK frequency For details regarding this DRCG mode refer to the latest DRCG specification When the DRCG output clock is slowed down the power consumed by the 2 5 V power supply is reduced After the SetR CIrR commands have been issued the BIOS drives the GPO low to bring the DRCG back to normal operation If a default low GPO is used during power up all devices may come up in the standby state at full speed this requires more power Design Guide InteP 820E Chipset intel Figure 105 Use a GPO to Reduce DRCG Frequency 50 GPO g DRCG 50 gpo drcg freq 6 1 5 2 Option 2 Increase the Current Capability of the 2 5 V Voltage Regulator The second implementation option requires that the 2 5 V power supply be modified to maintain the maximum amount of current required by a fully populated RDRAM channel 7 5 Design Guide 1
263. the Accelerated Graphics Port Interface Specification Revision 2 0 Intel intends to incorporate the AGP RM changes into later revisions of the AGP interface specification In addition Intel has defined a reference design for a mechanical device utilizing the features defined in ECR 48 ECR 48 can be viewed on the Intel Web site at http developer intel com technology agp ecr htm More information regarding this component AGP RM is available from the following vendors Resin Color Supplier Part No Left Handed Orientation Right Handed Orientation Preferred Alternate Black AMP P N 136427 1 136427 2 Foxconn P N 006 0002 939 006 0001 939 Green Foxconn P N 009 0004 008 009 0003 008 73 Inte 820E Chipset 2 9 Note intel Hub Interface The MCH and ICH2 ballout assignments have been optimized to simplify the hub interface routing between these devices It is recommended that the hub interface signals be routed directly from the MCH to ICH2 with all signals referenced to Vss Layer transition should be keep to a minimum If a layer change is required use only two vias per net and keep all data signals and associated strobe signals on the same layer The hub interface is broken into two signal groups data signals and strobe signals These groups are Data signal HI 10 0 e Strobe signals HL STB HL 5 HL STB HL STB is a differential strobe p
264. the board layout In the ideal design the entire AGP interface signal field would be referenced to ground These recommendations are not specific to any particular PCB stack up but are applicable to all Intel chipset designs 2 8 7 Generation and TYPEDET specifies two separate power planes and Vppo is the core power for the graphics controller Vcc is always 3 3 V is the interface voltage 1 0 implementations Vppo was also 3 3 V For the designer developing 1 0 motherboard there is no distinction between and Vppo because both are tied to the 3 3 V power plane on the motherboard AGP 2 0 requires that these power planes be separate In conjunction with the 4x data rate the AGP 2 0 interface specification provides for low voltage 1 5 V operation The AGP 2 0 specification implements a TYPEDET type detect signal on the AGP connector that determines the operating voltage of the AGP 2 0 interface Vppo The motherboard must provide either 1 5 V or 3 3 V to the add in card depending on the state of the signal Refer to 1 5 V low voltage operation applies only to the AGP interface Vppo Vcc is always 3 3 V 66 Design Guide intel Note InteP 820E Chipset The motherboard provides 3 3 V to the Vcc pins of the AGP connector If the graphics controller needs a lower voltage then the add in card must regulate the 3 3 V voltage to the c
265. the transformer There should not be a power plane under the magnetics module Create a spark gap between pins 2 through 5 of the phone line connector s and a shield ground of 1 6 mm 59 0 mil This requirement is critical to passing the FCC Part 68 test for a phone line connection Note For world wide certification a trench of 2 5 mm is required In North America the spacing requirement is 1 6 mm However home networking can be used in other parts of the world including Europe where some Nordic countries require the 2 5 mm spacing 109 Inte 820E Chipset 2 22 2 3 110 4 Layer Board Design Top Layer Routing Sensitive analog signals are routed completely on the top layer without the use of vias This allows tight control of signal integrity and removes any impedance inconsistencies due to layer changes Ground Plane A layout split 100 mils of the ground plane under the magnetics module between the primary and secondary side of the module 1s recommended Power Plane Physically separate digital and analog power planes must be provided to prevent digital switching noise from being coupled into the analog power supply plane s VDD A Analog power may be a metal fill island separated from digital power and better filtered than digital power Bottom Layer Routing The digital high speed signals which include all LAN interconnect interface signals are routed on the bottom layer Common Physical Layout Issues
266. they have a resistor divider on the card that divides down to as shown inlFigure 39 To account for potential differences between Vppo and GND at the MCH and graphics controller 1 5 V cards use a source generated Veer 1 the signal is generated at the graphics controller and sent to and another is generated at the and sent to the graphics controller Both the graphics controller and the are required to generate and distribute it through the connector 1 5 V add in cards only Two pins are defined on the AGP 2 0 universal connector to allow this Vggr passing as follows e VREFGC Veer from the graphics controller to the chipset e VREFCG Vngr from the chipset to the graphics controller To preserve the common mode relationship between the and data signals the routing of the two Veer signals must be matched in length to the strobe lines within 0 5 inch on the motherboard and within 0 25 inch on the add in card The voltage divider networks consist of AC and DC elements as shown in The divider network should be placed as close as practical to the AGP interface to obtain the benefit of the common mode power supply However the trace spacing around signals must be a minimum of 25 mils to reduce crosstalk and maintain signal integrity Design Guide intel InteP 820E Chipset During a 3 3 V AGP 2 0 operation must be 0
267. this signal Test point used for manufacturing appears in XOR tree Table 40 Power Design Guide Checklist Items Recommendations Reason Effect V CPU IO 1 0 The power pins should be connected to the proper power plane for the processor s CMOS compatibility signals Use one 0 1 uF decoupling cap Used to pull up all processor signals Vcc RTC No clear CMOS jumper on Vcc RTC Use a jumper on RTCRST or GPI or use safe mode strapping for clear CMOS Vcc 3 3 V Requires six 0 1 uF decoupling caps Vcc Sus 3 3 V Requires one 0 1 decoupling cap Vcc 1 8 V Requires two 0 1 decoupling caps Vcc Sus 1 8 V Requires one 0 1 decoupling cap 5V REF SUS Requires one 0 1 decoupling cap V5REF 505 affects only the 5 V tolerance for USB OC 3 0 ins and it can be connected to 5053 3 if 5 V tolerance is not required for these signals 5V REF 5 Vrer is the reference voltage for 5 V tolerant inputs in the ICH2 The VREF 2 1 pins must be tied together 5 Vrer must power up before simultaneously with Vcc 3 3 It must power down after or simultaneously with Vcc 3 3 Refer to which shows an example circuit schematic that may be used to ensure the proper 5 VREF sequencing 131 Inte 820 Chipset Figure 73 5Vpe r Circuitry Vcc supply 3 3 V To system Vref To system 5 V suppl
268. tical Dimensions for Component Placement K Intel L 82562 gt Magnetics 82562EM Module ICH2 EEPROM crit dim comp plac mm ome 2 22 4 4 1 Distance from Magnetics Module to RJ45 Distance A in the previous figure should be given the highest priority during board layout The separation between the magnetics module and the RJ45 connector should be kept to less than 1 inch The following trace characteristics are important and should be observed Differential impedance The differential impedance should be 100 The single ended trace impedance is approximately 50 However the differential impedance also can be affected by the spacing between traces e Trace symmetry Differential pairs e g TDP and TDN should be routed with consistent separation and with exactly the same lengths and physical dimensions e g width Asymmetric and unequal length traces in the differential pairs contribute to common mode noise This can degrade the receive circuit s performance and contribute to radiated emissions from the transmit circuit If the Intel 82562 component must be placed farther than a couple of inches from the RJ45 connector distance B can be sacrificed It should be a priority to minimize the total distance between the Intel 82562ET component and RJ 45 The measured trace impedance for layout designs targeting 100 often yields a lower actual
269. to the internal APIC as follows PIRQ A is connected to IRQ16 PIRQ B to IRQ17 PIRQ C to IRQ18 and PIRQ D to IRQ19 This frees the ISA interrupts PIRQ G F These signals require a pull up In non APIC mode the PIRQx signals be resistor Recommend a 2 7 routed to interrupts 3 4 5 6 7 9 10 11 12 14 or GPIO 4 3 pull up resistor to Vcc 5 or an 15 Each PIRQx line has a separate Route Control 8 2 pull up resistor to Vcc Register mode these signals connected to the internal I O APIC as follows PIRQ E E is connected to IRQ20 PIRQ F to IRQ21 PIRQ G to IRQ22 and PIRQ H to IRQ23 This frees the ISA interrupts PIRQ H These signals require a pull up In non APIC mode the PIRQx signals can be resistor 2 7 pull up resistor routed to interrupts 3 4 5 6 7 9 10 11 12 14 or to Vcc 5 or an 8 2 pull up 15 Each PIRQx line has a separate Route Control resistor to Vcc 3 3 is Register recommended In the mode these signals are connected to the internal I O APIC as follows PIRQ E is connected to IRQ20 PIRQ F to IRQ21 PIRQ G to IRQ22 and PIRQ H to IRQ23 This frees the ISA interrupts If not needed for interrupts these signals can be used as GPIO APIC e f the APIC is used If the APIC is not used on UP systems 150 Q pull up resistors on APICD 0 1 gt Same as SC242 checklist PICD 0 1
270. transfers at 3 3 V are not allowed Table 13 Connector Add in Card Interoperability 21 1 5 V Connector 3 3 V Connector Universal Connector 1 5 V card 3 3 V card Design Guide 71 Inte 820E Chipset 2 8 12 72 intel AGP Universal Retention Mechanism RM Environmental testing and field reports indicate that without proper retention AGP cards and AGP In Line Memory Module AIMM cards may come unseated during system shipping and handling In order to prevent the disengagement of AGP cards and AIMM modules Intel recommends that AGP based platforms use the AGP retention mechanism RM The AGP RM is a mounting bracket used to properly locate the card with respect to the chassis and to assist with card retention The AGP RM is available in two different handle orientations left handed see and right handed Most system boards accommodate the left handed AGP RM Because the manufacturing capacity is greater for the left handed RM Intel recommends that customers design into their systems the left handed AGP RM Figure 41 The right handed AGP RM is identical to the left handed AGP RM except for the position of the actuation handle which is located on the same end as in the primary design but extends from the opposite side parallel to the longitudinal axis of the part 41 details the keep out information for the left handed AGP RM Use this information to ensure that your motherboard design leaves adequate space for RM inst
271. ty in the signal s reference plane at this junction For the Intel 820E chipset FC PGA decoupling guidelines refer to the Intel 820 Chipset Design Guide Addendum for the Intel Pentium Ill Processor for the PGA370 Socket These guidelines can be downloaded from the Intel website at developer intel com desi Transmission line geometry also influences the return path of the reference plane The following decoupling recommendations take this into consideration e A signal that transitions from a stripline to another stripline should have close proximity decoupling among all four reference planes e A signal that transitions from a stripline to a microstrip or vice versa should have close proximity decoupling between the three reference planes e A signal that transitions from a stripline or microstrip through vias or pins to a component Intel 82820 MCH etc should have close proximity decoupling across all involved reference planes to ground for the device 159 Inte 820E Chipset 3 4 4 3 5 160 intel Clock Routing Analog simulations are required to ensure that the clock net signal quality and skew are acceptable The system clock skew must be minimized The calculations and simulations for the example topology in this document have a total clock skew of 200 ps and 150 ps of clock jitter For a given design the clock distribution system including the clock components must be evaluated to ensure that these
272. uide 1 8 V 2 5V diode 1 8V amp 2 5V The plane is used to power the interface and the graphics component interface Refer to the AGP Interface Specification Revision 2 0 http www agpforum org For long term component reliability the following power sequence is strongly recommended while the interface of the is running at 3 3 V If the AGP interface is running at 1 5 V the following power sequence recommendations no longer apply The power sequence recommendations are as follows 1 During the power up sequence the 1 8 V must ramp up to 1 0 V before the 3 3 V ramps up to 22 V 2 During the power down sequence the 1 8 V cannot ramp below 1 0 V before the 3 3 V ramps below 2 2 V 3 same power sequence recommendation applies when entering and exiting the S3 state because MCH power is completely off during the S3 state System designers must keep this requirement in mind while designing the voltage regulators and selecting the power supply For further details regarding the voltage sequencing requirements refer to the TEN revision of the Intel 820 Chipset Intel 82820 Memory Controller Hub MCH Datasheet h This regulator is required in all designs unless the design does not support 1 5 AGP and therefore does not support 4x AGP 3 3VSB The 3 3 plane powers the I O buffers in the resume well of the ICH2 and the PCI 3 3
273. uide 87 Inte 820E Chipset Figure 52 DN Support Circuitry for Multi Channel Audio Upgrade Motherboard CNR Board From AC 97 Controller AC97_RESET To General Purpose Input CDC_DN_ENAB To 97 4 SDATA INO Digital _ SDATA_IN1 Controller CNR Connector Figure 52 shows the circuitry required on the motherboard to support a two codec down configuration This circuitry disables the codec on a single codec CNR Notice that in this configuration the resistor has been changed to 100 Figure 53 DN Support Circuitry for Two Codecs on Motherboard One Codec on CNR Motherboard CNR Board From AC 97 Controller AC97_RESET To General Purpose Input CDC_DN_ENAB SDATA_INO SDATA_IN1 To AC 97 Digital Controller CNR Connector Figure 53 shows the case of two codecs down and a dual codec CNR In this case both codecs on the motherboard are disabled while both on CNR are active by being 10 and Rg being 1 88 Design Guide InteP 820 Chipset intel Figure 54 CDC DN ENAB Support Circuitry for Two Codecs on Motherboard Two Codecs on CNR Motherboard CNR Board RESET From AC 97 Controller AC97_RESET odec D To General Purpose Input CDC DN ENAB SDATA IN SDATA INO SDATA IN1 To AC 97 Digital Controller
274. us clock FWH Flash BIOS FWH Flash BIOS LPC UF clock clock pe 3V66 0 3 Hub interface AGP bus CLK66 66 MHz clock Hubinterfaceclock interface clock cke 0 1 Internal ICH2 logic 2 Internal super I O logic Super Vendor EOM 48MHz 2 33V CPU DIV2 0 1 reference clock DRCG REFCLK 50 66 MHz dee ow 21 10 The CK133 is a mixed voltage component Some of the output clocks are 3 3 V and some of the output clocks are 2 5 V As a result the CK133 device requires both 3 3 V and 2 5 V These power supplies should be a clean as possible Noise in the power delivery system for the clock driver can cause noise on the clock lines 163 Inte 820E Chipset 164 intel The MCH uses the same clock for hub interface and It is important that the hub interface AGP clocks are routed so as to ensure that the skew requirements are satisfied as follows Between the MCH hub interface AGP clock and the AGP connector or device Between the hub interface AGP clock and the ICH2 hub interface clock The DRCG reference clock operates at one half the processor clock frequency It is an input into the DRCG and is used to generate the Direct RDRAM clock to master differential pair
275. us topology to varying parameters to be analyzed systematically Sensitivity of the bus to minimum flight time maximum flight time and signal quality should be covered Suggested sweep parameters include trace lengths termination resistor values and any other factors that may affect the flight time signal quality and feasibility of layout Minimum flight time and worst signal quality are typically analyzed using fast I O buffers and interconnect Maximum flight time is typically analyzed using slow I O buffers and slow interconnects Outputs from each sweep should be analyzed to determine which regions meet timing and signal quality specifications To establish the working solution space find the common space across all sweeps that pass timing and signal quality tests The solution space should allow enough design flexibility for a feasible cost effective layout 145 Inte 820E Chipset 3 2 3 3 3 2 3 4 146 intel Monte Carlo Analysis Perform a Monte Carlo Analysis to refine the passing solution space region A Monte Carlo Analysis involves randomly varying parameters independently of one another over their tolerance ranges This analysis is designed to ensure that no region of failing flight time and signal quality exists between the extreme corner cases run in pre layout simulations For the example topology vary the following parameters during Monte Carlo simulations Lengths L1 through L3 Termination resistance R
276. used for the dual footprint are the for the Intel 82562 component and the SSOP for the Intel 82562 component 22 Q resistor can be placed at the driving side of the signal line to improve signal quality on the LAN connect interface Resistors should be placed as close as possible to components Use components that can satisfy both the Intel 82562ET and Intel 82562EH component configurations 1 a magnetics module Install components for either the Intel 82562 or Intel 82562 component configuration Only one configuration can be installed at a time Route shared signal lines such that stubs are not present or are minimized Stubs may occur on shared signal lines 1 e RDP and RDN These stubs result from traces routed to an uninstalled component Use 0 Q resistors to connect and disconnect circuitry not shared by both configurations Place resistor pads along the signal line to reduce stub lengths Refer to the Intel 820 CRB layout for routing examples 121 Inte 820E Chipset 2 22 7 122 intel Traces from magnetics to connector must be shared and not stubbed An RJ 11 connector that fits into the RJ 45 slot is available Any amount of stubbing will destroy both HomePNA and Ethernet performance ICH2 Decoupling Recommendations The ICH2 can generate large current swings when switching between logic high and logic low This condition could cause the component voltage rails to
277. ust not cross the power plane split lines Analog and digital signals should be located as far as possible from each other Partition the board with all analog components grouped together in one area and all digital components in another Separate analog and digital ground planes should be provided with the digital components over the digital ground plane and the analog components including the analog power regulators over the analog ground plane The split between planes must be a minimum of 0 05 inches wide Keep digital signal traces especially the clock as far as possible from the analog input and voltage reference pins Do not completely isolate the analog audio ground plane from the rest of the board ground plane There should be a single point 0 25 inches to 0 5 inches wide where the analog isolated ground plane connects to the main ground plane The split between planes must be a minimum of 0 05 inches wide Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main motherboard ground That is no signal should cross the split gap between the ground planes which would cause a ground loop thereby greatly increasing EMI emissions and degrading the analog and digital signal quality Analog power and signal traces should be routed over the analog ground plane Digital power and signal traces should be routed over the digital ground plane Bypassing and
278. ute more EMI than the original signal itself Design Guide intel 2 22 4 2 22 4 1 Design Guide InteP 820E Chipset 2 22 3 5 3 Distance from LPF to Phone RJ11 Distance should be less than 1 inch Regarding trace symmetry route differential pairs with consistent separation and with exactly the same lengths and physical dimensions Asymmetry and unequal length in the differential pairs contribute to common mode noise This can degrade the receive circuit performance and contribute to radiated emissions from the transmit side Intel 82562ET Intel 82562EM Component Guidelines Related document are as follows e Intel 82562ET 10 100 Mbps Platform LAN Connect PLC Product Preview Datasheet Order OR 2106 e Intel 82562ET Platform LAN Connect PLC Networking Silicon Advance Information Datasheet released e Intel 82562EM Platform LAN Connect PLC Networking Silicon Advance Information Datasheet released e Intel 82562ET LAN on Motherboard Design Guide 414 OR 2336 Intel 82562ET EM Design Platform LAN Connect AP 412 OR 2059 Reference Design Application Note AP 418 OR 2281 For correct LAN performance designers must comply with the general guidelines outlined in Section Additional guidelines for implementing an Intel 82562ET or Intel 82562 LAN connect component are as follows Guidelines for Intel 82562ET Intel 82562EM Component Placement Comp
279. ve differential traces The transmit trace closest to a receive trace will induce more crosstalk on the closest receive trace and it can greatly degrade the receiver s BER over long cables After exiting the PLC the transmit traces Design Guide InteP 820 Chipset should be kept at least 0 3 inch from the nearest receive trace Possible exceptions are only where the traces enter or exit the magnetics the RJ 45 11 and the PLC 6 Use of an inferior magnetics module The magnetics modules used by Intel have been fully tested for IEEE PLC conformance for long cable BER and for emissions and immunity Inferior magnetics modules often have less common mode rejection and or no autotransformer in the transmit channel 7 Using an Intel 82555 or Intel 82558 component s physical layer schematic in a PLC design The transmit terminations and decoupling are different and there also are differences in the receive circuit Please use the appropriate reference schematic or Application Notes 8 Failure to use or incorrect use of the termination circuits for the unused pins at the RJ 45 11 and for the wire side center taps of the magnetics modules Unused RJ pins and wire side center taps must be correctly referenced to chassis ground via the proper value resistor and a capacitance or termplane If these not terminated properly there can be emissions 1 FCC problems IEEE conformance issues and long cable noise BER problems T
280. way to connect the PDIAG CBLID signal of the IDE connector to the host is shown in the following figure All IDE devices have a 10 pull up resistor to 5 V on this signal Not all GPI and GPIO pins on the ICH2 are 5 V tolerant If non 5 V tolerant inputs are used a resistor divider is required to prevent 5 V on the ICH2 or FWH Flash BIOS pins The proper value of the divider resistor is 10 kO as shown in Design Guide intel InteP 820E Chipset Figure 46 Combination Host Side Device Side IDE Cable Detection Design Guide IDE drive To secondary IDE connector 10 GPIO L PDIAG PDIAG B CBLID GPIO Resistor required for IDE drive non 5V tolerant GPI 5V To secondary IDE connector e a 10 80 conductor IDE cable ICH2 PDIAG PDIAG CBLID GPIO HT Resistor required for non 5V tolerant GPI IDE_combo_cable_det After diagnostics this mechanism allows the BIOS to sample PDIAG CBLID If the signal is high there is a 40 conductor cable in the system and ATA modes 3 4 and 5 must not be enabled If PDIAG CBLID is detected low then there may be an 80 conductor cable in the system or there may be a 40 conductor cable and a legacy slave device Device 1 that does not release the PDIAG CBLID signal as required by the ATA ATAPI 4 standard In this case BIOS should check the IDENTIFY DEVICE information in a connected device t
281. with the SECC2 design The AGTL layout considerations detailed in Chapter Design ktill apply to FC PGA designs including ground referencing the AGTL signals The design guidelines are found in the Intel 820 Chipset Design Guide Addendum for the Pentium Processor for the PGA370 socket These guidelines can be downloaded from the Intel website at http developer intel com design chipsets designex 298178 htm 77 Inte 820E Chipset 2 10 1 2 11 78 intel System Bus Ground Plane Reference All system bus signals must be referenced to GND to provide the optimal current return path The ground reference must be continuous from the MCH to the Intel PGA370 socket This may require a GND reference island on the plane layers closest to the signals Any split in the ground island will provide a suboptimal return path In a 4 layer board this will require that the VCCID island be on an outer signal layer The following figure shows a 4 layer motherboard power plane with ground reference for system bus signals Figure 45 Ground Plane Reference 4 Layer Motherboard PGA370 GND Plane gnd plane ref 4layer Additional Host Bus Guidelines Minimizing Crosstalk on the AGTL Interface The following general rules will minimize the effect of crosstalk in a high speed AGTL bus design Maximize the space between traces Maintain a minimum of 0 010 inch between traces wherever possible It may be
282. y sys des 5Vref circ Table 41 IDE Checklist Checklist Items Recommendations Reason Effect PDD 15 0 SDD 15 0 No extra series termination resistors or other pull ups pull downs are required PDD7 SDD7 doesn t require a 10 pull down resistor Refer to the ATA TAPI 4 specification These signals have integrated series resistors NOTE Simulation data indicates that the integrated series termination resistors are a nominal 33 but can range from 31 Q to 43 PDIOW PDIOR PDDACK PDA 2 0 PDCS1 PDCS3 SDIOW SDIOR SDDACK SDA 2 0 SDCS1 SDCS3 No extra series termination resistors Pads for series resistors can be implemented if the system designer has signal integrity concerns These signals have integrated series resistors NOTE Simulation data indicates that the integrated series termination resistors are a nominal 33 but can range from 31 Q to 43 0 to form the IDERST signal 33 series termination resistor is recommended on this signal PDREQ No extra series termination resistors These signals have integrated series resistors in the ICH2 SDREQ No pull down resistors are needed These signals have integrated pull down resistors in the ICH2 PIORDY No extra series termination resistors These signals have integrated series resistors in the ICH2 SIORDY Pull up to 3 3 V via a 4 7 resistor IRQ14 IRQ15 Recommend
283. y factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane To minimize trace inductance high speed signals and signal layers close to a ground or power plane should be as short and wide as practical Ideally this ratio of trace width to height above ground plane should be between 1 1 and 3 1 To maintain trace impedance the trace width should be modified when changing from one board layer to another if the two layers are not equidistant from the power or ground plane Differential trace impedances should be controlled at approximately 100 It is necessary to compensate for trace to trace edge coupling which can lower the differential impedance by 10 when the traces within a pair are closer than 0 030 inch edge to edge Traces between decoupling and 1 filter capacitors should be as short and wide as practical Long and thin traces are more inductive and would reduce the intended effect of decoupling capacitors For similar reasons traces to I O signals and signal terminations should be as short as possible Vias to the decoupling capacitors should be sufficiently large in diameter to decrease series inductance 2 22 2 1 2 Signal Isolation Signal isolation rules include the following f possible separate and group signals by function on separate layers Maintain a gap of 100 mils between all differential pairs phone line and Ethernet and other nets but
284. yer 1 Ground isolation Layer 2 Ground plane e Layer 3 Ground reference in the power plane ayer 4 Ground isolation ground vias and pins MUST be connected to all 4 layers Direct RDRAM Connector Compensation The RIMM connector inductance causes an impedance discontinuity on the Direct RDRAM channel This may reduce the voltage and timing margin To compensate for the inductance of the connector an approximately 0 65 pF to 0 85 pF compensating capacitive tab C TAB is required on each RSL connector pin This compensating capacitance must be added to the following connector pins at each connector LCTM LCTM RCTM RCTM LCFM LCFM RCFM RCFM LROW 2 0 RROW 2 0 LCOL 4 0 RCOL 4 0 RDQAI8 0 LDQA S 0 RDQB 8 0 LDQB 8 0 SCK CMD This can be achieved on the motherboard by adding a copper tab to the specified RSL pins at each connector The target value is approximately 0 65 pF 0 85 pF The copper tab area for the recommended stack up was determined by means of simulation The copper tabs can be placed on any signal layer independently of the layer on which the RSL signal is routed The following equation is an approximation usable for calculating the copper tab area on an outer layer Equation 1 Approximate Copper Tab Area Calculation Design Guide Length x Width Area x Thickness of prepreg 1 1 Where 2 25 x 101 Farads mil Relative dielectric const
285. z 0z 6 18 1 06996 NOSTOA 2 ALIO 006 1 1634 41 14 99d 9 T 90 WHA Quvos LASdIHO 3028 191 3 111 0022445 ofues WHA 989 3015 ON SSH dd f 1 78198 84A 184049d013 m 811 L1NV4 XVI WHA 19 78198 1 SOON WHA 166 4916600 80 20 40 0 1xeu 160 6119 8119 AUNI SWH Jo v LL uoddns 70 797011107010780280 8 35 926 QqouMd WHA SOOA 994 peseq WHA 3 06956 NOS10d A 3v 00d ALIO 006 U A8 1530 99d 9 50 SYOLVINDSY Z 13SdIHO 3028 H 131NI t 91 01 0002 02 6 5 15 1 Ov JO 5 1UF X7R 15 Xass zoon NINE z L

Intel 820E Personal Computer User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents