Intel 80219 Computer Hardware User Manual
Contents
1. Data Cache Unit Can Stall for a Single Cycle When the data cache unit retries an operation that is in the pending buffer a single cycle stall occurs No workaround This is a performance issue only NoFix Specification Update 15 Core Errata Intel 80219 General Purpose PCI Processor m tel INTtel 10 Problem Workaround Status 16 Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty When there is an aborted store that hits clean data in the data cache data in an aligned four word range that has not been modified from the core since it was last loaded in from memory or cleaned the data in the array is not modified the store is blocked but the dirty bit is set When the line is then aged out of the data cache or explicitly cleaned the data in that four word range is evicted to external memory even though it has never been changed In normal operation this is nothing more than an extra store on the bus that writes the same data to memory as is already there Here is the boundary condition where this might be visible 1 a cache line is loaded into the cache at address A 2 another master externally modifies address A 3 a core store instruction attempts to modify A hits the cache aborts because of MMU permissions and is backed out of the cache That line should not be marked dirty but because of this errata is marked as dirty 4 the cache line at A then ages out or is explicit2. Date Version Description July 2004 002 Added Specification Clarification 7 November 2003 001 Initial Release Specification Update Intel 80219 General Purpose PCI Processor Preface Preface This document is an update to the specifications contained in the Affected Documents Related Documents table below This document is a compilation of device and documentation errata specification clarifications and changes It is intended for hardware system manufacturers and software developers of applications operating systems or tools Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents This document may also contain information that was not previously published Affected Documents Related Documents Title Order Inte 80219 General Purpose PCI Processor Developer s Manual 274017 Inte 80219 General Purpose PCI Processor Advance Information Datasheet 274018 Inte 80219 General Purpose PCI Processor Design Guide 274019 Nomenclature Note Errata are design defects or errors These may cause the Intel 80219 General Purpose PCI Processor behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications The
3. Intel 80219 General Purpose PCI Processor Specification Update July 2004 Notice The Intel 80219 General Purpose PCI Processor 80219 may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are documented in this specification update Document Number 274020 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL amp PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Designers must not rely on the
4. Data for the DWORD that Target Aborted from the MCU when Using 32 Bit Memory ECC Enabled and in PCI Mode The external PCI bus requests a read through the ATU to the MCU starting at the high DWORD Remember the MCU is in 32 bit mode The ATU requests multiple DWORDS since it pre fetches but starts at the high DWORD address The MCU issues two DWORDS First the high followed by the low and then a Target Abort so the DWORD count is two When the ATU returns the data to the external PCI agent in PCI Mode ONLY the logic ONLY disconnects on 64 byte QWORD boundaries Recall the ATU DWORD count is at two When the external PCI device returns to get data the ATU returns the first DWORD and SHOULD disconnect because it does not have enough data to get to the next QWORD boundary It does not do this Instead it returns invalid data in the high DWORD of the second QWORD data from a previous fetch and the transaction is corrupted This issue occurs when all of the following conditions exist in the MCU 1 32 bit memory 2 ECC is enabled 3 The PCI bus is in PCI mode Use 64 bit Memory PCI X Mode or ECC disabled NoFix PBI Issue When Using 16 bit PBI Transactions in PCI Mode Under certain conditions in bound burst and non burst reads and writes from the PCI bus to the PBI would appear as two writes on the PBI However the byte enables are not asserted for the second write This happens when 1 80219 is in PCI mode 2 Another PCI master
5. Intel 80219 General Purpose PCI Processor B 0 B 1 Stepping E m a e a c LL AD 11 x PCI X Bus AD 64 0 B2845 01 Specification Update 25 Intel 80219 General Purpose PCI Processor Specification Clarifications n B Specification Clarifications Issue Status Issue Status Note 26 The Intel 80219 general purpose PCI processor is compliant with the PCI Local Bus Specification Revision 2 2 but it is not compliant with PCI Local Bus Specification Revision 2 3 The Intel 80219 general purpose PCI processor was designed to be compliant with the PCI X Addendum to the PCI Local Bus Specification Revision 1 0a that calls out compliance with the PCI Local Bus Specification Revision 2 2 Since the release of the 80219 the PCI Special Interest Group has released a new specification revision PCI Local Bus Specification Revision 2 3 NoFix The current stepping of the 80219 is not compliant with PCI Local Bus Specification Revision 2 3 and there are no plans to make it compliant with the PCI Local Bus Specification Revision 2 3 in future steppings Modifications to the Hot Debug procedure are necessary for the Intel 80219 ge purpose PCI processor when flat memory mapping is not used Virtual Address z Physical Address The Intel 80219 general purpose PCI processor can implement Hot Debug as stated in the application note Hot Debug for Intel Xscale Core Debug http
6. is attempting to access the PBI behind the 80219 3 16 bit mode on PBI The BE signals can be used in combination with the PCE The BE prevents the second CE from being recognized by the Flash See the Intel IQ80219 evaluation platform board 1Q80219 schematic for a circuit design to correct this issue NoFix Specification Update intel 3 Problem Workaround Status 4 Problem Workaround Status 5 Problem Workaround Status Intel 80219 General Purpose PCI Processor Non Core Errata MCU Pointers are Incorrect following a Restoration from a Power Fail This issue occurs when 1 There is a power failure not during power management or normal shutdown 2 When power is restored the internal MCU pointers to the SDRAM may not be correct 3 When a read from SDRAM prior to doing a write to SDRAM is the first MCU operation done after the power is restored the MCU pointers may be incorrect and can be reading the wrong data 4 However when a write to SDRAM is the first MCU operation done after the power is restored then the pointers are correct and everything works properly Following restoration of power after a power failure ensure that the first MCU operation done is a write to SDRAM NoFix PMU Does Not Account for when the Arbiter Deasserts GNT One Cycle before FRAME One of the countable PMU events is bus acquisition latency for the ATU There is a condition where the
7. look similar to the MSR Move to Status register from an ARM register instruction to be interpreted as an MSR instruction The mis decoded MSR instruction also adds a SUBNV PC 0x4 to the instruction flow Workaround Do not use undefined opcodes of this form 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 54 3 2 10 0 0 0 1 0 10 001 O 00 0 1 0 10 010 O 00 0 1 0 10 1041120 Status NoFix 4 Debug Unit Synchronization with the TXRXCTRL Register Problem The RX bit in the TXRXCTRL TX RX Control register comes from the JTAG clock domain to the core clock domain and several cycles are needed for the register in the core clock domain to update During this time a debugger which is running a fast JTAG clock relative to the core clock may read the bit before it updates in the register thus reading the old value Workaround The JTAG clock should be slower than the core clock Status NoFix 5 Extra Circuitry Is Not JTAG Boundary Scan Compliant Problem The IEEE 1149 1 JTAG specification states that when the HIGHZ instruction is selected all system logic outputs shall immediately be placed in an inactive drive state The JTAG unit on the core creates an internal float signal which is driven to the I O pads This signal is derived from the HIGHZ instruction however the HIGHZ instruction gets flopped by a rising edge of TCK first before it is abl
8. not completed out of order When a data delivery sequence is required descriptors should be used to ensure sequenced arrival e g in the example above break the data into blocks then use multiple descriptors linked in the correct order to ensure sequential data delivery Writing to reserved registers can cause unexpected behavior The Intel 80219 General Purpose PCI Processor contains several reserved registers The Intel 80219 General Purpose PCI Processor Developer s Manual Section 15 5 Table 273 states that memory map register locations FFFFE800H FFFFE8FFH are reserved Writing to these can cause the processor to enter an undesired state NoFix Specification Update intel n 5 Documentation Changes None for this revision of this specification update gt wa z POWERED e Specification Update 29 Intel 80219 General Purpose PCI Processor Documentation Changes l n This Page Left Intentionally Blank 30 Specification Update
9. of offsets 40h to 4Ch Configure the BARO as non prefetchable IABARO 3 when accessing these non prefetchable MU registers Since non prefetchable memory windows cannot be placed above the 4 Gbyte address boundary when the Prefetchable Indicator bit IABARO 3 is cleared prior to host configuration also clear the Type Indicator bits IABARO 2 1 for 32 bit addressability When the non prefetchable MU registers are in use those memory accesses that require prefetchable operations use the BAR2 configured as prefetchable Reading Unpopulated SDRAM Memory Banks A hang condition can occur with the 80219 when firmware does a read to unpopulated SDRAM memory and DQSO is sampled low In this scenario putting a load i e scope probe on the DQSO signal could trigger DQSO to be sampled low which the MCU interprets as the pre amble and waits for DQSO to go high Since the read is to unpopulated memory nothing drives the DQSO signal high therefore the 80219 appears to hang Doc Do not attempt to read from non existent memory In some applications firmware performs a memory scan typically during boot up to determine the total amount o SDRAM installed Instead either use the Serial Presence Detect SPD mechanism or have it hard coded in firmware SPD is used to read via PC from a non volatile storage device This device contains data programmed by the DIMM manufacturer that identifies the module type various SDRAM organizations and timing pa
10. the first memory operation is correctly cancelled and no abort occurs However depending on the timing the second memory operation may not work correctly The data cache may internally cancel the second operation but the register file may have score boarded registers for that second memory operation The effect is that the core may hang due to a permanently score boarded register or that a store operation may be incorrectly cancelled In Special Debug State any memory operation that may cause a precise data abort should be followed by a write buffer drain operation This precludes further memory operations from being in the pipe when the abort occurs Load Multiple Store Multiple that may cause precise data aborts should not be used NoFix Specification Update 17 Core Errata Intel 80219 General Purpose PCI Processor m tel INTtel 13 Problem Workaround Status 14 Problem Workaround Status 18 Accesses to the CP15 ID register with opcode2 0b001 returns unpredictable values The ARM Architecture Reference Manual ARM DDI 0100E states the following in chapter B 2 section 2 3 If an lt opcode2 gt value corresponding to an unimplemented or reserved ID register is encountered the System Control processor returns the value of the main ID register ID registers other than the main ID register are defined so that when implemented their value cannot be equal to that of the main ID register Softwar
11. Intel Xeon Intel XScale Itanium JobAnalyst LANDesk LanRover MCS MMX MMX logo NetPort NetportExpress Optimizer logo OverDrive Paragon PC Dads PC Parents Pentium Pentium II Xeon Pentium IIl Xeon Performance at Your Command ProShare RemoteExpress Screamline Shiva SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside This Way In TokenExpress Trillium Vivonic and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries The ARM and ARM Powered logo marks the ARM marks are trademarks of ARM Ltd and Intel uses these marks under license from ARM Ltd Other names and brands may be claimed as the property of others 2 Specification Update i ntel Inte 80219 General Purpose PCI Processor Contents Revision HISIOry a E EO EE N EE eee yaad 5 ai ERROR TTE 6 Summary Table of GhantBb ee ER tetra EE DR NEE ae 7 Identification INGANGE EE EN en eu AE ee Nek es ene 11 Core Errata EO N T I TET 13 Moes AE ER ER EE N ED UOS 20 Specification Changes ii EG Eoo o D 24 Specification Clarifications CE TO 26 Documentation Changes N OR EE 29 Specification Update 3 Inte 80219 General Purpose PCI Processor 7 tel This Page Left Intentionally Blank 4 Specification Update intel Intel 80219 General Purpose PCI Processor Revision History Revision History
12. absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 80219 General Purpose PCI Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 2004 AlertVIEW i960 AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips Commerce Cart CT Connect CT Media Dialogic DM3 EtherExpress ETOX FlashFile GatherRound i386 i486 iCat iCOMP Insight960 InstantlP Intel Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel ChatPad Intel Create amp Share Intel Dot Station Intel GigaBlade Intel InBusiness Intel Inside Intel Inside logo Intel NetBurst Intel NetStructure Intel Play Intel Play logo Intel Pocket Concert Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel TeamStation Intel WebOutfitter
13. acquire counter is not stopped even though the ATU starts a transaction When the arbiter deasserts GNT in PCI X mode the requestor can still start a transaction for one cycle due to allowed pipelining In this situation the PMU does not properly detect the FRAME as the ATU and continues running the counter No workaround NoFix Lost Data During Bursts of Large Number of Partials with 32 bit ECC Memory When the MCU operates in 32 bit mode only and it is hit by enough partials to cause the input posted write buffer to fill in 32 bit mode it holds 512 bytes the MCU has conditions where it does NOT disconnect on the IB internal bus before overrunning When the buffer overruns the MCU momentarily thinks it is empty allowing the refresh to occur but also causing all data to be lost for the rest of the burst The ATU continues to throw data at the MCU but this data is lost This is strictly a 32 bit memory ECC on mode issue as this is the only way to fill the entire buffer since all buffers on the IB are 1 K in size except the MCU when operating in 32 bit DDR mode The DMA AAU and core cannot cause the situation in 32 bit mode because they only issue up to two partials in their burst before disconnecting In these situations the MCU will drain enough data to prevent buffer overrun Use 64 bit memory or ECC disabled NoFix Specification Update 21 Intel 80219 General Purpose PCI Processor Non Core Errata n a Proble
14. arge block transfer of data the core may have to wait until the DMA transaction is completed before it would have access to the internal bus to initiate its transaction No workaround NoFix The MCU supports a page size of 2 Kbytes for 64 bit mode The Intel 80219 General Purpose PCI Processor Developer s Manual Section 6 1 1 and Section 6 2 2 3 states that the MCU supports a page size of 4 Kbytes for 64 bit mode and 2 Kbytes for 32 bit mode This is in error The MCU supports a page size of 2 Kbytes for 64 bit mode and for 32 bit mode No workaround NoFix Specification Update Problem Implication Workaround Status Intel 80219 General Purpose PCI Processor Non Core Errata Vih Minimum Input High Voltage Vih level for the PCI pins The Vih Minimum Input High Voltage Vih level for the PCI pins is being tested at 100 mV higher than the minimum Vih level specified in Table 4 3 DC Specifications for 3 3 V Signaling of the PCI Local Bus Specification Revision 2 2 This Vih test limit only applies to cold temperature testing specified to be 0 C The PCI Local Bus Specification Revision 2 2 specifies the minimum Vih level to be 0 5 Vcc The Vcc specification is 3 3 V 10 with the minimum Vcc specification or minimum power level being tested at 3 0 V The minimum Vih level per the PCI Specification should therefore be 0 5 3 0 V or 1 5 V The 80219 is unable to meet this minimum Vih level at cold temperat
15. developer intel com design iio applnots 273539 htm However there can be a conflict for resources when flat memory mapping is not used Virtual Address Physical Address This is primarily due to the debug implementation within the core that causes the Instruction Memory Management Unit to be disabled when in this Special Debug State NoFix The following are suggested steps to overcome this conflict within a debug environment 1 Instrument the application code to add an infinite loop before any memory is remapped physically or virtually 2 Hook up the JTAG Debugger that supports Hot Debug 3 Set PC to address passed the loop 4 The code can now run without the need to reset the application environment Once a debug session has ended you must follow the above steps over again in order to regain debug control Specification Update Status Issue Status Issue Status Intel 80219 General Purpose PCI Processor Specification Clarifications BARO Configuration When Using the Messaging Unit MU When the BARO is configured as a prefetchable register by default and a burst request crosses into or through the range of offsets 40h to 4Ch i e this includes the Circular Queues the transaction is signaled a Target Abort immediately on the PCI PCI X bus which may be read as an NMI by the host BIOS Doc Do not configure the BARO as prefetchable when using BARO and the non prefetchable MU registers i e range
16. dressing Mode 5 Can Corrupt Protected 6 X 15 NoFix Registers X 15 NoFix Load Immediately Following a DMM Flush Entry is Also Flushed X 15 NoFix Trace Buffer Does Not Operate Below 1 3 V 9 X 15 NoFix Data Cache Unit Can Stall for a Single Cycle 10 X 16 NoFix Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty T X 17 NoFix cer Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated vents 42 X 17 NoFix In Special Debug State Back to Back Memory Operations Where the First Instruction Aborts May Cause a Hang 13 X 18 NoFix Accesses to the CP15 ID register with opcode2 gt 0b001 returns unpredictable values 14 X 18 NoFix and re enabling the MMU can hang the core or cause it to execute the wrong 15 X 19 NoFix Updating the JTAG parallel register requires an extra TCK rising edge Specification Update intel Non Core Errata Intel 80219 General Purpose PCI Processor Summary Table of Changes Steppings No Page Status Errata A 0 1 X 20 NoFix The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when Using 32 Bit Memory ECC Enabled and in PCI Mode 2 X 20 NoFix PBI Issue When Using 16 bit PBI Transactions in PCI Mode X 21 NoFix MCU Pointers are Incorrect following a Restoration from a Power Fail 4 X 21 NoFix PMU Does Not Account for when the Arbiter Deasserts GNT One Cycle before FRAME 5 X 2 NoFix Lost Data During B
17. e can therefore determine whether they exist by reading both the main ID register and the desired register and comparing their values If the two values are not equal the desired register exists The Intel Xscale core does not implement any CP15 ID code registers other than the Main ID register opcode2 0b000 and the Cache Type register opcode2 0b001 When any of the unimplemented registers are accessed by software e g mre p15 0 r3 c15 c15 2 the value of the Main ID register should be returned Instead an unpredictable value is returned No workaround NoFix Disabling and re enabling the MMU can hang the core or cause it to execute the wrong code When the MMU is disabled via the CP15 control register CP15 CR1 opcode 2 0 bit 0 after being enabled certain timing cases can cause the processor to hang In addition to this re enabling the MMU after disabling it can cause the processor to fetch and execute code from the wrong physical address To avoid these issues the code sequence below needs to be used whenever disabling the MMU or re enabling it afterwards The following code sequence can be used to disable and or re enable the MMU safely The alignment of the mcr instruction that disables or re enables the MMU needs to be controlled carefully so that it resides in the first word of an instruction cache line The following code sequence takes r0 as a parameter The value of r0 is written to the CP15 contr
18. e to float the pads This is in violation of the JTAG specification specif ically the term immediately It is possible for TCK to stop after the HIGHZ instruction is loaded and thus the pads may never float Workaround Do not stop the JTAG clock TCK Status NoFix 14 Specification Update Problem Workaround Status f Problem Workaround Status 8 Problem Workaround Status 9 Problem Workaround Status Intel 80219 General Purpose PCI Processor Core Errata Incorrect Decode of Unindexed Mode Using Addressing Mode 5 Can Corrupt Protected Registers The instruction decoder incorrectly decodes the valid combination of P 0 U 1 and W 0 when using unindexed mode in addressing mode 5 load and store coprocessor In this case the LDC or STC should produce consecutive address loads or stores with no base update until the coprocessor signals that it has received enough data Instead the instruction gets separated into an LDR STR and a CP access The LDR STR gets decoded as a post index address updating the base register Due to the decoding as post index the option bits normally reserved for the coprocessor in unindexed mode become the 8 bit offset value used in the base register update calculation The implication is that protected registers can be corrupted This errata can cause the corruption of FIQ registers R13 R14 in user and system modes when the LDC ins
19. entation or specification changes as noted This table uses the following notations Codes Used in Summary Table Stepping X No mark or Blank box Page Page Status Doc PlanFix Fixed NoFix Row Specification Update Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page location of item in this document Document change or update will be implemented This erratum may be fixed in a future stepping of the product This erratum has been previously fixed There are no plans to fix this erratum Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document Intel 80219 General Purpose PCI Processor Summary Table of Changes Core Errata Steppings No Page Status Errata A 0 1 X 13 NoFix Boundary Scan Is Not Fully Compliant to the IEEE 1149 1 Specification 2 X 13 NoFix Drain Is Not Flushed Correctly when Stalled in the Pipeline 3 X 14 NoFix Undefined Data Processing like Instructions are Interpreted as an MSR Instruction 4 X 14 NoFix Debug Unit Synchronization with the TXRXCTRL Register 5 X 14 NoFix Extra Circuitry Is Not JTAG Boundary Scan Compliant I Incorrect Decode of Unindexed Mode Using Ad
20. form a single 32 bit wide data cycle Specification Update 27 Intel 80219 General Purpose PCI Processor Specification Clarifications n B Issue Example Status Issue Status 28 In order Delivery not guaranteed for data blocks described by a single DMA descriptor In order delivery is not guaranteed for data blocks described by a single DMA descriptor that crosses a 1 KB boundary This may result in out of order execution of the DMA transfer When multiple DMA descriptors are used the ordering is maintained with respect to the blocks described by each descriptor When ordering is important the ordering needs to be maintained by splitting the relevant pieces of data into multiple DMA descriptors A 100 byte DMA transfer described by a single descriptor with a source address of Ox3ff8 Since each DMA channel has two 1 KB buffers the DMA unit breaks this transaction at the 1 KB boundary Therefore the first buffer might fetch the 8 bytes from Ox3ff8 0x3fff and the second buffer might fetch the remaining 92 byes from 0x4000 0x405C Both buffers have the ability to access the internal bus without preference i e either buffer may gain access first Therefore it is possible the 92 bytes of data after the 1 KB boundary could be transferred to the destination before the first 8 bytes However the transaction is completed and all data has been copied to the correct address when the descriptor completes i e descriptors are
21. ge 7 8 The boundary scan cells of the Intel Xscale core bi directional pads do not capture the data driven from the on chip system logic to the pins when these pads are acting as outputs This would only be useful when trying to capture the data driven from the on chip logic during normal operation of the assembled board However the Intel Xscale core does not allow single stepping of its clocks Thus even when the Intel Xscale core did provide the compliant boundary scan cell it would be extremely difficult or impossible to synch the boundary scan logic with the state of the on chip logic Therefore this feature of the boundary scan cells is not useful This has NO effect on the ability to determine the integrity of the interconnections on boards which is what the Intel Xscale core boundary scan logic was designed to support No workaround NoFix Drain Is Not Flushed Correctly when Stalled in the Pipeline In a load followed by a drain scenario the load table walks and then gets a precise data abort The core fetches the address for the abort handler but in the same cycle does not flush the drain Not a functional problem but may effect performance No workaround NoFix Specification Update 13 Core Errata Intel 80219 General Purpose PCI Processor m tel INTtel d Undefined Data Processing like Instructions are Interpreted as an MSR Instruction Problem The instruction decode allows undefined opcodes which
22. luding indirect branches and those mispredicted by the BTB 4 CPI5 mcr instructions to registers 7 8 9 or 10 which involve the instruction cache or the instruction TLB Each of the items above may cause the performance monitoring count to increment several times The resulting performance monitoring count may be higher than expected when the above items occur but never lower There is no way to obtain the correct number of cycles stalled due to instruction cache misses and instruction TLB misses Extra counts due to branch instructions mispredicted by the BTB may be one component of the unwanted count that can be filtered out The number of mispredicted branches can also be monitored using performance monitoring event 0x6 during the same time period as event Ox1 The mispredicted branch number can then be subtracted from the instruction cache stall number generated by the performance monitor to get a value closer to the correct one Note that this only addresses counts contributed by branches that the BTB is able to predict All the items listed above still affect the count Depending on the nature of the code being monitored this workaround may have limited value NoFix In Special Debug State Back to Back Memory Operations Where the First Instruction Aborts May Cause a Hang When back to back memory operations occur in the Special Debug State SDS used by ICE and Debug vendors and the first memory operation gets a precise data abort
23. ly cleaned The original data from location A is evicted to external memory overwriting the data written by the external master This only happens when software is allowing an external master to modify memory that is writeback or write allocate in the page tables and depending on the fact that the data is not dirty in the cache to preclude the cached version from overwriting the external memory version When there are any semaphores or any other handshaking to prevent collisions on shared memory this should not be a problem For this shared memory region mark it as write through memory in the page table This prevents the data from ever being written out as dirty NoFix Specification Update intel 11 Problem Workaround Status 12 Problem Workaround Status Intel 80219 General Purpose PCI Processor Core Errata Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated Events Event 0x1 in the performance monitor unit PMU can be used to count cycles in which the instruction cache cannot deliver an instruction The only cycles counted should be those due to an instruction cache miss or an instruction TLB miss The following unrelated events in the core also causes the corresponding count to increment when event number 0x1 is being monitored 1 Any architectural event e g IRQ data abort 2 MSR instructions which alter the CPSR control bits 3 Some branch instructions inc
24. m Implication Workaround Status 7 Problem Implication Workaround Status 22 The MTTR1 Core Multi Transaction Timer is not ef MG due to improper behavior of the core internal bus request signal REQ The MTTRI Core Multi Transaction Timer is not operating due to improper behavior of the core internal bus request signal REO All agents on the bus except the core maintain their assertion on REQfF signals upon receiving a retry When the MCU is busy this means that the core must wait for other agents to complete their transactions before the core gains access to memory Due to the fact that internal bus agents initiate larger transactions than the core this issue results in an unbalanced access to the internal bus biased to these other agents DMA ATU etc When opera tional the MTTR1 is intended to correct this balance See Section 11 2 2 of the Intel 80219 General Purpose PCI Processor Developer s Manual for more information on the MTTRI function In the case of the MCU internal bus target this problem is compounded by the many internal bus retries that are issued by the MCU when under heavily loaded conditions The result is that the internal bus arbiter removes the core access to the bus when the core deasserts REQ This condition may result in the core being locked out of accessing the MCU until other internal bus agents have completed their transaction s i e when the DMA is in the process of a l
25. ndard 1149 1 specifies the boundary scan logic to support two main goals 1 To allow the interconnections between the various components to be tested test data can be shifted into all the boundary scan register cells associated with component output pins and loaded in parallel through the component interconnections into those cells associated with inputs pins and 2 Toallow the components on the board to be tested the boundary scan register can be used as a means of isolating on chip system logic from stimuli received from surrounding components while an internal self test is performed Alternatively when the boundary scan register is suitably designed it can permit a limited slow speed static test of the on chip system logic since it allows delivery of test data to the component and examination of the test results IEEE std 1149 1 1990 page 1 5 The Intel Xscale core does not support the second goal because it does not support the optional INTEST or RUBIST instructions The Intel Xscale core is not required to provide these instructions however since it doesn t this makes the following statement practically invalid The IEEE std 1149 1 description of the SAMPLE PRELOAD instruction states that When the SAMPLE PRELOAD instruction is selected the state of all signals flowing through system pins input or output shall be loaded into the boundary scan register on the rising edge of the TCK in the Capture DR controller state Pa
26. ol register to either enable or disable the MMU 19 unlock I TLB 09 invalidate I TLB mcr p15 0 r0 c10 c4 mcr pi5 0 r0 CB c5 mrc p15 0 TO c2 cO 0 CPWAIT mov r0 ro sub pc pc 4 b TE branch to aligned code align 5 ls mcr p15 0 TO cl c0 0G enable disable MMU caches mrc p15 0 TO c2 cO 00 CPWAIT mov rO rO sub pc pc 4 NoFix Specification Update Intel 80219 General Purpose PCI Processor I n m Core Errata 15 Updating the JTAG parallel register requires an extra TCK rising edge Problem IEEE 1149 1 states that the effects of updating all parallel JTAG registers should be seen on the falling edge of TCK in the Update DR state The Intel Xscale core parallel JTAG registers incorrectly require an extra TCK rising edge to make the update visible Therefore operations like hold reset JTAG break and vector traps require either an extra TCK cycle by going to Run Test Idle or by cycling through the state machine again in order to trigger the expected hardware behavior Workaround When the JTAG interface is polled continuously this erratum has no effect When not an extra TCK cycle can be caused by going to Run Test Idle after writing a parallel JTAG register Status NoFix Specification Update 19 Intel 80219 General Purpose PCI Processor Non Core Errata n a Non Core Errata Workaround Status 2 Problem Workaround Status 20 The ATU Returns Invalid
27. ontrol of the bus granted GNT by the bus arbiter The IDSEL signal is used as a chip select during configuration cycles initiated by the BIOS operating system or 80219 The GPOD 0 can be driven low in firmware thereby disabling the P BMI signal and hiding the host I O device from the system by turning off its IDSEL When the 80219 intends to perform configuration cycles in the PCI bus segment of the I O device the P BMI signal should be asserted high by driving the GPODIO high The affect of these two operations is that the I O device is initialized and controlled by the 80219 More care must be taken with the gate chosen to control IDSEL since most host bridge controllers do not use PCI address stepping With IDSEL being a synchronous signal with respect to CLK the switch used must be a sub nanosecond propagation delay device e g Pericom PI5C3303 In Figure 2 the P BMI signal is used to control a MUX DeMUX switch that is used to enable disable IDSEL to the I O device Specification Update Intel 80219 General Purpose PCI Processor I n is Specification Changes Note The host BIOS does not require any modifications to accommodate this implementation All the responsibility for I O device configuration and resource falls to the 80219 firmware Figure 2 Intel 80219 General Purpose PCI Processor P_BMI Signal Implementation for Intel 80219 General Purpose PCI Processor B 0 B 1 Stepping GPOD Register Controller
28. rameters Using SPD or hard coded firmware eliminates the need to do SDRAM sizing in the firmware rae Writes to Unaligned 64 bit Addresses are Promoted to 64 bit Aligned rites In 80219 based applications that run the PCI bus segment in 32 bit PCI Mode or 64 bit PCI Mode with 32 bit targets write transactions that are on unaligned 64 bit addresses are promoted to 64 bit aligned writes The first half of the 64 bit write is on a 64 bit aligned address and has the BE signals disabled Therefore the write is invalid The second half on the 64 bit write is a valid write with the BE enabled and the write is to the intended 32 bit address Per the PCI Local Bus Specification Revision 2 2 the PCI compliant devices should ignore the first half of the 64 bit write due to the BE signals being disabled For devices that support using the I O memory window the 64 bit write does not occur when using the 80219 ATU I O Window and the only expected 32 bit write occurs See section 3 2 2 2 of the Intel 80219 General Purpose PCI Processor Developer s Manual for details For memory mapped devices the only option is to run in PCI X mode where the byte count and starting address are consistent with the actual number of bytes to be written i e 4 This is so because when a 64 bit PCI X request gets downshifted the requester can use the starting address byte count to recognize that the write request does not cross a DWORD address boundary and only per
29. riptor 7 X 28 Doc Writing to reserved registers can cause unexpected behavior Documentation Changes No Document Revision Page Status Documentation Changes None for this revision of this specification update 10 Specification Update intel EE ldentification Information Markings Figure 1 Topside Markings Intel 80219 General Purpose PCI Processor Specification Update 11 Intel 80219 General Purpose PCI Processor Identification Information l n Die Details apr GJ Intel 80219 General Stepping Part Number e Voltage V Purpose PCI Processor Notes Specification Number SL Speed MHz A 0 FW80219M400 Q690 3 3 400 Samples A 0 FW80219M600 Q691 3 3 600 Samples A 0 FW80219M400 SL7CL 3 3 400 Production Material A 0 FW80219M600 SL7CM 3 3 600 Production Material Device ID Registers Processor Device ID ATU Device ID ATU Revision ID Device and Stepping CP15 Register0 opcode 2 0 ATUDID ATURID EA Device ID A 0 400 MHz 0x69052E20 0x031A 0x00 0x0927E013 A 0 600 MHz 0x69052E30 0x031B 0x00 0x0927F013 12 Specification Update intel Intel 80219 General Purpose PCI Processor Core Errata Core Errata 1 Problem Workaround Status 2 Problem Implication Workaround Status Boundary Scan Is Not Fully Compliant to the IEEE 1149 1 Specification The IEEE Sta
30. rpose PCI processor This signal replaces using an external GPIO pin for Initialization Device Select IDSEL control of an I O device during host configuration cycles I O Device IDSEL control using the new P BMI signal When the system boots after reset the host BIOS initiates a PCI bus scan to find all the PCI components installed in the system The system uses the IDSEL signal to address the I O device when assigning the necessary resources Without special control over the IDSEL signal during configuration cycles the host and the 80219 may both attempt to configure the same I O device By taking control of IDSEL the 80219 can execute configuration cycles to the slave I O device SCSI and properly hide the slave I O device from the host and operating system initiated configuration cycles The 80219 has eight integrated General Purpose Input Output GPIO pins referred to as GPIO 7 0 These pins along with the new PCI X Bus Master Indicator P BMI signal can be used to control the IDSEL to the I O device External circuitry is no longer required other than a simple switch The output function of the P BMI signal is controlled by the GPIO Output Data Register GPOD Bit 0 as shown in Table 1 The P BMI signal is always driven and defaults to driving low at power up GPIO Output Data Register address FFFF E7CCh Bit Default Description 0 0 This bit value is driven on the P BMI signal when the 80219 has been given c
31. se changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the specification Errata remain in the specification update throughout the product life cycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals etc 1l ARM architecture compliant Specification Update intel Intel 80219 General Purpose PCI Processor Summary Table of Changes Summary Table of Changes The following table indicates the errata specification changes specification clarifications or documentation changes which apply to the Intel 80219 General Purpose PCI Processor product Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through docum
32. truction is executed using unindexed addressing mode It can also cause the corruption of FIQ registers R8 R12 in any mode when the LDC instruction is executed using unindexed addressing The R13 register in debug mode may also be corrupted during an LDC in any mode In the case of STC only Rn is corrupted Unexpected memory accesses can also occur In the case of an LDC any memory location may be accessed since the FIQ registers may be improperly used as the base register In the case of an STC the memory word located at Rn 4 is corrupted This is the memory location immediately following the locations which should be modified by STC unindexed Do not use unindexed addressing in addressing mode 5 Load and Store Coprocessor NoFix Load Immediately Following a DMM Flush Entry is Also Flushed A load that immediately follows a data memory management DMM flush entry command that also hits the data TLB is also flushed Therefore the instruction immediately following the flush is also flushed from the data TLB All flush entry commands to the data TLB must be followed by two NOPs The first ensures the erratum is not encountered and the second ensures the speed path is not hit NoFix Trace Buffer Does Not Operate Below 1 3 V The trace buffer within the debug unit is not guaranteed to operate due to voltage sensitivity when the core voltage supply is below 1 3 V Make sure the voltage is above 1 3 V during debug NoFix
33. ure testing specified to be 0 C During cold temperature manufacturing testing 80219 silicon is subjected to a 0 C environment for an extended period of time During this time the Vih test is implemented and the junction temperature is at or near the test temperature of 0 C This junction temperature is considered to be far less than the temperature the 80219 silicon would be subjected to in a customer application under operating conditions Below is an example calculation showing the expected junction temperature for a customer application operating in an ambient temperature of 0 C Tj junctions temperature Ta ambient temperature qja junction to ambient thermal resistance of the package P 2 power at minimum Vcc Tj Ta gja P where Ta OC qja 13 94 C W assuming 200lfm airflow see Table 11 of the Intel 80219 General Purpose PCI Processor Datasheet P 3 0 W Tj 2 0 13 94 C W 3 0 C Tj 41 82 C The minimum Vih level for the PCI pins will be tested at the PCI Local Bus Specification Revision 2 2 specification 0 5 Vcc plus an additional 100 mV that equates to 1 6 V during cold temperature manufacturing testing NoFix Specification Update 23 Intel 80219 General Purpose PCI Processor Specification Changes n Specification Changes Issue Table 1 24 SUM NC2 was renamed to P BMI AE23 New function added to signal The P BMI AE23 signal has been added to the Intel 80219 general pu
34. ursts of Large Number of Partials with 32 bit ECC Memory 6 X 22 NoFix The MTTR1 Core Multi Transaction Timer is not operating due to improper behavior of the core internal bus request signal REQ X 22 NoFix The MCU supports a page size of 2 Kbytes for 64 bit mode 8 X 23 NoFix Vih Minimum Input High Voltage Vih level for the PCI pins Specification Update Intel 80219 General Purpose PCI Processor Summary Table of Changes Specification Changes Steppings No Page Specification Changes A 0 1 X 24 Signal NC2 was renamed to P BMI AE23 New function added to signal P BMI Specification Clarifications Steppings No Page Status Specification Clarifications A 0 The Intel 80219 general purpose PCI processor is compliant with the PCI Local Bus 1 X 26 NoFix Specification Revision 2 2 but it is not compliant with PCI Local Bus Specification Revision 2 3 Modifications to the Hot Debug procedure are necessary for the Intel 80219 general 2 X 26 NoFix purpose PCI processor when flat memory mapping is not used Virtual Address Physical Address 3 X 27 Doc BARO Configuration When Using the Messaging Unit MU 4 X 27 Doc Reading Unpopulated SDRAM Memory Banks 5 X 27 Doc 32 bit Writes to Unaligned 64 bit Addresses are Promoted to 64 bit Aligned Writes 6 X 28 Doc In order Delivery not guaranteed for data blocks described by a single DMA desc
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