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Fujitsu MB89950/950A Pager User Manual

1. Figure 1 5 2 MQP 64C P01 pin assignment orn oOroor OO ee rrrrre OooOOomo 00000 W W WU WU WU LL WU HU Uu Hl NNNNNNNSNNNNW TONTrT Oo ot OO st o Oo e aCoODnDDONNMNNMNNNMNWW WH SEG5 1 51 SEG18 SEG4 2 EE 50 SEG19 SEG3 3 29 See 49 P00 SEG20 SIm 0000000 See 1 1 47 SEGO 6 Ce Ti ap PO3 SEG23 COM3 7 GE Bol 4 P04 SEG24 COM2 8 Ego Se ed 44 P05 SEG25 oom 9 Gas oo 43 P06 SEG26 COMO 10 O g0 pO 42 P07 SEG27 va 11 PO oi aO A P10 SEG28 V2 P33 12 Oo ke 40 P11 SEG29 V1 P32 13 Oo o O 39 P12 SEG30 P31 14 i A i 38 P13 SEG31 P30 15 QOOQOOQOQOO 37 P14 SEG32 P40 16 1 S8888bR 36 P15 SEG33 P41 PWM 17 35 P16 SEG34 P42 PWC INT1 V en 34 P17 SEG35 P43 SI 19 TOP VIEW 33 P20 SEG36 RANKAARARASSS Fotos QBXOrTOQeh PBZAXX SES SSE S 5 1 3 W LU LU Lu Lu FLDXNDD Dous Oo NN ANNAN D 0000 Pin assignment on package top MB89PV950 only Pin no Pinname Pinno Pinname Pinno Pinname Pinno Pinname 65 N C 73 A2 81 N C 89 OE 66 Vpp 74 A1 82 04 90 N C 67 A127 5 AO 83 05 91A 11 68 A7 76 N C 84 Op 92 A9 69 A6 77 OI 85 O7 93 A8 70 A5 78 02 86 08 94 A13 71 A4 79 03 87 CE 95 A14 72 A3 80 Vss 88 A10 96 Vcc N C Internally connected Do not use CHAPTER 1 OVERVIEW 1 6 Package Dimensions Two types of packages are available for MB89950 950A series Figure 1 6 1 FPT 64P M09 package dimensions and Figure 1 6 2
2. SE lt l i PDR read ek S When Read modify write instruction executed re L P ch S 5 Output latch j J SIT pp ra a ae PDR write 1 SE eee ee a ee cee amp A A Pin Port data direction register DDR N ch P42 PWC INT1 DDR write E TIT Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC 146 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC E Pulse width count timer registers Figure 8 3 2 Pulse width count timer registers PCR1 PWC pulse width control register 1 Address Bit7 Pre BitS Bit4 Bits Bit2 Bit1 BitO Initial value 0014H EN IE UF IR BF 0 0 000B R W R W RW RW R PCR2 PWC pulse width control register 2 Address Bit7 Bit6 Bit5 Bit4 D Bit2 Biti Bito Initial value 0015H FC RM TO C1 co Wi WO 000 0000B R W R W R W R W R W R W R W RLBR PWC reload buffer register Address Bit7 Bit6 BitS Bit4 Bits Bit2 Biti BitO Initial value 0016H XXXXXXXXB R W R W R W R W R W R W R W R W For the interval timer function R R R R R R R R eiss For the pulse width measurement function NCCR Noise filter control register Address Bit7 Pre Bit5 Bit4 Bits P Biti BitO Initial value 0017H NCS1 NCSO 00B RW RW
3. e Condition code 2 register CCR Ki Register oo E file E it bg E IR lt IPLA Check H Comparator 5 FeMC 8L CPU Wake up from START 7 stop mode gt Wake up from sleep mode gt gt Exit watch mode 6 RAM 1 Initialize peripheral 5 4 5 SS 5 Enable FF g Is an interrupt AND 8 request present at the Request FF peripheral 2 3 Ki Peripherals Intern Gi Is interrupt request output enabled for the peripheral 3 YES Check the interrupt priority level and transfer the level to the CPU 5 Compare the level with l the IL bits in PS Le z l I Is the level e higher than IL i l YES 2 Main program Poi l flag 1 execution NO l l TE E E EE E E 4 NO Interrupt processing e EEEE Clear interrupt request i Save PC and PS to the stack 7 Restore PC and PS Execute interrupt processing 6 PC _ interrupt vector 7 7 RETI Update IL in PS 37 CHAPTER 3 CPU After a reset all interrupt requests are disabled Initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program set the interrupt levels in the appropriate interrupt level setting registers ILR1 ILR2 ILR3 and start peripheral function The interrupt level can be set to 1 2 or 3 Level is the highest
4. SR SR v2 V2 VLCD VLCD R v1 V1 R R MB89950 950A series MB89950 950A series 1 2 bias 1 3 bias ES Table 12 2 1 LCD drive voltages and biasing modes LCD drive voltages V2 1 2 bias 1 2VLCD 1 2VLCD 1 3 bias 2 3VLCD 1 3VLCD V1 to V3 Voltages at pins V1 to V3 VLCD LCD operating voltage 239 CHAPTER 12 LCD CONTROLLER DRIVER E Use of external voltage divider 240 Figure 12 2 6 External voltage divider connection shows an external voltage divider connection Figure 12 2 6 External voltage divider connection Vcc vs VR V3 V OOA RX R Ve v2 OO oi RX Vi _ KA EECH RX LCD enable _ Met d TIT MB89950 950A series V1 to V3 Voltages at V1 to V3 pins Note To preclude the external voltage divider from being affected by the internal voltage divider the LCD drive supply voltage control bit of LCD control register LCDR VSEL must be written to 0 to isolate it from the entire internal voltage divider Reference The resistance of RX in the external voltage divider depends on the LCD used Select an appropriate value CHAPTER 12 LCD CONTROLLER DRIVER 12 3 Structure of LCD Controller Driver This section describes the pins pin block diagrams registers and display RAM of the LCD controller driver E LCD controller d
5. R W Readable and writable R Read only Unused X Indeterminate Pulse width count timer interrupt source IRQ3 For both the interval timer and pulse width measurement function the PWC generates an interrupt request if interrupt request output is enabled PCR1 IE 1 when the counter value underflows Oly gt 00p For the pulse width measurement function the PWC generates an interrupt request for the pulse width measurement function if interrupt request output is enabled PCR1 IE 1 when pulse width measurement completes or a pulse width measurement value remains in the RLBR register 147 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 3 1 PWC Pulse Width Control Register 1 PCR1 The PWC pulse width control register 1 PCR1 is used to enable or disable functions control interrupts and check the state of the pulse width count timer E PWC pulse width control register 1 PCR1 Figure 8 3 3 PWC pulse width control register 1 PCR1 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0014H EN IE UF IR BF 0 0 000B R W R W R W R W R BF Buffer full flag bit D No pulse width measurement value 1 Pulse width measurement value IR Measurement completion interr
6. gt TDRE Transmission data register empty bit 0 Full of transmission data 1 Empty gt RDRF ORFE Receive data flag bit Error flag bit 0 0 No data Framing error 0 1 When new data is received at R W Readable and writable this state RDRF will not be set R Read only 1 0 Normal data Unused 1 1 Overrun error Previous data X Indeterminate remains Initial value 209 CHAPTER 10 UART Table 10 4 3 Serial status and data register SSD bits RDRF Receive data register full bit Function This flag represents the status of the serial input data register SIDR This flag is set when receiving data is loaded into the SIDR register It is cleared when the SIDR register is read If the RDRF bit is set when the RIE bit is 1 a receive interrupt request is generated ORFE Overrun Framing error flag bit This bit is set when overrun or framing error is generated during receiving If this flag is set data is not transferred from the receive shift register to SIDR register When the SIDR register is read after reading the SSD register with the ORFE flag set to 1 the ORFE flag is cleared to 0 If the ORFE bit is set when the RIE bit is 1 a receive interrupt request is generated TDRE Transmission data register empty bit This flag represents the status of the serial output data register SODR This flag
7. PDR read RN PDR read for bit manipulation instructions Output latch Internal data bus PDR write SPL Pin state specification bit in the standby control register STBC lt L e Stop mode SPL 1 Pin Stop mode SPL 1 gt 4 N ch E Port 0 register The port 0 register consists of PDRO Each bit in the register has a one to one relationship with a port 0 pin Table 4 2 2 Correspondence between pin and register for port 0 shows the correspondence between the pins and register for port 0 Table 4 2 2 Correspondence between pin and register for Port 0 Correspondence between register bit and pin PDRO Corresponding pin 73 CHAPTER 4 I O PORTS 4 2 1 Port 0 Data Register PDRO This section describes the port 0 data register E Port 0 data register functions Port 0 data register PDRO The PDRO register holds the pin states Therefore a bit corresponding to a pin set as an output port can be read as the same state 0 or 1 as the output latch but when it is an input port it cannot be read as the output latch state Reference For SETB and CLRB bit operation instructions since the state of output latch not the pin is read the output latch states of bits other than those being operated on are not changed Settings as an LCD segment driver output To use pins as LCD segm
8. CHAPTER 12 LCD CONTROLLER DRIVER LCD panel connections and display data example 1 2 duty ratio drive mode Figure 12 4 3 Segment common connections data states and corresponding display Example Using segments to represent 5 ANEA T SEGn LG SEGn 3 KI COM K SEGn 1 45 ED n F D q 7 N COMO SEGn 2 O Address COM3 COM2 COM1 COMO Address COM3 COM2 COM1 COMO mi bits bit2 bitt bito SEGn Gel Eet D El EES 1__ SEGO bit7 bit6 bits bit4 SEGn 1 1 0 SEG1 non bits bit2 pitt moi SEGn 2 Gen _ DE geg SEET 0 _ SEG2 bit7 bite bits DR SEGn 3 0 1__ SEG3 0 to 7 Indicate corresponding display RAM bits Bits 2 3 6 and S SE 7 are not used Rad o Ee E ale TAN dan nai o x LCD Bit States for Numerals 0 through 9 5 3 8 B 8 8 Display bit7 bite ms bit4 bits pl bit1 bito zt CH CH CH CH CH CH eit Titolo Py ils f fefs SH SS oio TIO oir SSC A iaee a 1 E ee es ee SSDS S Ag e e rit o o rin ir o s 1 o 1 1 A O 1 f i 1 i 1 S G d Uc el 2 0 CN 1 1 i ARP ECKE SECHS EE cee E Oj Oe l a EE 1 0 Shale e e as Gel ee a aa Olli le lily de dy tbe dp bed yp del hd OL H DI o 1 1 o z Be SOEN HE HR ee aa a ES oe oos ot
9. E Main clock oscillation stabilization delay time When first starting operation in main clock mode after a state in which the main clock oscillator is stopped a delay time is required for oscillation to stabilize This delay time starts when the timebase timer starts counting up from its cleared state and ends when the count overflows at the specified bit Oscillation stabilization delay time during operation A time length must be selected for the oscillation stabilization delay time when an external interrupt takes the system from stop mode back to run mode One of two possible delay times can be selected by mask option 55 CHAPTER 3 CPU 56 Oscillation stabilization delay time at reset The oscillation stabilization delay time at reset the initial values of WT1 and WTO is selected as an option setting Products with power on reset require an oscillation stabilization delay time when exit from stop mode is triggered by resets in power on reset or external reset Table 3 6 1 Main clock startup conditions vs oscillation stabilization delay time shows the relationships between the conditions in which main clock mode operation is started and oscillation stabilization delay time Table 3 6 1 Main clock startup conditions vs oscillation stabilization delay time Main clock mode startup conditions At power on Oscillation stabilization delay time selection Exit from stop mode External reset External
10. P24 SEG40 P24 N ch open drain I O SEG40 LCD segment driver output P25 SEG41 P25 N ch open drain I O SEG41 LCD segment driver output See Section 1 7 I O Pins and Pin Functions for a description of the circuit type 82 CHAPTER 4 I O PORTS E Block diagram of port 2 pins Figure 4 4 1 Block diagram of port 2 pins Mask option LCD segment driver output CG Segment driver output select register PDR Port data register lt C e Stop mode SPL 1 PDR read RN PDR read for bit manipulation instructions Output latch Internal data bus PDR write Stop mode SPL 1 gt 4 N ch SPL Pin state specification bit in the standby control register STBC E Port 2 register The port 2 register consists of PDR2 Each bit in the register has a one to one relationship with a port 2 pin Table 4 4 2 Correspondence between pin and register for port 2 shows the correspondence between the pins and register for port 2 Table 4 4 2 Correspondence between pin and register for port 2 Correspondence between register bit and pin PDR2 Bit7 Bit6 BitS Bit4 Bit3 Bit2 Bitl Bit 0 Port 2 Corresponding pin P25 P24 P23 P22 P21 P20 83 CHAPTER 4 I O PORTS 4 4 1 Port 2 Data Register PDR2 This section describes the port 2 data
11. Segment No COM3 COM2 COMI LCD Panel e eanes EE eel o EUREN ene enc OR cee ete EHS SOUEEN SOUEEN 2 2 UR EA ene OR E ee EES a hes oO Be oR o Re o Bel i oR i oR o Bel oma aa fee AE l fe Bee BR oR i o Ri ol Bel l o Bey A ER ao ee El ol E ol E li ER Oo Ree o Bel i oni SEGO SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 D DD DD DD D D DE DE EA EG EG EG 9 ES EG BE o E Data in unit starting at bit 4 Data in unit starting at bit O In 1 3 duty ratio operation to be able to define two digits in three bytes the data stored in two bytes with the first byte starting at bit 0 and second byte starting at bit 4 CHAPTER 12 LCD CONTROLLER DRIVER 12 4 3 Output Waveforms during LCD Controller Driver Operation 1 4 Duty Ratio In the 1 4 duty ratio mode all four common outputs COM0 COM1 COM2 and COM3 are used E 1 3 bias 1 4 duty output waveforms The maximum potential difference exists between a segment output and the corresponding common output when the segment LCD cell is turned on Figure 12 4 6 Output waveforms 1 3 bias and 1 4 duty ratio example shows the output waveforms for the display RAM contents listed in Table 12
12. 4 Oscillation stabilization delay overflow 0000H Cleared by going to stop mode CPU operation starts Interval cycle TBTC TBC1 TBCO ie Power on reset 1 i optional Cleared by the interrupt processing routine i clear TBTC TBR 0 gt TBIF bit TBIE bit Sleep mode R SLP bit STBC register Wake up from sleep mode by IRQ6 Stop mode a STP bit 7 7 STBC register Wake up from stop mode by an external interrupt For the case when the interval time selection bits in the timebase timer control register TBTC TBC1 TBCO are set to 11g 22 Fcx Indicates the oscillation stabilization delay time CHAPTER 5 TIMEBASE TIMER 5 6 Notes on Using Timebase Timer This section lists points to note when using the timebase timer E Notes on using timebase timer Notes on setting bits by program The system cannot recover from interrupt processing if the overflow interrupt request flag bit TBTC TBIF is 1 and the interrupt request enable bit is enabled TBTC TBIE 1 Always clear the TBIF bit Clearing timebase timer In addition to being cleared by the timebase timer initialization bit TBTC TBR 0 the timer is cleared whenever the main clock oscillation stabilization delay time is required When the timebase timer is selected as a count clock of
13. Activating watchdog timer The watchdog timer is activated by writing 0101p to the watchdog control bits in the watchdog control register WDTC WTE3 to WTEO for the first time after a reset Once activated the watchdog timer cannot be stopped other than by a reset Clearing watchdog timer The watchdog timer counter is cleared by writing 0101p to the watchdog control bits in the watchdog control register WDTC WTE3 to WTEO for the second or subsequent times after a reset If the counter is not cleared within the interval time of the watchdog timer the counter overflows and the watchdog timer generates an internal reset signal for four instruction cycles Interval time of watchdog timer The interval time changes depending on when the watchdog timer is cleared Figure 6 4 1 Watchdog timer clear and interval time shows the relationship between the watchdog timer clear timing and the interval time The indicated times apply if the timebase timer output is selected as the count clock and the main clock oscillation frequency is 5 MHz CHAPTER 6 WATCHDOG TIMER Figure 6 4 1 Watchdog timer clear and interval time Minimum time Maximum time 419 43 ms Count clock output of rn the timebase timer Watchdog clear Overflow 1 bit watchdog a 4 counter Watchdog reset 838 86 ms Count clock output of the timebase timer Watchdog clear
14. l General purpose l registers i 0200H 0280H 4 Recommended set value for SP Stack area When the top address of RAM is 0280n Access prohibited ROM FFFFH Note The stack area is used in the downward direction starting from a high address by functions such as interrupts subroutine calls and the PUSHW instruction Instructions such as return instructions RETI RET and the POPW instruction release stack area in the upward direction Take care when the stack address is decreased by multiple interrupts or subroutine calls that the stack does not overlap the general purpose register area or areas containing other data 42 CHAPTER 3 CPU 3 5 Resets The MB89950 950A series supports the following four types of reset source e External reset e Software reset e Watchdog reset e Power on reset optional At reset main clock oscillation stabilization delay time may or may not occur by the operating mode and option settings E Reset source Table 3 5 1 Reset source Reset source Reset condition External reset Set the external reset pin to the L level Software reset Write 0 to the software reset bit in the standby control register STBC RST Watchdog reset Watchdog timer overflow Power on reset Power is turned on only on products with a power on reset External reset Inputting an L level to the external reset pin RST generates an external rese
15. Temporary accumulator 8 or 16 bits which are determined depending on the instruction being used Higher 8 bits of the temporary accumulator 8 bits Lower 8 bits of the temporary accumulator 8 bits Index register 16 bits Extra pointer 16 bits Program counter 16 bits Stack pointer 16 bits Program status 16 bits Either accumulator or index register 16 bits Condition code register 8 bits Register bank pointer 5 bits General purpose register 8 bits i 0 to 7 X is immediate data 8 or 16 bits which are determined depending on the instruction being used The content of X is to be accessed 8 or 16 bits which are determined depending on the instruction being used The address indicated by the X is to be accessed 8 or 16 bits which are determined depending on the instruction being used 268 B 2 Addressing APPENDIX B Overview of Instructions The F2MC 8L has the following ten addressing modes Direct addressing Extended addressing Bit direct addressing Index addressing Pointer addressing General purpose register addressing Immediate addressing Vector addressing Relative addressing Inherent addressing E Explanation of addressing Direct addressing Direct addressing is indicated by dir in the instruction list This addressing is used to access the area between 0000y and OOFF In this addressing mode the higher b
16. When the output pin control bit OE is 0 the pin If the PWM compare register COMR value is modified during coun operates as a general purpose UO port P41 er operation the new value will be effective in next cycle 132 CHAPTER 7 8 BIT PWM TIMER Note Do not change the count clock cycle CNTR P1 PO during operation of the interval timer function CNTR TPE 1 References Setting the COMR register value to 00 causes the PWM pin output to be inverted with the cycle of the selected count clock When the counter is stopped CNTR TPE 0 while the interval timer function is selected the PWM pin outputs an L level 133 CHAPTER 7 8 BIT PWM TIMER 7 6 Operation of PWM Timer Function This section describes the operation of the PWM timer function of the 8 bit PWM timer E Operation of PWM timer function Figure 7 6 1 PWM timer function settings shows the settings required to operate as the PWM timer function Figure 7 6 1 PWM timer function settings Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O CNTR P TX P1 PO TPE TIR OE TIE 1 1 Xx 4 x Used bit X Unused bit COMR Sets H width of pulse compare value 1 Set 1 On activation the counter starts to count up from 004 on the rising edge of the selected count clock The PWM pin PWM outputs PWM waveform an H level until the counter value matches th
17. 88 CHAPTER 4 I O PORTS 4 5 1 Port 3 Data Register PDR3 This section describes the port 3 data register E Port 3 data register functions Port 3 data register PDR3 The PDR3 register holds the pin states Therefore a bit corresponding to a pin set as an output port can be read as the same state 0 or 1 as the output latch but when it is an input port it cannot be read as the output latch state Reference For SETB and CLRB bit operation instructions since the state of output latch not the pin is read the output latch states of bits other than those being operated on are not changed Settings as an bias input V1 and V2 The PSEL bit in the LCD control register must be cleared to 0 in order to select P32 and P33 as LCD controller bias voltage input When LCD bias voltage input is selected by using the PSEL bit in the LCD control register these ports can be used as LCD bias voltage input only Table 4 5 3 Port 3 data register function lists the functions of the port 3 data register Table 4 5 3 Port 3 data register function Register Address Initial value Outputs an L level to the pin Sets 0 to the output latch and turn the output transistor ON Pin state is the L level Port 3 data register PDR3 Sets the pin to the high Pin state is the impedance state H level Sets 1 to the output latch and turn the output transistor OFF R W Rea
18. 05H to 07H Vacancy 08H Standby control register 0001 p 094 Watchdog timer control register XXXXp OAH Timebase timer control register 00000g 0By Vacancy OCH Port 3 data register soli tly 0Dy Vacancy Ou Port 4 data register XXXXXXXp OF y Port 4 direction register 0000000p 10H to lly Vacancy 124 PWM timer control register 0 000000g PWM timer compare register XXXXXXXXB PWC pulse width control register 1 0 0 000g PWC pulse width control register 2 000 0000g PWC reload buffer register XXXXXXXXp 174 PWC noise filter control register 18H to 1By Vacancy 1Cy 264 Serial mode register 00000000R Table A 1 I O map 2 2 Address Register name Register description Read Write Initial value Serial data register APPENDIX A I O Map XXXXXXXXp 1Fy Vacancy 201 SMC1 UART serial mode control register 1 00000 00p 21H SRC UART serial rate control register 011000g 224 SSD UART serial status data register 00100 1Xp 23H SIDR SODR UART serial data register XXXXXXXXB 24H SMC2 UART serial mode control register 2 1 0 00g 25H to 2Fy Vacancy 304 External interrupt control register 00000000 314 to 63H Vacancy 64H to 78H LCD data RAM XX
19. 1 and UART SIO selection bit SMC2 RSEL 1 automatically sets the P45 SCK pin as an output pin regardless of the port data direction register DDR4 bit 5 value and sets the pin to function as the SCK output pin In this case always select internal shift clock operation SMR CKS1 CKSO other than 11g 173 CHAPTER 9 8 BIT SERIAL I O E Block diagram of 8 bit serial I O pins Figure 9 3 1 Block diagram of 8 bit serial I O pin For P43 SI and P45 SCK PDR Port data register Ce mode SPL 1 Apprek SSC N Mask option PDR read bye SE E ee P44 SO SIO output i i i it 1 P45 SCK 2 N iy SIO PDR read d output enable P ch s hen Read modify write instruction executed bi i a E a GA g g Output latch T aD B P ch PDR write gj Le EE t e Pin Port data direction register DDR d SE DDR write F SEsh EE e Ss Wee Ee 7 7 Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC Reference Pins with a pull up resistor go to the H level pull up state rather than to the high impedance state when the output transistor is turned OFF E 8 bit serial I O registers Figure 9 3 2 8 bit serial I O registers SMR Serial mode register Address Bit7 Bit6 Bit5 Bit4 D D Bit1 Bit 0 Initial value 00
20. A lt AL V d8 74 282 OR A dir A lt AL V dir 75 Table B 5 2 Arithmetic operation instructions Continued MNEMONIC OR A EP Operation A lt AL V EP APPENDIX B Overview of Instructions OP CODE 77 OR A IX off A lt AL V IX off 76 OR A Ri A lt AL V Ri 78 to 7F CMP dir d8 dir d8 95 CMP EP d8 CEP d8 97 CMP IX off d8 IX off d8 96 CMP Ri d8 Ri d8 98 to 9F INCW SP SP lt SP 1 Cl DECW SP SP lt SP 1 D1 283 APPENDIX E Branch instructions Table B 5 3 Branch instructions No MNEMONIC Operation TL TH AH N z V C JOP CODE BZ BEQ rel if Z 1 then PC lt PC rel FD BNZ BNE rel if Z 0 then PC lt PC rel FC BC BLO rel if C 1 then PC lt PC rel F9 BNC BHS rel if C 0 then PC lt PC rel F8 BN rel if N 1 then PC lt PC rel FB BP rel if N 0 then PC lt PC rel FA BLT rel if V y N 1 then PC lt PC rel E BGE rel if V v N 0 then PC lt PC rel i BBC dir b rel if dir b 0 then PC lt PC rel BO to B7 BBS dir b rel if dir b 1 then PC lt PC rel B8 to BF JMP A PC lt A EO JMP ext PC lt ext 21 CALLV vct vector call E8 to EF CALL ext subroutine call 31 XCHW A PC PC lt A A lt PC 1 F4 RET re
21. Baud rate bps 4 912 MHz 5 MHz Input clock Division ratio 1 4 1 4 PDS division 1 64 1 8 CS1 CSO CR division Furthermore Figure 10 1 1 Sample calculation of the baud rate shows the formula of calculating the baud rate Figure 10 1 1 Sample calculation of the baud rate CPU cloc k Baud rate value E x Input clock divider x Transfer clock divider y Baud rate divider PDS1 PDSO CR CS1 CSO RC2 RC1 RCO FcH Main clock oscillation frequency 196 CHAPTER 10 UART Table 10 1 5 Transfer cycle and transfer rate by external clocks Asynchronous transfer mode Synchronous transfer mode Transfer Transfer rate Selected baud Transfer Transfer rate cycle baud 1 Selected baud rate division value rate division z value cycle baud 39062 or less 8 Foy or more 625k or less 9765 or less Foy Main clock oscillation frequency 1 Min external clock cycle of 8 Foy 0 16 us for Foy set at 5 MHz Figure 10 1 2 Sample calculation of the baud rate external clock is selected External clock input FCH 2 4 min CR 0 16 CR RR Baud rate value FcH Main clock oscillation frequency 197 CHAPTER 10 UART Table 10 1 6 Transfer cycle and transfer rate by 8 bit PWM timers Asynchronous transfer mode Synchronous transfer mode PWM timer count
22. E Block diagram of port 3 pins Figure 4 5 1 Block diagram of port 3 pins P30 and P31 PDR Port data register l p Stop mode SPL 1 gei PDR read o E m s N PDR read for bit manipulation instructions Output latch 1 PDR write Se Gee 2 i a b Pin Stop mode SPL 1 D gt H Sek SPL Pin state specification bit in the standby control register STBC GO Figure 4 5 2 Block diagram of port 3 pins P32 V1 and P33 V2 PSEL bit of LCDR register 1 N INZ V1 or V2 PDR Port data register ion 3 EA O O E E EE Stop mode SPL 1 Cl E PDR read m i 2 m s N PDR read for bit manipulation instructions F Output latch i PDR write bac Re oSm oa e aonn ee A Pin Stop mode SPL 1 D N ch SPL Pin state specification bit in the standby control register STBC 777 87 CHAPTER 4 I O PORTS E Port 3 register The port 3 register consists of PDR3 Each bit in the register has a one to one relationship with a port 3 pin Table 4 5 2 Correspondence between pin and register for port 3 shows the correspondence between the pins and register for port 3 Table 4 5 2 Correspondence between pin and register for port 3 Correspondence between register bit and pin PDR3 Corresponding pin
23. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM25 10146 1E F MC 8L 8 BIT MICROCONTROLLER MB89950 950A Series HARDWARE MANUAL co FUJITSU F MC 8L 8 BIT MICROCONTROLLER MB89950 950A Series HARDWARE MANUAL FUJITSU LIMITED PREFACE E Objectives and Intended Reader The MB89950 950A series has been developed as a general purpose version of the F MC 8L family consisting of proprietary 8 bit single chip microcontrollers The MB89950 950A series is applicable to a wide range of applications from consumer products to industrial equipment including portable devices This manual describes the functions and operation of the MB89950 950A series and is aimed at engineers using the MB89950 950A series of microcontrollers to develop actual products See the F MC 8L MB89600 Series Programming Manual for details on the MB89950 950A instruction set E Trademarks FMC is the abbreviation of FUJITSU Flexible Microcontroller Other system and product names in this manual are trademarks of respective companies or organizations The symbols TM and are sometimes omitted in this manual E Structure of This Manual This manual contains the following 12 chapters CHAPTER 1 OVERVIEW This chapter describes the main features and basic specifications of the MB89950 950A series CHAPTER 2 HANDLING DEVICE This chapter describes points to note when using the general purpose single chip microcontroller CHAPTER 3 CPU This chapter de
24. In stop mode serial I O operation and transfer stop as shown in Figure 9 7 2 Operation in stop mode halt internal shift clock As operation restarts after wake up from stop mode initialize the 8 bit serial I O depending on the state of the device with the 8 bit serial I O is communicating Figure 9 7 2 Operation in stop mode halt internal shift clock SCK au Sl a Ee Oscillation stabilization sstbit ff EE Idelay time Stop request i i 1 i i Cleared by the program SIOF bt e a d j food L Interrupt request NZ Ap NZ ele Ach NL aua N I HA Ne i N A6 SH SO pin output _ DGX XRX 5 enger EA Stop mode STP bit STBC register Wake up from stop mode by an external interrupt Operation during halt Halting operation during transfer SMR SST 0 halts the transfer and clears the shift clock counter as shown in Figure 9 7 3 Operation during halt internal shift clock Therefore the device being communicated with must also be initialized In serial output operation set data to the SDR register again before reactivating 185 CHAPTER 9 8 BIT SERIAL I O Figure 9 7 3 Operation during halt internal shift clock Seek EE EE aal gor 4 SST bit 1 1 1 d EE ap Operation reactivates Reset SDR register i SIOF bit s T SO pin output _ HOH E 5 San su DK E Using external shift clock 186 Operation in sleep mode In sleep mode
25. PULSE WIDTH COUNT TIMER PWC This chapter describes the functions and operation of the pulse width count timer PWC 8 1 Overview of Pulse Width Count Timer 8 2 Block Diagram of Pulse Width Count Timer 8 3 Structure of Pulse Width Count Timer 8 4 Pulse Width Count Timer Interrupts 8 5 Operation of Interval Timer Function 8 6 Operation of Pulse Width Measurement Function 8 7 Operation of Noise Filter Circuit 8 8 States in Each Mode during Pulse Width Count Timer Operation 8 9 Notes on Using Pulse Width Count Timer 8 10 Program Example for Timer Function of Pulse Width Count Timer 141 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 1 Overview of Pulse Width Count Timer The pulse width count timer PWC can be selected to function as either an interval timer or the pulse width measurement The interval timer function counts down in synchronous with one of three internal count clocks The pulse width measurement function measures the width of pulses input to an external pin Therefore the PWC can be used as an input capture by continuously measuring the pulse width of an external input E Interval timer function The interval timer function generates repeated interrupts at variable time intervals e The interval timer can operate with a cycle among 1 and 25 times the internal count clock cycle e The internal count clock can be selected from three different clocks e Two operating modes are available
26. Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Foy main clock oscillation frequency Note Initial value is 1 at each bit 292 Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller D 2 Programming Yield and Erasure This section describes the programming yield and the data erasure on EPROM microcomputer E Programming yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer due to its nature For this reason a programming yield of 100 cannot be assured at all times E Notes on using and data erasure on EPROM microcomputer Erasure In order to clear all locations of thei
27. es Watchdog timer counter e Reset controller e Counter clear controller es Watchdog timer control register WDTC E Block diagram of watchdog timer Figure 6 2 1 Block diagram of watchdog timer WDTC register WTE3 WTE2 WTE1 WTEO Watchdog timer Clear Start 221 FcH Overflow R Timebase timer output T 7 2 bit counter ka Reset controller gt RST Clear signal from timebase timer gt Sleep mode start Counter clear Stop mode start controller FcH Main clock oscillation frequency Watchdog timer counter 2 bit counter A 2 bit counter that uses the timebase timer output as a count clock Reset controller Generates a reset signal to the CPU when an overflow occurs on the watchdog timer counter Counter clear controller Controls clearing and halting the operation of watchdog timer counter 113 CHAPTER 6 WATCHDOG TIMER WDTC register The WDTC register is used to select the count clock and to activate or clear the watchdog timer counter As the register is write only the bit manipulation instructions cannot be used 114 CHAPTER 6 WATCHDOG TIMER 6 3 Watchdog Timer Control Register WDTC The watchdog timer control register WDTC is used to activate or clear the watchdog timer E Watchdog timer control register WDTC Figure 6 3 1 Watchdog time
28. 00H interrupt request flag bit BF EQU PCR1 0 Define the buffer full flag ILR1 EQU 007CH Address of the interrupt level setting register 1 INT_V DSEG ABS DATA SEGMENT ORG OFFF4H IRQ3 DW WARI Set interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB EN Stop counter operation CLRB IE Disable interrupt request output CLRB BF Clear buffer full flag PCR1 bit 0 MOV ILR1 0111111B Set interrupt level level 1 MOV RLBR 075H Counter reload value interval time MOV PCR2 01101000B Select interval timer function one shot timer mode initial output value of the TO and 32 tinst MOV PCR1 10100000B Start counter operation enable interrupt request output clear underflow 01H 00H interrupt request flag clear measurement complete interrupt request flag bit 1 SETI Enable interrupts Interrupt processing routine WARI CLRB UF Clear interrupt request flag PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END 168 CHAPTER 9 8 BIT SERIAL I O This chapter describes the functions and operation of the 8 bit serial I O 9 1 Overview of 8 bit Serial I O 9 2 Block Diagram of 8 bit Serial I O 9 3 Structure of 8 bit Seria
29. 1 Note When using the pulse width measurement function FC 1 set the P42 PWC INT1 pin as an input port RM Reload mode selection bit For the interval timer function This bit selects reload timer mode RM 0 or one shot timer mode RM 1 For the pulse width measurement function This bit has no meaning TO Timer output bit The value of this bit is inverted each time a counter value underflow 01 gt 004 occurs By counting the number of times this bit is inverted number of underflow Oly gt 00p occurs pulse widths longer than 28 x the cycle of the selected count clock can be measured Unused bit The read value is indeterminate Writing to this bit has no effect on the operation C1 CO Count clock selection bits These bits select the count clock for the interval timer function and pulse width measurement function Three internal count clocks can be selected Note Do not set 11 to C1 and CO bits W1 WO Measured pulse selection bits For the pulse width measurement function These bits select which pulse edges to use as the start and end conditions for pulse measurement Four types of pulse width or cycle can be selected For the interval timer function These bits have no meaning Note Do not modify the PCR2 register while the counter is operating PCR1 EN 1 151 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 3 3 PWC Reload
30. 1 In the receive mode only the stop bit of length 1 is valid and the second bit received is always ignored 194 E Selection of transfer clocks CHAPTER 10 UART The transfer clock can selected from the external clock SCK pin PWM timer or dedicated baud rate generator by setting CSO and CS1 bits of serial rate control register SRC In addition the CR bit of SRC and SMDE bit of serial mode control register 1 SMC1 can determine which divider for the selected transfer clock Please refer to Table 10 1 2 Clock ratio Table 10 1 2 Clock ratio Clock input External clock Asynchronous Synchronous PWM timer generator Dedicated baud rate When using the dedicated baud rate generator the input clock of the baud rate generator is selected by PDS1 and PDSO bits of serial mode control register 2 SMC2 The ratio of dividing frequency is shown in Table 10 1 3 Dividing frequency of dedicated baud rate generator Table 10 1 3 Dividing frequency of dedicated baud rate generator Dividing frequency Input clock 0 0 1 4 CPU operating clock 0 1 1 6 CPU operating clock 1 0 1 13 CPU operating clock 1 1 1 65 CPU operating clock CHAPTER 10 UART Table 10 1 4 Transfer cycle and transfer rate by baud rate generator is shown the example of baud rate when using the dedicated baud rate generator Table 10 1 4 Transfer cycle and transfer rate by baud rate generator
31. 1 ON LCD Bit States for Numerals 0 through 9 Display pit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Address COMO Display RAM LD LC D Di 7 E CH SEGO SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 Segment No COM3 COM2 COM1 e XK LCD Panel ry z F Z S S F CH S 259 CHAPTER 12 LCD CONTROLLER DRIVER 12 5 Program Example for LCD Controller Driver This section gives a program example for LCD controller driver E Program example for LCD controller driver Processing description The process writes LCD data to display RAM The data is that required to display the numbers 0 through 9 in an LCD panel connected as shown in Figure 12 4 7 Segment common connections data states and corresponding display The settings are as follows 260 Internal voltage divider is selected LCDR VSEL 1 1 3 bias and 1 4 duty ratio are used The main clock oscillation frequency is 5 MHz The frame frequency is set at 76 Hz LCDR FP1 FPO lei CHAPTER 12 LCD CONTROLLER DRIVER Coding example LCRAM EQU Starting address of LCD display RAM LCDR EQU Address of LCD control register LCDR SEGR EQU Address of segment output select register SEGR LCD
32. 1 3 Differences among Products 1 4 Block Diagram of MB89950 950A Series 1 5 Pin Assignment 1 6 Package Dimensions 1 7 I O Pins and Pin Functions CHAPTER 1 OVERVIEW 1 1 MB89950 950A Series Features The MB89950 950A series is a line of the general purpose single chip microcontrollers In addition to a compact instruction set the microcontrollers contain a variety of peripheral functions such as an LCD controller driver UART a serial I O PWC timer PWM timer and external interrupts E MB89950 950A series features Various package options e QFP packages 0 65 mm lead pitch for MB8995 1 A MB89953A MB89P955 only High speed processing at low voltage Minimum execution time 0 8 us 5 MHz F MC 8L family CPU core Instruction set optimized for controllers e Multiplication and division instructions e 16 bit arithmetic operations e Test and branch instructions e Bit manipulation instructions etc Single clock control system e Main clock max 5 MHz Four types of timer e 21 bit timebase timer e Watchdog timer e 8 bit PWM timer also can be used as an interval timer es 8 bit PWC timer Two types of serial interface es UART 5 7 8 bits transfer data length es Serial I O LCD controller driver e 42 segments x 4 commons max 168 pixels e Built in LCD voltage divider CHAPTER 1 OVERVIEW External interrupts 2 channels e Two channels are independent and capable of w
33. 26 21 ms 2 FcH 219 Fcy approx 104 86 ms 2 l Fcy approx 419 43 ms Foy Main clock oscillation frequency 100 E Clock supply function CHAPTER 5 TIMEBASE TIMER The clock supply function provides the timer output used for the main clock oscillation stabilization delay time two values and operation clock for some peripheral functions Table 5 1 2 Clocks supplied by timebase timer lists the cycles of the clocks that the timebase timer supplies to various peripherals Table 5 1 2 Clocks supplied by timebase timer Clock destination Main clock oscillation stabilization delay time Clock cycle 214 Fcp approx 3 28 ms 218 Fcy approx 52 43 ms Remarks Selected by mask option Noise filter circuit in PWC timer Foy approx 0 8 us 25 FcH approx 6 4 us Foy approx 25 6 us Select by noise filter control register Watchdog timer 27 Foy approx 419 43 ms Count up clock for the watchdog timer LCD controller driver Foy approx 12 8 us Foy Main clock oscillation frequency Frame cycle clock The values enclosed in parentheses are for a 5 MHz main clock oscillation frequency Reference The oscillation stabilization delay time should be used as a guide line since the oscillation cycle is unstable immediately after oscillation starts 101 CHAPTER 5 TIMEBASE TIMER 5 2 Block Diagram of Timebase Timer The timeb
34. CHAPTER 3 CPU MB89951A 0000H 1 0 0080H Reserved 00C0H 0100H 0140H Access prohibited FOOOH Registers FFCOH FFFFH MB89953A 0000H UO 0080H RAM O100H 4 Registers 0180H Access prohibited E000n ROM FFCOH FFFFH 0000H 0080H 0100H 0200H 0280H C000H FFCOH FFFFH MB89P955 1 0 Access prohibited 0000H 0080H 0100H 0200H 0480H 8000H FFCOH FFF MB89PV950 UO Access prohibited Vector table reset interrupt vector call instruction 23 CHAPTER 3 CPU 3 1 1 Special Areas In addition to the I O area the special purpose areas in the memory space include the general purpose register area and the vector table area E General purpose register areas addresses 0100 to 01FF 24 e Provides auxiliary registers for 8 bit arithmetic operation and transfer instructions e Allocated to a region of the RAM area Can also be used as normal RAM e Using the area as general purpose registers enables high speed access by general purpose register addressing using short instructions Table 3 1 1 General purpose register areas lists the areas in each device that can be used for general purpose registers Table 3 1 1 General purpose register areas MB89951A MB89953A MB89P955 PV950 8 16 32 Number of banks Address range
35. Instruction execution interrupts resets and similar update the contents of the program counter The initial value during a reset is the read address of the mode data FFFDy Accumulator A The accumulator is a 16 bit arithmetic operation register The accumulator is used to perform arithmetic operations and data transfers with data in memory or in other registers such as the temporary accumulator T The content of the accumulator can be treated as either word 16 bit or byte 8 bit data Only the lower 8 bits AL of the accumulator are used for byte arithmetic operations or transfers In this case the upper 8 bits AH remain unchanged The content of the accumulator after a reset is indeterminate 27 CHAPTER 3 CPU 28 Temporary accumulator T The temporary accumulator is an auxiliary 16 bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator A The content of the temporary accumulator is treated as word data 16 bit for word length arithmetic operations with the accumulator and as byte data 8 bit for byte length arithmetic operations For byte length arithmetic operations only the lower 8 bits of the temporary accumulator TL are used and the upper 8 bits TH are not used Executing a transfer instruction to transfer data to the accumulator A automatically transfer the previous content of the accumulator to the temporary accumulator In this case also a byte transfe
36. PWC 8 8 States in Each Mode during Pulse Width Count Timer Operation This section describes the operation of the pulse width count timer when the device goes to sleep or stop mode or an operation halt request occurs during operation E Operation during standby mode or operation halt Figure 8 8 1 Counter operation during standby mode or operation halt shows the counter value state when the device goes to sleep or stop mode or an operation halt request occurs during operation of the interval timer function or pulse width measurement function The counter halts and maintains its current value when the device goes to stop mode Operation starts again from the stored counter value after wake up from stop mode by an external interrupt Therefore the first interval time or pulse width measurement is not correct value Always initialize the pulse width count timer after wake up from stop mode Figure 8 8 1 Counter operation during standby mode or operation halt Counter value RLBR value FFH gt ER ge e e re ne PR esta ee Ee RY IS te ge SR 80H 00H F gt K H 3 Ime Timer cycle g Stop request e i Oscillation stabilization delay time 1 lt gt Interval time after wake up from stop mode indeterminate UF bit 1 Jk Operation halts Cleared by i A the program EN bit Operation restarts i Sleep mode IE b
37. Readable and writable Unused Initial value 246 CHAPTER 12 LCD CONTROLLER DRIVER Table 12 3 2 Segment output select register bit functions Function Bit 7 Unused bit e The read value is indeterminate e Writing to this bit has no effect on the operation Bit 6 SEGI5 e Selects P24 SEG40 to P25 SEG41 to function either as N ch open drain I O ports Segment output P24 to P25 or as LCD segment outputs SEG40 to SEG41 selection bit Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 5 SEG14 e Selects P20 SEG36 to P23 SEG39 to function either as N ch open drain I O ports Segment output P20 to P23 or as LCD segment outputs SEG36 to SEG39 selection bit Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 4 SEG13 e Selects P17 SEG35 to function either as N ch open drain I O port P17 or as LCD Segment output segment output SEG35 selection bit Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 3 SEG12 e Selects P16 SEG34 to function either as N ch open drain I O port P16 or as LCD Segment output segment output SEG34 selection bit Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 2 SEG11 e Selects P14 SEG32 to P15 SEG33 to functio
38. d8 IX off lt d8 86 MOV EP d8 EP lt d8 87 MOV Ri d8 Ri lt d8 88 to 8F MOVW dir A dir lt AH dir 1 lt AL D5 MOVW IX off A IX off lt AH IX off 1 lt AL D6 MOVW ext A ext lt AH ext 1 lt AL D4 MOVW EP A CEP lt AH EP 1 lt AL D7 MOVW EP A EP lt A E3 MOVW A d16 A lt d16 E4 MOVW A dir AH lt dir AL lt dir 1 C5 279 APPENDIX Table B 5 1 Transfer instructions Continued MNEMONIC Operation OP CODE MOVW A IX off AH lt IX off C6 AL lt IX off 1 MOVW A ext AH lt ext AL lt ext 1 C4 MOVW A A AH lt A AL lt A 1 93 MOVW A EP AH lt EP C7 AL lt EP 1 MOVW A EP A lt EP F3 MOVW FP d16 EP lt d16 E7 MOVW TIX A IX lt A E2 MOVW A IX A lt IX F2 MOVW SP A SP lt A El MOVW A SP A lt SP Fl MOV A T A lt T 82 MOVW A T A lt TH A 1 lt TL 83 MOVW IX d16 IX lt d16 E6 MOVW A PS A lt PS 70 MOVW PS A PS lt A 71 MOVW SP d16 SP lt d16 E5 SWAP AH lt gt AL 10 SETB dir b dir b lt 1 A8 to AF CLRB dir b dir b lt 0 AO to A7 SCH A T AL lt gt TL 42
39. enter the pull up state 2 The reset pin may serve as the output depending on the option setting 3 For P42 and P46 when edge detection for the external interrupt is selected only the external interrupt can be input even in the stop mode SPL 1 4 Whether the pins behave as I O port or LCD bias depends on the PSEL bit of LCDR see Chapter 12 LCD CONTROLLER DRIVER 5 These pins are selected as LCD bias after reset To turn P32 and P33 to ports after reset set PSEL bit of LCDR to 1 afterwards 295 APPENDIX 296 INDEX INDEX The index follows on the next page This is listed in alphabetic order 297 INDEX Index Numerics 1 2 bias 1 2 duty output waveform eeeeeeee 251 1 3 bias 1 3 duty output waveform eeeeeeeeeee 254 1 3 bias 1 4 duty output waveform eeeeeeeee 257 8 bit PWM timer interrupt source 127 8 bit PWM timer interrupt register and vector table for S 131 8 bit PWM timer pin 126 8 bit PWM timer pin block diagram of 126 8 bit PWM timer registers 127 8 bit PWM timer block diagram of 124 8 bit PWM timer note On ueimg eee 137 8 bit serial I O interrupt source 175 8 bit serial UO Pins 173 8 bit serial I O pins block diagram of 174 8 bit serial I O registers cceeeeeeeeeeetteeteteeees 174 8 bit Serial I O block diagram of 171 8 bit serial I O note ON USING eee eee 188 A addressing explanation of 269 arithmetic inst
40. in the PCR1 register before switching between the interval timer function and pulse width measurement function PCR2 FC Interrupt processing cannot return if the interrupt request flag bit PCR1 UF IR or BF is 1 and the interrupt request enable bit is enabled PCR1 IE 1 Always clear the interrupt request flag bit If a previous measurement value has not been read when performing continuous pulse width measurement for pulse width measurement function new measurement values are not transferred to the PWC reload buffer register RLBR The RLBR maintains the previous value Always read the measurement value before the next underflow 01 gt 00y when measuring long pulse widths The interrupt request flag bit PCR1 UF IR or BF is not set if the counter is disabled PCR1 EN 0 at the same time as an interrupt source is generated CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 10 Program Example for Timer Function of Pulse Width Count Timer This section gives two program examples for the timer function of the pulse width count timer E Program example 1 for interval timer function reload timer mode Processing description e Generates repeated interval timer interrupts at 3 ms intervals reload timer mode e The TO bit will be inverted after each interval time cycle The initial value of TO bit is 0 level e The following shows the RLBR register value that results in an interval time of approximately 3 ms f
41. l l gt FP1 FPO Frame cycle selection bits 0 D Fon x N 610 Hz 0 1 Fcu 2 x N 305 Hz 1 0 FcH 2 8 x N 152 Hz 1 1 Fou 2 4 x N 76 Hz Values for FcH 5 MHz and N 4 N Number of time divisions FcH Main clock frequency oscillation L____s MS1 MSO Display mode selection bits 0 O Stops LCD operation 0 1 1 2 duty ratio output mode time division N 2 1 O 1 3 duty ratio output mode time division N 3 1 1 1 4 duty ratio output mode time division N 4 BK Display blanking selection bit D Displays unblanked 1 Displays blanked VSEL Drive supply voltage control bit Uses external voltage divider internal voltage divider is isolated 1 Uses internal voltage divider gt PSEL LCD voltage supply selection bit O Selects as LCD power supply pins V1 and V2 1 Selects as port pins P32 and P33 RESV Reserved bit Always write 0 to this bit R W Readable and writable Unused Initial value 244 CHAPTER 12 LCD CONTROLLER DRIVER Table 12 3 1 LCD control register LCDR bit functions Function Bit 7 Reserved bit e Always write 0 to this bit Bit 6 PSEL e Selects P32 V1 and P33 V2 to function either as N ch open drain I O ports P32 LCD power supply P33 or as LCD power supply pins V1 and V2 selection bit Bit 5
42. operating states dung 58 State transition dagram 63 stop mode operation of 60 storing 16 bit data in RAM essere 26 storing 16 bit data ON stack 26 storing 16 bit operande ee eects eeeneeeeeeeenaees 26 T timebase timer control register TBTO 104 timebase timer interrupt 106 timebase timer interrupt register and vector table for vadeitacepetatalataed ety ouciain eege 106 timebase timer block diagram of 102 timebase timer note On using 109 timebase timer operation Of 108 timebase timer program example for 110 transfer clock SIECtION of 195 transfer iNStrUCtiONn eeceeeeeeeeeteeeeetenneeeeeteee 279 transmit interrupt ec eeeeeeeeeeeeeeeeeetenneeeeeeeee 215 transmit operation 0 eceeeeeeeeeeeeneeeeeteteeeeeeee 217 U UART function assier e a a a Sg 194 UART interrupt register and vector table jor 215 UART EE 202 UART pin block diagram of 203 UART registers A 204 UART block diagram of 199 UART operation of 216 UART program example Tor 220 V vector table area addresses FFCOH to FFFFH 25 INDEX W watchdog timer control register WDTC 115 watchdog timer Tupnchon 112 watchdog timer block diagram of 113 watchdog timer note ON Ueing tees 118 watchdog timer operation of 116 watchdog timer program example Tor 119 301 INDEX 302 CM25 10146 1E FUJITSU SEMICONDUCTOR e CONTROLLER MANUAL F MC 8L 8 BIT MIC
43. reload timer mode continuous operation and one shot mode one time operation Table 8 1 1 Interval time range lists the available interval time and square wave output ranges Table 8 1 1 Interval time range Internal count clock cycle Interval time Square wave output Hz 1 tinst to 28 tinst 1 2 tins to 1 2 tins 2 tinst to 21 tinst 12 tins to 1 021 tins 2t 126 t too t 14 ins inst inst to 1 2 tinst tinst Instruction cycle divide by four main clock oscillation The following shows an example of the interval time For a 5 MHz main clock oscillation Foy a PWC reload buffer register RLBR value of DDy 221 and a count clock cycle of one instruction cycle the interval time and square wave output frequency are calculated as follows Interval time 1 x 4 Fcu x RLBR register value 4 5 MHz x 221 176 8 us RLBR register value of OOH is assumed as 256 142 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC E Pulse width measurement function The pulse width measurement function can measure the H width L width and one cycle width of pulses input from an external pin PWC pin e The PWC can perform continuous pulse width measurement e The measurement speed internal count clock can be selected from three different speeds e The width of long input pulses can be measured using an interrupt processing routine Table 8 1 2 Available pulse width measured by pulse width measurement
44. when the edge selected by INT1 edge polarity selection bits SL11 SL10 is input to external interrupt pin INT1 An interrupt request is output when both this bit and INT1 interrupt request enable bit EIE1 are 1 Writing 0 clears the bit Writing 1 has no effect and does not change the bit value SL11 SL10 INT edge polarity mode selection bits Controls the mode of the input edge polarity of INT1 pin Writing 00g selects no edge detection 01 selects rising edge mode 10 selects falling edge mode or 11 selects both edge mode Always write 0 into EIR1 when changing these bits EIE1 INT interrupt request enable bit Enables or disables output of interrupt requests to the CPU An interrupt request is generated when both this bit and INT1 external interrupt request flag bit EIR1 are 1 1 EIRO INTO external interrupt request flag bit This bit is set to 1 when the edge selected by INTO edge polarity selection bits SLO1 SLOO is input to external interrupt pin INTO An interrupt request is output when both this bit and INT10 interrupt request enable bit EIEO are 1 Writing 0 clears the bit Writing 1 has no effect and does not change the bit value SLO1 SLOO INTO edge polarity mode selection bits Controls the mode of the input edge polarity of INTO pin Writing 00g selects no edge detection 01 selects rising edge mode 10g selects falling edge mode or 11 s
45. 00 mm Lead shape Straight Motherboard g Ceramic material Mounted package Plastic material MQP 64C P01 64 pin ceramic MQFP MQP 64C P01 18 70 736 TYP 16 30 0 33 12 00 472 TYP 642 013 NDEX AREA 15 58 0 20 ER 1 00 0 25 613 008 1 20 o 20 039 010 1 00 0 25 T S annnnnnnnnn 047 tee 039 010 1 27 0 13 z sch 050 005 i HHH d DEEN 12 02 473 1812 020 878 013 S Sue EN 18 00709 24 70 972 0 30 012 E TYP E TYP mec elas E ER IJH H H ITU 0 40 0 10 1 272013 o s0 012 TvP 016 004 0 40 0 10 12038 050 005 L 7 62 300 TYP 016 004 047 toe B 9 48 373 TYP L 11 68 460 TYP 10 82 426 osocooniTve Tint 0 15 0 05 MAX 50 006 002 WE UNI 1994 FUJITSU LIMITED M64004SC 1 3 Dimengions in mm neies 11 CHAPTER 1 OVERVIEW 1 7 UO Pins and Pin Functions Table 1 7 1 Pin description and Table 1 7 2 Pin description for external ROM for MB89PV950 only list the MB89950 950A series I O pins and their functions Table 1 7 3 I O circuit type lists the I O circuit types The letter in the I O circuit type column in Table 1 7 1 Pin description refer to the letter in the Type column Table 1 7 3 I O circuit type E I O pins and pin functions Table 1 7 1 Pin description 1 2 IO Pin name circuit Function type Clock oscillator pins Operation mode selection pin This pin is connected directly to Vgg with pul
46. 001DH EQU SMR 7 EQU SMR 0 EQU 007DH DSEG ABS ORG OFFFOH DW WARI ENDS Main program CSEG MOV DDR4 00000000B CLRI CLRB SST MOV ILR2 11110111B MOV SMR 01001100B TB SST User processing POPW A XCHW A T POPW A RETI ENDS END Serial mode register Serial data register Define the interrupt request flag bit Define the serial I O transfer start bit Address of the interrupt level setting register 2 DATA SEGMENT Set interrupt vector CODE SEGMENT Stack pointer SP etc are already initialized Set P45 SCK and P43 SI pin as an input Disable interrupts Stop serial I O transfer Set interrupt level level 1 Clear interrupt request flag enable interrupt request output set shift clock input SCK disable serial data output SO select the external shift clock LSB first Enable serial I O transfer Enable interrupts Clear interrupt request flag Read transfer data Enable serial I O transfer CHAPTER 10 UART This chapter describes the functions and operation of the UART 10 1 Overview of UART 10 2 Structure of UART 10 3 UART Pins 10 4 UART Registers 10 5 UART Interrupts 10 6 Operation of UART 10 7 Operation of Mode 0 1 3 10 8 Program Example for UART 193 CHAPTER 10 UART 10 1 Overview of UART The UART is a general purpose data commu
47. 1 Interrupt Level Setting Registers ILR1 ILR2 ILR3 The interrupt level setting registers ILR1 ILR2 ILR3 together contain 12 blocks of 2 bit data with each data corresponding to an interrupt request from a peripheral function The interrupt level for each interrupt is set in that interrupt s corresponding 2 bit data interrupt level setting bits WR Structure of interrupt level setting registers ILR1 ILR2 ILR3 Figure 3 4 1 Structure of interrupt level setting registers Register Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value ILR1 007CH L31 L30 L21 L20 L11 L10 LO LOO 11111111B W W W W W W W W ILR2 007DH L71 L70 L61 L60 L51 L50 L41 L40 11111111B W W W W W W W W ILR3 007EH LB1 LBO LA LAO L91 L90 L81 L80 11111111B W W W W W W W W W Write only Two bits of the interrupt level setting registers are allocated to each interrupt request The value of the interrupt level setting bits in these registers sets the interrupt priority interrupt levels 1 to 3 The interrupt level setting bits are compared with the interrupt level bits in the condition code register CCR IL1 ILO The CPU does not accept interrupt requests set to interrupt level 3 Table 3 4 2 Interrupt level setting bit and interrupt level shows the relationship between the interrupt level setting bits and the interrupt levels Table 3 4 2 Interrupt level setting bit and interrupt lev
48. 21 instruction cycles If on the other hand the program does not use the DIVU or MULU instructions the maximum interrupt processing time is 6 9 15 instruction cycles The time of one instruction cycle changes with the clock mode and the main clock frequency as selected by the speed shift gear function See Section 3 6 Clocks for details CHAPTER 3 CPU 3 4 5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing E Stack operation at start of interrupt processing The CPU automatically saves the current contents of the program counter PC and program status PS to the stack when an interrupt is accepted Figure 3 4 5 Stack operation at start of interrupt processing shows the stack operation at the start of interrupt processing Figure 3 4 5 Stack operation at start of interrupt processing Immediately before Immediately after interrupt interrupt Address Memory Address Memory Gel 0870H 027CH XXH SP 027CH ka 027CH O8H PS 027DH XXH 027DH 70H GC E000 027EH XXH PS 0870H 027EH EOH PG 027FH XXH 027FH OOH SP 0280H gt 0280H XxXH PC E000 0280H vu 0281H XXH 0281H XXH E Stack operation at interrupt return On exec
49. 7 6 Notes on Using Standby Mode The CPU does not go to standby mode if an interrupt request occurs from a peripheral function when a standby mode bit is set in the standby control register STBC Also if an interrupt is used to wake up from a standby mode to the normal operating state the operation after wake up differs depending on whether or not the interrupt request is accepted E Go to standby mode and interrupts If an interrupt request with an interrupt level higher than 11g occurs from a peripheral function to the CPU writing 1 to the stop bit STP sleep bit SLP in the standby control register STBC is ignored Therefore the CPU does not go to standby mode The CPU also does not go to the standby mode after completing interrupt processing This does not depend on whether or not the CPU accepts the interrupt Even if the CPU is currently performing interrupt processing after clearing the interrupt request flag bit the device can go to the standby mode if no other interrupt request is present E Wake up from standby mode by interrupt If an interrupt request with an interrupt level higher than 11 occurs from a peripheral function or others during sleep or stop mode the CPU wakes up from standby mode This does not depend on whether or not the CPU accepts the interrupt After wake up from standby mode the CPU performs the normal interrupt operations If the level set in the interrupt level setting register ILR1 to I
50. 8 bit serial UO E 8 bit serial I O pins 8 bit serial I O uses the P43 SI P44 SO and P45 SCK The pins are also used as UART I O pins To use the pins as serial I O pins set the UART SIO selection bit RSEL of UART serial mode control register 2 SMC2 RSEL 1 P43 SI pin The P43 SI pin can function either as a general purpose I O port P43 or as the serial data input hysteresis input for 8 bit serial I O or UART P44 SO pin The P44 SO pin can function either as a general purpose I O port P44 or as the serial data output for 8 bit serial I O or UART Enabling serial data output SMR SOE 1 and UART SIO selection bit SMC2 RSEL 1 automatically sets the P44 SO pin as an output pin regardless of the port data direction register DDR4 bit 4 value and sets the pin to function as the SO pin P45 SCK pin The P45 SCK pin can function either as a general purpose I O port P45 or as the shift clock I O for 8 bit serial I O or UART Set P45 SCK pin as an input port in the data direction register DDR4 bit 5 0 when using as SCK pin e When using as the shift clock input pin When using SCK as an input pin set the pin as an input port in the port data direction register DDR4 bit 5 0 and disable shift clock output SMR SCKE 0 In this case always select external shift clock operation SMR CKS1 CKSO 11 e When using as the shift clock output pin Enabling shift clock output SMR SCKE
51. A PC Main routine Subroutine MOVW A PUTSUB PUTSUB XCHW A EP XCHW A PC PUSHW A DB PUT OUT DATA EOL PTS1 MOV A EP MOVW A 1234H INCW EP 5 MOV 10 A lt CMP A EOL BNE PTS1 POPW A XCHW A EP JMP A Output table data here APPENDIX B Overview of Instructions CALLV vct This instruction is used to branch to a subroutine address stored in the vector table The instruction saves the return address contents of PC in the location at the address contained in SP stack pointer and uses vector addressing to cause a branch to the address stored in the vector table Because CALLV vct is a 1 byte instruction the use of this instruction for frequently used subroutines can reduce the entire program size Figure B 3 7 Example of executing CALLV 3 shows a summary of the instruction Figure B 3 7 Example of executing CALLV 3 Before execution After execution PC 5678H PC FED CH SP 1234H 2 SP 1232H 1232H XXH 1232H 56H 1233H X XH 1233H 79H FFC6H F EH FFC6H FEH FFC 7H DCH FFC 7H DCH After the CALLV vct instruction is executed the contents of PC saved on the stack area are the address of the operation code of the next instruction rather than the address of the operation code of CALLV vct Accordingly Figure B 3 7 Example of executing CALLV 3 shows that the value saved in
52. Ee BITS bii BI SEGS7 00771 bit3 bit2 bit1 bito SEG38 Pins SEG36 to SEG41 share pins bit7 bit bits bit4 SEG39 with Port 2 P20 to P25 bits bit2 bit bito SEG40 00784 Fiz bite bis Wu sEG41 COM3 COM2 COM1 COMO lt gt RAM area and common pins used in 1 2 duty ratio mode lt RAM area and common pins used in 1 3 duty ratio mode gt RAM area and common pins used in 1 4 duty ratio mode 248 CHAPTER 12 LCD CONTROLLER DRIVER Table 12 3 3 Segment outputs display RAM locations and sharing port pins Segment common output Corresponding pins used mask option display RAM area General purpose ports sharing same pins SEGO to SEG19 20 pins 64y to 6Dy POO to P07 P10 to P17 P20 to P25 22 pins SEGO to SEG19 SEG40 to 64y to 6Dy POO to P07 P10 to P17 P20 to P23 20 pins SEG41 22 pins 7844 SEGO to SEG19 SEG36 to 64y to 6Dy POO to P07 P10 to P17 16 pins SEG41 26 pins 76y to 78H SEGO to SEG27 SEG36 to 64y to 71H P10 to P17 8 pins SEG41 34 pins 76y to 784 SEGO to SEG31 SEG36 to 64y to 73H P14 to P17 4 pins SEG41 38 pins 76y to 784 SEGO to SEG39 40 pins 64y to 77H P24 to P25 2 pins SEGO to SEG33 SEG36 to 64y to 744 P16 to P17 2 pins SEG41 40 pins 76y to 784 SEGO to SEG34 SEG36 to SEG41 41 pins 64y to 784 P17 1 pin SEGO to SEG41 42 pins 64y to 78y None Note Locations in the display RAM area that are not r
53. LCD controller driver COMO to COM3 V3 Other pins gt P33 V2 MODA P32 V1 Veo Vss Port 3 25 P30 P31 N ch open drain I O port CHAPTER 1 OVERVIEW 1 5 Pin Assignment Figure 1 5 1 FPT 64P M09 pin assignment and Figure 1 5 2 MQP 64C P01 pin assignment show the pin assignment diagrams for the MB89950 950A series E FPT 64P MO09 pin assignment Figure 1 5 1 FPT 64P M09 pin assignment SEG4 SEG3 SEG2 SEG1 SEGO COM3 COM2 COM1 COMO V3 P33 V2 P32 V1 P31 P30 P40 P41 PWM A 2 3 4 5 6 7 8 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 Voc SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 TOP VIEW QFP 64 P42 INT1 PWC P43 SI RST P44 SO MODA XO X1 Vss P45 SCK P46 INTO P25 SEG41 P24 SEG40 P23 SEG39 P22 SEG38 P21 SEG37 P20 SEG36 P00 SEG20 P01 SEG21 P02 SEG22 P03 SEG23 P04 SEG24 P05 SEG25 P06 SEG26 P07 SEG27 P10 SEG28 P11 SEG29 P12 SEG30 P13 SEG31 P14 SEG32 P15 SEG33 P16 SEG34 P17 SEG35 E MQP 64C P01 pin assignment CHAPTER 1 OVERVIEW
54. Output Function type Pin name P00 SEG20 General purpose I O port P07 P06 to P07 SEG27 P10 SEG28 General purpose I O port P17 P16 to P17 SEG35 Nech Segment driver output SEG34 Segment driver output SEG27 SEG26 P20 SEG36 open drain General purpose I O port to P25 SEG41 Segment driver output General purpose I O port to P33 V2 P40 CMOS CMOS General purpose I O port LCD bias to resource push pull P46 INTO hysteresis option Peripherals 70 Table 4 1 2 Port registers Register Port 0 data register PDRO Read Write Address CHAPTER 4 I O PORTS Initial value 11111111 Port 1 data register PDR1 11111111 1114115 Port 3 data register PDR3 EL Port 2 data register PDR2 Port 4 data register PDR4 XXXXXXXg Port 4 data direction register DDR4 R W Readable and writable W Write only X Indeterminate Unused 0000000 71 CHAPTER 4 I O PORTS 4 2 Port 0 Port 0 is N ch open drain I O port that also serves as LCD segment driver outputs Port 0 pins can be switched between LCD segment driver output and port operation by mask option This section principally describes the port functions when operating as N ch open drain UO port The section describes the port structure and pins the pin block diagram and the port registe
55. POO SEG20 to P07 SEG27 P10 SEG28 to P17 SEG35 and P20 SEG36 to P25 SEG41 in order to be consistent with mask option E Segment output select register SEGR Figure 12 3 6 Segment output select register SEGR Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 007AH SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEGO0 0000000s R W R W R W R W R W R W R W E SEGOO Segment output selection bit 0 Select as N ch open drain UO ports POO to P07 1 Select as segment output SEG20 to SEG27 La SEG10 Segment output selection bit 0 Select as N ch open drain UO ports P10 to P13 1 Select as segment output SEG28 to SEG31 gt SEG11 Segment output selection bit 0 Select as N ch open drain UO ports P14 to P15 1 Select as segment output SEG32 to SEG33 LCS SEG 12 Segment output selection bit 0 Select as N ch open drain UO port P16 1 Select as segment output SEG34 gt SEG13 Segment output selection bit 0 Select as N ch open drain I O port P17 1 Select as segment output SEG35 SEG14 Segment output selection bit 0 Select as N ch open drain UO ports P20 to P23 1 Select as segment output SEG36 to SEG39 gt SEG15 Segment output selection bit 0 Select as N ch open drain UO ports P24 to P25 1 Select as segment output SEG40 to SEG41 R W
56. Serial Status and Data Register GD 209 10 4 4 Serial Input Data Register ID 211 10 4 5 Serial Output Data Register SODR essssseessiessresirssrisseriserrrstittstinstittsttntetutnttunetnnttnnnnnnnenenana 212 10 4 6 Serial Mode Control Register 2 MCL 213 UE Se a Rue 215 10 6 Operation Of UART 00 02 cccccececeeeceeeecneeeeeaeeeeeeeeeeeeeeeeeaeeecaeeeseaeeescaeeeseaeeeseaeeeeeeeseeaeeeseaeeeseaeesesueeeseaees 216 t07 Operationro Mode OT WEE 217 10 8 Program Example tor U ARM eeuidzebesdkteeget Eed E levee aa e E ER Ea AT EA EE Dee 220 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE seess sseeEESRREEEEEERREEEERSEEEEEE 223 11 1 Overview of the External Interrupt Circuit cccceeeceeeeeeeeeneeeeeeeeeeeeeeeeseaeeeeeeeeeaeeeseaeeeseaeeseeeeeneaees 224 11 2 Block Diagram of the External Interrupt Circuit 0 cccceeceeeeseeeeeneeeeeeeeseaeeeeeaeeeseaeeeseaeeeseaeeeteneeeeeaaes 225 11 3 Structure of the External Interrupt Circuit 0 ccceecceceeeeeeeeeeeeeeeeeeeeeeeeeseaeeeeeaeeeseaeeeseeeeseeeeseieeeeeaees 226 11 3 1 External Interrupt Control Register EIC ccceceseeeeeeeeeeeneeeeeeeeeeeeeseeeeeseneeeseaeeeecaeeeeeeeeeeaaeess 228 11 4 External Interrupt Circuit Interrupts ec eee eceeeeeneeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeaeeeseaeeeseaeeeseneeeeeaaes 230 11 5 Operation of the External Interrupt Circuit 0 ccecceeceeeeeeeeeeeeeeeeeeeeeeseaeeeeeaeeeseaeeeseaeeeseaeeeseneeeneaees 231 11 6 Program Examp
57. UART registers Figure 10 4 1 UART registers SMC1 Serial mode control register 1 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Initial value 0020H PEN SBL MC1 MCO SMDE SCKE SOE 00000 008 R W R W R W R W R W R W R W SRC Serial rate control register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Initial value 0021H CR CS1 CSO RC2 RC1 RCO 011000B R W R W R W R W R W R W SSD Serial status and data register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Initial value 0022H RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP 00100 1XB R R R R W R W R W R SIDR Serial input data register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Initial value 0023H XXXXXXXXB SODR Serial output data register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Initial value 0023H XXXXXXXXB Ww Ww Ww Ww Ww Ww Ww Ww SMC2 Serial mode control register 2 Address Bit7 Bit6 Bit5 Bit4 D Bit2 Biti BitO Initial value 0024H PSEN RSEL PDS1 PDSO 1 0 008 R W R W RW RW R W Readable and writable R Read only W Write only Unused X Indeterminate 204 CHAPTER 10 UART 10 4 1 Serial Mode Control Register 1 SMC1 Serial mode contro
58. XCHW A T A lt gt T 43 XCHW A EP A lt gt EP F7 XCHW A IX A lt gt IX F6 XCHW A SP A lt gt SP F5 MOVW A PC A lt PC FO Note In automatic transfer to T during byte transfer to A AL is transferred to TL If an instruction has two or more operands they are assumed to be saved in the order indicated by MNEMONIC 280 E Arithmetic instructions Table B 5 2 Arithmetic operation instructions MNEMONIC ADDC A Ri Operation A lt A Ri C APPENDIX B Overview of Instructions OP CODE 28 to 2F ADDC A d8 A lt A d8 C 24 ADDC A dir A lt A dir C 25 ADDC A IX off A lt A IX 0ff C 26 ADDC A EP A lt A EP C 27 ADDCW A A lt A T C 23 ADDC A AL lt AL TL C 22 SUBC A Ri A lt A Ri C 38 to 3F SUBC A d8 A lt A d8 C 34 SUBC A dir A lt A dir C 35 SUBC A IX off A lt A IX 0ff C 36 SUBC A EP A lt A EP C 37 SUBCW A A lt T A C 33 SUBC A AL lt TL AL C 32 INC Ri Ri lt Ri 1 INCW EP EP lt EP 1 C3 INCW Ix IX lt IX 1 C2 INCW A A lt A 1 CO DEC Ri Ri lt Ri 1 D8 to DF DECW EP EP lt EP 1 D3
59. address One of the N branch destination addresses is selected from a table and then transferred to A The instruction can be executed to perform N branch processing Figure B 3 1 JMP A shows a summary of the instruction Figure B 3 1 JMP A Before execution After execution A 1234H A 1234H Previous PC X X X XH gt CurrentPC 12344 MOVW A PC This instruction performs the operation which is the reverse of that performed by JMP A That is the instruction stores the contents of PC in A When the instruction is executed in the main routine so that a specific subroutine is called whether A contains a predetermined value can be checked by the subroutine This can be used to determine that the branch source is not any unexpected section of the program and to check for program runaway Figure B 3 2 MOVW A PC shows a summary of the instruction Figure B 3 2 MOVW A PC A XXX XH CS A 1234 Previous PC 123 4H Current PC 123 4H After the MOVW A PC instruction is executed A contains the address of the operation code of the next instruction rather than the address of the operation code of MOVW A PC Accordingly Figure B 3 2 MOVW A PC shows that A contains 1234y which is the address of the operation code of the instruction that follows MOVW A PC 274 APPENDIX B Overview of I
60. are selected as V1 and V2 and stop mode is entered the voltage at those pins before entering stop mode will be held For port output those pins states in stop mode are controlled by SPL bit in the STBC register The output transistors are forcibly turned OFF and the pins go to the high impedance state if the pin state specification bit in the standby control register STBC SPL is 1 when the device goes to stop mode Table 4 5 4 Port 3 pin state lists the port 3 pin states CHAPTER 4 I O PORTS Table 4 5 4 Port 3 pin state Normal operation Pin name sleep mode Stop mode SPL 1 stop mode SPL 0 P30 to P33 V2 General purpose I O ports bias input SPL Pin state specification bit in the standby control register STBC Hi Z High impedance CHAPTER 4 I O PORTS 4 6 Port 4 Port 4 is a general purpose I O port that also serves as the peripheral signal I O pins Individual pin can be switched between the port and resource function This section principally describes the port functions when operating as a general purpose I O port The section describes the port structure and pins the pin block diagram and the port registers for port 4 Structure of port A Port 4 consists of the following three components e General purpose I O port peripheral I O pins P40 to P46 INTO e Port 4 data register PDR4 e Port 4 data direction register DDR4 E Port 4 pins Port 4 consists of seven I O pins of CMOS type input a
61. are set as N ch open drain I O by mask option they cannot be used as LCD segment output 234 12 2 CHAPTER 12 LCD CONTROLLER DRIVER Block Diagram of LCD Controller Driver The LCD controller driver is made up of seven blocks listed below Functionally the circuit can be broken into two major sections the controller section which generates LCD segment and common signals based on the current contents of display RAM and the driver section which develops sufficient drive to operate the display LCD control register LCDR Display RAM Prescaler Timing controller V I converter Common output driver Segment output driver E Block diagram of LCD controller driver Figure 12 2 1 Block diagram of LCD controller driver LCD c Fou 28 e Timebase timer output Prescaler Internal bus FcH Main clock oscillation frequency ontrol register LCDR Timing controller Display RAM 42 x 4 bit 21 bytes Controller Power supply V1 to V3 Common output driver V I converter Segment output driver Driver LCD control register LCDR This register is used to control the LCD drive supply voltage select display blanking non blanking select the display mode and select the LCD clock cycle 235 CHAPTER 12 LCD CONTROLLER DRIVER 236 Display RAM This 42 x 4 bit block of RAM controls the segment output signa
62. clock cycle Clock division Transfer rate Clock division Transfer rate value baud value baud 39062 to 152 6 312 5k to 1 22k 9765 6 to 38 1 2441 4 to 9 5 19531 3 to 76 3 610 4 to 2 4 610 4 to 2 4 4882 8 to 19 1 152 6 to 0 6 19531 3 to 76 3 156 3 to 610 4 4882 8 to 19 1 4882 8 to 19 1 39062 to 152 6 1220 7 to 4 8 610 4 to 2 38 4882 8 to 19 1 152 3 to 0 6 tinst Instruction cycle 1 Main clock oscillation frequency Foy 5 MHz Figure 10 1 3 Sample calculation of the baud rate PWM timer is selected Input clock select bits PWM timer Clock Compare register 1 selection 16 p 0 PO i Se CR 0 16 Baud rate value AEo X 32 P1 1 PO 0 S e ae CR 1 64 PWC P1 1 PO 1 Cycle time FcH Main clock oscillation frequency PWC value depends on the value of PWC pulse width control register 2 bit 3 and bit 2 PCR2 C1 C0 C1 0 CO 0 gt 1 C1 0 CO 1 gt 4 C1 1 CO 0 gt 32 C1 1 C0 1 gt Prohibited Refer to CHAPTER 7 8 BIT PWM TIMER section for information on the count clock cycle of the PWM timer PWM compare register setting value and output cycle of the PWM timer 198 10 2 Structure of UART CHAPTER 10 UART The UART consists of the following blocks es Baud rate generator and serial clock generator e Data transmitter and data receiver e Re
63. executed ll G T b i i 1 C 1 E Output latch E i pat PDR write EE Sa Pin Port data direction register Sei opp OO DDR write l Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC 126 CHAPTER 7 8 BIT PWM TIMER E 8 bit PWM timer registers Figure 7 3 2 8 bit PWM timer registers CNTR PWM control register Address Bit7 Pre BitS Bit4 Bits Bit2 Biti BitO Initial value 0012H P T P1 PO TPE TIR OE TIE 0 0000008 R W Rw RW RW RW RW RW COMR PWM compare register Address Bit7 Bit6 Bit5 Bit4 Bits Bit2 Biti BitO Initial value 0013H XXXXXXXXB W W W W W W W W R W Readable and writable W Write only Unused X Indeterminate Note As the PWM compare register COMR is write only the bit manipulation instructions cannot be used E 8 bit PWM timer interrupt source IRQ2 For the interval timer function the 8 bit PWM timer generates an interrupt request if interrupt request output is enabled CNTR TIE 1 when the counter value matches the value set in the COMR register For PWM function no interrupt request is generated 127 CHAPTER 7 8 BIT PWM TIMER 7 3 1 PWM Control Register CNTR The PWM control register CNTR is used to select the operating mode of the 8 bit PWM timer interval timer operation or PWM timer operation enable or
64. from the timebase timer TBTC TBIF 1 is generated at the time when the clock mode starts operation In this case disable the timebase timer interrupt when entering to a mode in which the main clock oscillation is stopped stop mode E Register and vector table for timebase timer interrupts 106 Table 5 4 1 Register and vector table for timebase timer interrupt Interrupt level settings register Vector table address Interrupt Register Set bit IRQ6 ILR2 007Dy L61 Bit 5 L60 Bit 4 FFEEy FFEFy See Section 3 4 2 Interrupt Processing for details on the operation of interrupt CHAPTER 5 TIMEBASE TIMER 5 5 Operation of Timebase Timer The timebase timer has the interval timer function and the clock supply function for some peripherals E Operation of interval timer function timebase timer Figure 5 5 1 Interval timer function settings shows the settings required to operate the interval timer function Figure 5 5 1 Interval timer function settings Bit7 Bue Bits Bit4 Bits P Biti Bito TBTC TBIF TBIE TBR TBC1 TBCO Used bit 1 Gei 1 0 1 0 0 Set 0 Provided that the main clock is oscillating the timebase timer counter continues to count up in synchronous with the internal count clock divide by two main clock oscillation frequency After being cleared TBR 0 the counter restarts to count up from zero The t
65. function lists the available pulse widths measured by the pulse width measurement function Table 8 1 2 Available pulse width measured by pulse width measurement function Internal count clock cycle Interval time 8 1 tinst to 2 tinst 2 10 2 tinst tO 2 tinst 2 tint to 2 t inst Guer Instruction cycle divide by four main clock oscillation 143 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 2 Block Diagram of Pulse Width Count Timer The pulse width count timer consists of the following nine blocks e Count clock selector e 8 bit down counter s Input pulse edge detector e Noise filter circuit e Noise filter clock selector e PWC reload buffer register RLBR e PWC pulse width control register 1 PCR1 e PWC pulse width control register 2 PCR2 e Noise filter control register NCCR E Block diagram of pulse width count timer Figure 8 2 1 Block diagram of pulse width count timer Dh PCR1 EN IE UF IR BF To PWM timer PCR2 a ZS FC RM TO C1 co Wi wo o E P42 PWC INT1 Input pulse edge Noise filter ge 8 bit down counter d t ct r circuit lt Pin L y
66. gt Du by software in the interrupt processing routine Counting by software requires a buffer in RAM a software counter to hold the number of counter underflows Oly gt 00p After initializing the software counter and enabling counter operation the counter starts to count down from FFy when a measurement start edge is detected on the pulse input to the PWC pin An interrupt request is generated on detection of the measurement completion edge or when the counter underflows Oly gt 00y Check the measurement completion interrupt request flag bit PCR1 IR and underflow Oly gt Uu interrupt request flag bit PCR1 UF in the interrupt processing routine If the UF bit is 1 write 0 to the UF bit to clear the interrupt request and increment the software counter the PWC counter continues to operate When the IR bit is 1 calculate the pulse width including underflows including underflows Oly gt Uu from the values of the software counter and PWC reload buffer register RLBR When the RLBR register value is 00y calculate as 256 Calculating the width of long pulses Pulse width 256 RLBR register value number of counter underflows Oly gt 00y x 256 x one cycle width of count clock Calculate the pulse width before the next underflow Oly gt 00y occurs The correct measurement value may not be able to be calculated after the next underflow Oly gt 00y occurs Figure 8 6 3 Me
67. gt and PWC timer output output controller To UART lt 5 Q 5 P41 PWM Pin H tinst Instruction cycle 4 FcH Output pin control bit 124 CHAPTER 7 8 BIT PWM TIMER Count clock selector Selects a count up clock for the 8 bit counter from the three internal count clocks and the PWC timer output cycle 8 bit counter The 8 bit counter counts up on the count clock selected by the count clock selector Comparator circuit The comparator circuit has a latch to hold the COMR register value The circuit latches the COMR register value when the 8 bit counter value is 004 The comparator circuit compares the 8 bit counter value with the latched COMR register value and detects when a match occurs PWM generator and output controller When a match is detected during interval timer operation an interrupt request is generated and if the output pin control bit CNTR OE is 1 the output controller inverts the output level of the PWM pin At the same time the 8 bit counter is cleared When a match is detected during PWM timer operation the PWM generator changes the output level of the PWM pin from H to L The pin is set back to the H level when the next overflow occurs on the 8 bit counter COMR register The COMR register is used to set the value that is compared with the value of the 8 bit counter CNTR register The CNTR register is used to select the operating mode enable or disable operation
68. i Data receive control circuit PEN i l j l TIE l i l MC1 Parity TDRE D gt MCO generator Peer RIE WE IRQ4 S i RE X l P43 SI d d ORFE l Start Shift clock Wer l l Start bt Receiver gt l l i byte count l i detection y Transfer clock i Reset l f SIDR l l l CR RDRF ORFE f 4 At switching between port output and serial clock output the SCKE bit of the UART is valid when the RSEL bit is 0 the SCKE bit of the serial I O is valid when the RSEL bit is 1 2 At switching between port output and serial data output the SOE bit of the UART is valid when the RSEL bit is 0 the SOE bit of the serial I O is valid when the RSEL bit is 1 199 CHAPTER 10 UART 200 Baud rate generator and serial clock generator This block generates transmit receive clocks from the outputs of baud rate generator 8 bit PWM timer or external clock Date receive control circuit The receive control circuit consists of the receive byte counter the start bit detection circuit and the receive parity circuit The receive byte counter counts number of data bit received and generates an interrupt after having received data of the specified length The start bit detection circuit detects start bit from the serial input pin and starts to shift the following data bit received into the shifter The receive parity circuit stores a parity bit after receiving data with a parity When 9 bit long data is received the rece
69. in synchronous with PWC output clock or one of three internal count clocks Therefore an 8 bit interval timer time can be set and the output can be used to generate variable frequency square waves E Interval timer function square wave output function The interval timer function generates repeated interrupts at variable time intervals Also as the 8 bit PWM timer can invert the output level of the pin PWM each time an interrupt is generated the 8 bit PWM timer can output a variable frequency square waves e The interval timer can operate with a cycle among 1 and 28 times the count clock cycle e The count clock can be selected from four different clocks Table 7 1 1 Interval time and square wave output range lists the range for the interval time and square wave output Table 7 1 1 Interval time and square wave output range Count clock cycle Interval time Square wave output Hz 1 ting to 28 tinge 1 2 tinst to UO Geet Internal count 4 4 12 5 13 clock inst 2 tinst t0 2 tinct LC Geet to HOT tinge 26t PP to 214 tinst LC tinst to 1 2 gt Geet inst 2 tinst to 2 tinst 2 tiny to 21 tinst 1 2 tins to 1 218 tinct PWC timer 3 11 3 4 20 output cycle 2 tinst to 2 tinst 2 tinst to 2 9 tinst 1 2 tinst to 1 2 tinso inst Ce tinst tO SS tinst I EN tins to 1 GC tinst 26 tinto 24t tinst Instruction cycle Reference Calculation example for the interval time and
70. interrupt Option setting With power on reset No power on reset O Oscillation stabilization delay time provided X Oscillation stabilization delay time not provided CHAPTER 3 CPU 3 7 Standby Mode Low power Consumption The standby mode consists of sleep mode and stop mode Main run mode is switched to sleep mode or stop mode by setting the standby control register STBC Standby mode reduces the power consumption by stopping the operation of the CPU and peripheral functions This section describes the relationship between standby mode and clock mode and the operation of various sections during standby E Standby mode Standby mode reduces the power consumption however by stopping the clock signal supply to the CPU via clock controller sleep mode or by stopping the source oscillator itself stop mode Sleep mode Sleep mode stops the CPU and watchdog timer but operate the peripheral functions Stop mode Stop mode stops the CPU and peripheral functions The main clock oscillator is stopped Everything is shut down except external interrupt service 57 CHAPTER 3 CPU 3 7 1 Operating States in Standby Mode This section describes the operating states of the CPU and peripheral functions in standby mode E Operating states during standby mode Table 3 7 1 Operating states of the CPU and peripheral functions in standby mode Main clock mode Function Stop Sleep SP
71. interrupt requests corresponding to the peripheral functions On acceptance of an interrupt execution branches to the interrupt processing routine The contents of interrupt the vector table address corresponding to the interrupt request specifies the branch destination address for the interrupt processing routine An interrupt processing level can be for each interrupt request in the interrupt level setting registers ILR1 ILR2 ILR3 Three levels are available If an interrupt request with the same or lower level occurs during execution of an interrupt processing routine the latter interrupt is not normally processed until the current interrupt processing routine completes If interrupt request set the same level occur simultaneously the highest priority is IRQO Table 3 4 1 Interrupt request and interrupt vector Vector table address Bit names of the Interrupt request interrupt level Priority 1 Upper Lower setting register IRQO External interrupt 0 L01 LOO IRQ1 External interrupt 1 L11 L10 IRQ2 8 bit PWM timer L21 L20 IRQ3 PWC L31 L30 IRQ4 UART L41 L40 IRQS 8 bit serial I O L51 L50 IRQ6 Timebase timer L61 L60 IRQ7 Unused L71 L70 IRQ8 Unused L81 L80 IRQ9 Unused L91 L90 IRQA Unused LA1 LA0O IRQB Unused LB1 LBO 1 This priority is applied when interrupts of the same level occur simultaneously 35 CHAPTER 3 CPU 3 4
72. is cleared when transmission data is written into the SODR register It is set when the data is loaded into the transmit shifter and transmission begins If the TDRE bit is set when the TIE bit is 1 a transmission interrupt request is generated TIE Transmitter interrupt enable bit This bit enables transmission interrupt If the TDRE bit is 1 a transmission interrupt is immediately generated once transmission interrupt enable bit is set to 1 1 d RIE Receiver interrupt enable bit This bit enables receive interrupt If the RDRF bit is 1 or if any error flag is 1 a receive interrupt is immediately generated once receive interrupt enable bit is set to n 1 d Unused bit The read value is indeterminate Writing to this bit has no effect on the operation TD8 TP Transmitted data parity selection bit This bit is used to select the parity for the transmitted data 210 RD8 RP Received data parity selection bit This bit is used to select the parity for the received data CHAPTER 10 UART 10 4 4 Serial Input Data Register SIDR The serial input data register SIDR is used to input receive serial data E Serial input data register SIDR Figure 10 4 5 Serial input data register SIDR shows the bit allocations of the serial input data register Figure 10 4 5 Serial input data register SIDR Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0023H X
73. lt x lt Oj X OJ x xK xK x x lt If any customer wants to choose the mask option combination which is not shown in Table C 2 Recommended port segment mask option combinations please inform Fujitsu for special testing arrangement 288 APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller This appendix describes the programming specifications for one time PROM and EPROM microcontroller D 1 Programming Specifications for One time PROM and EPROM Microcontrollers D 2 Programming Yield and Erasure D 3 Programming to the EPROM with Piggyback Evaluation Device 289 APPENDIX D 1 Programming Specifications for One time PROM and EPROM Microcontrollers In EPROM mode the MB89P955 function is equivalent to the MBM27C256A This allows the PROM to be programmed with a general purpose EPROM programmer by using the dedicated adaptor Note that the electronic signature mode cannot be used E EPROM programmer socket adaptor Depending on the EPROM programmer inserting a capacitor of about 0 1 UF between Nep and Noe or Voc and Vss can stabilize programming operations Table D 1 1 EPROM programmer socket adaptor lists the EPROM programmer socket adaptors Table D 1 1 EPROM programmer socket adaptor Compatible socket adaptor FPT 64P M09 ROM 64QF2 28DP 8L3 Inquiries Sun Hayato Co
74. pin block diagram of 93 POM 4 PINS eege sie gg Eder ER port 4 register function 2 0 2 eececeeeeeeeeeeeteeteeeeeeeees 94 port 4 registers ceeeeeeceeeeeeeeeeeeeeeeeeeesnntneeeeeeeeees 93 port 4 operation Of 96 port 4 structure of 92 product range MB89950 950A serles 4 programming socket adaptor sssssseeeeseeseeeseee 294 programming viel 293 PROM option bit Map for 292 pulse width count timer interrupt source 147 pulse width count timer interrupt register and vector table fer ened e tet 155 pulse width count timer Din 146 pulse width count timer pin block diagram of 146 pulse width count timer regleterg ee 147 pulse width count timer block diagram of 144 pulse width count timer note on useimg 164 pulse width measurement Tunchon 143 pulse width measurement function interrupt for 155 pulse width measurement function operation of en e Bee deed eege ite ee 159 162 PWC noise filter control register NCCR 154 PWC pulse width control register 1 PCR1 148 PWC pulse width control register 2 PCR2 150 PWC reload buffer register DL DP 152 PWM compare register COMR n 130 PWM control register CONTR ssec 128 PWM timer function saesssesceiresserrreererrresrrnensens 123 PWM timer function operation of 134 PWM timer function program example for 140 R read modify write operaiion 278 receive int
75. pin with a pull up resistor optional go to H level Initialized to 0 by a reset Bit4 RST Specifies a software reset Software Writing 0 to this bit generates an internal reset source for four instruction reset bit cycles Writing 1 to this bit has no effect on operation Reading this bit always returns 1 Bit 3 Unused bits The read value is indeterminate Bit 2 Writing to these bits has no effect on operation Bit 1 Bit 0 CHAPTER 3 CPU 3 7 5 State Transition Diagram This section shows two state transition diagrams one diagram for with power on reset option products and the other for without power on reset products E State transition diagrams Figure 3 7 2 State transition diagram products with power on reset Power on Power on reset Oscillation stabilization 1 delay reset state 2 7 Main clock oscillation stabilization delay Clock mode gt Sleep mode Figure 3 7 3 State transition diagram products without power on reset Power on 1 External reset 7 Clock mode Sleep mode 5 Main clock oscillation stabilization delay 63 CHAPTER 3 CPU Go to normal state RUN and reset Table 3 7 3 Go to main clock mode run state and reset State transition Go to normal state RUN after power on Conditions events required for transition Products w
76. power supply GND For data input For ROM chip enable The High level is output in standby mode For address output For ROM output enable The Low level is always output For address output For address output For EPROM power supply 14 For internal connection Keep open CHAPTER 1 OVERVIEW Table 1 7 3 I O circuit type 1 2 Circuit Remarks Crystal oscillator Feedback resistor About 1 MQ 5 V N ch P ch I leew a E Mon ed gt Standby control signal CMOS input Pull down resistor N ch About 50 kQ 5 V Output pull up resistor P ch About 50 kQ 5 V Hysteresis input e N ch open drain output e CMOS input e The segment driver output is optional CHAPTER 1 OVERVIEW Table 1 7 3 I O circuit type 2 2 Circuit Remarks CMOS output CMOS input Hysteresis input peripheral input The pull up resistor is optional About 50 kQ 5 V N ch open drain output CMOS input LCD controller driver common segment driver output N ch open drain output CMOS input CHAPTER 2 HANDLING DEVICES This
77. register E Port 2 data register functions Port 2 data register PDR2 The PDR2 register holds the pin states Therefore a bit corresponding to a pin set as an output port can be read as the same state 0 or 1 as the output latch but when it is an input port it cannot be read as the output latch state Reference For SETB and CLRB bit operation instructions since the state of output latch not the pin is read the output latch states of bits other than those being operated on are not changed Settings as an LCD segment driver output To use pins as LCD segment driver outputs segment driver output must be selected by the mask option Furthermore the segment driver output select register must be set to the same as the mask option so that the CMOS input port can be protected Table 4 4 3 Port 2 data register function lists the functions of the port 2 data register Table 4 4 3 Port 2 data register function Register Address Initial value Outputs an L level to the pin Sets 0 to the output latch and turn the output transistor ON Pin state is the L level Port 2 data register PDR2 Sets the pin to the high Pin state is the impedance state H level Sets 1 to the output latch and turn the output transistor OFF 111111g R W Readable and writable Unused bit 84 CHAPTER 4 I O PORTS 4 4 2 Operation of Port 2 This section describes the o
78. register Address of the serial output data register Address of the serial mode control register 2 Define the baud rate generator operation start stop bit Address of the interrupt level setting register DATA SEGMENT Set interrupt vector Disable interrupts Set interrupt level level 1 Non parity 1 stop bit operating mode 1 asynchronous clock output enabled serial data output enabled Proprietary baud rate generator selected Set the baud rate at 150 baud Disable transmit interrupt request enable receive interrupt request Stop UART operation select UART function and select the input clock divider of 1 65 Write transmit data 13H Start UART operation Enable interrupts Bee Interrupt processing routine tepe a WARI PUSHW A XCHW A T USHW A bei User processing POPW A i XCHW A T POPW A RETI ENDS END Save A and T Restore A and T 221 CHAPTER 10 UART 222 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE This chapter describes the functions and operation of the external interrupt circuit 11 1 Overview of the External Interrupt Circuit 11 2 Block Diagram of the External Interrupt Circuit 11 3 Structure of the External Interrupt Circuit 11 4 External Interrupt Circuit Interrupts 11 5 Operation of the External Interrupt Circuit 11 6 Program Example for the External Interrupt Circuit 223 CHAPTER 11 EXTERNAL INTERRUPT CIR
79. register SRC Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0021H CR CS1 CSO RC2 DC RCO 011000B R W R W R W R W R W R W Baud rate selection bits Baud rate bps s Rc2 RC1 RCO Division 49152 MHz SES Clock ratio 1 4 1 4 1 65 PDS division CS1 CS0 1 64 1 8 1 16 CR division 0 0 0 20 9600 78125 2404 0 0 1 21 4800 39063 1202 0 1 0 22 2400 19531 601 0 1 1 23 1200 9766 300 1 0 0 24 600 4883 150 1 0 1 25 300 2441 75 1 1 0 26 150 1221 38 1 1 1 27 75 610 19 Transfer clock selection bits is CS1 CSO e Clock input CR Asynchronous Synchronous 0 0 External clock 0 me 17 1 1 64 0 1 PWM timer a E 1 2 1 1 64 0 1 16 1 0 Dedicated baud 1 2 rate generator 1 1 64 1 1 1 8 1 1 gt CR Clock rate selection bit 0 1 16 of clock input R W Readable and writable 1 1 64 of clock input Initial value Note When CS1 and CSO 11B the 1 8 clock rate is selected irrespective Unused of the value of the CR bit 207 CHAPTER 10 UART Table 10 4 2 Serial rate control register SRC bits Function Bit 7 Unused bits The read value is indeterminate Bit 6 Writing to these bits has no effect on the operation Bit 5 CR Used to select the asynchronous transfer clock rat
80. serial I O operation does not halt and transfer continues as shown in Figure 9 7 4 Operation in sleep mode external shift clock Figure 9 7 4 Operation in sleep mode external shift clock gt Clock for next data SRI r A A r r Transfer disable state SSTbt J fF ob pt i HES i i i r Cleared by the program Se ae a a a ee Ca es ele Ap ele A4 Sto Dale Act Deler A A Ngee Se Na SO pin output _ XG nn DK 2 KIS KH DKS HECHT Sleep mode SLP bit STBC register Wake up from sleep mode by IRQ5 Operation in stop mode In stop mode serial I O operation halts and transfer aborts as shown in Figure 9 7 5 Operation in stop mode external shift clock Operation restarts after wake up from stop mode This causes an error to occur on the device with which the 8 bit serial I O is communicating Initialize the 8 bit serial I O after wake up from stop mode CHAPTER 9 8 BIT SERIAL UO Figure 9 7 5 Operation in stop mode external shift clock Clock for next data SCK input Ge i i i i i i Oscillation SST bit i i l Stop request stabilizatio i i i i i o delay time 4 Cleared by the program SIOF bit Interrupt request SO pin output Stop m da ransfer error occurs STP bit STBC register Wake up from stop mode by an external interrupt Operation during halt Halting operation during transfer SMR SST 0 halts the transfer and clears the shi
81. square wave frequency In this example the main clock oscillation frequency Foy is 5 MHz the PWM compare register COMR value is set to DDy 221 and the count clock cycle is set to 1 Geer In this case the interval time and the frequency of the square wave output from the PWM pin where the PWM timer operates continuously and the value of the COMR register is constant are calculated as follows Interval time 1 x 4 Fcu x COMR register value 1 4 5 MHz x 221 1 177 6 us Output frequency FcuH 1 x 8 x COMR register value 1 5 MHz 8 x 221 1 2 8 kHz 122 CHAPTER 7 8 BIT PWM TIMER E PWM timer function The PWM timer function has 8 bit resolution and can control the H and L width of one cycle e As the resolution is 1 256 pulses can be output with duty ratio of between 0 and 99 6 e The cycle of the PWM wave can be selected from four types e The PWM timer can be used as a D A converter by connecting the output to a low pass filter Table 7 1 2 Available PWM wave cycle for PWM timer function lists the available PWM wave cycles for the PWM timer function Figure 7 1 1 Example D A converter configuration using PWM output and low pass filter shows an example D A converter configuration Table 7 1 2 Available PWM wave cycle for PWM timer function 1 2 3 4 Internal count clock 8 bit timer output cycle times Count clock cycle 6 2 tinst tO Si tinst 23 tinst tO gH tinst 2 tinst to SS tin
82. the interval time The counter is cleared when the counter value matches the value set in this register and the interrupt request flag bit is set to 1 CNTR TIR 1 If data is written to the COMR register during counter operation the new value applies from the next cycle after the next match is detected Reference The COMR setting for interval timer operation can be calculated using the following formula COMER register value interval time count clock cycle x instruction cycle 1 PWM timer operation This register is used to set the value to be compared with the counter value The register therefore sets the H width of the pulse The PWM pin outputs an H level until the counter value matches the value set in this register From the match until the counter value overflows the PWM pin outputs an L level If data is written to the COMR register during counter operation the new value applies from the next cycle after the next overflow Reference In PWM timer operation the COMR setting and the PWM cycle time can be calculated using the following formulas COMR register value duty ratio x 256 PWM wave cycle count clock cycle x instruction cycle x 256 CHAPTER 7 8 BIT PWM TIMER 7 4 8 bit PWM Timer Interrupts The 8 bit PWM timer can generate an interrupt request when a match is detected between the counter value and PWM compare register value for the interval timer function Interrupt re
83. the stack 12324 and 12334 is 56794 which is the address of the operation code of the instruction that follows CALLYV vct return address 277 APPENDIX B 4 Bit Manipulation Instructions SETB CLRB Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual E Read modify write operation By using these bit manipulation instructions only the specified bit in a register or RAM location can be set to 1 SETB or cleared to 0 CLRB However as the CPU operates on data in 8 bit units the actual operation read modify write operation involves a sequence of steps 8 bit data is read the specified bit is changed and the data is written back to the location at the original address Table B 4 1 Bus operation for bit manipulation instructions shows bus operation for bit manipulation instructions Table B 4 1 Bus operation for bit manipulation instructions MNEMONIC Address bus AO to A7 CLRB dir b Ni dir dir address Data A8 to AF SETB dir b dir address Data N 2 Next instruction E Read operation upon the execution of bit manipulation instructions For some I O ports and for the interrupt request flag bits the value to be read differs between a normal read operation and a read modify write operation 1 0 ports during a bit manipulation From some I O ports an I O pin value is read during a normal read operation while an o
84. the watchdog timer clearing the timebase timer also clears the watchdog timer Using as timer for oscillation stabilization delay time As the main clock oscillation frequency is stopped when the power is turned on during stop mode the timebase timer provides the oscillation stabilization delay time after the oscillator starts An appropriate oscillation stabilization delay time must be selected for the type of resonator connected to the main clock oscillator clock generator See Section 3 6 1 Clock Generator Notes on peripheral functions that provided a clock supply from timebase timer In modes in which the main clock oscillation frequency is stopped the timebase timer also stops and the counter is cleared As the clock derived from the timebase timer restarts output from its initial state when the timebase timer counter is cleared the H level may be shorter or the L level longer by a maximum of half cycle The clock of the watchdog timer also restarts output from its initial state 109 CHAPTER 5 TIMEBAS 5 7 E TIMER Program Example for Timebase Timer This section gives a program example for the timebase timer E Program example for timebase timer Processing description e Generates repeated interval timer interrupts at 21 FEcy Fey Main clock oscillation frequency intervals At this time the interval time is approximately 104 86 ms at 5 MHz operation Coding example TBTC TBIF I
85. to P46 INTO General purpose I O port peripheral I O SPL Pin state specification bit in the standby control register STBC Hi Z High impedance Reference Pins with a pull up resistor go to the H level pull up state rather than to the high impedance state when the output transistor is turned OFF 97 CHAPTER 4 I O PORTS 4 7 Program Example for I O Ports This section gives an example program for using the I O ports E Program example for I O ports Processing description e Port O and port 1 are used to illuminate all elements of seven segment LED eight segments if the decimal point is included e The POO pin is used for the anode common pin of the LED and the P10 to P17 pins operate as the segment pins Figure 4 7 1 Connection example for an eight segment LED shows the connection example for an eight segment LED Figure 4 7 1 Connection example for an eight segment LED MB89950 950A POO d P17 gt o P16 Bi L He el Coding example PDRO EQU 0000H Address of the port 0 data register DDRO EQU 0001H Address of the port 0 direction register E eege Main program CSEG CODE SEGMENT CLRB PDR0 0 Get POO to the L level MOV PDR1 11111111B Set all port 1 pins to the H level 98 CHAPTER 5 TIMEBASE TIMER This chapter describes the functions and operation of the ti
86. up resistor option is provided P42 PWC INT1 General purpose I O port Also serves as pulse width count timer input PWC and external interrupt input INT1 The PWC and INT inputs are hysteresis type A pull up resistor option is provided P43 SI General purpose I O port Also serves as serial I O and UART data input SI The SI input is hysteresis type A pull up resistor option is provided P44 SO General purpose I O port Also serves as serial I O and UART data output SO A pull up resistor option is provided P45 SCK General purpose I O port Also serves as serial I O and UART clock input output SCK The SCK input is hysteresis type A pull up resistor option is provided P46 INTO General purpose input port Also serves as external interrupt input INTO The input is hysteresis type A pull up resistor option is provided 5 to 1 64 to 57 55 to 49 6 to 1 64 to 58 56 to 50 SEGO to SEG19 For LCD segment driver outputs 9to6 10 to7 COMO to COM For LCD common driver outputs 10 11 For LCD driver power supply 56 57 Vec Power pin 24 25 1 FPT 64P M09 2 MQP 64C P01 Power GND pin CHAPTER 1 OVERVIEW Table 1 7 2 Pin description for external ROM for MB89PV950 only Pin name Function For high level output For address output For data input For
87. 0100y to 013Fy 0100y to 017Fy 0100y to O1FFy See section 3 2 2 Register Bank Pointer RP and section 3 3 General purpose Registers for details CHAPTER 3 CPU E Vector table area addresses FFCO to FFFF e Used as the vector table for the vector call instruction interrupts and resets e The vector table is allocated at the top of the ROM area The start address of the corresponding processing routine is set as data at each vector table address Table 3 1 2 Vector table lists the vector table addresses referenced by the vector call instruction interrupts and resets See Section 3 4 Interrupts Section 3 5 Resets and 6 CALLV vct in Appendix B 2 Special Instructions for details Table 3 1 2 Vector table Vector table address Vector table address Interrupts Upper Lower Upper Lower Vector call instruction CALLV 0 IRQB CALLV 1 IRQA CALLV 2 IRQ9 CALLV 3 IRQ8 CALLV 4 IRQ7 CALLV 5 IRQ6 CALLV 6 IRQ5 CALLV 7 IRQ4 IRQ3 IRQ2 IRQI IRQO Mode data Reset vector 1 FFFCy is not available Set FFy 25 CHAPTER 3 CPU 3 1 2 Storing 16 bit Data in Memory For 16 bit data and the stack store the upper data in the lower memory address value E Storing 16 bit data in RAM When writing 16 bit data to memory store the upper byte at the lower address and the lower byte at the next address Handle reading of 1
88. 1 Noise filter circuit function settings shows the settings required to operate as the noise filter circuit function Figure 8 7 1 Noise filter circuit function settings Bit7 pe BitS Bits Bits Bit2 pi Bito NCCR Nest NCSO e oO Unused bit Used bit When pulse width measurement function is selected the noise filter circuit can be used to clear the noise By the selecting different value for sampling clock pulse selection bit NCSI and NCSO of noise filter control register NCCR different kind of the noise can be filtered out Integrating the sampled signal clears the noise The maximum width of the cleared noise is as follows Nw sampling clock cycle x 5 When noise clearing is prohibited the PWC input is input directly to PWC counter timer Figure 8 7 2 Operation of noise filter circuit function shows the operation of the noise filter circuit Figure 8 7 2 Operation of noise filter circuit function clock pulse value Internal signal PWC input Sampling Integrated 162 CHAPTER 8 PULSE WIDTH COUNT TIMER
89. 1CH SIOF SIOE SCKE SOE CKS1 CKSO BDS SST 000000008 R W R W R W R W R W R W R W R W SDR Serial data register Address Bit7 Bit6 Bit5 Bit4 D D Bit1 Bit 0 Initial value DO Du XXXXXXXXB R W R W R W R W R W R W R W R W R W Readable and writable X Indeterminate 174 CHAPTER 9 8 BIT SERIAL UO E 8 bit serial I O interrupt source IRQS 8 bit serial I O generates an interrupt request IRQ5 if interrupt request output is enabled SMR SIOE 1 when the I O function completes input or output of 8 bit serial data 175 CHAPTER 9 8 BIT SERIAL I O 9 3 1 Serial Mode Register SMR The serial mode register SMR is used to enable or disable operation select the shift clock set the transfer direction control interrupts and check the state of 8 bit serial UO E Serial mode register SMR Figure 9 3 3 Serial mode register SMR Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 001CH SIOF SIOE SCKE SOE CKS1 CKSO BDS SST 000000008 R W R W R W R W R W R W R W R W gt sst Serial I O transfer start bit Read Write 0 Serial transfer stopped Stops disables serial transfer 1 S
90. 225 external interrupt circuit functions of 224 external interrupt circuit operation Of 231 external interrupt circuit program example for 232 external interrupt control register EICH 228 external reset pin function 45 external reset pin block diagram of 45 external shift clock ueimg 186 external voltage divider 239 external voltage divider use of 240 F F2MC 8L instruction Overview Of 267 FPT 64P MO9 package dimension sssssssssseneeeesees 10 FPT 64P MO9 pin aseionment 8 G general purpose register areas addresses 0100H to OU REA TETTE 24 general purpose registers features Of 34 general purpose registers structure of 33 H handling device note on 18 l e hue EE 264 I O pins and pin functions s s s 12 VO port FUNCTION ed eiiieaenii iinun 70 I O port program example Tor 98 instruction Cycle ooo eee hona aeaniee 54 MiStruction map 286 instruction symbol used with 268 internal shift clock USING ccceceeeeeeeeeteeeeeees 185 internal voltage divider A 237 internal voltage divider use of 238 interrupt acceptance control Di 30 interrupt level setting registers ILR1 ILR2 ILR3 Structure of 36 interrupt processing sssssssssresserrreesrrnrrerrrnrnerennnns 37 interrupt processing Hme 40 interrupt processing stack area fOr 42 interrupts when external interrupt circuit is operating ER AE A Eed 230 interval timer fUNCTION cccceeeeeeeeee
91. 3 4 PWC pulse width control register 2 PCR2 Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0015H FC RM TO Ci co WI WO 000 0000B R W R W R W R W R W R W R W LU wil wo Measured pulse selection bits Only applies to the pulse width measurement function FC 1 0 O High level 0 1 Low level 1 0 Rising edge to rising edge 1 1 Falling edge to falling edge gt C1 CO Count clock selection bits 0 O 1 tinst 0 1 4 tinst 1 D 32 tinst 1 1 Do not use this setting tinst Instruction cycle Timer output bit TO 2I Read Write 0 Can be used to set the ra the current output output value when the 1 counter is stopped S RM Reload mode selection bit Only applies to the interval timer function FC 0 0 Reload timer mode 1 One shot timer mode gt FC Operating mode selection bit 0 Operates as an interval timer function 1 Operates as a pulse width measurement function R W Readable and writable Unused Initial value 150 FC Operating mode selection bit CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Table 8 3 2 PWC pulse width control register 2 PCR2 bits Function This bit switches between the interval timer function FC 0 and pulse width measurement function FC
92. 4 Fcy about 3 28 ms Can be selected Can be selected adi poe Reset pin output Reset output available Reset output unavailable Foy main clock oscillation frequency Can be selected Can be selected Reset output available 1 The main clock oscillation stabilization time is generated by dividing the main clock oscillation Since the oscillation cycle is unstable immediately after oscillation starts the time in this table is only a guide 2 Port segment output switching should be specified in the same manner as the port allocation set by the segment output select register in the LCD controller described on Chapter 12 LCD CONTROLLER DRIVER 3 When these pins are used as ports applied voltage should never be higher than V3 287 APPENDIX Table C 2 Recommended port segment mask option combinations Number of segments Number of I O ports CU Mask Options P00 SEG20 to P07 SEG27 P10 SEG28 to P13 SEG31 Gei P14 SEG32 to P15 SEG33 Gei P16 SEG34 P17 SEG35 P20 SEG36 to P23 SEG39 Gei P24 SEG40 to P25 SEG41 Gei O O x O O x x Se X Mask option is selected for LCD segment outputs O Mask option is selected for port outputs 1 This column of numbers assume that all the multiplexed peripherals are disabled O O x O O O x Se O O x O O O O sis O O x Ol O O O O zg O OJ xK x xK P
93. 4 3 Display RAM contents example Table 12 4 3 Display RAM contents example Display RAM contents Segment COM2 COM1 257 CHAPTER 12 LCD CONTROLLER DRIVER 258 Figure 12 4 6 Output waveforms 1 3 bias and 1 4 duty ratio example COMO COM1 COM2 COM3 SEGn SEGn 1 Difference in potential between COMO and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM2 and SEGn Difference in potential between COM3 and SEGn Difference in potential between COMO and SEGn 1 Difference in potential between COM1 and SEGn 1 Difference in potential between COM2 and SEGn 1 Difference in potential between COMS and SEGn 1 V1 to V3 V1 to V3 pin voltages 1 frame Mo 1 cycle CHAPTER 12 LCD CONTROLLER DRIVER 8 segment LCD panel connections and display data 1 4 duty ratio drive mode Figure 12 4 7 Segment common connections data states and corresponding display Example Using segments to represent 5 ol zt A NY COMO COM3 SEGn D lt 5 gt E com JET TC Ben ZN o 7 O COM2 SEGn 1 Address _COM3 COM2 COM1 COMO Address COM3 COM2 COM1 COMO nH bit3 3 bit2 2 bn bito SEGn 0644 1 J EE Oe ale 1 SEGO bit77 ez bit5 dita SEGn 1 0 0 1 1 SEG 0 to 7 Indicate corresponding display RAM bits 0 OFF
94. 4C P01 package dimension sssssseeseeen 11 MQP 64C P01 pin asslonment 9 multiple interrupts A 39 N note when changing edge polarity selection 230 O operation during standby mode or operation halt ES TE AA A E A EEN 135 163 operation mode 0 1 3 operation of 217 oscillation stabilization delay reset state 47 oscillation stabilization delay time 55 66 106 OMEN INSHHUCTION eero d e 285 P peripheral function interrupt request from 35 pin state in various mode 295 pin states after reading mode data 48 pin states during reset ce eeeeeeeeeeeeeneeeeeeeeees 48 port O data register function 74 port 0 pin block diagram of 73 eieiei EE 72 port O register eee eee eee eeeeeeceteeeeeeeeeteeeseeeereeenneaes 73 port 0 Operation of 75 port O Structure of 72 port 1 data register function 79 port 1 pin block diagram of 78 DO T PINS SEENEN EE Ae 77 POrt 1 regteter eee aa eeeeeeeeteeeseeeeeteeseeeeeteeeneeees 78 port 1 Operation of 80 port 1 Structure Of 77 port 2 data register function 84 port 2 pin block diagram of 83 Dort 2 DINS enot a E i 82 p r 2 registo re 83 port 2 Operation of 85 port 2 structure Of 82 port 3 data register function 89 port 3 pin block diagram of 87 299 INDEX pon 3 PINS wisi eeir aie eaten ees 86 Dort 3 regieter ere 88 port 3 operation Of 90 port 3 structure of 86 port 4
95. 6 bit data in the same way Figure 3 1 2 Storing 16 bit data in memory shows how 16 bit data is stored in memory Figure 3 1 2 Storing 16 bit data in memory Before execution Memory After execution Memory MOVW 0081H A 0080H 0080H 0081H 12H 0081H A 1234H 0082H A 1234H 34H 00824 0083H 0083H E Storing 16 bit operands The same byte order applies when specifying a 16 bit operand in an instruction Store the upper byte at the address following the operation code instruction and the lower byte at the next address The byte ordering applies to both 16 bit immediate data and operands that specify a memory address Figure 3 1 3 Byte order of 16 bit data in an instruction shows how 16 bit data is stored in an instruction Figure 3 1 3 Byte order of 16 bit data in an instruction Example MOV A 5678H Extended address MOVW A 1234H 16 bit immediate data After assembly XXXOH XX XX XXX2H 605678 _ Extended address XXX5H E41234 16 bit immediate data XXX8BH XX E Storing 16 bit data on stack The same byte order applies when saving 16 bit register data on the stack during an interrupt or similar The upper byte is stored in the lower address 26 CHAPTER 3 CPU 3 2 Dedicated Registers The dedicated registers in the CPU consist of the program counter PC two arithmetic operation reg
96. 7 Figure 3 3 1 Register bank structure shows the register bank structure Figure 3 3 1 Register bank structure Lower 3 bits of the operation code 100H RO 000 R1 001 R2 010 Bank 0 RP p R3 011 00000 B R4 100 R5 101 32 banks R RAM area 6 1O The number of banks is limited R7 111 on available RAM size 108H RO 000 Bank 1 RP 00001 B R7 111 Bank 2 to Bank 30 1F8H RO 000 Bank 31 RP 11111 8 1FFH R7 111 The top address of a register bank 0100H 8 x upper 5 bits of RP See Section 3 1 1 Special Areas for the general purpose register area available for each product 33 CHAPTER 3 CPU E Features of general purpose registers 34 General purpose registers have the following features e RAM can be accessed at high speed using short instructions general purpose register addressing e Registers are grouped in blocks in the form of register banks This simplifies the process of saving register contents and dividing registers by function Dedicated register banks can be permanently assigned for each interrupt processing or vector call CALLV 0 to 7 processing routine by general purpose register For example register bank 4 interrupt 2 For example a particular interrupt processing routine only uses a particular register bank which cannot be written to unintentionally by other routines The interrupt processing ro
97. Buffer Register RLBR The PWC rel oad buffer register RLBR functions as a reload register for the interval timer function and as a measurement value storage register for the pulse width measurement function E PWC reload buffer register RLBR Figure 8 3 5 PWC reload buffer register RLBR shows the bit structure of the PWC reload buffer register Figure 8 3 5 PWC reload buffer register RLBR Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0016H XXXXXXXXB R W R W R W R W R W R W R W DA For the interval timer function R R R R R R R R l For the pulse width measurement function R W Readable and writable R Read only X Indeterminate For interval timer function 152 The register functions as a reload register specifying the interval time The counter starts to count down from the set value written in this register when counter operation is enabled PCR1 EN 1 In reload timer mode the RLBR register value is reloaded to the counter and the counter continues counting down when a counter value underflows Oly gt 00y If a value is written to the RLBR register during counter operation the new value applies from the next time the counter is reloaded due to an underflow Oly gt 00y Reference The setting value of the RLBR register for the interval timer function is calculated as follows RLBR register value interval time coun
98. C1 bits Function Bit 7 PEN e In the clock asynchronous mode sets whether there is parity data or not Parity control bit Bit 6 SBL e This bit determines the stop bit length Stop bit length e In serial transmission a stop bit of the bit length specified is appended control bit e In serial reception a stop bit is recognized as in a 1 bit length regardless of the value set here Bit 5 MC1 MCO e These two bits determine the transfer mode data length Bit 4 Transfer mode control bits Bit 3 SMDE e This bit selects the UART operating mode In asynchronous mode the UART Operation mode operates on the serial clock divided by 8 In clock synchronous mode it operates on control bit the selected serial clock Bit 2 Unused bit e The read value is indeterminate e Writing to this bit has no effect on the operation Bit 1 SCKE e This bit selects either serial clock input output SCK of the serial clock synchronous Serial clock output mode or general purpose I O port P45 bit es When SCKE 0 and the DDR4 bit 5 0 the SCK functions as serial clock input Bit 0 SOE e This bit selects either serial data output SO or general purpose I O port P44 206 Serial data output bit CHAPTER 10 UART 10 4 2 Serial Rate Control Register SRC The serial rate control register SRC is to set the UART transmission speed baud rate E Serial rate control register SRC Figure 10 4 3 Serial rate control
99. CHAPTER 3 CPU 3 6 3 Oscillation Stabilization Delay Time When the system goes to run mode from a state in which the main clock is stopped such as at power on and in stop mode and etc a delay time is required for oscillation to stabilize before starting any operation E Oscillation stabilization delay time After starting ceramic crystal and other resonators typically require the time between several milliseconds and several tens of milliseconds to stabilize at their fixed oscillation frequency Therefore operation of the CPU and other functions is disabled when oscillation first starts and no clock signal is supplied to the CPU and peripheral functions until the oscillation stabilization delay time has passed and the oscillation has sufficiently stabilized The time required for oscillation to stabilize depends on the resonator type crystal ceramic etc connected to the clock generator Consequently it is necessary to select an oscillation stabilization delay time that matches the type of oscillator being used Figure 3 6 5 Operation of oscillator after starting oscillation shows the operation of an oscillator after starting oscillation Figure 3 6 5 Operation of oscillator after starting oscillation Normal operation wake up from stop mode Resonator oscillation time Oscillation stabilization delay time Or reset operation gt lt gt lt gt ww f I Oscillation starts Oscillation stabilizes
100. CUIT EDGE 11 1 Overview of the External Interrupt Circuit The external interrupt circuit detects edges on the signals input to the two external interrupt pins and generates the corresponding interrupt requests to the CPU E Functions of the external interrupt circuit The function of the external interrupt circuit is to detect specified edges on signals input to the external interrupt pins and to generate interrupt requests to the CPU These interrupts can cancel standby mode and return the device to the normal operating state RUN state External interrupt pins 2 pins P42 PWC INT1 and P46 INTO External interrupt sources Input of a specified edge rising edge or falling edge on the signal input to an external interrupt pin Interrupt control Output of external interrupt requests is enabled or disabled by the interrupt request enable bits in external interrupt control register EIC Interrupt flags Detection of specified edges sets the external interrupt request flag bits in external interrupt control register EIC Interrupt request Separate interrupt request is generated for each external interrupt source IRQO IRQ1 224 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE 11 2 Block Diagram of the External Interrupt Circuit The external interrupt circuit consists of the following two elements e Edge detect circuit 0 1 e External interrupt control register EIC E Block diagram of the external interrupt
101. DECW Ix IX lt IX 1 D2 DECW A A lt A 1 DO MULU A A lt AL x TL 01 DIVU A A lt T AL MOD gt T 11 ANDW A A lt A A T 63 ORW A A lt A V T 73 XORW A A lt A V T 53 CMP A TL AL 12 281 APPENDIX Table B 5 2 Arithmetic operation instructions Continued MNEMONIC CMPW A Operation T A OP CODE 13 RORC A gt C gt A 03 ROLC A C lt A lt c 02 CMP A d8 A d8 14 CMP A dir A dir 15 CMP A EP A EP 17 CMP A IX off A IX off 16 CMP A Ri A Ri 18 to IF DAA decimal adjust for addition 84 DAS decimal adjust for subtraction 94 XOR A A lt AL V TL 52 XOR A d8 A lt AL V d8 54 XOR A dir A lt AL V dir 55 XOR A EP A lt AL V EP 57 XOR A IX off A lt AL V IX off 56 XOR A Ri A lt AL V Ri AND A A lt AL A TL 62 AND A d8 A lt AL A d8 64 AND A dir A lt AL A dir 65 AND A EP A lt AL A EP 67 AND A IX off A lt AL A IX off 66 AND A Ri A lt AL A Ri 68 to 6F OR A A lt AL V TL 72 OR A d8
102. DR register to the SO pin synchronized with the falling edge of the selected internal shift clock At this time the device being communicated with a serial input must be waiting for input of the external shift clock External shift clock Figure 9 5 2 Serial output settings when using external shift clock shows the settings required to operate serial output using an external shift clock Figure 9 5 2 Serial output settings when using external shift clock Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit2 Biti Bit 0 aC TT x Xx 0 X X x X X SMR SIOF SIOE scxe SOE CKS1 CKSO BDS SST Used bit 0 1 1 1 1 X Unused bit 1 Set 1 SDR Sets transmit data 0 Set 0 Enabling serial output operation outputs the contents of the SDR register to the SO pin synchronized with the falling edge of the external shift clock When serial output completes reset the SDR register and enable operation SMR SST 1 promptly for output of the next data 181 CHAPTER 9 8 BIT SERIAL I O When the device being communicated with has completed the serial input operation on the rising edge hold the external shift clock at the H level while waiting for next output data idle state Figure 9 5 3 8 bit serial output operation shows the 8 bit serial output operation Figure 9 5 3 8 bit serial output operation For LSB first Bit7 Bit6 Bit5 Bit4 Bits Bit2 Biti Bito S
103. IE RIE pes he z If non parity selected in mode 3 these are interpreted as TD8 and RD8 e m m respectively MC1 and MCO should be set as follows SIDR Receive data stored mode 0 00s mode 1 01s mode 3 11s SODR Transmit data written SMC2 PSEN RSEL PDS1 PDSO 0 DDR4 E Transmit operation Writing transmit data to the SODR register after reading from SSD register transfers the data written in the SODR to the transmit shift register and initiates a parallel serial conversion process The converted transmit data is sent to the serial data output pin with its LSB Least Significant Bit followed by other bits LSB first When the SODR register gets ready for the next data the TDRE bit is set to 1 and an interrupt request is issued to CPU if interrupt enabled SSD TIE 1 Figure 10 7 2 Transmit operation in mode 0 1 3 shows the transmit operation when mode 1 non parity and 1 stop bit are selected 217 CHAPTER 10 UART Figure 10 7 2 Transmit operation in mode 0 1 3 SSD read Write to the SODR i l Interrupt processing routine Transmit buffer full TDRE Transmit interrupt Transfer the data to the transmit shift register Transfer the data to the transmit shift register Transmit data START 0010213045 6 7 STOP START E Receive operation 218 If receive data is received from the serial data in
104. L 0 Main clock Operating Operating Stop Stop Instructions Operating Stop Stop Stop ROM Operating Hold Hold Hold RAM T O ports Operating Hold Hold Hi Z D Timebase timer Operating Operating Stop Stop 8 bit PWM timer Operating Operating Stop Stop 8 bit PWC timer Operating Operating Stop Stop Peripheral functions Watchdog timer Operating Stop Stop Stop LCD controller driver Operating Operating Stop Stop External Interrupts Operating Operating Operating Operating Serial I O Operating Operating Stop Stop UART Operating Operating Stop Stop 1 If pull up is selected it will be H level Pin States in Standby Mode Almost all I O pins will either keep the state they were placed in or go to the high impedance state according to the pin state control bit of the standby control register STBC SPL just prior to going to the stop mode This is true regardless of the clock mode See Appendix E MB89950 950A Series Pin States for pin states in standby mode 58 CHAPTER 3 CPU 3 7 2 Sleep Mode This section describes the operations of sleep mode E Operation of sleep mode Entering sleep mode Sleep mode stops the CPU operating clock The CPU stops while maintaining all register contents RAM contents and pin states at their values immediately prior to entering sleep mode However peripheral functions except the watchdog timer continue to op
105. LR2 110 EQU 0000AH EQU TBTC 3 EQU 007DH DSEG ABS ORG OFFEEH DW WARI ENDS Main program CSEG CLRI MOV ILR2 11011111B MOV TBTC 00010010B SETI CLRB TBOF PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI Interrupt program Address of the timebase timer control register Define the interrupt request flag bit Address of the interrupt level setting register 2 DATA SEGMENT Set interrupt vector CODE SEGMENT Stack pointer SP etc are already initialized Disable interrupts Set interrupt level Clear interrupt request flag enable interrupt level 1 request output select 2 9 Fcu and clear timebase timer Enable interrupts Clear interrupt request flag CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer 6 1 Overview of Watchdog Timer 6 2 Block Diagram of Watchdog Timer 6 3 Watchdog Timer Control Register WDTC 6 4 Operation of Watchdog Timer 6 5 Notes on Using Watchdog Timer 6 6 Program Example for Watchdog Timer 111 CHAPTER 6 WATCHDOG TIMER 6 1 Overview of Watchdog Timer The watchdog timer is a 2 bit counter that uses as its count clock source the timebase timer derived from the main clock The watchdog timer resets the CPU if not cleared within a fixed time after activation E W
106. LR3 corresponding to the interrupt request is higher than the interrupt level bits in the condition code register CCR IL1 ILO and if the interrupt enable flag is enabled CCR I 1 the CPU branches to the interrupt processing routine If the interrupt is not accepted operation restarts from the instruction following the instruction that activated the standby mode To prevent control from branching to an interrupt processing routine after wake up take measures such as disabling interrupts before setting standby mode bit E Notes on setting standby mode When setting the standby control register STBC to go to standby mode make the settings in accordance with Table 3 7 5 Standby control register STBC low power consumption mode settings Although the order of precedence as to which mode will be activated if more than one bit is set to 1 is stop mode and sleep mode it is best to set 1 for just one bit Table 3 7 5 Standby control register STBC low power consumption mode settings STBC register STP Bit 7 SLP Bit 6 Normal Sleep Stop 65 CHAPTER 3 CPU E Oscillation stabilization delay time 66 As the oscillator that provides the oscillation source is stopped during stop mode a delay time is required for oscillation to stabilize after the oscillator restarts operation In main clock mode the main clock oscillation stabilization delay time is selected from one of two possible delay times
107. Ltd Phone 81 3 3986 0403 E Memory map in EPROM mode Table D 1 1 Memory map in EPROM mode shows the memory map in EPROM mode Write the option data in the option setting area after consulting the OTPROM option bit map Figure D 1 1 Memory map in EPROM mode The address at normal operation The address at EPROM mode 00004 Prohibition 00004 80004 Ges Vacant area Prohibition Read value FF BFFO 3FFOy Option setting area Option setting area 3FF7y BFF6 Prohibition C0004 4000 Program area PROM PROM 7FFFyY Vacant area Read value FF FFFFy 290 APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller E Recommended screening conditions High temperature aging is recommended as the pre assembly screening procedure for a product with a blanked OTPROM microcomputer program Table D 1 2 Screening procedure shows the screening procedure Figure D 1 2 Screening procedure Program verify Aging 150 C 48 Hrs Data verification Assembly E Programming to the EPROM In EPROM mode the MB89P955 function is equivalent to the MBM27C256A Programming procedure 1 Set the EPROM programmer to the MBM27C256A 2 Load program data from 4000 to 7FFFy of the EPROM writer Note that OC000y to OFFFFy in the operation mode are equivalent to 4000y to 7FFFy in the EPROM mode Load option data from 3FFOy to 3FF6y o
108. MQP 64C P01 package dimensions show the package dimensions E FPT 64P M09 package dimensions Figure 1 6 1 FPT 64P M09 package dimensions 64 pin plastic LQFP Lead pitch 0 65 mm Package width x package length TEE Lead shape Gullwing Sealing method Plastic mold O Mounting height 1 70 mm MAX FPT 64P M09 64 pin plastic LQFP FPT 64P M09 Note Pins width and pins thickness include plating thickness 14 00 0 20 551 008 SQ 12 00 0 10 472 004 SQ 0 145 0 055 0057 0022 it KR O aoaoga Details of A part l 40 20 Tiss lt tr Mounting height po EE 0 25 010 EE C Ss BI PA EE i 0 50 0 20 0 1020 10 e 020 008 004 004 0 60 0 15 Stand off 024 006 0 65 026 0 3240 05 rz i 1013 0027 110 131 0085 Ee e 2001 FUJITSU LIMITED F64018S c 2 4 Dimensions in mm inches E MQP 64C P01 package dimensions Figure 1 6 2 MQP 64C P01 package dimensions CHAPTER 1 OVERVIEW 64 pin ceramic MQFP Lead pitch 1
109. O transfer SMR SST 1 When using an external shift clock and when serial data output is enabled SMR SOE 1 the output level on the SO pin when the external shift clock is the most significant bit when MSB first is selected or least significant bit when LSB first is selected This applies even if serial transfer is stopped SMR SST 0 The interrupt request flag bit SMR SIOF is not set if serial I O transfer is stopped SMR SST 0 at the same time as serial transfer data completes Interrupt processing cannot return if the SIOF bit is 1 and the interrupt requests enable bit is enabled SIOE 1 Always clear the SIOF bit idle state of shift clock Hold the external shift clock at the H level during the delay time between transfers of 8 bit data idle state When set as the shift clock output SMR SCKE 1 the internal shift clock SMR CKS1 CKSO other than 11 output an H level during the idle state Figure 9 8 1 Idle state of shift clock shows the idle state of the shift clock Figure 9 8 1 Idle state of shift clock Idle state 8 bit data transfer Idle state 8 bit data transfer Idle state 9 9 CHAPTER 9 8 BIT SERIAL UO Connection Example for 8 bit Serial UO This section shows an example of connecting together two MB89950 950A series 8 bit serial UO and performing bi directional serial I O Bi directional serial UO performing Figure 9 9 1 Conn
110. OFFFOH WARI SST ILR2 11110111B SDR 55H SMR 01111000B SST SIOF A A T A SDR 55H SST User processing POPW XCHW CHAPTER 9 8 BIT SERIAL I O Serial mode register Serial data register Define the interrupt request flag bit Define the serial I O transfer start bit Address of the interrupt level setting register 2 DATA SEGMENT Set interrupt vector CODE SEGMENT Stack pointer SP etc are already initialized Disable interrupts Stop serial I O transfer Set interrupt level level 1 Set transfer data 55H Clear Interrupt request flag enable interrupt request output enable shift clock output SCK enable serial data output SO select 32 tinst LSB first Start serial I O transfer Enable interrupts Clear interrupt request flag Save A and T Reset transfer data 55H Start serial I O transfer Restore A and T 191 CHAPTER 9 8 BIT SERIAL I O E Program example for serial input Proces sing description Inputs 8 bit serial data from the SI pin of serial I O then generates an interrupt when transfer is completed The interrupt processing routine reads the transferred data and continues transfer Serial I O uses the external shift clock The shift clock is input from the SCK pin Coding example DDR4 SMR SDR SIOF SST ILR2 192 EQU 000FH EQU 001CH EQU
111. Opin SDR 7 6 5 4 3 2 1 0 LI Serial output E lt lt KE E Ei Xs E Ei data Cleared by the program SIOF bit Transfer start 4 nterrupt request SST bit Automatically cleared when transfer completes E Operation at completion of serial output 182 The 8 bit serial I O sets the interrupt request flag bit SMR SIOF 1 and clears the serial I O transfer start bit SMR SST 0 on the rising edge of the shift clock after the serial data of the eighth bit is output CHAPTER 9 8 BIT SERIAL UO 9 6 Operation of Serial Input The 8 bit serial I O can perform serial input of 8 bit data synchronized with a shift clock E Serial input operation Serial input can operate using an internal or external shift clock When serial in operation is enabled input from the serial data input pin SI is stored in SDR register Serial output is performed at the same time Internal shift clock Figure 9 6 1 Serial input settings when using internal shift clock shows the settings required to operate serial input using an internal shift clock Figure 9 6 1 Serial input settings when using internal shift clock Bit 7 Bit 6 BitS Bit4 Bit 3 Bit 2 Bit 1 Bit 0 DDR4 X X X X 0 X x X SMR SIOF SIOE SCKE SOE CKS1 CKSO BDS SST Used bit 1 3 other th
112. P gem 9y py dk EM Dy py up Yy ID MAOW WON WOH o dno AON Yo d Yox AON 29 od dp AON gp y vm poy ap pi BPV my IBP Y spy lapay gou ot MAON WON WOH syd KEN HO a HON We od dp AON yd A di ap EI v v L Vo WON moa Mo WON 1 MAON Md MOO MdNO 3808 vu ap EI v v Lg WOH MoJa Mo AON AON HON We od dN OH vd US ap ee gluppe oU WON moa Mo oas Hm MdOd Two D MNW vO df M930 MdOd E dON 286 APPENDIX C Mask Options APPENDIX C Mask Options This appendix lists the mask options for the MB89950 950A series E Mask options Table C 1 Mask options Part number MB89951A MB89953A MB89P955 MB89PV950 Specifying procedure Port pull up resistor P40 to P46 Specify when ordering mask Can be selected for each pin Set with EPROM programmer Can be selected for each pin Setting not possible No pull up resistor Port Segment output POO to P07 P10 to P17 P20 to P25 Can be selected for every 8 to 1 pins SS Port segment output put Port segment output C3 Power on reset Power on reset available Power on reset unavailable Can be selected Can be selected Power on reset available Selection of main clock oscillation stabilization time at 5 MHz P About 2 8 Fcy about 52 4 ms About 2
113. PWM timer function show the counter value states when the device goes to sleep or stop mode or an operation halt request occurs during operation of the interval timer function or PWM timer function The counter halts and maintains its current value when the device goes to stop mode Operation starts again from the stored counter value after wake up from stop mode by an external interrupt Therefore the first interval time or PWM wave cycle does not match the set value Always initialize the 8 bit PWM timer after wake up from stop mode For interval timer function Figure 7 7 1 Counter operation during standby mode or operation halt for interval timer function Counter value COMR value FFH l Cleared by the operation halt be gt FFH ee EE Ee oon L_ Es i gt lt Time EEN i Oscillation stabilization Timercycle Stop request delay time 1 Cleared by the program 1 f 1 Operation halts Operation restarts 1 1 TIR bit l TPE bit PWM pin PE i Sleep mode lt SC OE 1 l L while counter is st copped SLP bit a STBC register nea ata Wake up from sleep mode by IRQ2 STP bit STBC register Wake up from stop mode by an external interrupt The PWM pin PWM goes to the high impedance state during stop mode if the pin state specification bit in the standby control register
114. Ports 4 2 Port 0 4 3 Port 1 4 4 Port 2 4 5 Port 3 4 6 Port 4 4 7 Program Example for I O Ports 69 CHAPTER 4 I O PORTS 4 1 Overview of I O Ports The I O ports consist of five ports 33 pins including N ch open drain and CMOS general purpose I O ports parallel I O ports The ports also serve as peripherals I O pins of peripheral functions E I O port functions The functions of the I O ports are to output data from the CPU via the I O pins and to fetch signals input to the I O pins into the CPU Input and output are performed via the port data registers PDR Also for certain ports the direction of each I O pin can be individually set to either input or output for each bit by the port data direction register DDR The following lists the functions of each port and the peripheral with which the ports also serve as e Port 0 General purpose N ch open drain I O port Also serves as LCD segment driver pins e Port 1 General purpose N ch open drain I O port Also serves as LCD segment driver pins e Port 2 General purpose N ch open drain I O port Also serves as LCD segment driver pins e Port 3 General purpose N ch open drain I O port Also serves as LCD bias pins e Port 4 General purpose CMOS I O port Also serves as other peripheral I O pins Table 4 1 1 Port function lists the functions of each port and Table 4 1 2 Port registers lists the registers for each port Table 4 1 1 Port function
115. R1 SL11 SL10 EIE1 EIRO SLO1 SLOO EIEO Used bit If the polarity of an edge on the input signal to one of the external interrupt pins INTO INT1 matches the edge polarity specified for the pin in the external interrupt control register EIC SL11 SL10 SLO1 SLOO the external interrupt circuit sets the external interrupt request flag bit EIC EIRO EIR1 to 1 The external interrupt request flag bit is set when the edge polarity match occurs regardless of the value of the interrupt request enable bit EIC ETEO EIE1 Figure 11 5 2 External interrupt INT1 operation shows the operation when an external interrupt is input to the INT1 pin Figure 11 5 2 External interrupt INT1 operation Input waveform EES l tothe INT1 pin Cleared at the same time Interrupt request flag bit is cleared as the EIE1 bit is set 1 by the program 1 1 1 v y i y EIR1 bit Sek EIE1 bit SL11 bit l SL10 bit a S IRQ1 Rising edge set lt _ gt Falling edge set Reference The pin state can be read directly from the port data register PDR4 even when used as an external interrupt input 231 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE 11 6 Program Example for the External Interrupt Circuit This section gives a program example fo
116. ROCONTROLLER MB89950 950A Series HARDWARE MANUAL July 2002 the first edition Published FUJITSU LIMITED Electronic Devices Edited Technical Information Dept
117. SEG 8 segment LCD data LCDDATA DB 11111B ak Ve DB 1000B SE DB 110B ene DB 1100B e DB 11101001B ETAT DB 01111101B e bh DB 01111111B GE DB 11011001B eit DB 11111111B Ae DB 11111101B i DB 00000000B END LCD SEG ENDS Main program CSEG CODE SEGMENT MOVW EP LCRAM Set LCD RAM address MOVW IX LCDDATA Set LCD data table address MOV SEGR 01111111B Set the segment output function LCDSET MOV A IX 00H MOV EP A INCW EP INCW IX BNZ CDSET Continue until data end 00H is detected MOV LCDR 00101111B Set LCDR and turn LCD display on 261 CHAPTER 12 LCD CONTROLLER DRIVER 262 APPENDIX This appendix includes I O maps instruction lists and other information APPENDIX A I O Map APPENDIX B Overview of Instructions APPENDIX C Mask Options APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller APPENDIX E MB89950 950A Series Pin States 263 APPENDIX APPENDIX A UO Map Table A 1 I O map lists the addresses of the registers of used by the internal peripheral functions of the MB89950 950A series E I O map Table A 1 I O map 1 2 Address Register name Register description Port 0 data register Read Write Initial value 11111111lp Vacancy Port 1 data register 11111111lp Vacancy 04H Port 2 data register 111111p
118. STBC SPL is 1 H level if pull up is selected for PWM pin When the SPL bit is 0 the pin maintains its value prior to entering stop mode 135 CHAPTER 7 8 BIT PWM TIMER For PWM timer function Figure 7 7 2 Operation during standby mode or operation halt for PWM timer function 00H 00H 00H 00H OOH PWM pin PWM waveform 1 Maintains the level prior to halting TPE bit A Operation halts Operation restarts Sleep mode lt S gt SLP bit STBC register e gt 1 1 1 1 1 1 i 1 1 1 1 1 1 1 1 1 1 fi 1 Wake up from sleep mode by an interrupt other than IRQ2 IRQ2 is not generated i Stop mode e ks STP bit i i STBC register gt lt Oscillation stabilization delay time Wake up from stop mode by an external interrupt The PWM pin PWM goes to the high impedance state during stop mode if the pin state specification bit in the standby control register STBC SPL is 1 H level if pull up is selected for PWM pin When the SPL bit is 0 the pin maintains its value prior to entering stop mode 136 CHAPTER 7 8 BIT PWM TIMER 7 8 Notes on Using 8 bit PWM Timer This section lists points to note when using the 8 bit PWM timer E Notes on using 8 bit PWM timer Error Activating the counter by program is not synchronized with the s
119. Serial mode control register 2 SMC2 bits Unused bits Function The read value is indeterminate Writing to these bits has no effect on the operation PSEN Operation enable bit This bit enables baud rate generator Baud rate generator is stopped by writing 0 to this bit after transmitting receiving the current serial data then disabled thereafter Reserved bit Always write 0 RSEL UART SIO selection bit The bit is used to select whether the UART or serial I O uses the data and clock I O pins Unused bit The read value is indeterminate Writing to this bit has no effect on the operation 214 PDS1 PDSO Input clock divider selection bits These bits are used to select the clock prescaler of the baud rate generator CHAPTER 10 UART 10 5 UART Interrupts The UART has three interrupt causes transfer error interrupt receive data full interrupt and transmit data empty interrupt e When receive data is transferred from the receive shift register to the serial input data register SIDR receive interrupt e When transmit data is transferred from the serial output data register SODR to the transmit shift register transmit interrupt E Transmit interrupt When transmission is enabled writing transmit data to SODR register transfers the transmit data to the transmit register The transmit data is converted to serial in the transmit shift register and sent to the serial
120. Set o On activation the RLBR register value is loaded to the counter and the counter starts to count down on the rising edge of the selected count clock When the counter value underflows Oly gt Ou the counter inverts the timer output bit PCR2 TO value automatically clears the counter operation enable bit PCR1 EN 0 to stop counter operation and sets the underflow Oly gt 00y interrupt request flag bit PCR1 UF 1 on the next rising edge of the count clock Figure 8 5 4 Operation in one shot timer mode shows the operation in one shot timer mode 157 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Figure 8 5 4 Operation in one shot timer mode Counter value FRY _ ___ ___ _ 80H 2 2 2 2 5 4 EEGEN 00H gt b f i i i Time Timer cycle RLBR value is modified FFH gt 80H RLBR value FFH Cleared by the program i i i i i UF bit p i EN bit g Automatic clear Reactivate Automatic clear Reactivate Automatic clear TOE bit J Invert Reactivates with the initial value unchanged Vo TO bit For an initial value of 1 on activation If the PWC reload buffer register RLBR value is modified during operation the new value will be effective in next cycle Note Do not modify PCR2 when the counter is operating PCR1 EN 1 Refere
121. The register functions as the receive data register When serial I O transfer starts SMR SST 1 the received serial transfer data is stored in this register During serial I O transfer Do not write data to the SDR register during serial I O transfer operating Also the read value has no meaning 179 CHAPTER 9 8 BIT SERIAL I O 9 4 8 bit Serial I O Interrupts The 8 bit serial I O can generate interrupt requests after completion of the serial input and output of the 8 bit data E Interrupt for serial output operation The 8 bit serial I O performs the serial input operation and serial output operation at the same time When the serial transfer starts the data in the serial data register SDR is input and output one bit at a time synchronized with the cycle of the selected shift clock The interrupt request flag bit SMR SIOF is set to 1 on the rising edge of the shift clock of the eighth bit At this time an interrupt request IRQ5 to the CPU is generated if the interrupt request enable bit is enabled SMR SIOE 1 Write 0 to the SIOF bit in the interrupt processing routine to clear the interrupt request The SIOF bit is set after completing 8 bit serial output regardless of the SIOE bit value Reference The interrupt request flag bit is not set SMR SIOF 1 if serial transfer is stopped SMR SST 0 at the same time as serial data transfer completes for the serial I O operation An interrupt reques
122. U accepts interrupt Interrupt is prohibited when this flag is set to 0 and the CPU does not accept interrupt The initial value after a reset is 0 Normal practice is to set the flag to 1 by the SETI instruction and clear to 0 by the CLRI instruction Interrupt level bits IL1 ILO These bits indicate the level of the interrupt currently being accepted by the CPU The value is compared with the interrupt level setting registers ILR1 to ILR3 which have a setting for each peripheral function interrupt request IRQO to IRQB Given that the interrupt enable flag is enabled I 1 the CPU only performs interrupt processing for interrupt requests with an interrupt level value that is less than the value of these bits Table 3 2 1 Interrupt level lists the interrupt level priorities The initial value after a reset is 11g Table 3 2 1 Interrupt level Interrupt level Priority Low no interrupt 30 CHAPTER 3 CPU Reference The interrupt level bits IL1 ILO are normally 11 when the CPU is not processing an interrupt during main program execution See Section 3 4 Interrupts for details on interrupts 31 CHAPTER 3 CPU 3 2 2 Register Bank Pointer RP The register bank pointer RP located in the upper 8 bits of the program status PS indicates the address of the general purpose register bank currently in use The RP is converted to form the actual address in general pur
123. VSEL e This bit controls the use of the internal voltage divider Writing a 1 to it enables the LCD drive supply use of the internal voltage divider Writing a 0 to it disables the use of the internal voltage control bit voltage divider Note This bit must be 0 in order to isolate the internal voltage divider when external voltage divider is used Bit 4 BK e Blanks unblanks the LCD Display blanking e Setting this bit to 1 blank outputs a deselect waveform to the LCD segments selection bit which blanks the display Bit 3 MS1 MSO e Selects one of three output waveform duty ratio modes The mode selected affects Bit 2 Display mode the common pins used Setting both bits to 0 turns off the display stops LCD selection bits controller driver display operation Note Before going to a mode in which the selected frame cycle generate clock oscillator is stopped stop mode etc these bits should be written to 00 to turn off the display Bit 1 FP1 FPO e These bits select one of four LCD frame cycles Bit O Frame cycle selection Note bits To determine this register setting calculate the optimum frame frequency for the LCD module you are using Note that the frame cycle is a function of main clock frequency 245 CHAPTER 12 LCD CONTROLLER DRIVER 12 3 2 Segment Output Select Register SEGR Segment output select register SEGR is used to select N ch open drain I O port function or segment output function for
124. When performing pulse width measurement the value of the 8 bit down counter is transferred to the RLBR register when measurement completes PCR1 and PCR2 register These registers are used to select the function set operating conditions enable or disable operation control interrupts and to check the PWC status NCCR register This register is used to select sampling clock pulse for the noise filter circuit 145 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 3 Structure of Pulse Width Count Timer This section describes the pins pin block diagram registers and interrupt source of the pulse width count timer E Pulse width count timer pin The pulse width count timer uses the P42 PWC INT1 pin This pin can function either as CMOS general purpose I O port P42 or external interrupt INT1 or as the measured pulse input PWC PWC The pulse width measurement function measures the pulse widths input to this pin Set the pin as an input port in the port data direction register DDR4 bit 2 0 when using as the PWC pin for the pulse width measurement function E Block diagram of pulse width count timer pin Figure 8 3 1 Block diagram of pulse width count timer pin Gem External interrupt enable To external interrupt lt x To peripheral input El PDR Port data register Pull up resistor l ek mode SPL 1 Approx 50 kQ N i Mask option PDR read Ee
125. XXXXXXXpB H Read only X Indeterminate This register stores received data Serial data received from the serial data input pin is converted to parallel in the shift register and stored in this register Operation in mode 0 and 1 If received data is normally set in this register the receive data flag bit RDRF is set to 1 and a receive interrupt request occurs if it is enabled When the interrupt request is detected check the RDRF bit in an interrupt processing or in a program If there is receive data stored in this register read this register and then the RDRF flag is cleared automatically 211 CHAPTER 10 UART 10 4 5 Serial Output Data Register SODR The serial output data register SODR is used to output transmit serial data E Serial output data register SODR Figure 10 4 6 shows the bit allocations of the serial output data register Figure 10 4 6 Serial output data register SODR Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0023H XXXXXXXXpB W W W W WwW W W W W Write only Indeterminate x lt When transmission is enabled writing transmit data to this register transfers the transmit data to the transmit register The transmit data is converted to serial in the transmit shift register and sent to the serial data output pin SO Writing transmit data to the SODR register se
126. XXXXXXpP 1719H LCD control register 0010000g TAY Segment output select register 0000000p TBH Vacancy 71Cy Interrupt level setting register 1 11111111g 7Dy Interrupt level setting register 2 WwW 11111111g TEY Interrupt level setting register 3 WwW 11111111g TFH Interrupt test register Read write access symbols R W Readable and writable R Read only W Write only Initial value symbols 0 The initial value of this bit is 0 1 The initial value of this bit is 1 X The initial value of this bit is undefined Unused Note Do not use vacancies Access prohibited XXXXXX00p 265 APPENDIX APPENDIX B Overview of Instructions Appendix B describes the instructions used by the F2MC 8L B 1 Overview of F2MC 8L Instructions B 2 Addressing B 3 Special Instructions DA Bit Manipulation Instructions SETB CLRB B 5 F MC 8L Instructions B 6 Instruction Map 266 APPENDIX B Overview of Instructions BI Overview of F2MC 8L Instructions The F2MC 8L supports 140 types of instructions E Overview of F2MC 8L instructions The F7MC 8L has 140 1 byte machine instructions 256 byte instruction map An instruction code consists of an instruction and zero or more operands that follow Figure B 1 1 Relationship between the instruction codes and the instruction map shows the relationship between the instruction codes
127. a reset If reset occurs during a write to RAM the contents of the RAM address cannot be assured E Overview of reset operation Figure 3 5 2 Reset operation flow diagram Software reset External reset input Watchdog reset Power on reset selected During reset operation Power on or stop mode Power on reset optional Main clock oscillation stabilization delay reset state Main clock oscillation stabilization delay reset state Wakes up from external reset Fetch mode data Mode fetch reset operation l Fetch reset vector EE I Normal operation RUN state Fetch the instruction code from the address indicated by the reset vector and begin execution 46 CHAPTER 3 CPU E Mode pin The MB89950 950A series devices are single chip mode devices The mode pin MODA must be tied to Vss The mode pin settings determine whether the mode data and reset vector are read from internal ROM Do not change the mode pin settings even after the reset has completed E Mode fetch When the CPU wakes up from a reset the CPU reads the mode data and reset vector from internal ROM Mode data address FFFDp Always set the mode to 00y single chip mode Reset vector address FFFE upper FFFFy lower Contains the address where execution is to start after completi
128. addressing is indicated by rel in the instruction list This addressing is used to branch to within the area between the address 128 bytes higher and that 128 bytes lower relative to the address contained in the PC program counter In this addressing mode the result of a signed addition of the contents of the operand to the PC is stored in the PC Figure B 2 9 Example of relative addressing shows an example Figure B 2 9 Example of relative addressing BNE FEH Vv 9ABCH FFFEH Previous PC 9 A Butz gt Current PC 9 A BAH In this example a branch to the address of the BNE operation code occurs thus resulting in an infinite loop Inherent addressing Inherent addressing is indicated as the addressing without operands in the instruction list This addressing is used to perform the operation determined by the operation code In this addressing mode different operations are performed via different instructions Figure B 2 10 Example of inherent addressing shows an example Figure B 2 10 Example of inherent addressing NOP Previous PC 9 A B CH Current PC 9 A B DH 273 APPENDIX B 3 Special Instructions This section describes the special instructions used for other than addressing E Special instructions JMP A This instruction sets the contents of A accumulator to PC program counter as the address and causes a branch to that
129. ages at V1 to V3 pins E Display brightness adjustment when internal voltage divider is used When internal voltage divider does not provide sufficient LCD display brightness connect an external brightness adjust variable resistor between Vcc and V3 as shown in Figure 12 2 4 Use of internal voltage divider with brightness adjustment Figure 12 2 4 Use of internal voltage divider with brightness adjustment Vcc VR V3 V3 _ R V2 c v2 R Vi Vi H LCD enable N ch MB89950 950A series When display brightness adjustment is desired V1 to V3 Voltages at V1 to V3 pins 238 CHAPTER 12 LCD CONTROLLER DRIVER 12 2 2 LCD Controller Driver External Voltage Divider External voltage divider can also be used with devices that have internal voltage divider Display brightness can be adjusted by a variable resistor VR connected between the Vcc and V3 pins E External voltage divider When you do not wish to use the internal voltage divider external voltage divider resistors can be connected at the LCD drive voltage supply pins V1 to V3 Figure 12 2 5 External voltage divider connection shows connection for external voltage divider for the two biasing modes and Table 12 2 1 LCD drive voltages and biasing modes lists the corresponding LCD drive voltages Figure 12 2 5 External voltage divider connection Vcc Vcc
130. ake up from low power consumption mode with an edge detection function Standby mode low power mode e Stop mode oscillation stops so as to minimize the current consumption e Sleep mode CPU stops so as to reduce the current consumption to approx 1 3 of normal 1 0 ports max 33 channels e General purpose I O ports N ch open drain 22 Also serve as segment pins e General purpose I O ports N ch open drain 4 2 also serve as LCD bias pins e General purpose I O ports CMOS 7 6 also serve as peripheral pins CHAPTER 1 OVERVIEW 1 2 MB89950 950A Series Product Range The MB89950 950A series contains 4 different models Table 1 2 1 MB89950 950A series product line up lists the product range and Table 1 2 2 Common specifications for the MB89950 950A series lists the common specifications E MB89950 950A series product range Table 1 2 1 MB89950 950A series product line up Part number MB89951A MB89953A MB89P955 MB89PV950 2 Classification Mask ROM OTP Piggy back ROM size 4K x 8 bits 8K x 8 bits 16K x 8 bits 32K x 8 bits internal mask ROM internal mask ROM internal OTP external ROM RAM size 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits Low power consumption Sleep mode and stop mode Standby mode Process CMOS Operating voltage 2 7 V to 5 5 V 2 7 V to 6 0 V 1 Varies with conditions such as operating frequencies 2 Use MBM27C256A as the ext
131. al timer function Processing description e Generates repeated interval timer interrupts at 2 5 ms intervals e Outputs a square wave to the PWM pin that inverts after each interval time e With a main clock oscillation frequency Foy of 5 MHz and the highest speed clock selected by the speed shift function 1 instruction cycle time 4 Fcy the COMR register is set for an interval time of approximately 5 ms an internal clock period of 64 tj is selected as the count clock The COMR register setting is calculated as follows COMR register value 5 ms 64 x 4 5 MHz 1 97 0614 138 Coding exampl e CNTR EQU 0012H COMR EQU 0013H TPE EQU CNTR 3 TIR EQU CNTR 2 ILR1 EQU 007CH INT_V DSEG ABS ORG OFFF6H IRQ2 DW WARI INT_V ENDS Main program CSEG CLRI CLRB TPE MOV MOV MOV SETT Interrupt program WARI CLRB PIR PUSHW A XCHW A r PUSHW A User processing POPW XCHW POPW RETI ENDS ILR1 11011111B COMR 061H i CNTR 00101011B CHAPTER 7 8 BIT PWM TIMER Address of the PWM control register Address of the PWM compare register Define the counter operation enable bit Define the interrupt request flag bit Address of the interrupt level setting register 3 DATA SEGMENT Set interrupt vector CODE SEGMENT Stack pointer SP etc are already initialized Disable interrupts Stop counter operation Set interrupt level le
132. am status can only be accessed by the MOVW A DS and MOVW PS A instructions Refer to the FMC 8L MB89600 series Programming Manual for details on using the dedicated registers CHAPTER 3 CPU 3 2 1 Condition Code Register CCR The condition code register CCR located in the lower 8 bits of the program status PS consists of the C V Z N and H bits indicating the results of arithmetic operations and the contents of transfer data and the I IL1 and ILO bits for control whether or not the CPU accepts interrupt requests E Structure of condition code register CCR Figure 3 2 2 Structure of condition code register RP CCR Bit15 Bit 14 Bit 13 Bit 12 Bit 11 Bit10 Bit9 Bit8 Bit7 Bit6 BitS Bit4 Bit3 Bit2 Bit1 Bito CCR initial value ps R4 R3 RR R1 RO H 1 majiio N Zz vd c yoaxxxxe Half carry flag Interrupt enable flag Interrupt level bits Negative flag Zero flag X Indeterminate Overflow flag Unused Carry flag E Arithmetic operation result bits Half carry flag H Set to 1 when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an arithmetic operation Clear to 0 otherwise As this flag is for the decimal adjustment instructions do not use this flag in cases other than addition or subtraction Negative flag N Set to 1 if the most si
133. an 11 1 X Unused bit 1 Set 1 SDR Stores the received data 0 Set 0 Starting serial input operation stores the value of the serial data input pin SI to the SDR register synchronized with the rising edge of the selected internal shift clock At this time the device being communicated with a serial output must have data set in the SDR register and be waiting for input of the external shift clock External shift clock Figure 9 6 2 Serial input settings when using external shift clock shows the settings required to operate serial input using an external shift clock Figure 9 6 2 Serial input settings when using external shift clock Bit 7 Bit 6 BitS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DDR4 X X 0 x 0 X X X SMR SIOF SIOE SCKE SOE CKS1 CKSO BDS SST Used bit 0 X 1 1 1 X Unused bit SDR Shows the received data E 0 Set 0 Enabling serial input operation stores the data on the SI pin to the SDR register synchronized with the rising edge of the external shift clock When serial input completes read the SDR register and enable operation SMR SST 1 promptly to input next data 183 CHAPTER 9 8 BIT SERIAL I O During this time hold the external shift clock at the H level while waiting for the next data idle state Figure 9 6 3 8 bit serial input operation shows the 8 bit serial input operation Figure 9 6 3 8 bit
134. and the instruction map Figure B 1 1 Relationship between the instruction codes and the instruction map 0 to 2 bytes which are assigned depending on the instruction A 1 byte P S Instruction code Machine instruction Operand Operand Higher 4 bits Instruction map Lower 4 bits lt e The instructions are classified into four types transfer arithmetic branch and other e A variety of addressing methods is available One of ten addressing modes can be selected depending on the selected instruction and specified operand s e Bit manipulation instructions are provided They can be used for read modify write operations e Some instructions are used for special operations 267 APPENDIX E Symbols used with Instructions Table B 1 1 Symbols in the instruction list lists the symbols used in the instruction code descriptions in Appendix B Table B 1 1 Symbols in the instruction list Direct address 8 bits Offset 8 bits Extended address 16 bits Vector table number 3 bits Immediate data 8 bits Immediate data 16 bits Bit direct address 8 bits 3 bits Branch relative address 8 bits Register indirect addressing examples A IX EP Accumulator 8 or 16 bits which are determined depending on the instruction being used Higher 8 bits of the accumulator 8 bits Lower 8 bits of the accumulator 8 bits
135. ase timer consists of the following four blocks e Timebase timer counter e Counter clear circuit e Interval timer selector e Timebase timer control register TBTC E Block diagram of timebase timer 102 Figure 5 2 1 Block diagram of timebase timer gt gt To PWC Timebase WE To watchdog timer timer counter gt To LCD controller driver Divide by x2 x22 x 23 x 24 x 28 x 26 x 29 x 20 x 2 x 212 x 213 x 214 x 215 x 216 x 217 x 218 x 219 x 220 two FCH i 1 e RON EES SS ea Ee Se ee Se De ee ee ee e euler an oe ie Se Ser EE EE OF OF OF OF Counter clear L s To clock controller for the oscillation stabilization delay time selector E Power on reset gt lt Counter _ Interval Stop mode start clear circuit timer selector Le A Timebase timer interrupt Gen OF Overflow TBTC TBIF TBIE TBR TBC1 TBCO FcH Main clock oscillation frequency Timebase timer counter A 20 bit up counter that uses the divide by two main clock oscillation frequency as a count clock The counter stops when the main clock oscillator is stopped Counter clear circuit In addition to being cleared by setting the TBTC register TBR 0 the counter is cleared when device goes
136. asuring long pulse width falling edge to falling edge shows the operation when the measured pulse selection bits PCR2 W1 WO are set to 11 falling edge to falling edge CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Figure 8 6 3 Measuring long pulse width falling edge to falling edge One cycle Input pulse Input waveform to the PWC pin y EN bit Counter value FFy Software counter value Set 0 UF bit r x Cleared by the program Cleared by the program IR bit BF bit A Data transferred from down counter io BLBR RLBR read Figure 8 6 4 Measuring long pulse width rising edge to rising edge shows the operation when the measured pulse selection bits PCR2 W1 WO are set to 10 rising edge to rising edge Figure 8 6 4 Measuring long pulse width rising edge to rising edge Input pulse id Wo Input waveform to the PWC pin EN bit l l l l FFy A l 0 1 gt IR bit AA AA Cleared by the program BF bit A A Data transferred from RLBR read down counter to RLBR 161 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 7 Operation of Noise Filter Circuit This section describes the operations of noise filter circuit function when the pulse width measurement function is selected E Operation of noise filter circuit function Figure 8 7
137. atchdog timer function 112 The watchdog timer is a counter provided to guard against program runaway Once activated the counter must be repeatedly cleared within a fixed time interval If the program becomes trapped in an endless loop or similar and does not clear the counter within the fixed time the watchdog timer generates a four instruction cycle watchdog reset to the CPU The timebase timer output can be selected as the watchdog timer count clock Table 6 1 1 Watchdog timer interval time lists the watchdog timer interval times If not cleared the watchdog timer generates a watchdog reset at a time between the minimum and maximum times listed Clear the counter within the minimum time given in the table Table 6 1 1 Watchdog timer interval time Count clock Timebase timer output main clock oscillation frequency at 5 MHz Minimum time Approx 419 43 ms D Maximum time Approx 838 86 ms 1 Divide by two of the main clock oscillation frequency Fcp x timebase timer count value 229 See Section 6 4 Operation of Watchdog Timer for the details on the minimum and maximum time of the watchdog timer interval times Reference The watchdog timer counter is cleared whenever the device goes to sleep or stop mode Operation halts until the device returns to normal operation RUN state CHAPTER 6 WATCHDOG TIMER 6 2 Block Diagram of Watchdog Timer The watchdog timer consists of the following four blocks
138. ate specification bit in the standby control register STBC 226 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE Reference Pins with a pull up resistor go to the H level pull up state rather than to the high impedance state when the output transistor is turned OFF E External interrupt circuit register Figure 11 3 2 External interrupt circuit register EIC External interrupt control register Address Bit7 Bit6 BitS Bit4 Bit3 Bit2 Biti BitO Initial value 0030H EIR1 SL11 SL10 EIE1 EIRO SLO1 SLOO EIEO 000000008 RW RW RW RW RW RW RW RW gt gt IRQ1 IRQO INT1 INTO E External interrupt circuit interrupt sources IRQO This interrupt request is generated if an edge of the selected polarity is input to the external interrupt pin INTO when output of interrupt requests is enabled IRQ1 This interrupt request is generated if an edge of the selected polarity is input to the external interrupt pin INT1 when output of interrupt requests is enabled 227 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE 11 3 1 External Interrupt Control Register EIC External interrupt control register EIC is used to select the edge polarity and to control interrupts for external interrupt pins INTO INT1 E External interrupt control register EIC Figure 11 3 3 External interrupt control register EIC Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Biti Bit 0 Initia
139. cal characteristics and vari ous examples of this product O F MC 8L Programming Manual manual including instructions for the F MC 8L family FR F MC Family Softune C Compiler Manual required only if C language is used for develop ment manual describing how to develop and activate programs in the C language FR F7MC Family Softune Assembler Manual for V3 manual describing program development using the assembler language FR F MC Family Softune Linkage Kit Manual for V3 manual describing functions and opera tions of the assembler linker and library manager Manuals with the mark are attached to each product Other manuals such as those for development are attached to respective products Software required for development Check field CT Softune V3 Workbench CT Softune V3 for personal ICE required only if the evaluation is performed for the personal ICE q Softune V3 for compact ICE required only if the evaluation is performed for the compact ICE The type of software product is dependent on the OS to be used For details see the FMC Development Tool Catalog or Product Guide O What is needed for evaluation on the one time PROM microcomputer if the programming operation is performed at your side Check field CH MB89P955 CT EPROM programmer Programmer available for the MBM27C1001 CT Package conversion adapter ROM 64QF2 28DP 8L3 Development tools Check field CT MB89PV950 piggyback e
140. chapter describes points to note when using the general purpose single chip microcontroller 2 1 Notes on Handling Devices CHAPTER 2 HANDLING DEVICES 2 1 Notes on Handling Devices This section lists points to note regarding the power supply voltage pins and other device handling aspects E Notes on handling devices Preventing latch up Latch up may occur on CMOS ICs if voltage higher than Vcc or lower than Vgg is applied to input and output pins other than medium to high voltage pins or if higher than the voltage which shows on Absolute Maximum Ratings is applied between Vcc and Vss When latch up occurs supply current increases rapidly and might thermally damage elements Take great care not to exceed the absolute maximum ratings in circuit operation Treatment of unused input pins Leaving unused input pins open could cause malfunctions They should be connected to pull up or pull down resistor Power supply voltage fluctuations Although Vcc power supply voltage is assured to operate within the rated a rapid change to the IC is therefore cause malfunctions even if it occurs within the rated range Stabilizing voltage supplied of the IC is therefore important As stabilization guidelines it is recommended to control power so that Vcc ripple fluctuations P P value will be less that 10 of the standard Vcc value at the commercial frequency 50 to 60 Hz and the transient fluctuation rate will be les
141. circuit Figure 11 2 1 Block diagram of the external interrupt circuit Edge detect circuit 0 im Z 10 Pin d tal P46 INTO gt Selector Edge detect circuit 1 Z J o0 a 1 Pin P42 PWC INT1 V EIR1 SL11 SL10 EIE1 EIRO SLO1 SLOO EIEO EIC H _ IRQO e IRQ1 gt Selector gt Edge detect circuit If the polarity of an edge on the input signal to one of the external interrupt pins INTO INT1 matches the edge polarity specified for the pin in the EIC register SLO1 SLOO SL11 SL10 the edge detect circuit sets the corresponding external interrupt request flag bit EIRO EIR1 to 1 EIC register The EIC register is used for operations such as edge selection enabling or disabling interrupt requests and checking interrupt requests 225 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE 11 3 Structure of the External Interrupt Circuit This section describes the pins pin block diagram register and interrupt sources of the external interrupt circuit E External interrupt circuit pins The external interrupt circuit has two external interrupt pins The external interrupt pins can function either as external interrupt inputs hysteresis inputs or general I O ports Although the P42 PWC INT1 a
142. controlled by clock and stop mode respectively E Clock generator Crystal or ceramic resonator Connect as shown in Figure 3 6 2 Connection example for a crystal or ceramic resonator Figure 3 6 2 Connection example for a crystal or ceramic resonator MB89950 950A series Main clock oscillator XO X1 I Reference A piezoelectric resonator FAR series that contains the external capacitors can also be used See Data Sheet for details 51 CHAPTER 3 CPU External clock Connect the external clock to the XO pin and leave X1 pin open as shown in Figure 3 6 3 Connection example for external clock Figure 3 6 3 Connection example for external clock MB89950 950A series Main clock oscillator X0 x1 Open T 52 3 6 2 Clock Controller CHAPTER 3 CPU The clock controller contains the following four blocks e Main clock oscillator e Clock controller e Oscillation stabilization delay e Standby control register STB time selector C E Block diagram of clock controller Figure 3 6 4 Block diagram of clock controller shows the block diagram of the clock controller Figure 3 6 4 Block diagram of clock controller Standby control register STBC STP SLP SPL RST gt Pin state gt Sleep mode y Enable X Divid e by 2 gt Stop m
143. dable and writable Unused bit 89 CHAPTER 4 I O PORTS 4 5 2 Operation of Port 3 This section describes the operations of the port 3 E Operation of port 3 90 Operation as an output port Writing data to the PDR3 register stores the data in the output latch When the output latch value is 0 the output transistor turns ON and an L level is output from the pin When the output latch value is 1 the transistor turns OFF and high impedance Hi Z is output from the pin Reading the PDR3 register returns the output latch value Operation as an input port Writing 0 to the PDR3 register set the port as an input port the output transistor is OFF and the pin goes to the high impedance state Reading the PDR3 register returns the pin value When V1 and V2 are selected by PSEL bit of the LCD control register the input data is always as 0 Operation as V1 and V2 When V1 and V2 are selected set the PDR3 register bits corresponding to V1 and V2 pins to 1 to turn the output transistor OFF Operation at reset At reset these ports serve as LCD controller driver bias input Resetting the CPU initializes the PDR3 register values to 1 This turns OFF the output transistor for all pins and all pins are in high impedance Hi Z state Since PSEL bit of LCD control register will be reset to 0 P32 and P33 will be configured to V1 and V2 after reset Operation in stop mode If P32 and P33
144. data transmit pin SO When the UART is ready to accept next data the TDRE is set to 1 and an interrupt request IRQ4 to the CPU is generated if transmit interrupt request is enabled SSD TIE 1 E Receive interrupt When the data is received normally stop bit is detected the RDRF is set to 1 When an overrun error a framing error or a parity error occurs their corresponding error flag bit is set to 1 These bits are set when the stop bit s are detected and an interrupt request IRQ4 to the CPU is generated if receive interrupt is enabled SSD RIE 1 E Registers and vector tables for UART interrupts Table 10 5 1 Registers and vector tables for UART interrupts Interrupt level setting register Vector table address Interrupt Register Setting bits IRQ4 ILR2 007Dy L41 Bit 1 L40 Bit 0 FFF24 FFF34 See Section 3 4 2 Interrupt Processing for details on the interrupt operation 215 CHAPTER 10 UART 10 6 Operation of UART This section describes the operation of the UART The UART has a serial communication function operation mode 0 1 3 E Operation of UART 216 Operation mode The UART has 3 operation modes The mode 0 1 3 are standard serial transmission modes in which a data type from 4 bit data length parity to 9 bit data length non parity is selected See Table 10 1 1 UART operating mode Transfer data format The UART can handle data type of the NRZ Non Re
145. de Low power Consumption ccesceeeeeeeeeeneeeeeeeeeeeeeeseaeeeeeaeeeseaeeeseaeesegeeeseaeesenaeetias 57 3 7 1 Operating States in Standby Mode cceccceccceeeeceeeeeeeeeeeeeeeeceaeeeseaaeeseaaeeseaeeescaeeeseeeeseaeeeteneeeesaees 58 3 7 2 Sleep Mode Eege Eegen Ee ed tev nae erie eee 59 ele BO 60 3 7 4 Standby Control Register STBC ccccccceceeseseeeeeeeeeeeaeeeeceeeseaaeeseeaeeseaeeeesaeeseeeeeseaeeeseaeeeseaeeeseaees 61 3 7 5 Stat Transition Diagrami sisri aiid ake ei eh et Aled aed vaca dee eee ane 63 3 7 6 Notes on Using Standby Mode ccccccccceseeeceneeeeeeeeeeeeeeeeeaeeeeaeeeeeaeeesaaeeseaeeeseaeeeseeeeseeeeeseeeeseaees 65 3 8 Memory Access Mode 00 00 eceeecccceeseenceeeeeseeeeeeeeseeeeeceaaaeneeeeeaaeeaeeeseaaeneeeeeagaeeeesessaaneeeseneaaeeeseeneaneneeeneaes 67 CHAPTER 4 VO PORTS x cccaseeiatatve ccecieesuessewencuacansunastuatavaccwades snasausasevenucissausuncideduetnanuseast 69 4 1 Overview ot VO Poms EE 70 A2 POTO EE 72 4 2 1 Port 0O Data Register PDRO AA 74 4 2 2 Operation of Port 0 cinei n e a e ed ea E a a ea ata aaaea Ne dE 75 GG E E 77 4 33 Port 1 Data Register PDR T is cscersecsccetecesscnccieeens ccadegesnsucte fi ts cctea ce A EE E AR 79 4 32 Operat On Of Ports sack kate Mato Geteste teenies 80 E Gin 82 4 4 1 Port 2 Data Register PDR2 AA 84 4 4 2 Operation Of Port 2 oo cccceccceee cence eeeneeeeeeeeeeeaeeeeeaeeeceeeeseaaeeseaaeeseaaeeseaaeesseeeesaeeeseeeeseaeeeseieeesea
146. defined by the timebase timer In main clock mode if the interval time set for the timebase timer is less than the oscillation stabilization delay time the timebase timer generates an interval timer interrupt request before the end of the oscillation stabilization delay time To prevent this disable the interrupt request output for the timebase timer TBTC TBIE 0 before going to stop mode in main clock mode as necessary CHAPTER 3 CPU 3 8 Memory Access Mode In the MB89950 950A series the only memory access mode is the single chip mode E Single chip mode In single chip mode the device uses internal RAM and ROM only Therefore the CPU can access no areas other than the internal I O area RAM area and ROM area internal access E Mode pin MODA Always set the mode pin MODA to Vss At reset reads the mode data and reset vector from internal ROM Do not change the mode pin settings even after completion of the reset i e during normal operation Table 3 8 1 Mode pin setting lists the mode pin settings Table 3 8 1 Mode pin setting MODA pin state Description Reads the mode data and reset vector from internal ROM Prohibited settings E Mode data Always set the mode data in internal ROM to 00y to select single chip mode Figure 3 8 1 Mode data structure Address Bit7 Bit 6Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFFDH Data Operation 00H Sel
147. dicated segment outputs by mask option selection may be used as N ch open drain I O port pins and the RAM that goes with those pins may be used as regular RAM See Table 12 3 3 Segment outputs display RAM locations and sharing port pins Figure 12 3 7 Segment common output pins and corresponding display RAM shows which display RAM bits are associated with each segment and common output pin Figure 12 3 7 Segment common output pins and corresponding display RAM Address bits bit2 bit bito SEGO 00644 Co bite bits om spe bits bit2 biti bito SEG2 n Uwe Tome bis bid Spo bits bit2 TT bito SEG18 fin FP bit bie bits T mu sEG19 bits bit2 bit bito SEG20 n bit bit bits bid Spoo bits bit2 bit bito SEG22 006FH bz IT bite bits bita SEG23 Pins SEG20 to SEG27 share pins Ge pits bit2 bitt Pm SEG24 with Port O POO to P07 bit bit6 bits bit4 SEG25 bits bit2 bit bito SEG26 0071H Bie bie BIS BI SEG27 bits bit2 bit bito SEG28 00728 Be BIS bi Bia SEG29 bits bit2 bit bito SEG30 0073H reste T bie T bid SEG31 Pins SEG28 to SEG35 share pins 0o74 LD PG bit bio SEGs2 With Port IP10 P17 bit bit bits bit SEG33 bits bit2 bitt bito SEG34 00757 Piz ie bi TE span bits bit2 bitt bito SEG36 0076
148. disable operation select the count clock control interrupts and check the state of the 8 bit PWM timer E PWM control register CNTR Figure 7 3 3 PWM control register CNTR Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0012H P T P1 PO TPE TIR OE TIE 0 000000B R W R W R W R W R W R W R W Ls TIE Interrup t request enable bit O Disables interrupt request output 1 Enables interrupt request output Ls OE Output pin control bit 0 Functions as a general purpose port P41 1 Functions as the interval timer PWM timer output pin PWM Interrupt request flag bit gt tip Read i Write Interval timer function PWMitimer i function O Counter value and set value do not match Clears this bit No change 1 Counter value and set value match No effect The bit does not change TPE Counter operation enable bit D Stops count operation 1 Starts count operation gt PI PO Clock selection bits 0 H Internal 1 tinst GH Oo 1 count 16 tinst 1 1 o clock 64 tinst 1 1 1 PWC timer output 2 Lt P T Operating mode selection bit O Operates as an interval timer 1 Operates as a PWM timer 1 tinst Instruction cycle 2 The PWC timer output referred to here is the PWC timer ou
149. e However when the CS1 and Clock rate selection CSO bit are 11g the 1 8 clock rate is selected in spite of the value of the CR bit bit Bit 4 CS1 CSO Used to select the clock input of the UART If the external or internal clock is Bit 3 Transfer clock selected as clock input the baud rate is a 1 16 or 1 64 clock frequency according to selection bits the value of the CR bit Bit 2 RC2 RC1 RCO Used to select the dedicated baud rate for the serial clock One of eight baud rates Bit 1 Baud rate can be selected from different combination of these bits Bit 0 selection bits 208 CHAPTER 10 UART 10 4 3 Serial Status and Data Register SSD The serial status and data register SSD is used to set and monitor transmit receive operation and error status E Serial status and rate register SSD Figure 10 4 4 Serial status and data register SSD Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0022H RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP 00100 1XB R R R R W R W R W R T SE gt RD8 RP Received data parity selection bit 0 Odd parity 1 Even parity gt TD8 TP Transmitted data parity selection bit 0 Odd parity 1 Even parity RIE Receiver interrupt enable bit 0 Disables interrupt 1 Enables interrupt gt TIE Transmitter interrupt enable bit 0 Disables interrupt 1 Enables interrupt
150. e 1 2 bias 1 2 duty ratio output waveform e 1 3 bias 1 3 duty ratio output waveform e 1 3 bias 1 4 duty ratio output waveform CHAPTER 12 LCD CONTROLLER DRIVER 12 4 1 Output Waveforms during LCD Controller Driver Operation 1 2 Duty Ratio The display drive output is a multiplex drive type two frame a c waveform In the 1 2 duty ratio mode the only common outputs are COMO and COM1 COM2 and COM3 are not used E 1 2 bias 1 2 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment LCD cell is turned on Figure 12 4 2 Output waveforms 1 2 bias and 1 2 duty ratio example shows the output waveforms for the display RAM contents listed in Table 12 4 1 Display RAM contents example Table 12 4 1 Display RAM contents example Display RAM contents Segment COM2 COM1 SEGn SEGn 1 Not used 251 CHAPTER 12 LCD CONTROLLER DRIVER 252 Figure 12 4 2 Output waveforms 1 2 bias and 1 2 duty ratio example COMO 1 1 f f Na V2 V1 Vo Vss COM1 COM2 V3 V2 V1 Vo Vss V3 V2 V1 COM3 SEGn SEGn11 Difference in potential between COMO and SEGn Difference in potential between COM1 and SEGn Difference in potential between COMO and SEGn 1 Difference in potential between COM1 and SEGn 1 Vi to V3 V1 to V3 pin voltages
151. e eee eee d Pin gt I N P32 V1 t PL 1 ch Stop mode S P33 V2 SPL Pin state specification bit in the standby control register STBC 777 LCD controller driver registers Figure 12 3 4 LCD controller driver registers LCDR LCD control register Address Bit7 Bit6 Bit5 Bit4 Bits Bit2 Biti Bit 0 Initial value 0079H RESV PSEL VSEL BK MS1 MSO FP1 FPO 0010000s R W R W R W R W R W R W R W R W SEGR Segment output select register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bit 0 Initial value 007AH SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEGO0O 0000000s R W R W R W R W R W R W R W R W Readable and writable Unused E LCD controller driver RAM LCD controller driver has 42 x 4 bit of internal display RAM in which the data used to generate the segment output signals is stored 243 CHAPTER 12 LCD CONTROLLER DRIVER 12 3 1 LCD Control Register LCDR LCD control register LCDR is used to select the frame cycle control the LCD drive supply voltage select display blanking non blanking and select the display mode E LCD control register LCDR Figure 12 3 5 LCD control register LCDR Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Initial value 00791 RESV PSEL VSEL BK MS1 MSO FP FPO 00100008 R W R W R W R W R W R W R W R W
152. e value set in the COMR register From the match until the counter value overflows FFy gt 004 the PWM pin outputs an L level Figure 7 6 2 Example of PWM waveform output PWM pin shows the PWM waveforms output from the PWM pin Figure 7 6 2 Example of PWM waveform output PWM pin For COMR register value of OOH duty ratio 0 Counter value OOH FFH Du PWM waveform S L For COMR register value of 80H duty ratio 50 Counter value OOH 80H FFH OOH gt PWM waveform For COMR register value of FFH duty ratio 99 6 Counter value OOH gt FFHOOH gt PWM waveform One count clock cycle width ko Note Do not change the count clock cycle CNTR P1 PO during operation of the PWM timer function CNTR TPE 1 Reference When the PWM timer function is selected the PWM pin maintains its existing level when the counter is stopped CNTR TPE 0 134 CHAPTER 7 8 BIT PWM TIMER 7 7 States in Each Mode during 8 bit PWM Timer Operation This section describes the operation of the 8 bit PWM timer when the device goes to sleep or stop mode or an operation halt request occurs during operation E Operation during standby mode or operation halt Figure 7 7 1 Counter operation during standby mode or operation halt for interval timer function and Figure 7 7 2 Operation during standby mode or operation halt for
153. ection example for 8 bit serial I O interface between two MB89950 950A Internal shift clock so ei SOA SI SO SIO B scx Cutput input J Sek ee External shift clock Figure 9 9 2 Operation of bi directional serial I O SIO A START Halt operation SIO A SST 0 Set the SI pin as serial data input input port Set the SCK pin as the shift clock output Set the SO pin as the serial data output Select an internal shift clock Set the data transfer shift direction NO Is serial transfer enabled on SIO B 1 Transfer enable state Set output data Start serial transfer SST 1 Serial data transfer YES FESS SIO B START Halt operation SIO B SST 0 Set the SI pin as serial data input input port Set the SCK pin as the shift clock output Set the SO pin as the serial data output Select an internal shift clock Select the same data transfer shift direction as SIO A Set output data Enable serial transfer SST 1 1 Serial data transfer Read input data YES More data to send in progress lee EEN SST The SST bit is the serial UO transfer start bit in the serial mode register SMR pos in progress Have 8 bits been transferred YES SST 0 Read input data 1 If the SO SI and SCK pins only are connected th
154. ects single chip mode ae Reserved Do not set this value 67 CHAPTER 3 CPU E Memory access mode selection operation Only the single chip mode can be selected Table 3 8 2 Mode pin and mode data lists the mode pin and mode data options Single chip mode Vss 004 Table 3 8 2 Mode pins and mode data Memory access mode Mode pin MODA Other modes Prohibited settings Prohibited settings Figure 3 8 2 Memory access selection operation shows the operation for memory access mode selection Figure 3 8 2 Memory access selection operation C Reset source generated D Prohibited setting Check mode pin Delay for wake up from reset source external reset or oscillation stabilization delay time Mode fetch Check mode data Prohibited setting Set UO pin functions for program execution RUN Mode pin MODA Single chip mode Read mode data from internal ROM I O pins are high impedance e Reset active Fetch mode data and reset vector from internal ROM Mode data Single chip mode 00x Set UO pins to input or output depending on their respective port data direction registers DDR etc I O pins are available as ports 68 CHAPTER 4 I O PORTS This chapter describes the functions and operation of the I O ports 4 1 Overview of I O
155. eeeeees 100 142 interval timer function one shot timer mode program example 2 for 167 interval timer function reload timer mode program example 1 Tor er eE 165 interval timer function square wave output function EN AE ATA TEA ETET 122 interval timer function timebase timer operation of SE 107 interval timer function interrupt for 106 131 155 interval timer function operation of 132 156 interval timer function program example for 138 L LCD control register CDD 244 LCD controller driver function cceeeeeee 234 LCD controller driver Din 241 LCD controller driver pin block diagram of 242 LCD controller driver DAN 243 LCD controller driver register csceeeeeee 243 LCD controller driver block diagram of 235 LCD controller driver operation of 250 LCD controller driver program example for 260 LCD driving waveiomm 250 M main clock oscillation stabilization delay time 55 main clock oscillation stabilization delay time and ESET SOUCO eege eeh geed 44 MASK OPON eege a aie elegy indeees ane 287 MB89950 950A series block diagram s 7 MB89950 950A series pin State cceeeeee 295 measuring long pulse widts AN 160 memory access mode selection operation 68 Memory Tan 23 memory Space 294 memory space Structure eee cere eee e eee 22 MOG datas E 67 mode e EE 47 mode EE 47 mode pin MODA 67 MQP 6
156. eeeeeneeeeeeeeeeeeeeeeaeeseaaeeesaeeeseaeeeecaeeeseeeeseeeeseneeetas 130 TA S btPWM Timer Interrupts sariei a ie aR eaa aa Ria EKE RNET RENAN ira biii ai EG 131 7 5 Operation of Interval Timer Function cceceeceeeceneeeeeneeeeeaeeeeeaeeeeeeeeeeaeeeecaeeeseaeeseeaeeeseaeeesseeeseeaees 132 7 6 Operation of PWM Timer Function ssssesseseseessiersitsrirssritsrintttittintstnntttntttetnttesttenatnnnstensnnnsnn nennt 134 7 7 States in Each Mode during 8 bit PWM Timer Operation ssseeseeseessiesrserirserissrrrserresrrrsrrrrsrrnserns 135 7 8 Notes on Using 8 bit PWM Timer arareo rert e a AAE EE A A eS EE SA 137 viii 7 9 Program Example for 8 bit PWM Timer eececeeeeenneeeeeeeneeeeeeeecaeeeeeeeaeeeeeseaaeeeeeeenaeeeeesseaaeeeeeeeaas 138 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC cccssssssseseseeeceeceeeeeeeeeeeeeeneeenes 141 8 1 Overview of Pulse Width Count Timer 0 cccceccceeeeeeeeeeeeeeeeeeee eee aeeeeaeeeseaaeeseeeessaeeeseaeeeseaeeeseeeeeeas 142 8 2 Block Diagram of Pulse Width Count Timer ccccceeceeeeeeneeeeeeeeeeeaeeeeeaaeeeeeeeseeaeeeseaeeseeaeeeeseeetaas 144 8 3 Structure of Pulse Width Count Timer ccccccececeeceneeeeeeeeeeeaeeeeaeeesaeeeseaaeeseaeeeseaeeeseaeeeseeeeeeneeesas 146 8 3 1 PWC Pulse Width Control Register 1 PCR1 ccccecceceeceeeeeeneeeeeeeeeseeeeeeeeeeeeeeeeseeeeeeieeeeseaeeeeaaes 148 8 3 2 PWC Pulse Width Control Register 2 PCR2 cccceesceeceeeeeeeeeeeeeeeeeeeeeeeaeeesesa
157. eeeneeeeeeeeeeeaeeeeeaaeeseaeeeseaeeeseaeeeseaeeeeseaeeesiaeeeseaeeeesaees 29 3 2 2 Register Bank Pointer RP ek 32 23 General purpose Registers cceceececeeeeeeeneeeeeeeeeeeeee cease eeeaeeeceaeeeceaeeeseaeesecaeeeeeaeeseaeeeseeeesecaeeseneeesaas 33 K Wl lui CEET 35 3 4 1 Interrupt Level Setting Registers ILR1 ILR2 ILR3 0 ee cceeeeceeeeeeeeeeeeeeeseaeeeseeeeseeeeeeneeeesaaes 36 9 4 2 Interrupt Processi WE 37 343 MultiplecInterrupts ee dree a a e a oa a a e E EA aa teteetauiee tees 39 3 4 4 Interrupt PDroceseimg TIME reiii eeni eeenee eee ie aiar Eeg aR ea kaia ENEE RNANA EEA RELA ENER EANA RAAKANA RAEE 40 3 4 5 Stack Operation during Interrupt Processing c cccceceeeeeeeteeeeeeneeeseaeeseaaeeecaeeeseeeeeseiaeeessaeeesaaes 41 3 4 6 Stack Area for Interrupt Processing ccccccceseeeeeneeeeeeeeeeeeeeeaeeeesaeeeseaaeeseaaeeseaeeeseeeeseeeeeseeeeeeaees 42 cb RESE a ege ERA AE EE E EE EE E AA 43 3 521 External RESOt PA norana are ei a a a aae eA a A e EA TERRA 45 3 5 2 Reset Operato N ra peara aaeeea a a e a a aa EAA E a a Ea ea a e aa aaa aeia 46 3 5 3 Pin States during Reset A 48 CR ER ee 49 3 6 1 Clock Generator csse enning deed needs deine steed SEENEN pae Ea Aee E Ee aE a taake aie AE EES 51 3 6 2 Cock Controler a ri ee aeaa ae EE EE a a a eaa eadeni 53 3 6 3 Oscillation Stabilization Delay Time ecccecececeeceneeeeeeeeeeeaeeeeeeeseeaeeseaaeeseaaeeseaaeeseeeessaeeeseeeeseaes 55 3 7 Standby Mo
158. eeeseaaeeseaeeeseaeeeseeeeseaeeesseeeeaas 173 9 3 1 Serial Mode Register MP 176 9 3 2 Serial Data Register GD 179 9 4 TER Blat 180 9 5 Operation of Serial Output oo cece sce ceseeeeeneeeeesceeeseeeeaaeeesaaneneaaeeseaaeeneaeaeseeaessneneessaaeseneeeeseaaeneaes 181 9 6 Operation of Serial Input ccceccceececeeeeeeeeeeeeeeeeeeeeeeeeseaaeeseeaeeceaaeeseaaeeegaeeessaeesssaeeeseaeeeeeaeeeeeaeeetaas 183 9 7 States in Each Mode during 8 bit Serial I O Operation 0 cccccceeceeeeeeeeeeeeeeeseeeeeeeeeeeeeeeseeeeeeaeeeseas 185 9 8 Notes on Using 8 bit Serial O oo cccccee cece ee ceneeeeeeeeeecaeeeeeaeeeeeaeeeeeaeeeseaaeeceaeessaeeeseaeeeseaeeeeeneeetaas 188 9 9 Connection Example for 8 bit Serial UO ceeeccecceceeceeeeeeeeeeeeeeeeeeaeeeeaaeeeseaaeeseeeeseeeeeseaeeeseaeeeeeneeesaas 189 9 10 Program Example for 8 bit Serial O eeecceccceeeeeeeeeteeeeeneeeeeeeeeteeeeeeeaeeseaaeeeeaeeseaeeeseeeeeieeeeseeeeees 190 CHAPTER 10 VART RE 193 10 1 Overview of UART eer eege ENEE NEE e ied venta ical se A Eria aee lees 194 10 2 Structure or WARD ere ea a a e ee eet eae ane aerate Ye ett hae 199 ECHT A RTE 202 TOA UART REGISTOS eaea dd d geed deed gd deed EENS 204 10 4 1 Serial Mode Control Register 1 SMC1 ceecccceeeeeeeeeeeeeeeneeeeeeeeeeaeeeecaeeseaeeseaeesesaeeeeneeeeseneeens 205 10 4 2 Serial Rate Control Register SRC ccccecccceeeeeeeeeeneeeeeeeeeeeeeeeeseaeeeecaeeseaeeseaeesecaeeseeeeeeseaeess 207 10 4 3
159. eeeseneeeseeeeeseaeeeeaaes 150 8 3 3 PWC Reload Buffer Register DL DP 152 8 3 4 PWC Noise Filter Control Register NCCR c ccecccceeeseceeeeeeeeeneeeeeeeeeecaeeeseaeeesaaeeeseaeeseenaeeeeaas 154 8 4 Pulse Width Count Timer Interrupts ccccceceeceneeeeeeeeeeeeeeeecaeeeeeaeeeeeaeeeseaaeeseaaeeseaeeeseaeeesneeeeseeetaas 155 8 5 Operation of Interval Timer Function cceceeeeeeeeeeeeeeeeeeeeeeeeeetecaeeeeeaeeseeaeeeeaeeseaeeeseaeeeseaeeeeeeeeees 156 8 6 Operation of Pulse Width Measurement Function 0 ccccceeeeceeeeeeeeeneeeeeaeeeseaeeeseaeeeseaeeeseaeeeseaeeetaas 159 8 7 Operation of Noise Filter Circuit cccccccceceeneeeceeeeceeeeeeeeeeeeeeaeeceaaeeeesaeeecaeeeeseeeenaeeeseaeeeseeeeeeneeeeas 162 8 8 States in Each Mode during Pulse Width Count Timer Operation ccccceseceeeeeeeeeteeeseneeeteneeeeans 163 8 9 Notes on Using Pulse Width Count Timer 0 c ceccceccceeeceeeeeeeee seers eeeaeeeeeeeeeeeaeessaeeeeeeeeeseeeeeneaeeseaas 164 8 10 Program Example for Timer Function of Pulse Width Count Timer ccceceseeeeeeeeeeeeeteeeteneeetees 165 CHAPTER 9 8 BIT SERIAL HE retee es ueseeeee eb ee desse Ehe SEELEN 169 9 1 Overview of 8 bit Serial l O EE 170 9 2 Block Diagram of 8 bit Serial O oo eee ecececcene eect eeeneeeeeceeeeeeaeeeeeaeeeeaaeeseaaeeeeeeeeesaeeeseaeeeseaeeeeeneeetaas 171 9 3 Structure of 8 bit Serial I O ceeeccceeceeceeeeeeee ee eeeeeeecaeeeeeaeeseaaeeeeeaeescea
160. ees 85 AS Gu EE 86 4 5 1 Port 3 Data Register BDO wissscsssssscczeeesertczeensscueaetensevecdesvessacan pes cnvacetenreveneneeseuacaeestecscdanpeangaceeeaes 89 4 52 Operation OP Ort EE 90 AG PONA EE 92 4 6 1 Port 4 Registers PDR4 DDR4 A 94 4 6 2 Operation of POMA ee NEEN Eege EEN ENEE ee petit rea EEE Taaa nae aaa Eai Ees 96 4 7 Program Example for UO Ports ccccceecceeeeeeeeeneeeeeeeeeeeeeeeeeeeeceaeeeeeeeeeseaeeesceaeescaeeseaaeeseaaeeseaeaeeseneeenaas 98 CHAPTER S TIMEBASE TIME sitcasisizicnatcetscteeetasceinatzesdaustsatsaetontseeetddelecsunhuaventuzhearsansen 99 5 1 Overview of Timebase Timer ececcececeeceneeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeseaeeeeeaeeeseaeeeesaaeeseeaeeseeaeeseieeeseaeeess 100 5 2 Block Diagram of Timebase Timer o oo eee ee eeeeeeeeeeeeneeeeeeeeaeeeeeeeaaaeeeeeteaeeeeeeeaaaeeeeeseaeeeeeneeaeeeeeeeaas 102 5 3 Timebase Timer Control Register TBTC c cceccceeeseeeeeeceeeeeeee ceases tease encase eeeaeeeneaeeseeeeeeeaeeseaeees 104 54 Timebase Timer IMterrupt gute eves fesaacccedentsaceepeseres O E A anaes AAEE 106 5 5 Operation of Timebase Timer aaea ar a a a ae ara e R a aea aaa a A oaa aaea a aa a ieaiai 107 5 6 Notes on Using Timebase TIMET cerien nene reee A EA OS Vea E aA EEL ATLE 109 5 7 Program Example for Timebase Timer ceccecceeeeeeneeeeeeeeneeeeeeeneaeeeeeeeeaeeeeeeeeaeeeeeeesaeeeeesenaaeeeeeenaas 110 CHAPTER 6 WATCHDOG TIMER ssssssssssnnnneenseennnnnnnnnnnnnnnnnnnn
161. eference Cancelling stop mode using an interrupt is only possible using the external interrupt circuit e An interrupt request is generated immediately if the external interrupt request flag bit is 1 when the interrupt request enable bit is changed from disabled to enabled 0 gt 1 E Register and vector table for the external interrupt circuit interrupts Table 11 4 1 Register and vector table for the external interrupt circuit interrupts Interrupt level setting register Vector table address Interrupt Register Setting Bits Upper Lower IRQO LOI Bit 1 L00 Bit 0 FFFAy FFFBy ILR1 007Cy L11 Bit 3 L10 Bit 2 FFF84 FFF9 See Section 3 4 2 Interrupt Processing for details on the operation of interrupts E Notes when changing edge polarity selection When changing the edge polarity for INTO to INT1 always write 0 into the corresponding EIR bits This will prevent from accidentally creating an interrupt 230 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE 11 5 Operation of the External Interrupt Circuit The external interrupt circuit can detect a specified edge on a signal input to an external interrupt pin E Operation of the external interrupt circuit Figure 11 5 1 External interrupt circuit settings shows the settings required to operate the external interrupt circuit Figure 11 5 1 External interrupt circuit settings Bit7 Bit6 BitS Bit4 Bits Bit2 Bit1 Dro EIC1 EI
162. el Interrupt request level LO1 to LB1 LOO to LBO Priority High Low no interrupt Reference The interrupt level bits in the condition code register CCR IL1 ILO are normally 11g during main program execution Note As the IRL1 ILR2 and ILR3 registers are write only the bit manipulation instructions cannot be used 36 CHAPTER 3 CPU 3 4 2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function If the CPU is able to receive the interrupt the CPU temporarily halts the currently executing program and executes the interrupt processing routine E Interrupt processing The procedure for interrupt operation is performed in the following order interrupt source generated at peripheral function set the interrupt request flag bit request FF discriminate the interrupt request enable bit enable FF the interrupt level ILR1 ILR2 ILR3 and CCR IL1 ILO simultaneously generated interrupt requests with the same level then check the interrupt enable flag CCR I Figure 3 4 2 Interrupt processing shows the interrupt processing Figure 3 4 2 Interrupt processing
163. elects both edge mode Always write 0 into EIRO when changing these bits EIEO INTO interrupt request enable bit Enables or disables output of interrupt requests to the CPU An interrupt request is generated when both this bit and INTO external interrupt request flag bit EIRO are 1 1 229 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE 11 4 External Interrupt Circuit Interrupts The external interrupt circuit can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin E Interrupts when the external interrupt circuit is operating On detecting a specified edge on an external interrupt input the external interrupt circuit sets the corresponding external interrupt request flag bit EIC EIRO EIR1 to 1 An interrupt request to the CPU IRQO IRQ1 is generated at this time if the corresponding interrupt request enable bit is enabled EIC EIEO EIE1 1 Always write 0 to the corresponding external interrupt request flag bit in the interrupt processing routine to clear the interrupt request Note When enabling interrupts EIEO EIE1 1 after exit of a reset always clear the corresponding external interrupt request flag bit EIRO EIR1 0 at the same time Interrupt processing cannot return if the external interrupt request flag bit is 1 and the interrupt request enable bit is enabled Always clear the external interrupt request flag bit R
164. ent driver outputs segment driver output must be selected by the mask option Furthermore the segment driver output select register must be set to the same as the mask option so that the CMOS input port can be protected Table 4 2 3 Port 0 data register function a lists the functions of the port 0 data register Table 4 2 3 Port 0 data register function Register Address Initial value Outputs an L level to the pin Sets 0 to the output latch and turn the output transistor ON Pin state is the L level Port 0 data register PDRO Sets the pin to the high Pin state is the impedance state H level Sets 1 to the output latch and turn the output transistor OFF 11111111 R W Readable and writable 74 CHAPTER 4 I O PORTS 4 2 2 Operation of Port 0 This section describes the operations of the port 0 E Operation of port 0 Operation as an output port e When the output latch value is 0 the output transistor turns ON and an L level is output from the pin When the output latch value is 1 the transistor turns OFF and high impedance Hi Z is output to the pin e Writing data to the PDRO register stores the data in the output latch and it will be output to the pin e Reading the PDRO register returns the output latch value Operation as an input port e Writing 0 to the PDRO register set the port as an input port the output transistor is OFF a
165. ential between COMO and SEGn 1 Difference in potential between COM1 and SEGn 1 Difference in potential between COM2 and SEGn 1 i i 1 frame V1 to V3 V1 to V3 pin voltages i 1 cycle 255 CHAPTER 12 LCD CONTROLLER DRIVER 256 LCD panel connections and display data example 1 3 duty ratio drive mode Figure 12 4 5 Segment common connections data states and corresponding display Example Using segments to represent 5 com JP Ba oo nd COM1 4 SEGn x7 a S 8 pa O COM2 SEGn 2 SEGn 1 Address COM3 COM2 COM1 COMO O64H o f o fJ 1 SEGO Address COM3 COM2 COM1 COMO 1 1 1 _ SEG1 nH mg Je oit oito SEGn KEE eee chee E e bit Jones bit5 bits SEGn 1 Aen i SC nn Ip Ines In Teg SEGn 2 RE 0 to 8 Indicate corresponding display RAM bits Bits 3 and 7 and 2 are 0 OFF not used 1 ON Bit States for Numerals 0 through 9 LCD Display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito R 5 W 1 0 1 1 x x T SS Z m 9 fF De E o E Ss Bei Bei ES lt CH CH CH CH CH H Ee ed TI 2 LECH EREECHEN OO i e i i i e i i i xt a r OI en el Oe lte LO SC SS ke i i i i gt i i 1 i D DE amp i i i S ei wiel eleli e leie le aA f i i i _
166. equired for display data can be used as regular RAM If any customer wants to choose the mask option combination which is not shown in Table 12 3 3 Segment outputs display RAM locations and sharing port pins please inform Fujitsu for special testing arrangement Table 12 3 4 Common outputs and display RAM bits used in each duty ratio mode shows the relationship between duty ratio mode common outputs and display RAM Table 12 3 4 Common outputs and display RAM bits used in each duty ratio mode Duty ratio Display data bit used f Common outputs used setting bit5 bit4 bit3 bit2 COMO to COM1 2 pins COMO to COM2 3 pins COMO to COM3 4 pins O Used Not used 249 CHAPTER 12 LCD CONTROLLER DRIVER 12 4 Operation of LCD Controller Driver The LCD controller driver provides the necessary control and drive for an LCD E Operation of LCD controller driver Figure 12 4 1 LCD controller driver settings shows the settings required to operate the LCD Figure 12 4 1 LCD controller driver settings Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDR RESV PSEL VSEL BK MS1 MSO FP1 FPO 0 0 Other than 00s Display RAM Display data Used bit 064H to 078H 1 Set 1 0 Get 0 Once the above settings have been made if the selected clock for frame cycle generation is running LCD panel drivi
167. er When the data length is set to 7 bits bit 7 does not have meaning CHAPTER 10 UART Serial output data register SODR This register stores data to be transmitted The data written in this register is converted to serial data and sent to serial output pin When the data length is set to be 7 bits bit 7 does not have meaning 201 CHAPTER 10 UART 10 3 UART Pins This section describes the pins and pin block diagram of UART E UART pins The pins for the UART function are shift clock input output pin P45 SCK serial data output pin P44 SO and serial data input pin P43 S1 P45 SCK 202 This pin function either as a general purpose input output port P45 or a clock input output pin hysteresis input for the UART SCK When clock output is enabled SMC1 SCKE 1 this pin functions as clock output pin SCK irrespective of settings on corresponding port direction register In this case do not select an external clock SRC CS1 CSO are not 00g To use the port as a UART clock input pin disable the clock output SMC1 SCKE 0 and configure the port as an input port by setting a corresponding port direction register bit DDR4 bit 5 0 In this case be sure to select an external clock SRC CS1 CSO 00g P44 SO This pin functions either as general purpose input output port P44 or serial data output pin of the UART SO When serial data output is enabled SMC1 SOE 1 thi
168. erate Writing 1 to the sleep bit in the standby control register STBC SLP puts the CPU to sleep mode If an interrupt request is generated when 1 is written to the SLP bit the write to the bit is ignored and the CPU continues the instruction execution without entering sleep mode The CPU does not go to sleep mode even after completion of the interrupt processing Wake up from sleep mode A reset or an interrupt from a peripheral function wakes up the CPU from sleep mode There is no oscillation stabilization delay period The reset operation also initializes the pin states If an interrupt request with an interrupt level higher than 11 occurs from a peripheral function or an external interrupt circuit during sleep mode the CPU wakes up from sleep mode regardless of the interrupt enable flag CCR I and interrupt level bits CCR IL1 and ILO in the CPU The normal interrupt operation is performed after wake up from sleep mode If the interrupt request is accepted the CPU executes interrupt processing If the interrupt request is not accepted the CPU continues execution from the subsequent instruction following the instruction executed immediately before entering sleep mode 59 CHAPTER 3 CPU 3 7 3 Stop Mode This section describes the operations of stop mode E Operation of stop mode 60 Entering stop mode Stop mode stops the oscillation source Almost all functions stop while maintaining all reg
169. eration enable interrupt request output clear underflow 01H gt 00H interrupt request flag clear measurement completion interrupt request flag bit 1 SETI Enable interrupts Interrupt processing routine WARI CLRB UF Clear interrupt request flag PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END 166 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC E Program example 2 for interval timer function one shot timer mode Processing description e Generates a single 1 5 ms interval timer interrupt one shot timer mode es The TO bit is initialized to 1 and inverted after the interval time e The following shows the RLBR register value that results in an interval time of approximately 3 ms for a 5 MHz main clock oscillation frequency The count clock is 32 ting tinsti Instruction cycle RLBR register value 3 ms 32 x 4 5 MHz 117 2 075 167 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Coding example PCR1 EQU 0014H Address of the PWC pulse width control register 1 PCR2 EQU 0015H Address of the PWC pulse width control register 2 RLBR EQU 0016H Address of the PWC reload buffer register EN EQU PCR1 7 Define the counter operation enable bit IE EQU PCR1 5 Define the interrupt request enable bit UF EQU PCR1 2 Define the underflow 01H gt
170. ere is no direct method of confirming whether SIO B has enabled serial transfer Therefore SIO A must use a software timer or similar to delay time for a sufficient time for SIO B to enable serial transfer 2 Data is not transferred correctly if SIO A starts data transfer when SIO B has not enabled serial transfer 3 An interrupt request is generated after 8 bit data have been transferred NO END 189 CHAPTER 9 8 BIT SERIAL I O 9 10 Program Example for 8 bit Serial I O This section gives program example for 8 bit serial I O E Program example for serial output Processing description e Outputs 8 bit serial data 554 from the SO pin of serial I O then generates an interrupt when transfer is completed e The interrupt processing routine resets the transfer data and continues output e Operates as an internal shift clock and outputs the shift clock from the SCK pin e With a main clock oscillation frequency Foy of 5 MHz the highest speed clock selected by the speed shift function 1 instruction cycle 4 Foy and a 32 ti shift clock the data transfer rate will be as follows Transfer speed 5 MHz 4 32 39 kbps Interrupt cycle 8 x 32 x 4 5 MHz 204 8 us 190 Coding exampl SMR SDR SIOF SST ILR2 e DSEG ORG DW ENDS CSEG CLRI CLRB MOV MOV MOV TB TT Di Di n LRB G P XCHW P M S ETB 001CH 001DH SMR 7 SMR 0 007DH ABS
171. erial transfer operating Starts enables serial transfer ri BDS Transfer direction selection bit D LSB first starts transfer from the least significant bit 1 MSB first starts transfer from the most significant bit gt CKS1 CKSO Shift cl ock sel ection bits SCK pin 0 0 2 tinst Output 0 1 internal shift 8 tinst Output 1 0 32 tinst Output 1 1 External shift clock Input tinst Instruction cycle __ DOE Serial data output enable bit D Functions P44 SO as the general purpose I O port 1 Functions P44 SO as the serial data output pin SCKE Shift clock output enable bit 0 Functions P45 SCK as a general purpose I O port or shift clock input pin 1 Functions P45 SCK as the shift clock output pin SIOE Interrupt request enable bit 0 Disables interrupt request output 1 Enables interrupt request output Interrupt request flag bit SIOF A Read Write 0 Mranster has not Clears this bit completed R W Readable and writable 1 Transfer has completed No effect The bit does not Initial value change 176 SIOF Interrupt request flag bit CHAPTER 9 8 BIT SERIAL UO Table 9 3 1 Serial mode register SMR bits Function This bit is set to 1 when the serial output operation has transmitted 8 serial data bits or the serial input operation has received 8 serial data bits An interrupt request is generated when both this bit and the interrupt request enable bit SIOE are vin e Writing 0 clears this bit Writing 1
172. ernal ROM CHAPTER 1 OVERVIEW Table 1 2 2 Common specifications for the MB89950 950A series Parameter Specification CPU functions Number of instructions 136 Instruction bit length 8 bits Instruction length 1 to 3 bytes Data bit length 1 8 16 bits Minimum execution time 0 80 us to 12 8 us at 5 MHz Interrupt processing time 7 26 us to 115 2 us at 5 MHz Peripheral functions Note General purpose I O ports N ch open drain 22 also serve as LCD segment pins l General purpose I O ports N ch open drain 4 two also serve as LCD bias pins General purpose I O ports CMOS 7 6 ports serve as peripherals Total 33 max 20 bit timebase timer 20 bits Interrupt cycle 6 55 ms 26 21 ms 104 86 ms 419 43 ms at 5 MHz Watchdog timer Reset generate cycle min 419 4 ms at 5 MHz 8 bit PWM timer 8 bit reload timer operation square wave output operating frequency 0 8 us 12 8 us 51 2 us at 5 MHz 8 bit resolution PWM operation conversion frequency 204 8 us 3 36 s Event count function PWC timer 8 bit interval timer operation 8 bit pulse width measurement continuous measurement High width Low width measurement and One cycle measurement Operation clock 0 8 us 3 2 us 25 6 us at 5 MHz UART Transfer data length 5 7 8 bits Internal baud rate generator Max 78125 bps at 5 MHz 8 bit serial I O 8 bits LSB first MSB first selectability One clock selectab
173. errupt 0 cee eee eeeeeeeeeeeteeeeeteneeeeeeeeeaees 215 receive operaion eee ceeeeeeeeeeeeeeeeeeeeeeeeeeeneeees 218 recommended screening condition e 291 register bank pointer RP structure of 32 reset operation overview Of 46 FESCUE SOUICE aiae a a a e a eia na 43 44 S segment output select register SEGR 246 serial data register DP 179 serial UO function c cece eeeeteeeeeeeeteeeetetaeeteaeees 170 300 serial input data register GIDP 211 Serial input operation 183 serial input operation at completion of 184 serial input program example for nsee 192 serial mode control register 1 SMC1 0 205 serial mode control register 2 SMC2 45 213 serial mode register MP 176 serial output data register OD 212 serial output Operation eseese 181 serial output operation interrupt Tor 180 serial output operation at completion of 182 serial output program example for 190 serial rate control register PC 207 serial status and rate register GG 209 single chip mode 67 sleep mode operation of 59 special iNStrUction orderida aani 274 stack operation at interrupt return seeen 41 stack operation at start of interrupt processing 41 standby control register GSTBC 61 standby mode AA 57 standby mode and interrupts go Io 65 standby mode by interrupt wake up from 65 standby mode note on Setting 65 standby mode
174. errupt level setting register Vector table address Interrupt Register Setting bits IRQ3 ILR1 007Cy 131 Bit 7 L30 Bit 6 FFF4 FFF5y See Section 3 4 2 Interrupt Processing for details on the operation of interrupt 155 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 5 Operation of Interval Timer Function This section describes the operation of the interval timer function of the pulse width count timer E Operation of interval timer function The interval timer function can operate as a continuous timer reload timer mode or as a timer that operates for one timer cycle and then stops one shot mode Reload timer mode Figure 8 5 1 Interval timer function reload timer mode settings shows the settings required to operate in reload timer mode Figure 8 5 1 Interval timer function reload timer mode settings Bit7 Bit6 BitS Bit4 Bit3 Bit2 Biti Bit O PCR1 EN IE UF IR BF 1 X X PCR2 FC RM TO C1 co WI WO Used bit X Unused bit 0 0 X X 1 Set 1 RLBR Sets interval time counter initial value EES On activation the RLBR register value is loaded to the counter and the counter starts to count down on the rising edge of the selected count clock When the counter value underflows Oly gt 00p the PWC inverts the timer output bit PCR2 TO value reloads the RLBR register value to the counter and sets the under
175. f the EPROM programmer See Bit map on the next page for the correspondence to each option 3 Program with the EPROM programmer 291 APPENDIX E Bit map for PROM option Table D 1 2 Bit map for PROM option shows the bit map for PROM option Table D 1 2 Bit map for PROM option Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Oscillation stabilization time 1 28 Foy 0 2 4 Foy Reset pin Output 1 Available 0 Unavailable Power on Reset 1 Available 0 Unavailable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable P46 Pull up 1 Unavailable 0 Available P45 Pull up 1 Unavailable 0 Available P44 Pull up 1 Unavailable 0 Available P43 Pull up 1 Unavailable 0 Available P42 Pull up 1 Unavailable 0 Available P41 Pull up 1 Unavailable 0 Available P40 Pull up 1 Unavailable 0 Available Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable
176. flow Oly gt On interrupt request flag bit PCR1 UF 1 on the next rising edge of the count clock Figure 8 5 2 Operation in reload timer mode shows the operation in reload timer mode 156 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Figure 8 5 2 Operation in reload timer mode Counter value FFH jesus 2 SS SSeS She eb ce iene Se ahs ES Reload 80H 4 N sea BEE Ree OOH L l gt i i Time Timercycle RLBR value is modified RLBR value 1 i FFH gt 80H 1 1 FFH Cleared by the program 1 1 ji 1 DS Ly ENbit TOE bit For an initial value of 0 TO bit If the PWC reload buffer register RLBR value is modified during operation the new value will be effective in next cycle Reference Setting the RLBR register value to 01 causes the TO bit to be inverted after each count clock cycle One shot timer mode Figure 8 5 3 Interval timer function one shot timer mode settings shows the settings required to operate in one shot timer mode Figure 8 5 3 Interval timer function one shot timer mode settings Bit7 Bit6 BitS Bit4 Bits Bit2 Biti Bit 0 PCR1 EN IE UF IR BF 1 X X PCR2 FC RM TO C1 co WI WO Used bit 0 1 e x X X Unused bit 1 Set 1 RLBR Sets interval time counter initial value 0
177. ft clock counter as shown in Figure 9 7 6 Operation during halt external shift clock Therefore the device being communicated with must also be initialized In serial output operation set the SDR register again before re activating If an external clock is input at this time the SO pin output changes Figure 9 7 6 Operation during halt external shift clock Clock for next data SCKinpt LIL ra r aa r m 1 i i T Tt R SST bit Operation halts T i Operation reactivates SIOF bit Ee SO pin output EE 1 X n XFX 187 CHAPTER 9 8 BIT SERIAL I O 9 8 Notes on Using 8 bit Serial UO This section lists points to note using when the 8 bit serial I O E Notes on using 8 bit serial UO 188 Error on starting serial transfer Activating the serial transfer by software SMR SST 1 is not synchronized with the falling edge output or rising edge input of the shift clock there is a delay of up to one cycle of the selected shift clock before the first serial data I O occurs Malfunction due to noise In serial data transfer malfunction of the serial I O may occur if unwanted pulses pulses exceeding the hysteresis width occur on the shift clock due to external noise Notes on setting by program Write to the serial mode register SMR and serial input register SDR when serial I O is stopped SMR SST 0 Do not modify other SMR register bits when starting enabling serial I
178. gisters 3 3 General purpose Registers 3 4 Interrupts 3 5 Resets 3 6 Clocks 3 7 Standby Modes Low power Consumption 3 8 Memory Access Mode 21 CHAPTER 3 CPU 3 1 Memory Space The microcontrollers of the MB89950 950A series offer a memory space of 64 Kbytes The memory space contains the I O area RAM area ROM area and external area The memory space contains areas used for special purposes such as the general purpose registers and vector table E Memory space structure 1 0 area addresses 0000 to 007F e Control registers and data registers for the internal peripheral functions are located in this area e As the I O area is allocated within the memory space I O can be accessed in the same way as memory High speed access using direct addressing is available RAM area e Internal static RAM is provided as an internal data area e The internal RAM size differs from product to product e Addresses between 0080y and OPP support high speed access using direct addressing e Addresses between 01004 and O1FFy can be used as the general purpose register area restrictions apply for some products es The contents of RAM is indeterminate after a reset ROM area e Internal ROM is provided as an internal program area e The internal ROM size differs from product to product e Addresses between FFCO and FFFFy are used for the vector table etc 22 E Memory map Figure 3 1 1 Memory map
179. gisters SMC1 SMC2 SRC SSD SIDR SODR E Block diagram of UART Figure 10 2 1 Block diagram of UART Internal data bus ee Eegen 7 Registers aay Baud rate generator and serial clock generator s SMC1 PEN SBL Wi MCO SMDE SCKE SOE l SEL Sek SMC2 PSEN RSEL PDS1 PDSO l l t l SSD RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP n MARS Sse d Gasen Sk eR est cso Rca DEI RCo SODR l Serial UO clock SIDR l Ppsi RC2 CS EE 7 i Pppso RCI Cen CR SMDE i i RCO l i l 1 4 O l CPU clock D n O l 1 13 Ve L O l l S 1 8 E Serial 1 639 om 1 2 o clock l PWMtimer gt O Si 1 4 O O l output l l a gt O l i P45 SCK 1 2 lo p i 5 Data transmit control circuit PEN TD8 TP eee l l l MCO l l Parity RSEL MC1 SBL TDRE generator S l l SOE l Timing Shift clock Shifter Q Transmitter _ Transmitter z N P44 SO i byte count control Transfer clock Serial I O data o y Le ransfer cloc l j Reset l SODR
180. gnificant bit MSB is set to 1 as a result of an arithmetic operation Clear to 0 when the bit is set to 0 Zero flag Z Set to 1 when an arithmetic operation results in 0 Clear to 0 otherwise Overflow flag V Set to 1 if a signed numeric value overflows because of an arithmetic calculation Clear to 0 if the overflow does not occur 29 CHAPTER 3 CPU Carry flag C Set to 1 when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation Clear to 0 otherwise Set to the shift out value in case of a shift instruction Figure 3 2 3 Change of carry flag by shift instruction shows the change of the carry flag by a shift instruction Figure 3 2 3 Change of carry flag by shift instruction Left shift ROLC Right shift RORC Bit 7 lt Bit 0 Bit 7 Bit 0 Cl gt C t Note The condition code register is part of the program status PS and cannot be accessed independently Reference In practice the flag bits are rarely fetched and used directly Instead the bits are used indirectly by instructions such as branch instructions such as BNZ or the decimal adjustment instructions DAA DAS The content of the flags after a reset is indeterminate E Interrupt acceptance control bit Interrupt enable flag I Interrupt is enabled when this flag is set to 1 and the CP
181. h data rather than the pin level the instructions do not change the output latch values for bits other than the bit being set or cleared Port 4 data direction register DDR4 The DDR4 register sets the direction input or output for each pin bit Setting 1 to the bit corresponding to a port pin sets the pin as an output port Setting 0 sets the pin as an input port Settings as a peripheral output To use a peripheral that has an output pin set the peripheral output enable bit for that pin to the enable state As can be seen in the block diagram the peripheral has precedence over the general purpose port for use of the output pin Once the peripheral output is enabled the states set in the PDR4 and DDR4 registers are no longer valid and do not affect the data output by the peripheral or the enabling of the output Settings as a peripheral input To use a peripheral that has a port 4 pin as an input pin set that pin as an input port The output latch data for that pin will no longer be valid Table 4 6 3 Port 4 PDR and DDR register function lists the functions of the port 4 PDR and DDR registers CHAPTER 4 I O PORTS Table 4 6 3 Port 4 PDR and DDR register function Register Address Initial value Outputs an L level to the pin if the pin functions as an output port Sets 0 to the output latch and turns the output transistor ON Pin state is the L level Port 4 data register PDR4 Sets
182. has no effect and does not change the bit value SIOE Interrupt request enable bit This bit enables or disables an interrupt request output to the CPU An interrupt request is issued when both this bit and the interrupt request flag bit SIOF are 1 SCKE Shift clock output enable bit This bit controls shift clock input and output when UART SIO selection bit SMC2 RSEL is set to 1 The P45 SCK pin function as the shift clock input pin when this bit is set to 0 and as the shift clock output pin when this bit is set to 1 Notes e Set the P45 SCK pin as an input port when using this pin as the shift clock input Also selects external shift clock operation in the shift clock selection bits CKS1 CKSO 11p e When using this pin as internal shift clock output SCK 1 select internal shift clock operation CKS1 CKSO other than lei References e The pin functions as the SCK output pin when shift clock is enabled SCKE 1 regardless of the state of the general purpose I O port P45 Set to shift clock input operation SCKE 0 when using this pin as a general purpose I O port P45 SOE Serial data output enable bit This bit controls serial data output when UART SIO selection bit SMC2 RSEL is set to 1 The P44 SO pin functions as a general purpose I O port P44 when this bit is set to 0 and as the serial data output pin SO when this bit is set to 1 Reference e The pin function
183. hen Read modify write instruction executed KH i d On Output latch DDR SPL Pin state specification bit in the standby control register STBC LO Se np Lea II OH N ch 7 7 Stop mode SPL 1 Reference Peripheral inputs continuously input the pin value except during stop mode E Port 4 registers The port 4 registers consist of PDR4 and DDR4 Each bit in these registers has a one to one relationship with a port 4 bit and port 4 pin Table 4 6 2 Correspondence between pin and register for port 4 shows the correspondence between pins and registers for port 4 Table 4 6 2 Correspondence between pin and register for port 4 PDR4 Correspondence between register bit and pin Corresponding pin DDR4 Corresponding pin 93 CHAPTER 4 I O PORTS 4 6 1 Port 4 Registers PDR4 DDR4 This section describes the port 4 registers E Port 4 register functions 94 Port 4 data register PDR4 The PDR4 register holds the pin states Therefore when used as an output port that is not a peripheral output it reads out as the same state 0 or 1 as that of the output data latch and when it is an input port the output latch state cannot be read out Reference As the bit manipulation instructions SETB and CLRB read the output latc
184. hen a reset source occurs with a few exceptions all I O pins peripheral pins go to the high impedance state and the mode data is read from internal ROM pins with a pull up resistor optional go to the H level E Pin states after reading mode data With a few exceptions the I O pins remain in the high impedance state immediately after reading the mode data pins with a pull up resistor optional go to the H level Note For devices connected to pins that change to high impedance state when a reset source occurs take care that malfunction does not occur due to the change in the pin states See Appendix E MB89950 950A Series Pin States for pin states at the time other than reset 48 CHAPTER 3 CPU 3 6 Clocks The clock generator provides an internal oscillation circuit By connecting with external resonator the circuits generate the high speed main clock sources Alternatively externally generated clock input can be used Clock controller controls the speed and supply of the clock signal according to the standby mode E Clock supply map Oscillation of a clock and its supply to the CPU and peripheral circuit peripheral functions are controlled by the clock controller As shown in the map operating clocks fed to the CPU and peripheral circuits are affected by standby sleep stop mode Divide by n output derived from the free run counter clocked by the peripheral circuit clock is supplied to the peripheral f
185. his bit when an external shift clock is selected CKS1 CKSO 11 enables data transfer clears the shift clock counter and sets serial I O to delay for input of the external shift clock This bit is cleared to 0 and the SIOF bit is set to 1 when transfer completes Writing 0 to this bit while transfer is in progress SST 1 aborts the transfer After halting a transfer data must be set again to the SDR register for data output and transfer restarted the shift clock counter cleared for data input 178 CHAPTER 9 8 BIT SERIAL UO 9 3 2 Serial Data Register SDR The serial data register SDR stores the transfer data for 8 bit serial I O The register can function as the transmit data register for serial output operation or as the receive data register for serial input operation E Serial data register SDR Figure 9 3 4 Serial data register SDR shows the bit structure of the serial data register Figure 9 3 4 Serial data register SDR Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value SDR 001DH XXXXXXXXB R W R W R W R W R W RW RW RW R W Readable and writable X Indeterminate Serial output operation The register functions as the transmit data register When serial I O transfer starts SMR SST 1 the 8 bit serial I O performs serial transfer of the data written in the register Serial input operation
186. imebase timer sets the overflow interrupt request flag bit TBIF to 1 when an overflow occurs on the interval timer bit Consequently the timebase timer generates interrupt requests at fixed intervals the selected interval time based on the time that the counter is cleared E Operation of clock supply function The timebase timer is also used as a timer to generate the main clock oscillation stabilization delay time The time from when the timebase timer counter is cleared and starts counting up until an overflow occurs on the oscillation stabilization delay time bit is the oscillation stabilization delay time If the timebase timer output is selected by the watchdog timer counter WDTC WTE3 to WTEO 0101 clearing the timebase timer counter by entering to stop mode STBC STP 1 will also clear the watchdog timer at the same time 107 CHAPTER 5 TIMEBASE TIMER E Operation of timebase timer 108 The state of following operations are shown in Figure 5 5 2 Operation of timebase timer es A power on reset occurs e Goes to sleep mode during operation of the interval timer function in the main clock mode e Goes to stop mode e A counter clear request occurs The timebase timer is cleared by going to stop mode and its operation is stopped The timebase timer counts the oscillation stabilization delay time after wake up from stop mode Figure 5 5 2 Operation of timebase timer Counter value 1FFFFFH x
187. in the interrupt processing routine to clear the interrupt request References e The UF bit is not set if the counter is stopped PCR1 EN 0 at the same time as the counter value underflows Oly gt 00 e An interrupt request is generated immediately if the UF bit is 1 when the IE bit is changed from disabled to enabled OO gt 1 E Interrupt for pulse width measurement function When the specified measurement completion edge is detected the measurement completion interrupt request flag bit PCR1 IR and the buffer full flag bit PCR1 BF are set to 1 Also when a counter underflow Oly gt On occurs due to measurement of a long pulse the UF bit is set to 1 At this time an interrupt request IRQ3 to the CPU is generated if the interrupt request enable bit is enabled PCR1 IE 1 Write 0 to the IR and UF bit in the interrupt processing routine to clear the interrupt request Also read the PWC reload buffer register RLBR to clear the BF bit to 0 References e The IR and BF bit are not set if the counter is stopped PCR1 EN 0 at the same time as the specified measurement completion edge is detected e An interrupt request is generated immediately if the IR BF or UF bit is 1 when the IE bit is changed from disabled to enabled OO gt 1 E Register and vector table for pulse width count timer interrupt Table 8 4 1 Register and vector table for pulse width count timer interrupt Int
188. ing measurement in pulse width measurement mode the counter stops but the value is not transferred to the RLBR register Restarting operation EN 1 sets the counter value to FF then enables operation Unused bit The read value is indeterminate Writing to this bit has no effect on the operation TE Interrupt request enable bit This bit enables or disables an interrupt request output to the CPU An interrupt request is output when both this bit and one or more of the interrupt request flag bits UF IR and BF are 1 Unused bits The read value is indeterminate Writing to these bits has no effect on the operation UF Underflow 0l gt Uu interrupt request flag bit This bit is set to 1 when the counter underflow 014 gt 00p occurs An interrupt request is output when both this bit and the interrupt request enable bit IE are 1 Writing 0 clears this bit Writing 1 has no effect and does not change the bit value Notes When the interval timer function is active the PWC inverts the timer output bit PCR2 TO if the counter underflow 01y gt 00p occurs In reload timer mode counting down continues from the RLBR register value In one shot timer mode the counter operation automatically stops EN 0 If the counter underflow Oly gt 00p occurs while measuring a long input pulse in the pulse width measurement function this bit is set to 1 and counter operation conti
189. interrupt processing routines the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority Interrupt levels can be set in the range 1 to 3 However the CPU does not accept interrupt requests set to interrupt level 3 Example of multiple interrupts As an example of multiple interrupt processing assume that an external interrupt has a higher priority than the timer interrupt The timer interrupt is set to level 2 and the external interrupt is set to level 1 Figure 3 4 3 Example of multiple interrupts shows the processing when the external interrupt occurs during execution of timer interrupt processing Figure 3 4 3 Example of multiple interrupts Initialize peripheral 1 Timer interrupt occurs 2 Restart main program 8 6 Main program Timer interrupt processing External interrupt processing Interrupt level 2 Interrupt level 1 CCR IL1 ILO 10 CCR 1L1 ILO 01 3 External interrupt occurs 4 External interrupt processing Halt Restart Timer interrupt processing 7 Timer interrupt returns 5 External interrupt returns During execution of timer interrupt processing the interrupt level bits in the condition code register CCR IL1 ILO are automatically set to the same value as the interrupt level setting register ILR1 ILR2 ILR3 corresponding to the timer interrupt level 2 in this example If the i
190. is waked up reset is Reset state is held until external reset is waked up then the reset is operated External reset D operated ES Software and watchdog reset Main clock mode After 4 instruction cycle reset occurs reset is operated Es Device enters main clock oscillation An external circuit must be provided stabilization delay time at power on to hold external reset asserted at Reset is operated after delay time power on until main clock has had ends 2 time to stabilize Power on reset 1 No oscillation stabilization delay time is required for external reset while main clock mode is operating Reset is operated after external reset is waked up 2 If the reset output option is selected L is output at RST pin during the main clock oscillation stabilization delay time 3 If the reset output option is selected L level is output at RST pin during 4 instruction cycle 44 CHAPTER 3 CPU 3 5 1 External Reset Pin Inputting an L level to the external reset pin generates a reset If products are set to with the reset output optional the pin outputs an L level depending on internal reset sources E Block diagram of external reset pin The external reset pin RST on products with the reset output is a hysteresis input type and N ch open drain output type with a pull up resistor The external reset pin on products without a reset output option is only for the reset input Fig
191. ister and RAM contents at their value immediately before entering stop mode Writing 1 to the stop bit in the standby control register STBC STP puts the CPU to stop mode At this time external pin states are held if the pin state specification bit STBC SPL is 0 If SPL is 1 external pins go to the high impedance state Pins with the pull up resistor optional go to the H level If an interrupt request is generated when 1 is written to the STP bit the write to the bit is ignored and the CPU continues the instruction execution without entering stop mode The CPU does not assume stop mode even after completion of the interrupt processing Prohibit interrupt request output from the timebase timer TBTC TBIE 0 before entering stop mode in main clock mode as necessary Wake up from stop mode A reset or an external interrupt wakes up the CPU from stop mode If reset occurs during stop mode on a product with power on reset the reset operation starts after the main clock oscillation stabilization delay time Products without power on reset do not require for the oscillation stabilization delay time after a reset in stop mode The reset initializes pin states If an interrupt request with an interrupt level higher than 11 occurs from an external interrupt circuit during stop mode the CPU wakes up from stop mode regardless of the interrupt enable flag CCR I and interrupt level bits CCR IL1 ILO in the CPU Onl
192. ister returns the pin value Operation as a peripheral output e Ifa peripheral output enable bit is set to enable the corresponding pin becomes a peripheral output e As the pin value can be read even if the peripheral output is enabled the peripheral output value can be read via the PDR4 register Operation as a peripheral input e A port pin is set as a peripheral input by setting the corresponding DDR4 register bit to 0 e Reading the PDR4 register returns the pin value regardless of whether or not the peripheral is using the input pin Operation at reset e Resetting the CPU initializes the DDR4 register value to 0 This sets output transistors OFF pins become input ports and sets the pins to the high impedance state e The PDR4 register is not initialized by a reset Therefore to use as output port the output data must be set in the PDR4 register before setting the corresponding DDR4 register bit to output mode 96 CHAPTER 4 I O PORTS Operation in stop mode e The pins go to the high impedance state if the pin state specification bit in the standby control register STBC SPL is 1 when the device goes to stop mode This is achieved by forcibly setting the output transistor OFF regardless of the DDR4 register value Table 4 6 4 Port 4 pin state lists the port 4 pin states Table 4 6 4 Port 4 pin state Normal operation Pin name sleep mode Stop mode SPL 1 stop mode SPL 0 P40
193. isters A and T three address pointers IX EP and SP and the program status PS All registers are 16 bits E Dedicated register configuration The dedicated registers in the CPU consist of seven 16 bit registers Some of these registers are also able to be used as 8 bit register using the lower 8 bits only Figure 3 2 1 Dedicated register configuration shows the structure of the dedicated registers Figure 3 2 1 Dedicated register configuration Initial value K 16 bits gt Program counter PRESS PC A register for indicating the current instruction storage positions Indeterminate A Accumulator A temporary register for storing arithmetic operations or transfer instructions Temporary accumulator A register for performing arithmetic operations with Indeterminate IX the accumulator Index register A register for indicating an index address Indeterminate T Indeterminate EP Extra pointer A pointer for indicating a memory address Indeterminate SP Stack pointer I lag 0 A register for indicating the current stack location ILO IL1 11 RP CCR Program status Other bits are indeterminate Are pelea storing a register bank panter and condition code PS E Dedicated register functions Program counter PC The program counter is a 16 bit counter that indicates the memory address of the instruction currently being executed by the CPU
194. it l p SLP bit L STBC register Wake up from stop mode by an external interrupt Wake up from sleep mode by IRQ3 i i d i STP bit s STBC register Sech d 163 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 9 Notes on Using Pulse Width Count Timer This section lists points to note when using the pulse width count timer E Notes on using pulse width count timer Error When using the interval timer function activating the counter by program is not synchronized with the start of counting down using the selected internal count clock Therefore the time from activating the counter until an underflow occurs may be shorter than the theoretical time by a maximum of one cycle of the count clock Figure 8 9 1 Error on starting counter operation shows the error that occurs on starting counter operation Figure 8 9 1 Error on starting counter operation Counter value Set value n x n 1 X n 2 X n 3 x n 4 X Count clock One cycle Error Cycle of set value n Counter activate Notes on setting by program 164 Do not modify the contents of the PWC pulse width control register 2 PCR2 when the interval timer function or pulse width measurement function is operating PCR1 EN 1 Stop the counter EN 0 disable interrupts IE 0 and clear the interrupt request flag bits UF IR BF 000g
195. ith power on reset Figure 3 7 2 1 Main clock oscillation stabilization delay time completes timebase timer output 2 Wake up from Reset input Products without power on reset Figure 3 7 3 1 External reset input must be held asserted until main clock oscillation has had time to stabilize 2 Wake up from reset input de asserted Reset in RUN state 3 Have external software or watchdog reset Go to wake up from standby mode Table 3 7 4 Go to wake up from standby mode State transition 3 Have external software or watchdog reset Conditions events required for transition Products with power on reset Figure 3 7 2 Products without power on reset Figure 3 7 3 Go to sleep mode 1 STBC SLP 1 1 STBC SLP 1 Wake up from sleep mode 2 Interrupt 3 External reset 2 Interrupt 3 External reset Go to stop mode 4 STBC STP 1 4 STBC STP 1 Wake up from stop mode 5 External interrupt 6 Main clock oscillation stabilization delay time completes timebase timer output 7 External reset 8 External reset during oscillation stabilization delay time STBC Standby control register 64 5 External interrupt 6 Main clock oscillation stabilization delay time completes timebase timer output 7 External reset 8 External reset during oscillation stabilization delay time CHAPTER 3 CPU 3
196. ive parity circuit stores the last bit received Data transmit control circuit The transmit control circuit consists of a transmission byte counter and a transmission parity circuit The transmit byte counter counts number of data bytes transmit and generates an interrupt after having received a data of the set length The transmission circuit generates a parity bit when transmitting data with a parity bit When 9 bit long data is sent the MSB of the transmit data is sent Serial mode control register 1 SMC1 This register controls operating modes in the UART The register is used to select parity non parity stop bit length operating mode data length synchronous asynchronous enable disable of UART serial clock output SCK and enable disable of serial data output SO Serial mode control register 2 SMC2 This register controls UART starting stopping operation UART SIO function and input clock divider of the baud rate generator Serial rate control register SRC This register controls the data transmission rate baud rate The register selects transfer rate generated by the baud rate generator Serial status and data register SSD This register is used to select or show transmit receive operation to indicate error status and to select received transmitted data parity Serial input data register SIDR This register holds received data Serial data received is converted to parallel data and stored in the regist
197. l I O 9 4 8 bit Serial I O Interrupts 9 5 Operation of Serial Output 9 6 Operation of Serial Input 9 7 States in Each Mode during 8 bit Serial UO Operation 9 8 Notes on Using 8 bit Serial I O 9 9 Connection Example for 8 bit Serial I O 9 10 Program Example for 8 bit Serial I O 169 CHAPTER 9 8 BIT SERIAL I O 9 1 Overview of 8 bit Serial UO The 8 bit serial I O function is the serial transfer of 8 bit data synchronized with the shift clock The shift clock can be selected from one external and three internal clocks The data shift direction can be selected as either LSB first or MSB first E Serial I O function The 8 bit serial I O function is the serial input and output of 8 bit data synchronized with the shift clock e The serial I O converts 8 bit parallel data to serial and outputs the serial data Similarly the serial I O converts input serial data to parallel and stores the data e One shift clock can be selected from one external and three internal clocks e The serial I O can control input and output of the shift clock and can output the internal shift clock e The data shift direction transfer direction can be selected as either LSB first or MSB first Table 9 1 1 Shift clock cycle and transfer speed Shift clock Clock cycle Frequency Hz Transfer speed Foy 5 MHz Internal shift clock output 2 tinst 1 2 Goal 625 kbps 8 tinst 1 8 tinst 156 kbps 32 tinst 1 32 tinst 39 kbp
198. l Overflow 1 bit watchdog counter Watchdog reset 117 CHAPTER 6 WATCHDOG TIMER 6 5 Notes on Using Watchdog Timer This section lists points to note when using the watchdog timer E Notes on using watchdog timer Stopping watchdog timer Once activated the watchdog timer cannot stop until a reset generates Clearing watchdog timer Clearing the counter being used as a count clock of the watchdog timer timebase timer or watch prescaler also simultaneously clears the watchdog timer counter The watchdog timer counter is cleared when entering sleep or stop mode Notes on programming When writing a program in which the watchdog timer is repeatedly cleared in the main loop including interrupt processing it should be less than the minimum watchdog timer interval time 118 CHAPTER 6 WATCHDOG TIMER 6 6 Program Example for Watchdog Timer This section gives a program example for the watchdog timer E Program example for watchdog timer Processing description Activates the watchdog timer immediately after the program Clears the watchdog timer in each loop of the main program The processing time for the main loop including interrupt processing must be less than the minimum interval time of the watchdog timer approximately 419 43 ms at 5 MHz operation Coding example WDTC EQU 0009H Address of the watchd
199. l down resistor Reset I O pin This pin consists of an N ch open drain output with a pull up resistor and hysteresis input A LOW level is output from this pin A LOW voltage on this port generates a RESET condition N channel open drain type general purpose I O ports Also serve as LCD controller driver segment outputs Switching between port output and segment driver output is performed by the mask option P00 SEG20 48 to 41 49 to 42 to PO7 SEG27 N channel open drain type general purpose I O ports Also serve as LCD controller driver segment outputs Switching between port output and segment driver output is performed by the mask option P10 SEG28 41 to 34 to P17 SEG35 N channel open drain type general purpose I O ports Also serve as LCD controller driver segment outputs Switching between port output and segment driver output is performed by the mask option P20 SEG36 32 to 27 33 to 28 to P25 SEG41 14 to 13 15 to 14 P30 to P31 N channel open drain type general purpose I O ports P32 V 1 to N channel open drain type general purpose I O ports peed EE P33 V2 Also serve as LCD controller driver power supply General purpose I O port 2 0 pan A pull up resistor option is provided Table 1 7 1 Pin description 2 2 Pin name P41 PWM IO circuit type CHAPTER 1 OVERVIEW Function General purpose I O port Also serves as PWM timer toggle output PWM A pull
200. l register 1 SMC1 sets synchronous mode stop bit length data length parity non parity and select the port function of SCK and SO E Serial mode control register 1 SMC1 Figure 10 4 2 Serial mode control register 1 SMC1 Address 0020H Initial value Unused Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value PEN SBL MC1 MCO SMDE SCKE SOE 00000 008 R W R W R W R W R W R W R W gt SOE Serial output enable bit 0 Functions as general purpose I O port P44 1 Functions as serial output SO gt SCKE Serial clock enable bit Functions as general purpose I O port P45 0 When the port is set to input DDR4 bit5 0 it also functions as serial clock input pin 1 Functions as serial clock SCK gt SMDE Operation mode control bit 0 Synchronous transfer 1 Asynchronous transfer Transfer mode control bits gt MC1 MCO Mode Data length W 0 0 5 4 0 1 1 8 7 1 0 Reserved 1 1 3 9 8 Value in parantheses is initial value and indicates the data length with parity gt SBL Stop bit length control bit 0 2 bit length 1 1 bit length PEN Parity control bit 0 Non parity R W Readable and writable 1 Parity odd even selected by TD8 TP bit 205 CHAPTER 10 UART Table 10 4 1 Serial mode control register 1 SM
201. l timer bit Four different interval times can be selected 105 CHAPTER 5 TIMEBASE TIMER 5 4 Timebase Timer Interrupt The timebase timer can generate an interrupt request when an overflow occurs on the specified bit of the timebase counter for the interval timer function Interrupts for interval timer function The counter counts up on the internal count clock When an overflow occurs on the selected interval timer bit the overflow interrupt request flag bit TBTC TBIF is set to 1 At this time an interrupt request IRQ6 to the CPU is generated if the interrupt request enable bit is enabled TBTC TBIE 1 Write 0 to the TBIF bit in the interrupt processing routine to clear the interrupt request The TBIF bit is set when at the specified counter bit overflows regardless of the TBIE bit value Note When enabling an interrupt request output TBIE 1 after wake up from a reset always clear the TBIF bit TBIF 0 at the same time References e An interrupt request is generated immediately if the TBIF bit is 1 when the TBIE bit is changed from disabled to enabled 0 gt 1 e The TBIF bit is not set if the counter is cleared TBTC TBR 0 at the same time as an overflow on the specified bit occurs E Oscillation stabilization delay time and timebase timer interrupt If the interval time is set shorter than the main clock oscillation stabilization delay time an interval interrupt request
202. l value 0030H EIR1 SL11 SL10 EIE1 EIRO SLO1 SLOO EIEO 000000008 R W R W R W R W R W R W R W R W e L gt EIEO INTO interrupt request enable bit 0 Disables output of interrupt requests 1 Enables output of interrupt requests gt SL01 SLOO INTO edge polarity selection bits 0 0 No edge detection 0 1 Rising edge 1 0 Falling edge 1 1 Both edge INTO external interrupt request flag bit gt EIRO e Head Write 0O The specified edge has not been detected Clears this bit 1 The specified edge has been detected No effect The bit does not change __ FIE1 INT1 interrupt request enable bit 0 Disables output of interrupt requests 1 Enables output of interrupt requests L gt SL11 SL10 INT1 edge polarity selection bits 0 0 No edge detection 0 1 Rising edge 1 0 Falling edge 1 1 Both edge INT1 external interrupt request flag bit S EIR as a Read Write R W Readable and writable O The specified edge has not been detected Clears this bit Initial value 1 The specified edge has been detected No effect The bit does not change 228 Bit CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE Table 11 3 2 External interrupt control register EIC bits Function EIR1 INTI external interrupt request flag bit This bit is set to 1
203. le for the External Interrupt Circuit ccecccceeeeeeeeeeeeeeeeeeeeeeeeeeaeeeseaeeeseaeeseeieeeeeaees 232 CHAPTER 12 LCD CONTROLLER DRIVER cccccsseeeeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeseeeeees 233 12 1 Overview of LCD Conttroller Driver 234 12 2 Block Diagram of LCD Controller Driver ccceecececeseeeeeneeeeeneeeeeeeeeeeeeeeseaeeeeeaeeseeaeesseaeeeseaeeseeaeeseeaees 235 12 2 1 LCD Controller Driver Internal Voltage Divider 0 ceccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseaaeeseaees 237 12 2 2 LCD Controller Driver External Voltage Divider A 239 12 3 Structure of LCD Controller Driver 0 ccccccecscececeeeeeneeeeeneeeseaeee tenes eeeaeeeseeeeeeeeaeeeeaeeeseaeeeseaeeeseneeeseaaes 241 12 3 1 LCD Control Register LCDR 0 c ccccceeeceeeeeeeceeeeeneeeeeeeeeeeeaeeeeaeeeteaee encase secaeeenaeeseeeeeseaaeeseaeess 244 12 3 2 Segment Output Select Register SEGR s ssssessssessssesisesiieriiserttritstiinstittstitstrntstnnnsnnnnnnnnntenna 246 12 3 3 DISplay OT E hauls hata ET 248 12 4 Operation of LCD Conttroller Driver ccceecccececeeeeeneeeeeeeeeeeaeeeeeeeeeceaeeeeeaeeeeeeeeeeeaeeeseaeeeseaeeseeeeeeeaees 250 12 4 1 Output Waveforms during LCD Controller Driver Operation 1 2 Duty Ratio c eeeeee 251 12 4 2 Output Waveforms during LCD Controller Driver Operation 1 3 Duty Ratio eee 254 12 4 3 Output Waveforms during LCD Controller Driver Operation 1 4 Duty Ratio eee 257 12 5 Program Exam
204. le from four transfer clocks one external shift clock three internal shift clocks 1 6 us 6 4 us 25 6 us at 5 MHz LCD controller driver Common output 4 max Segment output 42 max Operation mode 1 2 bias and 1 2 duty 1 3 bias and 1 3 duty 1 3 bias and 1 4 duty LCD display RAM size 21 bytes 42 x 4 bits max 168 pixels Dividing voltage for LCD driving built in external voltage divider selectable External interrupt 2 independent channels interrupt vector request flag request output enable Edge selectability rising falling Unless otherwise specified values given for clock cycle conversion times etc are for 5 MHz operation 1 Segment pins can be selected by mask option CHAPTER 1 OVERVIEW 1 3 Differences among Products This section describes the differences among the 4 products in the MB89950 950A series and lists points to note in product selection E Differences among products and points to note for product selection Table 1 3 1 Package and corresponding products Package Part number MB89951A MB89953A MB89P955 MB89PV950 FPT 64P M09 LQFP 64 0 65 mm pitch MQP 64C P01 MQEP 64 1 mm pitch O Available X Not available Current consumption e In the case of the MB89PV950 add the current consumed by the EPROM which is connected to the top socket e When operated at low speed the product with a one time PROM OTPROM or an EPROM will con
205. ler Driver 12 4 Operation of LCD Controller Driver 12 5 Program Example for LCD Controller Driver 233 CHAPTER 12 LCD CONTROLLER DRIVER 12 1 Overview of LCD Controller Driver The LCD controller driver includes 21 bytes of on chip display data in memory the contents of which control an LCD via 42 segment and 4 common outputs The function can drive an LCD panel directly using one of three selectable duty ratios E LCD controller driver function The LCD controller driver function displays the contents of a display data memory directly to the LCD Liquid Crystal Display panel by segment and common outputs e LCD can be driven directly e Built in voltage divider for LCD driving voltage Can be connected to the external voltage divider e Up to 42 segment outputs SEGO to SEG41 and four common outputs COMO to COM3 may be used e Built in display RAM 21 bytes 42 x 4 bits e Three selectable duty ratios 1 2 1 3 and 1 4 Not all duty ratios are available with all bias settings e SEG20 to SEG41 can be used as general purpose port option Table 12 1 1 Bias and duty ratio combinations shows the duty ratios available with various bias settings Table 12 1 1 Bias and duty ratio combinations Duty ratio 1 2 duty ratio 1 3 duty ratio 1 4 duty ratio 1 2 bias 1 3 bias O Recommended mode X Do not use Note P00 SEG20 to PO7 SEG27 P10 SEG28 to P17 SEG35 and P20 SEG36 to P25 SEG41
206. ls Its contents are automatically read out to the segment outputs in synchronous with the timing of the selected common signal Prescaler The prescaler generates one of the 4 frame frequencies according to the LCD control register setting Timing controller This block controls the segment and common signals based on the frame frequency and LCD control register settings V I converter This circuit generates alternating current waveforms from the voltage signals it receives from the timing controller to drive the LCD Common output driver This block contains the drivers for the LCD common pins Segment output driver This block contains the drivers for the LCD segment pins Voltage divider optional This voltage divider is used to provide the divided LCD driving voltage The voltage divider can be connected externally CHAPTER 12 LCD CONTROLLER DRIVER 12 2 1 LCD Controller Driver Internal Voltage Divider LCD driver supply voltage can be taken from an internal voltage divider external voltage divider may also be used E Internal voltage divider In these devices external voltage divider may also be connected at pins V1 through V3 The selection of internal or external voltage divider is made by the drive supply voltage control bit of LCD control register LCDR VSEL VSEL 1 connects the internal voltage divider Set VSEL to 1 when you want to use the internal voltage divider only when no ex
207. mebase timer 5 1 Overview of Timebase Timer 5 2 Block Diagram of Timebase Timer 5 3 Timebase Timer Control Register TBTC 5 4 Timebase Timer Interrupt 5 5 Operation of Timebase Timer 5 6 Notes on Using Timebase Timer 5 7 Program Example for Timebase Timer 99 CHAPTER 5 TIMEBASE TIMER 5 1 Overview of Timebase Timer The timebase timer provides interval timer functions Four different interval times can be selected The timebase timer uses a 20 bit free run counter which counts up in synchronous with the internal count clock divide by two the main clock oscillation frequency The timebase timer also provides the timer output for the oscillation stabilization delay time the operating clock for the watchdog timer the operating clock for LCD controller driver and sampling clock for noise filter circuit in PWC timer The timebase timer stops operating in stop mode E Interval timer function The interval timer function generates repeated interrupts at fixed time intervals e The timer generates an interrupt each time the interval timer bit overflows on the timebase timer counter e The interval timer bit interval time can be selected from four different settings Table 5 1 1 Timebase timer interval time lists the available interval time for the timebase timer Table 5 1 1 Timebase timer interval time Internal count clock cycle Interval time Foy 5 MHz e approx 6 55 ms ON Re approx
208. mer Function This section describes the operation of the interval timer function of the 8 bit PWM timer E Operation of interval timer function Figure 7 5 1 Interval timer function settings shows the settings required to operate as an interval timer function Figure 7 5 1 Interval timer function settings Bit 7 Bit 6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 CNTR P T P1 PO TPE TIR OE TIE 0 1 Used bit 1 Set 1 COMR Sets interval time compare value 0 Set 0 On activation the counter starts to count up from 00 on the rising edge of the selected count clock When the counter value matches the value set in the COMR register compare value the PWM timer inverts the level of the output pin PWM on the next rising edge of the count clock clears the counter sets the interrupt request flag bit CNTR TIR 1 and restarts counting from 00y Figure 7 5 2 Operation of 8 bit PWM timer shows the operation of the 8 bit PWM timer Figure 7 5 2 Operation of 8 bit PWM timer Counter value Compare value FFH Compare value 80H FFH e pines ee Sp mei fot ere ee a 80H te EE EE EE SEET taken tae 00H l gt 1 i i Time Timer cycle COMR value modified FFH 80H GOMK k FFH Cleared by the program TIR bit TPE bit OE bit PWM pin
209. n E Main clock oscillation stabilization delay time and the reset source Whether there will be an oscillation stabilization delay time depends on the operating mode when reset occurs and the power on reset option selected Following reset operation always starts out in the normal main clock operating mode regardless of the kind of reset it was or the operating mode the clock mode and standby mode prior to reset Therefore if reset occurs while the main clock oscillator is stopped or in a stabilization delay time the system will be in a main clock oscillation stabilization reset state and a clock stabilization period will be provided If the device is set for no power on reset however no main clock oscillation stabilization delay time is provided for power on or external reset In software or watchdog reset if the reset occurs while the device is in main clock mode no stabilization time is provided Table 3 5 2 Reset source and oscillation stabilization delay time shows the relationships between the reset sources and the main clock oscillation stabilization delay time and reset mode mode fetch operations Table 3 5 2 Reset source and oscillation stabilization delay time Reset operation and main clock oscillation stabilization delay time Reset source Operating state With power on reset Without power on reset After the main clock oscillation At power on stabilization delay time if the during stop mode external reset
210. n Hayato Co Ltd Phone 81 3 3986 0403 E Memory space Figure D 3 1 Memory map of piggyback evaluation device Normal operation Corresponding addresses on 0000H the EPROM programmer 1 0 0080H RAM 0480H Not available 8000H 0000H Program area Program area PROM PROM FFFFH s CEEER E Programming to EPROM 1 Set the EPROM programmer to the MBM27C256A 2 Load program data into the EPROM programmer at 0000y to 7FFFy 3 Program to 0000y to 7FFFy with the EPROM programmer 294 APPENDIX E MB89950 950A Series Pin States APPENDIX E MB89950 950A Series Pin States This section describes the pin states of the MB89950 950A series in various modes E MB89950 950A series pin states The state of each pin of the MB89950 950A series of microcontrollers at sleep stop and reset is as follows 1 Sleep The pin state immediately before entering sleep mode is held 2 Stop The pin state immediately before entering stop mode is held when the stop mode is started and bit 5 of the standby control register STBC is set to 0 When this bit is 1 outputs go to Hi Z High 3 impedance and input output pins go High Reset All I O go to Hi Z and peripheral pins excluding pins for pull up option go H level E Pin states in various modes Table E 1 Pin states in various modes Pin name COMO to COM3 Normal operation COM outputs Sleep mode COM ou
211. n either as N ch open drain I O ports Segment output P14 to P15 or as LCD segment outputs SEG32 to SEG33 selection bit Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 1 SEG10 e Selects P10 SEG28 to P13 SEG31 to function either as N ch open drain I O ports Segment output P10 to P13 or as LCD segment outputs SEG28 to SEG31 selection bit Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 0 SEGO0 e Selects POO SEG20 to PO7 SEG27 to function either as N ch open drain I O ports Segment output selection bit P00 to P07 or as LCD segment outputs SEG20 to SEG27 Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option 247 CHAPTER 12 LCD CONTROLLER DRIVER 12 3 3 Display RAM Display RAM consists of 42 x 4 bit 21 bytes of display data memory used to generate the segment output signals E Display RAM and output pins The contents of display RAM are automatically read out and output via the segment outputs in synchronous with the selected common signal timing A 1 bit is converted to a select display on voltage and a 0 to a deselect display off voltage Since the operation of the LCD is not directly related to the operation of the CPU display RAM read write timing can be set by the user The SEG20 to SEG41 pins that are not made de
212. n this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan 2002 FUJITSU LIMITED Printed in Japan READING THIS MANUAL E Notations of the Register Name and Pin Name Example for description of register name and bit name By writing 1 to the sleep bit STBC SLP in the standby control register D Bit name abbreviation Bit name Register name Register name abbreviation Disable the interrupt request output TBTC TBIE Q from the timebase timer Setup data Bit name abbreviation Register name abbreviation Interrupt is accepted if the interrupt is enabled CCR 1 Register name abbreviation Bit name abbreviation Current status Notations of a double purpose pin P22 SCK pin Some pins can be used by switching their functions using for example settings by a program Each double purpose pin is represented by separating the name of each function using E Documents and Development Tools Required for Development Items necessary for the development of this product are as follows To obtain the necessary documents and development tools contact a company sales representative Manuals required for development Check field O F MC 8L MB89950 950A series data sheet provides a table of electri
213. name sleep mode Stop mode SPL 1 stop mode SPL 0 General purpose I O ports segment P10 SEG28 to P17 SEG35 i driver output SPL Pin state specification bit in the standby control register STBC Hi Z High impedance 81 CHAPTER 4 I O PORTS 4 4 Port 2 Port 2 is N ch open drain I O port that also serves as LCD segment driver outputs Port 2 pins can be switched between LCD segment driver output and port operation by mask option This section principally describes the port functions when operating as N ch open drain UO port The section describes the port structure and pins the pin block diagram and the port register for port 2 Structure of port 2 Port 2 consists of the following two components e N ch open drain I O pins LCD segment driver output pins P20 SEG36 to P25 SEG41 e Port 2 data register PDR2 E Port 2 pins Port 2 consists of six N ch open drain I O When pins are used by the peripheral they cannot be used as N ch open drain I O Table 4 4 1 Port 2 pins lists the port 2 pins Table 4 4 1 Port 2 pins EOS Circuit type Pin name Function Shared peripheral Output P20 SEG36 P20 N ch open drain I O SEG36 LCD segment driver output P21 SEG37 P21 N ch open drain I O SEG37 LCD segment driver output P22 SEG38 P22 N ch open drain I O SEG38 LCD segment driver output Segment N ch P23 SEG39 P23 N ch open drain I O SEG39 LCD segment driver output open drain
214. nces e The UF bit is set to 1 if counter underflows Oly gt On regardless of the value of the interrupt request enable bit PCR1 IE e When the counter is stopped PCR1 EN 0 while the interval timer function is selected the TO bit maintains the value it had immediately before the counter stopped 158 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 6 Operation of Pulse Width Measurement Function This section describes the operations of the pulse width measurement function of the pulse width count timer E Operation of pulse width measurement function Figure 8 6 1 Pulse width measurement function settings shows the settings required to operate as the pulse width measurement function Figure 8 6 1 Pulse width measurement function settings Bit7 Bit6 BitS Bit4 Bit3 D Biti Bit O DDR4 X D X X X 0 X X PCR1 EN IE UF IR BF Used bit 1 9 A A Used to measure long PCR2 FC RM TO C1 co WI WO pulse widths 1 X X X Unused bit 1 Set 1 RLBR Holds the pulse width measurement value 0 Set 0 When counter operation is enabled the counter starts to count down from FFy when a measurement start edge is detected on the pulse input to the PWC pin For H level measurement the counter starts measurement from the next rising edge if the input is already H On detection of the measurement completion edge the curre
215. nd P46 INTO pins continuously function as external interrupt inputs the external interrupt circuit does not output interrupts if output of interrupt requests is disabled for the pin The pin states can be read directly from the port data register PDR4 at any time Table 11 3 1 External interrupt circuit pins When used as an external External interrupt pin interrupt input interrupt requests enabled When used as general I O port interrupt requests disabled P46 INTO INTO EIC EIEO 1 P46 EIC EIEO 0 P42 PWC INT1 INTI EIC EIEI 1 P42 EIC EIE1 0 INTO INT1 The external interrupt circuit generates the interrupt request when an edge of the specified polarity is detected on the pin E Block diagram of the external interrupt circuit pins Figure 11 3 1 Block diagram of the external interrupt circuit pins To external interrupt Di PDR Port data register O External interrupt enable Pull up resistor PA Stop mode SPL 1 Approx 50 kQ b i S Mask option PDR read i R N i i 1 1 i 1 SE i 1 E PDR read i P ch S When Read modify write instruction executed l gj T g Output latch Di L P ch i E PDR write AE NES E E r dE eege e EE eee d Pin Port data direction register DDR Se LJ eH N ch Stop mode SPL 1 DDR write SPL Pin st
216. nd output Six of these pins are also used as I O pins for various peripherals While they are being used by the peripheral these pins cannot be used as the general purpose I O port Table 4 6 1 Port 4 pins lists the port 4 pins Table 4 6 1 Port 4 pins I O type eee Pin name Function Shared peripheral Circuit Input Output type P40 P40 general purpose I O port P41 PWM P41 general purpose I O port PWM PWM output P42 PWC INT1 P42 general purpose I O port PWC INT1 PWC or external interrupt input P43 SI P43 general purpose I O port SI UART 8 bit SIO serial data input P44 SO P44 general purpose I O port SO UART 8 bit SIO serial data output P45 SCK P45 general purpose I O port SCK UART 8 bit SIO serial clock I O P46 INTO P46 general purpose I O port INTO External interrupt input See Section 1 7 I O Pins and Pin Functions for a description of the circuit type 92 E Block diagram of port 4 pins CHAPTER 4 I O PORTS Figure 4 6 1 Block diagram of port 4 pins Internal data bus To external interrupt lt To peripheral input cl a PDR Port data register eC External interrupt enable lt Q e a PDR write i i Pull ist vc D Stop mode SPL 1 Approx 50 kQ I XN Mask option PDR read ee ees Peripheral output i l Peripheral PDR read output enable ij P ch W
217. nd the pin goes to the high impedance state e Reading the PDRO register returns the pin value Operation as an LCD segment driver output e When the LCD output mask option is selected set the PDRO register bits corresponding to the LCD segment driver output pins to 1 to turn the output transistor OFF e You cannot read the LCD output data by reading PDRO Operation at reset e Resetting the CPU initializes the PDRO register values to 1 This turns OFF the output transistor for all pins and all pins are in high impedance Hi Z state 75 CHAPTER 4 I O PORTS Operation in stop mode e The output transistors are forcibly turned OFF regardless of the PR DO register value and the pins go to the high impedance state if the pin state specification bit in the standby control register STBC SPL is 1 when the device goes to stop mode Moreover to avoid leakage from floating input pin input must be driven by either 1 or 0 when SPL 1 Table 4 2 4 Port 0 pin state lists the port 0 pin states Table 4 2 4 Port 0 pin state Normal operation Pin name sleep mode Stop mode SPL 1 stop mode SPL 0 General purpose I O ports segment driver P00 SEG20 to PO7 SEG27 output SPL Pin state specification bit in the standby control register STBC Hi Z High impedance 76 CHAPTER 4 I O PORTS 4 3 Port 1 Port 1 is N ch open drain I O port that also serves as LCD segment driver outpu
218. ng waveforms reflecting the contents of display RAM will be output at the segment and common output pins COMO to COM3 and SEGO to SEG42 Although the clock for frame period generation can be switched even while the LCD is displaying data the display may flicker when the switching occurs This can be avoided by temporarily blanking the display LCDR BK 1 etc while switching The display driving output is a two frame a c waveform for which the bias level and display duty cycle is selected by settings When LCD operation is stopped LCDR MS1 MSO 00 and during reset all COM and SEG output pins are pulled L state so that nothing is displayed on the LCD panel Note If the selected frame cycle generate clock were to stop while the LCD is operating the circuit that converts the waveform from d c to a c would also stop causing a d c voltage to be applied to the liquid crystal cells The LCD must therefore be stopped before the clock is stopped The conditions under which the main clock is stopped is a function of the clock mode and standby mode E LCD driving waveforms 250 It is characteristic of LCD that applying d c drive to the panel can cause electrochemical degradation of the material used in the LCD cells For this reason the LCD controller driver includes a circuit to convert the original driving waveform to a two frame a c output waveform zero d c bias to drive the LCD There are three types of output waveform
219. nication interface The UART supports both synchronous clock and asynchronous clock mode and transmits variable length serial data The transmission format is the NRZ system and the transmission data rate is configurable by setting the proprietary baud rate generator external clocks internal timers E UART function The UART communicates with other CPU s and peripheral devices by transmitting receiving serial data serial input output e The full duplex double buffer embedded in the device enables full duplex bi directional communication e User can configure the UART to the synchronous transfer mode or asynchronous transfer mode e Internal baud rate generator allows user to select a baud rate from eight different speed for internal clock The baud rate is also configured by setting external clock inputs and 8 bit PWM timer allowing flexible setting of rate e The variable data length system allows users to set the data length at 5 8 and 9 bit with non parity or 4 7 and 8 bit with parity See Table 10 1 1 UART operating mode e The data transmission format is based on the NRZ Non Return to Zero system Table 10 1 1 UART operating mode Data length Operating mode Clock mode Stop bit length Non parity Parity Asynchronous Synchronous 1 bit or 2 bits P Asynchronous Synchronous 1 bit or 2 bits H Asynchronous Synchronous 1 bit or 2 bits UI Asynchronous Synchronous 1 bit or 2 bits UI
220. nnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnna 111 GI Overview of Watchdog Timer simer te nhan aae ea aa nr Daa haaa ae ESEE aaia ee esia un aidd nket 112 6 2 Block Diagram of Watchdog Timer cece eeeeeeeeeeeeeeeeeeeeeaeeeeeeeaaaeeeeeeeaaeeeeeseaaeeeeeeeeeeeeeeeeaaeeeeeenaas 113 6 3 Watchdog Timer Control Register WDTC cccccccecceeeeeeeeeeeeneeeeaeeeesaeeeeaeeeeseaeesseaeeeseaeeeseaeeeeeaeeetaas 115 6 4 Operation of Watchdog Timer cccececceeeeeeenee eect eeeceeeeecaeeeecaeeeeeaeeeeeaeeeseaaeeseaeeescaeeeseaeeesseeesseeetaas 116 6 5 Notes on Using Watchdog Timer 0 eee eceeeeeeeeeeeeeeeeeeeneeeeeeeeaaeeeeesecaeeeeesenaaeeeeesesaeeeeeeeeeaeeeeeenaas 118 6 6 Program Example for Watchdog Timer oo eeeceecceeeeeeneeeeeeeeneeeeeeeeeaeeeeeeeaeeeeeeeaeeeeeeenaeeeeeeenaaeeeeeeeaas 119 CHAPTER 7 8 BIT PWM TIMER tt teeeteccecceeeeeeeeeeeeeeseeensneneeeeeeeeeeeseeeeeeseeeeeneeesennenes 121 7 1 Overview of 8 Dit PWM Timer ccccceeeceeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeaeee ceases cages egeaeeseeaeeseaeeeseaeesenaeeeseeeess 122 7 2 Block Diagram of 8 bit PWM Timer 0 0 eee ee eceeceeeeeeneeeeeeeenee eee eeeaaeeeeeeeaaeeeeeeeaaaeeeeeseaeeeeeeeeaeeeeeeeaas 124 73 Structur e of 83 bit PWM TimMer idrolisi cnet ataa a a tae tain dee RAN ee iene 126 7 3 1 PWM Control Register CNTR essssseesesssseeseserrrsrirseritsrinttrntstnstrrnstintsrrnsttntstenannnstnnannnsen nannt 128 7 3 2 PWM Compare Register COMR ccceceeeee
221. nstructions MULU A This instruction performs an unsigned multiplication of AL lower eight bits of the accumulator and TL lower eight bits of the temporary accumulator and stores the 16 bit result in A The contents of T temporary accumulator do not change The contents of AH higher eight bits of the accumulator and TH higher eight bits of the temporary accumulator before execution of the instruction are not used for the operation The instruction does not change the flags and therefore care must be taken when a branch may occur depending on the result of a multiplication Figure B 3 3 MULU shows a summary of the instruction Figure B 3 3 MULU Before execution After execution A 567 8H A 1860H T 1234H T 1234H DIVU A This instruction divides the 16 bit value in T by the unsigned 8 bit value in AL and stores the 8 bit result and the 8 bit remainder in AL and TL respectively A value of 0 is set to both AH and TH The contents of AH before execution of the instruction are not used for the operation An unpredictable result is produced from data that results in more than eight bits In addition there is no indication of the result having more than eight bits Therefore if it is likely that data will cause a result of more than eight bits the data must be checked to ensure that the result will not have more than eight bits before it is used The instruction does no
222. nt down counter value is transferred to the PWC reload buffer register RLBR the measurement completion interrupt request flag bit PCR1 IR and buffer full flag bit PCR1 BF are both set to 1 and counter operation is re enabled The function supports continuous pulse width measurement and so can be used like an input capture Figure 8 6 2 Example of H width measurement using pulse width measurement function shows the operation when the measured pulse selection bits PCR2 W1 WO are set to 00g H width measurement 159 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Figure 8 6 2 Example of H width measurement using pulse width measurement function Input waveform to the PWC pin uy Counter value Hi widi Input pulse FFH SEI gt Time EN bit et Counter operation a ene Regen IR bit BF bit Data transferred from down RLBR read counter to RLBR Notes e Ifthe previous RLBR register value has not been read during continuous pulse width measurement the PWC leaves the BF bit set to 1 and maintains the previous measurement value In this case the new measurement value is lost e Do not modify the PCR2 register during pulse width measurement PCR1 EN 1 E Measuring long pulse widths 160 To measure pulse widths longer than 28 times the cycle of the selected count clock it is necessary to count the number of counter underflows Oly
223. nterrupt request set to higher interrupt level level 1 in this example occurs at this time the interrupt processing has priority To temporarily disable multiple interrupts during the timer interrupt the interrupt enable flag in the condition code register is set to interrupts disabled CCR I 0 or the interrupt level bits IL1 ILO set to 00g On execution of the interrupt return instruction RETI at the completion of interrupt processing the CPU restores the program counter PC and program status PS values saved on the stack and resumes execution of the interrupted program Restoring the program status PS returns the condition code register CCR to the value prior to the interrupt 39 CHAPTER 3 CPU 3 4 4 Interrupt Processing Time The total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time the time required to prepare for interrupt processing The maximum time for this process is 30 instruction cycles E Interrupt processing time 40 When an interrupt request occurs the time until the interrupt is accepted and the interrupt processing routine is executed includes the interrupt request sampling time and the interrupt handling time Interrupt request sampling time Whether or not an interrupt request has occurred is determined by sam
224. nues IR Measurement completion interrupt request flag bit For the pulse width measurement function This bit is set to 1 when the pulse width measurement is completed An interrupt request is output when both this bit and the interrupt request enable bit IE are 1 Writing 0 clears this bit Writing 1 has no effect and does not change the bit value For the interval timer function The bit has no meaning BF Buffer full flag bit For the pulse width measurement function This bit is an interrupt request flag and is set to 1 when a measurement value is present in the RLBR register An interrupt request is output when both this bit and the interrupt request enable bit IE are 1 This bit is set to 1 when pulse width measurement completes and cleared to 0 when the measurement value is read from the RLBR register This bit is read only The write value has no meaning and has no effect on the operation For the interval timer function This bit has no meaning 149 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 3 2 PWC Pulse Width Control Register 2 PCR2 The PWC pulse width control register 2 PCR2 is used to select the operating mode pulse width measurement or interval timer operation etc select the count clock set the measured pulse measurement edges and check the timer output state of the pulse width count timer E PWC pulse width control register 2 PCR2 Figure 8
225. o COM3 SEGO to SEG19 LCD drive voltage V1 or Vss P ch pes N ch Common segment control signal e gt Vi to V3 V1 to V3 pin voltages Figure 12 3 2 Block diagram of LCD controller driver pins SEG20 to SEG41 Common segment control signal e LCD drive voltage V3 or V2 gt A LCD drive voltage V1 or Vss Ge Common segment control signal o gt k Mask option PDR Port data register gt ea o Stop mode SPL 1 H Se PDR read j A g i l Port SEG selection signal dt i 1 bel 1 1 af PDR read for bit manipulation instructions m 5 Output latch Neon POO SEG20 to PO7SEG27 P10 SEG28 to P17 SEG35 PDR write P20 SEG36 to P25 SEG41 bees eee eens e Stop mode SPL 1 7 SPL Pin state specification bit in the standby control register STBC 242 CHAPTER 12 LCD CONTROLLER DRIVER Figure 12 3 3 Block diagram of LCD conitroller driver pin P32 V1 and P33 V2 PSEL bit of LCDR register X7 V1 or V2 i PDR Port data register N ch IL Er P ch EEN Foe Stop mode SPL 1 lt E PDR read a i i 1 1 S i i f 1 CHE PDR read for bit manipulation instructions 1 l 1 D Output latch SI a PDR write i wee ee ee ee ee ee ee e
226. ode gt Clock for yy timebase timer Clock supply oscillat Main clock Divide by 4 gt or Clock controller to CPU gt m 214 FcH gt From timebase timer 218 FcH gt Oscillation stabiliza tion delay time A selector optional Stop of supply to the CPU FcH Main clock oscillation frequency tinst Instruction cycle divide by four main c Mask option lock oscillation 1 tinst Main clock oscillator The main clock oscillator is stopped in main stop mode 53 CHAPTER 3 CPU Clock controller This circuit controls the supply of operating clocks to the CPU and peripheral circuits selecting the clock based on the active mode normal RUN or standby sleep stop mode Supply of the clock to the CPU is stopped until the clock supply stop signal in the oscillation stabilization delay time selector is released Oscillation stabilization delay time selector This selector selects a delay time between two main clock oscillation stabilization times timed by the timebase timer as the duration of CPU clock stop signal STEC register This register controls from normal operation RUN to the standby mode sets the pin states in the stop mode and initiates software reset E Instruction cycle tinst Instruction cycle minimum execution time is 1 4 of the main clock 54
227. og timer control register WDT_CLR EQU 00000101B VECT DSEG ABS DATA SEGMENT ORG OFFFEH RST_V DW PROG Set reset vector VECT ENDS Main program CSEG CODE SEGMENT PROG Initialization routine after a reset MOVW SP 0280H Set initial value of stack pointer for interrupt processing Initialization of peripheral functions interrupts etc INIT MOV WDTC WDT_CLR Activate the watchdog timer MAIN MOV WDTC WDT_CLR Clear the watchdog timer User processing interrupt processing may occur during this cycle JMP MAIN The loop must be executed in less than the minimum interval time of the watchdog timer 119 CHAPTER 6 WATCHDOG TIMER 120 CHAPTER 7 8 BIT PWM TIMER This chapter describes the functions and operation of the 8 bit PWM timer 7 1 Overview of 8 bit PWM Timer 7 2 Block Diagram of 8 bit PWM Timer 7 3 Structure of 8 bit PWM Timer 7 4 8 bit PWM Timer Interrupts 7 5 Operation of Interval Timer Function 7 6 Operation of PWM Timer Function 7 7 States in Each Mode during 8 bit PWM Timer Operation 7 8 Notes on Using 8 bit PWM Timer 7 9 Program Example for 8 bit PWM Timer 121 CHAPTER 7 8 BIT PWM TIMER 7 1 Overview of 8 bit PWM Timer The 8 bit PWM timer can be selected to function as either an interval timer or PWM timer with 8 bit resolution The interval timer function counts up
228. om oc e SSES Cl 1 0o 1 1 E a S a A a A a Ar E a A T E a TTT Soo oo o oo oo oO o o lloll 1 1 OQ i be sl al TE S ll 2 La e o G EES a e 7 a EI Ol El S 1 1 1 1 Oo e f O e a H a ie a ae NES a ee ee D 4 0 sel a4 4 ei l III zl zl 4 1 253 CHAPTER 12 LCD CONTROLLER DRIVER 12 4 2 Output Waveforms during LCD Controller Driver Operation 1 3 Duty Ratio In the 1 3 duty ratio mode the COMO COM1 and COM2 outputs are used by the display COND is not used E 1 3 bias 1 3 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment LCD cell is turned on Figure 12 4 4 Output waveforms 1 3 bias and 1 3 duty ratio example shows the output waveforms for the display RAM contents listed in Table 12 4 2 Display RAM contents example Table 12 4 2 Display RAM contents example Segment Display RAM contents COM2 COM1 Not used 254 CHAPTER 12 LCD CONTROLLER DRIVER Figure 12 4 4 Output waveforms 1 3 bias and 1 3 duty ratio example COMO COM1 COM2 COM3 SEGn SEGn 1 Difference in potential between COMO and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM2 and SEGn Difference in pot
229. on of the reset The CPU starts executing instructions from the address contained in the reset vector E Oscillation stabilization delay reset state On products with power on reset the reset operation for a power on reset or external reset in stop main clock mode starts after the main clock oscillation stabilization delay time selected by the stabilization delay time option If the CPU has not woken up from the external reset input when the delay time completes the reset operation does not start until the CPU wakes up from external reset As the oscillation stabilization delay time is also required when an external clock is used a reset requires that the external clock is input The main clock oscillation stabilization delay time is timed by the timebase timer On products without power on reset the oscillation stabilization delay reset state is not used Therefore for such products hold the external reset pin RST at the L level to disable the CPU operation until the source oscillation stabilizes E Effect of reset on RAM contents The contents of RAM are unchanged before and after a reset other than power on reset If an external reset is input close to a write timing however the contents of the write address cannot be assured For this reason all RAM locations being used should be initialized following reset 47 CHAPTER 3 CPU 3 5 3 Pin States during Reset Reset initializes the pin states E Pin states during reset W
230. or 1 as the output latch but when it is an input port it cannot be read the output latch state Reference For SETB and CLRB bit operation instructions since the state of output latch not the pin is read the output latch states of bits other than those being operated on are not changed Settings as an LCD segment driver output To use pins as LCD segment driver outputs segment driver output must be selected by the mask option Furthermore the segment driver output select register must be set to the same as the mask option so that the CMOS input port can be protected Table 4 3 3 Port 1 data register function lists the functions of the port data register Table 4 3 3 Port 1 data register function Register Address Initial value Outputs an L level to the pin Sets 0 to the output latch and turn the output transistor ON Pin state is the L level Port 1 data register PDR1 Sets the pin to the high Pin state is the impedance state H level Sets 1 to the output latch and turn the output transistor OFF 11111111 R W Readable and writable 79 CHAPTER 4 I O PORTS 4 3 2 Operation of Port 1 This section describes the operations of the port 1 E Operation of port 1 Operation as an output port e When the output latch value is 0 the output transistor turns ON and an L level is output from the pin When the output latch value is 1 the
231. or a 5 MHz main clock oscillation frequency The count clock is 32 ting tins Instruction cycle RLBR register value 3 ms 32 x 4 5 MHz 117 2 075 165 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Coding example PCR1 EQU 0014H Address of the PWC pulse width control register 1 PCR2 EQU 0015H Address of the PWC pulse width control register 2 RLBR EQU 0016H Address of the PWC reload buffer register EN EQU PCR1 7 Define the counter operation enable bit IE EQU PCR1 5 Define the interrupt request enable bit UF EQU PCR1 2 Define the underflow 01H 00H interrupt request flag bit BF EQU PCR1 0 Define the buffer full flag ILR1 EQU 007CH Address of the interrupt level setting register 1 INT_V DSEG ABS DATA SEGMENT ORG OFFF4H IRQ3 DW WARI Set interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB EN Stop counter operation CLRB IE Disable interrupt request output CLRB BF Clear buffer full flag PCR1 bit 0 MOV ILR1 10111111B Set interrupt level level 2 MOV RLBR 075H Counter reload value interval time MOV PCR2 00001000B Select interval timer function reload timer mode initial output value of the TO bit and 32 tinst MOV PCR1 11100000B Start counter op
232. ormal operation Pin name sleep mode Stop mode SPL 1 stop mode SPL 0 General purpose I O ports segment P20 SEG36 to P25 SEG41 driver output SPL Pin state specification bit in the standby control register STBC Hi Z High impedance 85 CHAPTER 4 I O PORTS 4 5 Port 3 Port 3 is N ch open drain I O port Two of them also serve as LCD bias input Port 3 pins can be switched between LCD bias input and port operation This section principally describes the port functions when operating as N ch open drain I O port The section describes the port structure and pins the pin block diagram and the port register for port 3 E Structure of port 3 Port 3 consists of the following two components e N ch open drain I O pins LCD bias input pins P30 to P33 V2 e Port 3 data register PDR3 E Port 3 pins Port 3 consists of four N ch open drain I O When pins are used by the peripheral they cannot be used as N ch open drain I O Table 4 5 1 Port 3 pins lists the port 3 pins Table 4 5 1 Port 3 pins VO type Circuit type Pin name Function Shared peripheral Output P30 N ch open drain I O N ch open drain P31 N ch open drain I O P32 N ch open drain I O V1 LCD bias input LCD bias CMOS N ch open drain P33 N ch open drain I O V2 LCD bias input See Section 1 7 I O Pins and Pin Functions for a description of the circuit type 86 CHAPTER 4 I O PORTS
233. perations of the port 2 E Operation of port 2 Operation as an output port e Writing data to the PDR2 register stores the data in the output latch When the output latch value is 0 the output transistor turns ON and an L level is output from the pin When the output latch value is 1 the transistor turns OFF and high impedance Hi Z is output from the pin e Reading the PDR2 register returns the output latch value Operation as an input port e Writing 0 to the PDR2 register set the port as an input port the output transistor is OFF and the pin goes to the high impedance state e Reading the PDR2 register returns the pin value Operation as an LCD segment driver output e When the LCD output mask option is selected set the PDR2 register bits corresponding to the LCD segment driver output pins to 1 to turn the output transistor OFF e You cannot read the LCD output data by reading PDR2 Operation at reset e Resetting the CPU initializes the PDR2 register values to 1 This turns OFF the output transistor for all pins and all pins are in high impedance Hi Z state Operation in stop mode e The output transistors are forcibly turned OFF and the pins go to the high impedance state if the pin state specification bit in the standby control register STBC SPL is 1 when the device goes to stop mode Table 4 4 4 Port 2 pin state lists the port 2 pin states Table 4 4 4 Port 2 pin state N
234. ple for LCD Controller Driver ceccceceseceeeeeeeeeneeeeeeeeeseeeeeeeeeeeseaeeseceeeeeeaeeesseeeseaees 260 REENEN ee 263 APPENDIX A LG Mep ee eege ENEE 264 APPENDIX B Overview of Instructions 0 eccceeeeeeeeeeeeeeneeeeeeeeeeeeeeeeeeaeeeceaeeeesaeeecaaeeesaeesecaeeeseaeeesecaeeseeaees 266 B 1 Overview of ECKE IESSE Ee 267 Bi2 sAdOreSSING EE 269 DC Special INStrUctions syssanta a aet ee EENS Eed datka 274 BA Bit Manipulation Instructions SETB CLRB cccccceeeeeeeeeneeeeeeeeeeeeeeeeeeeeeeeeeteeeeeeeeeseaeeeseaeeess 278 B 5 MC BIL IEN eerie tte a nc re 279 GR ER et Hu WEE 286 APPENDIX C Mask Options 209 vet dE ENEE de esi aa enee enter seu ceadesvereecucetvasgiasevlineevedeviveusd eueteeedicehe 287 APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller s 0 289 D 1 Programming Specifications for One time PROM and EPROM Microcontrollers seese 290 D 2 Programming Yield and EraSure eeleren niea NEEE AER ERREA EE EA ERN EEEN 293 D 3 Programming to the EPROM with Piggyback Evaluation Device ssesseeseeeereeesrrerrreerreerereesee 294 APPENDIX E MB89950 950A Series Pin States 0 c eecccececeee eens eeeneeeeeeeeeeeaeeeeeaeeeseeeeseaaeesecaeeseaeeeteeeeens 295 UNENEE Ee Ee 297 CHAPTER 1 OVERVIEW This chapter describes the main features and basic specifications of the MB89950 950A series 1 1 MB89950 950A Series Features 1 2 MB89950 950A Series Product Range
235. pling and testing for interrupt requests during the final cycle of each instruction Therefore the CPU is unable to identify interrupt requests during execution of an instruction The longest delay occurs when an interrupt request is generated immediately after starting execution of a DIVU instruction which has the longest instruction cycles 21 instruction cycles Interrupt handling time Nine instruction cycles are required to perform the following preparation for interrupt processing after the CPU accepts an interrupt request e Save the program counter PC and program status PS e Set the top address of the interrupt processing routine the interrupt vector in the PC e Update the interrupt level bits PS CCR IL1 ILO in the program status PS Figure 3 4 4 Interrupt processing time shows the interrupt processing time Figure 3 4 4 Interrupt processing time CPU operation fg Be onn lt gt Final cycle of instruction Interrupt requests are sampled at this timing l Execution of a standard instruction Interrupt handling Interrupt processing routine ae Interrupt request Interrupt handling time Interrupt waiting time sampling time 9 instruction cycles l Interrupt request occurs The total interrupt processing time of 21 9 30 instruction cycles is required if an interrupt request occurs immediately after starting execution of a DIVU instruction which has the longest instruction cycles
236. pose register addressing E Structure of register bank pointer RP Figure 3 2 4 Structure of register bank pointer shows the structure of the register bank pointer Figure 3 2 4 Structure of register bank pointer RP CCR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bits Bit7 Bit6 BitS Bit4 Bits Bit2 Biti BitO RP initial value PS R4 R3 R2 R1 RO H l IL1 ILO N Z V C XXXXXXXXs X Indeterminate Unused The register bank pointer indicates the address of the register bank currently in use Figure 3 2 5 Rule for conversion of actual addresses of general purpose register area shows the relationship between the pointer contents and the actual address is based on the conversion rule Figure 3 2 5 Rule for conversion of actual addresses of general purpose register area Upper bits of HP Lower operation codes o o mn mm o o wm 4 R4 R3 R2 RI RO b2 bi bO Cokie EE EE Generated addresses A15 A14 A13 A12 A10 A11 AQ A8 A7 A6 A5 A4 AB A2 A1 AOD The register bank pointer points to the memory block register bank in the RAM area that is used for general purpose registers A total of 32 register banks are available A register bank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bank pointer Each register bank contains eight 8 bit general purpose regis
237. priority followed by level 2 Setting level 3 disables the interrupt for that peripheral function Execute the main program for multiple interrupts execute the interrupt processing routine The interrupt request flag bit request FF for a peripheral function is set to 1 when the peripheral function generates an interrupt source If the interrupt request enable bit for the peripheral function is set to enable enable FF 1 the peripheral function outputs the interrupt request to the interrupt controller The interrupt controller continuously monitors for interrupt requests from the peripheral functions and passes the interrupt level of the current interrupt request with the highest interrupt level to the CPU The interrupt controller also evaluates the priority order if requests with the same level are present simultaneously If the interrupt level received by the CPU has a higher priority a lower level value than the level set in the interrupt level bits in the condition code register CCR IL1 ILO the CPU checks the interrupt enable flag CCR I and receives the interrupt if interrupts are enabled CCR I 1 The CPU saves the contents of the program counter PC and program status PS on the stack reads the top address of the interrupt processing routine from the interrupt vector table for the interrupt updates the interrupt level bits in the condition code register CCR IL1 ILO with the received inte
238. put pin a serial parallel conversion process is initiated in the internal receive shift register After the data is normally stop bit is detected the receive data is transferred from the internal shift register to the SIDR register and the RDRF bit is set to 1 If an overrun or a framing error occurs the receive data is not stored to the SIDR and the ORFE bit is set to 1 1 S The RDRF and ORFE bits are set when the last stop bit is detected after the completion of the receive operation If the receive interrupt is enabled SSD RIE 1 an interrupt request IRQ 4 is issued to the CPU If the RDRF bit is set the receive data has already been stored to the SIDR register Figure 10 7 3 Receive operation in mode 0 1 3 Figure 10 7 4 Operation at overrun error in mode 0 1 3 and Figure 10 7 5 Operation at framing error in mode 0 1 3 show receive operations non parity and 1 stop bit CHAPTER 10 UART Figure 10 7 3 Receive operation in mode 0 1 3 Data START O 1 2 3 4 5 6 7 8 iSTOR RDRF Receive interrupt Figure 10 7 4 Operation at overrun error in mode 0 1 3 Data STAT 0 1 2 3 4 5 6 7 8 STOP RDRF 1 Receive buffer full ORFE Receive interrupt Figure 10 7 5 Operation at framing error in mode 0 1 3 Data START 0 1 2 3 4 5 6 7 8 STP RDRF 0 a Soe ee ee ee es A ORFE Receive interrupt Reference When the s
239. quests are not generated for the PWM timer function 8 bit PWM timer generates the IRQ2 as an interrupt request E Interrupts for interval timer function The counter starts to count up from 00y on the selected count clock When the counter value matches the PWM compare register COMR value the interrupt request flag bit CNTR TIR is set to 1 At this time an interrupt request IRQ2 to the CPU is generated if the interrupt request enable bit is enabled CNTR TIE 1 Write 0 to the TIR bit in the interrupt processing routine to clear the interrupt request The TIR bit is set to 1 when the counter value matches the set value regardless of the value of the TIE bit Reference The TIR bit is not set if the counter is stopped CNTR TPE 0 at the same time as the counter value matches the COMR register value An interrupt request is generated immediately if the TIR bit is 1 when the TIE bit is changed from disabled to enabled 0 gt 1 E Registers and vector tables for 8 bit PWM timer interrupts Table 7 4 1 Registers and vector tables for 8 bit PWM timer interrupts Interrupt level setting register Vector table address Interrupt Register Setting bits Upper Lower 8 bit PWM timer IRQ2 ILR1 007Cyq L21 Bit 5 L20 Bit 4 FFF64 FFF7y See Section 3 4 2 Interrupt Processing for details on the interrupt operation 131 CHAPTER 7 8 BIT PWM TIMER 7 5 Operation of Interval Ti
240. r control register WDTC Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0009H WTE3 WTE2 WTE1 WTEO XXXX W W W W gt WTES3 WTE2 WTE1 WTEO Watchdog timer control bits e Activate the watchdog timer when writing for the first time 0 1 0 1 after a reset f e Clear the watchdog timer when writing for the second and subsequent times after a reset Other than the above No operation W Write only Unused X Indeterminate Note As the bit 3 0 are write only the bit manipulation instructions for these bits cannot be used Table 6 3 1 Watchdog timer control register WDTC bits Function Unused bits e The read value is indeterminate Writing to these bits has no effect on operation WTE3 WTEO Writing 0101 to these bits activates when writing for the first time after a reset or Watchdog timer clears when writing for the second and subsequent times after a reset the watchdog control bits timer e Writing a value other than 0101 has no effect on the operation Note The read value is always 1111 The bit manipulation instructions cannot be used 115 CHAPTER 6 WATCHDOG TIMER 6 4 Operation of Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows E Operation of watchdog timer 116
241. r for port 0 Structure of port 0 Port 0 consists of the following two components e N ch open drain I O pins LCD segment driver output pins PO0 SEG20 to P07 SEG27 e Port 0 data register PDRO E Port 0 pins Port 0 consists of eight N ch open drain I O When pins are used by the peripheral they cannot be used as N ch open drain I O Table 4 2 1 Port 0 pins lists the port 0 pins Table 4 2 1 Port 0 pins EOS Circuit type Pin name Function Shared peripheral Output PO0 SEG20 POO N ch open drain I O SEG20 LCD segment driver output PO1 SEG21 PO1 N ch open drain I O SEG21 LCD segment driver output P02 SEG22 P02 N ch open drain I O SEG22 LCD segment driver output P03 SEG23 P03 N ch open drain I O SEG23 LCD segment driver output Segment N ch P04 SEG24 P04 N ch open drain I O SEG24 LCD segment driver output open drain PO5 SEG25 P05 N ch open drain I O SEG25 LCD segment driver output P06 SEG26 P06 N ch open drain I O SEG26 LCD segment driver output PO7 SEG27 P07 N ch open drain I O SEG27 LCD segment driver output See Section 1 7 I O Pins and Pin Functions for a description of the circuit type 72 E Block diagram of port 0 pins Figure 4 2 1 Block diagram of port 0 pins CHAPTER 4 I O PORTS Mask option OO LCD segment driver output PDR Port data register Segment driver output select register
242. r leaves the upper 8 bits of the temporary accumulator TH unchanged The content of the temporary accumulator after a reset is indeterminate Index register IX The index register is a 16 bit register used to hold the index address The index register is used in conjunction with a single byte offset value 128 to 127 Adding the sign extended offset value to the index address generates the memory address for data access The content of the index register after a reset is indeterminate Extra pointer EP The extra pointer is a 16 bit register used to hold a memory address for data access The content of the extra pointer after a reset is indeterminate Stack pointer SP The stack pointer is a 16 bit register used to hold the address referenced during operations such as interrupts subroutine calls and the stack save and restore instructions The value of the stack pointer during program execution is the address of the most recently saved data on the stack The content of the stack pointer after a reset is indeterminate Program status PS The program status is a 16 bit control register The upper 8 bits contain the register bank pointer RP which points to the address of the current general purpose register bank The lower 8 bits contain the condition code register CCR which contains flags indicating the current CPU status The two 8 bit registers which form the program status cannot be accessed independently the progr
243. r programmed contents it is necessary to expose the internal EPROM to an ultraviolet light source A dosage of 10 W seconds cm is required to completely erase an internal EPROM This dosage can be obtained by exposure to an ultraviolet lamp wavelength of 2537 Angstroms A with intensity of 12000 uW cm2 for 15 to 21 minutes The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure It is important to note that the internal EPROM and similar devices will erase with light sources having wavelengths shorter than 4000 A Although erasure time will be much longer than with UV source at 2537 A nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM and exposure to them should be prevented to realize maximum system reliability If used in such an environment the package windows should be covered by an opaque label or substance 293 APPENDIX D 3 Programming to the EPROM with Piggyback Evaluation Device This section describes the programming to the EPROM with piggyback evaluation device E EPROM for use MBM27C256A 20TV E Programming socket adaptor To program to the PROM using an EPROM programmer use the socket adaptor manufacturer Sun Hayato Co Ltd listed below Table D 3 1 Programming socket adaptor Package Adaptor socket part number LCC 32 Rectangle ROM 32LC 28DP YG Inquiries Su
244. r the external interrupt circuit E Program example for the external interrupt circuit Processing description e Generates interrupts on detecting a rising edge on pulses input to the INT pin Coding example EIC1 EQU 0030H External interrupt control register 1 EIR1 EQU EIC1 7 Defines the external interrupt request flag bit SL10 EQU EIC1 5 Defines the edge polarity selection bit EIE1 EQU EIC1 4 Defines the interrupt request enable bit ILR1 EQU 007CH Set interrupt level setting register 1 INT_V DSEG ABS DATA SEGMENT ORG OFFF8H IRQ1 DW WARI Set INT1 interrupt vector INT_V ENDS EES Main program s sessS a Se Se CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB EIR1 Clear interrupt request flag MOV ILR1 11110111B Set interrupt level level 1 SETB SL10 Select rising edge SETB EIE1 Enable output of interrupt requests SETI Enable interrupts Gees Interrupt processing Coutine WARI CLRB EIEL Clear INT1 interrupt request flag PUSHW A XCHW A T p USHW A User processing POPW A XCHW A T POPW A RETI ENDS END 232 CHAPTER 12 LCD CONTROLLER DRIVER This chapter describes the functions and operation of the LCD controller driver 12 1 Overview of LCD Controller Driver 12 2 Block Diagram of LCD Controller Driver 12 3 Structure of LCD Control
245. river pins The LCD controller driver uses 4 common output pins COMO to COM3 42 segment output pin SEGO to SEG41 and 3 LCD driving power supply pins V1 to V3 COMO COM1 COM2 and COM pins COMO to COM3 can function LCD common output pins COMO to COM3 SEGO to SEG19 P00 SEG20 to P07 SEG27 P10 SEG28 to P17 SEG35 and P20 SEG36 to P25 SEG41 PO0 SEG20 to P07 SEG27 P10 SEG28 to P17 SEG35 and P20 SEG36 to P25 SEG41 pins can function either as N ch open drain I O ports POO to P07 P10 to P17 and P20 to P25 and LCD segment output pins SEG20 to SEG41 The selection however is made as a mask option Note When these pins are used as LCD segment outputs the corresponding port data registers PDRO PDR1 and PDR2 should be set to all 1 to turn the output transistors OFF P32 V1 P33 V2 and V3 V1 V2 and V3 pins are the LCD driving power supply pins The P32 V1 and P33 V2 can function either as N ch open drain I O ports P32 and P33 and LCD driving power supply pins V1 and V2 The selection however is made by setting LCDR PSEL bit 241 CHAPTER 12 LCD CONTROLLER DRIVER E Block diagrams of LCD controller driver pins Figure 12 3 1 Block diagram of LCD controller driver pins dedicated common segment output pins COMO to COM3 and SEGO to SEG19 Dedicated common segment output pins Common segment control signal e LCD drive voltage V3 or V2 a Pin Ee COMO t
246. rrupt level and starts execution of the interrupt processing routine Finally on execution of the RETI instruction the CPU restores the program counter PC and program status PS values saved on the stack and resumes execution from the instruction following the last instruction executed before the interrupt Note As the interrupt request flag bit of a peripheral function is not cleared automatically when an interrupt request is received the bit must be cleared by the program normally by writing 0 to the interrupt request flag bit at interrupt processing routine An interrupt wakes up the CPU from standby mode low power consumption See Section 3 7 Standby Modes Low power Consumption for details Reference 38 If the interrupt request flag bit is cleared at the top of the interrupt processing routine the peripheral function that has generated the interrupt becomes able to generate another interrupt during execution of the interrupt processing routine resetting the interrupt request flag bit However the interrupts are not normally accepted until the current processing routine completes CHAPTER 3 CPU 3 4 3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register for two or more interrupt requests from peripheral functions E Multiple interrupts If the interrupt request having the higher interrupt levels occurs during the
247. rrupt output Overflow interrupt request flag bit gt TBIF Read Write 0 No ET E specified Clears this bit 1 Overflow on specified bit ES Tne Dit does not change R W Readable and writable W Write only Unused Initial value 104 CHAPTER 5 TIMEBASE TIMER Table 5 3 1 Timebase timer control register TBTC bits Function Unused bits The read value is indeterminate Writing to these bits has no effect on the operation TBIF This bit is set to 1 when counter overflow occurs on the specified bit of the timebase Overflow interrupt timer counter request flag bit An interrupt request is generated when both this bit and the interrupt request enable bit TBIE are 1 Writing 0 clears this bit Writing 1 has no effect and does not change the bit value TBIE This bit enables or disables an interrupt request output to the CPU An interrupt request Interrupt request is output when both this bit and the overflow interrupt request flag bit TBOF are 1 TBR This bit clears the timebase timer counter Timebase timer Writing 0 to this bit clears the counter to 000004 Writing 1 has no effect and initialization bit does not change the bit value Note The read value is always 1 TBC1 TBCO The read value is indeterminate Interval time These bits select the cycle of the interval timer selection bits These bits select which bit of the timebase timer counter to use as the interva
248. ruction esessesseeeeeeeeeseeerrrnrnnnneee 281 arithmetic operation result bits cceeeeeees 29 B bi directional serial I O performing sesseesseeen 189 bit manipulation instruction read operation upon gt 1610110 Of 278 branch instruction sessssseeeesessseerernrrrrnrenserrrrens 284 Cc clock controller block diagram of 53 clock generator 51 clock Supply function sesesseseseeeeeeesesessserrrnnneen 101 clock supply function operation of 107 CIOCK supply map 49 condition code register CCR structure of 29 D dedicated register configuration eeeeeeeeee 27 dedicated register functions ceeeeeeeeeeees 27 differences among Products A 6 display brightness adjustment when internal voltage divider iS USCC sensen ara ienie 238 298 display RAM and output pin ssec 248 E effect of reset on RAM content 47 EPROM for use 294 EPROM microcomputer note on using and data erasure LON Nests a detveti a ieee Se NEEN 293 EPROM mode memory map In 290 EPROM programmer socket adaptot 00 290 EPROM programming Io 291 294 external interrupt circuit interrupt source 227 external interrupt circuit interrupt register and vector table e 230 external interrupt circuit Dim 226 external interrupt circuit pin block diagram of 226 external interrupt circuit redisler ee 227 external interrupt circuit block diagram of
249. s External shift clock input 2 tinst OF More 1 2 tinct or less DC to 625 kbps Foy main clock oscillation frequency tinst Instruction cycle 1 instruction cycle 4 Foy 170 CHAPTER 9 8 BIT SERIAL UO 9 2 Block Diagram of 8 bit Serial UO Each channel of the 8 bit serial I O consists of the following four blocks e Shift clock controller e Shift clock counter e Serial data register SDR e Serial mode register SMR E Block diagram of 8 bit serial I O Figure 9 2 1 Block diagram of 8 bit serial I O Internal data bus DO to D7 Transfer diene Sp to DO MSB first soleno LSB first D7 to DO P43 S Shift direction Pin r gt St Serial data register SDR SST BDS P44 SO Output buffer CKSO Pin CKS1 Output enable SOE Output enable SCKE Shift clock selection 2 I SIOE 2tinst SIOF Btinst Serial mode register 32tinst SMR Shift clock controller e E T P45 SCK 2 Pin ai IRQ5 LN Output buffer Clear gt Shift clock counter tinst Instruction cycle Note The SO and SCK output serve as UART outputs They can be used as the outputs of the serial I O when the RESL bit of SMC2 in the UART is 1 171 CHAPTER 9 8 BIT SERIAL I O Shift clock control circui
250. s for a description of the circuit type 77 CHAPTER 4 I O PORTS E Block diagram of port 1 pins Figure 4 3 1 Block diagram of port 1 pins Mask option LCD segment driver output OO Segment driver output select register PDR Port data register lt 5 Stop mode SPL 1 PDR read i LA ON PDR read for bit manipulation instructions Output latch Internal data bus PDR write Stop mode SPL 1 gt 4 N ch SPL Pin state specification bit in the standby control register STBC E Port 1 register The port 1 register consists of PDR1 Each bit in the register has a one to one relationship with a port pin Table 4 3 2 Correspondence between pin and register for port 1 shows the correspondence between the pins and register for port 1 Table 4 3 2 Correspondence between pin and register for port 1 Correspondence between register bit and pin PDRI1 Bit7 Bit6 BitS Bit4 Bit3 Bit2 Bitl Bit 0 Port 1 Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 78 CHAPTER 4 I O PORTS 4 3 1 Port 1 Data Register PDR1 This section describes the port 1 data register E Port 1 data register functions Port 1 data register PDR1 The PDR1 register holds the pin states Therefore a bit corresponding to a pin set as an output port can be read as the same state 0
251. s as the SO pin when serial data output is enabled SOE 1 regardless of the state of the general purpose I O port P44 CKS1 CKSO Shift clock selection bits These bits select the shift clock from one external and three internal shift clocks Setting these bits to other than 11 selects an internal shift clock In this case the shift clock is output from the SCK pin if the shift clock output enable bit SCKE is 1 Setting these bits to 11 selects the external shift clock This inputs the shift clock from the SCK pin if shift clock input is enabled SCKE 0 and DDR4 bit 5 0 BDS Transfer direction selection bit This bit selects whether serial data is transferred with the least significant bit first LSB first BDS 0 or the most significant bit first MSB first BDS 1 Note e As bits are set in the appropriate order when writing to or reading from the serial data register SDR modifying this bit does not apply to any data already set in the SDR register 177 CHAPTER 9 8 BIT SERIAL I O Table 9 3 1 Serial mode register SMR bits Function SST This bit controls serial I O transfer start and transfer enable This bit can also be used to determine Serial I O transfer whether transfer has completed start bit Writing 1 to this bit when an internal shift clock is selected CKS1 CKSO other than 11 clears the shift clock counter and starts data transfer Writing 1 to t
252. s pin functions as serial data output pin of the UART irrespective of settings on corresponding port direction register P43 SI This pin functions either as general purpose input output port P43 or serial data input pin of the UART SD To use the port as a UART serial data input pin configure the port as output port by setting a corresponding bit of the port data direction register DDR4 bit 3 0 E Block diagram of UART pins Figure 10 3 1 Block diagram of UART pins CHAPTER 10 UART For P45 SCK and P43 SI To peripheral input cl PDR Port data register PDR read When Read modify write instruction executed output enable Output latch Internal data bus DDR Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC ao n St bp Stop mode SPL 1 O N PDR read e UART output 1 UART Pull up resistor Approx 50 kQ Mask option For P45 SCK and l P44 SO E ra SE l P ch pe de Pin P45 SCK SR P44 SO P43 SI 7 7 Reference Pins with a pull up resistor go to the H level pull up state rather than to the high impedance state when the output transistor is turned OFF 203 CHAPTER 10 UART 10 4 UART Registers This section describes the registers of the UART E
253. s than 0 1 V ms at the time of a momentary fluctuation such as when power is switched Precaution when using an external clock Even when an external clock is used oscillation stabilization time is required for power on reset option selection and release from stop mode CHAPTER 2 HANDLING DEVICES Recommended screening conditions The OTPROM product should be screened by high temperature aging before mounting Verify program Y High temperature aging 150 C 48Hrs Y Read The programming test cannot be performed for all bits of the preprogrammed OTPROM product due to its characteristics Consequently 100 programming yielding cannot be ensured Treatment of N C pins Be sure to leave internally connected N C pins open Unused LCD controller driver dedicated pins When LCD controller driver dedicated pins are not in use keep it open Port shared with SEG pin When using port shared with SEG pin be sure that the input voltage to port does not exceed the voltage of V3 SEG driving voltage When power on or reset SEG pin will output an initial value of L LCD controller driver not in use When LCD controller driver is not in use connect the V3 pin to Vcc and keep other LCD controller driver dedicated pins open CHAPTER 2 HANDLING DEVICES 20 CHAPTER 3 CPU This chapter describes the functions and operation of the CPU 3 1 Memory Space 3 2 Dedicated Re
254. s used to access the entire 64 KB area In this addressing mode the address is the value resulting from sign extending the contents of the first operand and adding them to IX index register Figure B 2 4 Example of index addressing shows an example Figure B 2 4 Example of index addressing MOVW A IX 5 Au IX 2 7 A5u gt 27 F Fux 1 u 28 00H 3 4H gt A 12 34n L Pointer addressing Pointer addressing is indicated by EP in the instruction list This addressing is used to access the entire 64 KB area In this addressing mode the address is contained in EP extra pointer Figure B 2 5 Example of pointer addressing shows an example Figure B 2 5 Example of pointer addressing MOVW A EP EP 27 A5 gt 27 Adu 1 2h 27 A6H 3 4H A 12 34n 270 APPENDIX B Overview of Instructions General purpose register addressing General purpose register addressing is indicated by Ri in the instruction list This addressing is used to access a register bank in the general purpose register area In this addressing mode the higher byte of the address is always 01 and the lower byte is specified based on the contents of RP register bank pointer and the lower three bits of the operation code Figure B 2 6 Example of general purpose register addressing shows an example Figure B 2 6 Example of general p
255. scribes the functions and operation of the CPU CHAPTER 4 I O PORTS This chapter describes the functions and operation of the I O ports CHAPTER 5 TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer CHAPTER 7 8 BIT PWM TIMER This chapter describes the functions and operation of the 8 bit PWM timer CHAPTER 8 PULSE WIDTH COUNT TIMER PWC This chapter describes the functions and operation of the pulse width count timer PWC CHAPTER 9 8 BIT SERIAL I O This chapter describes the functions and operation of the 8 bit serial I O CHAPTER 10 UART This chapter describes the functions and operation of the UART CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT EDGE This chapter describes the functions and operation of the external interrupt circuit CHAPTER 12 LCD CONTROLLER DRIVER This chapter describes the functions and operation of the LCD controller driver APPENDIX This appendix includes I O maps instruction lists and other information The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to a
256. serial input operation For MSB first Bit7 Die BitS Bit4 Bit3 Bit2 Biti Bito SI pin SDR 7 6 5 4 3 2 1 0 LI Serial input data EE em nm XXH E Shift clock Ld Ld T Po T l Cleared by the program 0 1 2 3 4 5 6 7 SIOF bit Interrupt request SST bit Automatically cleared when transfer completes E Operation at completion of serial input The 8 bit serial I O sets the interrupt request flag bit SMR SIOF 1 and clears the serial I O transfer start bit SMR SST 0 on the rising edge of the shift clock after the serial data of the eighth bit is input 184 CHAPTER 9 8 BIT SERIAL UO 9 7 States in Each Mode during 8 bit Serial I O Operation This section describes the operation of the 8 bit serial UO when the device goes to sleep or stop mode or an operation halt request occurs during transfer E Using internal shift clock Operation in sleep mode In sleep mode serial I O operation does not halt and transfer continues as shown in Figure 9 7 1 Operation in sleep mode internal shift clock Figure 9 7 1 Operation in sleep mode internal shift clock ook opt Be Be Bee Be Be e See D emm SST bit a Cleared by the program SIOF bit T Interrupt request SO pin output 2018 eege 1 Sleep mode SLP bit STBC register Wake up from sleep mode by IRQS Operation in stop mode
257. set the count clock control interrupts and check the PWM status Setting the operation to PWM timer mode P T 0 disables clearing of the 8 bit counter and generation of interrupt requests IRQ2 when the comparator circuit detects a match 125 CHAPTER 7 8 BIT PWM TIMER 7 3 Structure of 8 bit PWM Timer This section describes the pin pin block diagram register source and interrupts of the 8 bit PWM timer E 8 bit PWM timer pin The 8 bit PWM timer uses the P41 PWM pin This pin can function as a CMOS general purpose I O port P41 or as the interval timer or PWM timer output PWM PWM When the interval timer function is selected the square waves are output to this pin When the PWM timer function is selected the pin outputs the PWM wave Setting the output pin control bit CNTR OE to 1 makes pin P41 PWM the output only pin for 8 bit PWM timer Once this has been done the pin performs its PWM function regardless of the state of the port data register output latch data PDR4 bit 1 E Block diagram of 8 bit PWM timer pin Figure 7 3 1 Block diagram of 8 bit PWM timer pin PDR Port data register D Stop mode SPL 1 Approx Sno R w Mask option PDR read i oe eae ee a PWM output S iy PWM i S PDR read de output enable tej P ch When Read modify write instruction
258. ssume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss Oe nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described i
259. st PWM wave cycle S 5 2tinst io 2 tinst Si tinst to SE tinst Se tinst to SC tinst tinst Instruction cycle Figure 7 1 1 Example D A converter configuration using PWM output and low pass filter PWMioutput Analog output Va PWM pin AM R Z C Analog output waveform TIT AT The relationship between the analog output voltage and PWM output waveform is Va Vcc TH T Vcc Tr is the time taken for the output to stabilize Tr i t PWM output waveform TL Reference Interrupt requests are not generated during operation of the PWM function 123 CHAPTER 7 8 BIT PWM TIMER 7 2 Block Diagram of 8 bit PWM Timer The 8 bit PWM timer consists of the following six blocks Count clock selector 8 bit counter Comparator circuit PWM generator and output controller PWM compare register COMR PWM control register CNTR E Block diagram of 8 bit PWM timer Figure 7 2 1 Block diagram of 8 bit PWM timer Internal data bus CNTR COMR P T P1 PO TPE TIR OE TIE PWM compare register Start 8 bit counter gt CLK gt IRQ2 Clear 8 Over flow 8 a v v Count clock Comparator circuit selector gt 7 Jaen Timer PWM 1 tinst X16 T PWM generator Ls X64
260. sume more current than the product with mask ROM However the current consumption in sleep stop mode is the same For more information about the package see Section 1 6 Package Dimensions e For more information about the current consumption see the electrical characteristics in the Data Sheet Mask options Functions that can be selected as options and how to designate these options vary from product to product Before using check Appendix C Mask Options Take particular care on the following points e In the MB89951A and MB89953A the number of common and segment outputs is specified by Data Release Form e Options are fixed on the MB89PV950 See Appendix C Mask Options CHAPTER 1 OVERVIEW 1 4 Block Diagram of MB89950 950A Series Figure 1 4 1 IMMB89950 950A series overall block diagram shows the block diagram of the MB89950 950A series E MB89950 950A series block diagram Figure 1 4 1 MB89950 950A series overall block diagram Main oscillator circuit gp P41 PWM 8 bit PWM timer External interrupt 8 bit pulse width 8 P42 PWC count timer INT1 P40 Clock control circuit T S Reset circuit gs gaor bf RST Watchdog timer a gt P45 SCK Timebase timer lt t P46 INTO Internal bus CMOS UO port 8 N ch open drain I O port P00 SEG20 to P07 SEG27 8 P10 SEG28 to P17 SEG35 ae P20 SEG36 to P25 SEG41 Port 0 1 2 20 SEGO to i SEG19
261. t Selects the shift clock from one external and three internal clocks If an internal shift clock is selected the shift clock can be output to the SCK pin If external shift clock is selected the clock input from the SCK pin is used as the shift clock The SDR register shifts in synchronous with the shift clock and the shifted out value is output to the SO pin Similarly the serial input is obtained by shifting the SI pin input to the SDR register Shift clock counter The shift clock counter counts the number of SDR register shifts generated by the shift clock and overflows after eight shifts The overflow clears the serial I O transfer start bit in the SMR register SST 0 and sets the interrupt request flag SIOF 1 The shift clock counter stops counting when serial transfer halts SST 0 The shift clock counter is cleared when serial transfer restarts SST 1 SDR register The SDR register is used to store the transfer data Data written to this register is converted to serial and output Serial input is converted to parallel data and stored in this register SMR register The SMR register is used to enable or disable serial I O operation select the shift clock set the transfer shift direction control interrupts and check the serial I O status 172 CHAPTER 9 8 BIT SERIAL UO 9 3 Structure of 8 bit Serial I O This section describes the pins pin block diagram registers and interrupt source of
262. t Returning the reset pin to the H level wakes up the CPU from the external reset When power is turned on to products with power on reset or for external resets in stop mode the reset operation is performed after the oscillation stabilization delay time has passed and the CPU wakes up from the external reset External resets on products without power on reset do not wait for the oscillation stabilization delay time The external reset pin can also function as a reset output pin optional Software reset Writing 0 to the software reset bit in the standby control register STBC RST generates a four instruction cycle reset The software reset does not wait for the oscillation stabilization delay time Watchdog reset The watchdog reset generates a four instruction cycle reset if data is not written to the watchdog timer control register WDTC within a fixed time after the watchdog timer starts The watchdog reset does not wait for the oscillation stabilization delay time 43 CHAPTER 3 CPU Power on reset Products can be set to with or without power on reset optional On products with power on reset turning on the power generates a reset The reset operation is performed after the oscillation stabilization delay time has passed Moreover external reset signal is outputted by the reset output option On products without power on reset an external reset circuit is required to generate a reset when the power is turned o
263. t is generated immediately if the SIOF bit is 1 when the SIOE bit is changed from disabled to enabled OO an 1 E Register and vector table for 8 bit serial I O interrupts Table 9 4 1 Register and vector table for 8 bit serial UO interrupts Interrupt level setting register Vector table address Interrupt Register Setting bits Upper Lower IRQ5 ILR2 007Dp L51 Bit3 L50 Bit 2 FFFO FFF ly See Section 3 4 2 Interrupt Processing for details on the interrupt operation 180 CHAPTER 9 8 BIT SERIAL UO 9 5 Operation of Serial Output The 8 bit serial UO can perform serial output of 8 bit data synchronized with a shift clock E Serial output operation Serial output can operate using an internal or external shift clock When serial output operation is enabled the contents of the SDR register are output to the serial data output pin SO Serial input is performed at the same time Internal shift clock Figure 9 5 1 Serial output settings when using internal shift clock shows the settings required to operate serial output using an internal shift clock Figure 9 5 1 Serial output settings when using internal shift clock Bit 7 Bit 6 BitS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMR SIOF SIOE ES SOE CKS1 CKSO BDS SST S H 1 1 other than 11 1 SDR Sets transmit data Used bit 1 Set 1 Activating serial output operation outputs the contents of the S
264. t 5 MHz Noise pulse width 0 0 No noise filter 0 1 27 F oH 0 8 us 4 0 us 1 0 25 FcH 6 4 us 32 us 1 1 27 FcH 25 6 us 128 us FcH Main clock oscillation frequency R W Readable and writable Unused Initial value Table 8 3 3 PWC noise filter control register NCCR bits Function Unused bits e The read value is indeterminate Writing to these bits has no effect on the operation NCS1 NCSO For the pulse width measurement function Sampling clock These bits select sampling clock pulse for the noise filter circuit pulse selection bits There are three type of selectable sampling clock pulse from timebase timer For the interval timer function These bits have no meaning 154 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 4 Pulse Width Count Timer Interrupts The pulse width count timer has the following two interrupts e Counter value underflow 014 gt 00 for the interval timer function e Measurement completion and buffer full for the pulse width measurement function E Interrupt for the interval timer function The counter counts down from the set value on the selected internal count clock When an underflow occurs the underflow Oly gt Dn interrupt request flag bit PCR1 UF is set to 1 At this time an interrupt request IRQ3 to the CPU is generated if the interrupt request enable bit is enabled PCR1 IE 1 Write 0 to the UF bit
265. t change the flags and therefore care must be taken when a branch may occur depending on the result of a division Figure B 3 4 DIVU A shows a summary of the instruction Figure B 3 4 DIVUA Before execution After execution A 567 8H A 0034H T 1862H T 0002H 275 APPENDIX 276 XCHW A PC This instruction swaps the contents of A and PC resulting in a branch to the address contained in A before execution of the instruction After the instruction is executed A contains the address that follows the address of the operation code of MOVW A PC This instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine Figure B 3 5 XCHW A PC shows a summary of the instruction Figure B 3 5 XCHW A PC Before execution After execution A 5678H a on A 123 5H PC 123 4H PC 567 8H After the XCHW A PC instruction is executed A contains the address of the operation code of the next instruction rather than the address of the operation code of XCHW A PC Accordingly Figure B 3 5 XCHW A PC shows that A contains 12354 which is the address of the operation code of the instruction that follows XCHW A PC This is why 1235y is stored instead of 1234 Figure B 3 6 Example of using XCHW A PC shows an assembly language example Figure B 3 6 Example of using XCHW
266. t clock cycle x instruction cycle CHAPTER 8 PULSE WIDTH COUNT TIMER PWC For pulse width measurement function The register is used to store the pulse width measurement value The counter value is transferred to this register when pulse width measurement completes on detection of the edge specified for measurement completion At this time the buffer full flag bit PCR1 BF and the measurement completion interrupt request flag bit PCR1 IR are set to 1 Reading this register clears the BF bit to 0 The register is read only if the pulse width measurement function is selected Reference The pulse width for the pulse width measurement function is calculated based on the RLBR register value as follows Pulse width 256 RLBR register value x count clock cycle x instruction cycle 153 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC 8 3 4 PWC Noise Filter Control Register NCCR The PWC noise filter control register is used to select the sampling clock for the noise filter circuit There are three type of selectable sampling clock from the timebase timer E PWC noise filter control register NCCR Figure 8 3 6 PWC noise filter control register NCCR Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0017H NCS1 NCSO 00B R W R W ke l nest Men Sampling clock pulse selection bits Clock selected FcH a
267. tart of counting up using the selected count clock Therefore the time from activating the counter until a match with the PWM compare register COMR is detected may be shorter than the theoretical time by a maximum of one cycle count clock Figure 7 8 1 Error on starting counter operation shows the error that occurs on starting counter operation Figure 7 8 1 Error on starting counter operation Counter value 00H x Din x 02H X 03H x 04H X Count clock One cycle Error Cycle for 00H Counter activate Notes on setting by program e Do not change the count clock cycle CNTR P1 PO when the interval timer function or PWM timer function is operating CNTR TPE 1 e Stop the counter CNTR TPE 0 disable interrupts TIE 0 and clear the interrupt request flag TIR 0 before switching between the interval timer function and PWM timer function CNTR P T e Interrupt processing cannot return if the interrupt request flag bit CNTR TIR is 1 and the interrupt request enable bit is enabled CNTR TIE 1 Always clear the TIR bit e The TIR bit is not set if the counter is disabled TPE OT at the same time as the counter and COMR register values match 137 CHAPTER 7 8 BIT PWM TIMER 7 9 Program Example for 8 bit PWM Timer This section gives program examples for the 8 bit PWM timer E Program example for interv
268. ternal voltage divider is connected The LCD enable is inactive when LCD operation is stopped LCDR MS1 MSO 00 or in stop mode STBC STP 1 Pin V2 and V1 should be shorted together when using the 1 2 bias setting Figure 12 2 2 Internal voltage divider equivalent circuit shows an equivalent circuit of the internal voltage divider Figure 12 2 2 Internal voltage divider equivalent circuit Va 1V3 Short together when using 1 2 bias N ch LCD enable N ch ae MB89950 950A series VSEL Vi to V3 Voltages at V1 to V3 pins 237 CHAPTER 12 LCD CONTROLLER DRIVER E Use of internal voltage divider Figure 12 2 3 Use of internal voltage divider shows the voltage divider circuits for 1 2 and 1 3 bias As shown in this figure in the 1 2 bias mode with LCD enabled V2 and V1 will be 1 2 of V3 V3 is the LCD operating voltage which is Vcc in this configuration In the 1 3 bias mode V1 is 1 3 of V3 and V2 is 2 3 of V3 Figure 12 2 3 Use of internal voltage divider Vcc Vcc V3 V3 V3 _ V3 poy oO 0M R M R V2 V2 lt ____ _ _ vo B m vi ie i Vi Vi v1 a OW oe A LCD enable 4 _ N ch LCD enable N ch MB89950 950A series 777 MB89950 950A series 7 7 1 2 bias 1 3 bias V1 to V3 Volt
269. ters Registers are specified by the lower 3 bits of the operation codes Using the register bank pointer the addresses 0100y to O1FFy can be used as the general purpose register area However the available area is limited on some products if internal RAM only is used The initial value after a reset is indeterminate Note The register bank pointer is part of the program status PS and cannot be accessed independently 32 CHAPTER 3 CPU 3 3 General purpose Registers The general purpose registers are a memory block made up of banks with 8 x 8 bit registers per bank The register bank pointer RP is used to specify the register bank The function permits the use of up to 32 banks but the number of banks that can actually be used depends on how much RAM the device has Register banks are valid for interrupt processing vector call processing and subroutine calls E Structure of general purpose registers e The general purpose registers are 8 bits and located in the register banks of the general purpose register area in RAM e One bank contains eight registers RO to R7 and up to a total of 32 banks However the number of banks available for general purpose registers is limited on some products if internal RAM only is used e The register bank currently in use is specified by the register bank pointer RP The lower three bits of the operation code specify general purpose register 0 RO to general purpose register 7 R
270. the pin to the high XXXXXXXp impedance state if the pin Pin state is the functions as an output port H level Sets 1 to the output latch and turns the output transistor OFF S Disables the output transistor Port 4 data and sets the pin as an input pin direction register 0000000g DDR4 Enables the output transistor and sets the pin as an output pin R W Readable and writable W Write only X Indeterminate Unused bit Pins with a pull up resistor optional go to the H level 95 CHAPTER 4 I O PORTS 4 6 2 Operation of Port 4 This section describes the operations of the port 4 E Operation of port A Operation as an output port e Setting the corresponding DDR4 register bit to 1 sets a pin as an output port e When a pin is as an output port the output transistor is enabled and the pin outputs the data stored in the output latch e Writing data to the PDR4 register stores the data in the output latch and outputs the data to the pin e Reading the PDR4 register returns the pin value Operation as an input port e Setting the corresponding DDR4 register bit to 0 sets a pin as an input port e When a pin is set as an input port the output transistor is OFF and the pin goes to the high impedance state e Writing data to the PDP4 register stores the data in the output latch but does not output the data to the pin e Reading the PDR4 reg
271. tion cycles 1 Reading always returns 1 No effect on operation SPL Pin state specification bit 0 External pins hold their states prior to entering stop mode External pins go to high impedance state on entering stop mode Sleep bit gt SLP Read Write 0 Reading always returns 0 No effect on operation 1 Goes to sleep mode Stop bit STP Read Write 0 Reading always returns 0 No effect on operation 1 Goes to stop mode R W Readable and writable W Write only Unused X Indeterminate Initial value 61 CHAPTER 3 CPU 62 Table 3 7 2 Standby control register STBC bits Function Bit7 STP Sets the CPU entering stop mode Stop bit Writing 1 to this bit sets the CPU entering stop mode Writing 0 to this bit has no effect on operation Reading this bit always returns 0 Bit6 SLP Sets the CPU entering sleep mode Sleep bit Writing 1 to this bit sets the CPU entering sleep mode Writing 0 to this bit has no effect on operation Reading this bit always returns 0 Bit5 SPL Specifies the states of the external pins during stop mode Pin state Writing 0 to this bit specifies that external pins hold their states levels specification when entering stop mode bit Writing 1 to this bit specifies that external pins go to high impedance state when entering stop mode
272. to stop mode STBC STP 1 or by power on reset optional Interval timer selector Selects one of four operating timebase timer counter bits as the interval timer bit An overflow on the selected bit triggers an interrupt CHAPTER 5 TIMEBASE TIMER TBITC register The TBTC register is used to select the interval timer bit clear the counter control interrupts and check the state of the timebase timer 103 CHAPTER 5 TIMEBASE TIMER 5 3 Timebase Timer Control Register TBTC The timebase timer control register TBTC is used to select the interval times bit clear the counter control interrupts and check the state of the timebase timer E Timebase timer control register TBTC Figure 5 3 1 Timebase timer control register TBTC Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value SS GR 00000 000An TBIF TBIE TBR TBC1 TBCO B R W R W WwW R W R W L TBC1 TBCO Interval time selection bits 0 0 215 FCH 0 1 2 7 FCH 1 0 219 FCH 1 1 2 1 FCH Fcu Main clock oscillation frequency Timebase timer initialization bit gt TBR Read Write 0 e Clears timebase timer counter 1 Reading always returns No effect The bit does gek not change ck TBIE Interrupt request enable bit 0 Disables interrupt request output 1 Enables inte
273. tput cycle R W Readable and writable Unused Initial value 128 P T Operating mode selection bit CHAPTER 7 8 BIT PWM TIMER Table 7 3 1 PWM control register CNTR bits Function This bit switches between the interval timer function P T 0 and PWM timer function P T 1 Note Write to this bit when the counter operation is stopped TPE 0 interrupts are disabled TIE 0 and the interrupt request flag bit is cleared TIR 0 Unused bit The read value is indeterminate Writing to this bit has no effect on the operation P1 PO Clock selection bits These bits select the count clock for the interval timer function and PWM timer function These bits can select the count clock from three internal count clocks or the output cycle of the PWC timer Note Do not change P1 and PO when the counter is operating TPE 1 TPE Counter operation enable bit This bit activates or stops operation of the PWM timer function and interval timer function Writing 1 to this bit starts the counter operation Writing 0 to this bit stops the count and clears the counter to 00y TIR Interrupt request flag bit For the interval timer function This bit is set to 1 when the counter and PWM compare register COMR value match An interrupt request is issued to the CPU when both this bit and the interrupt request enable bit TIE are 1 For the PWM timer f
274. tputs Stop mode SPL 0 Low level outputs Stop mode SPL 1 Low level outputs During reset Low level outputs SEGO to SEG19 Segment outputs Segment outputs Low level outputs Low level outputs Low level outputs P00 SEG20 to PO7 SEG27 P10 SEG28 to P17 SEG35 P20 SEG36 to P25 SEG41 Port I O Peripheral output Port I O Peripheral output Port I O Peripheral output Low High impedance D Peripheral output Low High impedance D X0 Input for oscillation Input for oscillation High impedance CI High impedance EI Input for oscillation Kal Output for oscillation Output for oscillation High output High output Output for oscillation MODA Mode input Mode input Mode input Mode input Mode input RST Reset input Reset input Reset input Reset input Reset input ES P30 P31 Port I O Port I O Port I O High impedance CH High impedance P32 V1 P33 V2 Port LCD bias Port LCD bias Port LCD bias High impedance D LCD bias High impedance 5 V3 Input Input Input Input Input P40 to P46 INTO Port I O Peripheral I O Port I O Peripheral I O Port I O Peripheral I O High impedance 1 3 High impedance CH 1 The internal input level is fixed to prevent leakage due to open input Pins for which the pull up option is selected
275. transistor turns OFF and high impedance Hi Z is output from the pin e Writing data to the PDR1 register stores the data in the output latch and it will be output to the pin e Reading the PDR1 register returns the output latch value Operation as an input port e Writing 0 to the PDR1 register set the port as an input port the output transistor is OFF and the pin goes to the high impedance state e Reading the PDR1 register returns the pin value Operation as an LCD segment driver output e When the LCD output mask option is selected set the PDR1 register bits corresponding to the LCD segment driver output pins to 1 to turn the output transistor OFF e You cannot read the LCD output data by reading PDR1 Operation at reset e Resetting the CPU initializes the PDR1 register values to 1 This turns OFF the output transistor for all pins and all pins are in high impedance Hi Z state 80 CHAPTER 4 I O PORTS Operation in stop mode e The output transistors are forcibly turned OFF regardless of the PR DO register value and the pins go to the high impedance state if the pin state specification bit in the standby control register STBC SPL is 1 when the device goes to stop mode Moreover to avoid leakage from floating input pin input must be driven by either 1 or 0 when SPL 1 Table 4 3 4 Port 1 pin state lists the port 1 pin states Table 4 3 4 Port 1 pin state Normal operation Pin
276. ts Port 1 pins can be switched between LCD segment driver output and port operation by mask option This section principally describes the port functions when operating as N ch open drain UO port The section describes the port structure and pins the pin block diagram and the port register for port 1 E Structure of port 1 Port 1 consists of the following two components e N ch open drain I O pins LCD segment driver output pins P10 SEG28 to P17 SEG35 e Port 1 data register PDR1 E Port 1 pins Port 1 consists of eight N ch open drain I O When pins are used by the peripheral they cannot be used as N ch open drain I O Table 4 3 1 Port 1 pins lists the port 1 pins Table 4 3 1 Port 1 pins I O type Circuit type Pin name Function Shared peripheral Output P10 SEG28 P10 N ch open drain I O SEG28 LCD segment driver output P11 SEG29 P11 N ch open drain I O SEG29 LCD segment driver output P12 SEG30 P12 N ch open drain I O SEG30 LCD segment driver output P13 SEG31 P13 N ch open drain I O SEG31 LCD segment driver output Segment N ch P14 SEG32 P14 N ch open drain I O SEG32 LCD segment driver output open drain P15 SEG33 P15 N ch open drain I O SEG33 LCD segment driver output P16 SEG34 P16 N ch open drain I O SEG34 LCD segment driver output P17 SEG35 P17 N ch open drain I O SEG35 LCD segment driver output See Section 1 7 I O Pins and Pin Function
277. ts the transmit data flag to 0 After the transmit data is transferred to the transmit shift register the transmit data flag is set to 1 and the SODR is ready for the next data If transmit interrupt request is enabled interrupt occurs Write next transmission data when transmit data flag bit is set to 1 When the data length is set to 7 bits bit 7 does not have meaning 212 10 4 6 CHAPTER 10 UART Serial Mode Control Register 2 SMC2 Serial mode control register 2 SMC2 selects the division ratio of the baud rate generator selects to function as UART or SIO and enables the baud rate generator E Serial mode control register 2 SMC2 Figure 10 4 7 Serial mode control register 2 SMC2 Address 0024H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value PSEN RESV RSEL PDS1 PDSO 1 0 00B R W R W R W R W R W ss PDS1 PDS0 Input clock divider selection bits 0 0 Divided by 4 0 Divided by 6 1 0 Divided by 13 1 1 Divided by 65 gt RSEL UART SIO selection bit Function as UART Function as SIO Reserved bit Always write 0 PSEN R W Readable and writable Initial value Unused Baud rate generator enable bit Stops baud rate generator Starts baud rate generator 213 CHAPTER 10 UART Table 10 4 4
278. turn from subroutine 20 RETI return from interrupt restore 30 284 E Other instructions Table B 5 4 Other instructions MNEMONIC PUSHW A Operation APPENDIX B Overview of Instructions Z V C JOP CODE POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 285 truction map Ins truction map shows the F2MC 8L Ins Instruction map 6 1 F2MC 8L Table B 6 1 F2MC 8L instruction map APPENDIX B 6 Table B E Instruction map d WY i UI BP ZH geg Vav Wy my L4 Y dno AON agns 20 AON OH d d ap Bi ap OH Dua my my Dy d DN 03d d AON HO agns od AON GH GY GY ap Ei eH SH Dy BUY GUY GY Gy Y zg DN oad d AON HO ons 20 AON p H HU ap FI BPH HU gem my ty my GC ATWO 930 dno AON Yo ogns od AON oH ey ap EI mm CH gen Pv cu Y GK eu V Na ATWO 930 dno AON HO agns od AON e EH H ap EI BP ZH gezu 0 ou 0 H Y dd KI 930 dno AON HO We od AON D d II ap pl BPE LH gen lay DK DK DK og TI 03d d AON HO ons od AON Di d d ap Di BP OH gem Dy my Dy OK ATWO oad W dno AOW HO og od AON Dn 0 W di a30 Y p UI 8P d30 QP d30 a30 Y oy W i va WOoV MIOV WIOY WIV WON 1 MONI MAON dno AON HO a HON AON 29 od dp AON QiP X V PXO P XIO Y ap Di SPEPHXI BPEPHXIO P XIO V Doug Y PHXIO V V PHXIO PHXIO V PHXIO Y PHXIO V PHXIO Y MAON WON WOH W d AON HO a HON AON 29 od dp AON DI dS W UIP ID ap Ei BPH UI
279. turn to Zero system only The transmission data always begins with a start bit L level followed by a specified length of data bits arranged in the LSB first format and ends with stop bit s H level In asynchronous transfer mode the relation between serial clock and serial input output signal is not as shown in Figure 10 6 1 Transfer data format Figure 10 6 1 Transfer data format shows the relation between transmit receive clock and data in operation mode 1 when non parity 2 stop bits synchronous transfer transmit data of 01001101 8 bits are selected Figure 10 6 1 Transfer data format Transmitting receiving clock l l l l i Transmit received data i i 1 1 START LSB MSB STOP STOP ro ia EE eg EE Gee A o i CHAPTER 10 UART 10 7 Operation of Mode 0 1 3 The operation mode 0 1 and 3 provide a serial communication function E Operation of operation mode 0 1 3 Settings shown in Figure 10 7 1 Operation of operation mode 0 1 3 are necessary for the UART operation Figure 10 7 1 Operation of operation mode 0 1 3 Bit7 De BitS Bit4 Bits Bit2 Biti Bito SMC1 PEN SBL MC1 MCO SMDE SCKE sol e 4 Used bit src cr cs1 cso rRC2 RC1 RCo 1 Set 1 O Set 0 SSD IRDRFIORFEITDRE T
280. unction Interrupt requests are not generated Writing 0 clears this bit Writing 1 has no effect and does not change the bit value OE Output pin control bit The P41 PWM pin functions as a general purpose I O port P41 when this bit is set to 0 and a dedicated pin PWM when this bit is set to 1 The PWM pin outputs a square wave when the interval timer function is selected and a PWM waveform when the PWM timer function is selected TIE Interrupt request enable bit This bit enables or disables interrupt request output to the CPU Interrupt request is generated when both this bit and the interrupt request flag bit TIR are 1 129 CHAPTER 7 8 BIT PWM TIMER 7 3 2 PWM Compare Register COMR The PWM compare register COMR sets the interval time for the interval timer function The register value sets the H width of the pulse for the PWM timer function E PWM compare register COMR 130 Figure 7 3 4 PWM compare register COMR shows the bit structure of the PWM compare register As the register is write only bit manipulation instructions cannot be used Figure 7 3 4 PWM compare register COMR W Write only X Indeterminate Address Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0013H XXXXXXXXB Interval timer operation This register is used to set the value to be compared with the counter value The register specifies
281. unctions Divide by n outputs from the timebase timer are also supplied to the peripheral functions These clocks however are not affected by the speed shift function etc The timebase timer is clocked by the output of the main clock source oscillator after it is fed through a divide by 2 circuit Figure 3 6 1 Clock supply map shows the clock supply map 49 CHAPTER 3 CPU Figure 3 6 1 Clock supply map Xo Peripheral functions Pin F Main clock FCH Se i 8 S Di ascillator I Divide by two gt Timebase timer Watchdog timer Pin K 7K 8 bit PWC timer Clock controller j 1 1 Clock mode 1 f Stop mode 1 1 i 55 8 bit PWM timer so i 1 GEES 1 1 OC ru Divide by four 1 i 20 i i oo 1 1 S i UART i SCK gt Pin 1 1 1 Sleep stop mode i oscillation stabilization delay l Serial O ER gt Supply to the CPU 1 U 1 ee WEEN 1 tinst gt LCD controller driver Free run counter Oscillation stabilization FcH Main clock oscillation frequency delay controller tinst Instruction cycle divide by four main clock oscillation 50 CHAPTER 3 CPU 3 6 1 Clock Generator Enable and stop of the main clock oscillation are
282. upt request flag bit Read Write 0O Pulse width measurement has not completed Clears this bit 1 Pulse width measurement has completed No effect The bit does not change UF Underflow 01H gt 00h interrupt request flag bit Read Write D No underflow 01H gt 00x on counter Clears this bit 1 Underflow 01H 00x on counter No effect The bit does not change The UF IR and BF bits are interrupt request flag bits IE Interrupt request enable bit D Disables interrupt request output 1 Enables interrupt request output EN Counter operation enable bit Timer function Pulse width measure function D Count disables stops Pulse width measure disables stops 1 Count enables starts Pulse width measure enables starts R W Readable and writable H Read only Unused Initial value 148 EN Counter operation enable bit CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Table 8 3 1 PWC pulse width control register 1 PCR1 bits Function For the interval timer function Writing 1 to this bit starts the counter to count down from the PWC reload buffer register RLBR value Writing 0 to this bit stops the counter operation For the pulse width measurement function Writing 1 to this bit enables measurement The counter starts to count down from FFy on detection of the specified edge on the measurement pulse Writing 0 to this bit stops the counter operation Note If operation is disabled EN 0 dur
283. ure 3 5 1 Block diagram of external reset pin shows the block diagram of the external reset pin Figure 3 5 1 Block diagram of external reset pin T Pull up resistor Approx 50 KQ 5 0V Option RST J P ch With reset output S L Internal reset source Pin l l l Without reset output N ch i i Ee gt Internal reset signal Input buffer E External reset pin functions Inputting an L level to the external reset pin RST generates an internal reset signal When selecting products with reset output option setting the pin outputs an L level depending on internal reset sources or during the oscillation stabilization delay time due to an external reset Software reset watchdog reset and power on reset are classed as internal reset sources Note The external reset input accepts asynchronous with the internal clock Therefore initialization of the internal circuit requires a clock Especially when an external clock is used a clock is needed to be input at the reset 45 CHAPTER 3 CPU 3 5 2 Reset Operation When the CPU wakes up from a reset the CPU selects the read address of the mode data and reset vector according to the mode pin settings then performs a mode fetch The mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power on reset or on wake up from stop mode by
284. urpose register addressing MOV A R6 RP 01 0108 01564 ABH a ABH Immediate addressing Immediate addressing is indicated by d8 in the instruction list This addressing is used when immediate data is required In this addressing mode the operand is used as immediate data Whether the data is specified in bytes or words is determined by the operation code Figure B 2 7 Example of immediate addressing shows an example Figure B 2 7 Example of immediate addressing MOV A 564 gt A 5 6H 271 APPENDIX Vector addressing Vector addressing is indicated by vct in the instruction list This addressing is used to branch to a subroutine address stored in the vector table In this addressing mode vct information is contained in the operation codes and the corresponding table addresses are created as shown in Table B 2 1 Vector table addresses corresponding to vet Table B 2 1 Vector table addresses corresponding to vct vct Vector table address higher address lower address of branch destination Figure B 2 8 Example of vector addressing shows an example Figure B 2 8 Example of vector addressing CALLV 5 gt Conversion gt F F C AH F EH FFCBH DCH Pc FEDCH e 272 APPENDIX B Overview of Instructions Relative addressing Relative
285. utine only needs to specify its dedicated register bank at the start of the routine to effectively save the general purpose registers in use prior to the interrupt Therefore saving the general purpose registers to the stack or other memory location is not necessary This allows high speed interrupt handling while maintaining simplicity Also as an alternative to saving general purpose registers in subroutine calls register banks can be used to create reentrant programs programs that do not use fixed addresses and can be entered more than once usually made by the index register IX Note If an interrupt processing routine changes the register bank pointer RP ensure that the program does not also change the interrupt level bits in the condition code register CCR IL1 ILO when specifying the register bank CHAPTER 3 CPU 3 4 Interrupts The MB89950 950A series has 12 interrupt request inputs corresponding to peripheral functions The interrupt level can be set independently If an interrupt request output is enabled in the peripheral function an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller The CPU performs interrupt operation according to how the interrupt is accepted The CPU wakes up from standby mode and returns to the interrupt or normal operation E Interrupt requests from peripheral functions Table 3 4 1 Interrupt request and interrupt vector lists the
286. ution of the interrupt return instruction RETI at the completion of interrupt processing the CPU performs the opposite processing to interrupt initiation restoring first the program status PS and then the program counter PC from the stack This returns the PS and PC to their states immediately prior to the start of the interrupt Note The CPU does not automatically save the accumulator A or temporary accumulator T contents to the stack Use the PUSHW and POPW instructions to save and restore A and T contents to and from the stack 41 CHAPTER 3 CPU 3 4 6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM The contents of the stack pointer SP specifies the top address of the stack area E Stack area for interrupt processing The subroutine call instruction CALL and vector call instruction CALLV use the stack area to save and restore the program counter PC The stack area is also used by the PUSHW and POPW instructions to temporarily save and restore registers e The stack area is located in RAM along with the data area e Initializing the stack pointer SP to the top address of RAM and allocating data areas upwards from the bottom RAM address is recommended Figure 3 4 6 Stack area for interrupt processing shows the example of stack area setting Figure 3 4 6 Stack area for interrupt processing 0000H 1 0 0080H Data area RAM O100H
287. utput latch value is read during a bit manipulation This prevents the other output latch bits from being changed accidentally regardless of the I O directions and states of the pins Interrupt request flag bits during a bit manipulation An interrupt request flag bit functions as a flag bit indicating whether an interrupt request exists during a normal read operation However 1 is always read from this bit during a bit manipulation This prevents the flag from being cleared accidentally by a value of 0 which would otherwise be written to the interrupt request flag bit when another bit is manipulated 278 APPENDIX B Overview of Instructions B 5 F2MC 8L Instructions Table B 5 1 Transfer instructions to Table B 5 4 Other instructions list the instructions used with the F2MC 8L E Transfer instructions Table B 5 1 Transfer instructions MNEMONIC MOV dir A Operation dir lt A OP CODE 45 MOV IX off A IX off lt A 46 MOV ext A ext lt A 61 MOV EP A EP lt A 47 MOV Ri A Ri lt A 48 to 4F MOV A d8 A lt d8 04 MOV A dir A lt dir 05 MOV A IX off A lt IX off 06 MOV A ext A lt ext 60 MOV A A A lt A 92 MOV A EP A lt EP 07 MOV A Ri A lt Ri 08 to OF MOV dir d8 dir lt d8 85 MOV IX off
288. valuation device CT Development tool Main unit Probe MB2141A MB2144 505 MB2144 203 To use a the other development environment contact respective makers References e FMC Development Tool Catalog e Microcomputer Product Guide vi CONTENTS CHAPTER 1 OVERVIEW sssiciesicncccsscecet ccteccceacetiadseninadeeeansnceactdonedeceocewecboctenstunserbundoususeuanasa 1 1 1 MB89950 950A Series Features A 2 1 2 MB89950 950A Series Product Range ccceccceceeeeeseneeeeeeeeseeeeeeeaeeeeeaeeeseaeeeeeaeeseaeesecaeeeseaeeensneeesaes 4 1 3 Differences AMONG Products 6 1 4 Block Diagram of MB89950 950A Series 7 RS lge ul EE 8 1 6 Package DIMENSIONS isie kee eege deed EEN 10 1 7 WO Pins and Pin FUNCtiONS 12 CHAPTER 2 HANDLING DEVICES Z ss aeeskeueesesd eegene eege Eege ans 17 2 1 Notes on Handling Devices eee eeeeeeeeeceeeeeee ence ee eeeeeeenesaaaeeesesaaaeaeeeesaaeasesesaaaeseseeeseeeaeseeneaneeeseneaas 18 CHAPTER 3 CPU si sczscsnaindesaiecvodatstsaactteunsteauess anv anvaes she sade ateuanssetucdtetaveusdocwews ereteaxteaeanes 21 Sule Memor feed aie A heh ne een See dee ce dee ed a teats 22 Belli ER EE 24 3 1 2 Storing 16 bit Data in Memory 0 eee cece cece eeeneeeeeeeeeeeeeeeeaeeseaaeeeeaaeeseaaeeecaeessaeeeseaeesseaeeeeeieeeseaees 26 3 2 Dedicated Registers ue cecal heed docs edd chases cDadtet ere gtee eege eege 27 3 2 1 Condition Code Register CCR cccceecceceeseee
289. vel 1 Value compared with the counter value interval time Operate interval timer select 64 tinst start counter operation clear interrupt request flag enable TO pin output enable interrupt request output Enable interrupts Clear interrupt request flag Save A and T Restore A and T zal Z el 139 CHAPTER 7 8 BIT PWM TIMER E Program example for PWM timer function Processing description 140 e Generates a PWM wave with a duty ratio of 50 Then changes the duty ratio to 25 e Does not generate interrupts e For a5 MHz main clock oscillation frequency Fcp selecting the interval 16 t count clock gives a PWM wave cycle of 16 x 4 5 MHz x 256 3 277 ms e The following shows the COMR register value required for a duty ratio of 50 COMR register value 50 100 x 256 128 080p Coding example CNTR EQU 0012H COMR EQU 0013H 4 TPE EQU CNTR 3 b CSEG i CLRB TPE MOV COMR 80H 5 MOV CNTR 10011010B MOV COMR 40H E ENDS END Address of the PWM control register Address of the PWM compare register Define the counter operation enable bit Stop counter operation Set H width of pulse Duty ratio 50 Operate PWM timer select 16 tinst start counter operation clear interrupt request flag enable PWM pin output and disable interrupt request output Change the duty ratio to 25 effective from the next PWM wave cycle CHAPTER 8
290. x aS 1 Count ET E Noise clock lt x4 K 1 tinst filter lt From ESA selector K x32 clock _ timebase selector lt timer RLBR ki ke NCCR NCS1 NCSO tinst Instruction cycle 144 CHAPTER 8 PULSE WIDTH COUNT TIMER PWC Count clock selector Selects a count clock for the 8 bit down counter from the three available internal count clocks 8 bit down counter The 8 bit down counter starts to count from the value set in the PWC reload buffer register RLBR when operating as an interval timer and from FFy when performing pulse width measurement When an underflow 014 gt 00p occurs the counter inverts the timer output bit PCR2 TO Input pulse edge detector Operates when the pulse width measurement function is selected and starts or stops the 8 bit down counter when an edge input from the PWC pin matches the edge specified by the PWC pulse width control register 2 PCR2 Noise filter circuit The PWC input is sampled by the clock pulse selected by the sample clock selector The sample input signal is integrated to clear the noise Noise filter clock selector Selects a sampling clock for the noise filter circuit from three count clocks of timebase timer RLBR register When operating in reload timer mode of the interval timer function the RLBR register value is re loaded to the counter and the count continues whenever a counter value underflow 01 gt 00y occurs
291. y external interrupt requests can occur during stop mode because peripheral functions are stopped After wake up from stop mode the normal interrupt operation is performed after the oscillation stabilization delay time has passed If the interrupt request is accepted the CPU executes interrupt processing If the interrupt request is not accepted the CPU continues execution from the subsequent instruction following the instruction executed immediately before entering stop mode Some peripheral functions restart from mid operation when the CPU wakes up from stop mode by an external interrupt The first interval time from the interval timer function for example is indeterminate Therefore initialize all peripheral functions after wake up from stop mode Note Only interrupt requests from external interrupt circuits can be used to wake up from stop mode by an interrupt CHAPTER 3 CPU 3 7 4 Standby Control Register STBC The standby control register STBC controls the CPU to enter to sleep mode stop mode sets the pin states in stop mode and initiates software reset E Standby control register STBC Figure 3 7 1 Standby control register STBC Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0008H STP SLP SPL RST 0001 B WwW WwW R W Ww Software reset bit RST 8 Read Write 0 Generates a reset signal for four instruc
292. ystem wakes up from the initialize process caused by reset an initializing period of 11 shift clocks is needed for initializing the internal control blocks 219 CHAPTER 10 UART 10 8 Program Example for UART This section gives program example for UART E Program example for UART Processing description 220 Perform serial transmit receive operation using communication functions of the UART P45 SCK P44 SO and P43 SI pins are used for communication Set a transmission speed of 150 baud by the internal baud rate generator A character 134 is transmitted from the SO pin and triggers the operation by interrupt The baud rate is set with the main clock oscillation frequency Foy of 5 MHz Coding example PDR4 EQU DOOER DDR4 EQU OO0OFH i SMC1 EQU 0020H A SRC EQU 0021H SSD EQU 0022H SIDR EQU 0023H SODR EQU 0023H SMC2 EQU 0024H PSEN EQU SMC2 5 i ILR2 EQU 007DH i INT_V DSEG ABS i ORG OFFF2H IRQ4 DW WARI INT_V ENDS DE Main Drogram CSEG i CLRI i MOV ILR2 11111101B MOV SMC1 01011011B MOV SRC 00010100B MOV SSD 00101000B MOV SMC2 00000011B MOV SODR 13H s SETB PSEN SZ SETI CHAPTER 10 UART Address of the port data register Address of the port direction register Address of the serial mode control register 1 Address of the serial rate control register Address of the serial status and data register Address of the serial input data
293. yte of the address is 00 and the lower byte is specified by the operand Figure B 2 1 Example of direct addressing shows an example Figure B 2 1 Example of direct addressing 4 5H ka Extended addressing Extended addressing is indicated by ext in the instruction list This addressing is used to access the entire 64 KB area In this addressing mode the first operand specifies the higher byte of the address and the second operand specifies the lower byte Figure B 2 2 Example of Extended Addressing shows an example Figure B 2 2 Example of extended addressing MOVWA 12341 gt 12 34H 5 6H 12 35H 7 8H ae gt A 56 7 8H 269 APPENDIX Bit direct addressing Bit direct addressing is indicated by dir b in the instruction list This addressing is used to access a particular bit in the area between 0000 and OOFFy In this addressing mode the higher byte of the address is 00y and the lower byte is specified by the operand The bit position at the address is specified by the lower three bits of the operation code Figure B 2 3 Example of bit direct addressing shows an example Figure B 2 3 Example of bit direct addressing SETB 34H 2 76543 210 00 344 XXXXX1XXeB Index addressing Index addressing is indicated by IX off in the instruction list This addressing i

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