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Cypress CY7C63310 Network Card User Manual

1. rd_wrn x X Document 38 08035 Rev K Page 49 of 83 Feedback CYPRESS PERFORM 17 Interrupt Controller The interrupt controller and its associated registers allow the code to respond to an interrupt from almost every functional block in the enCoRe Il devices The registers associated with the interrupt controller allow disabling interrupts globally or individually The registers also provide a mechanism by which a user may clear all pending and posted interrupts or clear individual posted or pending interrupts The following table lists all interrupts and the priorities that are available in the enCoRe II devices Table 17 1 Interrupt Numbers Priorities Vectors Priority Address Name 0 00000 Reset 1 0004h POR LVD 2 0008h INTO 3 000Ch SPI Transmitter Empty 4 0010h SPI Receiver Full 5 0014h Port 0 6 0018h GPIO Port 1 7 001Ch INT1 8 0020h 9 0024h 10 0028h 2 11 002Ch USB Reset 12 0030h USB Active 13 0034h 1 mS Interval timer 14 0038h Programmable Interval Timer 15 003Ch Capture 0 16 0040h Timer Capture 1 17 0044h 16 bit Free Running Timer Wrap 18 0048h INT2 19 004Ch 52 Data Low 20 0050h GPIO Port 2 21 0054h GPIO Po
2. E il CY7C63310 CY7C638xx Figure 10 3 Timer Capture Block Diagram System Clock Configuration Status and Control Captimer Clock i Y 16 bit counter Capture Registers e gt lt lt ims Overflow timer Interrupt Int Capture Int Interrupt Controller Table 10 7 Clock IO Config CLKIOCR 0x32 R W Bit 7 6 5 4 2 1 0 Field Reserved CLKOUT Select Read Write R W R W Default 0 0 0 0 0 0 0 Bit 7 2 Reserved Bit 1 0 CLKOUT Select 0 0 Internal 24 MHz Oscillator 0 1 External clock external clock at CLKIN P0 0 1 0 Internal 32 kHz low power oscillator 112 CPUCLK 10 2 CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select Bit 0 Table 10 3 on page 22 is forced to the Internal Oscillator and the oscillator is stopped When the CPU comes out of sleep mode it runs on the internal oscillator The internal oscillator recovery time is three clock cycles of the Internal 32 kHz Low power Oscillator If the system requires the CPU to run off the external clock after awaking from sleep mode the firmware must switch the clock source for the CPU Document 38 08035 Rev K Page 26 of 83 Feedback CYPRESS CY7C63310 CY7C638xx PERFORM
3. 1 SCK CPOL 0 eem e SCK 1 MOSI MSB Tssu Tsp01 gt MISO Document 38 08035 Rev K Tsup MSB LSB Page 74 of 83 Feedback Cypress CY7C63310 CY7C638xx 4 PERFORM 29 Ordering Information Ordering Code FLASH Size RAM Size Package Type CY7C63310 PXC 3K 128 16 PDIP CY7C63310 SXC 3K 128 16 SOIC CY7C63801 PXC 4K 256 16 PDIP CY7C63801 SXC 4K 256 16 SOIC CY7C63803 SXC 8K 256 16 SOIC CY7C63803 SXCT 8K 256 16 SOIC Tape and Reel CY7C63813 PXC 8K 256 18 PDIP CY7C63813 SXC 8K 256 18 SOIC CY7C63823 QXC 8K 256 24 QSOP CY7C63823 SXC 8K 256 24 SOIC CY7C63823 SXCT 8K 256 24 SOIC Tape and Reel CY7C63823 XC 8K 256 Die form CY7C63833 LFXC 8K 256 32 QFN CY7C63833 LTXC 8K 256 32 QFN Sawn CY7C63833 LTXCT 8K 256 32 QFN Sawn Tape and Reel 30 Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture The maximum bake time is the aggregate time that the parts are exposed to the bake temperature Exceeding this exposure time may degrade device reliability Parameter Description Min Typical Max Unit TBAKETEMP Bake Temperature 125
4. P1 5 5MOSI P0 7 2 191 7 TIOO PO 5 4 H 1 4 5 TIO1 PO 6 P1 6 5MISO INT2 P0 4 5 H P3 1 TIO0 P0 5 4 P1 5 5MOSI INT1 PO 3 6 P3 0 INT2 PO 4 5 P1 4 SCLK INTO PO 2 7 1 3 55 INT1 P0 3 6 P3 1 8 P1 2 VREG INTO PO 2 0 7 1P3 0 0 0 Q C P0 1 0 8 P1 3 SSEL P2 1 1P1 1 D P0 0 P2 1 P2 0 j P1 1 D NC CY7C63833 32 QFN Of 2 PO 6 TION P1 5 5MOSI 50940 5 00 P14 SCLK 5 00 PO A INT2 P3 1 PO 4 INT2 P0 3 INT1 P3 0 PO 3 INT1 PO 2 INTO P1 3 SSEL PO 2 INTO P0 1 NC P0 1 P0 0 18 P1 2 vREG POD P2 1 17H NC P2 1 9 4 6 OUGOUOUOU AA 522228835 aa Document 38 08035 Rev K Vss E ON Oak won P1 0 D CY7C63833 32 Pin Sawn QFN MOS e 22 2 nox 32 31 30 29 28 27 26 25 24 P1 5 SMOSI 23 P14 SCLK 22L P3 1 210 P3 0 20 1 P1 3 SSEL 19L NC 18L P1 2 VREG 17 NC 9 10 11 12 13 14 15 16 S00 0 28 8 P1 0 D P1 1 D Page 4 of 83 Feedback CYPRESS CY7C63310 CY7C638xx Figure 5 2 CY7C63823 Die Form 23 Cypress Logo lt x 14 5 Legend 8 Die step 1792 98 uim x 2272 998 um 9 Die size 17
5. SAMPLE LVD POR BRQ BRA CPU VY 577 KRY Document 38 08035 Rev Page 30 of 83 Feedback Bit 7 6 Reserved Bit 5 4 PORLEV 1 0 0 0 2 7V Range trip near 2 6V 0 1 2 3V Range trip near 2 9V internal PPOR comparator state with trip point set to the 3V range setting gt 2 CYPRESS CY7C63310 CY7C638xx PERFORM 13 Low Voltage Detect Control Table 13 1 Low Voltage Control Register LVDCR 0x1E3 R W Bit 7 6 5 4 3 2 1 0 Field Reserved PORLEV 1 0 Reserved VM 2 0 Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This register controls the configuration of the Power Reset Low voltage Detection block Note This register exists in the second bank of IO space This requires setting the bit in the CPU flags register This field controls the level below which the precision power on reset PPOR detector generates a reset 10 5V Range gt 4 75V trip near 4 65V This setting must be used when operating the CPU above 12 MHz 1 1 PPOR does not generate a reset but values read from the Voltage Monitor Comparators Register Table 13 2 give the Bit 3 Reserved Bit 2 0 VM 2 0 VM 2 0 5 LVD Trip LVD Trip LVD Trip oint V Min Point V Typ Point V Max 000 Reserved Reserved Reserved 001 Reserved Reserved Reserved 010 Reserved R
6. 10 1 Clock Architecture Description The enCoRe II clock selection circuitry allows the selection of independent clocks for the CPU USB Interval Timers and Capture Timers The CPU clock CPUCLK is sourced from an external clock or the Internal 24 MHz Oscillator The selected clock source is optionally divided by 2 where nis 0 5 7 see Table 10 4 on page 23 USBCLK which must be 12 MHz for the USB SIE to function properly is sourced by the Internal 24 MHz Oscillator or an external 12 MHz 24 MHz clock An optional divide by two allows the use of 24 MHz source The Interval Timer clock ITMRCLK is sourced from an external clock the Internal 24 MHz Oscillator the Internal 32 kHz low power oscillator or from the timer capture clock TCAPCLK A programmable prescaler of 1 2 3 4 then divides the selected Source Table 10 1 IOSC Trim IOSCTR 0x34 R W CY7C63310 CY7C638xx The Timer Capture clock TCAPCLK is sourced from an external clock Internal 24 MHz Oscillator or the Internal 32 kHz low power oscillator The CLKOUT pin PO 1 is driven from one of many sources This is used for test and is also used in some applications The sources that drive the CLKOUT follow m CLKIN after the optional EFTB filter m Internal 24 MHz Oscillator m Internal 32 kHz low power oscillator m CPUCLK after the programmable divider Bit 7 6 5 4 3 2 1 0 Field foffset 2 0 Gain 4 0 Read Write R
7. 2 CYPRESS CY7C63310 CY7C638xx PERFORM 23 Details of Mode for Differing Traffic Conditions continued Control Endpoint SIE Bus Event SIE EPO Mode Register EPO Count Register EPO Interrupt Comments Mode Token Count 00 1 Response I O DVAL COUNT FIFO 1101 IN x x x STALL Stall IN NAK IN 1100 OUT x x x Ignore 1100 IN x x x NAK If Enabled NAK IN 24 Register Summary The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above OxFF Addr Name 7 6 5 4 3 2 1 0 R W Default 00 PODATA 7 PO 6 TIO1 PO 5 TIOO PO 4 INT2 PO 3 INT1 PO 2 INTO PO 1 CLK bbbbbbbb 00000000 OUT N 01 P1DATA P1 7 P1 6 SMI P1 5 5MO P1 4 SCLK P1 3 SSEL P1 2 VREG P1 1 D P1 0 D bbbbbbbb 00000000 SO SI 02 P2DATA Res P2 1 P2 0 bbbbbbbb 00000000 03 P3DATA Res P3 1 P3 0 bbbbbbbb 00000000 04 P4DATA Res Res bbbb 00000000 05 POOCR Reserved Int Int Act TTL Thresh Reserved Open Drain Pull up Output bbbbbbb 00000000 Enable Low Enable Enable 06 PO1CR CLK Int Int Act TTL Thresh Reserved Open Drain Pull up Output bbbbbbbb 00000000 Output Enable Low Enable Enable 07 09 PO2CR
8. 0 200 REF 0 250 0 856 PIN 24 4 2 PIN 1 DOT LASER MARK amp 3 500 0 100 8 1 17 0 400 0 100 9 16 16 0 025 0 0202 6 06 SEATING PLANE Document 38 08035 Rev K 001 30999 A Page 79 of 83 Feedback CY7C63310 CY7C638xx CYPRESS PERFORM 32 Document History Page Document Title CY7C63310 CY7C638xx enCoRe Low Speed USB Peripheral Controller Document Number 38 08035 Rev ECN No 4 Description of Change 131323 XGR 12 11 03 New data sheet 221881 KKU See ECN Added Register descriptions and package information changed from advance information to preliminary B 271232 BON See ECN Reformatted Updated with the latest information 299179 See Corrected 24 pinout typo in Table 5 2 on page 6 Added Table 10 1 page 21 Updated Table 9 5 on page 16 Table 10 3 on page 22 Table 13 1 on page 31 Table 17 2 on page 52 Table 17 4 on page 52 Table 17 6 on page 53 and Table 15 2 on page 41 Added various updates to the GPIO Section General Purpose GPIO Ports on page 33 Corrected Table 15 4 on page 42 Corrected Figure 28 7 on page 73 and Figure 28 8 on page 73 Added the 16 pin PDIP package diagram section Package Diagrams on page 76 D 322053 TVR See ECN Introduction on page 3 Removed Low voltage reset in last paragraph There is no LVR only LVD Low voltage detect Ex
9. H H H clk sys 0 rise fall TIO1 1 rise 1 fall cap rise reg 0 fall reg 1 rise reg 1 fall reg Timing diagrams when is in 8 bit mode 1 rise reg cap fall reg Timing diagrams when is in 16 bit mode Document 38 08035 Rev K Page 48 of 83 Feedback Cypress 7 63310 CY7C638xx write data ready FRT reload 126 Prog Timer 125 reload interrupt 12 bit programmable timer load timing Capture timer 166 free running counter load 16b free 00 0 00 1 00 2 00A3 0044 00A5 00A6 00 7 00 8 00 9 00 0080 10081 0082 running counter 16 bit free running counter loading timing Figure 16 5 Memory Mapped Registers Read Write Timing Diagram clk_sys
10. Up to 20 GPIO pins 2 mA source current on all GPIO pins Configurable 8 or 50 mA pin current sink on designated pins Each GPIO port supports high impedance inputs config urable pull up open drain output CMOS TTL inputs and CMOS output Maskable interrupts on all IO pins m A dedicated 3 3V regulator for the USB PHY Aids in signalling and D line pull up Cypress Semiconductor Corporation Document 38 08035 Rev K 198 Champion Court m 125 mA 3 3V voltage regulator powers external 3 3V devices m 3 3V IO pins a 410 pins with 3 3V logic levels Each 3 3V pin supports high impedance input internal pull up open drain output or traditional CMOS output m SPI serial communication Master or slave operation Configurable up to 4 Mbit second transfers in the master mode Supports half duplex single data line mode for optical sensors m 2 channel 8 bit or 1 channel 16 bit capture timer registers Capture timer registers store both rising and falling edge times Two registers each for two input pins Separate registers for rising and falling edge capture a Simplifies the interface to RF inputs for wireless applications m Internal low power wakeup timer during suspend mode Periodic wakeup with no external components m 12 bit Programmable Interval Timer with interrupts m Advanced development tools based on Cypress PSoC tools m Watchdog timer WDT m Low voltage detectio
11. 11 Reset The microcontroller supports two types of resets Power on Reset POR and Watchdog Reset WDR When reset is initiated all registers are restored to their default states and all interrupts are disabled The occurrence of a reset is recorded in the System Status and Control Register CPU_SCR Bits within this register record the occurrence of POR and WDR Reset respectively The firmware interrogates these bits to determine the cause of a reset The microcontroller resumes execution from Flash address 0x0000 after a reset The internal clocking mode is active after a reset until changed by the user firmware Note The CPU clock defaults to 3 MHz Internal 24 MHz Oscillator divide by 8 mode at POR to guarantee operations at the low that may be present during the supply ramp Table 11 1 System Status and Control Register CPU SCR OxFF R W Bit 7 6 5 4 3 2 1 0 Field GIES Reserved WDRS PORS Sleep Reserved Stop Read Write R RICHI R W R W Default 0 0 0 1 0 0 0 0 bits of the CPU_SCR register used to convey status and control of events for various functions of an enCoRe II device Bit 7 GIES The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged The GIES bit is a legacy bit which was used to provide the ability to read the GIE bit of the CPU_F register However the CPU_F register is now readable When this bi
12. 2 CYPRESS CY7C63310 CY7C638xx DIMENSIONS IN INCHES JEDEC STD REF MO 119 Figure 31 5 24 Pin 300 Mil SOIC 13 O0 7 620 089 EATI LANE 163 E E TES Aforo aL 0 004 0 101 1270 gorapo sso SEM 0 019 0 482 Figure 31 6 24 Pin QSOP 0241 0033 12 1 PIN 1 ID 1 0 150 0 228 0 157 0 244 13 24 L 0 337 2 0 344 SEATING PLANE 0 053 0 069 0 004 0 004 0 010 0025 BSC Document 38 08035 Rev K 51 85025 C DIMENSIONS IN INCHES MIN MAX 0 007 0 010 _ d p IN 1 L 0 016 0 8 0 034 51 85055 B Page 78 of 83 Feedback CY7C63310 CY7C638xx Cypress PERFORM Figure 31 7 32 Pin QFN Package TOP VIEW SIDE VIEW BOTTOM VIEW PIN1 ID 0 20 3 50 0 23 0 05 PSR m RRL gt SOLDERABLE gt 3 50 25 0 30 0 50 51 85188 Figure 31 8 32 Pin Sawn QFN Package VIEW SIDE VIEW BOTTOM VIEW 3 500 REF 5 000 0 100 0 00050 100 0 500 pitch 32 25
13. Document 38 08035 Rev K Page 71 of 83 Feedback CY7C63310 CY7C638xx Source EOP Width Receiver EOP Width Teopre SEO Skew Figure 28 6 Differential Data Jitter ke gt Crossover Points Differential Data Lines Consecutive Transitions N Transitions 2 Document 38 08035 Rev K Page 72 of 83 Feedback YPRESS CY7C63310 CY7C638xx PERFORM Figure 28 7 SPI Master Timing CPHA 1 55 SS is under firmware control in SPI Master mode TsckL SCK CPOL 0 SCK CPOL 1 MOSI 5 LSB lt Figure 28 8 SPI Slave Timing 1 Tsss TsckL SCK CPOL 0 Toon SCK CPOL 1 MOSI MSB AM LSB lt lt Tspo 550 5 MSB LSB Document 38 08035 Rev K Page 73 of 83 Feedback PERFORM CY7C63310 CY7C638xx Figure 28 9 SPI Master Timing CPHA 0 55 SS is under firmware control in SPI Master mode SCK CPOL 0 SCK CPOL 1 T MDO1 4 gt MOSI 5 LSB Tsss Figure 28 10 SPI Slave Timing CPHA 0
14. M Wis 2 CYPRESS PERFORM CY7C63310 CY7C638xx enCoRe M Low Speed USB Peripheral Controller 1 Features USB 2 0 USB IF certified TID 40000085 m enCoRe USB enhanced Component Reduction Crystalless oscillator with support for an external clock The internal oscillator eliminates the need for an external crystal or resonator Two internal 3 3V regulators and an internal USB pull up resistor Configurable IO for real world interface without external com ponents m USB Specification compliance Conforms to USB Specification Version 2 0 Conforms to USB HID Specification Version 1 1 Supports one low speed USB device address Supports one control endpoint and two data endpoints Integrated USB transceiver with dedicated 3 3V regulator for USB signalling and D pull up Enhanced 8 bit microcontroller Harvard architecture M8C CPU speed is up to 24 MHz or sourced by an external clock signal m internal memory Up to 256 bytes of RAM Up to eight Kbytes of Flash including EEROM emulation m Interface can auto configure to operate as PS 2 or USB No external components for switching between PS 2 and USB modes General Purpose IO GPIO pins required to manage dual mode capability m Low power consumption Typically 10 mA at 6 MHz 10 uA sleep system reprogrammability Allows easy firmware update m GPIO ports
15. PS2 Data Low 0x0050 GPIO Port 2 0x0054 GPIO Port 3 0x0058 Reserved 0x005C Reserved 0x0060 Reserved 0x0064 Sleep Program Memory begins here If below interrupts not used program memory can start lower 0x0068 USB Reset USB Active 1 ms Interval timer Programmable Interval Timer Timer Capture 0 Timer Capture 1 16 bit Free Running Timer Wrap 3 KB ends here CY7C63310 OxOBFF 4 KB ends here CY7C63801 OxOFFF Page 13 of 83 8 KB ends here CY7C638x3 Feedback OxiFFF Document 38 08035 Rev K CYPRESS PERFORM 9 2 Data Memory Organization CY7C63310 CY7C638xx The CY7C63310 638xx microcontrollers provide up to 256 bytes of data RAM Figure 9 2 Data Memory Organization Stack begins here and grows upward after reset Address 8 bit PSP gt 0 00 of RAM Memory OxFF 9 3 Flash This section describes the Flash block of the enCoRe II Much of the user visible Flash functionality including programming and security are implemented in the M8C Supervisory Read Only Memory SROM The enCoRe II Flash has an endurance of 1000 cycles and a 10 year data retention capability 9 3 1 Flash Programming and Security All Flash programming is performed by code in the SROM The registers that control the Flash programming are only visible to the M8C CPU when it executes out of SROM Th
16. expr 70 7 24 7 2 AND expr A 2 5 2 MOV A expr 7E 10 1 2 25 8 21 A 2 6 2 MOVA 8 1 26 9 3 expr expr Z 5 2 expr A 8x 5 2 JMP 27 10 3 AND X expr expr 2 6 2 MOV X expr 9x 11 2 CALL 28 11 1 ROMX 2 8 3 MOV expr expr Ax 5 207 29 4 2 ORA expr 2 9 3 MOV X expr expr 5 2 JNZ 2A 6 2 ORA expr Z 4 2 MOV X expr Cx 5 2 JC 2B 7 2 ORA Z 6 2 MOV X expr Dx 5 2 JNC 2C 7 2 OR expr A 2 7 2 MOV X X expr Ex 7 2 JACC 13 2 INDEX Z Notes 2 Interrupt routines take 13 cycles before execution resumes at interrupt vector table 3 The number of cycles required by an instruction is increased by one for instructions that span 256 byte boundaries in the Flash memory space Document 38 08035 Rev K Page 12 of 83 Feedback CY7C63310 CY7C638xx CYPRESS PERFORM Figure 9 1 Program Memory Space with Interrupt Vector Table Address Program execution begins here after a reset 9 Memory Organization 9 1 Flash Program Memory Organization 0x0000 POR LVD 4 0 0004 INTO SPI Transmitter Empty SPI Receiver Full after reset 16 bit PC 0x0008 0 000 0 0010 0 0014 GPIO Port 0 0x0018 GPIO Port 1 0x001C INT1 0x0020 0x0024 0x0028 0 002 0 0030 0 0034 0 0038 0 003 0 0040 2 0 0044 0 0048 0 004
17. 1 Fall Enable 0 Disable the capture 1 falling edge interrupt 1 Enable the capture 1 falling edge interrupt Bit 2 1 Rise Enable 0 Disable the capture 1 rising edge interrupt 1 Enable the capture 1 rising edge interrupt Bit 1 Fall Enable 0 Disable the capture 0 falling edge interrupt 1 Enable the capture 0 falling edge interrupt Bit 0 0 Rise Enable 0 Disable the capture 0 rising edge interrupt 1 Enable the capture 0 rising edge interrupt Table 16 13 Capture Interrupt Status TCAPINTS 0x2C R W Bit 7 6 5 4 3 2 1 0 Field Reserved TIO1 Fall TIO1 Rise Active TIOO Fall TIOO Rise Active Active Active Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 4 Reserved Bit 3 1 Fall Active 0 No event 1 A falling edge has occurred 1 Bit 2 TIO1 Rise Active 0 No event 1 rising edge has occurred on TIO1 Bit 1 TIOO Fall Active 0 No event 1 A falling edge has occurred on TIOO Bit 0 TIOO Rise Active 0 No event 1 rising edge has occurred on TIOO Note The interrupt status bits must be cleared by firmware to enable subsequent interrupts This is achieved by writing a 1 to the corresponding Interrupt status bit Document 38 08035 Rev K Page 47 of 83 Feedback CYPRESS CY7C63310 CY7C638xx PERFORM Figure 16 3 Timer Functional Sequence Diagram clk_captimer 16 bit free running counter
18. Default 0 D D D D D D D This register is used to calibrate the 32 kHz Low speed Oscillator The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing tests This value does not require change during normal use This is the meaning of D in the Default field If the 32 kHz Low power bit is written care must be taken to not disturb the 32 kHz Bias Trim and the 32 kHz Freq Trim fields from their factory calibrated values Bit 7 32 kHz Low Power 0 The 32 kHz Low speed Oscillator operates in normal mode 1 The 32 kHz Low speed Oscillator operates in a low power mode The oscillator continues to function normally but with reduced accuracy Bit 6 Reserved Bit 5 4 32 kHz Bias Trim 1 0 These bits control the bias current of the low power oscillator 0 0 Mid bias 0 1 High bias 1 0 Reserved 1 1 Reserved Note Do not program the 32 kHz Bias Trim 1 0 field with the reserved 10b value because the oscillator does not oscillate at all corner conditions with this setting Bit 3 0 32 kHz Freq Trim 3 0 These bits are used to trim the frequency of the low power oscillator Table 10 3 CPU USB Clock Config CPUCLKCR 0x30 R W Bit 4 7 6 5 4 3 2 1 0 Field Reserved USB CLK 2 USB CLK Select Reserved CPUCLK Select Disable Read Write R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 Reserv
19. K Page 36 of 83 Feedback CYPRESS CY7C63310 CY7C638xx PERFORM Table 14 7 P0 2 INTO P0 4 INT2 Configuration PO2CR PO4CR 0 07 0 09 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 These registers control the operation of pins 0 2 0 4 respectively The pins are shared between the 0 2 0 4 GPIOs and the INTO INT2 These registers exist in enCoRe parts The INTO INT2 interrupts are different from all the other GPIO interrupts These pins are connected directly to the interrupt controller to provide three edge sensitive interrupts with independent interrupt vectors These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set The pins are enabled as interrupt sources in the interrupt controller registers Table 17 8 on page 55 and Table 17 6 on page 53 To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable If the INTO INT2 pins are configured as outputs with interrupts enabled firmware can generate an interrupt by writing the appropriate value to the 2 0 3 and 0 4 data bits in the PO Data Register Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable Int act Low TTL Threshold Open Drain
20. and Pull Up Enable bits control the behavior of the pin The P0 2 INTO PO 4 INT2 pins are individually configured with the PO2CR 0x07 PO3CR 0x08 and PO4CR 0x09 respec tively Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated When configuring these interrupt sources it is best to follow the following procedure 1 Disable interrupt source 2 Configure interrupt source 3 Clear any pending interrupts from the source 4 Enable interrupt source Table 14 8 P0 5 TIOO PO 6 TIO1 Configuration POSCR PO6CR 0x0A 0x0B R W Field TIO Output Int Enable Int Act Low TTL Thresh Pull up Enable Output Enable These registers control the operation of pins 5 through 6 respectively These registers exist enCoRe II parts P0 5 and PO 6 are shared with TIOO and 1 respectively To use these pins as Capture Timer inputs configure them as inputs by clearing the corresponding Output Enable To use TIOO and TIO1 as Timer outputs set the Output and Output Enable bits If these pins are configured as outputs and the TIO Output bit is clear firmware can control the TIOO and TIO 1 inputs by writing the value to the P0 5 and PO 6 data bits in the PO Data Register Regardless of whether either pin is used as a TIO or GPIO pin the Int Enable Int act Low TTL Threshold Open Drain and Pull Up Enable control the beh
21. bbbbbbbb 00000000 Interval Timer Timer DC INT CLR2 Reserved Reserved GPIO Port GPIO Port 2 PS 2 Data INT2 16 bit TCAP1 bbbbbbb 00000000 3 Low Counter Wrap DE INT MSK3 ENSWINT Reserved b 00000000 DF INT_MSK2_ Reserved Reserved GPIO Port GPIO Port 2 PS 2 Data INT2 16 bit 1 bbbbbbb 00000000 3 Int Enable Low Int Int Enable Counter Int Enable Int Enable Enable Wrap Int Enable E1 INT_MSK1 TCAPO Prog 1 ms USB Active USB Reset USBEP2 USB EP1 USB bbbbbbbb 00000000 Int Enable Interval Timer Int Enable Int Enable Int Enable Int Enable Int Enable Timer Int Enable Int Enable EO INT MSKO GPIOPort Sleep INT1 GPIO PortO SPI SPI Transmit INTO POR LVD bbbbbbbb 00000000 1 Timer Int Enable Int Enable Receive Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Document 38 08035 Rev K Page 65 of 83 Feedback 55 PERFORM CY7C63310 CY7C638xx 24 Register Summary continued The bit in the CPU Flags Register must be set to access the extended register space for all registers above OxFF Addr Name 7 6 5 4 3 2 1 0 R W Default E2 INT VC Pending Interrupt 7 0 bbbbbbbb 00000000 E3 RESWDT Reset Watchdog Timer 7 0 WWWWWWWW 00000000 A Temporary Register 1 7 0 00000000 CPU X X 7 0 00000000 CPU_PCL Prog
22. pins are controlled by writing to the D and D bits Table 14 3 P2 Data Register P2DATA 0x02 R W Bit 7 6 5 4 3 2 1 0 Field Reserved P2 1 P2 0 Read Write R W R W Default 0 0 0 0 0 0 0 0 This register contains the data for Port 2 Writing to this register sets the bit values to output on output enabled pins Reading from this register returns the current state of the Port 2 pins Bit 7 2 Reserved Data 7 2 Bit 1 0 P2 Data 1 0 2 1 2 0 only exist the CY7C638 2 3 3 Table 14 4 P3 Data Register P3DATA 0x03 R W Bit 7 6 5 4 3 2 1 0 Field Reserved P3 1 P3 0 Read Write R W R W Default 0 0 0 0 0 0 0 0 This register contains the data for Port 3 Writing to this register sets the bit values to be output on output enabled pins Reading from this register returns the current state of the Port 3 pins Bit 7 2 Reserved Data 7 2 Bit 1 0 P3 Data 1 0 P3 1 P3 0 only exist in the CY7C638 2 3 3 Document 38 08035 Rev K Page 34 of 83 Feedback IL gt I E CYPRESS PERFORM 14 2 GPIO Port Configuration All the GPIO configuration registers have common configuration controls The following are the bit definitions of the GPIO configuration registers 14 2 1 Int Enable When set the Int Enable bit allows the GPIO to generate interrupts Interrupt generate can occur regard
23. the end of an event then calculating the difference between the two values The two 8 bit capture timer registers save a programmable 8 bit range of the free running timer when a GPIO edge occurs on the two capture pins 5 P0 6 The two 8 bit captures may be ganged into a single 16 bit capture The enCoRe includes an integrated USB serial interface engine SIE that allows the chip to easily interface to a USB host The hardware supports one USB device address with three endpoints The USB D and D pins are optionally used as PS 2 SCLK and SDATA signals so that products are designed to respond to either USB or PS 2 modes of operation The PS 2 operation is supported with internal 5 KO pull up resistors on P1 0 D and P1 1 D and an interrupt to signal the start of PS 2 activity In USB mode the integrated 1 5 pull up resistor on D may be controlled under firmware No external components are necessary for dual USB and PS 2 systems and no GPIO pins need to be dedicated to switching between modes The enCoRe II supports in system programming by using the D and D pins as the serial programming mode interface The programming protocol is not USB 4 Conventions In this data sheet bit positions in the registers are shaded to indicate which members of the enCoRe family implement the bits Available in all enCoRe II family members CY7C638 1 2 3 3 only Page 3 of 83 Feedback C
24. 0 LVD and POR detection circuit to be continuously enabled during sleep This results in a faster response to an LVD or POR Bit 7 6 Reserved event during sleep at the expense of a slightly higher than average sleep current 0 The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle 1 The Sleep Duty Cycle value is overridden The LVD and POR detection circuit is always enabled Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep 1 0 bits below 0 Bit 5 Buzz During sleep the Sleep bit is set in the CPU_SCR Register Table 11 1 on page 27 the LVD and POR detection circuit is turned on periodically to detect any POR and LVD events on the pin the Sleep Duty Cycle bits in the ECO_TR are used to control the duty cycle Table 13 3 on page 32 To facilitate the detection of POR and LVD events the No Buzz bit is used to force the Bit 4 3 Sleep Timer 1 0 Note Sleep intervals are approximate Bit 2 0 CPU Speed 2 0 enCoRe may operate over a range of CPU clock speeds The reset value for the CPU Speed bits is zero as a result the default CPU speed is one eighth of the internal 24 MHz or 3 MHz External Clock Regardless of the CPU Speed bit s setting if the actual CPU speed is greater than 12 MHz the 24 MHz operating requirements Clock In 8 CPU when Internal Clock In 4 apply An example of this scenario
25. 12 17 19 27 28 29 30 31 16 16 15 12 17 11 15 Vcc Supply 13 13 12 9 14 8 12 Vss Ground 6 CPU Architecture This family of microcontrollers is based on a high performance 8 bit Harvard architecture microprocessor Five registers control the primary operation of the CPU core These registers are affected by various instructions but are not directly accessible through the register space by the user Table 6 1 CPU Registers and Register Names CPU Register Register Name Flags CPU F Program Counter CPU PC Accumulator CPU A Stack Pointer CPU SP Index CPU X The 16 bit Program Counter Register CPU PC allows direct addressing of the full 8 Kbytes of program memory space The Accumulator Register CPU A is the general purpose register which holds the results of instructions that specify any of the source addressing modes The Index Register CPU X holds an offset value that is used in the indexed addressing modes Typically this is used to address a block of data within the data memory space Document 38 08035 Rev K The Stack Pointer Register CPU SP holds the address of the current top of the stack in the data memory space It is affected by the PUSH POP LCALL CALL RETI and RET inst
26. 4 3 Field Pending Interrupt 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 The Interrupt Vector Clear Register holds the interrupt vector for the highest priority pending interrupt when read and when written clears all pending interrupts 8 bit data value holds the interrupt vector for the highest priority pending interrupt Writing to this register clears all pending interrupts Bit 7 0 Pending Interrupt 7 0 Document 38 08035 Rev K Page 55 of 83 Feedback SESJ Cypress CY7C63310 CY7C638xx PERFORM 18 Regulator Output 18 1 VREG Control Table 18 1 VREG Control Register VREGCR 0x73 R W Bit 4 7 6 1 0 Bit 7 2 Reserved Bit 1 Keep Alive Keep Alive when set allows the voltage regulator to source up to 20 pA of current when the voltage regulator is disabled P12CR 0 P12CR 7 must be cleared 0 Disabled 1 Enabled Bit 0 VREG Enable This bit turns on the 3 3V voltage regulator The voltage regulator only functions within specifications when is above 4 35V This block must not be enabled when Vec is below 4 35V although no damage or irregularities occur if it is enabled below 4 35V 0 Disable the 3 3V voltage regulator output on the VREG P1 2 pin 1 Enable the 3 3V voltage regulator output on the VREG P1 2 pin GPIO functionality of P1 2 is disabled Note Use of the alternate drive on pins 1 3 1 6 requires that the VREG Enable bit be set
27. 7 is added to the immediate value of 5 and the result is placed in the memory location at address 7 The immediate value of 6 is moved into the register space location at address 8 8 6 7 2 7 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within the RAM memory space or the register space Operand 1 is added to the X register to form the address of the result The source of the instruction is Operand 2 which is an immediate value Arithmetic instructions require two sources the second source is the location specified by Operand 1 added with the X register Instructions using this addressing mode are three bytes in length Table 7 13 Destination Indexed Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Index Immediate Value Examples ADD X 7 5 The value in the memory location at address X 7 is added with the immediate value of 5 and the result is placed in the memory location at address X 7 REG X 8 6 The immediate value of 6 is moved into the location in the register space at address X 8 7 2 8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory Operand 1 is the address of the result Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction This addr
28. Bit 1 16 bit Counter Wrap Interrupt Enable 1 Unmask INT2 interrupt Page 53 of 83 0 Mask 16 bit Counter Wrap interrupt 1 Unmask 16 bit Counter Wrap interrupt Feedback Bit 0 TCAP1 Interrupt Enable 0 Mask interrupt 1 Unmask 1 interrupt Document 38 08035 Rev K E Z CYPRESS CY7C63310 CY7C638xx C PERFORM Table 17 7 Interrupt Mask 1 INT MSK1 0xE1 R W Bit 7 6 5 4 3 2 1 0 Prog Interval 1 ms Timer USB Active USB Reset USB EP2 USB EP1 USB EPO Int Enable Timer Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 Bit 7 TCAPO Interrupt Enable 0 Mask interrupt 1 Unmask TCAPO interrupt Bit 6 Prog Interval Timer Interrupt Enable 0 Mask Prog Interval Timer interrupt 1 Unmask Prog Interval Timer interrupt Bit 5 1 ms Timer Interrupt Enable 0 Mask 1 ms interrupt 1 Unmask 1 ms interrupt Bit 4 USB Active Interrupt Enable 0 Mask USB Active interrupt 1 Unmask USB Active interrupt Bit 3 USB Reset Interrupt Enable 0 Mask USB Reset interrupt 1 Unmask USB Reset interrupt Bit 2 USB EP2 Interrupt Enable 0 Mask EP2 interrupt 1 Unmask 2 interrupt Bit 1 USB EP1 Interrupt Enable 0 Mask interrupt 1 Unmask interrupt Bit 0 USB EPO Interrupt Enab
29. CLKIN Configuration POOCR 0x05 R W Bit 7 6 5 4 3 2 0 Field Reserved Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This is shared between the P0 0 GPIO use and the CLKIN pin for an external clock When the external clock input is enabled Bit 0 in register CPUCLKCR Table 10 3 on page 22 the settings of this register are ignored The use of the pin as the P0 0 GPIO is available in all the enCoRe II parts Table 14 6 P0 1 CLKOUT Configuration PO1CR 0x06 R W Bit 7 6 5 4 3 2 1 0 Field CLK Output Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull Up Enable Output Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This is shared between the 1 GPIO use the CLKOUT When CLK output is set the internally selected clock is sent out onto pin The use of the pin as the 1 GPIO is available in all the enCoRe II parts 1 The clock selected by the CLK Select field Bit 1 0 of the CLKIOCR Register Table 10 7 on page 26 is driven out to the pin 1 Bit 7 CLK Output 0 The clock output is disabled Document 38 08035 Rev
30. CPOL 1 125 ns SPI Clock Low Time Low for CPOL 0 High for CPOL 1 125 ns Master Data Output 101 SCK to data valid 25 50 ns MasterData Output Time Time before leading SCK edge 100 Tn First bit with CPHA 0 Master Input Data Setup time 50 ns Master Input Data Hold time 50 ns Tssu Slave Input Data Setup Time 50 ns Tsup Slave Input Data Hold Time 50 ns Tspo Slave Data Output Time SCK to data valid 100 ns 1 Slave Data Output Time Time after SS LOW to data valid 100 ns First bit with CPHA 0 Tsss Slave Select Setup Time Before first SCK edge 150 ns TssH Slave Select Hold Time After last SCK edge 150 ns Note 10 In Master mode first bit is available 0 5 SPICLK cycle before Master clock edge available on the SCLK pin Document 38 08035 Rev K Page 70 of 83 Feedback CYPRESS CY7C63310 CY7C638xx Figure 28 1 Clock Timing 4 gt Tcu CLOCK 9 Figure 28 2 GPIO Timing Diagram 9096 GPIO Pin Output Voltage 10 l l l l l l l l l l l l l l l TA e x Figure 28 3 USB Data Signal Timing Figure 28 4 Receiver Jitter Tolerance gt Differential Data Lines Tur Turi Ture Consecutive Transitions Tperion Tan Paired Transitions Tperion Ture
31. CY7C638xx ILC Ux CYPRESS PERFORM Figure 31 3 18 Pin 300 Mil Molded DIP P3 DIMENSIONS IN INCHES MIN MAX 9 a gp pep p pp PART P18 3 STANDARD PKG 0 240 218 3 LEAD FREE PKG 0 270 281 0 030 0 060 0 870 0 920 SEATING PLANE 0 300 CUR gm 0140 0 120 0 190 0 140 gt 0 008 0 115 0 160 0 015 0 012 77 EN TT 0 060 oL 0 055 0 310 m TNNT gt 51 85010 B Figure 31 4 18 Pin 300 Mil Molded SOIC S3 110 di 1 MIN MAX LL 11 0 291 7 391 0 30017 620 HHHH DIMENSIONS IN INCHES MM REFERENCE JEDEC MO 119 10 007 0 394 10 642 0 419 10 18 La 00260660 0 03210 8121 0 447111 3531 SEATING PLANE 0 463 11 760 1 0 09212 336 o10p667 Ud j Hob f a C 00040101 L 00091002311 0 004 0 101 0 015 0381 0 0125 0 317 0 011810 299 0 050 1 270 51 85023 B 0 013 0 330 0 019 0 482 0 050 1 270 TYP Document 38 08035 Rev K Page 77 of 83 Feedback F
32. Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 1 0 This register exists CY7C638 2 3 3 This register controls the operation of pins 0 1 The SPI Master Slave Interface core logic runs on the SPI clock domain so that its functionality is independent of system clock speed 15 1 SPI Data Register Table 15 1 SPI Data Register SPIDATA 0x3C R W Bit 7 6 5 4 3 2 1 0 Field SPIData 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 When read this register returns the contents of the receive buffer When written it loads the transmit holding register Bit 7 0 SPI Data 7 0 meet this timing requirement results in incorrect data transfer Document 38 08035 Rev K When an interrupt occurs to indicate to the firmware that a byte of receive data is available or the transmitter holding register is empty the firmware has 7 SPI clocks to manage the buffers to empty the receiver buffer or to refill the transmit holding register Failure to Page 40 of 83 Feedback F CYPRESS CY7C63310 CY7C638xx PERFORM 15 2 SPI Configure Register Table 15 2 SPI Configure Register SPICR 0x3D R W Bit 7 6 5 4 3 2 1 0 Field Swap LSB First Comm Mode CPOL CPHA SCLK Select Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 Swap 0 Swap function disabled 1 Th
33. High to low edge 3 10 Vec Model ViLTTL Input Low Voltage TTL Modell pin Supply 4 0 5 5V 0 8 V Input High Voltage TTL Model IO pin Supply 4 0 5 5V 2 0 V Voltage High Drive lg4250m A _ VoL2 Output Low Voltage High Drivel loL1 25 mA 0 4 V Output Low Voltage Low Drivel 2 8 mA 0 4 V Output High Voltage lg 2mMA Vcc 05f V oAD Maximum Load Capacitance 50 pF 28 AC Characteristics Parameter Description Conditions Min Typical Unit Clock X External Clock Duty Cycle 45 55 TECLK1 External Clock Frequency External clock is the source of the 0 187 24 MHz CPUCLK External Clock Frequency External clock is not the source of the 0 24 MHz CPUCLK 1 Internal Main Oscillator Frequency No USB present 22 8 25 2 MHz Fimo2 Internal Main Oscillator Frequency With USB present 23 64 24 3 MHz FiLo4 Internal Low Power Oscillator Normal mode 29 44 37 12 kHz FiLo2 Internal Low Power Oscillator Low power mode 35 84 47 36 kHz 3 3V Regulator VorIP Output Ripple Voltage 10 Hz to 100 MHz at CLOAD 1 uF 200 Notes 7 Available only in CY7C638xx P1 3 P1 4 1 5 P1 6 1 7 8 Except for pins P1 0 and P1 1 in the GPIO mode 9 Except for pins P1 0 and P1 1 Document 38 08035 Rev K Page 69 of 83 Cypress CY7C63310 CY7C638xx PERFORM 28 AC Characteristics co
34. Interval Timer 7 0 Bit 7 Field Read Write Default Bit 7 0 Prog Interval Timer 7 0 This register holds the low order byte of the 12 bit programmable interval timer Reading this register causes the high order byte to be moved into a holding register allowing an automatic read of all 12 bits simultaneously Page 44 of 83 Document 38 08035 Rev K Feedback CY7C63310 CY7C638xx SS 5 W CYPRESS PERFORM Table 16 8 Programmable Interval Timer High PITMRH 0x27 R Bit 7 6 5 4 3 2 1 0 Field Reserved Prog Interval Timer 11 8 Read Write R R R R Default 0 0 0 0 0 0 0 0 Bit 7 4 Reserved Bit 3 0 Prog Internal Timer 11 8 This register holds the high order nibble of the 12 bit programmable interval timer Reading this register returns the high order nibble of the 12 bit timer at the instant that the low order byte was last read Table 16 9 Programmable Interval Reload Low PIRL 0x28 R W Bit 7 6 5 4 3 2 1 0 Field Prog Interval 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Prog Interval 7 0 This register holds the lower 8 bits of the timer When writing into the 12 bit reload register write the lower byte first then the higher nibble Table 16 10 Programmable Interval Re
35. R W R W Default 0 0 0 0 0 0 0 0 This register controls the operation of the 1 0 D when the USB interface is not enabled allowing the pin to be used as a PS2 interface or a GPIO See Table 21 1 on page 58 for information on enabling the USB When the USB is enabled none of the controls in this register have any affect on the 1 0 pin Note The P1 0 is an open drain only output It can actively drive a signal low but cannot actively drive a signal high Bit 1 PS 2 Pull up Enable 0 Disable the 5K ohm pull up resistors 1 Enable 5K ohm pull up resistors for both P1 0 and P1 1 Enable the use of the P1 0 D and P1 1 0 pins as a PS2 style interface Table 14 11 P1 1 D Configuration P11CR 0x0E R W E This register controls the operation of the P1 1 D pin when the USB interface is not enabled allowing the to be used as a PS2 interface or a GPIO See Table 21 1 on page 58 for information on enabling USB When USB is enabled none of the controls in this register have any affect on the P1 1 pin When USB is disabled the 5K ohm pull up resistor on this pin may be enabled by the PS 2 Pull Up Enable bit of the P10CR Register Table 14 10 Note There is no 2 mA sourcing capability on this pin The pin can only sink 5 mA at Vo 5 See section DC Characteristics on page 68 Table 14 12 P1 2 Configuration P
36. Up Enable control the behavior of the pin Table 14 14 1 4 1 6 Configuration 14 16 0x11 0x13 R W Bit 7 6 5 4 3 2 1 0 Field SPI Use Int Enable Int Act Low 3 3V Drive High Sink Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 These registers control the operation of pins P1 4 P 1 6 respectively These registers exist all enCoRe II parts Bit 7 SPI Use 0 Disable the SPI alternate function The pin is used as a GPIO 1 Enable the SPI function The SPI circuitry controls the output of the pin The 1 4 1 6 GPIO s threshold is always set to TTL When the SPI hardware is enabled pins that are configured as SPI Use have their output enable and output state controlled by the SPI circuitry When the SPI hardware is disabled or a pin has its SPI Use bit clear the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable Int act Low 3 3V Drive High Sink Open Drain and Pull up Enable control the behavior of the pin Note for Comm Modes 01 or 10 SPI Master or SPI Slave see Table 15 2 on page 41 When configured for SPI SPI Use 1 and Comm Modes 1 0 SPI Master or SPI Slave mode the input and output direction of pins P1 5 and P1 6 is set automatically by the SPI logic However pin P1 4
37. function expects very few variables in the parameter block to be set before calling the function The parameter block values that must be set besides the keys are the CLOCK and DELAY values Page 16 of 83 Feedback Table 9 8 ProtectBlock Parameters Name Address Description KEY1 0 F8h 3Ah KEY2 0 F9h Stack Pointer value when SSC is executed CLOCK 0 FCh Clock divider used to set the write pulse width DELAY 0 FEh For a CPU speed of 12 MHz set to 56h 9 5 6 EraseAll Function The EraseAll function performs a series of steps that destroy the user data in the Flash macros and resets the protection block in each Flash macro to all zeros the unprotected state The EraseAll function does not affect the three hidden blocks above the protection block in each Flash macro The first of these four hidden blocks is used to store the protection table for its eight Kbytes of user data The EraseAll function begins by erasing the user space of the Flash macro with the highest address range A bulk program of all zeros is then performed on the same Flash macro to destroy all traces of the previous contents The bulk program is followed by a second erase that leaves the Flash macro in a state ready for writing The erase program erase sequence is then performed on the next lowest Flash macro in the address space if it exists After the erase of the user space the protection block for the Flash macro
38. in the Byte Count Bit 3 0 of the Endpoint Count Register Table 21 2 in response to any IN token 23 Details of Mode for Differing Traffic Conditions Control Endpoint SIE Bus Event SIE EPO Mode Register EPO Count Register EPO Interrupt Comments Mode Token Count 00 1 Response I MODE DVAL COUNT FIFO DISABLED 0000 x x x x Ignore All STALL_IN_OUT 0011 SETUP gt 10 x x junk Ignore 0011 lt 10 invalid x junk Ignore 0011 SETUP lt 10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP 0011 IN x x x STALL Stall IN 0011 OUT gt 10 x x Ignore 0011 OUT lt 10 invalid x Ignore 0011 OUT lt 10 valid x STALL Stall OUT NAK_IN_OUT 0001 SETUP gt 10 x x junk Ignore 0001 lt 10 invalid x junk Ignore 0001 SETUP lt 10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP 0001 IN x x x NAK NAK IN 0001 OUT gt 10 x x Ignore 0001 OUT lt 10 invalid x Ignore 0001 OUT lt 10 valid x NAK NAK OUT ACK_IN_STATUS_OUT 1111 SETUP gt 10 x x junk Ignore 1111 SETUP lt 10 invalid x junk Ignore 1111 SETUP lt 10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP 1111 IN x x x TX Host Not ACK d 1111 IN x x x TX 1 1 0001 Yes Host ACK d 1111 OUT gt 10 x x Ig
39. individually On CY7C638xx CY7C63310 external clock input when configured as Clock In 6 8 8 7 12 6 10 1 GPIO Port 0 bit 1 Configured individually On CY7C638xx and CY7C63310 clock output when configured as Clock Out 5 7 7 6 11 5 9 PO 2 INTO GPIO Port 0 bit 2 Configured individually Optional rising edge interrupt INTO 4 6 6 5 10 4 8 PO 3 INT1 GPIO Port 0 bit Configured individually Optional rising edge interrupt INT1 3 5 5 4 9 3 7 PO 4 INT2 GPIO Port 0 bit 4 Configured individually Optional rising edge interrupt INT2 Note 1 P1 0 D and P1 1 D pins must be in IO mode when used as GPIO and in 1 mode Document 38 08035 Rev K Page 6 of 83 Feedback gt Ed lt CYPRESS PERFORM Table 5 2 Pin Description continued CY7C63310 CY7C638xx GFN soic sioc soic PDip Description 2 4 4 3 8 2 6 P0 5 TIOO GPIO Port 0 bit 5 Configured individually Alternate function Timer capture inputs or Timer output TIOO 1 3 3 2 7 1 5 PO 6 TIO1 GPIO Port 0 bit 6 Configured individually Alternate function Timer capture inputs or Timer output TIO1 32 2 2 1 6 0 7 GPIO Port 0 bit 7 Configured individually Not present in the 16 pin PDIP or SOIC package 10 1 1 11 12 24
40. is a device that is configured to use an external clock which supplies a frequency of 20 MHz If the CPU speed register s value is 05011 the CPU clock is at 20 MHz Therefore the supply voltage requirements for the device are the same as if the part were operating at 24 MHz The operating voltage requirements are not relaxed until the CPU speed Clock In 2 is at 12 MHz or less Oscillator is selected CPU Speed 2 0 000 3 MHz Default 6 MHz Clock In 1 Clock In 16 Clock In 32 010 12 MHz Clock In 128 Reserved 011 100 750 kHz 101 110 111 Page 23 of 83 Feedback 001 24 MHz 1 5 MHz Note Correct USB operations require the CPU clock speed be at least 1 5 MHz or not less than USB clock 8 If the two clocks have the same source then the CPU clock divider must not be set to divide by more than 8 If the two clocks have different 187 kHz sources the maximum ratio of USB Clock CPU Clock must never exceed 8 across the full specification range of both clock Reserved sources Note This register exists in the second bank of IO space This requires setting the bit in the CPU flags register Document 38 08035 Rev K CYPRESS CY7C63310 CY7C638xx PERFORM Table 10 5 USB Osclock Clock Configuration OSCLCKCR 0x39 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Fine Tune Only USB Osclock Disable Read Write R W R W Default 0 0 0
41. major circuit blocks The Flash memory module the internal 24 MHz oscillator the EFTB filter and the bandgap voltage reference These circuits transition into a zero power state The only operational circuits on chip are the Low Power oscillator the bandgap refresh circuit and the supply voltage monitor POR LVD circuit Figure 12 1 Sleep Timing Firmware write to SCR SLEEP bit causes an immediate BRQ edge CPUCLK CPU captures BRQ on next CPUCLK On the falling edge of CPUCLK CPU responds with PD is asserted The 24 48 MHz a BRA system clock is halted the Flash and bandgap are powered down 1 md IOW SLEEP BRQ BRA PD 12 2 Wake up Sequence Once asleep the only event that can wake the system up is an interrupt The global interrupt enable of the CPU flag register is not required to be set Any unmasked interrupt wakes the system up It is optional for the CPU to actually take the interrupt after the wake up sequence The wake up sequence is synchronized to the 32 kHz clock for purposes of sequencing a startup delay to allow the Flash memory module enough time to power up before the CPU asserts the first read access Another reason for the delay is to allow the oscillator Bandgap and LVD POR circuits time to settle before actually being used in the system As shown in Figure 12 2 on page 30 the wake up sequence is as follows 1 The wake up interrupt occu
42. of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code ex
43. only partially stored that is between the two writes ofthe 12 bit value The programmable interval timer generates an interrupt to the CPU on each reload The parameters to be set show up on the device editor view of PSoC Designer when the enCoRe Timer User Module is placed parameters are Source PITIMER Divider The PITIMER Source is the clock to the timer and the PITMER Divider is the value the clock is divided by CY7C63310 CY7C638xx The interval register PITMR holds the value that is loaded into the PIT counter on terminal count The PIT counter is a down counter The Programmable Interval Timer resolution is configurable For example TCAPCLK divide by x of CPU clock for example TCAPCLK divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz ITMRCLK divide by x of TCAPCLK for example ITMRCLK divide by 3 of TCAPCLK is 4 MHz so resolution is 0 25 us 10 1 2 Timer Capture Clock TCAPCLK The Timer Capture clock is sourced from an external clock Internal 24 MHz Oscillator or the Internal 32 kHz Low power Oscillator A programmable pre scaler of 2 4 6 or 8 then divides the selected source Figure 10 2 Programmable Interval Timer Block Diagram Configuration Status and Control Document 38 08035 Rev K 12 bit down reload 12 bit reload counter Interrupt counter Controller Page 25 of 83 Feedback R
44. set from 0 to 1 in the CPU 32 kHz cycles 3 The GPIO interrupts are edge triggered 17 4 Interrupt Latency The time between the assertion of an enabled interrupt and the start of its ISR is calculated from the following equation Latency Time for current instruction to finish Time for internal 2 The current executing instruction finishes 3 The internal interrupt is dispatched taking 13 cycles During interrupt routine to execute Time for LJMP instruction in Flag register this time the following actions occur the MSB and LSB of Program Counter and Flag registers CPU_PC and CPU_F are stored onto the program stack by an automatic CALL interrupt table to execute For example if the 5 cycle JMP instruction is executing when an instruction 13 cycles generated during the interrupt a The PCH PCL and Flag register CPU_F are stored onto the program stack in that order by an automatic CALL interrupt becomes active the total number of CPU clock cycles acknowledge process instruction 13 cycles generated during the interrupt b The CPU_F register is then cleared Because this clears the before the ISR begins is as follows 1 to 5 cycles for JMP to finish 13 cycles for interrupt routine Feedback acknowledge process GIE bit to 0 additional interrupts are temporarily disabled c The PCH PC 15 8 is cleared to zero d The interrupt vector is read from the interrupt controller and its value placed into P
45. signalling purposes and to provide for the 1 5K D pull up Unlike the other 3 3V regulator this regulator cannot be controlled or accessed by firmware When the device is suspended this regulator is disabled along with the bandgap which provides the reference voltage to the regulator and the D line is pulled up to 5V through an alternate 6 5K resistor During wake up following a suspend the band gap and the regulator are Switched on in any order Under an extremely rare case when the device wakes up following a bus reset condition and the volt age regulator and the band gap turn on in that particular order there is possibility of a glitch or low pulse occurring on the D line The host can misinterpret this as a deattach condition This condition although rare is avoided by keeping the bandgap circuitry enabled during sleep This is achieved by setting the No Buzz bit bit 5 in the register This is an issue only if the device is put to sleep during a bus reset condition 20 USB Serial Interface Engine SIE Firmware is required to handle the rest of the USB interface with the following tasks The SIE allows the microcontroller to communicate with the USB host at low speed data rates 1 5 Mbps The SIE simplifies the enumeration Dy decoding USB gevice requests interface between the microcontroller and the USB by incorpo m Fill and empty the FIFOs rating hardware that handles the following USB bus activity inde
46. to enable the regulator and provide the alternate voltage Page 56 of 83 Document 38 08035 Rev K Feedback CYPRESS CY7C63310 CY7C638xx PERFORM 19 USB PS2 Transceiver Although the USB transceiver has features to assist in interfacing to PS 2 these features are not controlled using these registers The registers only control the USB interfacing features PS 2 interfacing options are controlled by the D and D GPIO Configuration register See Table 14 2 on page 34 19 1 USB Transceiver Configuration Table 19 1 USB Transceiver Configure Register USBXCR 0x74 R W Bit 7 6 5 4 3 2 1 0 Field USB Pull up Reserved USB Force State Enable Read Write R W ES e R W Default 0 0 0 0 0 0 0 0 Bit 7 USB Pull up Enable 0 Disable the pull up resistor on D 1 Enable the pull up resistor on D This pull up is to Vcc if the PHY s internal voltage regulator is not enabled or to the internally generated 3 3V when VREG is enabled Bit 6 1 Reserved Bit 0 USB Force State This bit allows the state of the USB IO pins D and D to be forced to a state when USB is enabled 0 Disable USB Force State 1 Enable USB Force State Allows the D and D pins to be controlled by P1 1 and P1 0 respectively when the USBIO is in USB mode Refer to Table 14 2 on page 34 for more information Note The USB transceiver has a dedicated 3 3V regulator for USB
47. 0 0 Bit 7 0 Free running Timer 15 8 When reading the Free running Timer the low order byte must be read first and the high order second When writing the low order byte must be written first then the high order byte Page 43 of 83 Document 38 08035 Rev K Feedback CY7C63310 CY7C638xx Cypress PERFORM Table 16 3 Timer Capture 0 Rising TIOOR 0x22 R W Bit 7 6 5 4 3 2 1 0 Field Capture 0 Rising 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Capture 0 Rising 7 0 This register holds the value of the Free running Timer when the last rising edge occurred on the TIOO input When Capture 0 is in 8 bit mode the bits that are stored here are selected by the Prescale 2 0 bits in the Timer Configuration register When Capture 0 is in 16 bit mode this register holds the lower order 8 bits of the 16 bit timer Table 16 4 Timer Capture 1 Rising TIO1R 0x23 R W Bit 7 6 5 4 3 2 1 0 Field Capture 1 Rising 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Capture 1 Rising 7 0 This register holds the value of the Free running Timer when the last rising edge occurred on the TIO1 input in the 8 bit mode The bits that are stored here are selected by the Prescale 2 0 bits in the Timer Configuration
48. 0 0 0 0 0 This register is used to trim the Internal 24 MHz Oscillator using received low speed USB packets as a timing reference The USB Osclock circuit is active when the Internal 24 MHz Oscillator provides the USB clock Bit 7 2 Reserved Bit 1 Fine Tune Only 0 Fine and Course tuning 1 Disable the oscillator lock from performing the coarse tune portion of its retuning The oscillator lock must be allowed to perform a coarse tuning to tune the oscillator for correct USB SIE operation After the oscillator is properly tuned this bit is set to reduce variance in the internal oscillator frequency that would be caused course tuning Bit 0 USB Osclock Disable 0 Enable With the presence of USB traffic the Internal 24 MHz Oscillator precisely tunes to 24 MHz 1 5 1 Disable The Internal 24 MHz Oscillator is not trimmed based on USB packets This setting is useful when the internal oscillator is not sourcing the USBSIE clock Table 10 6 Timer Clock Config TMRCLKCR 0x31 R W Bit 7 6 5 4 3 2 1 0 Field TCAPCLK Divider TCAPCLK Select ITMRCLK Divider ITMRCLK Select Read Write R W R W R W R W R W R W R W R W Default 1 0 0 0 1 1 1 1 Bit 7 6 TCAPCLK Divider 1 0 TCAPCLK Divider controls the TCAPCLK divisor 0 0 Divider Value 2 0 1 Divider Value 4 1 0 Divider Value 6 1 1 Divider Value 8 Bit 5 4 TCAPCLK Select The TCAPCLK Select f
49. 1 FBh pointer to data buffer SSC CLOCK blk 1 FCh Clock SSC_MODE blk 1 FDh ClockW ClockE multiplier SSC_DELAY blk 1 FEh flash macro sequence delay count SSC WRITE ResultCode blk 1 FFh temporary result code _main mov A 0 mov SSC BLOCKID To read from Table 0 Silicon ID is stored in Table 0 Call SROM operation to read the SROM table mov X SP copy SP into X mov A X A temp stored in X add A 3 create 3 byte stack frame 2 pushed mov 55 KEY2 save stack frame for supervisory code load the supervisory code for flash operations mov SSC KEY1 3Ah FLASH_OPER_KEY 3Ah mov A 6 load A with specific operation 06h is the code for Table read Table 9 1 55 SSC call the supervisory ROM At the end of the SSC command the silicon ID is stored in F8 MSB and F9 LSB of the SRAM terminate jmp terminate Document 38 08035 Rev K Page 18 of 83 Feedback E CYPRESS 9 5 8 Checksum Function The Checksum function calculates a 16 bit checksum over a user specifiable number of blocks within a single Flash macro Bank starting from block zero The BLOCKID parameter is used to pass in the number of blocks to calculate the checksum over A BLOCKID value of 1 calculates the checksum of only block 0 while a BLOCKID value of 0 calculates the checksum of all 256 user blocks The 16 bit checksum is returned in KEY1 and KEY2 The parameter KEY1 holds the lower eight b
50. 1 USB D T If this pin is used as General Purpose output it draws current This pin must be configured as an input to reduce current draw 18 17 16 13 18 12 16 P1 2 VREG GPIO Port 1 bit 2 Configured individually 3 3V if regulator is enabled The 3 3V regulator is not available in the CY7C63310 and CY7C63801 A 1 uF min 2 uF max capacitor is required Vreg output 20 18 17 14 1 13 1 P1 3 SSEL GPIO Port 1 bit 3 Configured individually Alternate function is SSEL signal of the SPI bus TTL voltage thresholds Although Vreg is not available with the CY7C63310 3 3V IO is still available 23 21 20 15 2 14 2 P1 4 SCLK GPIO Port 1 bit 4 Configured individually Alternate function is SCLK signal of the SPI bus TTL voltage thresholds Although Vreg is not available with the CY7C63310 3 3V IO is still available 24 22 21 16 3 15 3 P1 5 5MOSI GPIO Port 1 bit 5 Configured individually Alternate function is SMOSI signal of the SPI bus TTL voltage thresholds Although Vreg is not available with the CY7C63310 3 3V IO is still available 25 23 22 17 4 16 4 1 6 5 GPIO Port 1 bit 6 Configured individually Alternate function is SMISO signal of the SPI bus TTL voltage thresholds Although Vreg is not available with the CY7C63310 3 3V IO is still available 26 24 23 18 5 P1 7 GPIO Port 1 bit 7 Configured individually TTL voltage threshold 7 9 9 8 13 7 11 P0 0 GPIO Port 0 bit 0 Configured
51. 1 must always have a value of 3Ah while KEY2 must have the same value as the stack pointer when the SROM function begins execution This would be the Stack Pointer value when the SSC opcode is executed plus three If either of the keys do not match the expected values the M8C halts with the exception of the SWBootReset function The following code puts the correct value in KEY1 and KEY2 The code starts with a halt to force the program to jump directly into the setup code and not run into it mov KEY1 3ah mov KEY2 A Table 9 2 SROM Function Parameters Variable Name SRAM Address Key1 Counter Return Code 0 F8h Key2 TMP 0 F9h BlockID 0 FAh Pointer 0 FBh Clock 0 FCh Mode 0 FDh Delay 0 FEh PCL 0 FFh 9 4 1 Return Codes The SROM also features Return Codes and Lockouts Return codes aid in the determination of the success or failure of a particular function The return code is stored in KEY 1 s position in the parameter block The CheckSum and TableRead functions do not have return codes because KEY1 s position in the parameter block is used to return other data Table 9 3 SROM Return Codes Return Code Description 00h Success 01h Function not allowed due to level of protection on block 02h Software reset without hardware reset 03h Fatal error SROM halted Read write and erase operations may fail if the target block is read or write prote
52. 1 update data Yes ACK SETUP 1011 IN x x x Host Not ACK d 1011 IN x x x 0011 Yes Host ACK d 1011 OUT 210 x x junk Ignore 1011 OUT lt 10 invalid x junk Ignore 1011 OUT lt 10 valid x ACK 111 0001 update 1 update data Yes Good OUT STATUS_IN 0110 SETUP gt 10 x x junk Ignore 0110 SETUP lt 10 invalid x junk Ignore 0110 SETUP lt 10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP 0110 IN x x x Host Not ACK d 0110 IN x x x 0011 Yes Host ACK d 0110 OUT 210 x x Ignore 0110 OUT lt 10 invalid x Ignore 0110 OUT lt 10 valid x STALL 0011 Yes Stall OUT Data Out Endpoints ACK OUT STALL Bit 0 1001 IN x x x Ignore 1001 OUT gt MAX x x junk Ignore 1001 OUT lt MAX invalid invalid junk Ignore 1001 OUT lt MAX valid valid ACK 1 1000 update 1 update data Yes ACK OUT ACK OUT STALL Bit 1 1001 IN x x x Ignore 1001 OUT gt MAX x x Ignore 1001 OUT lt MAX invalid invalid Ignore 1001 OUT lt MAX valid valid STALL Stall OUT NAK OUT 1000 IN x x x Ignore 1000 OUT gt MAX x x Ignore 1000 OUT lt invalid invalid Ignore 1000 OUT lt MAX valid valid NAK If Enabled NAK OUT Data In Endpoints ACK IN STALL Bit 0 1101 OUT x x x Ignore 1101 IN x x x Host Not ACK d 1101 IN x x x TX 1 1100 Yes Host ACK d ACK IN STALL Bit 1 1101 OUT x x x Ignore Page 63 of 83 Feedback Document 38 08035 Rev K
53. 11 32 CLKIOCR Reserved Reserved CLKOUT Select bbbbb 00000000 34 IOSCTR foffset 2 0 Gain 4 0 bbbbbbbb 000ddddd 36 LPOSCTR 32 kHz Reserved 32 kHz Bias Trim 1 0 32 kHz Freq Trim 3 0 b bbbbbb dddddddd Low Power 39 OSCLCKCR Reserved Fine Tune USB bb 00000000 Only Osclock Disable 3c SPIDATA SPIData 7 0 bbbbbbbb 00000000 3D SPICR Swap LSB First Comm Mode CPOL CPHA SCLK Select bbbbbbbb 00000000 40 USBCR USB Device Address 6 0 bbbbbbbb 00000000 Enable 41 EPOCNT Data Data Valid Reserved Byte Count 3 0 bbbbbbbb 00000000 Toggle 42 EP1CNT Data Data Valid Reserved Byte Count 3 0 bbbbbbbb 00000000 Toggle 43 EP2CNT Data Data Valid Reserved Byte Count 3 0 bbbbbbbb 00000000 Toggle 44 EPOMODE Setup IN rev d OUT rcv d ACK d trans Mode 3 0 ccccbbbb 00000000 rcv d 45 EP1MODE Stall Reserved Int Ack d trans Mode 3 0 b bcbbbb 00000000 Enable 46 EP2MODE Stall Reserved Int Ack d trans Mode 3 0 b bcbbbb 00000000 Enable 50 57 EPODATA Endpoint 0 Data Buffer 7 0 bbbbbbbb 2727777 58 5F EP1DATA Endpoint 1 Data Buffer 7 0 bbbbbbbb 2222222 60 67 EP2DATA Endpoint 2 Data Buffer 7 0 bbbbbbbb 2772779 73 VREGCR Reserved Keep Alive VREG bb 00000000 Enable 74 USBXCR USB Pull Reserved USB Force b b 00000000 up Enable State DA INT CLRO GPIOPort Sleep INT1 GPIO Port SPI SPI Transmit INTO POR LVD bbbbbbbb 00000000 1 Timer 0 Receive DB INT_CLR1 TCAPO Prog 1 ms USB Active USB Reset USBEP2 USB EP1 USB
54. 12CR 0x0F R W Bit 7 6 5 4 3 2 1 0 Field CLK Output Int Enable Int Act Low TTL Threshold Reserved Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This register controls the operation of the 1 2 Bit 7 CLK Output 0 The internally selected clock is not sent out onto 1 2 pin 1 When CLK Output is set the internally selected clock is sent out onto P1 2 pin Note Table 10 7 Clock Config CLKIOCR 0x32 R W on page 26 is used to select the external or internal clock in enCoRe Il devices Document 38 08035 Rev K Page 38 of 83 Feedback SS 2 Em SEU CYPRESS CY7C63310 CY7C638xx PERFORM Table 14 13 P1 3 Configuration P13CR 0x10 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low 3 3V Drive High Sink Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This register controls the operation of the P1 3 pin This register exists in enCoRe II parts The P1 3 GPIO s threshold is always set to TTL When the SPI hardware is enabled or disabled the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable Int act Low 3 3V Drive High Sink Open Drain and Pull
55. 27 um x 2187 um 12 Bond pad opening 70 um x 70 um Die thickness 14 mils Table 5 1 Die Pad Summary Pad Number Pad Name X microns Y microns 1 0 7 742 730 911 990 2 P0 6 755 060 792 200 3 P0 5 755 060 699 300 4 P0 4 755 060 606 400 5 P0 3 755 060 430 080 6 P0 2 755 060 522 980 7 PO 1 755 060 618 830 8 P0 0 CLKIN 755 060 714 020 9 P2 1 755 060 810 220 10 P2 0 393 580 977 930 11 VSS 537 500 964 700 12 1 0 D 736 110 936 680 13 P1 1 D 736 110 625 130 14 VDD 736 110 260 670 15 P1 2 VREG 736 110 53 800 16 P1 3 723 510 336 780 17 P3 0 723 510 438 690 18 P3 1 723 510 532 880 19 P1 4 723 510 635 310 20 P1 5 SMOSI 723 510 728 220 21 P1 6 SMISO 723 510 839 290 22 P1 7 696 630 1008 480 23 Reserved 795 400 1023 270 Document 38 08035 Rev K Page 5 of 83 Feedback gt p P ca CAE CYPRESS CY7C63310 CY7C638xx PERFORM Table 5 2 Pin Description 32 24 24 18 18 16 16 5 SIOC PDIP Ppip Description 21 19 18 P3 0 GPIO Port 3 Configured as a group byte 22 20 19 P3 1 9 11 11 P2 0 GPIO Port 2 Configured as a group byte 8 10 10 P2 1 14 14 13 10 15 9 13 1 0 0 GPIO Port 1 bit 0 USB D l If this pin is used as a General Purpose output it draws current This pin must be configured as an input to reduce current draw 15 15 14 11 16 10 14 P1 1 D GPIO Port 1 bit
56. CL PC 7 0 This sets the program counter to point to the appropriate address in the interrupt table for example 0004h for the POR LVD interrupt 4 Program execution vectors to the interrupt table Typically a LJMP instruction in the interrupt table sends execution to the user s Interrupt Service Routine ISR for this interrupt 5 The ISR executes Note that interrupts are disabled because 7 cycles for LIMP 21 to 25 cycles In the previous example at 24 MHz 25 clock cycles take 1 042 us Page 51 of 83 GIE 0 In the ISR interrupts are re enabled by setting GIE 1 care must be taken to avoid stack overflow Document 38 08035 Rev K 17 5 Interrupt Registers The Interrupt Clear Registers INT_CLRx are used to enable the individual interrupt sources ability to clear posted interrupts When an INT_CLRx register is read any bits that are set indicates an interrupt has been posted for that hardware resource Therefore reading these registers gives the user the ability to determine all posted interrupts Table 17 2 Interrupt Clear 0 INT_CLRO OxDA R W Cee RA RES Field GPIO Port 1 Sleep Timer INT GPIO Port 0 SPI Receive SPI Transmit INTO POR LVD When reading this register 0 There is no posted interrupt for the corresponding hardware 1 7 Posted interrupt for the corresponding hardware present Writing a 0 to the bits clears the post
57. Default 0 0 0 0 0 0 0 0 This register controls the ratios in numbers of 32 kHz clock periods of on time versus off time for LVD and POR detection circuit Bit 7 6 Sleep Duty Cycle 1 0 0 0 1 128 periods of the Internal 32 kHz Low speed Oscillator 0 1 1 512 periods of the Internal 32 kHz Low speed Oscillator 1 0 1 32 periods of the Internal 32 kHz Low speed Oscillator 1 1 1 8 periods of the Internal 32 kHz Low speed Oscillator Note This register exists in the second bank of IO space This requires setting the XIO bit in the CPU flags register Document 38 08035 Rev K Page 32 of 83 Feedback Bit 7 7 Data 7 only exists in the CY7C638xx Bit 6 5 PO 6 P0 5 Data TIO1 and TIOO To configure the 4 0 2 pins refer to the PO 2 INTO P0 4 INT2 Configuration Register Table 14 7 on page 37 gt Cypress CY7C63310 CY7C638xx PERFORM 14 General Purpose IO GPIO Ports 14 1 Port Data Registers Table 14 1 Data Register PODATA 0x00 R W Bit 7 6 5 4 3 2 1 0 Field P0 7 PO 6 TIO1 P0 5 TIOO PO 4 INT2 P0 3 INT1 P0 2 INTO PO 4 CLKOUT PO O CLKIN Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This register contains the data for Port 0 Writing to this register sets the bit values to be output on output enabled pins Reading from this register returns the current stat
58. G2 Output Voltage Vec gt 4 35V 0 lt temp lt 40 C 3 15 3 45 V 1 mA lt lypec lt 25 mA 3 3 4 T 0 to 40 C Ci oAD Capacitive load on Vreg pin 1 2 Line Regulation 1 IV LDREG Load Regulation 0 04 USB Interface Von Static Output High 15K 5 Ohm to Vas 2 8 3 6 V Vorr Static Output Low Ryp is enabled 0 3 V Note 6 In Master mode first bit is available 0 5 SPICLK cycle before Master clock edge available on the SCLK pin Document 38 08035 Rev K Page 68 of 83 ee CYPRESS PERFORM 27 DC Characteristics continued CY7C63310 CY7C638xx Parameter Description Conditions Min Typical Max Unit General Differential Input Sensitivity 0 2 V Vom Differential Input Common Mode 0 8 2 5 V Range Vse Single Ended Receiver Threshold 0 8 2 V CiN Transceiver Capacitance 20 pF lio Hi Z State Data Line Leakage OV lt Vin lt 3 3V 10 10 PS 2 Interface Static Output Low SDATA or SCLK pins 0 4 V Rps2 Internal PS 2 Pull up Resistance SDATA SCLK pins PS 2 Enabled 3 7 KQ General Purpose Interface Pull Up Resistance 4 12 Input Threshold Voltage Low CMOS Low to High edge 40 65 Vec model l VicF Input Threshold Voltage Low CMOS High to Low edge 3096 5596 Vec model Vuc Input Voltage CMOS
59. Read Write Default 0 0 0 0 0 0 0 0 Bit 7 0 Stack Pointer 7 0 8 bit data value holds a pointer to the current top of the stack Table 7 5 CPU Program Counter High Register CPU PCH Bit 7 6 5 4 3 2 1 0 Field Program Counter 15 8 Read Write Default 0 0 0 0 0 0 0 0 Bit 7 0 Program Counter 15 8 8 bit data value holds the higher byte of the program counter Table 7 6 CPU Program Counter Low Register CPU_PCL Program Counter 7 0 Bit 7 0 Program Counter 7 0 8 bit data value holds the lower byte of the program counter 7 2 Addressing Modes 7 2 1 Source Immediate The result of an instruction using this addressing mode is placed in the A register the F register the SP register or the X register which is specified as part of the instruction opcode Operand 1 is an immediate value that serves as a source for the instruction Arithmetic instructions require two sources the second source is the A or the X register specified in the opcode Instructions using this addressing mode are two bytes in length Document 38 08035 Rev K Table 7 7 Source Immediate Opcode Operand 1 Instruction Immediate Value Examples ADD A 7 The immediate value of 7 is added with the Accumulator and the result is placed in the Accumulator MOV X 8 The immediate value of 8 is moved to the X register AND F 9 The immediate v
60. Reserved Reserved Int Act TTL Thresh Reserved Open Drain Pull up Output bbbbbb 00000000 POACR Low Enable Enable 0 POSCR TIO Int Int Act TTL Thresh Reserved Open Drain Pull up Output bbbbbbbb 00000000 PO6CR Output Enable Low Enable Enable PO7CR Reserved Int Int Act TTL Reserved Open Drain Pull up Output bbbbbbb 00000000 Enable Low Enable Enable 00 P10CR Reserved Int Int Act Reserved PS 2 Pull Output bb bb 00000000 Enable Low up Enable Enable 0 P11CR Reserved Int Int Act Reserved Open Drain Reserved Output bb b b 00000000 Enable Low Enable OF P12CR CLK Int Int Act Reserved Open Drain Pull up Output bbbbbbbb 00000000 Output Enable Low Enable Enable 10 P13CR Reserved Int Int Act 3 3V Drive High Sink Open Drain Pull up Output bbbbbbb 00000000 Enable Low Enable Enable 11 13 P14CR SPI Use Int Int Act 3 3V Drive High Sink Open Drain Pull up Output bbbbbbbb 00000000 P16CR Enable Low Enable Enable 14 P17CR Reserved Int Int Act TTL Thresh High Sink Open Drain Pull up Output bbbbbbb 00000000 Enable Low Enable Enable 15 P2CR Reserved Int Int Act Thresh Reserved Open Drain Pull up Output bbbbbbb 00000000 Enable Low Enable Enable 16 P3CR Reserved Int Int Act Thresh Reserved Open Drain Pull up Output bbbbbbb 00000000 Enable Low Enable Enable 20 FRTMRL Free Running Timer 7 0 bbbbbbbb 00000000 21 FRTMRH Free Running Timer 15 8 bbbb
61. SR CZ 10 4 1 PUSHX 9 3 CMP expr 6A 4 1 RLCA 2 11 4 2 SUBA expr 2 0 2MVIA expr 6B 7 2 RLC expr 2 12 6 2 SUBA expr 2 0 2MVI expr 6C 8 2 RLC Xtexpr 2 13 7 2 SUBA 2 4 1 60 4 1 CZ 14 7 2 expr A CZ 9 3 AND reg expr expr Z 6E 7 2 RRC expr CZ 15 8 2 SUB X expr A CZ 0 3 reg X expr expr 2 6F 8 2 RRC X expr CZ 16 9 31508 expr expr CZ 9 3 ORreg expr expr Z 70 4 2 AND F expr CZ 17 10 3 SUB expr CZ 0 3 ORreg X expr expr Z 71 4 2 ORF expr C Z 18 5 1 2 9 3 XOR reg expr expr 2 72 4 2 XORF expr 2 19 4 2 SBBA expr 2 0 3 XOR expr 2 73 4 1 CPLA 2 6 2 SBB A expr C Z 8 3 TST expr expr Z 74 4 1 INCA CZ 1B 7 2 SBB A X expr CZ 9 3 TST expr 2 751 4 1 INCX 2 1C 7 2 SBB expr CZ 9 3 TST reg expr expr 2 76 7 2 INC expr CZ 10 8 21588 Xtexpr A CZ 0 3 TST reg X expr expr 2 77 8 2 INC X expr CZ 1E 9 3 5 expr expr 2 5 1 SWAP A X Z 78 4 1 DECA 2 10 3 SBB X expr expr 2 7 2 SWAP A expr Z 79 4 1 2 20 5 1 7 2 SWAP X expr 7 2 DEC expr 2 21 4 2 expr 2 5 1 SWAP A SP 7B 8 2 DEC 2 22 6 2 ANDA expr 2 4 1 SP 7 13 3 LCALL 23 7 2 2 4 2
62. See package label TBAKETIME Bake Time See package label 72 hours Document 38 08035 Rev K Page 75 of 83 Feedback CYPRESS PERFORM 31 Package Diagrams Figure 31 1 16 Pin 300 CY7C63310 CY7C638xx Mil Molded DIP P1 8 1 Pega ph pi phophy gr DIMENSIONS IN INCHES MIN MAX 0 240 0 260 hd hg hug Ng HJ a PL 0 015 0 035 0 740 0770 SEATING PLANE 0 280 0 325 i 0 140 h j 0 120 0 190 0 140 0 115 0 009 3 0 160 0 015 0 012 0 060 0 055 0 310 0 090 eS es 0 015 L _ 0 dn 0 065 0 020 0 385 51 85009 A Figure 31 2 16 Pin 150 Mil SOIC S16 15 PIN 1ID 1 O H u H U H U 1 DIMENSIONS INCHESIMM MIN MAX E REFERENCE JEDEC 5 012 01503310 PACKAGE WEIGHT 0 15gms 0 157 3 987 0 230 5 842 0 244 6 197 9 16 0 010 0 254 0386 9804 _ SEATING PLANE 7 Te 0 393 9 982 F e 4 gt 00040102 1 17 d 0 050 1 270 1 0 0075 0 190 BSC 0 8 00150400 0 0098 0 249 0 0138 0 350 0 102 0 035 0 889 0 0098 0 249 51 85068 0 0192 0 487 Document 38 08035 Rev K Page 76 of 83 Feedback CY7C63310
63. The SROM holds code that boots the part calibrates circuitry and performs Flash operations Table 9 1 on page 14 lists the SROM functions The functions of the SROM are accessed in the normal user code or operating from Flash The SROM exists in a separate memory space from the user code The SROM functions are accessed by executing the Supervisory System Call instruction SSC which has an opcode of 00h Before executing the SSC the M8C s accumulator must be loaded with the desired SROM function code from Table 9 1 on page 14 Undefined functions cause a HALT if called from the user code The SROM functions are executing code with calls as a result the functions require stack space With the exception of Reset all of the SROM functions have a parameter block in SRAM that must be configured before executing the SSC Table 9 2 on page 15 lists all possible parameter block variables The meaning of each parameter with regards to a specific SROM function is described later in this section Table 9 1 SROM Function Codes Function Code Function Name Stack Space 00h SWBootReset 0 01h ReadBlock 7 02h WriteBlock 10 03h EraseBlock 9 05h EraseAll 11 06h TableRead 3 07h CheckSum 3 Page 14 of 83 Feedback EE CYPRESS PERFORM Two important variables that are used for all functions are KEY 1 and KEY2 These variables are used to help discriminate between valid SSCs and inadvertent SSCs KEY
64. UP transaction before firmware has a chance to read the SETUP data This bit is cleared by any nonlocked writes to the register 0 No SETUP received 1 SETUP received Bit 6 IN Received This bit when set indicates a valid IN packet has been received This bit is updated to 1 after the host acknowledges an IN data packet When clear it indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake This bit is cleared by any nonlocked writes to the register 0 No IN received 1 IN received Bit 5 OUT Received This bit when set indicates a valid OUT packet has been received and ACKed This bit is updated to 1 after the last received packet in an OUT transaction When clear it indicates no OUT received This bit is cleared by any nonlocked writes to the register 0 No OUT received 1 OUT received Bit 4 ACK d Transaction The ACK d transaction bit is set when the SIE engages in a transaction to the register s endpoint which completes with a ACK packet This bit is cleared by any nonlocked writes to the register 1 The transaction completes with an ACK 0 The transaction does not complete with an ACK Bit 3 0 Mode 3 0 The endpoint modes determine how the SIE responds to the USB traffic that the host sends to the endpoint The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result
65. W R W R W R W R W R W R W R W Default 0 0 0 D D D D D The IOSC Calibrate register calibrates the internal oscillator The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing test This value does not require change during normal use This is the meaning of D in the Default field Bit 7 5 foffset 2 0 This value is used to trim the frequency of the internal oscillator These bits are not used in factory calibration and are zero Setting each of these bits causes the appropriate fine offset in oscillator frequency foffset bit 7 5 kHz foffset bit 1 15 kHz foffset bit 2 30 kHz Bit 4 0 Gain 4 0 The effective frequency change of the offset input is controlled through the gain input A lower value of the gain setting increases the gain of the offset input This value sets the size of each offset step for the internal oscillator Nominal gain change KHz offsetStep at each bit typical conditions 24 MHz operation Gain bit 0 1 5 kHz Gain bit 1 3 0 kHz Gain bit 2 6 kHz Gain bit 3 12 kHz Gain bit 4 24 kHz Document 38 08035 Rev K Page 21 of 83 Feedback YPRESS CY7C63310 CY7C638xx Table 10 2 LPOSC Trim LPOSCTR 0x36 R W Bit 7 6 5 4 3 2 1 0 Field 32 kHz Low Reserved 32 kHz Bias Trim 1 0 32 kHz Freq Trim 3 0 Power Read Write R W R W R W R W R W R W R W
66. alue of 9 is logically ANDed with the F register and the result is placed in the F register Page 9 of 83 7 2 2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register which is specified as part of the instruction opcode Operand 1 is an address that points to a location in the RAM memory space or the register space that is the source of the instruction Arithmetic instructions require two sources the second source is the A register or X register specified in the opcode Instructions using this addressing mode are two bytes in length Table 7 8 Source Direct Opcode Operand 1 Instruction Source Address Examples The value in the RAM memory location at address 7 is added with the Accumulator and the result is placed in the Accumu lator ADD 7 REG 8 The value in the register space at address 8 is moved to the X register 7 2 3 Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register which is specified as part of the instruction opcode Operand 1 is added to the X register forming an address that points to a location in the RAM memory space or the register space that is the source of the instruction Arithmetic instructions require two sources the second source is the A register or X register specified in the opcode In
67. ames given to the modes of the endpoint The mode of the endpoint is determined by the 4 bit binaries in the Encoding column as discussed in the following sections The Status IN and Status OUT represent the status IN or OUT stage of the control transfer Document 38 08035 Rev K The contents of the Encoding column represent the Mode Bits 3 0 of the Endpoint Mode Registers Table 21 3 on page 59 and Table 21 4 on page 60 The endpoint modes determine how the SIE responds to different tokens that the host sends to the endpoints For example if the Mode Bits 3 0 of the Endpoint 0 Mode Register are set to 0001 which is IN OUT mode the SIE sends an ACK handshake in response to SETUP tokens and NAK any IN or OUT tokens Page 61 of 83 Feedback CYPRESS CY7C63310 CY7C638xx PERFORM 22 3 SETUP and OUT Columns Depending on the mode specified the Encoding column the SETUP IN and OUT columns contain the SIE s responses when the endpoint receives SETUP IN and OUT tokens respectively Check in the Out column means that upon receiving an OUT token the SIE checks to see whether the OUT is of zero length and has a Data Toggle Data1 0 of 1 If these conditions are true the SIE responds with an ACK If any of the these conditions is not met the SIE responds with a STALL or Ignore Count entry in the IN column means that the SIE transmits the number of bytes specified
68. and the latency for the LVD is increased The actual latency is traded against power consumption by changing Sleep Duty Cycle field of the ECO TR Register The Internal 32 kHz Low speed Oscillator remains running Before entering the suspend mode the firmware can optionally configure the 32 kHz Low speed Oscillator to operate in a low power mode to help reduce the over all power consumption Using Bit 7 Table 10 2 on page 22 This helps save approximately 5 uA however the trade off is that the 32 kHz Low speed Oscillator is less accurate All interrupts remain active Only the occurrence of an interrupt wakes the part from sleep The Stop bit in the System Status and Control Register CPU SCR must be cleared for a part to resume out of sleep The Global Interrupt Enable bit of the CPU Flags Register CPU F does not have any effect Any unmasked interrupt wakes the system up As a result any interrupts not intended for waking must be disabled through the Interrupt Mask Registers Document 38 08035 Rev K When the CPU enters sleep mode the CPUCLK Select Bit 1 Table 10 3 on page 22 is forced to the Internal Oscillator The internal oscillator recovery time is three clock cycles of the Internal 32 kHz Low power Oscillator The Internal 24 MHz Oscillator restarts immediately on exiting Sleep mode If an external clock is used firmware switches the clock source for the CPU On exiting sleep mode after the clock is stable and the de
69. arry Set by the CPU to indicate whether there has been a carry in the previous logical arithmetic operation 0 No Carry 1 Carry Bit 1 Zero Set by the CPU to indicate whether there has been a zero result in the previous logical arithmetic operation 0 Not Equal to Zero 1 Equal to Zero Bit 0 Global IE Determines whether all interrupts are enabled or disabled 0 Disabled 1 Enabled Note CPU F register is only readable with the explicit register address OxF7 The OR F expr and AND F expr instructions must be used to set and clear the CPU F bits Table 7 2 CPU Accumulator Register CPU A Bit 7 6 5 4 3 2 1 0 CPU Accumulator 7 0 Read Write Default 0 0 0 0 0 0 0 0 Bit 7 0 CPU Accumulator 7 0 8 bit data value holds the result of any logical arithmetic instruction that uses a source addressing mode Page 8 of 83 Document 38 08035 Rev K Feedback CYPRESS PERFORM Table 7 3 CPU X Register CPU_X CY7C63310 CY7C638xx Bit 7 6 5 4 3 2 1 0 Field X 7 0 Read Write Default 0 0 0 0 0 0 0 0 Bit 7 0 X 7 0 8 bit data value holds an index for any instruction that uses an indexed addressing mode Table 7 4 CPU Stack Pointer Register CPU_SP Bit 7 6 5 4 3 2 1 0 Field Stack Pointer 7 0
70. avior of the pin TIOO PO0 5 when enabled outputs a positive pulse from the Free Running Timer This is the same signal that is used internally to generate the 1024 us timer interrupt This signal is not gated by the interrupt enable state The pulse is active for one cycle of the capture timer clock TIO1 PO0 6 when enabled outputs a positive pulse from the programmable interval timer This is the same signal that is used internally to generate the programmable timer interval interrupt This signal is not gated by the interrupt enable state The pulse is active for one cycle of the interval timer clock The P0 5 TIOO and PO 6 TIO1 pins are individually configured with the POSCR 0x0A and PO6CR 0 0 respectively Document 38 08035 Rev K Page 37 of 83 Feedback gt Ed 2 CYPRESS CY7C63310 CY7C638xx PERFORM Table 14 9 P0 7 Configuration PO7CR 0x0C R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This register controls the operation of pin 7 The 7 pin only exists in the CY7C638 1 2 3 3 Table 14 10 P1 0 D Configuration P10CR 0 00 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low Reserved PS 2 Pull up Output Enable Enable Read Write R W R W R W
71. bbbb 00000000 22 TCAPOR Capture 0 Rising 7 0 bbbbbbbb 00000000 23 TCAP1R Capture 1 Rising 7 0 bbbbbbbb 00000000 24 TCAPOF Capture 0 Falling 7 0 bbbbbbbb 00000000 25 TCAP1F Capture 1 Falling 7 0 bbbbbbbb 00000000 26 PITMRL Prog Interval Timer 7 0 bbbbbbbb 00000000 27 PITMRH Reserved Prog Interval Timer 11 8 bbbb 00000000 28 PIRL Prog Interval 7 0 bbbbbbbb 00000000 29 PIRH Reserved Prog Interval 11 8 bbbb 00000000 Document 38 08035 Rev K Page 64 of 83 Feedback Cypress 7 63310 7 638 PERFORM 24 Register Summary continued The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above OxFF Addr Name 7 6 5 4 3 2 1 0 R W Default 2A TMRCR First Edge 8 bit capture Prescale 0 16bit Reserved bbbbb 00000000 Hold Enable 2B TCAPINTE Reserved Cap1 Fall 1 Rise 0 Fall 0 Rise bbbb 00000000 Active Active Active Active 2C TCAPINTS Reserved 1 Fall Cap1 Rise Fall 0 Rise bbbb 00000000 Active Active Active Active 30 CPUCLKCR Reserved USB USB CLK Reserved CPU bb b 00010000 CLK 2 Select CLK Select Disable 31 ITMRCLKCR TCAPCLK Divider TCAPCLK Select ITMRCLK Divider ITMRCLK Select bbbbbbbb 100011
72. cation voltage can be less than 4 75V on Vbus if the USB portis a low power port the voltage can be between 4 4V and 5 25V Even for externally powered 5V applications developers must consider that on power up and power down voltage is less than 4 75 for some time Firmware must be implemented properly to prevent undesired behavior Use of 24 MHz requires the use of the high POR trip point of approximately 4 55 4 65V Register LVDCR Ox1E3 PORLEV 1 0 10b This setting is sufficient to protect the device from problems due to operating at low voltage with CPU speeds above 12 MHz This must be set before setting the CPU speed to greater than 12 MHz For devices with slow power ramps changing the POR threshold to the high level may result in one or more resets of the device as power ramps through the chip default POR set point of approximately 2 6V up through the high POR set point If multiple resets are undesirable for slow power ramps then firmware must do the following m Set the Low Voltage Detection circuit Register 0x1E3 VM 2 0 for one of the set points above the POR VM 2 0 110b 4 73 or 111b 4 82 m Monitor the LVD until voltage is above the trip point Register VLTCMP 0x1E4 bit 1 is clear Document 38 08035 Rev K m Debounce the indication to ensure that voltage is above the set point for possible noisy supplies m Set the POR to the high set point m Shift CPU speed to 24 MHz If the
73. cept as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 08035 Rev K Revised December 08 2008 Page 83 of 83 PSoC is a registered trademark of Cypress MicroSystems enCoRe is a trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their respective holders Feedback
74. cessary to create a hardware only interrupt Page 52 of 83 Feedback 1 7 Lm gt CYPRESS CY7C63310 CY7C638xx PERFORM Table 17 5 Interrupt Mask 3 INT MSK3 OxDE R W Bit 7 6 5 4 3 2 1 0 Field ENSWINT Reserved Read Write R W Default 0 0 0 0 0 0 0 0 Bit 7 Enable Software Interrupt ENSWINT 0 Disable Writing Os to an INT CLRx register when ENSWINT is cleared causes the corresponding interrupt to clear 1 Enable Writing 1s to an INT CLRx register when ENSWINT is set causes the corresponding interrupt to post Bit 6 0 Reserved Table 17 6 Interrupt Mask 2 INT MSK2 OxDF R W Bit 7 6 5 4 3 2 0 Field Reserved Reserved GPIO Port 3 GPIO Port 2 PS 2 Data Low INT2 16 bit Counter TCAP1 Int Enable Int Enable Int Enable Int Enable Wrap Int Enable Int Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 Reserved Bit 6 GPIO Port 4 Interrupt Enable 0 Mask GPIO Port 4 interrupt 1 Unmask GPIO Port 4 interrupt Bit 5 GPIO Port 3 Interrupt Enable 0 Mask GPIO Port 3 interrupt 1 Unmask GPIO Port interrupt Bit 4 GPIO Port 2 Interrupt Enable 0 Mask GPIO Port 2 interrupt 1 Unmask GPIO Port 2 interrupt Bit 3 PS 2 Data Low Interrupt Enable 0 Mask PS 2 Data Low interrupt 1 Unmask PS 2 Data Low interrupt Bit 2 INT2 Interrupt Enable 0 Mask INT2 interrupt
75. clusive For Endpoint 0 Count Register when the count updates from a SETUP or OUT transaction the count register locks and cannot be written by the CPU Reading the register unlocks it This prevents firmware from overwriting a status update on it Document 38 08035 Rev K Page 58 of 83 Feedback CYPRESS 7 63310 CY7C638xx PERFORM 21 3 Endpoint 0 Mode Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers the SIE provides an interlocking mechanism to prevent accidental overwriting of data When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them Writing to this register clears the upper four bits regardless of the value written Table 21 3 Endpoint 0 Mode EPOMODE 0x44 R W Bit 7 6 5 4 3 2 1 0 Field Setup Received IN Received OUT Received ACK d Trans Mode 3 0 Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 SETUP Received This bit is set by hardware when a valid SETUP packet is received It is forced HIGH from the start of the data packet phase of the SETUP transactions until the end of the data phase of a control write transfer and cannot be cleared during this interval While this bit is set to 1 the CPU cannot write to the EPO FIFO This prevents firmware from overwriting an incoming SET
76. cted Block protection levels are set during device programming The EraseAll function overwrites data in addition to leaving the entire user Flash in the erase state The EraseAll function loops through the number of Flash macros in the product executing the following sequence erase bulk program all zeros erase After all the user space in all the Flash macros are erased a second loop erases and then programs each protection block with zeros Document 38 08035 Rev K CY7C63310 CY7C638xx 9 5 SROM Function Descriptions 9 5 1 SWBootReset Function The SROM function SWBootReset is the function that is responsible for transitioning the device from a reset state to running user code SWBootReset function is executed whenever the SROM is entered with an M8C accumulator value of 00h the SRAM parameter block is not used as an input to the function This happens by design after a hardware reset because the M8C s accumulator is reset to 00h or when the user code executes the SSC instruction with an accumulator value of 00h The SWBootReset function is not executed when the SSC instruction is executed with a bad key value and a non zero function code enCoRe Il device executes the HALT instruction if a bad value is given for either KEY1 or KEY2 The SWBootReset function verifies the integrity of the calibration data by way of a 16 bit checksum before releasing the M8C to run user code 9 5 2 ReadBlock Function The R
77. cument 38 08035 Rev K Page 27 of 83 Feedback EE CYPRESS PERFORM 11 1 Power on Reset POR occurs every time the power to the device is switched on POR is released when the supply is typically 2 6V for the upward supply transition with typically 50 mV of hysteresis during the power on transient Bit 4 of the System Status and Control Register CPU_SCR is set to record this event the register contents are set to 00010000 by the POR After a POR the microprocessor is held off for approximately 20 ms for the Vcc supply to stabilize before executing the first instruction at address 0x00 in the Flash If the Vcc voltage drops below the POR downward supply trip point POR is reasserted The Vcc supply must ramp linearly from 0 to 4V in less than 200 ms Note The PORS status bit is set at POR and is cleared only by the user It cannot be set by firmware 11 2 Watchdog Timer Reset The user has the option to enable the WDT The WDT is enabled by clearing the PORS bit After the PORS bit is cleared the WDT cannot be disabled The only exception to this is if a POR event takes place which disables the WDT Table 11 2 Reset Watchdog Timer RESWDT 0xE3 W CY7C63310 CY7C638xx The sleep timer is used to generate the sleep time period and the Watchdog time period The sleep timer uses the Internal 32 kHz Low power Oscillator system clock to produce the sleep time period The user can program the sleep time period usi
78. d Capture Timer clock TCAPCLK The 32 kHz Low power Oscillator can operate in low power mode or can provide a more accurate clock in normal mode The Internal 32 kHz Low power Oscillator accuracy ranges between 0 70 C follow m 5V Normal mode 8 to 16 m 5V LP mode 12 to 48 Document 38 08035 Rev K CY7C63310 CY7C638xx When using the 32 kHz oscillator the PITMRL H registers must be read until 2 consecutive readings match before the result is considered valid The following firmware example assumes the developer is interested in the lower byte of the PIT Read PIT counter mov A reg PITMRI mov 57h A mov A reg PITMRI mov 58h A mov 59h A mov A reg PITMRI mov 60h A 77 7Start comparison mov A 60h mov X 59h sub A 59h jz done mov A mov X sub A jz done mov X 57h data is in memory location 57h done mov 57h X ret 59h 58h 58h Page 19 of 83 Feedback CY7C63310 CY7C638xx PERFORM Figure 10 1 Clock Block Diagram CPUCLK SEL CLK_EXT gt SCALE divide by 27 MUX 0 5 7 P CPU_CLK CLK 24MHz EXT MUX CLK USB 24 MHz SEL SCALE SEL SCALE OUT 0 X 12 MHz 0 X 12 MHz 1 1 EXT 2 1 1 EXT LP OSC CLK 32 32 KHz KHz Page 20 of 83 Feedback Document 38 08035 Rev K
79. e 2200V DC Input Voltage 0 5 to Voc 0 5V Latch Up Current 200 mA DC Voltage Applied to Outputs in High Z 0 5V to 0 5V 27 DC Characteristics Description Parameter Conditions Min Typical Unit General Veca Operating Voltage No USB activity CPU speed lt 12 MHz 4 0 5 5 V Vcc2 Operating Voltage USB activity CPU speed 12 MHz 4 35 5 25 V Vec3 Operating Voltage Flash programming 4 0 5 5 V Operating Voltage No USB activity CPU speed is 4 75 5 5 V between 12 MHz and 24 MHz Operating Temp Flash Programming 0 70 lcc4 Vec Operating Supply Current 5 25V no GPIO loading 40 mA 24 MHz gt Vec Operating Supply Current Vcc 5 0 no GPIO loading 6 MHz 10 mA Isp4 Standby Current Internal and External Oscillators 10 Bandgap Flash CPU Clock Timer Clock USB Clock all disabled Low Voltage Detect Low Voltage Detect Trip Voltage 2 681 4 872 V 8 programmable trip points 3 3V Regulator lvREG Max Regulator Output Current 4 35V lt Voc lt 5 5V 125 mA Keep Alive Current When regulator is disabled with 20 keep alive enable Vka Keep Alive Voltage Keep alive bit set in VREGCR 2 35 3 8 V VnEG1 Output Voltage Vec gt 4 35V 0 lt temp lt 40 C 3 0 3 6 V 25 lt lt 125 mA 3 3V 8 01070 VRE
80. e M8C s A and X registers are used by the TableRead function to return the die s Revision ID The Revision ID is a 16 bit value hard coded into the SROM that uniquely identifies the die s design The return values for corresponding Table calls are tabulated as shown in Table 9 11 on page 17 Table 9 11 Return values for Table Read Return Value Table Number A 0 Revision ID Family ID 1 Internal Revision Counter OxFF 2 7 OxFF OxFF Page 17 of 83 Feedback CYPRESS CY7C63310 CY7C638xx PERFORM Figure 9 3 SROM Table F8h F9h FAh FBh FCh FDh FEh FFh Tableo ID a ID Table1 ud Revision Table2 Table3 Table4 Table5 Table6 Table7 The Silicon IDs for enCoRe II devices are stored in SROM tables in the part as shown in Figure 9 3 The Silicon ID can be read out from the part using SROM Table reads Table 0 This is demonstrated in the following pseudo code As mentioned in the section SROM on page 14 the SROM variables occupy address F8h through FFh in the SRAM Each of the variables and their definition is given in the section SROM on page 14 AREA SSCParmB1kA RAM ABS org F8h Variables are defined starting at address F8h SSC KEY1 F8h supervisory key SSC RETURNCODE blk 1 F8h result code SSC KEY2 blk 1 F9h supervisory stack ptr key SSC BLOCKID blk 1 FAh block ID 55 POINTER blk
81. e SPI block swaps its use of SMOSI and SMISO This is useful in implementing single wire communications similar to SPI Bit 6 LSB First 0 The SPI transmits and receives the MSB Most Significant Bit first 1 The SPI transmits and receives the LSB Least Significant Bit first Bit 5 4 Comm Mode 1 0 0 0 All SPI communication disabled 0 1 SPI master mode 1 0 SPI slave mode 1 1 Reserved Bit 3 CPOL This bit controls the SPI clock SCLK idle polarity 0 SCLK idles low 1 SCLK idles high Bit 2 CPHA The Clock Phase bit controls the phase of the clock on which data is sampled Table 15 4 on page 42 shows the timing for the various combinations of LSB First CPOL and CPHA Bit 1 0 SCLK Select This field selects the speed of the master SCLK When in master mode SCLK is generated by dividing the base CPUCLK Note for Comm Modes 01b or 10b SPI Master or SPI Slave When configured for SPI SPI Use 1 Table 14 14 on page 39 the input output direction of pins P1 3 1 5 and P1 6 is set automatically by the SPI logic However pin P1 4 s input output direction is NOT automatically set it must be explicitly set by firmware For SPI Master mode pin P1 4 must be configured as an output for SPI Slave mode pin P1 4 must be configured as an input Table 15 3 SPI SCLK Frequency SCLK CPUCLK SCLK Frequency when CPUCLK Select Divisor 12 MHz 24 MHz 00 6 2MHz 4 MHz 01 12 1 MHz 2 MHz 10 48 250 kH
82. e of the Port 0 pins Besides their use as the 6 5 GPIOs these pins are also used for the alternate functions as the Capture Timer input or Timer output pins 1 and TIOO To configure the 5 and 6 pins refer to the P0 5 TIOO PO 6 TIO1 Configuration Register The use of the pins as the 6 5 GPIOs and the alternate functions exist in all the enCoRe II parts Besides their use as the P0 4 P0 2 GPIOs these pins are also used for the alternate functions as the Interrupt pins INTO INT2 Table 14 8 on page 37 Bit 4 2 4 0 2 Data INT2 INTO The use of the pins as the 4 0 2 GPIOs and the alternate functions exist in all the enCoRe II parts Bit 1 PO 1 CLKOUT Besides its use as the 1 GPIO this is also used for an alternate function as the CLK OUT To configure the 1 pin refer to the P0 0 CLKIN Configuration Register Table 14 5 on page 36 refer to the PO 1 CLKOUT Configuration Register Table 14 6 on page 36 Bit 0 PO 0 CLKIN Besides its use as the P0 0 this is also used for an alternate function as the CLKIN pin To configure the PO O pin Document 38 08035 Rev K Page 33 of 83 Feedback CY7C63310 CY7C638xx Table 14 2 P1 Data Register P1DATA 0x01 R W Bit 7 6 5 4 3 2 1 0 Field BAS P1 6 SMISO P1 5 SMOSI P1 4 SCLK P1 3 SSEL 1 2 P1 1 D P1 0 D Read Write R W R W R W R W R W R W R W R W D
83. eadBlock function is used to read 64 contiguous bytes from Flash a block This function first checks the protection bits and determines if the desired BLOCKID is readable If the read protection is turned on the ReadBlock function exits setting the accumulator and KEY2 back to 00h KEY1 has a value of 01h indicating a read failure If read protection is not enabled the function reads 64 bytes from the Flash using instruction and stores the results in the SRAM using an MVI instruction The first of the 64 bytes stored in the SRAM at the address indicated by the value of the POINTER parameter When the ReadBlock completes successfully the accumulator KEY1 and KEY2 all have a value of 00h Table 9 4 ReadBlock Parameters Name Address Description KEY1 O 8h KEY2 O F9h Stack Pointer value when SSC is executed BLOCKID O FAh Flash block number POINTER O FBh First of 64 addresses in SRAM where returned data must be stored Page 15 of 83 Feedback 9 5 3 WriteBlock Function The WriteBlock function is used to store data in the Flash Data is moved 64 bytes at a time from SRAM to Flash using this function The WriteBlock function first checks the protection bits and determines if the desired BLOCKID is writable If write protection is turned on the WriteBlock function exits setting the accumulator and KEY2 back to 00 KEY1 has a value of 01h indicating a write fail
84. eck STALL IN and ACK zero byte OUT Control endpoint only STALL IN OUT 0011 Accept STALL STALL STALL IN and OUT token Control endpoint only STATUS IN ONLY 0110 Accept TXO byte STALL STALL OUT and send zero byte data for IN token Con trol endpoint only ACK OUT STATUS 1011 Accept TXO byte ACK ACK the OUT token or send zero byte data for IN token IN Control endpoint only ACK IN STATUS 1111 Accept TX Count Check Respond to IN data or Status OUT Control endpoint OUT only NAK OUT 1000 Ignore Ignore NAK Send NAK handshake to OUT token Data endpoint only ACK OUT STALL 0 1001 Ignore Ignore ACK This mode is changed by the SIE to mode 1000 on is suance of ACK handshake to an OUT Data endpoint only ACK OUT STALL 1 1001 Ignore Ignore STALL STALL the OUT transfer NAK IN 1100 Ignore NAK Ignore Send NAK handshake for IN token Data endpoint only ACK IN STALL 0 1101 Ignore TX Count Ignore This mode is changed by the SIE to mode 1100 after receiving ACK handshake to an IN data Data endpoint only ACK IN STALL 1 1101 Ignore STALL Ignore STALL the IN transfer Data endpoint only Reserved 0101 Ignore Ignore Ignore These modes are not supported by SIE Firmware must not use this mode in Control and Data endpoints Reserved 0111 Ignore Ignore Ignore Reserved 1010 Ignore Ignore Ignore Reserved 0100 Ignore Ignore Ignore Reserved 1110 Ignore Ignore Ignore 22 2 Encoding Column The Mode column contains the mnemonic n
85. ed Bit 6 USB CLK 2 Disable This bit only affects the USBCLK when the source is the external clock When the USBCLK source is the Internal 24 MHz Oscillator the divide by two is always enabled 0 USBCLK source is divided by two This is the correct setting to use when the Internal 24 MHz Oscillator is used or when the external source is used with a 24 MHz clock 1 USBCLK is undivided Use this setting only with a 12 MHz external clock Bit 5 USB CLK Select This bit controls the clock source for the USB SIE 0 Internal 24 MHz Oscillator With the presence of USB traffic the Internal 24 MHz Oscillator is trimmed to meet the USB requirement of 1 5 tolerance see Table 10 5 on page 24 1 External clock Internal Oscillator is not trimmed to USB traffic Proper USB SIE operation requires 12 MHz or 24 MHz clock accurate to lt 1 5 Bit 4 1 Reserved Bit 0 CPU CLK Select 0 Internal 24 MHz Oscillator 1 External clock External clock at CLKIN P0 0 pin Note The CPU speed selection is configured using Register Table 10 4 on page 23 Document 38 08035 Rev K Page 22 of 83 Feedback CY7C63310 CY7C638xx R W 1 CPU Speed 2 0 R W 0 3 R W 4 Sleep Timer 1 0 R W 0 5 R W YPRESS 6 R W 0 7 Reserved S Table 10 4 OSC Control 0 05 0 0x1E0 R W No Buzz 0 Bit Read Write Default Field
86. ed interrupts for the corresponding hardware Writing 1 to the bits AND to the ENSWINT Bit 7 of the INT MSK3 Register posts the corresponding hardware interrupt Table 17 3 Interrupt Clear 1 INT CLR1 OxDB R W CY7C63310 CY7C638xx Bit 7 6 5 4 3 2 1 0 Field TCAPO Prog Interval 1 ms Timer USB Active USB Reset USB EP2 USB EP1 USB EPO Timer Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 When reading this register 0 There is no posted interrupt for the corresponding hardware 1 Posted interrupt for the corresponding hardware present Writing a 0 to the bits clears the posted interrupts for the corresponding hardware Writing a 1 to the bits and to the ENSWINT Bit 7 of the INT_MSK3 Register posts the corresponding hardware interrupt Table 17 4 Interrupt Clear 2 INT CLR2 OxDC R W Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved GPIO Port 3 GPIO Port 2 PS 2 Data Low INT2 16 bit Counter TCAP1 Wrap Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 When reading this register 0 There is no posted interrupt for the corresponding hardware 1 Posted interrupt for the corresponding hardware present Writing a 0 to the bits clears the posted interrupts for the corresponding hardware Writing a 1 to the bits AND to the ENSWINT Bit 7 of the INT_MSK3 Register post
87. efault 0 0 0 0 0 0 0 0 This register contains the data for Port 1 Writing to this register sets the bit values to be output on output enabled pins Reading from this register returns the current state of the Port 1 pins Bit 7 P1 7 Data P1 7 only exists in the CY7C638xx Bit 6 3 1 6 1 3 Data SPI Pins SMISO SMOSI SCLK SSEL Besides their use as the 1 6 1 3 GPIOs these pins are also used for the alternate function as the SPI interface pins To configure the 1 6 1 3 pins refer to the P1 3 P 1 6 Configuration Register Table 14 13 page 39 The use of the pins as the 1 6 1 3 GPIOs and the alternate functions exist in all the enCoRe II parts Bit 2 P1 2 VREG On the CY7C638x3 this is used as the P1 2 GPIO or the VREG output If the VREG output is enabled Bit 0 Table 19 1 on page 57 is set a 3 3V source is placed on the pin and the GPIO function of the pin is disabled The VREG functionality is not present in the CY7C63310 the CY7C63801 variants A 1 uF min 2 F max capacitor is required on VREG output Bit 1 0 P1 1 P1 0 D and D When the USB mode is disabled Bit 7 in Table 21 1 on page 58 is clear the P1 1 and P1 0 bits are used to control the state of the P1 0 and P1 1 pins When the USB mode is enabled the P1 1 and P1 0 pins are used as the D and D pins respectively If the USB Force State bit Bit 0 in Table 19 1 is set the state of the D and D
88. es are numbered zero through seven All user and hidden blocks in the CY7C638xx parts consist of 64 bytes An internal table Table 0 holds the Silicon ID and returns the Revision ID The Silicon ID is returned in SRAM while the Revision and Family IDs are returned in the CPU A and CPU X registers The Silicon ID is a value placed in the table by programming the Flash and is controlled by Cypress Semicon ductor Product Engineering The Revision ID is hard coded into the SROM and also redundantly placed in SROM Table 1 This is discussed in more detail later in this section SROM Table 1 holds Family Die ID and Revision ID values for the device and returns a one byte internal revision counter The internal revision counter starts out with a value of zero and is incremented when one of the other revision numbers is not incre mented It is reset to zero when one of the other revision numbers is incremented The internal revision count is returned in the CPU A register The CPU X register is always set to FFh when Table 1 is read The CPU A and CPU X registers always return a value of FFh when Tables 2 7 are read The BLOCKID value in the parameter block indicates which table must be returned to the user Only the three least significant bits of the BLOCKID parameter are used by TableRead function for enCoRe devices The upper five bits are ignored When the function is called it transfers bytes from the table to SRAM addresses F8h FFh Th
89. eserved Reserved 011 Reserved Reserved Reserved 100 4 439 4 48 4 528 101 4 597 4 64 4 689 110 4 680 4 73 4 774 111 4 766 4 82 4 862 Document 38 08035 Rev K Page 31 of 83 Feedback 2 CYPRESS 7 63310 CY7C638xx PERFORM Table 13 2 Voltage Monitor Comparators Register VLTCMP 0x1E4 R Bit 7 6 5 4 3 2 1 0 Field Reserved LVD PPOR Read Write R R Default 0 0 0 0 0 0 0 0 This read only register allows reading the current state of the Low Voltage Detection and Precision Power On Reset compar ators Bit 7 2 Reserved Bit 1 LVD This bit is set to indicate that the low voltage detect comparator has tripped indicating that the supply voltage has gone below the trip point set by VM 2 0 See Table 13 1 0 No low voltage detect event 1 A low voltage detect has tripped Bit 0 PPOR This bit is set to indicate that the precision power on reset comparator has tripped indicating that the supply voltage is below the trip point set by PORLEV 1 0 0 No precision power on reset event 1 A precision power on reset event has occurred Note This register exists in the second bank of IO space This requires setting the bit in the CPU flags register 13 0 1 ECO Trim Register Table 13 3 ECO ECO TR 0x1EB R W Bit 7 6 5 4 3 2 1 0 Field Sleep Duty Cycle 1 0 Reserved Read Write R W R W
90. essing mode is only valid on the MOV instruction The instruction using this addressing mode is three bytes in length Document 38 08035 Rev K CY7C63310 CY7C638xx Table 7 14 Destination Direct Source Direct Opcode Operand 1 Operand 2 Instruction Destination Address Source Address Example MOV 7 8 The value in the memory location at address 8 is moved to the memory location at address 7 7 2 9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator Operand 1 is an address pointing to a location within the memory space which contains an address the indirect address for the source of the instruction The indirect address is incremented as part of the instruction execution This addressing mode is only valid on the MVI instruction The instruction using this addressing mode is two bytes in length Refer to the 5 Designer Assembly Language User Guide for further details on MVI instruction Table 7 15 Source Indirect Post Increment Opcode Operand 1 Instruction Source Address Address Example MVI A 8 The value in the memory location at address 8 is an indirect address The memory location pointed to by the indirect address is moved into the Accumulator The indirect address is then incremented 7 2 10 Destination Indirect Post Increment The result of an instructio
91. fault 7 R W R W Unknown Unknown Table 21 6 Endpoint 1 Data EP1DATA 0x58 0x5F R W 5 The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57 Bit Field Read Write Default Unknown Document 38 08035 Rev K The Endpoint 1 buffer is comprised of 8 bytes located at address 0x58 to 0x5F Page 60 of 83 Feedback 55 PERFORM Table 21 7 Endpoint 2 Data EP2DATA 0x60 0x67 R W CY7C63310 CY7C638xx Bit 7 6 5 4 3 2 1 0 Field Endpoint 2 Data Buffer 7 0 Read Write R W R W R W R W R W R W R W R W Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67 The three data buffers are used to hold data for both IN and OUT transactions Each data buffer is 8 bytes long The reset values of the Endpoint Data Registers are unknown Unlike past enCoRe parts the USB data buffers are only accessible in the IO space of the processor 22 USB Mode Tables 22 1 Mode Column Mode Encoding SETUP IN OUT Comments DISABLE 0000 Ignore Ignore Ignore Ignore all USB traffic to this endpoint Used by Data and Control endpoints NAK IN OUT 0001 Accept NAK NAK NAK IN and OUT token Control endpoint only STATUS OUT ONLY 0010 Accept STALL Ch
92. gisters immediately following a firmware write and rewrite if the value read is incorrect R W The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint The mode controls how 3 Bit 4 ACK d Transaction the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the Unknown 0 endpoint R W Unknown 1 Unknown Note When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the EP1MODE registers respectively if both writes occur in the same clock cycle This is because the design employs only one 4 Endpoint 0 Data Buffer 7 0 R W 1 The transaction completes with an ACK common update signal for both EP1MODE and EP2MODE registers As a result when SIE writes to say EP1MODE register R W R W Unknown the update signal is set and this prevents firmware writes to EP2MODE register SIE writes to the endpoint mode registers Unknown 2 higher priority than firmware writes This mode register write block situation can put the endpoints in incorrect modes Firmware R W 6 R W R W Unknown Unknown 3 7 R W Bit R W Unknown Table 21 5 Endpoint 0 Data EPODATA 0x50 0x57 R W 5 4 Endpoint 1 Data Buffer 7 0 R W Unknown R W Field Unknown Read Write 6 Unknown R W De
93. ield controls the source of the TCAPCLK 0 0 Internal 24 MHz Oscillator 0 1 External clock external clock at CLKIN 0 0 input 1 0 Internal 32 kHz low power oscillator 1 1 TCAPCLK Disabled Note The 1024 us interval timer is based on the assumption that TCAPCLK is running at 4 MHz Changes in TCAPCLK frequency causes a corresponding change in the 1024 us interval timer frequency Bit 3 2 ITMRCLK Divider ITMRCLK Divider controls the ITMRCLK divisor 0 0 Divider value of 1 0 1 Divider value of 2 1 0 Divider value of 3 1 1 Divider value of 4 Bit 1 0 ITMRCLK Select 0 0 Internal 24 MHz Oscillator 0 1 External clock external clock at CLKIN P0 0 input 1 0 Internal 32 kHz low power oscillator 112 TCAPCLK Document 38 08035 Rev K Page 24 of 83 Feedback 10 1 1 Interval Timer Clock ITMRCLK The Interval Timer Clock TITMRCLK is sourced from an external clock the Internal 24 MHz Oscillator the Internal 32 kHz Low power Oscillator or the Timer Capture clock A programmable prescaler of 1 2 3 or 4 then divides the selected source The 12 bit Programmable Interval Timer is a simple down counter with a programmable reload value It provides a 1 us resolution by default When the down counter reaches zero the next clock is spent reloading The reload value is read and written while the counter is running but the counter must not unintentionally reload when the 12 bit reload value is
94. into the 64 bytes of the protection block As a result each protection block byte stores the protection level for four Flash blocks The bits are packed into a byte with the lowest numbered block s protection level stored in the lowest numbered bits Table 9 7 The first address of the protection block contains the protection level for blocks 0 through 3 the second address is for blocks 4 through 7 The 64th byte stores the protection level for blocks 252 through 255 Table 9 7 Protection Modes Mode Settings Description 000 SR EW IW Unprotected 01b 5 IW Read protect 106 ISR ER EW IW Disable external Marketing Unprotected Factory upgrade Field upgrade write 11b ISR ER EW IW Disable internal Full protection write 7 6 5 4 3 2 1 0 Block n 3 Block n 2 Block n 1 Block n The level of protection is only decreased by an EraseAll which places zeros in all locations of the protection block To set the level of protection the ProtectBlock function is used This function takes data from SRAM starting at address 80h and ORs it with the current values in the protection block The result of the OR operation is then stored in the protection block The EraseBlock function does not change the protection level for a block Because the SRAM location for the protection data is fixed and there is only one protection block per Flash macro the ProtectBlock
95. is makes it impossible to read write or erase the Flash by bypassing the security mechanisms implemented in the SROM Customer firmware can program the Flash only through SROM calls The data or code images are sourced through any interface with the appropriate support firmware This type of programming requires a boot loader which is a piece of firmware resident on the Flash For safety reasons this boot loader must not be overwritten during firmware rewrites The Flash provides four extra auxiliary rows that are used to hold Flash block protection flags boot time calibration values configuration tables and any device values The routines for accessing these auxiliary rows are documented in the section SROM on page 14 section The auxiliary rows are not affected by the device erase function 9 3 2 In System Programming Most designs that include enCoRe Il part have USB connector attached to the USB D and pins on the device These designs require the ability to program or reprogram a part through the USB D and pins alone enCoRe Il devices enable this type of in system programming by using the D and D pins as the serial programming mode interface This allows an external controller Document 38 08035 Rev K to enable the enCoRe II part to enter the serial programming mode and then use the test queue to issue Flash access functions in the SROM The programming protocol is not USB 9 4 SROM
96. ith V3 3 enabled When clear the pull up is disabled 14 2 7 Output Enable When set the output driver of the pin is enabled When clear the output driver of the pin is disabled For pins with shared functions there are some special cases 14 2 8 VREG Output SPI Use The P1 2 VREG P1 3 SSEL P1 4 SCLK P1 5 SMOSI and P1 6 SMISO pins are used for their dedicated functions or for GPIO To enable the pin for GPIO clear the corresponding VREG Output or SPI Use bit The SPI function controls the output enable for its dedicated function pins when their GPIO enable bit is clear The VREG output is not available on the CY7C63801 and CY7C63310 14 2 9 3 3V Drive The P1 3 SSEL P1 4 SCLK P1 5 SMOSI and P1 6 SMISO pins have an alternate voltage source from the voltage regulator If the 3 3V Drive bit is set a high level is driven from the voltage regulator instead of from Vcc Setting the 3 3V Drive bit does not enable the voltage regulator That must be done explicitly by setting the VREG Enable bit in the VREGCR Register Table 19 1 on page 57 Page 35 of 83 Feedback gt CYPRESS CY7C63310 7 638 PERFORM Figure 14 1 Block Diagram of a GPIO VREG CC 3 3V Drive FT 5 25 Pull Up Enable 7 E Output Enable V VREG HO Open Drain J m Data Out Port Data n GPIO zm D unm wc i High Sink VREG GND Voc GND Data In TTL Threshold Table 14 5 P0 0
97. its of the checksum and the parameter KEY2 holds the upper eight bits of the checksum The checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksummed romx add adc KEY1 KEY2 O Table 9 12 Checksum Parameters Name Address Description KEY1 0 F8h 3Ah KEY2 0 F9h Stack Pointer value when SSC is executed BLOCKID 0 FAh Number of Flash blocks to calculate checksum on 10 Clocking The enCoRe II has two internal oscillators the Internal 24 MHz Oscillator and the 32 kHz Low power Oscillator The Internal 24 MHz Oscillator is designed such that it may be trimmed to an output frequency of 24 MHz over temperature and voltage variation With the presence of USB traffic the Internal 24 MHz Oscillator may be set to precisely tune to the USB timing requirements 24 MHz 1 5 Without USB traffic the Internal 24 MHz Oscillator accuracy is 24 MHz 5 between 0 70 No external components are required to achieve this level of accuracy The internal low speed oscillator of nominally 32 kHz provides a slow clock source for the enCoRe II in suspend mode particu larly to generate a periodic wakeup interrupt and also to provide a clock to sequential logic during power up and power down events when the main clock is stopped In addition this oscillator can also be used as a clocking source for the Interval Timer clock ITMRCLK an
98. lay time has expired the instruction immediately following the sleep instruction is executed before the interrupt service routine if enabled The Sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption The Sleep interrupt may also be used to provide periodic interrupts during non sleep modes Page 28 of 83 Feedback SESJ CYPRESS PERFORM 12 1 Sleep Sequence The SLEEP bit is an input into the sleep logic circuit This circuit is designed to sequence the device into and out of the hardware sleep state The hardware sequence to put the device to sleep is shown in Figure 12 1 and is defined as follows Firmware sets the SLEEP bit in the register The Bus Request BRQ signal to the CPU is immediately asserted This is a request by the system to halt CPU operation at an instruction boundary The CPU samples BRQ on the positive edge of CPUCLK Due to the specific timing of the register write the CPU issues a Bus Request Acknowledge BRA on the following positive CY7C63310 CY7C638xx edge of the CPU clock The sleep logic waits for the following negative edge of the CPU clock and then asserts a system wide Power Down PD signal In Figure 12 1 on page 29 the CPU is halted and the system wide power down signal is asserted 3 The system wide PD power down signal controls several
99. le 0 Mask EPO interrupt 1 Unmask EPO interrupt Document 38 08035 Rev K Page 54 of 83 Feedback 1 0 Mask Port 1 interrupt 1 Unmask Port 1 interrupt Bit 6 Sleep Timer Interrupt Enable 0 Mask Sleep Timer interrupt 1 Unmask Sleep Timer interrupt Bit 5 INT1 Interrupt Enable 0 Mask interrupt 1 Unmask INT1 interrupt Bit 4 GPIO Port 0 Interrupt Enable 0 Mask GPIO Port 0 interrupt 1 Unmask GPIO Port 0 interrupt Bit 3 SPI Receive Interrupt Enable 0 Mask SPI Receive interrupt 1 Unmask SPI Receive interrupt Bit 2 SPI Transmit Interrupt Enable 0 Mask SPI Transmit interrupt 1 Unmask SPI Transmit interrupt Bit 1 INTO Interrupt Enable 0 Mask INTO interrupt 1 Unmask INTO interrupt 229 Ed Z CYPRESS CY7C63310 CY7C638xx PERFORM Table 17 8 Interrupt Mask 0 5 0 0xE0 R W Bit 7 6 5 4 3 2 0 Field GPIO Port 1 Sleep Timer INT1 GPIO Port 0 SPI Receive SPI Transmit INTO POR LVD Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 GPIO Port 1 Interrupt Enable Bit 0 POR LVD Interrupt Enable 0 Mask POR LVD interrupt 1 Unmask POR LVD interrupt Table 17 9 Interrupt Vector Clear Register INT VC 0 2 R W Bit 7 6 5
100. less of whether the pin is configured for input or output All interrupts are edge sensitive however for any interrupt that is shared by multiple sources that is Ports 2 3 and 4 all inputs must be deasserted before a new interrupt can occur When clear the corresponding interrupt is disabled on the pin It is possible to configure GPIOs as outputs enable the interrupt on the pin and then generate the interrupt by driving the appro priate pin state This is useful in tests and may have value in applications 14 2 2 Int Act Low When set the corresponding interrupt is active on the falling edge When clear the corresponding interrupt is active on the rising edge 14 2 3 TTL Thresh When set the input has TTL threshold When clear the input has standard CMOS threshold 14 2 4 High Sink When set the output can sink up to 50 mA When clear the output can sink up to 8 mA Only the 1 7 1 3 have 50 mA sink drive capability Other pins have 8 mA sink drive capability Document 38 08035 Rev K CY7C63310 CY7C638xx 14 2 5 Open Drain When set the output on the pin is determined by the Port Data Register If the corresponding bit in the Port Data Register is set the pin is in high impedance state If the corresponding bit in the Port Data Register is clear the pin is driven low When clear the output is driven LOW or HIGH 14 2 6 Pull up Enable When set the pin has a 7K pull up to Vcc or VREG for ports w
101. load High PIRH 0x29 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Prog Interval 11 8 Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 4 Reserved Bit 3 0 Prog Interval 11 8 nibble System Clock Clock Timer This register holds the higher 4 bits of the timer While writing into the 12 bit reload register write the lower byte first then the higher Figure 16 2 Programmable Interval Timer Block Diagram Configuration Status and Control Document 38 08035 Rev K 12 bit down counter Interrupt 12 bit Controller reload counter Page 45 of 83 Feedback ERFORM 16 1 2 Timer Capture Cypress enCoRe has two 8 bit captures Each capture has separate registers for the rising and falling time The two eight bit captures can be configured as a single 16 bit capture When configured the capture 1 registers hold the high order byte of the 16 bit timer capture value Each of the four capture registers may be programmed to generate an interrupt when it is loaded Table 16 11 Timer Configuration TMRCR 0x2A R W Cypress CY7C63310 CY7C638xx Bit 7 6 5 4 3 2 1 0 Field First Edge Hold 8 bit Capture Prescale 2 0 0 16bit Reserved Enable Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 First Edge Hold The First Edge Hold function applies to all fou
102. mation updated Vreg can operate independent of USB lower case Added information on SROM Table read section 9 6 Updated section 12 3 Low Power in Sleep Mode Included Set P10CR 1 during non USB mode operations Added section 25 Voltage Vs CPU Frequency char connection Included IMO and ILO characteristics in the AC char section Added Package Handling information Updated to data sheet template E 12 12 08 CMCC PYRS 2620679 Document 38 08035 Rev Page 82 of 83 Feedback _ Cypress CYPRESS CY7C63310 CY7C638xx PERFORM 33 Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2003 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use
103. n as clock output source onto either 1 CLKOUT or P12 VREG pins All the other blocks go to the power down mode automatically on suspend A CY7C63310 CY7C638xx The following steps are user configurable and help in reducing the average suspend mode power consumption 1 Configure the power supply monitor at a large regular inter vals control register bits are 1 EB 7 6 Power system sleep duty cycle PSSDC 1 0 2 Configure the Low power oscillator into low power mode control register bit is LOPSCTR 7 For low power considerations during sleep when external clock is used as the CPUCLK source the clock source must be held low to avoid unintentional leakage current If the clock is held high then there may a leakage through M8C To avoid current consumption make sure ITMRCLK TCPCLK and USBCLK are not sourced by either low power 32 kHz oscillator or 24 MHz crystal less oscillator Do not select 24 MHz or 32 kHz oscillator clocks on to the 1 CLKOUT P12 VREG pin Note In case of a self powered designs particularly battery power the USB suspend current specifications may not be met because the USB pins are expecting termination Figure 12 2 Wake Up Timing Interrupt is double sampled by 32K clock and PD is negated to Sleep Timer or GPIO interrupt occurs A CLK32K CPU is restarted after 90ms nominal system PD BANDGAP LVD PPOR ENABLE SAMPLE
104. n instruction using this addressing mode is placed within the RAM memory space or the register space Operand 1 is added to the X register forming the address that points to the location of the result The source for the instruction is the A register Arithmetic instructions require two sources the second source is the location specified by Operand 1 added with the X register Instructions using this addressing mode are two bytes in length Table 7 11 Destination Indexed Opcode Operand 1 Instruction Destination Index Example ADD 7 A The value in the memory location at address X 7 is added with the Accumu lator and the result is placed in the memory location at address x 7 The Accumulator is unchanged Page 10 of 83 Feedback 7 2 6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within the RAM memory space or the register space Operand 1 is the address of the result The source of the instruction is Operand 2 which is an immediate value Arithmetic instructions require two sources the second source is the location specified by Operand 1 Instructions using this addressing mode are three bytes in length Table 7 12 Destination Direct Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Address Immediate Value Examples ADD 7 5 The value in the memory location at address
105. n using this addressing mode is placed within the memory space Operand 1 is an address pointing to a location within the memory space which contains an address the indirect address for the destination of the instruction The indirect address is incremented as part of the instruction execution The source for the instruction is the Accumulator This addressing mode is only valid on the MVI instruction The instruction using this addressing mode is two bytes in length Table 7 16 Destination Indirect Post Increment Opcode Operand 1 Instruction Destination Address Address Example MVI 8 A The value in the memory location at address 8 is an indirect address The Accumulator is moved into the memory location pointed to by the indirect address The indirect address is then incremented Page 11 of 83 Feedback Cypress CY7C63310 CY7C638xx PERFORM 8 Instruction Set Summary The instruction set is summarized in Table 8 1 numerically and serves as a quick reference If more information is needed the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide available on the Cypress web site at http www cypress com Table 8 1 In
106. n with user configurable threshold voltages m Operating voltage from 4 0V to 5 5V DC m Operating temperature from 0 70 m Available in 16 and 18 pin PDIP 16 18 and 24 pin SOIC 24 pin QSOP and 32 pin QFN packages m industry standard programmer support 1 1 Applications The CY7C63310 CY7C638xx is targeted for the following applications m PC HID devices Mice optomechanical optical trackball m Gaming Joysticks Game pad m General purpose Barcode scanners POS terminal Consumer electronics Toys Remote controls Security dongles San Jose CA 95134 1709 408 943 2600 Revised December 08 2008 Feedback CYPRESS 2 Logic Block Diagram Low Speed USB PS2 Low Speed Interrupt Transceiver USB SIE Control 3 3V Regulat and Pull up Internal External Clock Watchdog POR Timer Low Voltage Detect gt Document 38 08035 Rev CY7C63310 CY7C638xx 24 MHz Oscillator RAM Control Byte Byte Up to 14 Extended IO Pins 4 3VIO SPI Pins Flash Up to 8K 16 bit Free running timer 12 bit Timer Page 2 of 83 Feedback 3 Introduction Cypress has reinvented its leadership position in the low speed USB market with a new family of innovative microcontrollers Introd
107. ndicating a write failure The EraseBlock function is only useful as the first step in programming When a block is erased the data in the block is not one hundred percent unreadable If the objective is to obliterate data in a block the best method is to perform an EraseBlock followed by a Write Block of all zeros To set up the parameter block for the EraseBlock function correct key values must be stored in KEY1 and KEY2 The block number to be erased must be stored in the BLOCKID variable and the CLOCK and DELAY values must be set based on the current CPU speed Document 38 08035 Rev K CY7C63310 CY7C638xx Table 9 6 EraseBlock Parameters Name Address Description KEY1 0 F8h 3Ah KEY2 0 F9h Stack Pointer value when SSC is executed BLOCKID 0 Flash block number OOh 7Fh CLOCK 0 FCh Clock divider used to set the erase pulse width DELAY 0 For a CPU speed of 12 MHz set to 56h 9 5 5 ProtectBlock Function The enCoRe II devices offer Flash protection on a block by block basis Table 9 7 lists the protection modes available In this table ER and EW indicate the ability to perform external reads and writes For internal writes IW is used Internal reading is permitted by way of the instruction The ability to read by way of the SROM ReadBlock function is indicated by SR The protection level is stored in two bits according to Table 9 7 These bits are bit packed
108. ng the Sleep Timer bits of the Register Table 10 4 page 23 When the sleep time elapses sleep timer overflows an interrupt to the Sleep Timer Interrupt Vector is generated The Watchdog Timer period is automatically set to be three counts of the Sleep Timer overflow This represents between two and three sleep intervals depending on the count in the Sleep Timer at the previous WDT clear When this timer reaches three a WDR is generated The user can either clear the WDT or the WDT and the Sleep Timer When the user writes to the Reset WDT Register RES WDT the WDT is cleared If the data that is written is the hex value 0x38 the Sleep Timer is also cleared at the same time Bit 7 6 5 4 3 2 1 0 Field Reset Watchdog Timer 7 0 Read Write Ww Default 0 0 0 0 0 0 0 0 Any write to this register clears Watchdog Timer a write of 0x38 also clears the Sleep Timer Bit 7 0 Reset Watchdog Timer 7 0 12 Sleep Mode The CPU is put to sleep only by the firmware This is accomplished by setting the Sleep bit in the System Status and Control Register CPU SCR This stops the CPU from executing instructions and the CPU remains asleep until an interrupt comes pending or there is a reset event either a Power on Reset or a Watchdog Timer Reset The Low Voltage Detection circuit LVD drops into fully functional power reduced states
109. nore 1111 OUT lt 10 invalid x Ignore 1111 OUT lt 10 lt gt 2 valid x STALL 0011 Yes Bad Status 1111 OUT 2 valid 0 STALL 0011 Yes Bad Status 1111 OUT 2 valid 1 ACK 1111 0010 1 1 2 Yes Good Status STATUS OUT 0010 SETUP 210 x x junk Ignore 0010 SETUP lt 10 invalid x junk Ignore 0010 SETUP lt 10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP 0010 IN x x x STALL 0011 Yes 5 0010 OUT gt 10 x x Ignore 0010 OUT lt 10 invalid x Ignore Document 38 08035 Rev K Page 62 of 83 Feedback CY7C63310 CY7C638xx A Me IE CYPRESS PERFORM 23 Details of Mode for Differing Traffic Conditions continued Control Endpoint SIE Bus Event SIE EPO Mode Register EPO Count Register EPO Interrupt Comments Mode Token Count 00 1 Response I O MODE DVAL COUNT FIFO 0010 OUT lt 10 lt gt 2 valid x STALL 0011 Yes Status 0010 OUT 2 valid 0 STALL 0011 Yes Status 0010 OUT 2 valid 1 ACK 111 1 1 2 Yes Good Status ACK OUT STATUS IN 1011 SETUP 210 x x junk Ignore 1011 SETUP lt 10 invalid x junk Ignore 1011 SETUP lt 10 valid x ACK 1 1 0001 update
110. ntinued Parameter Description Conditions Min Typical Max Unit USB Driver Trt Transition Rise Time Ci oAp 200 pF 75 ns Tro Transition Rise Time 600 pF 300 ns TF2 Transition Fall Time CLoap 600 pF 300 ns Rise Fall Time Matching 80 125 Vers Output Signal Crossover Voltage 1 3 2 0 V USB Data Timing TpRATE Low Speed Data Rate Average Bit Rate 1 5 Mbps 1 5 1 4775 1 5225 Mbps 1 Receiver Data Jitter Tolerance To next transition 75 75 ns TDJR2 Receiver Data Jitter Tolerance To pair transition 45 45 ns Differential to EOP Transition Skew 40 100 ns TEOPR1 EOP Width at Receiver Rejects as EOP 330 ns TEoPR2 EOP Width at Receiver Accept as EOP 675 ns TEoPT Source EOP Width 1 25 1 5 us Differential Driver Jitter To next transition 95 95 ns TupJ2 Differential Driver Jitter To pair transition 95 95 ns Width of SEO during Diff Transition 210 ns Non USB Mode Driver Characteristics TrEPs2 SDATA SCK Transition Fall Time 50 300 ns GPIO Timing Tr GPIO Output Rise Time Measured between 10 and 90 50 ns Vdd Vreg with 50 pF load GPIO Output Fall Measured between 10 90 15 ns Vdd Vreg with 50 pF load SPI Timing SPI Master Clock Rate 2 2 Tssck SPI Slave Clock Rate 2 2 MHz TsckH SPI Clock High Time High for CPOL 0 Low for
111. ocked by a 4 MHz source It also generates an interrupt when the free running counter overflow occurs every 16 384 ms with a 4 MHz source This allows extending the length of the timer in software Figure 16 1 16 Bit Free Running Counter Block Diagram Overflow Interrupt Wrap Interrupt Timer Capture 16 bit Free Clock Running Counter 1024us Timer Interrupt Table 16 1 Free Running Timer Low order Byte FRTMRL 0x20 R W Bit 7 6 5 4 3 2 1 0 Field Free running Timer 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Free running Timer 7 0 This register holds the low order byte of the 16 bit free running timer Reading this register causes the high order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously For reads the actual read occurs in the cycle when the low order is read For writes the actual time the write occurs is the cycle when the high order is written When reading the Free Running Timer the low order byte must be read first and the high order second When writing the low order byte must be written first then the high order byte Table 16 2 Free Running Timer High order Byte FRTMRH 0x21 R W Bit 7 6 5 4 3 2 1 0 Field Free running Timer 15 8 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0
112. of host packets to the endpoint Note 5 Clear This bit is cleared only by the user and cannot be set by firmware Document 38 08035 Rev K Page 59 of 83 Feedback CY7C63310 CY7C638xx Bit 7 Stall Bit 6 Reserved Bit 5 NAK Int Enable _ x a CYPRESS PERFORM 21 4 Endpoint 1 and 2 Mode Table 21 4 Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45 0x46 R W Bit 7 6 5 4 3 2 0 Field Stall Reserved NAK Int Enable ACK d Mode 3 0 Transaction Read Write R W R W R W R C Note 4 R W R W R W R W Default 0 0 0 0 0 0 0 0 When this bit is set the SIE stalls OUT packet if the Mode Bits are set to and the SIE stalls an IN packet if the mode bits are set to ACK IN This bit must be clear for all other modes This bit when set causes an endpoint interrupt to be generated even when a transfer completes with a NAK Unlike enCoRe enCoRe II family members do not generate an endpoint interrupt under these conditions unless this bit is set 0 Disable interrupt on NAK d transactions 1 Enable interrupt on NAK d transaction The ACK d transaction bit is set when the SIE engages in a transaction to the register s endpoint that completes with an ACK R W packet Unknown This bit is cleared by any writes to the register 0 The transaction does not complete with an ACK Bit 3 0 Mode 3 0 Unknown must read the EP1 2MODE re
113. pendently of the microcontroller m Translate the encoded received data and format the data to be transmitted on the bus m CRC checking and generation Flag the microcontroller if errors exist during transmission m Address checking Ignore the transactions not addressed to the device m Send appropriate ACK NAK STALL handshakes m Token type identification SETUP IN or OUT Set the appropriate token bit after a valid token is received m Place valid received data in the appropriate endpoint FIFOs m Send and update the data toggle bit Data1 0 m Bit stuffing and unstuffing m Suspend and Resume coordination m Verify and select Data toggle values Document 38 08035 Rev K Page 57 of 83 Feedback F CY7C63310 CY7C638xx 21 USB Device 21 1 USB Device Address Table 21 1 USB Device Address USBCR 0x40 R W Field USB Enable Device Address 6 0 Bit 7 USB Enable This bit must be enabled by firmware before the serial interface engine SIE responds to the USB traffic at the address specified in Device Address 6 0 When this bit is cleared the USB transceiver enters power down state User s firmware must clear this bit before entering sleep mode to save power 0 Disable USB device address and put the USB transceiver into power down state 1 Enable USB device address and put the USB transceiver into normal operating mode Bit 6 0 Device Address 6 0 These bits must be set by fi
114. plained more about LVD and POR Changed capture pins from P0 0 P0 1 to P0 5 P0 6 Table 6 1 on page 7 Changed table heading Removed Mnemonics and made as Register names Table 9 5 on page 16 Included of rows for different flash sizes Clock Architecture Description on page 21 Changed CPUCLK selectable options from n 0 5 7 8 to 0 5 7 Clocking on page 19 Changed ITMRCLK division to 1 2 3 4 Updated the sources to ITMRCLK Mentioned P17 is TTL enabled permanently Corrected FRT PIT data write order Updated INTCLR INTMSK registers in the register table also DC Characteristics on page 68 changed LVR to LVD included max min programmable trip points based on char data Updated the 50ma sink pins on 638xx 63903 Keep alive voltage mentioned corresponding to Keep alive current of 20uA Included Notes regarding VOL VOH on P1 0 P1 1 and TMDO spec AC Characteristics on page 69 Tspo In description column changed Phase to 0 BON Pinouts on page 4 Removed the VREG from the CY7C63310 and CY7C63801 Removed SCLK and SDATA Created a separate pinout diagram for the CY7C63813 Added the GPIO Block Diagram Figure 14 1 on page 36 Table 10 4 on page 23 Changed the Sleep Timer Clock unit from 32 kHz count to Hz Table 21 1 on page 58 Added more descriptions to the register 341277 See ECN Corrected Vi TTL value in DC Characteristics page 68 Updated V TTL value Added footnote to pin description
115. r capture timers 0 The time of the most recent edge is held in the Capture Timer Data Register If multiple edges have occurred since reading the capture timer the time for the most recent one is read 1 The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read Subsequent edges are ignored until the Capture Timer Data Register is read Bit 6 4 8 bit Capture Prescale 2 0 This field controls which 8 bits of the 16 Free Running Timer are captured when in bit mode 000 capture timer 7 0 001 capture timer 8 1 0 1 0 capture timer 9 2 011 timer 10 3 100 timer 11 4 10 1 capture 12 5 110 capture 13 6 111 capture timer 14 7 Bit 3 16 bit Enable 0 Capture 0 16 bit mode is disabled 1 Capture 0 16 bit mode is enabled Capture 1 is disabled and the Capture 1 rising and falling registers are used as an extension to the Capture 0 registers extending them to 16 bits Bit 2 0 Reserved Document 38 08035 Rev K Page 46 of 83 Feedback Table 16 12 Capture Interrupt Enable TCAPINTE 0x2B R W CY7C63310 CY7C638xx Bit 7 6 5 4 3 2 1 0 Field Reserved Cap1 Fall Cap1 Rise Fall Rise Enable Enable Enable Enable Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 4 Reserved Bit 3
116. ram Counter 7 0 1 ene 00000000 CPU_PCH Program Counter 15 8 wenn 00000000 CPU_SP Stack Pointer 7 0 1 ean 00000000 CPU_F Reserved XOl Super Carry Zero Global IE brwww 00000010 FF CPU_SCR GIES Reserved WDRS PORS Sleep Reserved Reserved Stop r ccb b 00010000 1 0 OSC_CRO Reserved No Buzz Sleep Timer 1 0 CPU Speed 2 0 bbbbbb 00000000 1 LVDCR Reserved PORLEV 1 0 Reserved VM 2 0 bb bbbb 00000000 1EB TR Sleep Duty Cycle 1 0 Reserved bb 00000000 1E4 VLTCMP Reserved LVD PPOR rr 00000000 Legend In the R W column b Both Read and Write r Read Only w Write Only c Read Clear Unknown d calibration value Must not change during normal use Document 38 08035 Rev K Page 66 of 83 Feedback EE CYPRESS PERFORM 25 Voltage Vs CPU Frequency Characteristics CY7C63310 CY7C638xx Figure 25 1 Voltage vs CPU Frequency Characteristics A 5 50 4 75 Vdd volts 4 00 93 KHz 12 MHz 24 MHz CPU Frequency Running the CPU at 24 MHz requires a minimum voltage of 4 75 This applies to any CPU speed above 12 MHz so using an external clock between 12 24 MHz must also adhere to this requirement Operating the CPU at 24MHz when the supply voltage is below 4 75V can cause undesired behavior and must be avoided Many enCoRe II applications use USB Vbus 5V as the power source for the device According to the USB specifi
117. register When Capture 0 is in 16 bit mode this register holds the high order 8 bits of the 16 bit timer from the last Capture 0 rising edge Table 16 5 Timer Capture 0 Falling TIOOF 0x24 R W Bit 7 6 5 4 3 2 1 0 Capture 0 Falling 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Capture 0 Falling 7 0 This register holds the value of the Free running Timer when the last falling edge occurred on the TIOO input When Capture 0 is in 8 bit mode the bits that are stored here are selected by the Prescale 2 0 bits in the Timer Configuration register When Capture 0 is in 16 bit mode this register holds the lower order 8 bits of the 16 bit timer Table 16 6 Timer Capture 1 Falling TIO1F 0x25 R W Bit 7 6 5 4 3 2 1 0 Field Capture 1 Falling 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Capture 1Falling 7 0 This register holds the value of the Free running Timer when the last falling edge occurred on the 1 input in the 8 bit mode The bits that are stored here are selected by the Prescale 2 0 bits in the Timer Configuration register When capture 0 is in 16 bit mode this register holds the high order 8 bits of the 16 bit timer from the last Capture 0 falling edge Table 16 7 Programmable Interval Timer Low PITMRL 0x26 3 2 6 5 4 Prog
118. rmware during the USB enumeration process that is SetAddress to the nonzero address assigned by the USB host 21 2 Endpoint 0 1 and 2 Count Table 21 2 Endpoint 0 1 and 2 Count 2 0x41 0x43 0x45 R W Bit 7 6 5 4 3 2 1 0 Field Data Toggle Data Valid Reserved Byte Count 3 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 Data Toggle This bit selects the DATA packet s toggle state For IN transactions firmware must set this bit to select the transmitted Data Toggle For OUT or SETUP transactions the hardware sets this bit to the state of the received Data Toggle bit 0 DATAO 1 DATA1 Bit 6 Data Valid This bit is used for OUT and SETUP tokens only This bit is cleared to 0 if CRC bitstuff or PID errors have occurred This bit does not update for some endpoint mode settings 0 Data is invalid If enabled the endpoint interrupt occurs even if invalid data is received 1 Data is valid Bit 5 4 Reserved Bit 3 0 Byte Count Bit 3 0 Byte Count Bits indicate the number of data bytes in a transaction For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO Valid values are 0 to 8 inclusive For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus 2 for the CRC bytes Valid values 2 10 in
119. rrupt to inform the processor about the low voltage event POR and LVD share the same interrupt There is no separate interrupt for each The Watchdog timer may be used to ensure the firmware never gets stalled in an infinite loop Document 38 08035 Rev K CY7C63310 CY7C638xx The microcontroller supports 22 maskable interrupts in the vectored interrupt controller Interrupt sources include a USB bus reset LVR POR a programmable interval timer a 1 024 ms output from the free running timer three USB endpoints two capture timers four GPIO Ports three Port 0 pins two SPI a 16 bit free running timer wrap an internal sleep timer and a bus active interrupt The sleep timer causes periodic interrupts when enabled The USB endpoints interrupt after a USB transaction complete is on the bus The capture timers interrupt when a new timer value is saved because of a selected GPIO edge event A total of seven GPIO interrupts support both TTL or CMOS thresholds For additional flexibility on the edge sensitive GPIO pins the interrupt polarity is programmed as rising or falling The free running 16 bit timer provides two interrupt sources the 1 024 ms outputs and the free running counter wrap interrupt The programmable interval timer provides up to 1 usec resolution and provides an interrupt every time it expires These timers are used to measure the duration of an event under firmware control by reading the desired timer at the start and at
120. rs and is synchronized by the neg ative edge of the 32 kHz clock 2 Atthe following positive edge of the 32 kHz clock the system wide PD signal is negated The Flash memory module internal oscillator EFTB and bandgap circuit are all powered up to a normal operating state Document 38 08035 Rev K 3 At the following positive edge of the 32 kHz clock the current values for the precision POR and LVD have settled and are sampled 4 At the following negative edge of the 32 kHz clock after about 15 uS nominal the signal is negated by the sleep logic circuit On the following CPUCLK is negated by the CPU and instruction execution resumes Note that in Figure 12 2 on page 30 fixed function blocks such as Flash internal oscillator EFTB and bandgap have about 15 start up The wakeup times interrupt to CPU operational range from 75 uS to 105 US Page 29 of 83 Feedback 12 3 Low Power Sleep Mode To achieve the lowest possible power consumption during suspend or sleep the following conditions must be observed in addition to considerations for the sleep timer 1 All GPIOs must be set to outputs and driven low Clear P11CR 0 PTOCR 0 during USB and Non USB opera tions Clear the USB Enable USBCR 7 during USB mode opera tions Set PTOCR 1 during non USB mode operations Make sure 32 kHz oscillator clock is not selected as clock source to ITMRCLK TCAPCLK Not eve
121. rt 22 0058h Reserved 23 005Ch Reserved 24 0060h Reserved 25 0064h Sleep Timer Document 38 08035 Rev K CY7C63310 CY7C638xx 17 1 Architectural Description An interrupt is posted when its interrupt conditions occur This results in the flip flop in Figure 17 1 on page 51 clocking in a 1 The interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate INT CLRx register A posted interrupt is not pending unless it is enabled by setting its interrupt mask bit in the appropriate INT MSKx register All pending interrupts are processed by the Priority Encoder to determine the highest priority interrupt which is taken by the M8C if the Global Interrupt Enable bit is set in the CPU F register Disabling an interrupt by clearing its interrupt mask bit in the INT MSKx register does not clear a posted interrupt nor does it prevent an interrupt from being posted It prevents a posted interrupt from becoming pending Nested interrupts are accomplished by re enabling interrupts inside an interrupt service routine To do this setthe IE bit in the Flag Register A block diagram of the enCoRe II Interrupt Controller is shown in Figure 17 1 on page 51 Page 50 of 83 Feedback CY7C63310 CY7C638xx Interrupt Vector Interrupt Request M8C Core Priority Encoder Figure 17 1 Interrupt Controller Block Diagram CYPRESS Pending In
122. ructions which manage the software stack It is also affected by the SWAP and ADD instructions The Flag Register CPU F has three status bits Zero Flag bit Carry Flag bit 2 Supervisory State bit 3 The Global Interrupt Enable bit 0 globally enables or disables interrupts The user cannot manipulate the Supervisory State status bit 3 The flags are affected by arithmetic logic and shift operations The manner in which each flag is changed is dependent upon the instruction being executed such as AND OR XOR and others See Table 8 1 on page 12 Page 7 of 83 Feedback F CY7C63310 CY7C638xx 7 CPU Registers The CPU registers in enCoRe Il devices are two banks with 256 registers in each bank Bit 4 XIO bit in the CPU Flags register must be set cleared to select between the two register banks Table 7 1 on page 8 7 1 Flags Register The Flags Register is set or reset only with logical instruction Table 7 1 CPU Flags Register CPU_F R W Bit 7 6 5 4 3 2 1 0 Field Reserved Super Carry Zero Global IE Read Write R W R RW RW RW Default 0 0 0 0 0 0 1 0 Bit 7 5 Reserved Bit 4 Set by the user to select between the register banks 0 Bank 0 1 Bank 1 Bit 3 Super Indicates whether the CPU is executing user code or Supervisor Code This code cannot be accessed directly by the user 0 User Code 1 Supervisor Code Bit 2 C
123. s input and output direction is NOT automatically set it must be explicitly set by firmware For SPI Master mode pin P1 4 must be configured as an output for SPI Slave mode pin P1 4 must be configured as an input Table 14 15 P1 7 Configuration P17CR 0x14 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low Reserved High Sink Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 1 0 This register controls the operation of pin P1 7 This register only exists in CY7C638 1 2 3 3 The P1 7 GPIO s threshold is always set to TTL Table 14 16 P2 Configuration P2CR 0x15 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 This register only exists in CY7C638 2 3 3 This register controls the operation of pins 2 0 2 1 Document 38 08035 Rev K Page 39 of 83 Feedback CY7C63310 CY7C638xx 15 Serial Peripheral Interface SPI SPI is a four pin serial interface comprised of a clock an enable and two data pins PERFORM Table 14 17 P3 Configuration P3CR 0x16 R W Bit 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low TTL Thresh Reserved Open Drain Pull up Enable Output
124. s the corresponding hardware interrupt 17 5 1 Interrupt Mask Registers The Interrupt Mask Registers INT_MSKx enable the individual interrupt sources ability to create pending interrupts There are four Interrupt Mask Registers INT MSKO INT MSK1 INT MSK2 INT MSK3 which may be referred to in general as INT MSKx If cleared each bit in an INT MSKx register prevents a posted interrupt from becoming a pending interrupt input to the priority encoder However an interrupt can still post even if its mask bit is zero All INT MSKx bits are independent of all other INT MSKx bits If an INT MSKx bit is set the interrupt source associated with that mask bit may generate an interrupt that becomes a pending interrupt Document 38 08035 Rev K The Enable Software Interrupt ENSWINT bit in INT MSK3 T7 determines the way an individual bit value written to an INT CLRx register is interpreted When it is cleared writing 1 s to an INT CLRx register has no effect However writing O s to an INT CLRx register when ENSWINT is cleared causes the corresponding interrupt to clear If the ENSWINT bit is set any 05 written to the INT CLRx registers are ignored However 1s written to an INT CLRx register when ENSWINT is set causes an interrupt to post for the corresponding interrupt Software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level interac tions that are sometimes ne
125. ssignment tables and Ordering information Keyboard references removed CY7C63923 XC die diagram removed removed references to the 639xx parts Updated part numbers in the header See ECN Minor text changes 32 QFN part added Removed GPIO port 4 configuration details Removed all residual references to external crystal oscillator and GPIO4 Documented the dedicated 3 3V regulator for USB transceiver Documented bandgap voltage regulator behavior on wake up See ECN H 504691 Voltage regulator line load regulation documented GPIO capacitance and timing diagram included Method to clear Capture Interrupt Status bit discussed Sleep and Wake up sequence documented Minor text changes USB Active and PS2 Data low interrupt trigger conditions documented EP1MODE EP2MODE register issue discussed TYJ Removed 638xx die diagram and die form pad assignment Corrected GPIO characteristics of P0 0 and 1 to P1 0 and P1 1 respectively Document 38 08035 Rev K Page 81 of 83 Feedback CYPRESS Orig of 32 Document History Page continued Submission Date 05 20 2008 on GPIO pins to 2mA source current on all GPIO pins of Vcc3 line 3 to 4 0 and 5 5 respectively TID number entered on page 1 Also changed the sentence High current drive Point 26 0 DC Characteristics on page 68 changed the min and max voltages Point 19 0 title modified to Regulator Outpu
126. struction Set Summary Sorted Numerically by Opcode Order 31 Hlal g E 2 3 5 instruction Format Flags Instruction Format Flags Instruction Format Flags 00 15 1 55 20 8 2 OR Z 5 2 MOV expr X 01 4 2 ADDA expr CZ 2bE 9 expr expr Z 5B 4 1 MOV A X 7 02 6 2 ADD A expr CZ 2F 10 3 OR X expr expr 2 5C 4 1 MOVX A 03 7 2 CZ 9 1 HALT 5D 6 2 MOVA reg expr 2 04 7 2 expr CZ 4 2 XORA expr 5E 7 2 MOVA reg X expr 2 05 8 2 ADD X expr A CZ 6 2 expr 10 3 MOV expr expr 06 9 3S ADD expr expr CZ 7 2 XORA X expr 60 5 2 MOV 07 10 3 ADD X expr expr CZ 7 2 XOR expr A 61 6 2 MOV reg X expr A 08 4 8 2 XOR A 62 8 S3 MOV reg expr expr 09 4 2 expr CZ 9 3 XOR expr expr 63 9 S3 MOV reg X expr expr 6 2 expr CZ 0 3 XOR expr 64 4 1 ASLA CZ OB 7 2 ADC A CZ 5 2 ADD SP expr 65 7 2 ASL expr CZ 0 7 2 ADC expr A CZ 5 2 expr 66 8 2 ASL X expr CZ 00 8 2 ADC A 2 7 2 2 1 67 4 1 ASRA 2 9 3 expr CZ 8 2 CMP A if A lt B C 1 68 7 2 ASR expr 2 OF 10 3 ADC X expr expr CZ 8 3 CMP expr expr 69 8 2 A
127. structions using this addressing mode are two bytes in length Table 7 9 Source Indexed Opcode Operand 1 Instruction Source Index Examples ADD JA X 7 The value in the memory location at address X 7 is added with the Accumulator and the result is placed in the Accumulator MOV X REG X 8 The value in the register space at address X 8 is moved to the X register Document 38 08035 Rev K CY7C63310 CY7C638xx 7 2 4 Destination Direct The result of an instruction using this addressing mode is placed within the RAM memory space or the register space Operand 1 is an address that points to the location of the result The source for the instruction is either the A register or the X register which is specified as part of the instruction opcode Arithmetic instruc tions require two sources the second source is the location specified by Operand 1 Instructions using this addressing mode are two bytes in length Table 7 10 Destination Direct Opcode Operand 1 Instruction Destination Address Examples ADD 7 A The value in the memory location at address 7 is added with the Accumu lator and the result is placed in the memory location at address 7 The Accumulator is unchanged MOV REG 8 A The Accumulator is moved to the register space location at address 8 The Accumulator is unchanged 7 2 5 Destination Indexed The result of a
128. supply voltage dips below 4 75V and the application can tolerate running at a CPU speed of 12 MHz then application firmware may also implement the following to minimize the chance of a reset event due to a voltage transient m Set the LVD for one of the desired high setting 4 73 or 4 82 Enable the LVD interrupt m in the LVD ISR reduce CPU speed to 12 MHz and shift the POR to a lower threshold m Firmware can monitor for VLTCMP to clear within the normal application main loop m Debounce the indication to ensure voltage is above the set point m Shift the POR to the high set point m Shift the CPU to 24 MHz Page 67 of 83 Feedback mE c 7 2 CYPRESS PERFORM CY7C63310 CY7C638xx Maximum Total Sink Current into Port 0 and Port 1 erat 70 mA Maximum Total Source Output Current into GPIO Pins30 mA Maximum On chip Power Dissipation 26 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device User guidelines are not tested Storage Temperature 40 to 90 C on any Pin 50 mW Ambient Temperature with Power Applied 0 to 70 C Power Dissipation esses 300 mW Supply Voltage on Vcc Relative to Vss 0 5V to 7 0V Static Discharge Voltag
129. t instead of USB Regulator CY7C63310 CY7C638xx Description of Change Document Number 38 08035 Change VGT AESA ECN No e PERFORM Document Title CY7C63310 CY7C638xx enCoRe Il Low Speed USB Peripheral Controller Output Changed the storage temperature to 40 to 90C in Point 25 0 Absolute Rev 2147747 J Added a point 3 under Point 17 3 In line 3 under Bit 2 P1 2 VREG of Table 14 2 on page 34 the changes made Maximum Ratings on page 68 Added the die form after the end of page 4 were CY7C63310 CY7C638xx instead of CY7C63813 In line 1 under Bit 6 USB CLK 2 Disable of Table 10 3 on page 22 entered the word clock instead of crystal oscillator sub table under Bit 2 0 VM 2 0 of Table 13 1 on page 31 Under Bit 7 6 Sleep Duty Cycle 1 0 made the following changes 0 0 1 128 periods of the internal 32 kHz low speed oscillator 0 1 1 512 periods of the internal 32 kHz low speed oscillator Entered the word Reserved and left its corresponding fields blank in the 1 0 1 32 periods of the internal 32 kHz low speed oscillator 1 1 1 8 periods of the internal 32 kHz low speed oscillator In Table 17 3 on page 52 in line 4 deleted 57 and made the word AND to information Added 32 Pin Sawn QFN Pin Diagram package diagram and ordering Removed references to 3V for the 32 kHz oscillator in Section 10 Clocking P1DATA register infor
130. t is set it indicates that the GIE bit in the CPU_F register is also set which in turn indicates that the microprocessor services interrupts 0 Global interrupts disabled 1 Global interrupt enabled Bit 6 Reserved Bit 5 WDRS The WDRS bit is set by the CPU to indicate that a WDR event has occurred The user can read this bit to determine the type of reset that has occurred The user can clear but not set this bit 0 No WDR 1 A WDR event has occurred Bit 4 PORS The PORS bit is set by the CPU to indicate that a POR event has occurred The user can read this bit to determine the type of reset that has occurred The user can clear but not set this bit 0 No POR 1 A POR event has occurred Note WDR events do not occur until this bit is cleared Bit 3 SLEEP Set by the user to enable CPU sleep state CPU remains in sleep mode until any interrupt is pending The Sleep bit is covered in more detail in the section Sleep Mode on page 28 0 Normal operation 1 Sleep Bit 2 1 Reserved Bit 0 STOP This bit is set by the user to halt the CPU The CPU remains halted until a reset WDR POR or external reset has taken place If an application wants to stop code execution until a reset the preferred method is to use the HALT instruction rather than writing to this bit 0 Normal CPU operation 1 CPU is halted not recommended Note 4 Clear This bit is cleared only by the user and cannot be set by firmware Do
131. table for 0 0 pins Added Typical Values to Low Voltage Detect table Corrected Pin label on 16 pin PDIP package Corrected minor typos F 408017 TYJ See Table 5 2 on page 6 Corrected pin assignment for the 24 pin QSOP package GPIO port 3 New Assignments Pin 19 assigned to P3 0 and pin 20 to P3 1 Table 17 7 on page 54 INT MASK1 changed to OxE1 Table 17 8 on page 55 INT MASKO changed to OxEO Register Summary on page 64 Register Summary address EO assigned to INT MASKO and address E1 assigned to INT MASK1 Page 80 of 83 Feedback Document 38 08035 Rev K CYPRESS 32 Document History Page continued Submission Orig of Date See ECN CY7C63310 CY7C638xx Description of Change Minor text changes to make document more readable Removed CY7C639xx from Ordering Information on page 75 Corrected Figure 9 2 on page 15 to represent single stack Document Number 38 08035 Change ECN No TYJ e PERFORM Document Title CY7C63310 CY7C638xx enCoRe Low Speed USB Peripheral Controller Added text concerning current draw for P0 0 and P0 1 in Table 5 2 on 6 Removed CY7C639xx Added comment about availability of 3 3V 10 on P1 3 P1 6 in Table 5 2 on page Added information on Flash endurance and data retention to section Flash on 6 Rev 424790 page 14 Added block diagrams and timing diagrams G TYJ 491711 Added CY7C638xx die form diagrams Pad a
132. terrupt CPU 0 GIE 6 The ISR ends with a RETI instruction which restores the Program Counter and Flag registers CPU PC and CPU F The restored Flag register re enables interrupts because InterruptTaken INT_CLRxWrite Posted Interrupt Interrupt Source Timer INT_MSKx Mask Bit Setting GIE 1 again However GP10 etc 7 Execution resumes at the next instruction after the one that occurred before the interrupt However if there are more pending interrupts the subsequent interrupts are processed before the next normal program instruction 17 3 Interrupt Trigger Conditions Trigger conditions for most interrupts in Table 17 1 on page 50 have been explained in the relevant sections conditions under which the USB Active interrupt address 0030h and PS2 Data Low interrupt address 004Ch interrupts are 17 2 Interrupt Processing The sequence of events that occur during interrupt processing a The interrupt condition occurs for example a timer expires triggered are explained follow 1 USB Active Interrupt Triggered when the D lines are non idle state that is K state or SEO state 2 PS2 Data Low Interrupt Triggered when SDATA becomes low when the SDATA pad is in the input mode for at least 6 7 follows 1 An interrupt becomes active because b A previously posted interrupt is enabled through an update of an interrupt mask register An interrupt is pending and GIE is
133. that interface at a voltage level of 3 3V Additionally each may be used to generate a GPIO interrupt to the microcontroller Each GPIO port has its own GPIO interrupt vector in addition GPIO Port 0 has three dedicated pins that have independent interrupt vectors 0 2 P0 4 The enCoRe II features an internal oscillator With the presence of USB traffic the internal oscillator may be set to precisely tune to USB timing requirements 24 MHz 1 5 Optionally an external 12 MHz or 24 MHz clock is used to provide a higher precision reference for USB operation The clock generator provides the 12 MHz and 24 MHz clocks that remain internal to the microcontroller The enCoRe II also has a 12 bit program mable interval timer and a 16 bit Free Running Timer with Capture Timer registers In addition the enCoRe II includes Watchdog timer and a vectored interrupt controller The enCoRe has up to eight Kbytes of Flash for user code and up to 256 bytes of RAM for stack space and user variables The power on reset circuit detects logic when power is applied to the device resets the logic to a known state and begins executing instructions at Flash address 0x0000 When power falls below a programmable trip voltage it generates a reset or may be configured to generate an interrupt There is a low voltage detect circuit that detects when drops below a programmable trip voltage It is configurable to generate LVD inte
134. ucing enCoRe USB enhanced Component Reduction Cypress has leveraged its design expertise in USB solutions to advance its family of low speed USB microcontrollers which enable peripheral developers to design new products with a minimum number of components The enCoRe USB technology builds on the enCoRe family The enCoRe family has an integrated oscillator that eliminates the external crystal or resonator reducing overall cost Also integrated into this chip are other external components commonly found in low speed USB applications such as pull up resistors wakeup circuitry and a 3 3V regulator Integrating these components reduces the overall system cost The enCoRe is an 8 bit Flash programmable microcontroller with an integrated low speed USB interface The instruction set is optimized specifically for USB and PS 2 operations although the microcontrollers may be used for a variety of other embedded applications The enCoRe II features up to 20 GPIO pins to support USB 5 2 and other applications The pins are grouped into four ports Port 0 to 3 The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2 and 3 are configured only as a group Each GPIO port supports high impedance inputs configurable pull up open drain output CMOS TTL inputs and CMOS output with up to five pins that support a programmable drive strength of up to 50 mA sink current GPIO Port 1 features four pins
135. ure The configuration of the WriteBlock function is straightforward The BLOCKID of the Flash block where the data is stored must be determined and stored at SRAM address FAh The SRAM address of the first of the 64 bytes to be stored in Flash must be indicated using the POINTER variable in the parameter block SRAM address FBh Finally the CLOCK and DELAY value must be set correctly The CLOCK value deter mines the length of the write pulse that is used to store the data in the Flash The CLOCK and DELAY values are dependent on the CPU speed and must be set correctly Table 9 5 WriteBlock Parameters Name Address Description KEY1 O F8h 3Ah KEY2 O F9h Stack Pointer value when SSC is executed BLOCKID O FAh 8 Flash block number 00h 7Fh 4KB Flash block number 00h 3Fh 3KB Flash block number 00h 2Fh POINTER O FBh Firstof64 addresses in SRAM where the data to be stored in Flash is located before calling WriteBlock CLOCK O FCh Clock divider used to set the write pulse width DELAY O FEh For a CPU speed of 12 MHz set to 56h 9 5 4 EraseBlock Function The EraseBlock function is used to erase a block of 64 contiguous bytes in Flash The EraseBlock function first checks the protection bits and determines if the desired BLOCKID is writable If write protection is turned on the EraseBlock function exits setting the accumulator and KEY2 back to 00h KEY1 has a value of 01h i
136. with the highest address range is erased Following the erase of the protection block zeros are written into every bit of the protection table The next lowest Flash macro in the address space then has its protection block erased and filled with zeros The end result of the EraseAll function is that all user data in the Flash is destroyed and the Flash is left in an unprogrammed state ready to accept one of the various write commands The protection bits for all user data are also reset to the zero state The parameter block values that must be set besides the keys are the CLOCK and DELAY values Table 9 9 EraseAll Parameters Name Address Description KEY1 0 F8h 3Ah KEY2 0 F9h Stack Pointer value when SSC is executed CLOCK 0 FCh Clock divider used to set the write pulse width DELAY 0 FEh For a CPU speed of 12 MHz set to 56h Document 38 08035 Rev K CY7C63310 CY7C638xx 9 5 7 TableRead Function The TableRead function gives the user access to part specific data stored in the Flash during manufacturing It also returns a Revision ID for the die not to be confused with the Silicon ID Table 9 10 Table Read Parameters Name Address Description KEY1 0 F8h 3Ah KEY2 0 F9h Stack Pointer value when SSC is executed BLOCKID 0 Table number to read The table space for the enCoRe ll is simply a 64 byte row broken up into eight tables of eight bytes The tabl
137. ypress PERFORM 5 Pinouts CY7C63801 CY7C63310 16 Pin PDIP SSEL P1 3 1 SCLK P1 4 12 SMOSI P1 5 3 SMISO P1 6 4 TIO1 PO 6 5 12 Vss TIOO PO 5 6 11 0 P0 0 INT2 P0 4 O 7 10 H1 P0 1 INT1 P0 3 L 8 9 PO 2 INTO CY7C63813 18 Pin PDIP SSEL P1 3 1 SCLK P1 4 2 5 1 5 0 3 5 1 CY7C63801 CY7C63310 16 Pin SOIC 1 6 5 5 1P1 5 5MOSI P1 4 SCLK P1 3 SSEL TIO1 PO 6 1 TIOO PO 5 2 INT2 P0 4 3 INT1 PO 3 4 INTO PO 2 O 5 0 1 6 07 Vss 8 9 O P1 0 D P0 7 O 1 TIO1 P0 6 2 TIOO PO 5 3 CY7C63310 CY7C638xx CY7C63803 16 Pin SOIC 16 O P1 6 5MISO 15 J P1 5 5MOSI 14 P1 4 SCLK 13 P1 3 SSEL TIO1 PO 6 Q 1 TIOO PO 5 2 INT2 PO 4 3 INT1 PO 3 4 INTO PO 2 Q 5 12 H1 P1 2 VREG P0 10 6 11 O Po 007 10 1 1 9 1 0 0 CY7C63813 18 Pin SOIC 17 P1 6 5MISO P1 5 SMOSI SMISO P1 6 4 15 9 1 0 0 INT2 P0 4 4 H P14 SCLK P1705 14 Vss INT1 P0 3 65 H P1 3 SSEL P0 7 6 13 720 0 INTO PO 2 6 1 2 TIO1 PO 6 7 12 P0 1 007 A TIOO PO 5 F 8 11 T P0 2 INTO 0 0 8 11 H 1 4 0 INT2 P0 4 0 9 CY7C63823 24 Pin QSOP 10 P0 3 INT1 10 1 P1 0 D CY7C63823 24 Pin SOIC NC E 1 J P1 7 Po 7 gt P1 6 SMISO NC 1 NC TIO1 PO 6
138. z 500 kHz 11 96 125 kHz 250 kHz Document 38 08035 Rev K Page 41 of 83 Feedback ZA 15 3 SPI Interface Pins The SPI interface uses the 1 3 1 6 pins These pins are configured using the P1 3 P1 4 P1 6 Configuration EN a CYPRESS PERFORM CY7C63310 CY7C638xx Table 15 4 SPI Mode Timing vs LSB First CPOL and CPHA LSB First CPHA CPOL Diagram 0 0 0 0 0 1 1 0 sse DATA x is Y 0 1 1 1 0 0 Eo shoe d sec DATA 3 igs X X X X ane X X mse X SCLK ey 1 1 0 1 1 1 Document 38 08035 Rev 42 83 Feedback j CY7C63310 CY7C638xx 16 Timer Registers All timer functions of the enCoRe Il are provided by a single timer block The timer block is asynchronous from the CPU clock 16 1 Registers 16 1 1 Free Running Counter The 16 bit free running counter is clocked by the Timer Capture Clock TCAPCLK It is read in software for use as a general purpose time base When the low order byte is read the high order byte is registered Reading the high order byte reads this register allowing the CPU to read the 16 bit value atomically loads all bits at one time The free running timer generates an interrupt at 1024 us rate when cl

Cypress CY7C63310 Network Card User Manual

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