Connect Tech 104 Network Card User Manual
Contents
1. GPIOP 31 Input Output GND Power GND Power Revision 0 00 GND power GND Power 11 Connect Tech FreeForm PCI 104 User Manual Hardware Installation Before installing the FreeForm PCI 104 into a PC 104 stack ensure the following o Slot selection properly set using the rotary switch RSW1 Note that the FreeForm PCI 104 address space consumes 32 bytes o FPGA configuration jumper J1 is set to read from Flash Once installed in the system and power is applied the LED D1 will illuminate to indicate that FreeForm PCI 104 is functioning properly Standalone Operation Operating the FreeForm PCI 104 outside of a PCI 104 stack or a PCI system for extended periods of time is not recommended The PCI to local bus bridge PLX 9056 requires the pull up pull down resistors provided on a system main board Configuring programming the FreeForm PCI 104 in standalone mode is acceptable providing it is not left powered in that state Software Installation FPGA Development Environment FreeForm PCI 104 has been developed with Xilinx WebPACK 9 2 available free of charge at http www xilinx com ise logic design prod webpack htm Drivers and Application Examples The FreeForm PCI 104 ships with a CD containing drivers for various operating systems and example programs to help quickly develop applications Refer to the CD for installation instructions For other operating systems please c2. GPIOP 4 Input Output GPIOP 20 Input Output GPION 5 Input Output GPION 21 Input Output GPIOP 5 Input Output GPIOP 21 Input Output GPION 6 Input Output GPION 22 Input Output GPIOP 6 Input Output GPIOP 22 Input Output GPION 7 Input Output GPION 23 Input Output GPIOP 7 Input Output GPIOP 23 Input Output GND Power GND Power GND Power GND Power GPION 8 Input Output GPION 24 Input Output GPIOP 8 Input Output GPIOP 24 Input Output GPION 9 Input Output GPION 25 Input Output GPIOP 9 Input Output GPIOP 25 Input Output GPION 10 Input Output GPION 26 Input Output GPIOP 10 Input Output GPIOP 26 Input Output GPION 11 Input Output GPION 27 Input Output GPIOP 11 Input Output GPIOP 27 Input Output GND Power GND Power GND Power GND Power GPION 12 Input Output GPION 28 Input Output GPIOP 12 Input Output GPIOP 28 Input Output GPION 13 Input Output GPION 29 Input Output GPIOP 13 Input Output GPIOP 29 Input Output GPION 14 Input Output GPION 30 Input Output GPIOP 14 Input Output GPIOP 30 Input Output GPION 15 Input Output GPION 31 Input Output GPIOP 15 Input Output
3. E gt Add Device zl Revision 0 00 18 Connect Tech FreeForm PCI 104 User Manual Add Device Look in E init pl GPIO25 e A ef ES L 3 ngo EG 5 _xmsgs My Recent 5 templates Documents set 3 Desktop a Hee ter My Network File name init bit Places Files of type FPGA Bit Files bit D 6 Click No when asked if another device is to be added Click OK to accept the setup 7 Double Click Generate File from the iMPACT processes menu The status will be reported in the console IMPACT Processes Available Operations are Generate File Operations BATCH CMD setMode pff BATCH CMD setSubmode pffparallel BATCH CMD setAttribute configdevice attr fillValue value FF BATCH CMD setAttribute configdevice attr swapBit value true BATCH CMD setAttribute configdevice attr fileFormat value mcs BATCH CMD setAttribute configdevice attr dir value UP Ef BATCH CMD setAttribute configdevice attr path value m ee e NEN Wen PM bi _plx GPIOZ25X BATCH CMD setAttribute configdevice attr name value init plx GPIO25 cs Total configuration bit size 9371136 bits Total configuration byte size 1171392 bytes BATCH CMD setCurrentDesign version 0 BATCH CMD generate spi Swap bit can only be disabled in Hex file format only OxlldfcO 1171392 bytes loaded
4. 8 30 a m to 5 00 p m Eastern Standard Time Our numbers for calls are Telephone 800 426 8979 North America only Telephone 519 836 1291 Live assistance available 8 30 a m to 5 00 p m EST Monday to Friday Facsimile 519 836 4878 on line 24 hours Email Internet You may contact us through the Internet Our email and URL addresses are sales 9 connecttech com support connecttech com www connecttech com Mail Courier You may contact us by letter and our mailing address for correspondence is Connect Tech Inc 42 Arrow Road Guelph Ontario Canada NIK 1S6 Revision 0 00 3 Connect Tech FreeForm PCI 104 User Manual Table of Contents Limited Rate tine Warr any ee 2 Copyright NOUCE Em 2 Trademark Acknowledetrieut EE 2 Customer Support RE TE 3 Contact Information 2 0 m 3 Tablero Contents ii ds 4 et rk Tal ii A 3 EECHER 5 Ee 6 ESAS aah oo Siesta NEED A US apie ands cR tu DADO eine ads dead tuo IO CE 6 Hardware Description and Cont UTA A a 8 Junipers and Mis e eo bo 8 SOE SEE CON RO A T T UT o 8 EPGA Contbutalion Settings JI octanos 8 GoOmector Di MH tas 9 PERITOS Header P Dus EE 9 FEAG Prosrtamiung Header P2 EE 9 SPL Flash Programming Header P iussit rtl tuoque isa Rd laicis abus 9 E5455 Headers P5 PO uode ios 10 External Power Connector Point 10 GPIO Header P EE 11 HardWare he Ee EE 12 tanda OP latas 12 EEN 12 FPGA Development E
5. Query Do vou have a BSDL or BIT file for this device Cancel ES My Recent Type BSDL File Documents Date Modified 2007 10 26 4 31 PM f Size 16 3 KB Deskto Mu Documents Mu Computer ei My Network File name bsd m Places Files of type Boundary Scan Files bsd e Cancel Revision 0 00 Connect Tech FreeForm PCI 104 User Manual 6 iMPACT will add the device to the JTAG chain E m xc5vix3 t pciarsb5ba r1 unknown init bit pcianssba bzd file 7 TD 7 Again a prompt will ask for device number three National PHY Browse to the bsdl folder and select DP83849IVS bsd The device will be added to the JTAG chain TDI xc5vIx30t pcianssba r1 dpa3a43i init ott pcianseba bsd dpa3a48iva bad TD 8 To test stream integrity right click on the FPGA and select Get Device ID The console will report IDCODE 82a6e093 Tol Program Verify xcov Get Device ID init bt e e d TDO Get Device Signature Usercode Add SPI Flash Add BPI Flash Assign New Configuration File BATCH CMD Readldcode p 1 Maximum TCE operating frequency for this device chain 10000000 Validating chain Boundary scan chain validated successfully O Device Temperature Current Reading 273 00 C O VCCIMT Supply Current Reading 0 000 Y O VCCAUX Supply Current Reading 0 000 Y 1 IDCODE is 10000010101001101110000010010011 1 IDCODE
6. is 202015 in hex ID Check passed Erasing Device Programming Device Reading device contents Verification completed iMPACT l Checking done pin done Programmed successfully iMPACT 1 Checking done pin done Programmed successfully PROGRESS END End Operation Elapsed time 179 sec Revision 0 00 23 Connect Tech FreeForm PCI 104 User Manual Reference Design The FreeForm PCI 104 ships with a pre installed reference design This reference design demonstrates how the FPGA interacts with the PLX 9056 PLX to local bus bridge Functionality o Local bus interface driven at 50MHz o Slave access to o BAR2 16x32 bit control registers 16x32 bit user memory o BAR3 SPI flash programming interface o Master access to same 16x32 user memory as located in BAR2 Transfer controlled through slave accessible registers o Local bus master configuration of bridge happens automatically with reset Single ended GPIO control through registers o LED control through registers O Memory Map Table 10 Bar Local Address Space 0 Bar 2 00000000 INTERRUPT_MASK R W Bit 0 Direct master state machine Bit 1 SPI programmer 00000004 INTERRUPT SOURCE Bit 0 Direct master state machine Bit 1 SPI programmer 00000008 REG2 RW UNED 0000000C REG3 E usi 00000010 GPIO P OUT W Each bit corresponds to one GPIO pin output Direction must be set to output Bit GPIO_P 00000014 GPIO_P_TRI W E
7. is S8za656en95 in hex ir Manufacturer s ID Xilinx xc5vlx3 t Version 8 Revision 0 00 15 Connect Tech FreeForm PCI 104 User Manual Programming the FPGA 1 Right click on device number one Virtex 5 FPGA and select program The following diagram will appear Note that verification will only work if an msk file has been created Ep rogramming Properties Category SN Programming Properties Advanced PROM Programming Properties Revision Properties Verify General CPLO And PROM Properties Erase Before Programming Head Fratect PFRHBM EaaslRunnerll Usercode 8 Hes Digits CPLO Specific Properties nte Protect Functional Teszt Dn The Fly Program SPLA UES Enterup to 13 characters EEE PROM Specific Properties Load FPGA Parallel Mode Use D4 for CF Spartan3 M Programming Properties Data Protect Data Lockdown FPGA Device Specific Programming Properties Pulse PROG Program Key Assert Cable INIT during programming 2 Select OK to begin programming After programming is complete the status window will report INFO INFO INFO d A dn We INFO iMPACT 2219 Status register values iMPACT 0011 1111 1001 1110 0000 1010 1110 0000 iMPACT 1 Checking done pin done Programmed successfully Verifying device IMFO iMPACT z2502 Complete word count is 93637443 32 2292517 done e INFO INFO b doses iMPACT 24295 Readback Size is 9363744 Ver
8. out side of a PCI PCI 104 system Table 8 External Power Connector Pinout P8 3 3 enable connect to 5V VIO connect to 5V It is recommended that a Connect Tech Inc FreeForm PCI 104 power supply is used Orientation of the power supply connector is important Ensure that the clip on the cable aligns with the catch on P as shown below e SUL yk Figure 3 External Power Connection Revision 0 00 10 Connect Tech FreeForm PCI 104 User Manual GPIO Header P7 The GPIO header has been design such that when in differential mode the positive P and negative N signals are adjacent on a standard ribbon cable Note that the GPIO voltage level is set via hardware FCG001 has L12 populated enabling 2 5V I O including LVDS FCG002 has L13 populated enabling 3 3V I O GPION 0 Table 9 GPIO Header Pinout Input Output GPION 16 Input Output GPIOP 0 Input Output GPIOP 16 Input Output GPION 1 Input Output GPION 17 Input Output GPIOP 1 Input Output GPIOP 17 Input Output GPION 2 Input Output GPION 18 Input Output GPIOP 2 Input Output GPIOP 18 Input Output GPION 3 Input Output GPION 19 Input Output GPIOP 3 Input Output GPIOP 19 Input Output O CO otn iur GND power GND Power GND Power GND Power GPION 4 Input Output GPION 20 Input Output
9. up from 0x0 Using user specified prom size of 2048K Writing file C iNDataMProjectsNFreeFormPCIl104NhardwareMlogicNinit plx GPIO25M init pls GPIO25 mcs Writing file C Data Projects FreeFormPC1I104 hardware logic init_plx_GPI025 init_plx_GPI025 prm Revision 0 00 19 Connect Tech FreeForm PCI 104 User Manual Configuring the FPGA with the SPI Flash In previous Xilinx FPGA configurations the SPI flash would require programming via 3 party JTAG test software or through in system methods The following features are new to ISE 9 1 9 2 and are only available on select FPGAs including the Virtex 5 Your FreeForm PCI 104 card featuring the Xilinx Virtex 5 FPGA includes a standard core to enable programming of BPI and SPI flashes over JTAG Configuring the FPGA SPI flash Association 1 Select Boundary Scan from the Flows tab PA Boundary Scan Sal Slaves erial ee SelecthAP Sa lDesktop Configuration Sa Direct SPI Configuration SystemACE PROM File Formatter Modes 2 Right click on the FPGA and select Add SPI Flash TDI E UNK Eo Program verify xciv Get Device ID init 36451 Sive bed DO Get Device Signature Usercode 4dd SPI Flash Add BPI Flash Assign Mew Configuration File Revision 0 00 20 Connect Tech FreeForm PCI 104 User Manual 3 Browse to the directory containing the previously generated MCS file Select
10. upto 13 characters Od PROM Specific Properties Load FPGA ParallelMode Use D4 for CF Spartan dan Programming Properties Data Protect Data Lockdown FPGA Device Specific Programming Properties Pulse PROG Program Key Assert Cable INIT during programming Revision 0 00 P9 Connect Tech FreeForm PCI 104 User Manual 3 Observe the results in the transcript window a The SPI core is first download to the FPGA device b The IDCODE is checked and verified c Flash is erased d Flash is programmed After completion of the flash programming the FPGA will attempt to configure itself from the flash If the SPI flash setting is not selected with J1 this step will fail This does not mean the flash is not programmed but rather the verification of the programmed contents has failed Van tus SPI access core not detected SPI access core will be downloaded to the device to enable operations PROGRESS START Starting Operation Ite done V s INEO INFO INFO INEO E LEE Ite Poss ue E Ve ps AUR done its INFO Ve KA INFO Va E Downloading core Reading status register contents iMPACT 2219 Status register values iMPACT 0011 1111 1001 1110 0000 1010 1000 0000 iMPACT 2492 1 Completed downloading core to device iMPACT l s Checking done ins done Core downloaded successfully IDCODE is Z02015 fin hex ID Check passed IDCODE
11. 256 Bytes of for flash page storage 100001FC Implementation Refer to the FreeForm PCI 104 VHDL Reference Design Application Note for further information Revision 0 00 Connect Tech FreeForm PCI 104 User Manual Specifications Programmable FPGA Virtex 5 FPGA LX30T Input Clock 100MHz Memory 8MB Flash 128MB DDR2 400 General Purpose User I O 64 single ended I O 32 LVDS I O Serial 2 x RS 485 Ethernet 2 x IOBase T 100Base TX Operating Environment Storage Temperature 65 C to 150 C Operating Temperature 0 C to 70 C commercial 40 C to 85 C industrial Power Requirements 3 3V DC and 5V DC in PCI 104 stack 5V DC standalone Current requirements are configuration dependant Dimensions PC 104 Plus 2 2 compliant PCI 104 1 0 compliant Connectors Revision 0 00 Two RJ 45 modular jacks Ethernet Two 2x5 0 100 headers serial One 2x40 0 050 x 0 100 header general I O One 1x6 0 100 header flash programming 26
12. Connect Tech Inc Industrial Strength Communications FreeForm PCI 104 User Manual sai wvoun AA MIC 24121 5308 oj 1 it Lan NH721 LF3 ST J LEE R UE CUR i d 3 E IHE C2412 UHTI g P 21421 PL ta IS a E 1 TEES 2 JM Li un O KEY IER BE LG lat e TITRE d IO c O j Bis S9 0o x A X AC UNN VIRTEX 4 XC5VLX30T f FRGAf cespem ol Salsa 7 T EPI d v Kl sr 1 hl L AUREA EEE ARANA DAD AV LEE EE EE L EEEE Connect Tech Inc 42 Arrow Road Guelph Ontario Canada N1K 156 Tel 519 836 1291 800 426 8979 Fax 519 836 4878 Email sales connecttech com support connecttech com URL http www connecttech com CTIM 00040 Revision 0 00 January 28 2008 Connect Tech FreeForm PCI 104 User Manual Limited Lifetime Warranty Connect Tech Inc provides a Lifetime Warranty for all Connect Tech Inc products Should this product in Connect Tech Inc s opinion fail to be in good working order during the warranty period Connect Tech Inc will at its option repair or replace this product at no charge provided that the product has not been subjected to abuse misuse accident disaster or non Connect Tech Inc authorized modification or repair You may obtain warranty service by delivering this product to an authorized Connect Tech Inc business partner or to Connect Tech Inc along with proof of purchase Product returned to Connect Tech Inc must be pre authoriz
13. Inc Trademark Acknowledgment Connect Tech Inc acknowledges all trademarks registered trademarks and or copyrights referred to in this document as the property of their respective owners Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document Revision 0 00 2 Connect Tech FreeForm PCI 104 User Manual Customer Support Overview If you experience difficulties after reading the manual and or using the product contact the Connect Tech reseller from which you purchased the product In most cases the reseller can help you with product installation and difficulties In the event that the reseller is unable to resolve your problem our highly qualified support staff can assist you Our support section is available 24 hours a day seven days a week on our website at www connecttech com support support asp See the contact information section below for more information on how to contact us directly Our technical support is always free Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document Contact Information We offer three ways for you to contact us Telephone Facsimile Technical Support representatives are ready to answer your call Monday through Friday from
14. ach bit corresponds to one GPIO pin direction Output 00000018 GPIO_P_IN Each bit corresponds to one GPIO pin input Bit GPIO_P 0000001C GPIO N OUT Same as GPIO N OUT 00000020 GPIO N TRI W Same as GPIO N TRI 00000024 GPIO N IN RO SameasGPIONIN as GPIO N IN sca DM STATE Bits a E to direct master states refer to plx32master vhd for more details 0000002C USER_LED Bit 0 Led 1 Bit 1 Led 2 Bit 2 Led 3 Bit 3 Led 4 00000030 DM_CTRL W Bit 0 start operation when complete must be cleared before another operation can begin Bit 1 Write 1 Read 0 00000034 DM_ADDR W Local bus destination address Must match what is programmed into PLX configuration register DMLBAM 00000038 DM_CNT Number of DWORDs to transfer 0000003C REVISION Reference design revision 00000040 R W User Memory 0000007C Revision 0 00 24 Connect Tech FreeForm PCI 104 User Manual Table 11 Local Address Space 1 Bar 3 10000000 SPI Command RW SPI controller command register once command is written operation begins 10000004 SPI Parameters There are four parameters each one byte 0x04 ParamO 0x05 Paraml 0x06 Param2 0x07 Param3 10000008 SPI Status SPI controller status register Bit 0 Operation complete 1000000C SPI Result There are four results each one byte 0x04 ResultO 0x05 Resultl 0x06 Result2 0x07 Result3 10000010 Un addressable N A N A 100000FC 10000100 Dual port memory RW
15. and click Open ld Add PROM File gt init pls GPIO25 CO nao I xmsgs Mo Recent templates Documents aset i ES linit ge GPIO 5 mcs Desktop My Network File name finit plc P PID 25 mcs Places N Files of type MES Files mes Cancel 4 The FPGA SPI Flash Association window will appear select M25P16 this 1s the flash device connected to the FPGA E FPGA SPI Flash Association select SPI Flash FPGA SPI Flash Hoyle SO 14125P16 5 The flash will be added to the FPGA Note that this flash is not part of the JTAG chain TDI dpa3a43i dpa3ada8ivs bad pciansB5ba r1 init bt pcidO05bba bzd xc5vIx30t TD Revision 0 00 21 Connect Tech FreeForm PCI 104 User Manual Programming the Flash 1 Right click the previously associated flash device and select program Ris ht click device to select operations al E i ee Vert TDI i Erase Blank Check Readback la i Toa 4ssign Mew Configuration File 849ivs bed Delete 2 The programming dialog will appear Select Verify and Erase Before Programming then click OK En rogramming Properties Category E Programming Properties Advanced PROM Programming Properties Revision Properties Verity General CPLD And PROM Properties Head Protect PROM EecRunnerl Usercode 8 Hex Digt CPLO Specific Properties Write Protect Functional Test On The Fly Program PLA UES Enter
16. ed by Connect Tech Inc with an RMA Return Material Authorization number marked on the outside of the package and sent prepaid insured and packaged for safe shipment Connect Tech Inc will return this product by prepaid ground shipment service The Connect Tech Inc Lifetime Warranty is defined as the serviceable life of the product This is defined as the period during which all components are available Should the product prove to be irreparable Connect Tech Inc reserves the right to substitute an equivalent product if available or to retract Lifetime Warranty if no replacement is available The above warranty is the only warranty authorized by Connect Tech Inc Under no circumstances will Connect Tech Inc be liable in any way for any damages including any lost profits lost savings or other incidental or consequential damages arising out of the use of or inability to use such product Copyright Notice The information contained in this document is subject to change without notice Connect Tech Inc shall not be liable for errors contained herein or for incidental consequential damages in connection with the furnishing performance or use of this material This document contains proprietary information that is protected by copyright All rights are reserved No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Connect Tech Inc Copyright 2008 by Connect Tech
17. g the FPGA for more information Power pins are for voltage reference only they do not provide power to the configuration circuitry Note that the FPGA can always be programmed via JT AG regardless of the J1 configuration setting Table 4 JTAG Programming Header Pinout P2 Pin Signal Direction TRST 3 Input 4 Output 6 GND JjRefeene SPI Flash Programming Header P3 P3 may be used to directly program the SPI flash providing that J1 is set correctly to the tri state FPGA position The power pins are for voltage reference only They do not provide power to the configuration circuitry Table 5 SPI Flash Programming Header Pinout P3 Pin Signal Direction SPI CSN SPI MOSI SPI MISO 4 SPI CLK Input 5 5 GND Reference L6 33V Reference Revision 0 00 9 Connect Tech FreeForm PCI 104 User Manual RS 485 Headers P5 P6 Table 6 RS 485 Port 1 Pinout P5 Pin Signal Direction RXD 1 EH eee TXDH TXD 1 9 GND power PO TED le Table 7 RS 485 Port 2 Pinout P6 Pin Signal Direction RXD 2 EXA LOA TXD 2 TXD 2 9 GND power A Ln External Power Connector P8 The external connector provides 5V to the power regulation circuitry In addition the power connector enables the 3 3V regulator and provides VIO to the PCI Bridge The external power connector should only be used when the FreeForm PCI 104 is being programmed
18. heck the Connect Tech website s download zone http www connecttech com asp Support DownloadZone asp Revision 0 00 12 Connect Tech FreeForm PCI 104 User Manual FPGA Configuration To configure the FPGA via JTAG connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly It is important to note that P2 also has the TRST signal on pin 1 which is not part of Xilinx s Parallel or USB programming cables Launch Impact 1 Open iMPACT and select create a new project iMPACT Project want to Browse Load most recent project file when IMPACT starts create a new project ipf default ipf Cancel 2 Select configure devices using boundary scan iMPACT will scan the JT AG chain and identify three devices The first device will be the FPGA TDI unknown file unknown file xc5vix3 t file TOO Revision 0 00 Connect Tech FreeForm PCI 104 User Manual 3 A prompt will ask for a new configuration file Select the bitstream from the project directory G Assign New Configuration File init bit File type All Design Files bit zt nky isc bsd we None C3 Enable Programming of SPI Flash Device Attached to this FPGA Enable Programming of BFI Flash Device Attached to this FPGA 4 A prompt will ask for a BSDL file for device number 2 PLX PCI9056 Click Yes E Unknown Device File
19. ification completed successfully iMPACT 572 1 Completed downloading bit file to device IMPACT 1 Checking done pin done Programmed successfully PROGRESS END End Operation Elapsed time BO sec Revision 0 00 16 Connect Tech FreeForm PCI 104 User Manual Generating a PROM MCS File 1 Double click Prom File Formatter in the Flows window F On H A Boundary Scan Sa SlaveS erial T Select AP Se Desktop Configuration Sa Direct SPI Configuration SystemACE I E PROM File Formatter 2 The Prepare PROM Files dialog will appear Ensure that the following settings are selected 3 Party SPI PROM MSC PROM File Format 3 Give the file a name and click Next iMPACT Prepare PROM Files want to target a Co lee PROM Generic Parallel PROM Ce 3rd Party SPI PROM C3 PROM Supporting Multiple Design Versions Spartan 3E MultiBoot PROM File Format MCS O TEK UFP C format CO Exo C3 BIN ISE HEX Swap Bits Checksum Fil Value 2 Hes Diis PROM File Mame init pls GPID25 cs Location EAD ataXProjectesFreeFormPCH O4 AhardwareMogic init pl GPIOZ5 Revision 0 00 17 Connect Tech FreeForm PCI 104 User Manual 4 Select the PROM density 16M gt click Next gt click Finish iMPACT Specify SPI PROM Device E Jm LI Jensity bits KENN 5 A prompt will ask to add device to data stream 0 Click OK Select the bitstream from the project directory
20. mpers Switches Description RSW1 Slot selection Jl FPGA configuration settings Components Description User LEDs D5 FPGA load complete LED U4 PLX PCI local bus bridge US Virtex 5 FPGA U10 FPGA configuration flash UII Embedded code flash U12 U13 DDR2 memory Ul4 Parameter EEPROM U15 U16 RS 485 transceiver U17 Dual 10 100 PHY Ol 100MHz oscillator main clock Revision 0 00 Connect Tech FreeForm PCI 104 User Manual Hardware Description and Configuration The following sections describe the function of all switches jumpers and provide details on connector pinouts Jumpers and Switches Slot Selection RSW1 This rotary switch selects a slot position in the PCI 104 stack When mounting on a PCI adapter card ensure slot one is selected Table 2 Slot Selection RSW1 FPGA Configuration Settings J1 Jumper J1 is used to control FPGA configuration Table 3 FPGA Configuration Settings J1 FPGA waits for configuration over JTAG using the cable it is connected to FPGA reads configuration from SPI flash FPGA is tri state program flash directly Revision 0 00 Connect Tech FreeForm PCI 104 User Manual Connector Pinouts PCI 104 Header P1 Refer to PCI 104 specifications Note P1 must be connected to a PCI 104 stack supplying both 3 3V and 5V JTAG Programming Header P2 Use P2 to configure the FPGA via JTAG Refer to Programmin
21. nvironment coccccccccnnnnnnnnoonnnnnnnnnnnnnnnnnnnonnnnnnnnnnnnnnnnnnnnonnnonnnnnnaninnnnnnss 12 Drivers and Application Examples socorro ici 12 PG A COn uration ios 13 Lanne une e EE 13 Prosramimimneg the FPUA ibi 16 Generating a PROVEMCES A TEE 17 Contigurine the FPGA with the SPI Plain 20 Configuring the FPGA SPI flash Association ccccccccccnnnnnnonnnonncnnnnnnnnnnnnnnnnnnononnnos 20 Prostamtiimne te Pla HE 22 Reference DC SION ouod quiet dee EE tet qup di D D deduc ats tola ind du II deg 24 Eet ter E EE 24 Memory Mapescornmuai 24 Enplementation ido oia 23 JU lei ee 26 Revision 0 00 4 Connect Tech FreeForm PCI 104 User Manual List of Tables Table 1 FreeForm PCI 104 Components i 7 Table 2 SslobSelecton Rn EE 8 Table 3 FPGA Configuration Settings J 1 io petet iitn ates 8 Table 4 JTAG Programming Header Pinout OPB7 9 Table 5 SPI Flash Programming Header Pinout P3 sese 9 Table RS 485 Port J PIOULCAE 9 de iive e EISE deed a E ape estu tatem ade tu oes a ias 10 Table 7 RS495 Port 2 PIBnout PO die hotte beoe osi a Ee vay estu bebo ede t oe a ER UR Neu bs 10 Table 8 External Power Connector Pinout P8 oooccnncccnnnccnnncccnnoccnnnocnnnocnnnarcnnnccnnnoccnncccnnanos 10 Table GPIO HeaderpPInOoUbo a 11 Table I0 BarLocalAddress Space 0 Bart 2 EE 24 Table local Address Space l Bar 3 socio o EOD an 25 List of Figures Figure I FreeF
22. orm PCT 104 Block Dia E E 6 Erue 2 FreebPornvyPCT D04 E OU cass oq veda ro ceo iia d Preure 3 External Power CoODDnec Obi eege 10 Revision 0 00 Connect Tech FreeForm PCI 104 User Manual Introduction Connect Tech s FreeForm PCI 104 features Xilinx s Virtex 5 multi platform FPGA offering users a flexible reconfigurable product that also takes advantage of the high bandwidth capabilities of the PCI bus while communicating with various I O interfaces Features PCI 104 form factor 32 Bit 33MHz Xilinx multi platform Virtex 5 FPGA with 3 million logic gates 8MB Flash for embedded code storage Designed for embedded processing using MicroBlaze 100MHz input clock 128MB DDR2 400 memory External 5V power connection for stand alone usage 2 x 10 100 Ethernet with modular jacks 2 x RS 485 serial interface On board reset switch 64 single ended or 32 LVDS general purpose I O Available in industrial temperature range of 40 C to 85 O O O O O O Oo OO OO O PCI 104 Bus 64 1 0 32 LVDS Pairs tP C t 1x Header Core Circuitry 2 Figure 1 FreeForm PCI 104 Block Diagram Revision 0 00 Connect Tech FreeForm PCI 104 User Manual UNIVERSAL STANDALONE FreeForm PCI 104 Table 1 FreeForm PCI 104 Components Connectors Description P1 PCI 104 connector P2 JTAG programming header P3 SPI flash programming header RS 485 header P GPIO header P8 External power header P9 RJ 45 A P10 RJ 45 B Ju
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