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Atmel AT91CAP7A-STK Computer Hardware User Manual

1. Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A J1 A17 L1 A20 N1 D4 R1 D10 J2 A18 L2 A23 N2 D6 R2 D11 J3 VDDIO L3 DO N3 VDDIO R3 D12 J4 A16 14 D1 N4 D14 R4 D13 J5 L5 5 PB19 TCLKO R5 PB20 TIOAO 46 L6 N6 VDDIO R6 PB23 TIOA1 J7 L7 N7 PB25 TCLK2 R7 PB24 TIOB1 J8 18 8 PA1 TIOA3 R8 PA3 TCLK4 J9 L9 N9 VDDIO R9 PA4 TIOA4 J10 _ L10 _ N10 PA8 TIOB5 R10 J11 L11 N11 PA9 IRQO R11 PA6 TCLK5 J12 PA29 NPCS3 L12 PA25 MOSI N12 VDDCORE R12 PA12 IRQ3 J13 SHDN L13 PA22RXD2 N13 VDDIO R13 PA14 SCKO J14 VDDPLL L14 PA26 NPCSO NSS N14 PA19 RXD1 R14 PA15 TXDO J15 PLLRC L15 XOUT N15 GND R15 PA16 RXDO K1 A19 M1 D2 1 D5 K2 A22 M2 D3 P2 D7 K3 21 M3 VDDCORE P3 D8 K4 GND M4 GND P4 D9 K5 5 GND P5 D15 K6 6 PB21 TIOBO P6 PB22 TCLK1 K7 7 GND P7 PB26 TIOA2 K8 M8 PB27 TIOB2 P8 2 K9 9 9 PA7 TIOA5 K10 10 GND P10 PA10 IRQ1 K11 M11 PA23 SPCK P11 PA11 IRQ2 K12 PA28 NPCS2 M12 GND P12 PA13 FIQ K13 VDDIO M13 PA21 TXD2 P13 PA17SCK1 K14 PA27 NPCS1 M14 PA24 MISO P14 PA18 TXD1 NTRI K15 GNDPLL M15 XIN P15 PA20 SCK2 AMEL s 1745D ATARM 04 Nov 05 AMEL Figure 2 1 176 lead LQFP Pinout 132 89 133 88
2. Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A A1 NCS1 C1 AO NLB E1 A4 G1 A12 A2 NWAIT C2 NCSO E2 A3 G2 A9 NRST C3 VDDIO ES A5 G3 A8 A4 NTRST VDDCORE E4 GND G4 GND A5 PB18 BMS C5 TMS E5 G5 6 NWDOVF C6 VDDIO E6 B G6 16 MCKO E7 G7 A8 PB12 C8 PB13 E8 G8 B A9 PB10 C9 PB6 ADOTRIG 9 B G9 10 9 10 VDDIO E10 G10 A11 PB8 C11 PB4 IRQ5 E11 G11 12 57 C12 PBO E12 AD6 G12 AD3 A13 NCS6 C13 VDDIO E13 AD5 G13 AD2 14 GND C14 DAO E14 NRSTBU G14 GND A15 DAVREF C15 ADVREF E15 GNDBU G15 XIN32 B1 NCS2 D1 A2 F1 A10 H1 A15 B2 NUB NWR1 D2 A1 F2 H2 A14 B3 NWE NWRO D3 NCS3 F3 VDDIO H3 A13 B4 NOE NRD D4 GND 6 H4 A11 B5 TDO D5 TCK F5 5 B6 TDI D6 JTAGSEL F6 6 B7 PB17 D7 GND F7 H7 B8 PB11 D8 PB15 F8 H8 B9 PB7 AD1TRIG D9 PB14 F9 _ H9 _ B10 PB3 IRQ4 D10 PB5 F10 10 B11 PB2 D11 PB1 F11 11 B12 NCS5 D12 GND F12 GND H12 AD1 B13 54 D13 VDDCORE F13 AD4 H13 ADO B14 DA1 D14 AD7 F14 VDDBU 14 WAKEUP B15 GNDA D15 VDDA F15 XOUT32 15 GND 4 AT91M55800A mememe 1745D ATARM 04 Nov 05 mms n 91 55800 Table 2 2 Pin Configuration for 176 ball BGA Package Continued
3. Bit Associated BSR Number Pin Name Pin Type Cells 164 INPUT PA21TXD2 IN OUT 163 CTRL 162 OUTPUT 161 205 2 IN OUT INPUT 160 CTRL 159 OUTPUT 158 PA19RXD1 IN OUT INPUT 157 CTRL 156 OUTPUT 155 PA18 TXD1 NTRI IN OUT INPUT 154 CTRL 153 OUTPUT 152 PA17 SCK1 IN OUT INPUT 151 CTRL 150 OUTPUT 149 PA16 RXDO IN OUT INPUT 148 CTRL 147 OUTPUT 146 PA15 TXDO IN OUT INPUT 145 CTRL 144 OUTPUT 143 PA14 SCKO IN OUT INPUT 142 CTRL 141 OUTPUT 140 PA13 FIQ IN OUT INPUT 139 CTRL 138 OUTPUT 137 PA12 IRQ3 IN OUT INPUT 136 CTRL 135 OUTPUT 134 PA11 IRQ2 IN OUT INPUT 133 CTRL 132 OUTPUT 131 PA10 IRQ1 IN OUT INPUT 130 CTRL 222 AT91M55800A memme 1 55800 Table 23 1 JTAG Boundary scan Register Continued Bit Associated BSR Number Pin Name Pin Type Cells 129 OUTPUT 128 PA9 IRQO IN OUT INPUT 127 CTRL 126 OUTPUT 125 PA8 TIOB5 IN OUT INPUT 124 CTRL 123 OUTPUT 122 PA7 TIOA5 IN OUT INPUT 121 CTRL 120 OUTPUT 119 PA6 CLK5 IN OUT INPUT 118 CTRL 117 OUTPUT 116 5 4 IN OUT INPUT 115 CTRL 114 OUTPUT 113 PA4 TIOA4 IN OUT INPUT 112 CTRL 111 OUTPUT 110 PA3 TCLK4 IN OUT INPUT 109
4. peeH Ayes SIUM 1 od cSON LSON OV MON 39 AMEL 1745D ATARM 04 Nov 05 AMEL Figure 11 19 through Figure 11 25 show the timing cycles and wait states for read and write access to the various AT91M55800A external memory devices The configurations described are as follows Table 11 1 Memory Access Waveforms Figure Number Number of Wait States Bus Width Size of Data Transfer 11 19 0 16 Word 11 20 1 16 Word 11 21 1 16 Half word 11 22 0 8 Word 11 23 1 8 Half word 11 24 1 8 Byte 11 25 0 16 Byte 1745D ATARM 04 Nov 05 ma vn A191 55800A Figure 11 19 0 Wait States 16 bit Bus Width Word Transfer NCS N NLB N i NUB N 4 Standard Protocol Internal Bus B2 Bi I Ba Bs Bi Early Protocol NRD WRITE ACCESS Byte Write Byte Select Option NWE uum CEP a AIMEL 1745D ATARM 04 Nov 05 NE AIMEL Figure 11 20 1 Wait State 16 bit Bus Width Word Transfer T TN 27714 Il d
5. 91 55800 11 8 Wait States The EBI can automatically insert wait states The different types of wait states are listed below e Standard wait states Data float wait states External wait states Chip select change wait states Early read wait states as described in Read Protocols 11 8 1 Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding device This is done by setting the WSE field in the corresponding CSR The number of cycles to insert is programmed in the NWS field in the same register Below is the correspondence between the number of standard wait states programmed and the number of cycles during which the NWE pulse is held low 0 wait states 1 2 cycle 1 wait state 1 cycle For each additional wait state programmed an additional cycle is added Figure 11 11 One Wait State Access 1 Wait State Access I MCK NRD 2 Notes 1 Early Read Protocol 2 Standard Read Protocol 11 8 2 Data Float Wait State Some memory devices are slow to release the external bus For such devices it is necessary to add wait states data float waits after a read access before starting a write access or a read access to a different external memory The Data Float Output Time for each external memory device is programmed in the TDF field of the register for the cor
6. sa asss j sese ads desee 5 T 3 CY s 1 8 n 3 sur 1 e Oe s NE T d 1 Wait State xj I 18 L L mm 2 a 2 c m c z lt z z z n lt a T E ll u o lt o I IN 9 241118 z l z o ull 18 Q 8 19 SEE g lt al 8 wl lt 112 l 5 S 5 gt 11 lu 1745D ATARM 04 Nov 05 91 55800 muu 42 mmn A 1 55800 Figure 11 21 1 Wait State 16 bit Bus Width Half word Transfer f 1 Wait State MCK 1 NCS NLB
7. Table 16 2 Controller B Connection Table PIO Controller Peripheral Bit Port Signal OFF Pin Number Name Port Name Signal Description Direction Value Reset State Number 0 PBO PIO Input 139 1 PB1 PIO Input 140 2 PB2 PIO Input 141 3 PB3 IRQ4 External Interrupt 4 Input 0 PIO Input 142 4 PB4 IRQ5 External Interrupt 5 Input 0 PIO Input 143 5 PB5 0 PIO Input 144 6 PB6 ADOTRIG ADCO External Trigger Input 0 PIO Input 145 7 PB7 AD1TRIG ADC1 External Trigger Input 0 PIO Input 146 8 PB8 PIO Input 149 9 PB9 PIO Input 150 10 PB10 PIO Input 151 11 PB11 152 12 12 PIO Input 153 13 PB13 PIO Input 154 14 PB14 155 15 15 PIO Input 156 16 PB16 1 1 157 17 17 PIO Input 158 18 PB18 BMS Boot Mode Select Input 0 PIO Input 163 19 PB19 TCLKO Timer 0 Clock signal Input 0 PIO Input 55 20 PB20 TIOAO Timer 0 Signal A Bi directional 0 PIO Input 56 21 PB21 TIOBO Timer 0 Signal B Bi directional 0 PIO Input 57 22 PB22 TCLK1 Timer 1 Clock signal Input 0 PIO Input 58 23 PB23 TIOA1 Timer 1 Signal A Bi directional 0 PIO Input 61 24 PB24 TIOB1 Timer 1 Signal B Bi directional 0 PIO Input 62 25 PB25 TCLK2 Timer 2 Clock signal Input 0 PIO Input 63 26 PB26 TIOA2 Timer 2 Signal A Bi directional 0 PIO Input 64 27 PB27 TIOB2 Timer 2 Signal B Bi directional 0 PIO Input 65 28
8. 238 Ordering Informati ri S 239 jj m 240 Rrevision History X 245 Table of Contents uu 2 iets i AT91M55800A mun 1745D ATARM 04 Nov 05 AIMEL EE 5 Atmel Corporation Atmel Operations 2325 Orchard Parkway Memory RF Automotive San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 La Chantrerie BP 70602 44306 Nantes Cedex 3 France Tel 33 2 40 18 18 18 Fax 33 2 40 18 19 60 ASIC ASSP Smart Cards Zone Industrielle 13106 Rousset Cedex France Tel 33 4 42 53 60 00 Fax 33 4 42 53 60 01 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany Tel 49 71 31 67 0 Fax 49 71 31 67 2340 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540
9. TCOXCOS External Clock Signal 0 Selection TCOXCOS Signal Connected to XCO Code Label 0 TCLKO TC TCLKOXCO 0 None TC NONEXCO 1 TIOA1 TC TIOA1XCO 1 TIOA2 TC TIOA2XCO TC1XC1S External Clock Signal 1 Selection TC1XC1S Signal Connected to XC1 Code Label TC TC1XC1S 0 TCLK1 TC TCLK1XC1 0 None TC 1 TIOAO TC_TIOAOXC1 1 TIOA2 TC_TIOA2XC1 TC2XC2S External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 Code Label TC2XC2S 0 TCLK2 TC TCLK2XC2 0 None TC NONEXC2 1 TIOAO TC TIOAOXC2 1 TIOA1 TC TIOA1XC2 91 55800 m 1745D ATARM 04 Nov 05 91 55800 19 5 3 TC Channel Control Register Register Name TC CCR Access Type Write only Offset 0 00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKEN Counter Clock Enable Command Code Label CLKEN 0 No effect 1 Enables the clock if CLKDIS is not 1 CLKDIS Counter Clock Disable Command Code Label TC CLKDIS 0 No effect 1 Disables the clock SWTRG Software Trigger Command Code Label TC SWTRG 0 No effect 1 A software trigger is performed the counter is reset and clock is started A MEL 171 1745D
10. OVRE2 OVRE1 OVREO 2 EOC1 EOCO EOC End of Conversion Interrupt Enable Code Label 0 No effect 1 Enables the End of Conversion Interrupt OVRE Overrun Error Interrupt Enable Code Label ADC OVREx 0 No effect 1 Enables the Overrun Error Interrupt 21 0 13 ADC Interrupt Disable Register Register Name ADC_IDR Access Type Write only Offset 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 r j OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 Eocs EOC End of Conversion Interrupt Disable Code Label 0 No effect 1 Disables the End of Conversion Interrupt OVRE Overrun Error Interrupt Disable Code Label ADC_OVREx 0 No effect 1 Disables the Overrun Error Interrupt 216 AT91M55800A cm mmn rsrsnnK n A191 55800A 21 0 14 ADC Interrupt Mask Register Register Name ADC_IMR Access Type Read only Reset State 0 Offset 0x2C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 _ OVRES OVRE2 7 6 5 4 3 2 1 0 Cea c T s EOCO EOC End of Conversion Interrupt Mask Code Label EOCx 0 End of Conversion Interrupt is disabled 1 End of Conversion Interrupt is enabled OVRE Overrun Error Interrupt Mask Code Label OVREXx 0 Ove
11. X 91 55800 2 Pin Configurations Table 2 1 Pin Configuration for 176 lead LQFP Package Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A 1 GND 45 GND 89 GND 133 GND 2 GND 46 GND 90 GND 134 GND 3 NCSO 47 D8 91 PA19 RXD1 135 NCS4 4 NCS1 48 D9 92 PA20 SCK2 136 NCS5 5 NCS2 49 D10 93 PA21 TXD2 137 NCS6 6 NCS3 50 D11 94 PA22 RXD2 138 NCS7 7 NLB AO 51 D12 95 PA23 SPCK 139 PBO 8 A1 52 D13 96 PA24 MISO 140 PB1 9 A2 53 D14 97 PA25 MOSI 141 PB2 10 A3 54 D15 98 PA26 NPCSO NSS 142 PB3 IRQ4 11 4 55 PB19 TCLKO 99 PA27 NPCS1 143 PB4 IRQ5 12 A5 56 PB20 TIOAO 100 PA28 NPCS2 144 PB5 13 A6 57 PB21 TIOBO 101 PA29 NPCS3 145 PB6 ADOTRIG 14 A7 58 PB22 TCLK1 102 VDDIO 146 PB7 AD1TRIG 15 VDDIO 59 VDDIO 103 GND 147 VDDIO 16 GND 60 GND 104 VDDPLL 148 GND 17 A8 61 PB23 TIOA1 105 XIN 149 PB8 18 A9 62 24 1 106 XOUT 150 PB9 19 A10 63 PB25 TCLK2 107 GNDPLL 151 PB10 20 A
12. Notes 1 Early Read Protocol 2 Standard Read Protocol 11 8 4 Chip Select Change Wait States A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories if no wait states have already been inserted If any wait states have already been inserted e g data float wait then none are added Figure 11 14 Chip Select Wait Mem 1 Chip Select Wait 2 gt MCK NRD 2 Notes 1 Early Read Protocol 2 Standard Read Protocol AMEL s 1745D ATARM 04 Nov 05 AMEL 11 9 Memory Access Waveforms Figure 11 15 through Figure 11 18 show examples of the two alternative protocols for external memory read access Figure 11 15 Standard Read Protocol with no 1 _ N E gt 1 ie N gt E z 1 s gt N gt _ 3s 2 25 55 1 gt u 1 c mco gt E z 1 gt u EID CE lt s a Lu T e lt 82 2 P P 2 o 5 o 1 e 1745D ATARM 04 Nov 05 mnr A 1 55800 Figure 11 16 Early Read Protocol with no Pla diuo
13. 18 8 4 System nii tree teret e ga IRR 19 8 5 User Peripherals 424244 nennen 20 9 22 10 Peripheral Memory 23 11 EBI External BUS Interface 24 11 1 External Memory Mapping 25 11 2 EBI Pin Description 26 11 9 Data Bus ted pta 27 11 4 Byte write Byte select ACCESS 27 11 5 jBooton NGSO e 29 AMEL AMEL 11 6 Read Protocols eonenna pete debe ERS 30 11 7 Write Data Hold Time 32 11 8 Wait States Ge 33 11 9 Memory Access Waveforms 36 11 10 EBI User Interface reete ee RES ERR E 48 12 APMC Advanced Power Management Controller 52 12 1 Operating Modes 53 12 2 Slow Clock Generator eroe 55 12 3 Clock Generator trei e 56 12 4 System 59 12 5 Peripheral Clocks 59 12 6 Shut down and Wake up
14. bits the peripheral registers shown as compatibility These bits read O and must be written at 0 for upward 8 2 Peripheral Interrupt Control The Interrupt Control of each peripheral is controlled from the status register using the inter rupt mask The status register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt Enable Register and the Interrupt Disable Register The enable disable status or mask makes it possible to enable or disable peripheral interrupt sources with a non interruptible sin gle instruction This eliminates the need for interrupt masking at the AIC or Core level in real time and multi tasking systems 8 3 Peripheral Data Controller An on chip 8 channel Peripheral Data Controller PDC transfers data between the on chip USARTS SPI and the on and off chip memories without processor intervention One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and SPI The user interface of a PDC channel is integrated in the memory space of each peripheral It contains a 32 bit address pointer register and a 16 bit count register When the programmed data is transferred an end of transfer interrupt is generated by the corresponding peripheral 18
15. 5 3 A o zh 18 10 15 USART Transmit Counter Register Name US TCR Access Type Read Write Reset State 0 Offset Ox3C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E En Aa Aa En Em E o TXCTR TXCTR gt lt N d o 2 o 5 TXCTR must be loaded with the size the transmit buffer 0 Stop Peripheral Data Transfer dedicated to the transmitter 1 65535 Start Peripheral Data transfer if TXRDY is active 156 AT91M55800A mmm 1745D ATARM 04 Nov 05 mr n 1 55800 19 Timer Counter 1745D ATARM 04 Nov 05 The AT91M55800A features two Timer Counter Blocks each containing three identical 16 bit timer counter channels Each channel can be independently programmed to perform a wide range of functions including frequency measurement event counting interval measurement pulse generation delay timing and pulse width modulation Each Timer Counter channel has three external clock inputs five internal clock inputs and two multi purpose input output signals which can be configured by the user Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts via the AIC Advanced Interrupt Controller Each Timer Counter block has two global registers which act upon all three TC channels The Blo
16. Offset Register Name Access Reset State 0x00 Control Register US CR Write only 0 04 Mode Register US MR Read write 0 0x08 Interrupt Enable Register US_IER Write only 0x0C Interrupt Disable Register US_IDR Write only 0x10 Interrupt Mask Register US_IMR Read only 0 0x14 Channel Status Register US_CSR Read only 0x18 0x18 Receiver Holding Register US_RHR Read only 0 Ox1C Transmitter Holding Register US THR Write only 0 20 Baud Rate Generator Register US BRGR Read write 0 0x24 Receiver Time out Register US RTOR Read write 0 0x28 Transmitter Time guard Register US TTGR Read write 0 0 2 Reserved 0 30 Receive Pointer Register US RPR Read write 0 0x34 Receive Counter Register US_RCR Read write 0 0x38 Transmit Pointer Register US_TPR Read write 0 Ox3C Transmit Counter Register US TCR Read Write 0 mr mnr rr 91 55800 18 10 1 USART Control Register Name US_CR Access Type Write only Offset 0x00 11 SENDA STTTO STPURK STU R STSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSIX RSTRX Reset Receiver Code Label US RSTRX 0 No effect 1 The receiver logic is reset RSTTX Reset Transmitter Code Label Us RSTTX 0 No effect 1 The transmitter logic is reset RXEN Receiver Enable Code Label US RXEN 0 No effect 1 The receiver is enabled if RXDIS is 0 RXDIS Receiver Disable Code Label 08 RXDIS 0 No effect 1 The receiver is disabled TXEN Transmi
17. 29 30 _ _ _ 31 Note 1 The OFF value is the default level seen on the peripheral input when the PIO line is enabled 16 91 55800 A mw 1 55800 16 9 User Interface PIO Controller Base Address 0xFFFECOO0 Code Label PIOA BASE PIO Controller B Base Address 0xFFFF0000 Code Label PIOB BASE Table 16 3 Controller Memory Map Offset Register Name Access Reset State 0x00 PIO Enable Register PIO PER Write only 0 04 Disable Register PIO PDR Write only Status Register PIO_PSR Head oniy iu tB 0x0C Reserved 0x10 Output Enable Register PIO_OER Write only 0 14 Output Disable Register Write only 0x18 Output Status Register PIO OSR Read only 0 0x1C Reserved 0 20 Input Filter Enable Register PIO IFER Write only 0 24 Input Filter Disable Register PIO IFDR Write only 0 28 Input Filter Status Register PIO IFSR Read only 0 0 2 Reserved 0 30 Set Output Data Register PIO SODR Write only 0 34 Clear Output Data Register CODR Write only 0 38 Output Data Status Register PIO ODSR Read only 0 Ox3C Pin Data Status Register see Note 0 40 Interrupt Enable Register PIO IER Write only 0 44 Interrupt Disable Register PIO IDR Write only B
18. P pre This register is used to disable the open drain configuration of the output buffer 1 Disables the multi driver option on the corresponding pin 0 No effect 16 9 20 Multi driver Status Register Register Name PIO MDSR Access Type Read only Reset Value 0 0 Offset 0x58 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P p e m Po j P P 7 6 5 4 3 2 1 0 pg m P P P Jj P This register indicates which pins are configured with open drain drivers 1 PIO is configured as an open drain 0 PIO is not configured as an open drain J ATMEL 1745D ATARM 04 Nov 05 AMEL 17 SF Special Function Registers The AT91M55800A provides registers which implement the following special functions e Chip identification e RESET status 17 1 Chip Identifier The following chip identifier values are covered in this datasheet Product fii Chip ID AT91M55800A A 0x15580040 17 2 SF User Interface Chip ID Base Address OxFFF00000 Code Label SF BASE Table 17 1 SF Memory Map Offset Register Name Access Reset State 0x00 Chip ID Register SF CIDR Read only Hardwired 0x04 Chip ID Extension Register SF EXID Read only Hardwired 0x08 Reset Status Register SF RSR Read only 0x0C Reserved _ _ _ 0x10 Reserved _ 0x14 Reserved 0x18 Protect Mode Register
19. This provides a programmable time out period of 4 ms to 8 sec with a 33 MHz system clock All write accesses are protected by control access keys to help prevent corruption of the watchdog should an error condition occur To update the contents of the mode and control registers it is necessary to write the correct bit pattern to the control access key bits at the same time as the control bits are written the same write access Figure 14 1 Watchdog Timer Block Diagram Advanced Peripheral Bus APB WD RESET Control Logic NWDOVF WDIRQ Overflow MCK 32 MCK 128 16 Bit Clock Select Programmable MCK 1024 CLK_CNT Down Counter MCK 4096 AMEL 1745D ATARM 04 Nov 05 AMEL 14 0 1 WD User Interface WD Base Address OxFFFF8000 Code Label WD BASE Table 14 1 WD Memory Offset Register Name Access Reset State 0x00 Overflow Mode Register WD OMR Read Write 0 0x04 Clock Mode Register WD CMR Read Write 0 0x08 Control Register WD CR Write only OxOC Status Register WD SR Read only 0 90 AT91M55800A mw 1745D ATARM 04 Nov 05 mr A T 9 1 155800 14 0 2 WD Overflow Mode Register Name WD_OMR Access Read Write Reset Value 0 Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OKEY EXTEN IRQEN RSTEN WDEN WDEN Watchdog Enable Code Label WD 0 Watchdog is disabled and does no
20. Advanced Peripheral Bus TIOAQ TIOA5 22 1 Conversion Details Control Logic VDDA Data Holding Register Data Output 10 bit DAC 9 Register DAVREF Trigger Selection Digital to analog conversions are possible only if the DAC has been enabled in the APMC and the startup time precisely in the has elapsed This startup time is a maximum of 5 usec and is indicated more Electrical Characteristics datasheet of the device as parameter tpasu Digital inputs are converted to output voltages on a linear conversion between 0 and DAVREF The analog output voltages on DAO and DA1 pins are determined by the following equation 215 AT91M55800A memme 1745D ATARM 04 Nov 05 mnr A 1 55800 DA DAVREF x DAC_DOR 1024 When DAC_DOR Data Output Register is loaded the analog output voltage is available after a settling time of approximately 5 usec The exact value depends on the power supply voltage and the analog output load and is indicated in the Electrical Characteristics Sheet of the device as parameter tpast The output register cannot be written directly and any data transfer to the DAC must be per formed by writing in DAC_DHR Data Holding Register The transfer from DAC_DHR to DAC_DOR is performed automatically or when an hardware trigger occurs depending on the bit TRGEN in DAC_MR Mode Register The DAC integrates an output buff
21. J AMEL 1745D ATARM 04 Nov 05 AMEL 15 10 12 AIC Interrupt Set Command Register Register Name AIC_ISCR Access Type Write only Offset 0x12C 31 30 29 28 27 26 25 24 COMMRX COMMTX IRQS IRQS 23 22 21 20 19 18 17 16 APMCIRQ RTCIRQ DAC1IRQ DACOIRQ ADC1IRQ 15 14 13 12 11 10 9 8 ADCOIRQ PIOBIRQ PIOAIRQ WDIRQ TC5IRQ TC4IRQ TC3IRQ TC2IRQ 7 6 5 4 3 2 1 0 TC1IRQ TCOIRQ SPIRQ US2IRQ US1IRQ USOIRQ SWIRQ e Interrupt Set 0 No effect 1 Sets corresponding interrupt 15 10 13 AIC End of Interrupt Command Register Register Name AIC EOICR Access Type Write only Offset 0x130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment 18 AT91M55800A m us 1745D ATARM 04 Nov 05 91 55800 15 10 14 AIC Spurious Vector Register Register Name AIC SPU Access Type Read Write Reset Value 0 Offset 0 134 SPUVEC SPUVEC SPUVEC SPUVEC ja EN o AR m e 5 A A N 2 3 A o E N o o SPUVEC Spurious Interru
22. gt A N En Aa E N 15 14 13 12 11 10 9 8 ow e 1 4 en 1 ce N A o RXCHR RXCHR Received Character Last character received if RXRDY is set When number of data bits is less than 9 bits the bits are right aligned All unused bits read zero 18 10 8 USART Transmitter Holding Register Name US THR Access Type Write only Offset Ox1C 31 30 29 28 27 26 25 24 A N Aa A E E E En A Em 8 TXCHR o TXCHR Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set When number of data bits is less than 9 bits the bits are right aligned X m 1 55800 18 10 9 USART Baud Rate Generator Register Name US BRGR Access Type Read Write Reset State 0 Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD CD N En o CD Clock Divisor This register has no effect if Synchronous Mode is selected with an external clock CD 0 Disables Clock 1 Clock Divisor bypass 210 65535 Baud Rate Asynchronous Mode Selected clock 16 x CD Baud Rate Synchronous Mode Selected clock CD Notes 1 In Synchronous Mode the value p
23. 159 19 2 Timer Counter Description 160 19 3 Capture Operating Mode 163 19 4 Waveform Operating Mode 165 19 5 User Interface 168 20 SPI Serial Peripheral Interface 185 20 1 Pin Description 185 20 2 Master Mode uu 186 20 3 Slave crit edid Fb 190 20 4 Data Transfer 4 0 nenne 191 20 5 Clock Generation itte tei a tret t ea 192 A MEL iii 1745D ATARM 04 Nov 05 21 22 23 24 25 26 27 AMEL 20 6 Peripheral Data Controller sse 192 20 7 SPI Programmers Model 193 ADC Analog to digital Converter 207 DAC Digital to analog Converter 218 22 1 Conversion Details u u a aad Ea ERR a 218 22 2 User Interface 2 nennen enne 220 JTAG Boundary scan Register 227 Packaging Information 235 Soldering Profile 238 25 1 Green Package Soldering Profile 2 238 25 2 ROHS Package Soldering Profile
24. 1745D ATARM 04 Nov 05 mm rrnrrs nn A T 9 1 VI55800 A 13 3 7 RTC Status Register Register Name RTC_SR Access Type Read only Reset State 0x0 Offset 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s polos lp e ee TIMEV ALARM ACKUPD e ACKUPD Acknowledge for Update Code Label RTC ACKUPD 0 Time and Calendar registers cannot be updated 1 Time and Calendar registers can be updated ALARM Alarm Flag Code Label RTC ALARM 0 No alarm matching condition occurred 1 An alarm matching condition has occurred SEC Second Event Code Label RTC SEC 0 No second event has occurred since the last clear 1 At least one second event has occurred since the last clear TIMEV Time Event Code Label RTC TIMEV 0 No time event has occurred since the last clear 1 At least one time event has occurred since the last clear The time event is selected in the TEVSEV field CR and can be any one of the following events minute change hour change noon midnight day change CALEV Calendar Event Code Label RTC CALEV 0 No calendar event has occurred since the last clear 1 At least one calendar event has occurred since the last clear The calendar event is selected in the CEVSEL field in CR and can be any one of the following events week change month change year change AMEL 1745D ATARM 04 Nov 05 AMEL 13 3 8 R
25. Lee AIC SRCTYPE INT LEVEL SENSITVE Low level AIC SRCTYPE EXT LOW LEVEL Sensitive Sensitive Edge Negative 0 1 09 AIC SRCTYPE INT EDGE TRIGGERED Edge AIC EXT NEGATIVE EDGE triggered triggered 1 o Level AIC SRCTYPE INT LEVEL High level AIC_SRCTYPE_EXT_HIGH_LEVEL Sensitive Sensitive 1 Edge AIC SRCTYPE INT EDGE TRIGGERED PoSitive Edge SRCTYPE EXT POSITIVE EDGE triggered triggered 1745D ATARM 04 Nov 05 Register Name AIC_SVRO AIC_SVR31 Access Type Read Write Reset Value 0 31 30 29 28 27 26 25 24 VECTOR 23 N o E E N E VECTOR _ A A 6 A ck VECTOR N A 99 VECTOR VECTOR Interrupt Handler Address The user may store in these registers the addresses of the corresponding handler for each interrupt source 15 10 3 AIC Interrupt Vector Register Register Name IVR Access Type Read only Reset Value 0 Offset 0x100 31 30 29 28 27 26 25 24 IRQV N o N E IRQV A A a A A ER zx IRQV IRQV gt o 5 75 lt e o o The IRQ Vector Register contains the vector programmed by the user the Source Vector Register corresponding to the curren
26. 12 9 3 APMC System Clock Status Register Register Name APMC SCSR Access Type Read only Reset Value 0 1 Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S e 9 _ e _ CPU System Clock Status Bit 0 System Clock is disabled 1 System Clock is enabled 12 9 4 APMC Peripheral Clock Enable Register Register Name APMC PCER Access Type Write only Offset 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ ce CL pe DACO ADC 15 14 13 12 11 10 9 8 ADCO PIOB Ts 14 13 7 6 5 4 3 2 1 0 TC s Us u u Peripheral Clock Enable per peripheral 0 No effect 1 Enables the peripheral clock 64 91 55800 J A191 55800A 12 9 5 APMC Peripheral Clock Disable Register Register Name APMC PCDR Access Type Write only Offset 0x14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Lo qo qp jJ DACO 15 14 13 12 11 10 9 8 ADCO PIOB poa 15 7 6 5 4 3 2 1 0 s ue u Peripheral Clock Disable per peripheral 0 No effect 1 Disables the peripheral clock 12 9 6 APMC Peripheral Clock Status Register Register Name APMC PCSR Access Type Read only Reset Value 0 0 Offset 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18
27. US CHMODE AUTOMATIC ECHO Receiver Data Input is connected to TXD pin 1 0 Local Loopback Transmitter Output Signal is connected to Receiver Input Signal NOCAT eer CS 1 1 Remote Loopback RXD pin is internally connected to TXD pin Ue CHMODE LOOPBACK MODES 9 Bit Character Length Code Label US MODE9 0 CHRL defines character length 1 9 Bit character length e CKLO Clock Output Select Code Label US CLKO 0 The USART does not drive the SCK pin 1 The USART drives the SCK pin if USCLKS 1 is 0 Iu 91 55800 18 10 3 USART Interrupt Enable Register Name US IER Access Type Write only Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY Enable RXRDY Interrupt Code Label US RXRDY 0 No effect 1 Enables RXRDY Interrupt TXRDY Enable TXRDY Interrupt Code Label 08 TXRDY 0 No effect 1 Enables TXRDY Interrupt RXBRK Enable Receiver Break Interrupt Code Label US_RXBRK 0 No effect 1 Enables Receiver Break Interrupt ENDRX Enable End of Receive Transfer Interrupt Code Label 05 ENDRX 0 No effect 1 Enables End of Receive Transfer Interrupt ENDTX Enable End of Transmit Transfer Interrupt Code Label US_ENDTX 0 No effect 1 Enables End of Transmit Transfer Interrup
28. gt 4 gt 4 Pla gt lt ple P lt ple 1 MMM sra L6LV s a 1 sra cSON LSON 3MN GUN OV MON 37 AMEL 1745D ATARM 04 Nov 05 AIMEL NEED Figure 11 17 Standard Read Protocol with t k IOl 1 I eA 1 l eye eye eye 4 gt lt pla gt lt d lt gt q l H I guew zuew peeH We sta oq 1617 sra oq cSON LSON QuN OV AT91M55800A memme 38 1745D ATARM 04 Nov 05 mnr A 1 55800 Figure 11 18 Early Read Protocol with oa gt gt gt 1617 oa o q lt lt ly L q amp Y amp amp Wold 12014 12014 eq eq ea gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt 2
29. 15 14 13 12 11 10 9 8 P15 P14 P13 P12 11 10 7 6 5 4 3 2 1 0 P5 P pre This register is used to enable input glitch filters It affects the pin whether or not the PIO is enabled The register is pro grammed as follows 1 Enables the glitch filter on the corresponding pin 0 No effect 16 9 8 PIO Input Filter Disable Register Register Name IO IFDR Access Type Write only Offset 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Pi Pa P P Po P 7 6 5 4 3 2 1 0 Ps P P P Pm This register is used to disable input glitch filters It affects the pin whether or not the PIO is enabled The register is pro grammed as follows 1 Disables the glitch filter on the corresponding pin 0 No effect A MEL 121 1745D ATARM 04 Nov 05 AMEL 16 9 9 PIO Input Filter Status Register Register Name PIO_IFSR Access Type Read only Offset 0x28 Reset Value 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22 P21 15 14 13 12 11 10 9 8 Pis P Pts Po P Po o P 7 6 5 4 3 2 1 0 Pa P P P J P This register indicates which pins have glitch filters selected It is updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR 1 Filter is selected on the corresponding input peripheral and PIO 0 Filter is not selected on the corresponding input Note When the glitch
30. Bit between two characters value period 18 5 Multi drop Mode 1745D ATARM 04 Nov 05 When the field PAR in US MR equals 11X binary value the USART is configured to run in multi drop mode In this case the parity error bit PARE in 06 is set when data is detected with a parity bit set to identify an address byte PARE is cleared with the Reset Sta tus Bits Command RSTSTA in US CR If the parity bit is detected low identifying a data byte PARE is not set The transmitter sends an address byte parity bit set when a Send Address Command SENDA is written to US CR In this case the next byte written to US will be transmit ted as an address After this any byte transmitted will have the parity bit cleared Figure 18 6 Synchronous and Asynchronous Modes Character Transmission Example 8 bit parity enabled 1 stop Baud Rate H H xb i Stat D 03 D D6 07 Parity Stop Bit Bit A MEL 137 AMEL 18 6 Break A break condition is a low signal level which has a duration of at least one character including start stop bits and parity 18 6 1 Transmit Break The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR Control Register In this case the character present in the Transmit Shift Register is com pleted before the line is held low To cancel a b
31. PCS xxxONPCSJ 3 0 1110 PCS xx01NPCS 3 0 1101 PCS x011NPCS 3 0 1011 PCS 0111NPCS 3 0 0111 PCS 1111forbidden no peripheral is selected x don t care If PCSDEC 1 NPCSJ 3 0 output signals PCS 19 91 55800 1745D ATARM 04 Nov 05 91 55800 20 7 5 SPI Status Register Register Name SP SR Access Type Read only Reset State 0 Offset 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPENDTX SPENDRX OVRES MODF TDRE RDRF Receive Data Register Full Code Label SP_RDRF 0 No data has been received since the last read of SP 1 Data has been received and the received data has been transferred from the serializer to RDR since the last read of SP RDR Transmit Data Register Empty Code Label SP TDRE 0 Data has been written to and not yet transferred to the serializer 1 The last data written in the Transmit Data Register has been transferred in the serializer TDRE equals zero when the SPI is disabled or at reset The SPI enable command sets this bit to one Mode Fault Error Code Label SP 0 No Mode Fault has been detected since the last read of SP SR 1 Mode Fault occurred since the last read of the SP SR e OVRES Overrun Error Status Code Label OVRES 0 No overrun has been
32. Peripheral registers are only word accessible byte half word accesses not sup ported If a byte or a half word access is attempted the memory controller automatically masks the lowest address bits and generates a word access Each peripheral has a 16 Kbyte address space allocated the AIC only has a 4 Kbyte address space 8 1 Peripheral Registers The following registers are common to all peripherals e Control Register Write only register that triggers a command when a one is written to the corresponding position at the appropriate address Writing a zero has no effect Mode Register read write register that defines the configuration of the peripheral Usually has a value of 0x0 after a reset Data Register read and or write register that enables the exchange of data between the processor and the peripheral Status Register Read only register that returns the status of the peripheral Enable Disable Status Registers shadow command registers Writing one in the Enable Register sets the corresponding bit in the Status Register Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register Writing a bit to zero has no effect This register access method maximizes the efficiency of bit manipulation and enables modification of a register with a single non interruptible instruction replacing the costly read modify write operation
33. 0x48 Interrupt Mask Register PIO_IMR Read only 0 Ox4C Interrupt Status Register PIO ISR Read only see Note 0x50 Multi driver Enable Register PIO MDER Write only 0 54 Multi driver Disable Register PIO MDDR Write only 0 58 Multi driver Status Register PIO MDSR Read only 0 0x5C Reserved Notes 1 reset value of this register depends on the level of the external pins at reset 2 This register is cleared at reset However the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read A MEL 117 1745D ATARM 04 Nov 05 AMEL 16 9 1 PIO Enable Register Register Name PIO_PER Access Type Write only Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 7 6 5 4 3 2 1 0 P5 P pP P This register is used to enable individual pins to be controlled by the PIO Controller instead of the associated peripheral When the PIO is enabled the associated peripheral if any is held at logic zero 1 Enables the PIO to control the corresponding pin disables peripheral control of the pin 0 No effect 16 9 2 PIO Disable Register Register Name PIO PDR Access Type Write only Offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Po P P8 7 6 5 4 3 2 1 0 Ps Pa P FP j P j P This regi
34. 176 45 1 44 Figure 2 2 1745D ATARM 04 Nov 05 mnnn 91 55800 3 Pin Description Table 3 1 Pin Description Active Module Name Function Type Level Comments AO A23 Address bus Output DO D15 Data bus 50 NCS7 Chip select Output Low NWRO Lower byte 0 write signal Output Low Used in Byte write option NWR1 Lower byte 1 write signal Output Low Used in Byte write option NRD Read signal Output Low Used in Byte write option NWE Write enable Output Low Used in Byte select option NOE Output enable Output Low Used in Byte select option NUB Upper byte select Output Low Used in Byte select option NLB Lower byte select Output Low Used in Byte select option NWAIT Wait input Input Low BMS Boot mode select Input Sampled during reset IRQO IRQ5 External interrupt request Input PIO controlled after reset PS FIQ Fast external interrupt request Input PIO controlled after reset TCLKO TCLK5 Timer external clock Input PIO controlled after reset Timer TIOA5 Multipurpose timer I O pin PIO controlled after reset TIOBO TIOB5 Multipurpose timer pin B PIO controlled after reset SCKO SCK2 External serial clock E PIO controlled after reset USART TXDO TXD2 Transmit data output Output PIO controlled after reset RXDO RXD2 Receive data input Input PIO controlled after reset SPCK SPI clo
35. Base Address DAC 0 0xFFFA8000 Code Label DACO BASE Base Address DAC 1 0xFFFACOO0 Code Label DAC1 BASE Offset Register Name Access Reset State 0x00 Control Register DAC CR Write only 0 04 Mode Register DAC MR Read Write 0 0x08 Data Holding Register DAC DHR Read Write 0 0x0C Data Output Register DAC_DOR Read only 0 0x10 Status Register DAC_SR Read only 0 0x14 Interrupt Enable Register DAC_IER Write only _ 0x18 Interrupt Disable Register DAC_IDR Write only _ 0x1C Interrupt Mask Register DAC_IMR Read only 0 220 AT91M55800A mw ss mm nrsr rn 191 155800 22 2 1 DAC Control Register Register Name DAC_CR Access Type Write only Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SWRST Software Reset Code Label DAC SWRST 0 No effect 1 Resets the DAC A software triggered reset of the DAC interface is performed A MEL 221 1745D ATARM 04 Nov 05 AMEL 22 2 2 DAC Mode Register Register Name DAC_MR Access Type Read Write Reset State 0 Offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Low j j n TTRGSEL TTRGEN TTRGEN Timer Trigger Enable Code Label TTRGEN EN TTRGEN Selected TTRGEN Code Label The data written into the Data Holding Register DHR is transferred one main clock cycle later to the data output register DAC DOR The data tr
36. Current Year Code Label RTC YEAR The range that can be set is 00 99 BCD The lowest four bits encode the units The higher bits encode the tens MONTH Current Month Code Label RTC MONTH The range that can be set is 01 12 BCD The lowest four bits encode the units The higher bits encode the tens DAY Current Day Code Label RTC DAY The range that can be set is 1 7 BCD The significance of the number which number represents which day is user defined as it has no effect on the date counter DATE Current Date Code Label RTC DATE The range that can be set is 01 31 BCD The lowest four bits encode the units The higher bits encode the tens 80 AT91M55800A memm 1745D ATARM 04 Nov 05 mnn Y A 1 55800 13 3 5 RTC Time Alarm Register Register Name RTC_TAR Access Type Read Write Reset State 0x0 Offset 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HOUREN AMPM HOUR 15 14 13 12 11 10 9 8 MINEN MIN 7 6 5 4 3 2 1 0 SECEN SEC SEC Second Alarm This field is the alarm field corresponding to the BCD coded second counter SECEN Second Alarm Enable SECEN Selected SECEN Code Label 0 The second matching alarm is disabled RTC SEC ALARM DIS 1 The second matching alarm is enabled RTC SEC ALARM EN MIN Minute Alarm This field is the alarm field corresponding to the BCD coded minute counter MINEN Minute Alarm Enable MINEN Selected MINEN Code Label
37. IRQ OSC Timer PLL Timer APMCIRQ Advanced Peripheral Bus Note The RTC peripheral is described in a separate section 52 91 55800 1745D ATARM 04 Nov 05 KA T 9 1 155800 12 4 Operating Modes Five operating modes are supported by the APMC and offer different power consumption lev els and event response latency times Normal Mode The Main Power supply is switched on the ARM Core Clock is enabled and the peripheral clocks are enabled according to the application requirements dle Mode The Main Power is switched on the ARM Core Clock is disabled and waiting for the next interrupt or a main reset the peripheral clocks are enabled according to the application requirements and the PDC transfers are still possible Slow Clock Mode Similar to Normal Mode but the Main Oscillator and the PLL are switched off to save power the device core and peripheral run in Slow Clock Mode Note that Slow Clock Mode is the mode selected after the reset e Standby Mode A combination of the Slow Clock Mode and the Idle Mode which enables the processor to respond quickly to a wake up event by keeping very low power consumption Power down Mode The Main Power supply is turned off at the external power source until a programmable edge on the wake up signal or a programmable RTC Alarm occurs ATMEL s 1745D ATARM 04 Nov 05 Figure 12 2 Block Diagram
38. Load Overrun Status RA or RB has been loaded at least twice without any read of the corresponding register since the last read of the status LDRAS Load RA Status RA has been loaded at least once without any read since the last read of the status LDRBS Load RB Status RB has been loaded at least once without any read since the last read of the status ETRGS External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status A MEL 163 AIMEL EE Figure 19 4 Capture Mode inideo 1 151 i dO1S8d1 pepeo S VH Jl 19 14 91 1JO 9919 vagi 1911 9 pepeo Jo jou VH 9049413 obp3 SOLLIN LOX 09X 82 L MON 80N 91 55800 memme 164 1745D ATARM 04 Nov 05 mm 1 55800 19 4 Waveform Operating Mode This mode is entered by setting the WAVE parameter in TC CMR Channel Mode Register Waveform Operating Mode allows the TC Channel to generate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles or to generate different types of one shot or repetitive pulses In this mode TIOA is configured as output and TIOB is defined as output if it is not used as an
39. Offset Register Name Access Reset State 0x0000 Mode Register RTC_MR Read Write 0x00000000 0x0004 Hour Mode Register RTC_HMR Read Write 0x00000000 0x0008 Time Register RTC_TIMR Read Write 0x00000000 0 000 Calendar Register RTC CALR Read Write 0x01819819 0x0010 Time Alarm Register RTC TAR Read Write 0x00000000 0x0014 Calendar Alarm Register RTC CAR Read Write 0x00000000 0x0018 Status Register RTC_SR Read only 0x00000000 0x001C Status Clear Register RTC_SCR Write only 0 0020 Interrupt Enable Register IER Write only 0x0024 Interrupt Disable Register RTC_IDR Write only 0x0028 Interrupt Mask Register RTC_IMR Read only 0x00000000 0 002 Valid Entry Register RTC VER Read only 0x00000000 76 91 55800 ma YA 1 55800 13 3 1 RTC Mode Register Register Name RTC_MR Access Read Write Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Poo qp p s q 15 14 13 12 11 10 9 8 l d a 7 6 5 4 3 2 1 0 UPDTIM Update Request Time Register Code Label RTC UPDTIM 0 Enables the RTC time counting 1 Stops the RTC time counting Time counting consists of second minute and hour counters Time counters can be programmed once this bit is set UPDCAL Update Request Calendar Register Code Label RTC UPDCAL 0 Disables the RTC calendar counting 1 Stops the RTC calen
40. Return the value written in the AIC SVR corresponding to the current interrupt The previous step has effect to branch to the corresponding interrupt service routine This should start by saving the Link Register r14 irq and the SPSR SPSR irq Note that the Link Register must be decremented by 4 when it is saved if it is to be restored directly into the Program Counter at the end of the interrupt Further interrupts can then be unmasked by clearing the bit in the CPSR allowing re assertion of the NIRQ to be taken into account by the core This can occur if an interrupt with a higher priority than the current one occurs The Interrupt Handler can then proceed as required saving the registers which are used and restoring them at the end During this phase an interrupt of priority higher than the current level will restart the sequence from step 1 Note that if the interrupt is programmed to be level sensitive the source of the interrupt must be cleared during this phase The bit in the CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner The End Of Interrupt Command Register AIC EOICR must be written in order to indicate to the AIC that the current interrupt is finished This causes the current level to be popped from the stack restoring the previous current level if one exists on the stack If another interrupt is pending with lower or equal priority than old
41. WKACKS Wake up Acknowledge Alarm Shut down WKACKC Alarm Output ALWKEN Controller ALSHEN SHDALC SHDALS Backup Reset Shut down Alarm RTC Alarm NRSTBU Reset Backup Reset Control RTC 1 Slow Clock RTC Oscillator Battery Power VDDBU XOUT32 Main Power VDDIO VDDCORE Main Oscillator PRES Prescaler MCKODS MCK Master Clock D _ _ APMC PCSR NIRQ NFIQ ARM7TDMI Clock Peripheral Clocks Note 1 The RTC is described in another chapter 54 AT91M55800A 1745D ATARM 04 Nov 05 mmn 1 55800 12 2 Slow Clock Generator The AT91M55800A has a very low power 32 kHz oscillator powered by the backup battery voltage supplied on the VDDBU pins The XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal The oscillator has been especially designed to connect to a 6 pF typical load capacitance crystal and does not require any external capacitor as it integrates the XIN32 and XOUT32 capacitors to ground For a higher typical load capacitance two external capaci tances must be wired as shown in Figure 12 3 Figure 12 3 Higher Typical Load Capacitance XIN32 XOUT32 GNDPLL 12 12 2 1 Backup Reset Controller 12 2 2 Slow Clock 1745D ATARM 04 Nov 05 The backup reset controller initializes the logic supplied by the backup battery power A
42. check BCD and range 00 59 8 Second check BCD and range 00 59 Note If the 12 hour mode is selected by means of the MODE register a 12 hour value can be programmed and the returned value on TIME will be the corresponding 24 hour value The entry control checks the value of the AM PM indicator bit 22 of RTC_TIME register to determine the range to be checked 13 2 4 Updating Time Calendar 1745D ATARM 04 Nov 05 To update any of the time calendar fields the user must first stop the RTC by setting the corre sponding field in the Mode Register MR Bit UPDTIM must be set to update time fields hour minute second and bit UPDCAL must be set to update calendar fields century year month date day Then the user must poll or wait for the interrupt if enabled of bit ACKUPD in the Status Reg ister SR Once the bit reads 1 the user must clear this status bit by writing ACKUPD to 1 in SCR the user can write to the appropriate register Once the update is finished the user must reset 0 UPDTIM and or UPDCAL in the Mode Register MR When programming the calendar fields the time fields remain enabled This avoids a time slip in case the user stays in the calendar update phase for several tens of seconds or more ATMEL 13 3 RTC User Interface Base Address 0xFFFB8000 Code Label RTC BASE AMEL Table 13 1 Memory
43. the following EBI behavior is correct NWAIT is asserted before the first rising edge of the master clock and respects the NWAIT to MCKI rising setup timing as defined in the Electrical Characteristics datasheet NWAIT is sampled inactive and at least one standard wait state remains to be executed even if NWAIT does not meet the NWAIT to first MCKI rising setup timing NWAIT is asserted only on the second rising edge of MCKI In these cases the access is delayed as required by NWAIT and the access operations are correctly performed A191 55800A In other cases the following erroneous behavior occurs 32 bit read accesses are not managed correctly and the first 16 bit data sampling takes into account only the standard wait states 16 and 8 bit accesses are not affected During write accesses of any type the NWE rises on the rising edge of the last cycle as defined by the programmed number of wait states However NWAIT assertion does affect the length of the total access Only the NWE pulse length is inaccurate At maximum speed asserting the NWAIT in the first access cycle is not possible as the sum of the timings Falling to Chip Select and NWAIT setup to rising are generally higher than one half of a clock period This leads to using at least one standard wait state However this is not sufficient except to perform byte or half word read accesses Wo
44. 0 1 Set TC ACPA SET OUTPUT 1 0 Clear TC ACPA CLEAR OUTPUT 1 1 Toggle TC ACPA TOGGLE OUTPUT ACPC RC Compare Effect on TIOA ACPC Effect Code Label TC ACPC 0 0 None TC ACPC OUTPUT NONE 0 1 Set TC ACPC SET OUTPUT 1 0 Clear TC ACPC CLEAR OUTPUT 1 1 Toggle TC ACPC TOGGLE OUTPUT A MEL 175 1745D ATARM 04 Nov 05 AEEVT External Event Effect on AMEL AEEVT Effect Code Label TC_AEEVT 0 0 TC AEEVT OUTPUT NONE 0 1 Set TC AEEVT SET OUTPUT 1 0 Clear TC AEEVT CLEAR OUTPUT 1 1 Toggle C AEEVT TOGGLE OUTPUT ASWTRG Software Trigger Effect on TIOA ASWTRG Effect Code Label TC ASWTRG 0 0 None TC ASWTRG OUTPUT NONE 0 1 Set TC ASWTRG SET OUTPU 1 0 Clear TC ASWTRG CLEAR OUTPUT 1 1 Toggle C ASWTRG TOGGLE OUTPUT BCPB RB Compare Effect on TIOB BCPB Effect Code Label TC BCPB 0 None TC BCPB OUTPUT NONE 0 Set TC BCPB SET OUTPUT 1 Clear TC BCPB CLEAR OUTPUT 1 Toggle TC BCPB TOGGLE OUTPUT BCPC RC Compare Effect on TIOB BCPC Effect Code Label TC BCPC 0 None TC BCPC OUTPUT NONE 0 Set TC BCPC SET OUTPUT 1 Clear TC BCPC CLEAR OUTPUT 1 Toggle TC BCPC TOGGLE OUTPUT BEEVT External Event Effect on TIOB BEEVT Eff
45. 0x00 System Clock Enable Register APMC_SCER 0 04 System Clock Disable Register SCDR 0x08 System Clock Status Register SCSR R 0 1 0x0C Reserved 0x10 Peripheral Clock Enable Register APMC_PCER 0x14 Peripheral Clock Disable Register APMC_PCDR W 0x18 Peripheral Clock Status Register APMC_PCSR R 0 0x1C Reserved W 0 20 Clock Generator Mode Register CGMR R W 0 0 24 Reserved 0 28 Power Control Register APMC PCR 0 2 Power Mode Register APMC PMR R W 0 1 0 30 Status Register APMC SR R 0 34 Interrupt Enable Register APMC IER 0x38 Interrupt Disable Register APMC IDR W Ox3C Interrupt Mask Register IMR R 0 1745D ATARM 04 Nov 05 A191 55800A 12 9 1 APMC System Clock Enable Register Register Name APMC SCER Access Type Write only Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d ee CPU System Clock Enable Bit 0 No effect 1 Enables the System Clock 12 9 2 APMC System Clock Disable Register Register Name APMC_SCDR Access Type Write only Offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPU System Clock Disable Bit 0 No effect 1 Disables the System Clock ATMEL 1745D ATARM 04 Nov 05 AMEL
46. 17 16 E _ ce CL pe DACO ADC 15 14 13 12 11 10 9 8 ADCO PIOB Ts 13 t 7 6 5 4 3 2 1 0 To j s ue u Peripheral Clock Status per peripheral 0 The peripheral clock is disabled 1 The peripheral clock is enabled AMEL 1745D ATARM 04 Nov 05 AMEL 12 9 7 APMC Clock Generator Mode Register Register Name APMC_CGMR Access Type Read Write Reset Value 0x0 Offset 0x20 31 30 29 28 27 26 25 24 ld PLLCOUNT 23 22 21 20 19 18 17 16 OSCOUNT 15 14 13 12 11 10 9 8 CSS MUL 6 5 4 3 2 1 0 PRES MCKODS MOSCEN MOSCBYP MOSCBYP Main Oscillator Bypass Code Label APMC MOSC BYP 0 Crystal must be connected between XIN and XOUT 1 External clock must be provided on XIN MOSCEN Main Oscillator Enable Code Label APMC MOSC EN 0 Main Oscillator is disabled 1 Main Oscillator is enabled Note When operating in Bypass Mode the Main Oscillator must be disabled MOSCEN and MOSCBYP bits must never be set together MCKODS Master Clock Output Disable Code Label APMC MCKO DIS 0 The MCKO pin is driven with the Master Clock 1 The MCKO pin is tri stated PRES Prescaler Selection PRES Prescaler Selected Code Label 0 0 0 None Prescaler Output is the selected clock APMC PRES NONE 0 0 1 Selected clock is divided by 2 PRES DIV2 0 1 0 Selected clock is divided by 4 APMC PRE
47. 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 N E o RB Register B Code Label TC RB contains the Register B value in real time 19 5 9 TC Register C Register Name TC RC Access Type Read Write Reset State 0 Offset Ox1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ER _ A A N _ ssi A 2 A o 2 O RC Register C Code Label TC RC contains the Register C value in real time ATMEL 1745D ATARM 04 Nov 05 AMEL 19 5 10 TC Status Register Register Name TC_SR Access Type Read Write Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p c qp c c iji MOS MTIOA CLKSTA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS e COVFS Counter Overflow Status Code Label TC 5 0 No counter overflow has occurred since the last read of the Status Register 1 counter overflow has occurred since the last read of the Status Register e LOVRS Load Overrun Status Code Label LOVRS 0 Load overrun has not occurred since the last read of the Status Register or WAVE 1 1 RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta tus Register if WAVE 0 CPAS RA Compare Status Code Label TC CPAS 0 RA Compare has not occurred since t
48. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tok MOSCS Main Oscillator Interrupt Disable Code Label APMC MOSCS 0 No effect 1 Disables the Main Oscillator Stabilized Interrupt LOCK PLL Lock Interrupt Disable Code Label PLL LOCK 0 No effect 1 Disables the PLL Lock Interrupt 12 9 13 APMC Interrupt Mask Register Register Name APMC_IMR Access Type Read only Reset Value 0 0 Offset Ox3C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tok woscs MOSCS Main Oscillator Interrupt Mask Code Label Moscs 0 The Main Oscillator Interrupt is disabled 1 The Main Oscillator Interrupt is enabled LOCK PLL Lock Interrupt Mask Code Label APMC PLL LOCK 0 The PLL Lock Interrupt is disabled 1 The PLL Lock Interrupt is enabled 72 AT91M55800A memm mnr 1 55800 13 RTC Real time Clock The 91 55800 features a Real time Clock RTC peripheral that is designed for very low power consumption It combines a complete time of day clock with alarm and a two hundred year Gregorian calendar complemented by a programmable periodic interrupt The time and calendar values are coded in Binary Coded Decimal BCD format The time for mat can be 24 hour mode or 12 hour mode with an AM PM indicator Updating time and calendar fields and
49. 5 3 A o zh 20 7 42 SPI Transmit Counter Register Name SP TCR Access Type Read Write Reset State 0 Offset 0 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E E E Em o TXCTR TXCTR gt lt m o 2 o 3 3 TXCTR must be loaded with the size of the transmit buffer 0 Stop Peripheral Data Transfer dedicated to the transmitter 1 65535 Start Peripheral Data transfer if TDRE is active N 1 55800 20 7 13 SPI Chip Select Register Register Name CSRO SP_CSR3 Access Type Read Write Reset State 0 Offset 0x30 0x3C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CPOL Clock Polarity Code Label sP CPOL 0 The inactive state value of SPCK is logic level zero 1 The inactive state value of SPCK is logic level one CPOL is used to determine the inactive state value of the serial clock SPCK It is used with NCPHA to produce a desired clock data relationship between master and slave devices NCPHA Clock Phase Code Label 8 NCPHA 0 Data is changed on the leading edge of SPCK and captured on the following edge of SPCK 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK NCPHA determines which ed
50. ATARM 04 Nov 05 J A191 55800A EEVTEDG External Event Edge Selection EEVTEDG Edge Code Label TC EEVTEDG 0 0 None TC EEVTEDG EDGE NONE 0 1 Rising edge TC EEVTEDG RISING EDGE 1 0 Falling edge TC EEVTEDG FALLING EDGE 1 1 Each edge TC EEVTEDG BOTH EDGE EEVT External Event Selection Signal Selected as EEVT External Event TIOB Direction Code Label TC EEVT 0 0 TIOB Input TC EEVT TIOB 0 1 XCO Output TC EEVT XCO 1 0 XC1 Output TC EEVT 1 1 XC2 Output TC EEVT XC2 Note If TIOB is chosen as the external event signal it is configured as an input and no longer generates waveforms ENETRG External Event Trigger Enable Code Label TC ENETRG 0 The external event has no effect on the counter and its clock In this case the selected external event only controls the TIOA output 1 The external event resets the counter and starts the counter clock CPCTRG RC Compare Trigger Enable Code Label CPCTRG 0 RC Compare has no effect on the counter and its clock 1 RC Compare resets the counter and starts the counter clock WAVE 1 Code Label TC WAVE 0 Waveform Mode is disabled Capture Mode is enabled 1 Waveform Mode is enabled ACPA RA Compare Effect on TIOA ACPA Effect Code Label TC ACPA 0 0 None TC ACPA OUTPUT NONE
51. ATARM 04 Nov 05 AMEL 19 5 4 TC Channel Mode Register Capture Mode Register Name TC_CMR Access Type Read Write Reset State 0 Offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 twm J 15 14 13 12 11 10 9 8 crema emee 7 6 5 4 3 2 1 0 TCCLKS Clock Selection TCCLKS Clock Selected Code Label TC CLKS 0 0 0 MCK 2 TC CLKS MCK2 0 0 1 MCK 8 TC CLKS MCK8 0 1 0 MCK 32 TC CLKS MCK32 0 1 1 MCK 128 TC CLKS MCK128 1 0 0 MCK 1024 TC CLKS MCK1024 1 0 1 XCO TC CLKS XCO 1 1 0 XC1 TC CLKS XC1 1 1 1 XC2 TC CLKS XC2 CLKI Clock Invert Code Label TC CLKI 0 Counter is incremented on rising edge of the clock 1 Counter is incremented on falling edge of the clock BURST Burst Signal Selection BURST Selected BURST Code Label TC BURST 0 0 The clock is not gated by an external signal TC BURST NONE 0 1 is ANDed with the selected clock TC BURST XCO 1 0 XC1 is ANDed with the selected clock TC BURST XC1 1 1 XC2 is ANDed with the selected clock TC BURST XC2 LDBSTOP Counter Clock Stopped with RB Loading Code Label TC LDBSTOP 0 Counter clock is not stopped when RB loading occurs 1 Counter clock is stopped when RB loading occurs LDBDIS Counter Clock Disable with RB Loading Code Label TC LDBDIS 0 Counter clock is not disabled when RB loading occurs 1 Counte
52. ENDRX 0 No effect 1 Disables the End of Receiver Transfer Interrupt SPENDTX End of Transmitter Transfer Interrupt Disable Code Label SP_ENDTX 0 No effect 1 Disables the End of Transmitter Transfer Interrupt A MEL 201 1745D ATARM 04 Nov 05 AMEL 20 7 8 SPI Interrupt Mask Register Register Name SP_IMR Access Type Read only Reset State 0 Offset Ox1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPENDTX SPENDRX OVRES MODF TDRE RDRF Receive Data Register Full Interrupt Mask Code Label SP RDRF 0 Receive Data Register Full Interrupt is disabled 1 Receive Data Register Full Interrupt is enabled TDRE Transmit Data Register Empty Interrupt Mask Code Label SP TDRE 0 Transmit Data Register Empty Interrupt is disabled 1 2 Transmit Data Register Empty Interrupt is enabled MODF Mode Fault Interrupt Mask Code Label SP MODF 0 Mode Fault Interrupt is disabled 1 Mode Fault Interrupt is enabled OVRES Overrun Error Interrupt Mask Code Label SP_OVRES 0 Overrun Error Interrupt is disabled 1 Overrun Error Interrupt is enabled SPENDRX End of Receiver Transfer Interrupt Mask Code Label SP_ENDRX 0 End of Receiver Transfer Interrupt is disabled 1 End of Receiver Transfer Interrupt is enabled SPENDTX End of Transmitter Transfer Interrupt Mask Code Label sP ENDTX 0 End of Transmitter
53. If WAVE 0 this means that TIOA pin is high If WAVE 1 this means that TIOA is driven high 10 AT91M55800A mmm mnnn 1 55800 MTIOB TIOB Mirror Code Label MTIOB 0 TIOB is low If WAVE 0 this means that TIOB pin is low If WAVE 1 this means that TIOB is driven low 1 is high If WAVE 0 this means that pin is high If WAVE 1 this means that TIOB is driven high AIMEL i 1745D ATARM 04 Nov 05 Gw AMEL 19 5 11 TC Interrupt Enable Register Register Name TC IER Access Type Write only Offset 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS Counter Overflow Code Label TC covrs 0 No effect 1 Enables the Counter Overflow Interrupt LOVRS Load Overrun Code Label TC LovRns 0 No effect 1 Enables the Load Overrun Interrupt CPAS RA Compare Code Label TC CPAS 0 No effect 1 Enables the RA Compare Interrupt CPBS RB Compare Code Label TC CPBS 0 No effect 1 Enables the RB Compare Interrupt CPCS RC Compare Code Label TC CPCS 0 No effect 1 Enables the RC Compare Interrupt LDRAS RA Loading Code Label TC LDRAS 0 No effect 1 Enables the RA Load Interrupt LDRBS RB Loading Code Label TC LDRBS 0 No effect 1 Enables the RB Load Interrupt ETRGS External Trigger Code Label TC ETRGS 0 No effect 1 Enables the E
54. Modes 140 Each USART channel is closely connected to a corresponding Peripheral Data Controller channel One is dedicated to the receiver The other is dedicated to the transmitter Note The PDC is disabled if 9 bit character length is selected MODE9 1 in US MR The PDC channel is programmed using 05 TPR Transmit Pointer and US TCR Transmit Counter for the transmitter and 05 Receive Pointer and 05 Receive Counter for the receiver The status of the PDC is given US by the ENDTX bit for the transmit ter and by the ENDRX bit for the receiver The pointer registers 05 and US are used to store the address of the transmit or receive buffers The counter registers 05 TCR and 05 RCR are used to store the size of these buffers The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is triggered by TXRDY When a transfer is performed the counter is decremented and the pointer is incremented When the counter reaches 0 the status bit is set ENDRX for the receiver ENDTX for the transmitter in 05 CSR and can be programmed to generate an inter rupt Transfers are then disabled until a new non zero counter value is programmed Interrupt Generation Each status bit in 05 CSR has a corresponding bit in US IER Interrupt Enable and US IDR Interrupt Disable which controls the generation of interrupts by asserting the USART inter rupt line connected to the
55. N I VA READ ACCESS Standard Protocol NRD Internal Bus Bi I Early Protocol NRD N DO D15 B2B WRITE ACCESS Byte Write l Byte Select Option AMEL i 1745D ATARM 04 Nov 05 AMEL Figure 11 22 0 Wait States 8 bit Bus Width Word Transfer MCK AO A23 NCS READ ACCESS ADDR ADDR 1 ADDR 2 ADDR 3 I I E pue tege pq tec Early Protocol NRD DO D15 WRITE ACCESS DO D15 44 AT91M55800A memme mmn A 1 55800 Figure 11 23 1 Wait State 8 bit Bus Width Half word Transfer lt 1 Wait State 1 Wait State TEE 2 D mias ucc n r M OI Standard Protocol 1 DO D15 X Bh X Bb Internal Bus XIX X B B2 Bi Early Protocol NRD 00 D15 XB WRITE ACCESS 00 015 AMEL a 1745D ATARM 04 Nov 05 AMEL Figure 11 24 1 Wait
56. Problem Fix Workaround The user should minimally access the Advanced Peripheral Bus by using an interrupt driven driver rather than polling methods 1745D ATARM 04 Nov 05 mr n 1 55800 Rrevision History Doc Rev Date Comments Change Request Ret 1745A July 2001 First Issue First issue 1745B 18 Jul 2002 Page 9 Change to Block Diagram Page 9 Peripherals Text changed Page 10 User Peripherals Text changed Page 16 Internal Memories Text added to paragraph Page 16 Peripheral Data Controller Text changed Page 18 Digital to analog Converter Text changed Page 204 Digital to analog Converter Text changed Page 205 8 to 10 bit Conversion Mode Text changed 1745C 16 Dec 2002 Page 195 Analog to Digitial Conversion Text removed Page 199 PRESCAL Text changed Equation modified Page 219 220 Table 25 bit 30 and bit 12 changed Global Change in format introduced Chapter numbering with change to table and figure 1745D 03 Oct 05 numbering Package reference TQFP changed to LQFP page 235 Section 24 Packaging Information Chapters added to page 238 Section 25 Soldering Profile correspond with page 239 Section 26 Ordering Information Summary page 14 Section 7 4 2 NTRST Pin info added CSR 05 451 Figure 7 1 Separate or Common Reset Management added to chapter page 240 Section 27 Errata added to and dedicated AT91 documentation errata do
57. Register Name APMC_SR Access Type Read only Offset 0x30 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E C o L o MOSCS MOSCS Main Oscillator Status Code Label APMC MOSCS 0 Main Oscillator output signal is not stabilized or the Main Oscillator is disabled 1 The Main Oscillator is enabled and its output is stabilized Actually this bit indicates that the Main Oscillator counter reached 0 e LOCK PLL Lock Status Code Label PLL LOCK 0 PLL output signal or main oscillator output signal is not stabilized or the main oscillator is disabled 1 Main Oscillator is enabled its output is stabilized and the PLL output signal is stabilized Actually this bit is set when the PLL Lock Counter reaches 0 12 9 11 APMC Interrupt Enable Register Register Name APMC IER Access Type Write only Offset 0x34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ tok woss MOSCS Main Oscillator Interrupt Enable Code Label APMC MOSCS 0 No effect 1 Enables the Main Oscillator Stabilized Interrupt e LOCK PLL Lock Interrupt Enable Code Label PLL LOCK 0 No effect 1 Enables the PLL Lock Interrupt AIMEL n 1745D ATARM 04 Nov 05 AMEL 12 9 12 APMC Interrupt Disable Register Register Name Access Type Write only Offset 0x38 31
58. SF PMR Read Write 0 0 123 91 55800 1745D ATARM 04 Nov 05 mI nn 1 55800 17 2 1 Chip ID Register Register Name SF CIDR Access Type Read only Offset 0x00 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH VDSIZ 15 14 13 12 11 10 9 8 NVDSIZ NVPSIZ 6 5 4 3 2 1 0 7 L o 1 VERSION VERSION Version of the chip Code Label sF VERSION This value is incremented by one with each new version of the chip from zero to a maximum value of 31 NVPSIZ Nonvolatile Program Memory Size NVPSIZ Size Code Label SF NVPSIZ 0 0 0 0 None NVPSIZ NONE 0 0 1 1 32K Bytes SF NVPSIZ 32K 0 1 0 1 64K Bytes SF NVP SIZ 64K 0 1 1 1 128K Bytes SF NVP SIZ 128K 1 0 0 1 256K Bytes SF NVP SIZ 256K Others Reserved NVDSIZ Nonvolatile Data Memory Size NVDSIZ Size Code Label SF NVDSIZ 0 0 0 0 None SF NVDSIZ NONE Others Reserved VDSIZ Volatile Data Memory Size VDSIZ Size Code Label SF VDSIZ 0 0 0 0 None SF VDSIZ NONE 0 0 0 1 1K Bytes SF VDSIZ 1K 0 0 1 0 2K Bytes SF VDSIZ 2K 0 1 0 0 4K Bytes SF VDSIZ 4K 1 0 0 0 8K Bytes SF VDSIZ 8K Others Reserved AMEL 1745D ATARM 04 Nov 05 AMEL e ARCH Chip Architecture Code of Architecture Two BCD digits ARCH Selected ARCH Code Label SF_ARCH 0110 0011 AT91x63yyy SF_ARCH_AT91x63
59. Transfer Interrupt is disabled 1 End of Transmitter Transfer Interrupt is enabled mm vY A191 55800A 20 7 9 SPI Receive Pointer Register Name SP_RPR Access Type Read Write Reset State 0 Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPTR Receive Pointer RXPTR must be loaded with the address of the receive buffer 20 7 10 SPI Receive Counter Register Name SP RCR Access Type Read Write Reset State 0 Offset 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXCTR RXCTR N a 2 o lt o E o x 3 a gt 5 E must be loaded with the size of the receive buffer 0 Stop Peripheral Data Transfer dedicated to the receiver 1 65535 Start Peripheral Data transfer if RDRF is active AIMEL 1745D ATARM 04 Nov 05 www AMEL 20 7 11 SPI Transmit Pointer Register Name SP_TPR Access Type Read Write Reset State 0 Offset 0x28 31 30 TXPTR 23 A N E N E TXPTR E E Em TXPTR TXPTR x 3 gt g 3 Bo o 9 3 52 s te 5 gt E D a gt
60. Variable Peripheral NPCS SP_TDR PCS NPCS SP_MR PCS Delay DLYBS Serializer SP_TDR TD TDRE 1 Data Transfer SP RDR RD Serializer 1 Delay DLYBCT NPCS OxF 1 Variable Peripheral SP TDR PCS New Peripheral NPCS OxF Delay DLYBCS NPCS SP TDR PCS O Fixed Peripheral Same Peripheral 91 55800 Figure 20 2 in Master Mode MR MCK32 SPCK Clock Generator SPI MCK MCK 32 Clock SE CSRxIIS 0 D S Q E Z SP MR PCS E SP 115 OlIDIIDIIVIIP 1 D R IRIIRI II F EJ F EJJE 1 1 i i 511 1 1 I 4 J 5 IER ISP IDR 1 SPIRQ A MEL 189 1745D ATARM 04 Nov 05 AMEL 20 3 Slave Mode In Slave Mode the SPI waits for NSS to go active low before receiving the serial clock from an external master In slave mode CPOL NCPHA and BITS fields of SP_CSRO are used to define the transfer characteristics The other Chip Select Registers are not used in slave mode Figure 3 SPI in Slave Mode P 1 i SP_RDR 1 1 1 1 LSB vos r erializer MISO 1 1 1 1 1 1 1 SP TDR SP IER 5 IDR ISP IMR 190 AT91M55800A mmm 1 55800 20 4 Data Transfer The following waveforms show examples of data transfers Figure 20 3 SPI
61. are done All non significant bits read O A MEL 223 1745D ATARM 04 Nov 05 22 2 4 Register Access Type Reset State Offset AMEL DAC Output Register DAC_DOR Read only 0 0x0C N A N E E E N E E E E DATA DATA DATA Data being Converted Code Label DATA 10BITS or DAC DATA 8BITS depending on RES Data being converted is stored in a right aligned format in this register All non significant bits read O 22 2 5 DAC Status Register Register Name DAC SR Access Type Read only Reset State 0 Offset 0x10 31 30 29 28 27 26 25 24 N A N A E E E N m 0 DATRDY DATRDY Data Ready for Conversion Code Label DAC DATRDY 0 Data has been written to the Data Holding Register and not yet transferred to the Data Output Register 1 The last data written in the Data Holding Register has been transferred to the Data Output Register This is equal to 0 when the Timer Trigger is disabled or at reset Enabling the Timer Trigger sets this bit to 1 A191 55800A 22 2 6 DAC Interrupt Enable Register Register Name DAC IER Access Type Write only Offset 0 14 31 30 24 29 28 27 26 25
62. at the following configuration for chip select 8 wait states WSE 1 NWS 7 8 bit or 16 bit data bus width depending on BMS Byte access type and number of data float time are respectively set to Byte write Access and 0 With a nonvolatile memory interface any value can be programmed for these parameters Before the remap command the user can modify the chip select O configuration programming the CSRO with exact boot memory characteristics The base address becomes effective after the remap command but the new number of wait states can be changed immediately This is useful if a boot sequence needs to be faster ATMEL 11 6 Read Protocols AMEL The EBI provides two alternative protocols for external memory read access standard and early read The difference between the two protocols lies in the timing of the NRD read cycle waveform The protocol is selected by the field in Memory Control Register and is valid for all memory devices Standard read protocol is the default protocol after reset Note Inthe following waveforms and descriptions NRD represents NRD and NOE since the two sig nals have the same waveform Likewise NWE represents NWE NWRO NWR1 unless NWRO NWRI are otherwise represented ADDR represents AO A23 and or A1 A23 11 6 1 Standard Read Protocol Standard read protocol implements a read cycle in which NRD and NWE are similar Both are active dur
63. been requested even though TXRDY 1 in US CSR Anew STTBRK command must not be issued until an existing break has ended TXEMPTY 1 in 05 CSR 138 91 55800 memme 1 55800 The standard break transmission sequence is 1 Wait for the transmitter ready US CSR TXRDY 1 2 Sendthe STTBRK command write 0 0200 to 05 CR 3 Wait for the transmitter ready bit TXRDY 1 in US CSR 4 Sendthe STPBRK command write 0 0400 to 05 CR The next byte can then be sent 5 Wait for the transmitter ready bit TXRDY 1 in US CSR 6 Sendthe next byte write byte to 05 THR Each of these steps can be scheduled by using the interrupt if the bit TXRDY in 05 IMR is set For character transmission the USART channel must be enabled before sending a break 18 6 2 Receive Break The receiver detects a break condition when all data parity and stop bits are low When the low stop bit is detected the receiver asserts the RXBRK bit in US An end of receive break is detected by a high level for at least 1 bit 1 16 of a bit period in asynchronous oper ating mode or at least one sample in synchronous operating mode RXBRK is also asserted when an end of break is detected Both the beginning and the end of a break can be detected by interrupt if the bit US IMR RXBRK is set A MEL 139 1745D ATARM 04 Nov 05 AMEL 18 7 Peripheral Data Controller 18 8 18 9 Channel
64. configuring the alarm fields is performed by a parallel capture on the 32 bit data bus An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month year century 13 1 Year 2000 Conformity The Real time Clock complies fully with the Year 2000 Conformity Requirements as stated in the British Standards Institution Document Ref BSI DISC PD2000 1 Year 2000 conformity shall mean that neither performance nor functionality is affected by dates prior to during and after the year 2000 It has been tested to be compliant with the four associated rules 1 No value for current date will cause any interruption in operation 2 Date based functionality must behave consistently for dates prior to during and after year 2000 3 In all interfaces and data storage the century in any date must be specified either explicitly or by unambiguous algorithms or inferencing rules 4 Year 2000 must be recognized as a leap year The RTC represents the year as a four digit number 1998 1999 2000 2001 etc so that the century is unambiguously identified in accordance with Rule 3 Figure 13 1 RTC Block Diagram SLCK Slow Clock Advanced Peripheral Bus 1745D ATARM 04 Nov 05 RTCIRQ 32768 Divider Bus Interface Interrupt Control Entry Control AMEL 7 AMEL 13 2 Functional Description 13 2 1 13 2 2 13 2 3 7
65. contains a character waiting to be transferred to the Transmit Shift Register or an STTBRK command has been requested 1 US_THR is empty and there is no Break request pending TSR availability Equal to zero when the USART is disabled or at reset Transmitter Enable command in 05 CR sets this bit to one RXBRK Break Received End of Break Code Label US RXBRK 0 No Break Received nor End of Break detected since the last Reset Status Bits command in the Control Register 1 Break Received or End of Break detected since the last Reset Status Bits command in the Control Register e ENDRX End of Receive Transfer Code Label 05 ENDRX 0 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive 1 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active ENDTX End of Transmit Transfer Code Label 08 ENDTX 0 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive 1 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active OVRE Overrun Error Code Label US OVRE 0 No byte has been transferred from the Receive Shift Register to the US when RxRDY was asserted since the last Reset Status Bits command 1 At least one byte has been transferred from the Receive Shift Register to the 05 when RxRDY wa
66. default state Shut down Logic Initialized in the Wake up state or Non Alarm The Power Mode Register Shut down defines SHDN as level 0 SHDALS 1 Wake up defines SHDN as tri state WKACKS 0 The Real time Clock Configuration and Data Registers A simple RC network can be used as a power on reset for the battery supply The pin SHDN is tri stated by default An external resistor must hold the main power supply shut down pin in the inactive state The shut down logic can be programmed with the correct active level of the power supply shut down input during the first start up sequence The first time the system is powered up the SHDN pin is tri stated because different power supplies use different logic levels for their shut down input signals To minimize backup bat tery power consumption there is no internal pull up or pull down on this signal If the power supply needs a logic level on its shut down input in order to start the main power supply then an external Force Start Up jumper is required to provide this level The jumper provides the necessary level on the SHDN to maintain the power supply when the AT91 boots and it can be removed until the next loss of battery power ATMEL 12 9 User Interface Base Address 0xFFFF4000 Code Label APMC BASE AMEL Table 12 1 APMC Memory Offset Register Name Access Main Reset Backup Reset
67. filter is selected and the PIO Controller clock is disabled either the signal on the peripheral input or the corre sponding bit in PIO PDSR remains at the current state 16 9 10 PIO Set Output Data Register Register Name PIO SODR Access Type Write only Offset Ox30 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22 21 15 14 13 12 11 10 9 8 Pi Pa P3 a j P j P P O 7 6 5 4 3 2 1 0 pm pre P P P P j Pr This register is used to set PIO output data It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO Otherwise the information is stored 1 PIO output data on the corresponding pin is set 0 No effect 122 AT91M55800A memm r A 1 55800 16 9 11 PIO Clear Output Data Register Register Name CODR Access Type Write only Offset 0x34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 pis Pa P3 Pt Po 9 P 7 6 5 4 3 2 1 0 7 re Ps P P j P This register is used to clear PIO output data It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO Otherwise the information is stored 1 PIO output data on the corresponding pin is cleared 0 No effect 16 9 12 PIO Output Data Status Register Register Name PIO ODSR Access Type Read only Offset 0x38 Reset Va
68. in any application phase the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption AMEL 7 3 7 4 7 4 1 7 4 2 14 Master Clock Reset NRST Pin NTRST Pin AT91M55800A AMEL Master Clock is generated in one of the following ways depending on programming in the APMC registers From the 32768 Hz low power oscillator that clocks the RTC The on chip main oscillator together with a PLL generate a software programmable main clock in the 500 Hz to 33 MHz range The main oscillator can be bypassed to allow the user to enter an external clock signal The Master Clock MCK is also provided as an output of the device on the pin MCKO whose state is controlled by the APMC module Reset restores the default states of the user interface registers defined in the user interface of each peripheral and forces the ARM7TDMI to perform the next instruction fetch from address zero Aside from the program counter the ARM7TDMI registers do not have defined reset states NRST is active low level input It is asserted asynchronously but exit from reset is synchro nized internally to the MCK At reset the source of MCK is the Slow Clock 32768 Hz crystal and the signal presented on MCK must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation Test Access Port TAP reset functionality is provide
69. is preloaded with the PLLCOUNT value when the MUL field in the Clock Generator Mode register CGMR is modified but only if the MUL value is different from 0 PLL disabled and also the PLLCOUNT value itself different from Ox0 PLLCOUNT must be loaded with a minimum value of 2 in order to guarantee a time of at least one slow clock period ATMEL s7 1745D ATARM 04 Nov 05 AMEL 12 9 8 APMC Power Control Register Register Name APMC_PCR Access Type Write only Offset 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHDALC Shut down or Alarm Command Code Label SHDALC 0 No effect 1 Configures the SHDN pin as defined by the field SHDALS in WKACKC Wake up or Alarm Acknowledge Command Code Label APMC WKACKC 0 No effect 1 Configures the SHDN pin as defined by the field WKACKS Note If both the SHDALC and WKACKS bits are set the WKACKS command has priority 68 91 55800 memm 1 55800 12 9 9 APMC Power Mode Register Register Name APMC PMR Access Type Read Write Backup Reset 0 1 Offset 0 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEDG ALSHEN ALWKEN WKACKS SHDALS SHDALS Shut down or Alarm Output Selection This field defines the state of the SHDAL pin
70. memory can store twice as many Thumb instructions as ARM ones Boot Mode Select The ARM reset vector is at address 0x0 After the NRST line is released the ARM7TDMI exe cutes the instruction stored at this address This means that this address must be mapped in nonvolatile memory after the reset The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory see Table 7 2 The pin BMS is multiplexed with the I O line PB18 that can be programmed after reset like any standard PIO line Table 7 2 Boot Mode Select BMS Boot Mode 1 External 8 bit memory on NCSO 0 External 16 bit memory on NCSO Remap Command Abort Control The ARM vectors Reset Abort Data Abort Prefetch Abort Undefined Instruction Interrupt Fast Interrupt are mapped from address 0 0 to address 0x20 In order to allow these vectors to be redefined dynamically by the software the AT91M55800A microcontroller uses a remap command that enables switching between the boot memory and the internal RAM bank addresses The remap command is accessible through the EBI User Interface by writing one in RCB of EBI RCR Remap Control Register Performing a remap command is mandatory if access to the other external devices connected to chip selects 1 to 7 is required The remap operation can only be changed back by an internal reset or an NRST assertion The abort signal providing a Data Abo
71. operate in Asynchronous Mode SYNC 0 in the Mode Register US the selected clock is divided by 16 times the value CD written in US BRGR Baud Rate Generator Register If US BRGR is set to 0 the Baud Rate Clock is disabled Selected Clock Baud Rate 16x CD When the USART is programmed to operate in Synchronous Mode SYNC 1 and the selected clock is internal USCLKS 1 0 in the Mode Register 05 MR the Baud Rate Clock is the internal selected clock divided by the value written in US BRGR If US BRGR is set to 0 the Baud Rate Clock is disabled Baud Rate Selected Clock CD In Synchronous Mode with external clock selected USCLKS 1 1 the clock is provided directly by the signal on the SCK pin No division is active The value written in US_BRGR has no effect Figure 18 2 Baud Rate Generator M 134 MCK CK 8 SCK 91 55800 Baud Rate Clock 1745D ATARM 04 Nov 05 1 55800 18 3 Receiver 18 3 1 Asynchronous Receiver The USART is configured for asynchronous operation when SYNC 0 bit 7 of US In asynchronous mode the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit A low level space on RXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock which is 16 times the baud rate Hence a space which is longer than 7 16 of the bit pe
72. read cycle to allow time for the write cycle to end before the subsequent read cycle begins see Figure 11 9 This wait state is generated in addition to any other pro grammed wait states i e data float wait No wait state is added when a read cycle is followed by a write cycle between consecutive accesses of the same type or between external and internal memory accesses Early read wait states affect the external bus only They do not affect internal bus timing Figure 11 9 Early Read Wait State Write Cycle Early Read Wait i Read Cycle NCS N N NRD NWE l AMEL s 1745D ATARM 04 Nov 05 32 AMEL Write Data Hold Time During write cycles in both protocols output data becomes valid after the falling edge of the NWE signal and remains valid after the rising edge of NWE as illustrated in the figure below The external NWE waveform on the NWE pin is used to control the output data timing to guarantee this operation It is therefore necessary to avoid excessive loading of the NWE pins which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol Figure 11 10 Data Hold Time ADDR NWE Data output In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access AT91M55800A m 1745D ATARM 04 Nov 05
73. software is disabling the corresponding source through IDCR this can happen due to the pipelining of the ARM Core 98 AT91M55800A memm mm r 91 55800 15 9 Protect Mode 1745D ATARM 04 Nov 05 The same mechanism of Spurious Interrupt occurs if the ARM7TDMI reads the IVR applica tion software or ICE when there is no interrupt pending This mechanism is also valid for the FIQ interrupts Once the AIC enters the Spurious Interrupt management it asserts neither the NIRQ nor the lines to the ARM7TDMI as long as the Spurious Interrupt is not acknowledged There fore it is mandatory for the Spurious Interrupt Service Routine to acknowledge the Spurious behavior by writing to the AIC_EOICR End of Interrupt before returning to the interrupted software It also can perform other operation s e g trace possible undesirable behavior The Protect Mode permits reading of the Interrupt Vector Register without performing the associated automatic operations This is necessary when working with a debug system When a Debug Monitor or an ICE reads the AIC User Interface the IVR could be read This would have the following consequences in normal mode f an enabled interrupt with a higher priority than the current one is pending it would be stacked f there is no enabled pending interrupt the spurious vector would be returned In either case an End of Interrupt Command would be necessary to acknowledge a
74. to the external inputs TCLKO TCLK1 or TCLK2 or be connected to the configurable I O signals TIOAO 1 or 2 for chaining by programming the TC BMR Block Mode Each channel can independently select an internal or external clock source for its counter Internal clock signals MCK 2 MCK 8 MCK 32 MCK 128 MCK 1024 External clock signals XC1 or XC2 The selected clock can be inverted with the CLKI bit in Channel Mode This allows counting on the opposite edges of the clock The burst function allows the clock to be validated when an external signal is high The BURST parameter in the Mode Register defines this signal none 0 XC1 XC2 Note Inall cases if an external clock is used the duration of each of its levels must be longer than the system clock MCK period The external clock frequency must be at least 2 5 times lower than the system clock Figure 19 2 Clock Selection MCK 128 MCK 1024 Selected Clock 1745D ATARM 04 Nov 05 mr rp A191 55800A 19 2 3 Clock Control The clock of each counter can be controlled in two different ways it can be enabled disabled and started stopped The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR In Waveform Mode it can be disabled by RC Compare event if CPCDI
75. used to enable PIO interrupts on the corresponding pin It has effect whether PIO is enabled or not 1 Enables an interrupt when a change of logic level is detected on the corresponding pin 0 No effect mm 1 55800 16 9 15 PIO Interrupt Disable Register Register Name PIO IDR Access Type Write only Offset 0x44 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 je 11 10 9 8 P15 P14 P13 P12 P11 P10 7 6 5 4 3 2 1 0 ps ps P P This register is used to disable PIO interrupts on the corresponding pin It has effect whether the PIO is enabled or not 1 Disables the interrupt on the corresponding pin Logic level changes are still detected 0 No effect 16 9 16 PIO Interrupt Mask Register Register Name PIO IMR Access Type Read only Offset 0x48 Reset Value 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P p Pa m Po j P P 1 7 6 5 4 3 2 1 0 m P PP P J P This register shows which pins have interrupts enabled It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR 1 Interrupt is enabled on the corresponding input pin 0 Interrupt is not enabled on the corresponding input pin AMEL 1745D ATARM 04 Nov 05 AMEL 16 9 17 PIO Interrupt Status Register Register Name PIO_ISR Access Type Read only Offset 0 4 Reset Value 0 31 30 2
76. where it left off In order to stop a peripheral it is recommended that the system software waits until the periph eral has executed its last programmed operation before disabling the clock This is to avoid data corruption or erroneous behavior of the system The peripheral clocks are automatically disabled after a reset The bits that control the peripheral clocks are the same as those that control the Interrupt Sources in the AIC 12 6 Shut down and Wake up 1745D ATARM 04 Nov 05 The APMC Advanced Power Management Controller integrates shut down and wake up logic to control an external main power supply This logic is supplied by the Battery Backup Power This feature makes the Power down mode possible If the SHDN pin is connected to the shut down pin of the main power supply the Shut down command SHDALC in APMC PCR disables the main power The shut down input of the converter is generally pulled up or down by a resistor depending on its active level There are 3 ways to exit Power down mode and restart the main power e An alarm programmed in the RTC occurs and the bit ALWKEN in is set An edge defined by the field WKEDG in APMC occurs on the WAKEUP The user opens the Shut down line with an external jumper or push button Figure 12 7 shows a typical application using the Shut down and Wake up features AMEL s AMEL Figure 12 7 Shut down and Wake up Features Power Supply V
77. within 5 C of Actual Peak Temperature 20 sec to 40 sec Peak Temperature Range 260 0 Ramp down Rate 6 C sec max Time 25 C to Peak Temperature 8 min max Note The package is certified to be backward compatible with Pb Sn soldering profile A maximum of three reflow passes is allowed per component 25 2 RoHS Package Soldering Profile Table 25 2 gives the recommended soldering profile from J STD 20C Table 25 2 Soldering Profile RoHS Compliant Package Profile Feature Convection or IR Convection Average Ramp up Rate 183 C to Peak 3 C sec max Preheat Temperature 125 C 25 C 180 sec max Temperature Maintained Above 183 C 60 sec to 150 sec Time within 5 C of Actual Peak Temperature 20 sec to 40 sec Peak Temperature Range 260 0 C Ramp down Rate 6 C sec Time 25 C to Peak Temperature 8 min max Note It is recomended to apply a soldering temperature higher than 250 C A maximum of three reflow passes is allowed per component 91 55800 m 1745D ATARM 04 Nov 05 mr sr 91 55800 26 Ordering Information Table 26 1 Ordering Information Ordering Code Package Package Type AT91M55800A 33AI LQFP 176 Sn Pb AT91M55800A 33AU LQFP 176 Green 91 55800 33 BGA 176 Sn PB AT91M55800A 33CJ BGA 176 RoHS Temperature Operating Range Industrial 40 C to 85 C 17
78. year Gregorian calendar complemented by a programmable periodic interrupt The Parallel Input Output Controllers PIOA and PIOB control the 58 I O lines They enable the user to select specific pins for on chip peripheral input output functions and general pur pose input output signal pins The PIO controllers can be programmed to detect an interrupt on a signal change from each line The Watchdog WD can be used to prevent system lock up if the software becomes trapped in a deadlock The Special Function SF module integrates the Chip ID and Reset Status registers 5 2 2 User Peripherals 1745D ATARM 04 Nov 05 Three USARTS independently configurable enable communication at a high baud rate in syn chronous or asynchronous mode The format includes start stop and parity bits and up to 8 data bits Each USART also features a Timeout and a Time Guard Register facilitating the use of the two dedicated Peripheral Data Controller PDC channels The six 16 bit Timer Counters TC are highly programmable and support capture or waveform modes Each TC channel can be programmed to measure or generate different kinds of waves and can detect and control two input output signals Each TC also has three external clock signals The SPI provides communication with external devices in master or slave mode It has four external chip selects which can be connected to up to 15 devices The data length is program mable from 8 to 16 bits
79. 0 The minute matching alarm is disabled MIN ALARM DIS 1 The minute matching alarm is enabled RTC MIN ALARM EN HOUR Hour Alarm This field is the alarm field corresponding to the BCD coded hour counter AMPM AM PM Indicator This bit is the AM PM indicator 12 Hour mode It must be written at 0 if HRMOD in HMR defines 24 Hour mode HOUREN Hour Alarm Enable HOUREN Selected HOUREN Code Label 0 The hour matching alarm is disabled RTC HOUR ALARM DIS 1 The hour matching alarm is enabled RTC HOUR ALARM EN AMEL 1745D ATARM 04 Nov 05 AMEL 13 3 6 RTC Calendar Alarm Register Register Name RTC_CAR Access Type Read Write Reset State 0x0 Offset 0x14 31 30 29 28 27 26 25 24 TE 23 22 21 20 19 18 17 16 MONTH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MONTH Month Alarm This field is the alarm field corresponding to the BCD coded month counter MTHEN Month Alarm Enable MTHEN Selected MTHEN Code Label 0 The month matching alarm is disabled RTC MONTH ALARM DIS 1 The month matching alarm is enabled MONTH ALARM EN DATE Date Alarm This field is the alarm field corresponding to the BCD coded date counter DATEN Date Alarm Enable DATEN Selected DATEN Code Label 0 The date matching alarm is disabled RTC DATE ALARM DIS 1 The date matching alarm is enabled DATE ALARM EN
80. 0 to 11 set FFF and bits 12 to 15 equaling HPCV e CKEY Clock Access Key Code Label WD CKEY Used only when writing WD CKEY is read as 0 0 06 Write access in WD is allowed Other value Write access in WD is prohibited 1745D ATARM 04 Nov 05 mm 191 155800 14 0 4 WD Control Register Name WD Access Write only Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RSTKEY 7 6 4 3 2 1 0 5 RSTKEY RSTKEY Restart Key Code Label WD_RSTKEY 0xC071 Watch Dog counter is restarted Other value No effect ATMEL s 1745D ATARM 04 Nov 05 AMEL 14 0 5 WD Status Register Name WD_SR Access Read only Reset Value 0x0 Offset OxOC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WDOVF Watchdog Overflow Code Label WD WDOVF 0 No watchdog overflow 1 A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset 14 0 6 WD Enabling Sequence To enable the Watchdog Timer the sequence is as follows 1 Disable the Watchdog by clearing the bit WDEN Write 0 2340 to WD OMR This step is unnecessary if the WD is already disabled reset state 2 Initialize the WD Clock Mode Register 3 Write Ox373C to WD CMR 15 WDCLKS MCK 8 4 Restart the timer Write 71 to WD CR 5 Enable the watchdog Write 0x2345 to WD OMR in
81. 0100 0000 AT91x40yyy SF_ARCH_AT91x40 0101 0101 AT91x55yyy SF_ARCH_AT91x55 NVPTYP Nonvolatile Program Memory Type NVPTYP Type Code Label SF_NVPTYP 0 0 1 M Series or F Series SF NVPTYP M 1 0 0 R Series SF NVPTYP R Note All other codes are reserved EXT Extension Flag Code Label sF EXT 0 Chip ID has a single register definition without extensions 1 An extended Chip ID exists to be defined in the future 17 2 2 Chip ID Extension Register Register Name SF EXID Access Type Read only Offset 0x04 This register is reserved for future use It will be defined when needed 130 AT91M55800A memme mmn n 91 55800 17 2 3 Reset Status Register Register Name Access Type Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SF_RSR Read only 0x08 15 14 13 12 11 10 9 8 N E o RESET RESET Reset Status Information This field indicates whether the reset was demanded by the external system via NRST or by the Watchdog internal reset request Reset Cause of Reset Code Label Ox6C External Pin SF EXT RESET 0x53 Internal Watchdog SF WD RESET 17 2 4 SF Protect Mode Register Register Name SF PMR Access Type Read Write Reset Value 0 0 Offset 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p n e Tq c qp se jJ i PMRKEY Protect Mode Register Key Use
82. 1 Controller 16K Bytes 0 000 OxFFFD7FFF Timer Counter Channels 3 4 5 16K Bytes OxFFFD4000 OxFFFD3FFF Timer Counter Channels 0 1 2 16K Bytes OxFFFD0000 OxFFFCBFFF Universal Synchronous USART2 Asynchronous 16K Bytes OxFFFC8000 Receiver Transmitter 2 OxFFFC7FFF Universal Synchronous USART1 Asynchronous 16K Bytes OxFFFC4000 Receiver Transmitter 1 OxFFFCSFFF Universal Synchronous USARTO Asynchronous 16K Bytes 0000 Receiver Transmitter 0 OxFFFBFFFF Serial Peripheral Interface 16K Bytes OxFFFBCOO00 OxFFFBBFFF Real time Clock 16K Bytes OxFFFB8000 OxFFFB7FFF Analog to digital Converter 1 16K Bytes OxFFFB4000 OxFFFB3FFF Analog to digital Converter 0 16K Bytes OxFFFBOO00 OxFFFAFFFF Digital to analog Converter 1 16K Bytes OxFFFACOO0 OxFFFABFFF Digital to analog Converter 0 16K Bytes OxFFFA8000 OxFFFO3FFF SF Special Function 16K Bytes OxFFF00000 OxFFEOSFFF External Bus Interface 16K Bytes 0 00000 0 00000 AIMEL 1745D ATARM 04 Nov 05 AMEL 11 EBI External Bus Interface The EBI generates the signals that control the access to the external memory or peripheral devices The EBI is fully programmable and can address up to 128M bytes It has eight chip selects and a 24 bit address bus The 16 bit data bus can be configured to interface with 8 or 16 bit external devices Separate read and write control signals allow for direct memory and peripheral interfacing The EBI
83. 11 64 PB26 TIOA2 108 PLLRC 152 PB11 21 A12 65 PB27 TIOB2 109 VDDBU 153 PB12 22 13 66 PAO TCLK3 110 XIN320 154 PB13 23 A14 67 PA1 TIOA3 111 xoura20 155 PB14 24 A15 68 PA2 TIOB3 112 NRSTBU 156 PB15 25 A16 69 PA3 TCLK4 113 GNDBU 157 PB16 26 17 70 PA4 TIOA4 114 WAKEUP 158 17 27 18 71 PA5 TIOB4 115 SHDN 159 NWDOVF 28 19 72 PAG TCLK5 116 GNDBU 160 MCKO 29 VDDIO 73 VDDIO 117 VDDA 161 VDDIO 30 GND 74 GND 118 ADO 162 GND 31 A20 75 7 5 119 10 163 18 5 32 21 76 PA8 TIOB5 120 AD2 164 JTAGSEL 33 A22 77 PA9 IRQO 121 AD3 165 TMS 34 A23 78 PA10 IRQ1 122 AD4 166 TDI 35 DO 79 PA11 IRQ2 123 AD5 167 TDO 36 D1 80 PA12 IRQ3 124 ADe 168 TCK 37 D2 81 PA13 FIQ 125 AD7 169 NTRST 38 D3 82 PA14 SCKO 126 ADVREF 170 NRST 39 D4 83 PA15 TXDO 127 DAVREF 171 NWAIT 40 D5 84 PA16 RXDO 128 172 NOE NRD 41 D6 85 PA17 SCK1 129 DAI 173 NWE NWRO 42 D7 86 PA18 TXD1 NTRI 130 GNDA 174 NUB NWR1 43 VDDCORE 87 VDDCORE 131 VDDCORE 175 VDDCORE 44 VDDIO 88 VDDIO 132 VDDIO 176 VDDIO Notes 1 Analog pins 2 Battery backup pins AMEL 1745D ATARM 04 Nov 05 AMEL Table 2 2 Pin Configuration for 176 ball BGA Package
84. 12 HRMOD 78 91 55800 memm 1745D ATARM 04 Nov 05 T 9 1VI55800 A 13 3 3 RTC Time Register Register Name RTC_TIMR Access Type Read Write Reset State 0x0 Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 J a i C HR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s SEC SEC Current Second Code Label RTC SEC The range that be set is 0 59 BCD The lowest four bits encode the units The higher bits encode the tens MIN Current Minute Code Label RTC MIN The range that can be set is 0 59 BCD The lowest four bits encode the units The higher bits encode the tens HOUR Current Hour Code Label RTC HOUR The range that can be set is 1 12 BCD in 12 hour mode or 0 23 BCD in 24 hour mode AMPM Ante Meridiem Post Meridiem Indicator Code Label RTC AMPM This bit is the AM PM indicator in 12 hour mode It must be written at 0 if HRMOD defines 24 Hour mode 0 AM 12 PM ATMEL 1745D ATARM 04 Nov 05 AMEL 13 3 4 RTC Calendar Register Register Name RTC_CALR Access Type Read Write Reset State 0x01819819 Offset 0x0C 31 30 29 28 27 26 25 24 PE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 2 CENT Current Century Code Label RTC CENT The range that can be set is 19 20 BCD The lowest four bits encode the units The higher bits encode the tens YEAR
85. 16 15 14 13 12 11 10 9 8 AR USCLKS Selected Clock Code Label US CLKS 0 0 MCK US CLKS MCK 0 1 MCK 8 US CLKS MCK8 1 X External SCK US CLKS SCK CHRL Character Length CHRL Character Length Code Label US CHRL 0 0 Five bits US CHRL 5 0 1 Six bits US CHRL 6 1 0 Seven bits US CHRL 7 1 1 Eight bits US CHRL 8 Start stop and parity bits are added to the character length e SYNC Synchronous Mode Select Code Label 05 SYNC 0 USART operates in Asynchronous Mode 1 USART operates Synchronous Mode PAR Parity Type PAR Parity Type Code Label US PAR 0 0 0 Even Parity US PAR EVEN 0 0 1 Odd Parity US PAR ODD 0 1 0 Parity forced to 0 Space US PAR SPACE 0 1 1 Parity forced to 1 Mark US PAR MARK 1 0 x No parity US_PAR_NO 1 1 x Multi drop mode US PAR MULTIDROP A MEL 145 1745D ATARM 04 Nov 05 AMEL NBSTOP Number of Stop Bits The interpretation of the number of stop bits depends on SYNC NBSTOP Asynchronous SYNC 0 Synchronous SYNC 1 Code Label 75 NBSTOP 0 0 1 stop bit 1 stop bit US NBSTOP 1 0 1 1 5 stop bits Reserved US NBSTOP 1 5 1 0 2 stop bits 2 stop bits US NBSTOP 2 1 1 Reserved Reserved CHMODE Channel Mode CHMODE Mode Description Code Label 05 CHMODE Normal Mode 0 0 The USART Channel operates as Rx Tx USART SRNODE NORMAL 0 1
86. 1759 Biometrics Imaging Hi Rel MPU High Speed Converters RF Datacom Avenue de Rochepleine BP 123 38521 Saint Egreve Cedex France Tel 33 4 76 58 30 00 Fax 33 4 76 58 34 80 Tel 1 719 576 3300 9F Tonetsu Shinkawa Bldg Fax 1 719 540 1759 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Scottish Enterprise Technology Park Tel 81 3 3523 3551 Maxwell Building Fax 81 323 3523 7581 East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING ITS PRODUCTS INCLUDING BUT NOT LIMITED THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSS
87. 222 PB9 IN OUT INPUT 221 CTRL 220 OUTPUT 219 PB8 IN OUT INPUT 218 CTRL 217 OUTPUT 216 PB7 AD1TRIG IN OUT INPUT 215 CTRL 214 OUTPUT 213 PB6 ADOTRIG IN OUT INPUT 212 CTRL 211 OUTPUT 210 PB5 IN OUT INPUT 209 CTRL 208 OUTPUT 207 PB4 IRQ5 IN OUT INPUT 206 CTRL 205 OUTPUT 204 PB3 IN OUT INPUT 203 CTRL 202 OUTPUT 201 PB2 IN OUT INPUT 200 CTRL 28 AT91M55800A memme 1 55800 Table 23 1 JTAG Boundary scan Register Continued Bit Associated BSR Number Pin Name Pin Type Cells 199 OUTPUT 198 PB1 IN OUT INPUT 197 CTRL 196 OUTPUT 195 PBO IN OUT INPUT 194 CTRL 193 NCS7 OUTPUT OUTPUT 192 NCS6 OUTPUT OUTPUT 191 NCS5 OUTPUT OUTPUT 190 NCS4 OUTPUT OUTPUT 189 OUTPUT 188 PA29NPCS3 IN OUT INPUT 187 CTRL 186 OUTPUT 185 PA28NPCS2 IN OUT INPUT 184 CTRL 183 OUTPUT 182 PA27NPCS1 IN OUT INPUT 181 CTRL 180 OUTPUT 179 PA26NPCSO IN OUT INPUT 178 CTRL 177 OUTPUT 176 PA25MOSI IN OUT INPUT 175 CTRL 174 OUTPUT 173 PA24MISO IN OUT INPUT 172 CTRL 171 OUTPUT 170 PA23SPCK IN OUT INPUT 169 CTRL 168 OUTPUT 167 PA22RXD2 IN OUT INPUT 166 CTRL 165 PA21TXD2 IN OUT OUTPUT A MEL 229 1745D ATARM 04 Nov 05 AMEL Table 23 1 JTAG Boundary scan Register Continued
88. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L m dq o Ji ee DATRDY Data Ready for Conversion Interrupt Enable Code Label DATRDY 0 No effect 1 Enables the Data Ready for Conversion Interrupt 22 2 7 DAC Interrupt Disable Register Register Name DAC_IDR Access Type Write only Offset 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L p 1 L nmay DATRDY Data Ready for Conversion Interrupt Disable Code Label DAC DATRDY 0 No effect 1 Disables the Data Ready for Conversion Interrupt AMEL 2 1745D ATARM 04 Nov 05 AMEL 22 2 8 DAC Interrupt Mask Register Register Name DAC_IMR Access Type Read only Reset State 0 Offset Ox1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ox qo C dom m p a 1 DATRDY Data Ready for Conversion Interrupt Mask Code Label DAC DATRDY 0 Data Ready for Conversion Interrupt is disabled 1 Data Ready for Conversion Interrupt is enabled 222 AT91M55800A cm 1 55800 23 JTAG Boundary scan Register The Boundary scan Register BSR contains 256 bits which correspond to active pins and associated control signals Each AT91M55800A input pin has a corresponding bit in the Boundary scan Register for observability Each AT91M55800A output pin has a corresponding 2 bit re
89. 30 29 28 27 26 25 24 COMMRX Im IRQS 23 22 21 20 19 18 17 16 RTCIRQ DAC1IRQ DACOIRQ ADC1IRQ 15 14 13 12 11 10 9 8 ADCOIRQ PIOBIRQ PIOAIRQ WDIRQ 5 TC4IRQ TC3IRQ TC2IRQ 7 6 5 4 3 2 1 0 TC1IRQ TCOIRQ SPIRQ US2IRQ US1IRQ USOIRQ SWIRQ Interrupt Enable 0 No effect 1 Enables corresponding interrupt 16 AT91M55800A mmm mn 91 55800 15 10 10 AIC Interrupt Disable Command Register Register Name AIC IDCR Access Type Write only Offset 0x124 81 30 29 28 27 26 25 24 COMMRX ma IRQS 23 22 21 20 19 18 17 16 APMCIRQ RTCIRQ DAC1IRQ DACOIRQ ADC1IRQ 15 14 13 12 11 10 9 8 ADCOIRQ PIOBIRQ PIOAIRQ WDIRQ 5 TC4IRQ TC3IRQ TC2IRQ 7 6 5 4 3 2 1 0 TC1IRQ TCOIRQ SPIRQ US2IRQ US1IRQ USOIRQ SWIRQ Interrupt Disable 0 No effect 1 Disables corresponding interrupt 15 10 11 AIC Interrupt Clear Command Register Register Name AIC ICCR Access Type Write only Offset 0x128 31 30 29 28 27 26 25 24 COMMRX Io IRQS 23 22 21 20 19 18 17 16 RTCIRQ DAC1IRQ DACOIRQ ADC1IRQ 15 14 13 12 11 10 9 8 ADCOIRQ PIOBIRQ PIOAIRQ WDIRQ TC5IRQ TC4IRQ TC3IRQ TC2IRQ 7 6 5 4 3 2 1 0 TC1IRQ TCOIRQ SPIRQ US2IRQ US1IRQ USOIRQ SWIRQ e Interrupt Clear 0 No effect 1 Clears corresponding interrupt
90. 4 Timing Alarm Error Checking The RTC provides a full Binary Coded Decimal BCD clock which includes century 19 20 year with leap years month date day hours minutes and seconds The valid year range is 1900 to 2099 a two hundred year Gregorian calendar achieving full Y2K compliance The RTC can operate in 24 hour mode or in 12 hour mode with an AM PM indicator Corrections for leap years are included all years divisible by 4 being leap years including year 2000 This is correct up to the year 2099 The RTC is updated in real time at one second intervals in normal mode for the counters of seconds at 1 minute intervals for the counter of minutes and so on Due to the asynchronous operation of the RTC with respect to the rest of the chip to be cer tain that the value read in the RTC registers century year month date day hours minutes seconds are valid and stable it is necessary to read these registers twice If the data is the same both times then it is valid Therefore a minimum of two and a maximum of three accesses is required The RTC has five programmable fields with which to program an alarm MONTH and DATE in the Calendar Alarm Register RTC CAR and SEC MIN and HOUR in the Time Alarm Regis ter Each of these fields be enabled or disabled using the bits MTHEN DATEN SECEN MINEN HOUREN to match the alarm condition f all the fields are enabled an alarm flag is genera
91. 4 Core Interrupt Status Register AIC CISR Read only 0 0x118 Reserved 0x11C Reserved _ 0x120 Interrupt Enable Command Register AIC_IECR Write only 0x124 Interrupt Disable Command Register AIC_IDCR Write only 0x128 Interrupt Clear Command Register ICCR Write only E 0x12C Interrupt Set Command Register AIC_ISCR Write only 0x130 End of Interrupt Command Register AIC_EOICR Write only 0x134 Spurious Vector Register 5 Read Write 0 Note 1 The reset value of this register depends on the level of the External IRQ lines All other sources are cleared at reset A MEL 101 1745D ATARM 04 Nov 05 AMEL 15 10 1 Source Mode Register Register Name AIC SMRO AIC SMR31 Access Type Read Write Reset Value 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sowe J PRO PRIOR Priority Level Code Label PRIOR Program the priority level for all sources except source 0 FIQ The priority level be between 0 lowest and 7 highest The priority level is not used for the FIQ in the SMRO SRCTYPE Interrupt Source Type Code Label SRCTYPE Program the input to be positive or negative edge triggered or positive or negative level sensitive The active level or edge is not programmable for the internal sources Internal External SRCTYPE Sources Code Label Internal Sources Code Label External o
92. 4 Pad Output E Pad Input Peripheral 1 Output Output Peripheral Input OFF Value PIO PDSR 1 Event Detection I 1 Note 1 See Section 16 8 PIO Connection Tables n A 1 55800 16 8 PIO Connection Tables Table 16 1 Controller A Connection Table PIO Controller Peripheral Bit Port Signal OFF Pin Number Name Port Name Signal Description Direction Value Reset State Number 0 PAO TCLK3 Timer 3 Clock signal Input 0 PIO Input 66 1 PA1 TIOA3 Timer 3 Signal A Bi directional 0 PIO Input 67 2 PA2 TIOB3 Timer 3 Signal B Bi directional 0 PIO Input 68 3 PA3 TCLK4 Timer 4 Clock signal Input 0 PIO Input 69 4 PA4 TIOA4 Timer 4 Signal A Bi directional 0 PIO Input 70 5 5 4 Timer 4 Signal B Bi directional 0 PIO Input 71 6 PA6 TCLK5 Timer 5 Clock signal Input 0 PIO Input 72 7 PA7 5 Timer 5 Signal A Bi directional 0 PIO Input 75 8 5 Timer 5 Signal B Bi directional 0 PIO Input 76 9 PA9 IRQO External Interrupt 0 Input 0 PIO Input 77 10 10 IRQ1 Exter
93. 45D ATARM 04 Nov 05 ATMEL 239 AMEL 27 Errata The following known errata are applcable to The following datasheets AT91M55800A Summary 1745S AT91M55800A This document AT91M55800A Electrical Characteristics Rev 1727 e 176 lead LQFP and 176 ball BGA devices with the following markings AT91M55800A 33Al AT91M55800A 33AU AT91M55800A 33CI AT91M55800A 33CJ Internal Product Reference 56515B 27 1 ADC Characteristics and Behavior The tracking time has a theoretical minimum duration It equals one ADC Clock period and is normally ensured by the ADC Controller It might randomly happen that this minimum duration cannot be guaranteed on the first enabled channel When this happens the sampling and hold process is too short and the conversion result is wrong Problem Fix Work Around To use only one channel the user has to enable two channels and then must use the sec ond channel only In the event that all of the ADC channels need to be used only three channels will be available A software workaround allows all the channels to be used It consists of performing several conversions and averaging the samples on the first enabled channel This method does not support fast conversion However signals from temperature sensors which are slow signals can be handled by averaging a number of samples 27 2 Warning Additional NWAIT Constraints When the NWAIT signal is asserted during an external memory access
94. 58 INPUT D8 IN OUT 57 OUTPUT 56 D 15 8 IN OUT CTRL 55 INPUT D7 IN OUT 54 OUTPUT 53 INPUT D6 IN OUT 52 OUTPUT 51 INPUT D5 IN OUT 50 OUTPUT 49 INPUT D4 IN OUT 48 OUTPUT 47 INPUT D3 IN OUT 46 OUTPUT 45 INPUT D2 IN OUT 44 OUTPUT 43 INPUT D1 IN OUT 42 OUTPUT 41 IN OUT INPUT DO 40 OUTPUT 39 D 7 0 IN OUT CTRL 38 A23 OUTPUT OUTPUT 37 A22 OUTPUT OUTPUT 36 A21 OUTPUT OUTPUT 35 A20 OUTPUT OUTPUT 34 A19 OUTPUT OUTPUT 33 A18 OUTPUT OUTPUT 32 A17 OUTPUT OUTPUT 31 A16 OUTPUT OUTPUT 30 A 23 16 OUTPUT CTRL 29 A15 OUTPUT OUTPUT 28 A14 OUTPUT OUTPUT 27 A13 OUTPUT OUTPUT 26 A12 OUTPUT OUTPUT AMEL 233 AMEL Table 23 1 JTAG Boundary scan Register Continued Bit Associated BSR Number Pin Name Pin Type Cells 25 A11 OUTPUT OUTPUT 24 A10 OUTPUT OUTPUT 23 A9 OUTPUT OUTPUT 22 A8 OUTPUT OUTPUT 21 A 15 8 OUTPUT CTRL 20 A7 OUTPUT OUTPUT 19 A6 OUTPUT OUTPUT 18 A5 OUTPUT OUTPUT 17 A4 OUTPUT OUTPUT 16 A3 OUTPUT OUTPUT 15 A2 OUTPUT OUTPUT 14 A1 OUTPUT OUTPUT 13 NLB AO OUTPUT OUTPUT 12 A 7 0 OUTPUT CTRL 11 NCS3 OUTPUT OUTPUT 10 NCS2 OUTPUT OUTPUT 9 NCS1 OUTPUT OUTPUT 8 NCSO OUTPUT OUTPUT 7 OUTPUT NUB NWR1 IN OUT 6 INPUT 5 OUTPUT NUB NWRO IN OUT 4 INPUT 3 OUTPUT NOE NRD IN OUT 2 INPUT NCS 7 0 NUB NWR1 1 IN OUT TRL NWE NWRO di NOE NRD 1745D ATARM 04 Nov 05 AT91
95. 59 12 7 a 60 12 8 FirstStart up Sequence 61 12 9 APMC User Interface 1111 0000 62 13 RTC Real time COCK 73 13 1 Year 2000 Conformity tete Beanies 73 132 Functional Description 74 133 esi ree 76 14 WD Watchdog 89 15 AIC Advanced Interrupt Controller 95 151 Hardware Interrupt Vectoring 2 een 97 15 2 Priority Controller i certi t ERA RE ER KORR 97 15 3 Interrupt Handling 97 154 nene meat m Ee t 98 15 5 Interrupt Clearing and Setting 22222 4 0 0 0 0 98 15 6 Fast Interrupt Request ull ll luu l l 98 15 7 Software Interrupt eet receta ice aiid 98 158 Spurious Interr pt tret 98 15 9 Protect Moda n 99 15 10 User Interface ect IEEE SER 101 15 11 Standard Interrupt Sequence 110 16 PIO Parallel I O Controller 112 16 1 Multiplexed O Lines eir tre RE ee beth x e ERE staves 112 i AT91M55800A mus NN 1745D ATARM 04 Nov 05 mnm n T 9 1 VI55800 A 16 2 Output Selection 112 1
96. 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aa ALARM ACKUPD ACKUPD Acknowledge Update Interrupt Mask Code Label RTC ACKUPD 0 2 The acknowledge for update interrupt is disabled 1 2 The acknowledge for update interrupt is enabled ALARM Alarm Interrupt Mask Code Label RTC ALARM 0 The alarm interrupt is disabled 1 The alarm interrupt is enabled SEC Second Event Interrupt Mask Code Label RTC SEC 0 The second periodic interrupt is disabled 1 The second periodic interrupt is enabled TIMEV Time Event Interrupt Mask Code Label RTC TIMEV 0 The selected time event interrupt is disabled 1 The selected time event interrupt is enabled CALEV Calendar Event Interrupt Mask Code Label RTC CALEV 0 The selected calendar event interrupt is disabled 1 The selected calendar event interrupt is enabled ATMEL 1745D ATARM 04 Nov 05 AMEL 13 3 12 RTC Valid Entry Register Register Name RTC VER Access Type Read only Reset State 0 0 Offset 0 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NVT Non Valid Time Code Label RTC NVT 0 No invalid data has been detected in RTC_TIMR 1 has contained invalid data since it was last programmed NVC Non Valid Calendar Code Label RTC NVC 0 No invalid data has been detected in RTC_CALR 1 RTC_CALR has contained invalid data since it was last programmed NVTAL Non
97. 6 3 1 112 16 4 oie 112 16 5 E 113 166 e eee rete 113 16 7 Multi driver Open Drain 113 16 8 Connection Tables 0 22222 0 nnne Eas nnns 115 16 9 User Interface 117 17 SF Special Function Registers 128 17 1 CHIP IdentifiGr I 128 17 2 User Interface 128 18 USART Universal Synchronous Asynchronous Receiver Transmitter 132 181 uu Beast 133 182 Baud Rate Generator 134 18 9 eoe eoe o de P ten ce 135 LE RN CIIM 137 18 5 u ke tl et ree ena ead 137 18 6 YI 138 18 7 Peripheral Data Controller 140 18 8 Interrupt Generation 140 18 9 Channel Modes eorr reti teer tr de eee dot ha et 140 18 10 USART User Interface 142 18 TC Timer Counter 157 19 1 Signal Name Description
98. 9 28 27 26 25 24 23 22 21 20 19 18 17 16 P22 21 15 14 13 12 11 10 9 8 Pis P Pts Pt Pn Po P P 7 6 5 4 3 2 1 0 ug Pa P P P J P This register indicates for each pin when a logic value change has been detected rising or falling edge This is valid whether the PIO is selected for the pin or not and whether the pin is an input or an output The register is reset to zero following a read and at reset 1 At least one input change has been detected on the corresponding pin since the register was last read 0 No input change has been detected on the corresponding pin since the register was last read 16 9 18 PIO Multi driver Enable Register Register Name PIO_MDER Access Type Write only Offset 0x50 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 ms 4 pa P Pio P P 7 6 5 4 3 2 1 0 P P This register is used to enable output drivers to be configured as open drain to support external drivers on the same pin 1 Enables multi drive option on the corresponding pin 0 No effect 126 AT91M55800A mmm 1 55800 16 9 19 Multi driver Disable Register Register Name PIO MDDR Access Type Write only Offset 0x54 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 11 10 7 6 5 4 3 2 1 0 P5
99. A and GNDA and the input reference DAVREF ATMEL n 1745D ATARM 04 Nov 05 AMEL 9 Memory Map Figure 9 1 91 55800 Memory Map Before and after Remap Command Before Remap After Remap Address Function Size Abort Control Address Function Size Abort Control OxFFFFFFFF OxFFFFFFFF On chip On chip Peripherals 4M Bytes No Peripherals 4M Bytes No 0 00000 0 00000 OxFFBFFFFF OxFFBFFFFF External Up to 8 Devices Reserved Devices Programmable Page Size yes up to 8 1 4 16 64M Bytes 0x00400000 0x00400000 0x003FFFFF 0x003FFFFF On chip RAM 1M Byte No Reserved 1M Byte No 0x00300000 0x00300000 0x002FFFFF 0x002FFFFF Reserved Reserved On chip 1M Byte No On chip 1M Byte No Device Device 0x00200000 0x00200000 0x001FFFFF 0x001FFFFF Reserved Reserved 1 Onan 1M Byte No Device Device 0x00100000 0x00100000 0x000FFFFF 0x000FFFFF External Devices 1 On chip RAM 1M Byte No by NCSO 0x00000000 0x00000000 22 AT91M55800A 1745D ATARM 04 Nov 05 91 55800 10 Peripheral Memory Figure 1 AT91M55800A Peripheral Memory Address Peripheral Peripheral Name Size OxFFFFFFFF Advanced Interrupt Controller Bytes OxFFFFFO0O OxFFFFBFFF WD WatchdogTimer 16K Bytes OxFFFF8000 OxFFFF7FFF Advanced Power 16K Bytes Management Controller OxFFFF4000 OxFFFF3FFF Parallel 1 Controller 16K Bytes 0 0000 OxFFFEFFFF Parallel
100. ADC_IDR Write only 0 2 Interrupt Mask Register ADC IMR Read only 0 0x30 Convert Data Register 0 ADC CDRO Read only 0 0x34 Convert Data Register 1 ADC CDR1 Read only 0 0x38 Convert Data Register 2 ADC CDR2 Read only 0 Ox3C Convert Data Register 3 ADC CDR3 Read only 0 AT91M55800A m 1745D ATARM 04 Nov 05 m s m rr 1 55800 21 0 6 ADC Control Register Register Name ADC_CR Access Type Write only Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SWRST Software Reset Code Label SWRST 0 No effect 1 Resets the ADC simulating a hardware reset START Start Conversion Code Label ADC START 0 No effect 1 Begins analog to digital conversion and clears all EOC bits A MEL 211 1745D ATARM 04 Nov 05 AMEL 21 0 7 ADC Mode Register Register Name Access Type Reset State Offset ADC_MR Read Write 0 0x04 15 aa eee PRESCAL 7 6 5 4 3 2 1 0 ste RS TnRGSL TRGEN Trigger Enable TRGEN Selected TRGEN Code Label Hardware triggers are disabled Starting a conversion is only possible by x software ADC TRGEN DIS 1 Hardware trigger selected by TRGSEL field is enabled ADC TRGEN EN TRGSEL Trigger Selection This field selects the hardware trigger TTRGSEL Selected TRGSEL Code Label ADC B TTRGSEL 0 0 0 TIO
101. AO ADC TRG TIOAO 0 0 1 TIOA1 ADC TRG TIOA1 0 1 0 TIOA2 ADC TRG TIOA2 0 1 1 TRG 1 0 0 4 ADC TRG TIOA4 1 0 1 TIOA5 ADC TRG 5 1 1 0 External trigger ADC TRG EXT 1 1 1 Reserved RES Resolution RES Selected RES Code Label 0 10 bit resolution ADC 10 BIT RES 1 8 bit resolution ADC 8 BIT RES 212 AT91M55800A memm 1745D ATARM 04 Nov 05 mmn A191 55800A SLEEP Sleep Mode SLEEP Selected SLEEP Code Label 0 Normal Mode NORMAL MODE 1 Sleep Mode ADC SLEEP MODE PRESCAL Prescaler Rate Selection PRESCAL This field defines the conversion clock in function of the Master Clock MCK ADCClock MCK PRESCAL 1 x 2 The ADC clock range is between MCK 2 PRESCAL 0 128 PRESCAL 63 PRESCAL must be pro grammed in order to provide an ADC clock frequency according to the parameters given in the AT91M55800A Electrical Datasheet literature number 1727 A MEL 213 1745D ATARM 04 Nov 05 AMEL 21 0 8 ADC Channel Enable Register Register Name ADC_CHER Access Type Write only Offset 0x10 31 30 24 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH Channel Enable Code Label ADC CHx 0 No effect 1 Enables the corresponding channel 21 0 9 ADC Channel Disable Register Register Name ADC_CHDR Access Type Write o
102. AT91 ADC Sleep Mode maximizes power saving by deactivating the ADC when it is not being used for conversions Sleep Mode is selected by setting the bit SLEEP in the Mode Reg ister ADC MR When a start conversion request occurs the ADC is automatically activated As the analog cell requires a start up time the logic waits during this time and starts the conversion sequence on 91 55800 memme 1745D ATARM 04 Nov 05 Xw 1 55800 the enabled channel When all conversions are complete the ADC is deactivated until the next trigger This permits an automatic conversion sequence with minimum CPU intervention and opti mized power consumption A MEL 209 1745D ATARM 04 Nov 05 AMEL 21 0 5 ADC User Interface Base Address 0 0xFFFB0000 Code Label BASE Base Address 1 0xFFFB4000 Code Label ADC1 BASE Table 21 2 ADC Memory Offset Register Name Access Reset State 0x00 Control Register ADC CR Write only 0 04 Mode Register ADC MR Read Write 0 0x08 Reserved 0x0C Reserved 0x10 Channel Enable Register ADC_CHER Write only 0x14 Channel Disable Register ADC_CHDR Write only 0x18 Channel Status Register ADC CHSR Read only 0 0x1C Reserved 0 20 Status Register SR Read only 0 0x24 Interrupt Enable Register ADC_IER Write only 0x28 Interrupt Disable Register
103. AT91M55800A memm mms 1 155800 Most importantly the PDC removes the processor interrupt handling overhead and signifi cantly reduces the number of clock cycles required for a data transfer It can transfer up to 64K contiguous bytes As a result the performance of the microcontroller is increased and the power consumption reduced 8 4 System Peripherals 8 4 1 APMC Advanced Power Management Controller The AT91M55800A Advanced Power Management Controller allows optimization of power consumption The APMC enables disables the clock inputs of most of the peripherals and the ARM Core Moreover the main oscillator the PLL and the analog peripherals can be put in standby mode allowing minimum power consumption to be obtained The APMC provides the following operating modes Normal clock generator provides clock to the entire chip except the RTC Wait mode ARM Core clock deactivated Slow Clock mode clock generator deactivated master clock 32 kHz Standby mode RTC active all other clocks disabled Power down RTC active supply on the rest of the circuit deactivated 8 4 2 RTC Real time Clock The AT91M55800A features a Real time Clock RTC peripheral that is designed for very low power consumption It combines a complete time of day clock with alarm and a two hundred year Gregorian calendar complemented by a programmable periodic interrupt The time and calendar values are coded in Binary Coded Decimal BCD format
104. ATARM 04 Nov 05 AMEL 173 AMEL 19 5 5 TC Channel Mode Register Waveform Mode Register Name TC_CMR Access Type Read Write Reset State 0 Offset 0 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCCLKS Clock Selection TCCLKS Clock Selected Code Label TC CLKS 0 0 0 MCK 2 TC CLKS MCK2 0 0 1 MCK 8 TC CLKS MCK8 0 1 0 MCK 32 TC CLKS MCK32 0 1 1 MCK 128 TC CLKS MCK128 1 0 0 MCK 1024 TC CLKS MCK1024 1 0 1 XC0 TC_CLKS_XC0 1 1 0 XC1 TC_CLKS_XC1 1 1 1 2 TC CLKS XC2 CLKI Clock Invert Code Label TC CLKI 0 Counter is incremented on rising edge of the clock 1 Counter is incremented on falling edge of the clock BURST Burst Signal Selection BURST Selected BURST Code Label TC BURST 0 0 The clock is not gated by an external signal TC BURST NONE 0 1 XCO is ANDed with the selected clock TC BURST XCO 1 0 XC1 is ANDed with the selected clock TC BURST XC1 1 1 XC2 is ANDed with the selected clock TC BURST XC2 CPCSTOP Counter Clock Stopped with RC Compare Code Label TC CPCSTOP 0 Counter clock is not stopped when counter reaches RC 1 Counter clock is stopped when counter reaches RC CPCDIS Counter Clock Disable with RC Compare Code Label TC CPCDIS 0 Counter clock is not disabled when counter reaches RC 1 Counter clock is disabled when counter reaches RC 1745D
105. Advanced Interrupt Controller US IMR Interrupt Mask Register indicates the status of the corresponding bits When bit is set in US and the same bit is set in US the interrupt line is asserted The USART can be programmed to operate in three different test modes using the field CHMODE in 06 MR Automatic echo mode allows bit by bit re transmission When a bit is received on the RXD line itis sent to the TXD line Programming the transmitter has no effect Local loopback mode allows the transmitted characters to be received TXD and RXD pins are not used and the output of the transmitter is internally connected to the input of the receiver The RXD pin level has no effect and the TXD pin is held high as in idle state Remote loopback mode directly connects the RXD pin to the TXD pin The Transmitter and the Receiver are disabled and have no effect This mode allows bit by bit re transmission AT91M55800A m V 1745D ATARM 04 Nov 05 1745D ATARM 04 Nov 05 Figure 18 7 Channel Modes Automatic Echo TXD RXD Remote Loopback Vpp Disabled Receiver 7 RXD Disabled Transmitter TXD ATMEL AT91M55800A 141 AMEL 18 10 USART User Interface Base Address USARTO Code Label USARTO BASE Base Address USART1 OxFFFC4000 Code Label USART1 BASE Base Address USART2 OxFFFC8000 Code Label USART2 BASE Table 18 2 USART Memory
106. CTRL 108 OUTPUT 107 PA2 TIOB3 IN OUT INPUT 106 CTRL 105 OUTPUT 104 PA1 TIOA3 IN OUT INPUT 103 CTRL 102 OUTPUT 101 IN OUT INPUT 100 CTRL 99 OUTPUT 98 PB27 TIOB2 IN OUT INPUT 97 CTRL 96 PB26 TIOA2 IN OUT OUTPUT A MEL 231 1745D ATARM 04 Nov 05 AMEL Table 23 1 JTAG Boundary scan Register Continued Bit Associated BSR Number Pin Name Pin Type Cells 95 INPUT 94 CTRL 93 OUTPUT 92 PB25 TCLK2 IN OUT INPUT 91 CTRL 90 OUTPUT 89 24 1 IN OUT INPUT 88 CTRL 87 OUTPUT 86 PB23 TIOA1 IN OUT INPUT 85 CTRL 84 OUTPUT 83 PB22 TCLK1 IN OUT INPUT 82 CTRL 81 OUTPUT 80 PB21TIOBO IN OUT INPUT 79 CTRL 78 OUTPUT 77 PB20 TIOAO IN OUT INPUT 76 CTRL 75 OUTPUT 74 PB19 TCLKO IN OUT INPUT 73 CTRL 72 INPUT D15 IN OUT 71 OUTPUT 70 INPUT D14 IN OUT 69 OUTPUT 68 INPUT D13 IN OUT 67 OUTPUT 66 INPUT D12 IN OUT 65 OUTPUT 64 INPUT D11 IN OUT 63 OUTPUT 62 INPUT D10 IN OUT 61 OUTPUT 1745D ATARM 04 Nov 05 1 55800 Table 23 1 JTAG Boundary scan Register Continued Bit Associated BSR Number Pin Name Pin Type Cells 60 INPUT D9 IN OUT 59 OUTPUT
107. DDCORE Resistor required by some DC DC Battery Converters Backup NRSTBU Shut down Jumper Disable coo WAKE UP TT ain Start Up To accommodate the different types of main power supply available and different signals that can command the shut down of this device tri state level O and level 1 are user definable for the Shut down pin The Wake up pin can be configured as detected on the positive or nega tive edge and at high or low level They are selected by the SHDALS and WKACKS fields in 12 7 Alarm If the Shut down feature is not used the pin SHDN can be used as an Alarm Output Signal from the RTC Alarm The Alarm State corresponds to Shut down and the Acknowledge or Non Alarm State corresponds to Wake up The alarm control logic is the same as that for Shut down The SHDALC command in APMC PCR defined by the field SHDALS APMC and the WKACKS command PCR defined by the field WKACKS field in APMC control the SHDN pin The alarm can be positioned by an RTC Alarm and be acknowledged by a programmable edge on the WAKEUP pin The Backup Reset initializes the logic in Non Alarm State 60 AT91M55800A memm 1745D ATARM 04 Nov 05 mmn A 1 55800 12 8 First Start up Sequence 1745D ATARM 04 Nov 05 At initial startup or after VDDBU has been disconnected the battery supplied logic must be initialized The Battery Backup Reset sets the following
108. Eight Chip select Registers CSRO to CSR7 are used to program the parameters for the individual external memories Each CSR must be programmed with a different base address even for unused chip selects Base Address 0 00000 Code Label EBI BASE Table 11 2 EBI Memory Offset Register Name Access Reset State 0x00 Chip select Register 0 EBI CSRO Read Write n 0x04 Chip select Register 1 EBI_CSR1 Read Write 0x10000000 0x08 Chip select Register 2 EBI_CSR2 Read Write 0x20000000 0x0C Chip select Register 3 EBI_CSR3 Read Write 0x30000000 0x10 Chip select Register 4 EBI_CSR4 Read Write 0x40000000 0x14 Chip select Register 5 EBI_CSR5 Read Write 0x50000000 0x18 Chip select Register 6 EBI_CSR6 Read Write 0x60000000 Ox1C Chip select Register 7 CSR7 Read Write 0x70000000 0x20 Remap Control Register Write only 0 24 Memory Control Register Read Write 0 Notes 1 8 bit boot if BMS is detected high 2 16 bit boot if BMS is detected low 1745D ATARM 04 Nov 05 mr nn 91 55800 11 10 1 EBI Chip Select Register Register Name CSRO CSR7 Access Type Read Write Reset Value See Table 11 2 Absolute Address OxFFEO00000 OXFFE0001C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAGES we NWS DB
109. Enable Memory Enable Write Enable Read Enable Memory Enable Byte select Access is used to connect 16 bit devices in a memory page e The signal is used as NLB and enables the lower byte for both read and write operations The signal NWR1 NUB is used as NUB and enables the upper byte for both read and write operations The signal NWRO NWE is used as NWE and enables writing for byte or half word e The signal NRD NOE is used as NOE and enables reading for byte or half word Figure 11 5 shows how to connect a 16 bit device with byte and half word access e g 16 bit SRAM on NCS2 Figure 11 5 Connection for a 16 bit Data Bus with Byte and Half word Access DO D7 D8 D15 18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable 28 91 55800 memm 1 55800 Boot NCSO 1745D ATARM 04 Nov 05 Figure 11 6 shows how to connect a 16 bit device without byte access e g Flash on NCS2 Figure 11 6 Connection for a 16 bit Data Bus Without Byte write Capability Write Enable Output Enable Memory Enable Depending on the device and the BMS pin level during the reset the user can select either an 8 bit or 16 bit external memory device connected on NCSO as the Boot Memory In this case CSRO Chip select Register 0 is reset
110. FVR register when an FIQ interrupt is raised By storing the following instruction at address 0x0000001C the processor loads the program counter with the interrupt handler address stored in the AIC FVR register ldr PC PC amp F20 Alternatively the interrupt handler be stored starting from address 0x0000001C as described in the ARM7TDMI datasheet 15 7 Software Interrupt Interrupt source 1 of the advanced interrupt controller is a software interrupt It must be pro grammed to be edge triggered in order to set or clear it by writing to the AIC ISCR and ICCR This is totally independent of the SWI instruction of the ARM7TDMI processor 15 8 Spurious Interrupt When the AIC asserts the NIRQ line the ARM7TDMI enters IRQ mode and the interrupt han dler reads the IVR It may happen that the AIC de asserts the NIRQ line after the core has taken into account the NIRQ assertion and before the read of the IVR This behavior is called a Spurious Interrupt The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the IVR is read The Spurious Vector can be programmed by the user when the vector table is initialized A Spurious Interrupt may occur in the following cases With any sources programmed to be level sensitive if the interrupt signal of the AIC input is de asserted at the same time as it is taken into account by the ARM7TDMI e f an interrupt is asserted at the same time as the
111. Features Utilizes the ARM7TDMI ARM Thumb Processor Core High performance 32 bit RISC Architecture High density 16 bit Instruction Set Leader in MIPS Watt Embedded ICE In Circuit Emulation 8K Bytes Internal SRAM Fully programmable External Bus Interface EBI Maximum External Address Space of 128M Bytes Eight Chip Selects Software Programmable 8 16 bit External Databus 8 level Priority Individually Maskable Vectored Interrupt Controller Seven External Interrupts Including a High priority Low latency Interrupt Request Fifty eight Programmable Lines 6 channel 16 bit Timer Counter Six External Clock Inputs and Two Multi purpose Pins per Channel Three USARTs Master Slave SPI Interface 8 bit to 16 bit Programmable Data Length Four External Slave Chip Selects Programmable Watchdog Timer 8 channel 10 bit ADC 2 channel 10 bit DAC Clock Generator with On chip Main Oscillator and PLL for Multiplication 3 to 20 MHz Frequency Range Main Oscillator Real time Clock with On chip 32 kHz Oscillator Battery Backup Operation and External Alarm 8 channel Peripheral Data Controller for USARTs and 5 Advanced Power Management Controller APMC Normal Wait Slow Standby and Power down modes IEEE 1149 1 JTAG Boundary scan on all Digital Pins Fully Static Operation 0 Hz to 33 MHz 2 7V to 3 6V Core Operating Range 2 7V to 5 5V I O Operating Range 2 7V to 3 6V Analog Operating Range 1 8V to 3 6V Back
112. Figure 18 5 Synchronous Mode Character Reception Example 8 bit parity enabled 1 stop RXD Sampling i D0 D1 D2 D3 D4 D5 D6 D7 i Stop Bit True Start Detection Parity Bit Receiver Ready When a complete character is received it is transferred to the US_RHR and the RXRDY sta tus bit in US_CSR is set If US_RHR has not been read since the last transfer the OVRE status bit in US_CSR is set Parity Error Each time a character is received the receiver calculates the parity of the received data bits in accordance with the field PAR in US_MR It then compares the result with the received par ity bit If different the parity error bit PARE in US_CSR is set When the character is completed and as soon as the character is read the parity status bit is cleared Framing Error If a character is received with a stop bit at low level and with at least one data bit at high level a framing error is generated This sets FRAME in US_CSR Time out This function allows an idle condition on the RXD line to be detected The maximum delay for which the USART should wait for a new character to arrive while the RXD line is inactive high level is programmed in US_RTOR Receiver Time out When this register is set to 0 no time out is detected Otherwise the receiver waits for a first character and then initializes a counter which is decremented at each bit period and reloaded at each byte reception When the counter reaches 0 the TIMEOUT bit in US_C
113. IBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products not intended authorized or warranted for use as components in applications intended to support or sustain life POWERED ARM Atmel Corporation 2005 All rights reserved Atmel logo and combinations thereof Everywhere You Are and others are registered trade mark sor trademarks of Atmel Corporation or its subsidiaries ARM the ARM Powered Logo and others are registered trademarks or trade marks of ARM Limited Other terms and product names may be the trademarks of others Printed recycled paper 1745D ATARM 04 Nov 05
114. M55800A 24 Packaging Information Figure 24 1 176 lead Thin Quad Flat Pack Package Drawing IUP VIEW BOTTOM VIEW C D T PIN 1 Yo mE 92 SEE DETAIL Ew S J IUO i Mn Al ced s m c oB EM EN A a H 1 DATUM 9 S x PLANE R1 R2 WITH LEAD FINISH 025 w g Y i 1 1 X N j lt d A 1 BASE METAL 2 2 DETAIL B A MEL 235 AMEL Table 24 1 Common Dimensions mm Symbol Min Nom Max 0 09 0 20 ci 0 09 0 16 0 45 0 6 0 75 L1 1 00 REF R2 0 08 0 2 1 0 08 5 0 2 4 0 3 5 7 01 0 02 11 12 13 03 11 12 13 A 1 6 A1 0 05 0 15 A2 1 35 1 4 1 45 Tolerances of form and position aaa 0 2 bbb 0 2 Table 24 2 Lead Count Dimensions mm Count BSC BSC 176 26 0 24 0 0 17 0 20 0 27 0 17 0 20 0 23 0 08 Table 24 3 Device and 176 lead LQFP Package Maximum Weight 2023 mg 236 AT91M55800A mw 1745D ATARM 04 Nov 05 Figure 24 2 176 ball Ball Grid Array
115. N and XOUT pin Consequently CL1 and CL2 can be removed when a crystal with a load capaci tance of 12 5 pF is used Figure 12 4 Typical Crystal Connection of Main Oscillator XIN XOUT GNDPLL 12 The Main Oscillator can be bypassed if the MOSCBYP bit in the Clock Generator Mode Regis ter APMC_CGMR is set to 1 In this case any frequency up to the maximum specified in the electrical characteristics datasheet can be input on the XIN pin If the PLL is used a minimum input frequency is required To minimize the power required to start up the system the Main Oscillator is disabled after the reset The software can deactivate the Main Oscillator to reduce the power consumption by clearing the MOSCEN bit The MOSCS Main Oscillator Status bit in APMC SR is automatically cleared indicating that the Main Oscillator is off Writing the MOSCEN bit in APMC reactivates the Main Oscillator and loads the value written in the OSCOUNT field in APMC_CGMR in the oscillator counter Then the oscillator counter decrements every 8 clock cycles and when it reaches 0 the MOSCS bit is set and can provide an interrupt Phase Lock Loop The Main Oscillator output signal feeds the phase lock loop which aims at multiplying the fre quency of its input signal by a number up to 64 This number is programmed in the MUL field of and the multiplication ratio is the programmed value plus one MUL 1 If a null valu
116. No effect AMEL 1745D ATARM 04 Nov 05 AMEL 16 9 5 PIO Output Disable Register Register Name PIO_ODR Access Type Write only Offset 0x14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ms Pua Pe J Pr Pm Po mo 7 6 5 4 3 2 1 0 wm P L This register is used to disable PIO output drivers If the pin is driven by the peripheral this has no effect on the pin but the information is stored The register is programmed as follows 1 Disables the PIO output on the corresponding pin 0 No effect 16 9 6 PIO Output Status Register Register Name PIO OSR Access Type Read only Offset 0x18 Reset Value 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p22 21 15 14 13 12 11 10 9 8 P P JL mn Po P j P P 7 6 5 4 3 2 1 0 P P 1 e T P TT gt This register shows the PIO pin control output enable status which is programmed in PIO_OER and PIO ODR The defined value is effective only if the pin is controlled by the PIO The register reads as follows 1 The corresponding PIO is output on this line 0 The corresponding PIO is input on this line 12 AT91M55800A memme 1745D ATARM 04 Nov 05 1 55800 16 9 7 PIO Input Filter Enable Register Register Name PIO IFER Access Type Write only Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
117. OA and PIOB The PIO controller enables the generation of an inter rupt on input change and insertion of a simple input glitch filter on any of the PIO pins WD Watchdog The Watchdog is built around a 16 bit counter and is used to prevent system lock up if the software becomes trapped in a deadlock It can generate an internal reset or interrupt or assert an active level on the dedicated NWDOVF All programming registers are pass word protected to prevent unintentional programming SF Special Function The AT91M55800A provides registers which implement the following special functions e Chip identification RESET status User Peripherals USART Universal Synchronous Asynchronous Receiver Transmitter The AT91M55800A provides three identical full duplex universal synchronous asynchronous receiver transmitters Each USART has its own baud rate generator and two dedicated Peripheral Data Controller channels The data format includes a start bit up to 8 data bits an optional programmable par ity bit and up to 2 stop bits The USART also features a Receiver Timeout register facilitating variable length frame sup port when it is working with the PDC and a Time guard register used when interfacing with slow remote equipment TC Timer Counter The AT91M55800A features two Timer Counter blocks that include three identical 16 bit timer counter channels Each channel can be independently programmed to perform a wide range
118. Package Drawing SIDE VIEW TYP 321 R g O B QAC Detail A AT91M55800A coeser 15141318 1110 9 8 2 5 5 4 342877 iain 0000000 ocodoog P OO B 989996920522 ROO F ODGO T 000 4 i i o P R Bottom View Symbol Maximum aaa 0 1 bbb 0 1 ddd 0 1 eee 0 03 fff 0 04 ggg 0 03 hhh 0 1 kkk 0 1 Notes 1 Package dimensions conform to Table 24 4 Device and 176 ball BGA Package Maximum Weight 606 mg JEDEC MO 205 2 Dimensioning and tolerancing per ASME Y14 5M 1994 3 All dimensions in mm 4 Solder Ball position designation per JESD 95 1 SPP 010 5 Primary datum Z and seating plane are defined by the spherical crowns of the solder balls 1745D ATARM 04 Nov 05 AMEL 237 AMEL 25 Soldering Profile 25 1 Green Package Soldering Profile Table 25 1 gives the recommended soldering profile from J STD 020C Table 25 1 Soldering Profile Green Compliant Package Profile Feature Green Package Average Ramp up Rate 217 C to Peak 3 C sec max Preheat Temperature 175 C 25 C 180 sec max Temperature Maintained Above 217 C 60 sec to 150 sec Time
119. RC Compare match at least once since the last read of the status COVFS Counter Overflow Counter has attempted to count past FFFF since the last read of the status ETRGS External Trigger External trigger has been detected since the last read of the status AT91M55800A m V Waveform Mode 191 55800A Figure 19 5 167 1911 9 SYlLMsa f 1912919 4 naaa sou 5 S SOLLN AMEL eieduo2 eyeduio o E 2 m o 4015040 09X o L MOW VOLLIA Sc LAON S MOW ZAN 1745D ATARM 04 Nov 05 19 5 User Interface Block 0 Base Address TC Block 1 Base Address AMEL OxFFFD0000 Code Label TCBO BASE OxFFFD4000 Code Label TCB1 BASE Table 19 2 Global Memory Offset Channel Register Name Access Reset State 0x00 TC Channel 0 See Table 19 3 0x40 TC Channel 1 See Table 19 3 0x80 TC Channel 2 See Table 19 3 0xC0 TC Block Control Register TC_BCR Write only _ 0xC4 TC Block Mode Register TC_BMR Read Write 0 TC_BCR Block Control Register and TC_BMR Block Mode Register control the TC block TC Channels are controlled by the registers listed in Table 19 3 The offset of each of the Channel registers in Table 19 3 is in relation to the offset of the cor
120. RQ DACOIRQ ADC1IRQ 15 14 13 12 11 10 9 8 ADCOIRQ PIOBIRQ PIOAIRQ WDIRQ TC5IRQ TC2IRQ 7 6 5 4 3 2 1 0 TC1IRQ TCOIRQ SPIRQ US2IRQ US1IRQ USOIRQ SWIRQ Interrupt Pending 0 Corresponding interrupt is inactive 1 Corresponding interrupt is pending 15 10 7 AIC Interrupt Mask Register Register Name AIC_IMR Access Type Read only Reset Value 0 Offset 0x110 31 30 29 28 27 26 25 24 COMMRX Io IRQS 23 22 21 20 19 18 17 16 APMCIRQ RTCIRQ DAC1IRQ DACOIRQ ADC1IRQ 15 14 13 12 11 10 9 8 ADCOIRQ PIOBIRQ PIOAIRQ WDIRQ TC5IRQ TC4IRQ TC2IRQ 7 6 5 4 3 2 1 0 TC1IRQ TCOIRQ SPIRQ US2IRQ US1IRQ USOIRQ SWIRQ Interrupt Mask 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled ATMEL 9 1745D ATARM 04 Nov 05 AMEL 15 10 8 AIC Core Interrupt Status Register Register Name AIC_CISR Access Type Read only Reset Value 0 Offset 0 114 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 us E _ T 6 5 4 3 2 1 0 NFIQ NFIQ Status Code Label NFIQ 0 NFIQ line inactive 1 NFIQ line active NIRQ NIRQ Status Code Label NIRQ 0 NIRQ line inactive 1 NIRQ line active 15 10 9 AIC Interrupt Enable Command Register Register Name AIC_IECR Access Type Write only Offset 0x120 31
121. Registers A and B are used as capture registers This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA The parameter LDRA defines the TIOA edge for the loading of register A and the parameter LDRB defines the TIOA edge for the loading of Register B RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA RB is loaded only if RA has been loaded since the last trigger or the last loading of RB Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag LOVRS in TC SR Status Register In this case the old value is overwritten 19 3 2 Trigger Conditions 19 3 3 Status Register 1745D ATARM 04 Nov 05 In addition to the SYNC signal the software trigger and the RC compare trigger an external trigger can be defined Bit ABETRG in selects input signal TIOA or TIOB as an external trigger Parameter ETRGEDG defines the edge rising falling or both detected to generate an external trigger If ETRGEDG 0 none the external trigger is disabled The following bits in the status register are significant in Capture Operating Mode CPCS RC Compare Status There has been an RC Compare match at least once since the last read of the status COVFS Counter Overflow Status The counter has attempted to count past FFFF since the last read of the status LOVRS
122. S 0 1 1 Selected clock is divided by 8 PRES DIV8 1 0 0 Selected clock is divided by 16 APMC PRES DIV16 1 0 1 Selected clock is divided by 32 APMC PRES DIV32 1 1 0 Selected clock is divided by 64 APMC PRES DIV64 1 1 1 Reserved MUL Phase Lock Loop Factor 0 The PLL is deactivated reducing power consumption to a minimum 1 63 The PLL output is at a higher frequency MUL 1 than the input if the bit lock is set in APMC_SR 66 91 55800 memm 1745D ATARM 04 Nov 05 mms r ncrs c r O I A191 55800A CSS Clock Source Selection CSS Clock Source Selection Code Label 0 0 Low frequency clock provided by the RTC APMC CSS LF 0 1 Main oscillator Output or external clock APMC CSS MOSC 1 0 Phase Lock Loop Output CSS 1 1 Reserved OSCOUNT Main Oscillator Counter Specifies the number of 32 768 Hz divided by 8 clock cycles for the main oscillator start up timer to count before the main oscillator is stabilized after the oscillator is enabled The main oscillator counter is a down counter which is preloaded with the OSCOUNT value when the MOSCEN bit in the Clock Generator Mode register CGMR is set but only if the OSCOUNT value is different from 0x0 PLLCOUNT PLL Lock Counter Specifies the number of 32 768 Hz clock cycles for the PLL lock timer to count before the PLL is locked after the PLL is started The PLL counter is a down counter which
123. S is set to 1 in TC_CMR When disabled the start or the stop actions no effect only a CLKEN command in the Control Register can re enable the clock When the clock is enabled the CLKSTA bit is set in the Status Register The clock can also be started or stopped a trigger software synchro external or compare always starts the clock The clock can be stopped by an RB load event in Capture Mode LDBSTOP 1 in TC CMR or a RC compare event in Waveform Mode CPCSTOP 1 in The start and the stop commands have effect only if the clock is enabled Figure 19 3 Clock Control Selected Clock Trigger Stop Disable Counter Event Event Clock 19 2 4 Timer Counter Operating Modes Each Timer Counter channel can independently operate in two different modes Capture Mode allows measurement on signals Waveform Mode allows wave generation The Timer Counter Mode is programmed with the WAVE bit in the TC Mode Register In Cap ture Mode TIOA and TIOB are configured as inputs In Waveform Mode TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger 19 2 5 Trigger A trigger resets the counter and starts the counter clock Three types of triggers are common to both modes and a fourth external trigger is available to each mode The following triggers are common to both modes A MEL 161 1745D ATARM 04 Nov 05 AMEL
124. SR is set The user can restart the wait for a first character with the STTTO Start Time out bit in US_CR Calculation of time out duration Duration Value e 4 e BitPeriod 91 55800 m mmn rc a A 1 55800 18 4 Transmitter 18 4 1 Time guard The transmitter has the same behavior in both synchronous and asynchronous operating modes Start bit data bits parity bit and stop bits are serially shifted lowest significant bit first on the falling edge of the serial clock See example in Figure 18 6 The number of data bits is selected in the CHRL field in 05 MR The parity bit is set according to the PAR field in US MR The number of stop bits is selected in the NBSTOP field in US MR When a character is written to US THR Transmit Holding it is transferred to the Shift Regis as soon as it is empty When the transfer occurs the TXRDY bit in 05 is set until a new character is written to US THR If Transmit Shift Register and US THR are both empty the TXEMPTY bit in US CSR is set The Time guard function allows the transmitter to insert an idle state on the TXD line between two characters The duration of the idle state is programmed in US TTGR Transmitter Time guard When this register is set to zero no time guard is generated Otherwise the transmit ter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in 05 TTGR Idle state duration Time guard
125. State 8 bit Bus Width Byte Transfer 4 1 Wait State i I 5 fA READ ACCESS onc Standard Protocol NRD 00 015 i 1 XB I I Early Protocol E NRD N L DO D15 X Bi WRITE ACCESS e e s 14 1 n Y H I e c r A NWRO N gt NWR1 I 1745D ATARM 04 Nov 05 A 1 55800 Figure 11 25 0 Wait States 16 bit Bus Width Byte Transfer MCK ADDR X X X 0 ADDR X XX 0 A1 A23 N Internal Address NCS NLB NUB READ ACCESS 00 015 Internal Bus Early Protocol NRD D0 D15 WRITE ACCESS NWRO NWR1 00 015 Byte Select Option 1745D ATARM 04 Nov 05 AMEL 11 10 EBI User Interface The EBI is programmed using the registers listed in the table below The Remap Control Reg ister RCR controls exit from Boot Mode see Section 11 5 Boot on 50 on page 29 The Memory Control Register is used to program the number of active chip selects and data read protocol
126. TC Status Clear Register Register Name RTC_SCR Access Type Write only Offset Ox1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALARM ACKUPD ACKUPD Acknowledge for Update Interrupt Clear Code Label RTC ACKUPD 0 No effect 1 Clears Acknowledge for Update status bit ALARM Alarm Flag Interrupt Clear Code Label RTC ALARM 0 No effect 1 Clears Alarm Flag bit SEC Second Event Interrupt Clear Code Label RTC SEC 0 No effect 1 Clears Second Event bit TIMEV Time Event Interrupt Clear Code Label RTC TIMEV 0 No effect 1 Clears Time Event bit e CALEV Calendar Event Interrupt Clear Code Label RTC CALEV 0 No effect 1 Clears Calendar Event bit 84 91 55800 1 A191 55800A 13 3 9 RTC Interrupt Enable Register Register Name RTC IER Access Type Write only Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALARM ACKUPD ACKUPD Acknowledge Update Interrupt Enable Code Label ACKUPD 0 No effect 1 2 The acknowledge for update interrupt is enabled ALARM Alarm Interrupt Enable Code Label RTC ALARM 0 No effect 1 The alarm interrupt is enabled SEC Second Event Interrupt Enable Code Label RTC SEC 0 No effect 1 The second periodic interrupt
127. TDMI processor with the on chip 32 bit memories the External Bus Interface EBI and the AMBA Bridge The AMBA Bridge drives the APB which is designed for accesses to on chip peripherals and optimized for low power consumption The AT91M55800A microcontroller implements the ICE port of the ARM7TDMI processor on dedicated pins offering a complete low cost and easy to use debug solution for target debugging 5 1 Memory The AT91M55800A microcontroller embeds 8K bytes of internal SRAM The internal memory is directly connected to the 32 bit data bus and is single cycle accessible The AT91M55800A microcontroller features an External Bus Interface EBI which enables connection of external memories and application specific peripherals The EBI supports 8 or 16 bit devices and can use two 8 bit devices to emulate a single 16 bit device The EBI imple ments the early read protocol enabling faster memory accesses than standard memory interfaces 5 2 Peripherals The AT91M55800A microcontroller integrates several peripherals which are classified as sys tem or user peripherals All on chip peripherals are 32 bit accessible by the AMBA Bridge and can be programmed with a minimum number of instructions The peripheral register set is composed of control mode data status and enable disable status registers An on chip 8 channel Peripheral Data Controller PDC transfers data between the on chip USARTS SPI and the on and off chip memories w
128. TRI Tri state mode select Input Low Sampled during reset JTAGSEL between ICE and JTAG Input _ TMS Test mode select Input Schmidt trigger internal pull up JTAG ICE TDI Test data input Input Schmidt trigger internal pull up TDO Test data output Output Test clock Input Schmidt trigger internal pull up NTRST Test reset input Input Low Schmidt trigger internal pull up VDDA Analog power Analog pwr GNDA Analog ground Analog gnd VDDBU Power backup Power GNDBU Ground backup Ground VDDCORE Digital core power Power x VDDIO Digital I O power Power VDDPLL Main oscillator and PLL power Power GND Digital ground Ground GNDPLL PLL ground Ground 1745D ATARM 04 Nov 05 4 JTAGSEL NTRST TMS TDO TDI TCK PBO PB1 PB2 PB5 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB3 IRQ4 PB4 IRQ5 PA9 IRQO PA10 IRQ1 PA11 IRQ2 PA12 IRQ3 PA13 FIQ PA14 SCKO PA15 TXDO PA16 RXDO PA17 SCK1 PA18 TXD1 NTRI PA19 RXD1 PA20 SCK2 PA21 TXD2 PA22 RXD2 PA23 SPCK PA24 MISO PA25 MOSI PA26 NPCSO NSS PA27 NPCS1 PA28 NPCS2 PA29 NPCS3 NWDOVF VDDA DAO DAVREF DA1 PB6 ADOTRIG ADO D1 D2 D3 gt gt gt ADVREF AD4 AD5 AD6 PB7 AD1TRIG GNDA 1745D ATARM 04 Nov 05 7 20 7 Embedded ICE JTAGSEL ARM7TDMI Core Internal RAM 8K Bytes ASB Controller k AIC K Advanced Interrup
129. The time for mat can be 24 hour mode or 12 hour mode with an AM PM indicator Updating time and calendar fields and configuring the alarm fields is performed by a parallel capture on the 32 bit data bus An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month year century 8 4 3 AIC Advanced Interrupt Controller The AIC has an 8 level priority individually maskable vectored interrupt controller and drives the NIRQ and NFIQ pins of the ARM7TDMI from The external fast interrupt line FIQ The six external interrupt request lines IRQO IRQ5 The interrupt signals from the on chip peripherals The AIC is largely programmable offering maximum flexibility and its vectoring features reduce the real time overhead in handling interrupts The AIC also features a spurious vector which reduces Spurious Interrupt handling to a mini mum and a protect mode that facilitates the debug capabilities 8 4 4 PIO Parallel Controller The AT91M55800A has 58 programmable I O lines 13 pins are dedicated as general purpose pins The other lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins The PIO lines are controlled by two separate and identical ATMEL 1745D ATARM 04 Nov 05 8 4 5 8 4 6 8 5 8 5 1 8 5 2 8 5 3 8 5 4 20 AMEL PIO Controllers called PI
130. The two identical 4 channel 10 bit analog to digital converters ADC are based on a Succes sive Approximation Register SAR approach ATMEL AIMEL 6 Associated Documentation Table 6 1 Associated Documentation Literature Product Information Document Title Number Internal architecture of processor ARM Thumb instruction sets ARM7TDMI Thumb Datasheet 0673 Embedded in circuit emulator External memory interface mapping Peripheral operations Peripheral user interfaces Ordering information AT91M55800A Datasheet This document 1745 Packaging information Soldering profile AT91M55800A Errata DC Characteristics Power consumption Thermal and reliability coniderations AC characteristics AT91M55800A Electrical Characteristics 1727 Product overview Ordering information Packaging information Soldering profile AT91M55800A Summary Datasheet 1745S 12 91 55800 memm mmn 91 55800 7 Product Overview 7 1 7 2 1745D ATARM 04 Nov 05 Power Supplies The AT91M55800A has 5 kinds of power supply pins VDDCORE pins which power the chip core VDDIO pins which power the Lines VDDPLL pins which power the oscillator and PLL cells VDDA pins which power the analog peripherals ADC and DAC VDDBU pins which power the RTC the 32768 Hz oscillator and the Shut down Logic of the APMC VDDIO and VDDCORE are separated to permit the I O lines to be powered wi
131. Transfer Format NCPHA equals One 8 bits per transfer SPCK cycle for refe SPCK CPOL 0 SPCK CPOL 1 MOSI from master MISO from slave NSS to slave Figure 20 4 SP SPCK cycle for reference 1 2 3 4 5 6 7 8 SPCK CPOL 0 SPCK CPOL 1 MOSI from master MISO from slave NSS to slave 1745D ATARM 04 Nov rence 1 2 3 4 5 6 7 8 qr Eu Transfer Format NCPHA equals Zero 8 bits per transfer EE SE CES bap A MEL 191 05 AMEL Figure 20 5 Programmable Delays DLYBCS DLYBS and DLYBCT Chip Select 1 Chip Select 2 SPCK Output Change peripheral of peripheral DLYBCS 4 3 20 5 Clock Generation In master mode the SPI Master Clock is either MCK or MCK 32 as defined by the MCK32 field of SP MR The SPI baud rate clock is generated by dividing the SPI Master Clock by a value between 4 and 510 The divisor is defined in the SCBR field in each Chip Select Register The transfer speed can thus be defined independently for each chip select signal CPOL and NCPHA in the Chip Select Registers define the clock data relationship between master and slave devices CPOL defines the inactive value of the SPCK NCPHA defines which edge causes data to change and which edge causes data to be captured In Slave Mode the input clock l
132. Valid Time Alarm Code Label RTC NVTAL 0 No invalid data has been detected in 1 RTC has contained invalid data since it was last programmed NVCAL Non Valid Calendar Alarm Code Label RTC NVCAL 0 No invalid data has been detected in CAR 1 RTC CAR has contained invalid data since it was last programmed 88 AT91M55800A memm mm 1 55800 14 WD Watchdog Timer The AT91M55800A has an internal Watchdog Timer that can be used to prevent system lock up if the software becomes trapped in a deadlock In normal operation the user reloads the watchdog at regular intervals before the timer over flow occurs If an overflow does occur the watchdog timer generates one or a combination of the following signals depending on the parameters in WD OMR Overflow Mode Register If RSTEN is set an internal reset is generated WD RESET as shown in Figure 14 1 If IRQEN is set a pulse is generated on the signal WDIRQ which is connected to the Advanced Interrupt Controller If EXTEN is set a low level is driven on the NWDOVF signal for a duration of 8 cycles The watchdog timer has a 16 bit down counter Bits 12 15 of the value loaded when the watchdog is restarted are programmable using the HPVC parameter WD Clock Mode Four clock sources are available to the watchdog counter MCK 32 MCK 128 MCK 1024 or MCK 4096 The selection is made using the WDCLKS parameter WD
133. W DBW Data Bus Width Code Label DBW Data Bus Width EBI DBW 0 0 Reserved 0 1 16 bit data bus width EBI DBW 16 1 0 8 bit data bus width DBW 8 1 1 Reserved NWS Number of Wait States This field is valid only if WSE is set Code Label NWS Number of Standard Wait States EBI NWS 0 0 0 1 EBI NWS 1 0 0 1 2 EBI NWS 2 0 1 0 3 EBI NWS 3 0 1 1 4 EBI NWS 4 1 0 0 5 NWS 5 1 0 1 6 EBI NWS 6 1 1 0 7 EBI NWS 7 1 1 1 8 EBI NWS 8 WSE Wait State Enable Code Label EBI WSE 0 Wait state generation is disabled No wait states are inserted 1 Wait state generation is enabled AIMEL 1745D ATARM 04 Nov 05 Gw AMEL PAGES Page Size Code Label PAGES Page Size Active Bits in Base Address EBI_PAGES 0 0 1M Byte 12 Bits 31 20 EBI PAGES 1M 0 1 4M Bytes 10 Bits 31 22 EBI PAGES 4M 1 0 16M Bytes 8 Bits 31 24 EBI PAGES 16M 1 1 64M Bytes 6 Bits 31 26 EBI PAGES 64M TDF Data Float Output Time Code Label TDF Number of Cycles Added after the Transfer EBI TDF 0 0 0 0 EBI TDF 0 0 0 1 1 EBI TDF 1 0 1 0 2 EBI TDF 2 0 1 1 3 EBI TDF 3 1 0 0 4 EBI TDF 4 1 0 1 5 EBI TDF 5 1 1 0 6 EBI TDF 6 1 1 1 7 EBI TDF 7 BAT Byte Access Type Code Label BAT Selected BAT EBI BAT 0 Byte write access type EBI BAT BYTE WRITE 1 Byte select access type EBI BAT BYTE SELECT CSEN Chip Select Enable Co
134. al for Channel 3 TIOB3 TIOB signal for Channel 3 TIOA4 TIOA signal for Channel 4 TIOB4 TIOB signal for Channel 4 5 TIOA signal for Channel 5 5 TIOB signal for Channel 5 Notes 1 After a hardware reset the TC clock is disabled by default See APMC Advanced Power Management Controller on page 52 The user must configure the Power Management Controller before any access to the User Interface of the TC 2 After a hardware reset the Timer Counter block pins are controlled by the PIO Controller They must be configured to be controlled by the peripheral before being used 1745D ATARM 04 Nov 05 AMEL 159 AMEL 19 2 Timer Counter Description 19 2 1 19 2 2 160 Counter Clock Selection AT91M55800A Each Timer Counter channel is identical in operation The registers for channel programming are listed in Table 19 1 on page 159 Each Timer Counter channel is organized around a 16 bit counter The value of the counter is incremented at each positive edge of the input clock When the counter reaches the value OxFFFF and passes to 0x0000 an overflow occurs and the bit COVFS in SR Status Reg ister is set The current value of the counter is accessible in real time by reading CV The counter be reset by a trigger In this case the counter value passes to 0x0000 on the next valid edge of the clock At block level input clock signals of each channel can either be connected
135. anced Power Management Controller which optimizes both the power consumption of the device and the complete system The APMC controls the clocking elements such as the oscillators and the PLL the core and the peripheral clocks and has the capability to control the system power supply Main Power is used throughout this document to identify the voltages powering the AT91M55800A and other components of the system with the exception of the Battery Backup voltage which is applied to the VDDBU Main Power supplies VDDIO VDDCORE and if required the analog voltage VDDA A battery or battery capacitor generally supplies the Bat tery Backup Power The APMC consists of the following elements The RTC Oscillator which provides the Slow Clock at 32768 Hz The Main Oscillator which provides a clock that depends on the frequency of the crystal connected to the XIN and XOUT pins The Phase Lock Loop The ARM Core Clock Controller which allows entry to the Idle Mode The Peripheral Clock Controller which conserves the power consumption of unused peripherals The Master Clock Output Controller The Shut down Logic which controls the Main Power Figure 12 1 APMC Module Shut down SHDN Logic NRSTBU LI Reset Control XIN32 L RTC XOUT32 LI Slow Clock SLCK VDDIO VDDCORE Arm Clock Device 0 XIN L Clock Peripheral Clocks Main OSC PLL Control n XOUTL ARM Interrupt IRQ and FIQ SLCKIRQ
136. ansfer from the DAC DHR to the DAC DOR is synchronized by the timer trigger 0 DAC TTRGEN DIS DAC TTRGEN EN TTRGSEL Timer Trigger Selection Only used if TTRGEN 1 Code Label TTRGSEL Selected Timer Trigger DAC TTRGSEL 0 0 0 TIOAO DAC 0 0 1 TIOA1 1 0 1 0 2 DAC TRG TIOA2 0 1 1 DAC TRG 1 0 0 TIOA4 1 0 1 5 DAC TRG 5 1 1 X Reserved RES Resolution RES Selected RES Code Label 0 10 bit resolution DAC 10 BIT RES 8 bit resolution DAC 8 BIT RES 222 AT91M55800A ma 1745D ATARM 04 Nov 05 mm A191 55800A 22 2 3 DAC Data Holding Register Register Name DHR Access Type Read Write Reset State 0 Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 LECCE DATA 7 6 5 4 3 2 1 0 DATA DATA Data to be Converted Code Label DAC DATA 10BITS DAC DATA 8BITS depending on RES Data that is to be converted by the DAC is stored in this register Data to be converted must be written in a right aligned format In 8 bit resolution mode RES 1 data written into the Data Holding Register will be shifted to the left by 2 bits and the two LSBs will be O In both 8 bit and 10 bit modes data will be read as written after the adjustments
137. around The user must either wait for the PLL lock flag to be set in the APMC status register or switch to an intermediate 32 kHz oscillator output CSS 0 27 4 Clock Switching with the Prescaler in the APMC is not Permitted Switching from the selected clock PRES 0 to the selected clock divided by 4 PRES 2 8 PRES 3 or 64 PRES 6 may lead to unpredictable results Problem Fix Workaround First the user should switch to any other value PRES 1 4 or 5 and wait for the actual switch to perform at least 64 cycles of the selected clock Then the user can write the final prescaler value 27 5 Initializing SPI in Master Mode May Cause a Mode Fault Detection Problem Fix Workaround In order to prevent this error the user must pull up the PA26 NPCSO NSS pin to the power supply A MEL 243 1745D ATARM 04 Nov 05 AMEL 27 6 SPI Slave Mode does not Work In transmission the data to be transmitted written in SP TDR is transferred in the shift register and consequently the TDRE bit in SP SR is set to 1 Though the transfer has not begun when the following data are written in SP TDR they are also transferred into the shift register crushing the precedent data and setting the bit TDRE to 1 Problem Fix Workaround No problem fix workaround to propose 27 7 Consumption is not Guaranteed The battery supply voltage consumption is not guaranteed in the case of internal peripheral accesses
138. ck PIO controlled after reset MISO Master in slave out PIO controlled after reset SPI MOSI Master out slave in PIO controlled after reset NSS Slave select Input Low PIO controlled after reset 50 NPCS3 Peripheral chip select Output Low PIO controlled after reset PAO PA29 Parallel I O port A Input after reset us PBO PB27 Parallel I O port B y o Input after reset WD NWDOVF Watchdog timer overflow Output Low Open drain ADO AD7 Analog input channels 0 7 Analog in ADOTRIG ADCO external trigger Input PIO controlled after reset iid AD41TRIG ADC1 external trigger Input PIO controlled after reset ADVREF Analog reference Analog ref 1745D ATARM 04 Nov 05 AMEL AMEL Table 3 1 Pin Description Continued Active Module Name Function Type Level Comments DAO DA1 Analog output channels 0 1 Analog out Mis DAVREF Analog reference Analog ref E XIN Main oscillator input Input XOUT Main oscillator output Output PLLRC RC filter for PLL Input XIN32 32 kHz oscillator input Input XOUT32 32 kHz oscillator output Output System clock Output sane WAKEUP Wakeup request Input SHDN Shutdown request Output Tri state after backup reset NRST Hardware reset input Input Low Schmidt trigger Reset NRSTBU 22 reset inp t tor battery Input Low Schmidt trigger N
139. ck Control Register allows the three channels to be started simultaneously with the same instruction The Block Mode Register defines the external clock inputs for each Timer Counter channel allowing them to be chained The internal configuration of a single Timer Counter Block is shown in Figure Figure 19 1 on page 158 A MEL 157 AMEL Figure 19 1 TC Block Diagram Parallel IO Controller Timer Counter Channel 0 Timer Counter Channel 1 Timer Counter Channel 2 Timer Counter Block Advanced Interrupt Controller 156 91 55800 mu 1 55800 19 4 Signal Name Description Table 19 1 Signal Name Description Channel Signals Description Block 0 Signals TCLKO TCLK1 TCLK2 XCO XC1 XC2 External Clock Inputs TIOA Capture Mode General purpose input Waveform Mode General purpose output TIOB Capture Mode General purpose input Waveform Mode General purpose input output INT Interrupt signal output SYNC Synchronization input signal Description External Clock Inputs for Channels 0 1 2 Block 1 Signals TCLK4 TCLK5 TIOAO TIOA signal for Channel 0 TIOBO TIOB signal for Channel 0 TIOA1 TIOA signal for Channel 1 TIOB1 TIOB signal for Channel 1 TIOA2 TIOA signal for Channel 2 TIOB2 TIOB signal for Channel 2 Description External Clock Inputs for Channels 3 4 5 TIOA3 TIOA sign
140. cument lit 1780 suppressed format update 1745D ATARM 04 Nov 05 ATMEL 245 msn rn 91 55800 Table of Contents 1745D ATARM 04 Nov 05 a i 1 1 Description 1 2 Pin Configurations 3 3 Pin Description PD 7 E 9 5 Architectural Overview 10 51 MOMON T 10 52 e Na 10 6 Associated Documentation 12 77 Product OVEIVIBW iD DRUNK QUEM USE 13 74 JPowerSupplies rn rena ee HO ERR RENE ERE 13 7 2 Input Output Considerations 13 7 9 Ctucie AR 14 em 14 7 5 Emulation Functions uuu l l u eric Pede 15 7 6 Memory Controller ice reeci 15 7 7 Extemal Bus Interface rentre Lr tr Ve b EE YER YR a dde 17 8 Peripherals EET EEUU 18 8 1 Peripheral Registers 2 18 8 2 Peripheral Interrupt Control 18 8 3 Peripheral Data Controller
141. current level but with higher priority than the new current level the NIRQ line is reasserted but the interrupt sequence does not immediately start because the bit is set in the core The SPSR SPSR is restored Finally the saved value of the Link Register is restored directly into the PC This has effect of returning from the interrupt to what ever was being executed before and of loading the CPSR with the stored SPSR 10 AT91M55800A mmm 1745D ATARM 04 Nov 05 mnr 1 55800 masking or unmasking the interrupts depending the state saved in the SPSR the previous state of the ARM Core Note Thel bitin the SPSR is significant If it is set it indicates that the ARM Core was just about to mask IRQ interrupts when the mask instruction was interrupted Hence when the SPSR is restored the mask instruction is completed IRQ is masked A MEL 111 1745D ATARM 04 Nov 05 AMEL 16 PIO Parallel Controller The AT91M55800A has 58 programmable I O lines 13 pins are dedicated as general purpose I O pins The other lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins The PIO lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB The PIO controller enables the generation of an inter rupt on input change and insertion of a simple input glitch filter on any of the PIO pins 16 1 Multiplexed I O Lines Some I O
142. d only when writing SF PMR PMRKEY is reads O 0x27A8 Write access in SF PMR is allowed Other value Write access in PMR is prohibited AIC AIC Protect Mode Enable Code Label SF AIC 0 The Advanced Interrupt Controller runs in Normal Mode 1 The Advanced Interrupt Controller runs in Protect Mode AMEL 1745D ATARM 04 Nov 05 AMEL 18 USART Universal Synchronous Asynchronous Receiver Transmitter AT91M55800AA provides three identical full duplex universal synchronous asynchro nous receiver transmitters which are connected to the Peripheral Data Controller The main features are Programmable Baud Rate Generator Parity Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo Local Loopback and Remote Loopback channel modes Multi drop Mode Address Detection and Generation Interrupt Generation Two Dedicated Peripheral Data Controller channels 5 6 7 8 and 9 bit character length Figure 18 1 USART Block Diagram ASB Peripheral Data Controller Receiver Transmitter Channel Channel PIO Parallel USART Channel yo APB Controller Transmitter RXD USxIRQ Interrupt Control us gt TXD Baud Rate Generator Baud Rate Clock MCK 8 SCK 1 55800 18 1 Pin Description Table 18 1 USART Channel External Signals Name Description USART Serial clock can be conf
143. d through the NTRST signal The NTRST control pin initializes the selected TAP controller The TAP controller involved in this reset is determined according to the initial logical state applied on the JTAGSEL pin after the last valid NRST In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir cuitry as shown in Figure 7 1 below But in all cases the NTRST like the NRST signal must be asserted after each power up See the AT91M55800A electrical datasheet Atmel lit 1727 for the necessary minimum pulse assertion time Figure 7 1 Separate or Common Reset Management Reset Controller Reset Controller Reset AT91M55800A AT91M55800A 1 2 Notes 1 NRST and NTRST handling in Debug Mode during development 2 NRST and NTRST handling during production 1745D ATARM 04 Nov 05 mmn rr sn n 191 55800A In order to benefit the most regarding the separation of NRST and NTRST during the Debug phase of development the user must independently manage both signals as shown in exam ple 1 of Figure 7 1 above However once Debug is completed both signals are easily managed together during production as shown in example 2 of Figure 7 1 above 7 4 3 Watchdog Reset The watchdog can be programmed to generate an internal reset In this case the reset has the same effect as the NRST pin assertion but the pins BMS and NTRI are not sampled Boot Mode and Tri state Mode are n
144. dar counting Calendar counting consists of day date month year and century counters Calendar counters can be programmed once this bit is set TEVSEL Time Event Selection The event which generates the flag in SR Status Register depends on the value TEVSEL TEVSEL Event Code Label 0 0 Minute change RTC TEVSEL MN CHG 0 1 Hour change TEVSEL 1 0 Every day at midnight TEVSEL EVDAY MD 1 1 Every day at noon RTC TEVSEL EVDAY NOON CEVSEL Calendar Event Selection The event which generates the flag CALEV in RTC_SR depends on the value of CEVSEL CEVSEL Event Code Label 0 0 Week change every Monday at time 00 00 00 RTC CEVSEL WEEK CHG 0 1 Month change every 01 of each month at time 00 00 00 RTC CEVSEL MONTH CHG 1 0 Year change every January 1st at time 00 00 00 RTC CEVSEL YEAR CHG 1 1 Reserved AMEL 1745D ATARM 04 Nov 05 AMEL 13 3 2 RTC Hour Mode Register Register Name RTC_HMR Access Type Read Write Reset State 0x0 Offset 0x04 31 30 29 28 27 26 25 24 1 23 22 21 20 19 18 17 16 E aa Ll a _ 15 14 13 12 11 10 9 8 11 h 7 6 5 4 3 2 1 0 qoo qo oo dE lt soo CL HRMOD 12 24 Hour Mode Selected HRMOD Code Label 24 Hour mode is selected 24 HRMOD 12 Hour mode is selected RTC
145. de Label EBI CSEN 0 Chip select is disabled 1 Chip select is enabled BA Base Address Code Label EBI BA These bits contain the highest bits of the base address If the page size is larger than 1M byte the unused bits of the base address are ignored by the EBI decoder 50 AT91M55800A memm 1745D ATARM 04 Nov 05 mm Fr A191 55800A 11 10 22 EBI Remap Control Register Register Name EBI_RCR Access Type Write only Absolute Address OxFFE00020 Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p C C C L se RCB Remap Command Bit Code Label EBI RCB 0 No effect 1 Cancels the remapping performed at reset of the page zero memory devices 11 10 3 Memory Control Register Register Name Access Read Write Reset Value 0 Absolute Address OxFFE00024 Offset 0x24 31 30 29 28 27 26 25 24 ieee E Jj 23 22 21 20 19 18 17 16 poo _ 15 14 13 12 11 10 9 8 L uw p Cj o Se 7 6 5 4 3 2 1 0 NN NE De DRP Data Read Protocol Code Label DRP Selected DRP EBI_DRP 0 Standard read protocol for all external memory devices enabled EBI_DRP_STANDARD 1 Early read protocol for all external memory devices enabled EBI DRP EARLY AMEL s 1745D ATARM 04 Nov 05 AMEL 12 APMC Advanced Power Management Controller The AT91M55800A features an Adv
146. detected since the last read of SP SR 1 An overrun has occurred since the last read of SP SR An overrun occurs when SP RDR is loaded at least twice from the serializer since the last read of the SP SPENDRX End of Receiver Transfer Code Label SP ENDRX 0 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive 1 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active SPENDTX End of Transmitter Transfer Code Label SP ENDTX 0 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive 1 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active SPIENS SPI Enable Status Code Label sP SPIENS 0 SPI is disabled 1 SPI is enabled A MEL 199 1745D ATARM 04 Nov 05 AMEL 20 7 6 SPI Interrupt Enable Register Register Name SP_IER Access Type Write only Offset 0x14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPENDTX SPENDRX OVRES MODF TDRE RDRF Receive Data Register Full Interrupt Enable Code Label SP RDRF 0 No effect 1 Enables the Receiver Data Register Full Interrupt TDRE SPI Transmit Data Register Empty Interrupt Enable Code Label SP_TDRE 0 No effect 1 Enables the Transmit Data Register Empty I
147. e 21 1 ADC Pin Description Pin Name Description VDDA Analog power supply GNDA Analog ground ADVREF Reference voltage ADO AD7 Analog input channels ADOTRIG AD1TRIG External triggers A MEL 207 1745D ATARM 04 Nov 05 21 0 1 21 0 2 21 0 3 21 0 4 208 AMEL Analog to digital Conversion The ADC has an internal sample and hold circuit that holds the sampled analog value during a complete conversion The reference voltage pin ADVREF allows the analog input conversion range to be set between 0 and ADVREF Analog inputs between these voltages convert to values based on a linear conversion The ADC uses the ADC Clock to perform the conversion To convert a single analog value to a 10 bit digital data requires 11 ADC clock cycles The ADC Clock frequency is selected in the PRESCAL field of the Mode Register ADC_MR Conversion Results When a conversion is complete the resulting 10 bit digital value is stored in the Convert Data Register ADC_CDR of the selected channel and the corresponding EOC flag in the Status Register ADC_SR is set This bit can provide an interrupt signal and is automatically cleared when the corresponding Convert Data Register ADC_CDR is read If the ADC_CDR is not read before further incoming data is converted the corresponding Overrun Error OVRE flag is set in the Status Register SR The ADC offers an 8 bit or 10 bit operating mode By default afte
148. e AIC pins are controlled by the PIO Controller They must be configured to be controlled by the peripheral before being used 1745D ATARM 04 Nov 05 AMEL AMEL Table 15 1 Interrupt Sources Interrupt Source Interrupt Name Interrupt Description 0 FIQ Fast interrupt 1 SWIRQ Software interrupt 2 USOIRQ USART Channel 0 interrupt 3 US1IRQ USART Channel 1 interrupt 4 US2IRQ USART Channel 2 interrupt 5 SPIRQ SPI interrupt 6 TCOIRQ Timer Channel 0 interrupt 7 TC1IRQ Timer Channel 1 interrupt 8 TC2IRQ Timer Channel 2 interrupt 9 TC3IRQ Timer Channel 3 interrupt 10 TC4IRQ Timer Channel 4 interrupt 11 TC5IRQ Timer Channel 5 interrupt 12 WDIRQ Watchdog interrupt 13 PIOAIRQ Parallel I O Controller A interrupt 14 PIOBIRQ Parallel I O Controller B interrupt 15 ADOIRQ Analog to digital Converter Channel 0 interrupt 16 AD1IRQ Analog to digital Converter Channel 1 interrupt 17 DAOIRQ Digital to analog Converter Channel 0 interrupt 18 DA1IRQ Digital to analog Converter Channel 1 interrupt 19 RTCIRQ Real time Clock interrupt 20 APMCIRQ Advanced Power Management Controller interrupt 21 Reserved 22 Reserved 23 SLCKIRQ Slow Clock Interrupt 24 IRQ5 External interrupt 5 25 IRQ4 External interrupt 4 26 IRQ3 External interrupt 3 27 IRQ2 External interrupt 2 28 IRQ1 External interrupt 1 29 IRQ0 External interrupt 0 30 COMMRX RX Debu
149. e Software Trigger Each channel has a software trigger available by setting SWTRG in TC_CCR e SYNC Each channel has a synchronization signal SYNC When asserted this signal has the same effect as a software trigger The SYNC signals of all channels are asserted simultaneously by writing TC_BCR Block Control with SYNC set Compare RC Trigger RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC CMR The Timer Counter channel can also be configured to have an external trigger In Capture Mode the external trigger signal can be selected between TIOA and TIOB In Waveform Mode an external event can be programmed on one of the following signals TIOB XCO XC1 or XC2 This external event can then be programmed to perform a trigger by setting ENETRG in If an external trigger is used the duration of the pulses must be longer than the system clock MCK period in order to be detected 191 55800A 19 3 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC CMR Channel Mode Register Capture Mode allows the TC Channel to perform measurements such as pulse timing fre quency period duty cycle and phase on TIOA and TIOB signals which are considered as input Figure 19 4 shows the configuration of the TC Channel when programmed in Capture Mode 19 3 1 Capture Registers A and B RA and RB
150. e is programmed into MUL the PLL is automatically disabled to save power The PLL is disabled at reset to minimize the power consumption A start up sequence must be executed to enable the PLL if it is disabled This sequence is started by writing a new MUL value in This automatically clears the LOCK bit AT91M55800A mm waww 1745D ATARM 04 Nov 05 mmn 91 55800 12 3 3 12 3 4 PLL Filter in APMC_SR and loads the PLL counter with the value programmed in the PLLCOUNT field Then the PLL counter decrements at each Slow Clock cycle Note Programming in PLLCOUNT is the minimum allowed and guarantees at least 2 Slow Clock cycles before the lock bit is set Programming nin PLLCOUNT guarantees n 1 the delay of Slow Clock cycles When the PLL Counter reaches 0 the LOCK bit in APMC_SR is set and can cause an interrupt Programming MUL or PLLCOUNT before the LOCK bit is set may lead to unpredictable behavior If the PLL multiplication is changed while the PLL is already active the LOCK bit in APMC_SR is automatically cleared and the same sequence is restarted The PLL is automatically bypassed while the frequency is changing while LOCK is 0 If the Main Oscillator is reacti vated at the same time the PLL is enabled the LOCK bit is set only when both the Main Oscillator and the PLL are stabilized The Phase Lock Loop has a dedicated PLLRC pin which must connect with an appropriate second order fil
151. ect Code Label TC BEEVT 0 None TC BEEVT OUTPUT NONE 0 Set TC BEEVT SET OUTPUT 1 Clear TC BEEVT CLEAR OUTPUT 1 Toggle TC BEEVT TOGGLE OUTPUT 16 AT91M55800A m L 1745D ATARM 04 Nov 05 mr n 191 55800 BSWTRG Software Trigger Effect on TIOB BSWTRG Effect Code Label TC BSWTRG 0 0 None TC BSWTRG OUTPUT NONE 0 1 Set TC BSWTRG SET OUTPUT 1 0 Clear TC BSWTRG CLEAR OUTPUT 1 1 Toggle TC BSWTRG TOGGLE OUTPUT A MEL 177 1745D ATARM 04 Nov 05 AMEL 19 5 6 TC Counter Value Register Register Name TC_CVR Access Type Read only Reset State 0 Offset 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ A A A _ N _ lt NT lt N A o e CV Counter Value Code Label TC CV contains the counter value in real time 19 5 7 TC Register A Register Name TC RA Access Type Read only if WAVE 0 Read Write if WAVE 1 Reset State 0 Offset 0 14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RA Register A Code Label TC RA contains the Register A value in real time 178 AT91M55800A mc 1745D ATARM 04 Nov 05 mm rsn 191 155800 19 5 8 TC Register B Register Name TC RB Access Type Read only if WAVE 0 Read Write if WAVE 1 Reset State 0 Offset 0x18 31 30 29 28 27
152. efined in four different ways according to the following conditions If a pin is controlled by the PIO Controller and is defined as an output see Output Selection above the level is programmed using the registers SODR Set Output Data and PIO CODR Clear Output Data In this case the programmed value can be read in PIO ODSR Output Data Status If a pin is controlled by the PIO Controller and is not defined as an output the level is deter mined by the external circuit If a pin is not controlled by the PIO Controller the state of the pin is defined by the peripheral see peripheral datasheets In all cases the level on the pin can be read in the register PIO PDSR Pin Data Status Optional input glitch filtering is available on each pin and is controlled by the registers PIO IFER Input Filter Enable and PIO IFDR Input Filter Disable The input glitch filtering 112 AT91M55800A memm 1745D ATARM 04 Nov 05 A 1 55800 16 5 Interrupts 16 6 User Interface can be selected whether the pin is used for its peripheral function or as a parallel I O line The register PIO IFSR Input Filter Status indicates whether or not the filter is activated for each pin Each parallel I O can be programmed to generate an interrupt when a level change occurs This is controlled by the PIO IER Interrupt Enable and PIO IDR Interrupt Disable registers which enable disable the interr
153. er enabling the reduction of the output impedance and the possibility of driving external loads directly without having to add an external operational amplifier The maximum load supported by the output buffer is indicated in the Electrical Char acteristics of the device 22 1 1 8 or 10 bit Conversion Mode Bit RES in the Mode Register DAC_MR selects between 8 bit or 10 bit modes of operation In 8 bit mode the data written in DAC_DHR is automatically shifted left two bits and the two lowest bits are written 0 The bit RES also affects the type of transfers performed by the PDC channel in 8 bit mode only byte transfer is performed in 10 bit mode a half word transfer 16 bits is performed 22 1 2 Trigger Selection 1745D ATARM 04 Nov 05 A conversion is triggered when data is written in DAC and TRGEN in DAC MR is 0 If TRGEN is 1 a hardware trigger is selected by the field TTRGSEL between the Timer Counter Channel outputs TIOA In this case the corresponding Timer Counter channel must be programmed in Waveform Mode and each time the DAC detects a rising edge on the TC output it transfers the last data written in DAC into DAC DOR The bit DATRDY traces the fact that a valid data has been written in DAC and not yet been transferred in DAC DOR An interrupt can be generated from this status bit to tell the software to load the following value A MEL 219 AMEL 22 2 DAC User Interface
154. eripheral registers that are updated at 32 kHz cannot be ensured Master Clock Output The Master Clock can be output to the MCKO pad The MCKO pad can be tri stated to mini mize power consumption by setting the bit MCKODS Master Clock Output Disable in APMC_CGMR default is MCKO enabled 91 55800 memme 1745D ATARM 04 Nov 05 mmn 1 55800 12 4 5 AT91M55800A has only system clock the ARM Core clock It be enabled and disabled by writing to the System Clock Enable APMC_SCER and System Clock Disable Registers SCDR The status of the ARM Core clock at least for debug purposes be read in the System Clock Status Register APMC_SCSR The ARM Core clock is enabled after a reset and is automatically re enabled by any enabled interrupt When the ARM Core clock is disabled the current instruction is finished before the clock is stopped Note Stopping the ARM Core does not prevent PDC transfers 12 5 Peripheral Clocks Each peripheral clock integrated in the AT91M55800A can be individually enabled and dis abled by writing to the Peripheral Clock Enable APMC and Peripheral Clock Disable APMC PCDR Registers The status of the peripheral clocks can be read in the Peripheral Clock Status Register APMC When a peripheral clock is disabled the clock is immediately stopped When the clock is re enabled the peripheral resumes action
155. est to the processor and clears the interrupt in case it is programmed to be edge trig gered This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs At the end of the interrupt service routine the end of interrupt command register must be written This allows pending interrupts to be serviced ATMEL 1745D ATARM 04 Nov 05 AMEL 15 4 Interrupt Masking Each interrupt source including FIQ can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR The interrupt mask can be read in the Read only register AIC_IMR A disabled interrupt does not affect the servicing of other interrupts 15 5 Interrupt Clearing and Setting All interrupt sources which are programmed to be edge triggered including FIQ can be indi vidually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR This function of the interrupt controller is available for auto test or software debug purposes 15 6 Fast Interrupt Request The external FIQ line is the only source which can raise a fast interrupt request to the proces sor Therefore it has no priority controller The external FIQ line can be programmed to be positive or negative edge triggered or high or low level sensitive in the AIC SMRO register The fast interrupt handler address can be stored in the AIC SVRO register The value written into this register is available by reading the AIC
156. external event EEVT parameter in Figure 19 5 shows the configuration of the TC Channel when programmed in Waveform Oper ating Mode 19 4 1 Compare Register A B and C RA RB and RC In Waveform Operating Mode RA RB and RC are all used as compare registers RA Compare is used to control the TIOA output RB Compare is used to control the TIOB if configured as output RC Compare can be programmed to control TIOA and or TIOB outputs RC Compare can also stop the counter clock CPCSTOP 1 in CMR and or disable the counter clock CPCDIS z 1 in CMR As in Capture Mode RC Compare can also generate a trigger if CPCTRG 1 Trigger resets the counter so RC can control the period of PWM waveforms 19 4 2 External Event Trigger Conditions An external event can be programmed to be detected on one of the clock sources XCO XC1 XC2 or TIOB The external event selected can then be used as a trigger The parameter EEVT in selects the external trigger The parameter EEVTEDG defines the trigger edge for each of the possible external triggers rising falling or both If EEVTEDG is cleared none no external event is defined If TIOB is defined as an external event signal EEVT 0 TIOB is no longer used as output and the TC channel can only generate a waveform on TIOA When an external event is defined it can be used as a trigger by setting bit ENETRG in TC CMR As in Capture Mode the SYNC signal
157. fines peripheral chip select signals 4 to 7 SP CSR2defines peripheral chip select signals 8 to 11 CSR3defines peripheral chip select signals 12 to 150 Note 1 The 16th state corresponds to a state in which all chip selects are inactive This allows a dif ferent clock configuration to be defined by each chip select register e MCK32 Clock Selection Code Label SP DIV32 0 SPI Master Clock equals 1 SPI Master Clock equals MCK 32 LLB Local Loopback Enable Code Label SP LLB 0 Local loopback path disabled 1 2 Local loopback path enabled LLB controls the local loopback on the data serializer for testing in master mode only A MEL 195 1745D ATARM 04 Nov 05 AMEL PCS Peripheral Chip Select Code Label sP PCS This field is only used if Fixed Peripheral Select is active PS 0 If PCSDEC 0 PCS 3 0 1110 Code Label SP PCSO PCS xx01NPCS 3 0 1101 Code Label SP PCS1 PCS x011NPCS 3 0 1011 Code Label SP PCS2 PCS 0111NPCS 3 0 0111 Code Label SP PCS3 PCS 1111forbidden no peripheral is selected x 2 don t care If PCSDEC 1 NPCS 3 0 output signals PCS DLYBCS Delay Between Chip Selects Code Label SP DLYBCS This field defines the delay from NPCS inactive to the activation of another NPCS The DLYBCS time guarantees non over lapping chip selects and solves bus contentions in case of peripherals having long data float times If DLYBCS is
158. g Communication Channel interrupt 31 COMMTX TX Debug Communication Channel interrupt 96 AT91M55800A mu 1745D ATARM 04 Nov 05 mm n 1 55800 15 1 Hardware Interrupt Vectoring The hardware interrupt vectoring reduces the number of instructions to reach the interrupt handler to only one By storing the following instruction at address 0x00000018 the processor loads the program counter with the interrupt handler address stored in the AIC_IVR register Execution is then vectored to the interrupt handler corresponding to the current interrupt ldr amp F20 The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register AIC_IVR is read The value read in the AIC_IVR corresponds to the address stored in the Source Vector Register AIC_SVR of the current interrupt Each interrupt source has its cor responding AIC_SVR In order to take advantage of the hardware interrupt vectoring it is necessary to store the address of each interrupt handler in the corresponding AIC_SVR at system initialization 15 2 Priority Controller The NIRQ line is controlled by an 8 level priority encoder Each source has a programmable priority level of 7 to 0 Level 7 is the highest priority and level 0 the lowest When the AIC receives more than one unmasked interrupt at a time the interrupt with the highest priority is serviced first If both interrupts have equal priority the interrupt with the low est
159. ge of SPCK causes data to change and which edge causes data to be captured NCPHA is used with CPOL to produce a desired clock data relationship between master and slave devices BITS Bits Per Transfer The BITS field determines the number of data bits transferred Reserved values should not be used BITS 3 0 Bits Per Transfer Code Label sP BITS 0000 8 SP BITS 8 0001 9 SP BITS 9 0010 10 SP BITS 10 0011 11 SP BITS 11 0100 12 SP BITS 12 0101 13 SP BITS 13 0110 14 SP BITS 14 0111 15 SP BITS 15 1000 16 SP BITS 16 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved A MEL 205 1745D ATARM 04 Nov 05 AMEL e SCBR Serial Clock Baud Rate Code Label SP_SCBR In Master Mode the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock selected between MCK and MCK 32 The Baud rate is selected by writing a value from 2 to 255 in the field SCBR The following equation determines the SPCK baud rate SPI Master Clock frequency 2 x SCBR SPCK Baud Rate Giving SCBR a value of zero or one disables the baud rate generator SPCK is disabled and assumes its inactive state value No serial transfers may occur At reset baud rate is disabled DLYBS Delay Before SPCK Code Label SP DLYBS This field defines the delay from NPCS valid to the first valid SPCK transit
160. gister in the BSR The OUTPUT bit contains data which can be forced on the pad The CTRL bit can put the pad into high impedance Each AT91M55800A in out pin corresponds to a 3 bit register in the BSR The OUTPUT bit contains data that can be forced on the pad The INPUT bit is for the observability of data applied to the pad The CTRL bit selects the direction of the pad Table 23 1 JTAG Boundary scan Register Bit Associated BSR Number Pin Name Pin Type Cells 256 NWAIT INPUT INPUT 255 NRST INPUT INPUT 254 OUTPUT 253 PB18 BMS IN OUT INPUT 252 CTRL 250 CTRL 249 OUTPUT NWDOVF OUTPUT 248 CTRL 247 OUTPUT 246 PB17 IN OUT INPUT 245 CTRL 244 OUTPUT 243 PB16 IN OUT INPUT 242 CTRL 241 OUTPUT 240 PB15 IN OUT INPUT 239 CTRL 238 OUTPUT 237 PB14 IN OUT INPUT 236 CTRL PB13 IN OUT 234 233 PB13 IN OUT CTRL 1745D ATARM 04 Nov 05 AMEL 227 AMEL Table 23 1 JTAG Boundary scan Register Continued Bit Associated BSR Number Pin Name Pin Type Cells 232 OUTPUT 231 PB12 IN OUT INPUT 230 CTRL 229 OUTPUT 228 PB11 IN OUT INPUT 227 CTRL 226 OUTPUT 225 PB10 IN OUT INPUT 224 CTRL 223 OUTPUT
161. gram below ATMEL s 12 3 5 12 3 6 12 3 7 58 AMEL Slow Clock Mode 3 PLL Clock Cycles Figure 12 6 Clock Switch 5 SLCK Cycles 5 SLCK Cycles 3 SLCK Cycles 3 Oscillator Clock Cycles 5 SLCK Cycles PLL Clock Mode 8 PLL Clock Cycles 7 SLCK Cycles Oscillator Clock Mode 3 PLL Clock Cycles 4 SLCK Cycles 3 Oscillator Clock Cycles Slow Clock Interrupt Prescaler The APMC also features the Slow Clock interrupt allowing the user to detect when the Master Clock is actually switched to the Slow Clock Switching from the Slow Clock to a higher fre quency is generally performed safely as the processor is running slower than the target frequency However switching from a high frequency to the Slow Clock requires the high fre quency to be valid during the switch time The Slow Clock interrupt permits the user to know exactly when the switch has been achieved thus when the Main Oscillator or the PLL can be disabled The prescaler is the last stage to provide the master clock It permits the selected clock to be divided by a power of 2 between 1 and 64 The default value is 1 after the reset The prescaler allows the microcontroller operating frequency to reach down to 512 Hz Precautions must be taken when defining a master clock lower than the Slow Clock as some peripherals RTC and APMC can still operate at Slow Clock frequency In this case access to the p
162. he last read of the Status Register or WAVE 0 1 RA Compare has occurred since the last read of the Status Register if WAVE 1 CPBS RB Compare Status Code Label TC CPBS 0 RB Compare has not occurred since the last read of the Status Register or WAVE 0 1 RB Compare has occurred since the last read of the Status Register if WAVE 1 CPCS RC Compare Status Code Label TC CPCS 0 RC Compare has not occurred since the last read of the Status Register 1 RC Compare has occurred since the last read of the Status Register LDRAS RA Loading Status Code Label TC LDRAS 0 RA Load has not occurred since the last read of the Status Register or WAVE 1 1 RA Load has occurred since the last read of the Status Register if WAVE 0 LDRBS RB Loading Status Code Label TC LDRBS 0 RB Load has not occurred since the last read of the Status Register or WAVE 1 1 RB Load has occurred since the last read of the Status Register if WAVE 0 ETRGS External Trigger Status Code Label TC ETRGS 0 External trigger has not occurred since the last read of the Status Register 1 External trigger has occurred since the last read of the Status Register CLKSTA Clock Enabling Status Code Label TC CLKSTA 0 Clock is disabled 1 Clock is enabled TIOA Mirror Code Label TC 0 TIOA is low If WAVE 0 this means that TIOA pin is low If WAVE 1 this means that TIOA is driven low 1 TIOA is high
163. he transfer is finished before the SPI is disabled If both SPIEN and SPIDIS are equal to one when the control register is written the SPI is disabled SWRST SPI Software reset Code Label SWRST 0 No effect 1 Resets the SPI A software triggered hardware reset of the SPI interface is performed XX m A191 55800A 20 7 2 SPI Mode Register Register Name SP MR Access Type Read Write Reset State 0 Offset 0 04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m oe j 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ug PCSDEC MSTR MSTR Master Slave Mode Code Label SP MSTR 0 SPI is in Slave mode 1 SPI is in Master mode MSTR configures the SPI Interface for either master or slave mode operation PS Peripheral Select PS Selected PS Code Label sP PS 0 Fixed Peripheral Select SP PS FIXED 1 Variable Peripheral Select SP PS VARIABLE PCSDEC Chip Select Decode Code Label PCSDEC 0 The chip selects are directly connected to a peripheral device 1 The four chip select lines are connected to a 4 to 16 bit decoder When PCSDEC equals one up to 16 Chip Select signals can be generated with the four lines using an external 4 to 16 bit decoder The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules SP_CSROdefines peripheral chip select signals 0 to SP CSRtde
164. igured as input or output SCK SCK is configured as input if an External clock is selected USCLKS 1 1 SCK is driven as output if the External Clock is disabled USCLKS 1 0 and Clock output is enabled CLKO 1 TXD Transmit Serial Data is an output RXD Receive Serial Data is an input Notes 1 After a hardware reset the USART clock is disabled by default The user must configure the Power Management Controller before any access to the User Interface of the USART 2 After a hardware reset the USART pins are deselected by default see Section 16 Parallel Controller on page 112 The user must configure the PIO Controller before enabling the transmitter or receiver If the user selects one of the internal clocks SCK can be configured as a PIO A MEL 133 1745D ATARM 04 Nov 05 AMEL 18 2 Baud Rate Generator The Baud Rate Generator provides the bit period clock the Baud Rate clock to both the Receiver and the Transmitter The Baud Rate Generator can select between external and internal clock sources The exter nal clock source is SCK The internal clock sources can be either the master clock MCK or the master clock divided by 8 8 Note In all cases if an external clock is used the duration of each of its levels must be longer than the system clock MCK period The external clock frequency must be at least 2 5 times lower than the system clock When the USART is programmed to
165. ing the second half of the clock cycle The first half of the clock cycle allows time to ensure completion of the previous access as well as the output of address and NCS before the read cycle begins During a standard read protocol external memory access NCS is set low and ADDR is valid at the beginning of the access while NRD goes low only in the second half of the master clock cycle to avoid bus conflict see Figure 11 7 NWE is the same in both protocols NWE always goes low in the second half of the master clock cycle see Figure 11 8 Figure 11 7 Standard Read Protocol MCK NCS N K NRD 4 or NWE 11 6 2 Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NRD at the beginning of the clock cycle In the case of successive read cycles in the same memory NRD remains active continuously Since a read cycle normally limits the speed of operation of the external memory system early read protocol can allow a faster clock frequency to be used However an extra wait state is required in some cases to avoid contentions on the external bus 30 91 55800 memm 1745D ATARM 04 Nov 05 mnr rn 1 55800 Figure 11 8 Early Read Protocol NCS N NRD or NWE 11 6 3 Early Read Wait State In early read protocol an early read wait state is automatically inserted when an external write cycle is followed by a
166. interrupt source number see Table Table 15 1 is serviced first The current priority level is defined as the priority level of the current interrupt at the time the register AIC_IVR is read the interrupt which is serviced In the case when a higher priority unmasked interrupt occurs while an interrupt already exists there are two possible outcomes depending on whether the AIC IVR has been read f the NIRQ line has been asserted but the IVR has not been read then the processor reads the new higher priority interrupt handler address in the AIC IVR register and the current interrupt level is updated e If the processor has already read the IVR then the NIRQ line is reasserted When the processor has authorized nested interrupts to occur and reads the AIC IVR again it reads the new higher priority interrupt handler address At the same time the current priority value is pushed onto a first in last out stack and the current priority is updated to the higher priority When the end of interrupt command register AIC EOICR is written the current interrupt level is updated with the last stored interrupt level from the stack if any Hence at the end of a higher priority interrupt the AIC returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted 15 3 Interrupt Handling The interrupt handler must read the as soon as possible This de asserts the NIRQ requ
167. ion When DLYBS equals zero the NPCS valid to SPCK transition is 1 2 the SPCK clock period Otherwise the following equation determines the delay NPCS to SPCK Delay DLYBS SPI Master Clock period DLYBCT Delay Between Consecutive Transfers Code Label SP DLYBCT This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select The delay is always inserted after each transfer and before removing the chip select if needed When DLYBCT equals zero a delay of four SPI Master Clock periods are inserted Otherwise the following equation determines the delay Delay After Transfer 32 DLYBCT SPI Master Clock period 26 AT91M55800A mnn amp X A 1 55800 21 ADC Analog to digital Converter The AT91M55800A features two identical 4 channel 10 bit Analog to digital converters ADC based on a Successive Approximation Register SAR approach Each ADC has 4 analog input pins AD0 to AD3 and AD4 to AD7 digital trigger input pins ADOTRIG AD1TRIG and provides an interrupt signal to the AIC Both ADCs share the analog power supply pins VDDA and GNDA and the input reference voltage pin ADVREF Figure 21 1 Block Diagram ADOTRIG ADIRQO AD1 ADCO Analog to digital Converter ADVREF Advanced Peripheral Bus GNDA gm AD4 AD5 ADC 1 dim l AD6 Analog to digital Converter AD1TRIG ADIRQ1 Tabl
168. is enabled TIMEV Time Event Interrupt Enable Code Label RTC TIMEV 0 No effect 1 The selected time event interrupt is enabled CALEV Calendar Event Interrupt Enable Code Label RTC CALEV 0 No effect 1 The selected calendar event interrupt is enabled ATMEL 1745D ATARM 04 Nov 05 AMEL 13 3 10 RTC Interrupt Disable Register Register Name RTC IDR Access Type Write only Offset 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALARM ACKUPD ACKUPD Acknowledge Update Interrupt Disable Code Label RTC ACKUPD 0 No effect 1 2 The acknowledge for update interrupt is disabled ALARM Alarm Interrupt Disable Code Label RTC ALARM 0 No effect 1 The alarm interrupt is disabled SEC Second Event Interrupt Disable Code Label RTC SEC 0 No effect 1 The second periodic interrupt is disabled TIMEV Time Event Interrupt Disable Code Label RTC TIMEV 0 No effect 1 The selected time event interrupt is disabled e CALEV Calendar Event Interrupt Disable Code Label RTC CALEV 0 No effect 1 The selected calendar event interrupt is disabled 86 91 55800 memm 1 55800 13 3 11 RTC Interrupt Mask Register Register Name RTC IMR Access Type Read only Reset State 0 0 Offset 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1
169. ithout processor intervention One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and of the SPI Most importantly the PDC removes the processor interrupt handling overhead and signifi cantly reduces the number of clock cycles required for a data transfer It can transfer up to 64K contiguous bytes As a result the performance of the microcontroller is increased and the power consumption reduced 5 2 1 System Peripherals The External Bus Interface EBI controls the external memory and peripheral devices via an 8 or 16 bit data bus and is programmed through the APB Each chip select line has its own programming register The Advanced Power Management Controller APMC optimizes power consumption of the product by controlling the clocking elements such as the oscillators and the PLL system and user peripheral clocks and the power supplies The Advanced Interrupt Controller AIC controls the internal interrupt sources from the inter nal peripherals and the eight external interrupt lines including the FIQ to provide an interrupt and or fast interrupt request to the ARM7TDMI It integrates an 8 level priority controller and using the Auto vectoring feature reduces the interrupt latency time 10 AT91M55800A memm mF 91 55800 The Real time Clock RTC peripheral is designed for very low power consumption and com bines a complete time of day clock with alarm and a two hundred
170. le Overrun Error Interrupt Code Label US_OVRE 0 No effect 1 Disables Overrun Error Interrupt FRAME Disable Framing Error Interrupt Code Label US_FRAME 0 No effect 1 Disables Framing Error Interrupt PARE Disable Parity Error Interrupt Code Label US PARE 0 No effect 1 Disables Parity Error Interrupt TIMEOUT Disable Time out Interrupt Code Label US_ TIMEOUT 0 No effect 1 Disables Receiver Time out Interrupt TXEMPTY Disable TXEMPTY Interrupt Code Label 05 TXEMPTY 0 No effect 1 Disables TXEMPTY Interrupt mnnn 91 55800 18 10 5 USART Interrupt Mask Register Name US IMR Access Type Read only Reset Value Offset 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TMEOUT 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY RXRDY Interrupt Mask Code Label US RXRDY 0 RXRDY Interrupt is Disabled 1 RXRDY Interrupt is Enabled TXRDY TXRDY Interrupt Mask Code Label US TXRDY 0 TXRDY Interrupt is Disabled 1 TXRDY Interrupt is Enabled RXBRK Receiver Break Interrupt Mask Code Label US_RXBRK 0 Receiver Break Interrupt is Disabled 1 Receiver Break Interrupt is Enabled ENDRX End of Receive Transfer Interrupt Mask Code Label 08 ENDRX 0 End of Receive Transfer Interrupt is Disabled 1 End of Receive Transfer Interrupt is Enabled ENDTX End of Transmit Transfer Interru
171. lect Registers See Table 20 1 In master mode the peripheral selection can be defined in two different ways Fixed Peripheral Select SPI exchanges data with only one peripheral Variable Peripheral Select Data can be exchanged with more than one peripheral Figures 20 1 and 20 2 show the operation of the SPI in Master Mode For details concerning the flag and control bits in these diagrams see the tables in the Programmer s Model starting on page 193 20 2 1 Fixed Peripheral Select This mode is ideal for transferring memory blocks without the extra overhead in the transmit data register to determine the peripheral Fixed Peripheral Select is activated by setting bit PS to zero in MR Mode Register The peripheral is defined by the PCS field also in MR This option is only available when the SPI is programmed in master mode 186 AT91M55800A m Yu 1745D ATARM 04 Nov 05 X 1 55800 20 2 2 Variable Peripheral Select 20 2 3 Chip Selects Variable Peripheral Select is activated by setting bit PS to one The PCS field in SP TDR Transmit Data Register is used to select the destination peripheral The data transfer charac teristics are changed when the selected peripheral changes according to the associated chip select register The PCS field in the MR has no effect This option is only available when the SPI is programmed in master mode The Chip Selec
172. less than or equal to six six SPI Master Clock periods will be inserted by default Otherwise the following equation determines the delay Delay Between Chip Selects DLYBCS SPI Master Clock period 196 AT91M55800A mwww um r 1745D ATARM 04 Nov 05 mr n 1 55800 20 7 3 SPI Receive Data Register Register Name SP_RDR Access Type Read only Reset State 0 Offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Caoa C S 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RD Receive Data Code Label SP RD Data received by the SPI Interface is stored in this register right justified Unused bits read zero PCS Peripheral Chip Select Status In Master Mode only these bits indicate the value on the NPCS pins at the end of a transfer Otherwise these bits read Zero J ATMEL 1745D ATARM 04 Nov 05 AMEL 20 7 4 SPI Transmit Data Register Register Name SP_TDR Access Type Write only Offset 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 P PCS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TD Transmit Data Code Label sP TD Data which is to be transmitted by the SPI Interface is stored in this register Information to be transmitted must be written to the transmit data register in a right justified format PCS Peripheral Chip Select This field is only used if Variable Peripheral Select is active PS 1 and if the SPI is in Master Mode If PCSDEC 0
173. lines are multiplexed with an I O signal of a peripheral After reset the pin is con trolled by the PIO Controller and is in input mode When a peripheral signal is not used in an application the corresponding pin can be used as a parallel I O Each parallel I O line is bi directional whether the peripheral defines the signal as input or output Figure 16 1 shows the multiplexing of the peripheral signals with Parallel I O signals If a pin is multiplexed between the PIO Controller and a peripheral the pin is controlled by the registers PIO PER PIO Enable and PIO PDR PIO Disable The register PIO PSR PIO Status indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller If a pin is a general multi purpose parallel I O pin not multiplexed with a peripheral PER and PDR have no effect PSR returns 1 for the bits corresponding to these pins When the PIO is selected the peripheral input line is connected to zero 16 2 Output Selection 16 3 WO Levels 16 4 Filters The user can enable each individual I O signal as an output with the registers OER Out put Enable and Output Disable The output status of the I O signals can be read in the register OSR Output Status The direction defined has effect only if the pin is con figured to be controlled by the PIO Controller Each pin can be configured to be driven high or low The level is d
174. lue 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p22 21 15 14 13 12 11 10 9 8 p mmu e Po P j Po j P P 7 6 5 4 3 2 1 0 Pa P om P J P This register shows the output data status which is programmed in PIO_SODR or PIO_CODR The defined value is effec tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output 1 The output data for the corresponding line is programmed to 1 0 The output data for the corresponding line is programmed to 0 AMEL 1745D ATARM 04 Nov 05 AMEL 16 9 13 PIO Pin Data Status Register Register Name PIO PDSR Access Type Read only Offset Ox3C Reset Value Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22 P21 15 14 13 12 11 10 9 8 Pis P Pts Pt P Po P P 7 6 5 4 3 2 1 0 Pa P P P J P This register shows the state of the physical pin of the chip The pin values are always valid regardless of whether the pins are enabled as PIO peripheral input or output The register reads as follows 1 The corresponding pin is at logic 1 0 The corresponding pin is at logic 0 16 9 14 Interrupt Enable Register Register Name PIO_IER Access Type Write only Offset 0x40 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22 21 15 14 13 12 11 10 9 8 Pa a Pu j P j P 7 6 5 4 3 2 1 0 LD e e Ps P P P j Pm This register is
175. n case of an Abort see the ARM7TDMI datasheet for further information Figure 11 1 External Memory Smaller than Page Size Hi 1 Mbyte Device Low Hi 1 Mbyte Device Low Low Hi ow 4 Base 4M Byte Repeat 3 4 Base Byte Repeat 2 Memory lt N Base 2M Byte Map Repeat 1 1 Mbyte Device 1 Mbyte Device i lt L Base 1M Byte lt Base ATMEL gt 11 2 EBI Pin Description 26 AMEL Name Description Type AO A23 Address bus output Output DO D15 Data bus input output 50 NCS7 Active low chip selects output Output NRD Read Enable output Output NWRO NWR1 Lower and upper write enable output Output NOE Output enable output Output NWE Write enable output Output NUB NLB Upper and lower byte select output Output NWAIT Wait request input Input The following table shows how certain EBI signals are multiplexed Multiplexed Signals Functions A0 NLB 8 or 16 bit data bus NRD NOE Byte write or byte select access NWRO NWE Byte write or byte select access NWR1 NUB Byte write or byte select access AT91M55800A m 1745D ATARM 04 Nov 05 mF A191 55800A 11 3 Data Bus Width A data bus width of 8 or 16 bits can be selected for each chip select This option is controlled by the DBW field in the Chip select Register for the c
176. nal Interrupt 1 Input 0 PIO Input 78 11 PA11 IRQ2 External Interrupt 2 Input 0 PIO Input 79 12 PA12 IRQ3 External Interrupt 3 Input 0 PIO Input 80 13 PA13 FIQ Fast Interrupt Input 0 PIO Input 81 14 PA14 SCKO USART 0 Clock signal Bi directional 0 PIO Input 82 15 PA15 TXDO USART 0 transmit data Output PIO Input 83 16 PA16 RXDO USART 0 receive data Input 0 PIO Input 84 17 PA17 SCK1 USART 1 Clock signal Bi directional 0 PIO Input 85 18 PA18 TXD1 USART 1 transmit data Output PIO Input 86 19 PA19 RXD1 USART 1 receive data Input 0 PIO Input 91 20 PA20 SCK2 USART 2 Clock signal Bi directional 0 PIO Input 92 21 PA21 TXD2 USART 2 transmit data Output PIO Input 93 22 PA22 RXD2 USART 2 receive data Input 0 PIO Input 94 23 PA23 SPCK SPI Clock signal Bi directional 0 PIO Input 95 24 PA24 MISO SPI Master In Slave Out Bi directional 0 PIO Input 96 25 PA25 MOSI SPI Master Out Slave In Bi directional 0 PIO Input 97 26 PA26 NPCSO SPI Peripheral Chip Select 0 Bi directional 1 PIO Input 98 27 PA27 NPCS1 SPI Peripheral Chip Select 1 Output PIO Input 99 28 PA28 NPCS2 SPI Peripheral Chip Select 2 Output PIO Input 100 29 PA29 NPCS3 SPI Peripheral Chip Select 3 Output PIO Input 101 30 31 Note 1 The OFF value is the default level seen on the peripheral input when the PIO line is enabled A MEL 115 1745D ATARM 04 Nov 05 AMEL
177. nd to restore the context of the AIC This operation is generally not performed by the debug system Hence the debug system would become strongly intrusive and could cause the application to enter an undesired state This is avoided by using Protect Mode The Protect Mode is enabled by setting the AIC bit in the SF Protect Mode Register When Protect Mode is enabled the AIC performs interrupt stacking only when a write access is performed on the AIC IVR Therefore the Interrupt Service Routines must write arbitrary data to the IVR just after reading it The new context of the AIC including the value of the Interrupt Status Register AIC ISR is updated with the current interrupt only when IVR is written An AIC read on its own e g by a debugger modifies neither the AIC context nor the AIC ISR Extra reads performed in between the read and the write can cause unpredictable results Therefore it is strongly recommended not to set a breakpoint between these 2 actions nor to stop the software The debug system must not write to the as this would cause undesirable effects AMEL s The following table shows the main steps of an interrupt and the order in which they are per AMEL formed according to the mode Action Normal Mode Protect Mode Calculate active interrupt f Read AIC_IVR Read AIC_IVR higher than current or spurious Determine and return the vect
178. ng is not delayed The second data sampling is correct Figure 27 3 Number of Standard Wait States is One Second Data Sampling Correct First Data Sampling 4 Erroneous 4 1 2 1 20 101 20 2 32 bit Access Two 16 bit Accesses Each Access Length One Wait State Assertion for One More Cycle Note 1 These numbers refer to the standard access cycles mnnn 1 55800 If the first two conditions are not met during write accesses the NWE signal is not affected by the NWAIT assertion The following example illustrates the number of standard wait states NWAIT is not asserted during the first cycle but is asserted at the second and last cycle of the standard access The access is correctly delayed as the NCS line rises accordingly to the NWAIT assertion However the NWE signal waveform is unchanged and rises too early Figure 27 4 Description of the Number of Standard Wait States I Erroneous NWE Rising NWE 1 gt Access Length One Wait State Assertion of the NWAIT for One More Cycle 27 Unpredictable Result in APMC State Machine on Switch from Oscillator to PLL An automatic switch from the main oscillator output CSS 1 may cause an unpredictable result in the APMC state machine The automatic PLL to PLL transition is also effected by this problem Problem Fix Work
179. nly Offset 0x14 CH Channel Disable Code Label ADC_CHx 0 No effect 1 Disables the corresponding channel mms rm 1 55800 21 0 10 ADC Channel Status Register Register Name ADC CHSR Access Type Read only Reset State 0 Offset 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ce ce cm CH Channel Status Code Label CHx 0 Corresponding channel is disabled 1 Corresponding channel is enabled 21 0 11 Status Register Register Name ADC SR Access Type Read only Reset State 0 Offset 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 5 OVRE2 OVRE OVREO 7 6 5 4 3 2 1 0 _ Eso EOCO EOC End of Conversion Code Label 0 Corresponding analog channel is disabled or the conversion is not finished 1 Corresponding analog channel is enabled and conversion is complete OVRE Enable Overrun Error Interrupt Code Label ADC OVREx 0 No overrun on the corresponding channel since the last read of SR 1 There has been an overrun on the corresponding channel since the last read of SR AMEL 1745D ATARM 04 Nov 05 AMEL 21 0 12 ADC Interrupt Enable Register Register Name ADC_IER Access Type Write only Offset 0x24 31 30 24 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 _
180. nterrupt Mode Fault Error Interrupt Enable Code Label SP 0 No effect 1 Enables the Mode Fault Interrupt OVRES Overrun Error Interrupt Enable Code Label SP_OVRES 0 No effect 1 Enables the Overrun Error Interrupt SPENDRX End of Receiver Transfer Interrupt Enable Code Label SP_ENDRX 0 No effect 1 Enables the End of Receiver Transfer Interrupt SPENDTX End of Transmitter Transfer Interrupt Enable Code Label SP_ENDTX 0 No effect 1 Enables the End of Transmitter Transfer Interrupt 20 91 55800 cm mnr A 1 55800 20 7 7 SPI Interrupt Disable Register Register Name SP_IDR Access Type Write only Offset 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPENDTX SPENDRX OVRES MODF TDRE RDRF Receive Data Register Full Interrupt Disable Code Label SP RDRF 0 No effect 1 Disables the Receiver Data Register Full Interrupt TDRE Transmit Data Register Empty Interrupt Disable Code Label SP_TDRE 0 No effect 1 Disables the Transmit Data Register Empty Interrupt Mode Fault Interrupt Disable Code Label SP MODF 0 No effect 1 Disables the Mode Fault Interrupt OVRES Overrun Error Interrupt Disable Code Label SP_OVRES 0 No effect 1 Disables the Overrun Error Interrupt SPENDRX End of Receiver Transfer Interrupt Disable Code Label SP
181. of functions including frequency measurement event counting interval measurement pulse generation delay timing and pulse width modulation The Timer Counters can be used in Capture or Waveform mode and all three counter chan nels can be started simultaneously and chained together SPI Serial Peripheral Interface The SPI provides communication with external devices in master or slave mode It has four external chip selects that can be connected to up to 15 devices The data length is program mable from 8 to 16 bit ADC Analog to digital Converter The two identical 4 channel 10 bit analog to digital converters ADC are based on a Succes sive Approximation Register SAR approach Each ADC has 4 analog input pins ADO to AD3 and AD4 07 digital trigger input pins ADOTRIG and AD1TRIG and provides an interrupt signal to the AIC Both ADCs share the analog power supply pins VDDA and GNDA and the input reference voltage pin ADVREF 91 55800 ma mmn n 91 55800 Each channel can be enabled or disabled independently and has its own data register The ADC can be configured to automatically enter Sleep mode a conversion sequence and can be triggered by the software the Timer Counter or an external signal 8 5 5 DAC Digital to analog Converter Each DAC has an analog output pin DA0 and DA1 and provides an interrupt signal to the AIC DAOIRQ and DA1IRQ Both DACs share the analog power supply pins VDD
182. or of the Read AIC_IVR Read AIC_IVR active interrupt Memorize interrupt Read AIC_IVR Read AIC IVR on internal stack the current priority Read AIC IVR Write AIC IVR Acknowledge the interrupt Read AIC_IVR Write AIC_IVR No effect Write IVR Notes 1 NIRQ de assertion and automatic interrupt clearing if the source is programmed as level sensitive 2 Note that software which has been written and debugged using Protect Mode will run cor rectly in Normal Mode without modification However in Normal Mode the AIC write has no effect and can be removed to optimize the code 10 91 55800 mmm mmn 91 55800 15 10 AIC User Interface Base Address OxFFFFFO000 Code Label AIC BASE Table 15 2 Memory Offset Register Name Access Reset State 0 000 Source Mode Register 0 AIC SMRO Read Write 0 0x004 Source Mode Register 1 AIC SMR1 Read Write 0 Read Write 0 0x07C Source Mode Register 31 AIC SMR31 Read Write 0 0x080 Source Vector Register 0 SVRO Read Write 0 0x084 Source Vector Register 1 AIC SVR1 Read Write 0 Read Write 0 OxOFC Source Vector Register 31 AIC SVR81 Read Write 0 0x100 IRQ Vector Register AIC_IVR Read only 0 0x104 FIQ Vector Register AIC_FVR Read only 0 0x108 Interrupt Status Register AIC_ISR Read only 0 0x10C Interrupt Pending Register AIC_IPR Read only see Note 0x110 Interrupt Mask Register AIC_IMR Read only 0 0x11
183. orresponding chip select Figure 11 2 shows how to connect a 512K x 8 bit memory on NCS2 Figure 11 2 Memory Connection for an 8 bit Data Bus 0 Write Enable Output Enable Memory Enable Figure 11 3 shows how to connect a 512K x 16 bit memory on NCS2 Figure 11 3 Memory Connection for a 16 bit Data Bus DO D7 08 015 A18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable 11 4 Byte write Byte select Access Each chip select with a 16 bit data bus can operate with one of two different types of write access Byte write Access supports two Byte write and a single read signal Byte select Access selects upper and or lower byte with two byte select lines and separate read and write signals This option is controlled by the BAT field in the Chip select Register for the corre sponding chip select Byte write Access is used to connect 2 x 8 bit devices as a 16 bit memory page The signal AO NLB is not used The signal NWR1 NUB is used as NWR1 and enables upper byte writes The signal NWRO NWE is used as NWRO and enables lower byte writes e The signal NRD NOE is used as NRD and enables half word and byte reads Figure 11 4 shows how to connect two 512K x 8 bit devices in parallel on NCS2 AMEL 1745D ATARM 04 Nov 05 AMEL Figure 11 4 Memory Connection for 2 x 8 bit Data Busses Write Enable Read
184. ot updated If the NRST is asserted and the watchdog trig gers the internal reset the NRST pin has priority 7 5 Emulation Functions 7 5 1 Tri state Mode The AT91M55800A provides a Tri state Mode which is used for debug purposes This enables the connection of an emulator probe to an application board without having to desol der the device from the target board In Tri state Mode all the output pin drivers of the AT91M55800A microcontroller are disabled To enter Tri state Mode the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST For normal operation the pin NTRI must be held high during reset by a resistor of up to 400K Ohm NTRI is multiplexed with I O line PA18 and USART 1 serial data transmit line TXD1 Standard RS232 drivers generally contain internal 400K Ohm pull up resistors If TXD1 is con nected to a device not including this pull up the user must make sure that a high level is tied on NTRI while NRST is asserted 7 5 2 JTAG ICE Debug Mode ARM Standard Embedded In Circuit Emulation is supported via the JTAG ICE port It is con nected to a host computer via an external ICE Interface The JTAG ICE debug mode is enabled when JTAGSEL is low In ICE Debug Mode the ARM Core responds with a non JTAG chip ID which identifies the core to the ICE system This is not JTAG compliant 7 5 3 IEEE 1149 1 JTAG Boundary scan JTAG Boundary scan is enabled when JTAGSEL is high The function
185. ounter Overflow Code Label TC covFs 0 The Counter Overflow Interrupt is disabled 1 The Counter Overflow Interrupt is enabled LOVRS Load Overrun Code Label Tc_LOvRS 0 The Load Overrun Interrupt is disabled 1 The Load Overrun Interrupt is enabled CPAS RA Compare Code Label TC CPAS 0 RA Compare Interrupt is disabled 1 The RA Compare Interrupt is enabled CPBS RB Compare Code Label CPBS 0 The RB Compare Interrupt is disabled 1 The RB Compare Interrupt is enabled CPCS RC Compare Code Label TC CPCS 0 2 The RC Compare Interrupt is disabled 1 The RC Compare Interrupt is enabled LDRAS RA Loading Code Label TC LDRAS 0 The Load RA Interrupt is disabled 1 The Load RA Interrupt is enabled LDRBS RB Loading Code Label TC LDRBS 0 The Load RB Interrupt is disabled 1 The Load RB Interrupt is enabled ETRGS External Trigger Code Label TC ETRGS 0 The External Trigger Interrupt is disabled 1 The External Trigger Interrupt is enabled mms nrwr rY 55800 20 SPI Serial Peripheral Interface 20 1 Pin Description 1745D ATARM 04 Nov 05 The AT91M55800A includes an SPI which provides communication with external devices in master or slave mode The SPI has four external chip selects which can be connected to up to 15 devices The data length is programmable from 8 to 16 bit As for the USART a 2 channel PDC can be used to move data between memor
186. ow and high pulse duration must strictly be longer than two system clock MCK periods 20 6 Peripheral Data Controller 192 The SPI is closely connected to two Peripheral Data Controller channels One is dedicated to the receiver The other is dedicated to the transmitter The PDC channel is programmed using SP TPR Transmit Pointer and SP TCR Transmit Counter for the transmitter and RPR Receive Pointer and RCR Receive Counter for the receiver The status of the PDC is given in SR by the SPENDTX bit for the trans mitter and by the SPENDRX bit for the receiver The pointer registers SP TPR and SP are used to store the address of the transmit or receive buffers The counter registers SP TCR and SP are used to store the size of these buffers The receiver data transfer is triggered by the RDRF bit and the transmitter data transfer is trig gered by TDRE When a transfer is performed the counter is decremented and the pointer is incremented When the counter reaches 0 the status bit is set SPENDRX for the receiver for the transmitter in SR and can be programmed to generate an interrupt While the counter is at zero the status bit is asserted and transfers are disabled 91 55800 memme 1745D ATARM 04 Nov 05 1 55800 20 7 SPI Programmer s Model SPI Base Address OxFFFBCOOO0 Code Label SPI BASE Table 20 1 SPI Memor
187. pt Mask Code Label 05 ENDTX 0 End of Transmit Transfer Interrupt is Disabled 1 End of Transmit Transfer Interrupt is Enabled OVRE Overrun Error Interrupt Mask Code Label US OVRE 0 Overrun Error Interrupt is Disabled 1 Overrun Error Interrupt is Enabled FRAME Framing Error Interrupt Mask Code Label US_FRAME 0 Framing Error Interrupt is Disabled 1 Framing Error Interrupt is Enabled PARE Parity Error Interrupt Mask Code Label US PARE 0 Parity Error Interrupt is Disabled 1 Parity Error Interrupt is Enabled TIMEOUT Time out Interrupt Mask Code Label US_TIMEOUT 0 Receive Time out Interrupt is Disabled 1 Receive Time out Interrupt is Enabled TXEMPTY TXEMPTY Interrupt Mask Code Label US_TXEMPTY 0 TXEMPTY Interrupt is Disabled 1 TXEMPTY Interrupt is Enabled A MEL 149 1745D ATARM 04 Nov 05 AMEL 18 10 6 USART Channel Status Register Name US_CSR Access Type Read only Reset 0x18 Offset 0x14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ITXMPYY TMEOUT 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY Receiver Ready Code Label US RXRDY 0 No complete character has been received since the last read of the 05 or the receiver is disabled 1 At least one complete character has been received and the US has not yet been read TXRDY Transmitter Ready Code Label 08 TXRDY 0 US
188. pt Vector Handler Address The user may store the address of the Spurious Interrupt handler in this register ATMEL 9 1745D ATARM 04 Nov 05 AMEL 15 11 Standard Interrupt Sequence It is assumed that The Advanced Interrupt Controller has been programmed AIC SVR are loaded with corresponding interrupt service routine addresses and interrupts are enabled The Instruction at address 0x18 IRQ exception vector address is ldr pc amp F20 When NIRQ is asserted if the bit of CPSR is 0 the sequence is 1 The CPSR is stored SPSR the current value of the Program Counter is loaded in the IRQ link register r14_irq and the Program Counter r15 is loaded with 0x18 In the following cycle during fetch at address Ox1C the ARM Core adjusts r14 decrementing it by 4 The ARM Core enters IRQ mode if it is not already When the instruction loaded at address 0x18 is executed the Program Counter is loaded with the value read AIC IVR Reading the IVR has the following effects Setthe current interrupt to be the pending one with the highest priority The current level is the priority level of the current interrupt De assert the NIRQ line on the processor Even if vectoring is not used AIC IVR must be read in order to de assert NIRQ Automatically clear the interrupt if it has been programmed to be edge triggered Push the current level on to the stack
189. r a reset the ADC operates in 10 bit mode If the bit RES in MR is set the 8 bit mode is selected When operating in 10 bit mode the field DATA in CDR is fully significant When operating in 8 bit mode only the 8 lowest bits of DATA are significant and the 2 highest bits read O Conversion Triggers Sleep Mode Conversions of the active analog channels are started with a software or a hardware trigger The software trigger is provided by writing the bit START in the Control Register CR The hardware trigger can be one of the TIOA outputs of the Timer Counter channels or the external trigger input of the ADC ADOTRIG for the ADCO or AD1TRIG for ADC1 The hard ware trigger is selected with the field TRGSEL in the Mode Register MR The selected hardware trigger is enabled with the bit TRGEN in the Mode Register If a hardware trigger is selected the start of a conversion is detected at each rising edge of the selected signal If one of the TIOA outputs is selected the corresponding Timer Counter chan nel must be programmed in Waveform Mode Only one start command is necessary to initiate a conversion sequence on all the channels The ADC hardware logic automatically performs the conversions on the active channels then waits for a new request The Channel Enable CHER and Channel Disable ADC_CHDR Registers enable the analog channels to be enabled or disabled independently The
190. r clock is disabled when RB loading occurs 172 AT91M55800A maa 1745D ATARM 04 Nov 05 mmn 1 55800 ETRGEDG External Trigger Edge Selection ETRGEDG Edge Code Label TC ETRGEDG 0 0 None TC ETRGEDG EDGE NONE 0 1 Rising edge TC ETRGEDG RISING EDGE 1 0 Falling edge TC ETRGEDG FALLING EDGE 1 1 Each edge TC ETRGEDG BOTH EDGE ABETRG TIOA or TIOB External Trigger Selection ABETRG Selected ABETRG Code Label TC ABETRG 0 TIOB is used as an external trigger TC ABETRG TIOB 1 TIOA is used as an external trigger TC ABETRG TIOA CPCTRG RC Compare Trigger Enable Code Label TC CPCTRG 0 RC Compare has no effect on the counter and its clock 1 RC Compare resets the counter and starts the counter clock WAVE 0 Code Label TC WAVE 0 Capture Mode is enabled 1 Capture Mode is disabled Waveform Mode is enabled LDRA RA Loading Selection LDRA Edge Code Label TC LDRA 0 0 None TC LDRA EDGE NONE 0 1 Rising edge of TIOA TC LDRA RISING EDGE Falling edge of TIOA TC DRA FALLING Each edge of TIOA LDRB RB Loading Selection TC L DRA BOTH EDGE LDRB Edge Code Label TC LDRB 0 0 None TC LDRB EDGE NONE 0 1 Rising edge of TIOA TC LDRB RISING EDGE Falling edge of TIOA TC LDRB FALLING EDGE Each edge of TIOA TC LDRB BOTH EDGE 1745D
191. rd write accesses require at least two standard wait states The following waveforms further explain the issue If the NWAIT setup time is satisfied on the first rising edge of MCKI the behavior is accurate The EBI operations are not affected when the NWAIT rises Figure 27 1 NWAIT Rising NWAIT I l NWAIT Setup before MCKI Rising EBls If the NWAIT setup time is satisfied on the following edges of MCKI and if at least one stan dard wait state remains to be executed the behavior is accurate In the following example the number of standard wait states is two The NWAIT setup time on the second rising edge of MCKI must be met A MEL 241 1745D ATARM 04 Nov 05 AMEL Figure 27 2 Number of Standard Wait States is Two MCKI I I I NWAIT lt NCS 10 201 3 1 P Standard Access Length with Two Wait States Note 1 These numbers refer to the standard access cycles If the first two conditions are not met during a 32 bit read access the first 16 bit data is read at the end of the standard 16 bit read access In the following example the number of standard waits is one NWAIT assertions do affect both NRD pulse lengths but first data sampli
192. reak condition on the TXD line the STPBRK command in US_CR must be set The USART completes a minimum break duration of one character length The TXD line then returns to high level idle state for at least 12 bit periods to ensure that the end of break is cor rectly detected Then the transmitter resumes normal operation The BREAK is managed like a character The STTBRK and the STPBRK commands are performed only if the transmitter is ready bit TXRDY 1 in US CSR The STTBRK command blocks the transmitter holding register bit TXRDY is cleared in US until the break has started A break is started when the Shift Register is empty any previous character is fully transmitted US CSR TXEMPTY is cleared The break blocks the transmitter shift register until it is completed high level for at least 12 bit periods after the STPBRK command is requested In order to avoid unpredictable states STTBRK and STPBRK commands must not be requested at the same time Once an STTBRK command is requested further STTBRK commands are ignored until the BREAK is ended high level for at least 12 bit periods All STPBRK commands requested without a previous STTBRK command are ignored A byte written into the Transmit Holding Register while a break is pending but not started bit TXRDY 0 in US is ignored It is not permitted to write new data the Transmit Holding Register while a break is in progress STPBRK has not
193. responding channel as mentioned in Table 19 2 Table 19 3 TC Channel Memory Map Offset Register Name Access Reset State 0x00 Channel Control Register TC CCR Write only 0 04 Channel Mode Register TC CMR Read Write 0 0x08 Reserved 0x0C Reserved 0x10 Counter Value TC_CV Read Write 0 0x14 Register A TC_RA Read Write 0 0x18 Register B TC_RB Read Write 0 0 1 Register C TC RC Read Write 0 0x20 Status Register TC SR Read only 0 24 Interrupt Enable Register TC IER Write only 0 28 Interrupt Disable Register TC IDR Write only 0 2 Interrupt Mask Register TC IMR Read only 0 Note 1 Read only if WAVE 0 188 91 55800 mu 1745D ATARM 04 Nov 05 9 91 55800 19 5 1 TC Block Control Register Register Name TC BCR Access Type Write only Offset OxCO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SYNC Synchro Command Code Label TC SYNC 0 No effect 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels A MEL 169 1745D ATARM 04 Nov 05 AMEL 19 5 2 TC Block Mode Register Register Name TC_BMR Access Type Read Write Reset State 0 Offset OxC4 3 1 30 29 28 27 26 25 24 i dE 23 22 21 20 19 18 17 16 deco Cs Cb s j 15 14 13 12 11 10 9 8 Ea e ere pce 7 6 5 4 3 2 1 0 exes
194. responding chip select The value 0 7 clock cycles AMEL s 1745D ATARM 04 Nov 05 AMEL indicates the number of data float waits to be inserted and represents the time allowed for the data output to go high impedance after the memory is disabled Data float wait states do not delay internal memory accesses Hence a single access to an external memory with long tpe will not slow down the execution of a program from internal memory The EBI keeps track of the programmed external data float time during internal accesses to ensure that the external memory system is not accessed while it is still busy Internal memory accesses and consecutive accesses to the same external memory do not have added Data Float wait states Figure 11 12 Data Float Output Time NCS N ND gt Notes 1 Early Read Protocol 2 Standard Read Protocol 11 8 3 External Wait The NWAIT input can be used to add wait states at any time NWAIT is active low and is detected on the rising edge of the clock If NWAIT is low at the rising edge of the clock the EBI adds a wait state and changes neither the output signals nor its internal counters and state When NWAIT is de asserted the EBI fin ishes the access sequence The NWAIT signal must meet setup and hold requirements on the rising edge of the clock 1745D ATARM 04 Nov 05 1 55800 Figure 11 13 External Wait
195. riod is detected as a valid start bit A space which is 7 16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit When a valid start bit has been detected the receiver samples the RXD at the theoretical mid point of each bit It is assumed that each bit lasts 16 cycles of the sampling clock one bit period so the sampling point is 8 cycles 0 5 bit periods after the start of the bit The first sampling point is therefore 24 cycles 1 5 bit periods after the falling edge of the start bit was detected Each subsequent bit is sampled 16 cycles 1 bit period after the previous one Figure 18 3 Asynchronous Mode Start Bit Detection aes RXD 111 True Start DO Detection Sampling Figure 18 4 Asynchronous Mode Character Reception Example 8 bit parity enabled 1 stop 0 5 bit 1 bit periods period RXD Sampling i D0 D1 D2 D3 D4 D5 D6 D7 i Stop Bit True Start Detection Parity Bit A MEL 135 1745D ATARM 04 Nov 05 18 3 2 18 3 3 18 3 4 18 3 5 18 3 6 136 AMEL Synchronous Receiver When configured for synchronous operation SYNC 1 the receiver samples the RXD signal on each rising edge of the Baud Rate clock If a low level is detected it is considered as a start Data bits parity bit and stop bit are sampled and the receiver waits for the next start bit See example in Figure 18 5
196. rogrammed must be even to ensure a 50 50 mark space ratio 2 Clock divisor bypass CD 1 must not be used when internal clock MCK is selected USCLKS 0 AIMEL 1745D ATARM 04 Nov 05 AMEL 18 10 10 USART Receiver Time out Register Name US_RTOR Access Type Read Write Reset State 0 Offset 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TO 9 3 o A 5 When value is written to this register Start Time out Command is automatically performed TO 0 Disables the RX Time out function 1 255 The Time out counter is loaded with TO when the Start Time out Command is given or when each new data character is received after reception has started Time out duration TO x 4 x Bit period 18 10 11 USART Transmitter Time guard Register Name US TTGR Access Type Read Write Reset State 0 Offset 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 N A o TG TG Time guard Value 0 Disables the TX Time guard function 1 255 TXD is inactive high after the transmission of each character for the time guard duration Time guard duration TG x Bit period 1745D ATARM 04 Nov 05 X 91 55800 18 10 12 USART Receive Pointer Register Name US RPR Access Type Read Write Reset S
197. rrun Error Interrupt is disabled 1 Overrun Error Interrupt is enabled 21 0 15 ADC Convert Data Register Register Name CDRO to ADC_CDR3 Access Type Read only Reset State 0 Offset 0x30 to Ox3C 31 30 29 28 27 26 25 24 A E E N E A A DATA N E o DATA DATA Converted Data The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new conver sion is completed The Convert Data Register CDR is only loaded if the corresponding analog channel is enabled DATA Selected DATA Code Label CDRx 0 or 1 10 bits Data ADC DATA 10BITS 0 or 1 8 bits Data ADC DATA 8BITS AMEL 1745D ATARM 04 Nov 05 22 DAC Digital to analog Co AMEL nverter The AT91M55800A features two identical 1 channel 10 bit Digital to analog converters DAC Each DAC has an analog output pin DAO and DA1 and provides an interrupt signal to the AIC DAOIRQ DA1IRQ Both DACs share the analog power supply pins VDDA and GNDA and the Table 22 1 input reference pin DAVREF Pin Name VDDA Meaning Analog power supply GNDA Analog ground DAVREF Reference voltage DAO Analog output channel 0 DA1 Analog output channel 1 Figure 22 1 DAC Block Diagram
198. rt or a Prefetch Abort exception to the ARM7TDMI is asserted when accessing an undefined address in the EBI address space No abort is generated when reading the internal memory or by accessing the internal peripher als whether the address is defined or not AT91M55800A memme 1745D ATARM 04 Nov 05 91 55800 7 7 External Bus Interface 1745D ATARM 04 Nov 05 The External Bus Interface handles the accesses between addresses 0x0040 0000 and OxFFCO 0000 It generates the signals that control access to the external devices and can configure up to eight 16 Mbyte banks In all cases it supports byte half word and word aligned accesses For each of these banks the user can program Number of wait states Number of data float times wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus Data bus width 8 bit or 16 bit With a 16 bit wide data bus the user can program the EBI to control one 16 bit device Byte Access Select Mode or two 8 bit devices in parallel that emulate a 16 bit memory Byte write Access mode The External Bus Interface features also the Early Read Protocol configurable for all the devices that significantly reduces access time requirements on an external device ATMEL AMEL 8 Peripherals The AT91M55800A peripherals are connected to the 32 bit wide Advanced Peripheral Bus
199. s SAMPLE EXTEST and BYPASS are implemented There is no JTAG chip ID The Special Function module pro vides a chip ID which is independent of JTAG It is not possible to switch directly between JTAG and ICE operations A chip reset must be performed NRST and NTRST after JTAGSEL is changed 7 6 Memory Controller The ARM7TDMI processor address space is 4G bytes The memory controller decodes the internal 32 bit address bus and defines three address spaces Internal memories in the four lowest megabytes Middle space reserved for the external devices memory or peripherals controlled by the EBI AMEL 1745D ATARM 04 Nov 05 7 6 1 7 6 2 7 6 3 7 6 4 16 AMEL Internal peripherals in the four highest megabytes In any of these address spaces the ARM7TDMI operates in Little Endian mode only Internal Memories The AT91M55800A microcontroller integrates an 8 Kbyte SRAM bank This memory bank is mapped at address 0x0 after the remap command allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software The rest of the bank can be used for stack allocation to speed up context saving and restoring or as data and program storage for critical algorithms All internal memory is 32 bits wide and single clock cycle accessible Byte 8 bit half word 16 bit or word 32 bit accesses are supported and are executed within one cycle Fetching Thumb or ARM instructions is supported and internal
200. s asserted since the last Reset Status Bits command FRAME Framing Error Code Label 05 FRAME 0 No stop bit has been detected low since the last Reset Status Bits command 1 At least one stop bit has been detected low since the last Reset Status Bits command PARE Parity Error Code Label US PARE 1 At least one parity bit has been detected false or a parity bit high in multi drop mode since the last Reset Status Bits command 0 No parity bit has been detected false or a parity bit high in multi drop mode since the last Reset Status Bits command 10 AT91M55800A mmm mj s sv A191 55800A TIMEOUT Receiver Time out Code Label US TIMEOUT 0 There has not been a time out since the last Start Time out command or the Time out Register is 0 1 There has been a time out since the last Start Time out command TXEMPTY Transmitter Empty Code Label 05 TXEMPTY 0 There are characters in either 05 THR or the Transmit Shift Register or a Break is being transmitted 1 There are no characters in US and the Transmit Shift Register and Break is not active Equal to zero when the USART is disabled or at reset Transmitter Enable command in 05 CR sets this bit to one A MEL 151 1745D ATARM 04 Nov 05 AMEL 18 10 7 USART Receiver Holding Register Name US_RHR Access Type Read only Reset State 0 Offset 0x18 m
201. simple RC circuit connected to the NRSTBU pin provides a power on reset signal to the RTC and the shutdown logic When the reset signal increases and as the startup time of the 32 kHz oscilla tor is around 300 ms the AT91M55800A maintains the internal backup reset signal for 32768 oscillator clock cycles in order to guarantee the backup power supplied logic does not operate before the oscillator output is stabilized Alternatively a reset supervisor can be connected to the NRSTBU pin in place of the RC The Slow Clock is the only clock considered permanent in an AT91M55800A based system and is essential in the operations of the APMC Advanced Power Management Controller In any use case a 32768 Hz crystal must be connected to the XIN32 and XOUT32 pins in order to ensure that the Slow Clock is present ATMEL s AMEL 12 3 Clock Generator 12 3 1 12 3 2 56 Main Oscillator The clock generator consists of the main oscillator the PLL and the clock selection logic with its prescaler It aims at selecting the Master Clock called MCK throughout this datasheet The clock generator also contains the circuitry needed to drive the MCKO pin with the master clock signal The Main Oscillator is designed for a 3 to 20 MHz fundamental crystal The typical crystal con nection is illustrated in Figure 12 4 The 1 KQ resistor is only required for crystals with frequencies lower than 8 MHz The oscillator contains 25 pF capacitances on each XI
202. ster is used to disable PIO control of individual pins When the PIO control is disabled the normal peripheral func tion is enabled on the corresponding pin 1 Disables PIO control enables peripheral control on the corresponding pin 0 No effect 18 AT91M55800A muwu w 91 55800 16 9 3 PIO Status Register Register Name PIO PSR Access Type Read onlyRead only Offset 0x08 Reset Value Ox3FFFFFFF A OxOFFFFFFF B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 P21 15 14 13 12 11 10 9 8 Pi Pa Ps Pa Po P re 7 6 5 4 3 2 1 0 P P P Pm P 1 This register indicates which pins are enabled for PIO control This register is updated when PIO lines are enabled or disabled 1 PIO is active on the corresponding line peripheral is inactive 0 PIO is inactive on the corresponding line peripheral is active 16 9 4 PIO Output Enable Register Register Name PIO_OER Access Type Write only Offset 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p22 15 14 13 12 11 10 9 8 Ps Pis Po P Po P P 7 6 5 4 3 2 1 0 ps Pt P P Pm P This register is used to enable PIO output drivers If the pin is driven by a peripheral this has no effect on the pin but the information is stored The register is programmed as follows 1 Enables the PIO output on the corresponding pin 0
203. supports different access protocols allowing single clock cycle memory accesses The main features are External memory mapping 8 active low chip select lines 8 or 16 bit data bus Byte write or byte select lines Remap of boot memory Two different read protocols Programmable wait state generation External wait request Programmable data float time The EBI User Interface is described on page 48 1745D ATARM 04 Nov 05 msn nv 1 55800 11 4 External Memory Mapping 1745D ATARM 04 Nov 05 The memory map associates the internal 32 bit address space with the external 24 bit address bus The memory map is defined by programming the base address and page size of the external memories see EBI User Interface registers CSRO to EBI_CSR7 Note that AO A23 is only significant for 8 bit memory A1 A23 is used for 16 bit memory If the physical memory device is smaller than the programmed page size it wraps around and appears to be repeated within the page The EBI correctly handles any valid access to the memory device within the page See Figure 11 1 In the event of an access request to an address outside any programmed page an Abort sig nal is generated Two types of Abort are possible instruction prefetch abort and data abort The corresponding exception vector addresses are respectively 0 0000 000C and 0x0000 0010 It is up to the system programmer to program the error handling routine to use i
204. t OVRE Enable Overrun Error Interrupt Code Label 08 OVRE 0 No effect 1 Enables Overrun Error Interrupt FRAME Enable Framing Error Interrupt Code Label US FRAME 0 No effect 1 Enables Framing Error Interrupt PARE Enable Parity Error Interrupt Code Label US PARE 0 No effect 1 Enables Parity Error Interrupt TIMEOUT Enable Time out Interrupt Code Label US_TIMEOUT 0 No effect 1 Enables Reception Time out Interrupt TXEMPTY Enable TXEMPTY Interrupt Code Label 05 0 No effect 1 Enables TXEMPTY Interrupt A MEL 147 1745D ATARM 04 Nov 05 AMEL 18 10 4 USART Interrupt Disable Register Name US_IDR Access Type Write only Offset 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY RXRDY Disable RXRDY Interrupt Code Label US RXRDY 0 No effect 1 Disables RXRDY Interrupt TXRDY Disable TXRDY Interrupt Code Label US TXRDY 0 No effect 1 Disables TXRDY Interrupt RXBRK Disable Receiver Break Interrupt Code Label US_RXBRK 0 No effect 1 Disables Receiver Break Interrupt ENDRX Disable End of Receive Transfer Interrupt Code Label US_ENDRX 0 No effect 1 Disables End of Receive Transfer Interrupt ENDTX Disable End of Transmit Transfer Interrupt Code Label 08 ENDTX 0 No effect 1 Disables End of Transmit Transfer Interrupt OVRE Disab
205. t k EBI External Bus Interface Interface PIOB Controller TC Timer Counter Block 0 Controller 2 PDC USARTO Channels dm USART1 2 PDC Channels M 2 PDC SPI Serial TC Timer Counter Block 1 Peripheral 2 PDC Channels Interface PIOA Controller WD Watchdog Timer Clock Generator PLL Advanced Power Management Controller RTC u Real Time Clock 4 Channel ADCO 4 Channel ADC1 Analog Battery Backup AIMEL T AT91M55800A NRST VDDIO VDDCORE GND DO D15 A1 A23 NRD NOE NWRO NWE NWR1 NUB NWAIT NCSO NCS7 PB18 BMS PB19 TCLKO PB22 TCLK1 PB25 TCLK2 PB20 TIOAO PB21 TIOBO y PB23 TIOA1 PB24 TIOB1 PB26 TIOA2 PB27 TIOB2 PA0 TCLK3 PAG TCLK5 PA1 TIOA3 PA2 TIOB3 PA4 TIOA4 5 4 P O g PA7 TIOA5 PA8 TIOB5 VDDPLL MCKO XIN 16 MHz XOUT PLLRC GNDPLL VDDBU SHDN WAKEUP NRSTBU XIN32 32 768 kHz XOUT32 GNDBU AMEL 5 Architectural Overview The AT91M55800A microcontroller integrates an ARM7TDMI with its embedded ICE inter face memories and peripherals Its architecture consists of two main buses the Advanced System Bus ASB and the Advanced Peripheral Bus APB Designed for maximum perfor mance and controlled by the memory controller the ASB interfaces the ARM7
206. t generate any signals 1 Watchdog is enabled and generates enabled signals RSTEN Reset Enable Code Label WD RSTEN 0 Generation of an internal reset by the Watchdog is disabled 1 When overflow occurs the Watchdog generates an internal reset IRQEN Interrupt Enable Code Label WD IRQEN 0 Generation of an interrupt by the Watchdog is disabled 1 When overflow occurs the Watchdog generates an interrupt EXTEN External Signal Enable Code Label WD EXTEN 0 Generation of a pulse on the pin NWDOVF by the Watchdog is disabled 1 When an overflow occurs a pulse the NWDOVF is generated OKEY Overflow Access Key Code Label OKEY Used only when writing WD OKEY is read as 0 0 234 Write access in WD OMR is allowed Other value Write access in WD OMR is prohibited ATMEL 1745D ATARM 04 Nov 05 AMEL 14 0 3 WD Clock Mode Register Name WD CMR Access Read Write Reset Value 0 Offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cv j _ Jc HPV d WDCLKS Clock Selection Code Label WDCLKS Clock Selected WD WDCLKS 0 0 MCK 32 WD WDCLKS MCK32 0 1 MCK 128 WD WDCLKS MCK128 1 0 MCK 1024 WD WDCLKS 1024 1 1 MCK 4096 WD WDCLKS MCK4096 HPCV High Pre load Counter Value Code Label WD HPCV Counter is preloaded when watchdog counter is restarted with bits
207. t interrupt The Source Vector Register 1 to 31 is indexed using the current interrupt number when the Interrupt Vector Register is read When there is no current interrupt the IRQ Vector Register reads O AMEL 9 1745D ATARM 04 Nov 05 AMEL 15 10 4 AIC FIQ Vector Register Register Name FVR Access Type Read only Reset Value 0 Offset 0x104 31 30 29 28 27 26 25 24 FIQV A o Aa E E FIQV En Aa Aa En FIQV FIQV NI AR E o FIQV FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corresponds to FIQ 15 10 5 AIC Interrupt Status Register Register Name AIC_ISR Access Type Read only Reset Value 0 Offset 0x108 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 4 3 2 1 0 7 6 5 poe G ono s IRQID Current IRQ Identifier Code Label IRQID The Interrupt Status Register returns the current interrupt source number 1745D ATARM 04 Nov 05 mm rar Fr 1 55800 15 10 6 Interrupt Pending Register Register Name AIC_IPR Access Type Read only Reset Value Undefined Offset 0x10C 31 30 29 28 27 26 25 24 COMMRX 82 IRQS 23 22 21 20 19 18 17 16 APMCIRQ RTCIRQ DAC1I
208. t lines are driven by the SPI only if it is programmed in Master Mode These lines are used to select the destination peripheral The PCSDEC field in MR Mode Regis ter selects 1 to 4 peripherals PCSDEC 0 or up to 15 peripherals PCSDEC 1 If Variable Peripheral Select is active the chip select signals are defined for each transfer in the PCS field in SP TDR Chip select signals can thus be defined independently for each transfer If Fixed Peripheral Select is active Chip Select signals are defined for all transfers by the field PCS in SP If a transfer with a new peripheral is necessary the software must wait until the current transfer is completed then change the value of PCS MR before writing new data in SP TDR The value on the NPCS pins at the end of each transfer can be read in the RDR Receive Data Register By default all NPCS signals are high equal to one before and after each transfer 20 2 4 Mode Fault Detection 1745D ATARM 04 Nov 05 A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCSO NSS signal When a mode fault is detected the bit in the SP SR is set until the SP SR is read and the is disabled until re enabled by bit SPIEN in the CR Control Register A MEL 187 AMEL Figure 20 1 Functional Flow Diagram in Master Mode SPI Enable 0 Fixed Peripheral
209. tate 0 Offset 0 30 31 m m a A RXPTR A N En Aa E N RXPTR RXPTR RXPTR gt lt 79 N 2 o lt o 7 o 3 a o E RXPTR must be loaded with the address of the receive buffer 18 10 13 USART Receive Counter Register Name US Access Type Read Write Reset State 0 Offset 0x34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXCTR RXCTR N a 2 o lt o E o x 3 a gt 5 E must be loaded with the size of the receive buffer 0 Stop Peripheral Data Transfer dedicated to the receiver 1 65535 Start Peripheral Data transfer if RXRDY is active AIMEL 1745D ATARM 04 Nov 05 www AMEL 18 10 14 USART Transmit Pointer Register Name US_TPR Access Type Read Write Reset State 0 Offset 0x38 m a A 31 30 TXPTR N A N En Aa E N E 23 TXPTR E En E En En Em TXPTR TXPTR x 3 g 2 Eod o 9 3 52 s te 5 8 5 D a gt
210. ted the corresponding flag is asserted and an interrupt generated if enabled at a given month date hour minute and second f only the seconds field is enabled then an alarm is generated every minute Depending on the combination of fields enabled a large number of possibilities are available to the user ranging from minutes to 365 366 days A verification on user interface data is performed when accessing the century year month date day hours minutes seconds and alarms A check is performed on illegal BCD entries such as illegal date of the month with regards to the year and century configured If one of the time fields is not correct the data is not loaded into the register counter and a flag is set in the Valid Entry Register VER This flag cannot be reset by the user It is reset as soon as an acceptable value is programmed This avoids any further side effects in the hardware The same processing is done for the alarm The following checks are processed Century check if it is in range 19 20 Year BCD entry check Date check range 01 31 Month check if it is in BCD range 01 12 check validity regarding date 5 Day check range 1 7 PON gt 91 55800 m 1745D ATARM 04 Nov 05 mms 1 55800 6 Hour BCD check in 24 hour mode check range 00 23 and check that AM PM flag is not set if RTC is set in 24 Hour mode in 12 Hour mode check range 01 12 7 Minute
211. ter made up of one resistor and two capacitors If the integrated PLL is not used it can remain disabled The PLLRC pin must be grounded if the resistor and the capaci tors need to be saved The following figure shows a typical filter connection Figure 12 5 Typical Filter Connection PLLRC GNDPLL In order to obtain optimal results with a 16 MHz input frequency and a 32 MHz output fre quency the typical component values for the PLL filter are R 2870 C1 680 nF C2 68 nF The lock time with these values is about 3 5 us in this example Master Clock Selection 1745D ATARM 04 Nov 05 The Master Clock can be selected through the CSS field in CGMR between the Slow Clock the output of the Main Oscillator or the output of the PLL The following CSS field definitions are forbidden and the write operations are not taken into account by the APMC deselect the Slow Clock if the Main Oscillator is disabled or its output is not stabilized disable the PLL without having first selected the Slow Clock or the Main Oscillator clock select the PLL clock and in the same register write disable the PLL select either the Main Oscillator or the PLL clocks and in the same register write disable the Main Oscillator disable the Main Oscillator without having first selected the Slow Clock This clock switch is performed in some Slow Clocks and PLLs or Main Oscillator clock cycles as described in the state machine dia
212. terrupt enabled 1745D ATARM 04 Nov 05 1 55800 15 AIC Advanced Interrupt Controller The AT91M55800A has an 8 level priority individually maskable vectored interrupt controller This feature substantially reduces the software and real time overhead in handling internal and external interrupts The interrupt controller is connected to the NFIQ fast interrupt request and the NIRQ stan dard interrupt request inputs of the ARM7TDMI processor The processor s NFIQ line can only be asserted by the external fast interrupt request input FIQ The NIRQ line can be asserted by the interrupts generated by the on chip peripherals and the external interrupt request lines IRQ0 to IRQ5 An 8 level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources Internal sources are programmed to be level sensitive or edge triggered External sources can be programmed to be positive or negative edge triggered or high or low level sensitive The interrupt sources are listed in Table 15 1 on page 96 and the AIC programmable registers in Table 15 2 on page 101 Figure 15 1 Advanced Interrupt Controller Block Diagram Advanced Peripheral Bus APB Control Logic Internal Interrupt Sources t Memorization Prioritization External Interrupt Sources Controller Manage NFI ARM7TDMI Core Note After a hardware reset th
213. th 5V thus resulting in full TTL compliance The following ground pins are provided GND for both VDDCORE and VDDIO GNDPLL for VDDPLL GNDA for VDDA GNDBU for VDDBU All of these ground pins must be connected to the same voltage generally the board electric ground with wires as short as possible GNDPLL GNDA and GNDBU are provided sepa rately in order to allow the user to add a decoupling capacitor directly between the power and ground pads In the same way the PLL filter resistor and capacitors must be connected to the device and to GNDBU with wires as short as possible Also the main oscillator crystal and the 32768 Hz crystal external load capacitances must be connected respectively to GNDPLL and to GNDBU with wires as short as possible The main constraints applying to the different voltages of the device are e VDDBU must be lower than or equal to VDDCORE VDDA must be higher than or equal to VDDCORE VDDCORE must be lower than or equal to VDDIO The nominal power combinations supported by the AT91M55800A are described in the follow ing table Table 7 1 Nominal Power Combinations Maximum Operating VDDIO VDDCORE VDDA VDDPLL VDDBU Frequency 3V 3V 3V 3V 3V 33 2 3 3V 3 3V 3 3V 3 3V 3 3V 33 MHz 5V 3 3V 3 3V 3 3V 3 3V 33 MHz Input Output Considerations After the reset the peripheral I Os are initialized as inputs to provide the user with maximum flexibility It is recommended that
214. the software trigger and the RC compare trigger are also available as triggers 19 4 3 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event TIOB control is used only if TIOB is defined as output not as an external event The following events control TIOA and TIOB software trigger external event and RC com pare RA compare controls TIOA and RB compare controls TIOB Each of these events can be programmed to set clear or toggle the output as defined in the corresponding parameter in TC CMR A MEL 165 1745D ATARM 04 Nov 05 19 4 4 166 AMEL The tables below show which parameter in TC_CMR is used to define the effect of each event Parameter TIOA Event ASWTRG Software trigger AEEVT External event ACPC RC compare ACPA RA compare Parameter TIOB Event BSWTRG Software trigger BEEVT External event BCPC RC compare BCPB RB compare If two or more events occur at the same time the priority level is defined as follows Software trigger External event RC compare RA or RB compare Status The following bits in the status register are significant in Waveform Mode CPAS RA Compare Status There has been a RA Compare match at least once since the last read of the status CPBS RB Compare Status There has been a RB Compare match at least once since the last read of the status CPCS RC Compare Status There has been a
215. tter Enable Code Label US TXEN 0 No effect 1 The transmitter is enabled if TXDIS is 0 TXDIS Transmitter Disable Code Label US TXDIS 0 No effect 1 The transmitter is disabled RSTSTA Reset Status Bits Code Label 75 RSTSTA 0 No effect 1 Resets the status bits PARE FRAME OVRE and RXBRK in the 05 STTBRK Start Break Code Label 05 STTBRK 0 No effect 1 If break is not being transmitted start transmission of a break after the characters present in 05 THR and the Transmit Shift Register have been transmitted e STPBRK Stop Break Code Label US STPBRK 0 No effect 1 If a break is being transmitted stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods A MEL 143 1745D ATARM 04 Nov 05 AMEL e STTTO Start Time out Code Label US STTTO 0 No effect 1 Start waiting for a character before clocking the time out counter SENDA Send Address Code Label 05 SENDA 0 No effect 1 In Multi drop Mode only the next character written to the US is sent with the address bit set 1745D ATARM 04 Nov 05 mm 1 55800 18 10 2 USART Mode Register Name US MR Access Type Read Write Reset State 0 Offset 0x04 NEC CLKO CHMODE NBSTOP SYNC 7 6 5 4 3 2 1 0 CHRL USCLKS Eo quoe USCLKS Clock Selection Baud Rate Generator Input Clock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
216. up Battery Operating Range 2 7V to 3 6V Oscillator and PLL Operating Range 40 C to 85 C Temperature Range Available in a 176 lead LQFP or 176 ball BGA Package 1 Description The AT91M55800A is a member of the Atmel AT91 16 32 bit microcontroller family which is based on the ARM7TDMI processor core This processor has a high perfor mance 32 bit RISC architecture with a high density 16 bit instruction set and very low power consumption In addition a large number of internally banked registers result in very fast exception handling making the device ideal for real time control applications The fully programmable External Bus Interface provides a direct connection to off chip memory in as fast as one clock cycle for a read or write operation An eight level prior AMEL G AT91 ARM Thumb Microcontrollers AT91M55800A Rev 1745D ATARM 04 Nov 05 AMEL ity vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real time performance of the device The device is manufactured using Atmel s high density CMOS technology By combining the ARM7TDMI processor core with an on chip SRAM a wide range of peripheral functions analog interfaces and low power oscillators on a monolithic chip the Atmel AT91M55800A is a powerful microcontroller that provides a highly flexible and cost effective solution to many ultra low power applications 1745D ATARM 04 Nov 05
217. upt by setting clearing the corresponding bit in the PIO IMR When a change in level occurs the corresponding bit in the PIO ISR Interrupt Sta tus is set whether the pin is used as a PIO or a peripheral and whether it is defined as input or output If the corresponding interrupt in IMR Interrupt Mask is enabled the PIO interrupt is asserted When PIO ISR is read the register is automatically cleared Each individual I O is associated with a bit position in the Parallel I O user interface registers Each of these registers are 32 bits wide If a parallel I O line is not defined writing to the corre sponding bits has no effect Undefined bits read zero 16 7 Multi driver Open Drain 1745D ATARM 04 Nov 05 Each I O be programmed for multi driver option This means that the I O is configured as open drain can only drive a low level in order to support external drivers on the same pin An external pull up is necessary to guarantee a logic level of one when the pin is not being driven Registers MDER Multi driver Enable and MDDR Multi driver Disable control this option Multi driver can be selected whether the pin is controlled by the PIO Controller or the peripheral PIO_MDSR Multi driver Status indicates which pins are configured to support external drivers A MEL 113 AMEL Figure 16 1 Parallel I O Multiplexed with a Bi directional Signal L Pad Output Enable Enable
218. when shut down or alarm is requested SHDALS Shut down or Alarm Output Selected Code Label 0 Tri stated APMC SHDALS OUT TRIS 0 Level 0 APMC SHDALS OUT LEVELO 1 Level 1 APMC SHDALS OUT LEVEL1 1 Reserved WKACKS Wake up or Alarm Acknowledge Output Selection This field defines the state of the WKACKS pin when wake up or alarm acknowledge is requested Wake up or Alarm Acknowledge Output WKACKS Selected Code Label 0 Tri stated APMC_WKACKS_OUT_TRIS 0 Level 0 APMC WKACKS OUT LEVEL 0 1 Level 1 APMC WKACKS OUT LEVEL 1 1 Reserved ALWKEN Alarm Wake up Enable Code Label APMC WKEN 0 The alarm from the RTC has no wake up effect 1 The alarm from the RTC commands a wake up ALSHEN Alarm Shut down Enable Code Label APMC ALSHEN 0 The alarm from the RTC has shut down effect 1 If ALWKEN is 0 the alarm from the RTC commands a shut down 1745D ATARM 04 Nov 05 AMEL 69 AMEL WKEDG Wake up Input Edge Selection This field defines the edge to detect on the Wake up pin WAKEUP to provoke a wake up WKEDG Wake up Input Edge Selection Code Label 0 0 None No edge is detected on wake up APMC WKEDG NONE 0 1 Positive edge APMC WKEDG POS EDG 1 0 Negative edge APMC WKEDG NEG EDG 1 1 Both edges WKEDG BOTH EDG 70 91 55800 memm 1745D ATARM 04 Nov 05 mI nn A 1 55800 12 9 10 APMC Status Register
219. xternal Trigger Interrupt mman 91 55800 19 5 12 TC Interrupt Disable Register Register Name TC IDR Access Type Write only Offset 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS e COVFS Counter Overflow Code Label TC covFs 0 No effect 1 Disables the Counter Overflow Interrupt LOVRS Load Overrun Code Label TC LovRs 0 No effect 1 Disables the Load Overrun Interrupt if WAVE 0 CPAS RA Compare Code Label TC CPAS 0 No effect 1 Disables the RA Compare Interrupt if WAVE 1 CPBS RB Compare Code Label TC CPBS 0 No effect 1 Disables the RB Compare Interrupt if WAVE 1 CPCS RC Compare Code Label TC CPCS 0 No effect 1 Disables the RC Compare Interrupt LDRAS RA Loading Code Label TC LDRAS 0 No effect 1 Disables the RA Load Interrupt if WAVE 0 LDRBS RB Loading Code Label TC LDRBS 0 No effect 1 Disables the RB Load Interrupt if WAVE 0 ETRGS External Trigger Code Label TC ETRGS 0 No effect 1 Disables the External Trigger Interrupt A MEL 183 1745D ATARM 04 Nov 05 AMEL 19 5 13 TC Interrupt Mask Register Register Name TC IMR Access Type Read only Reset State 0 Offset 0 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS e COVFS C
220. y Offset Register Name Access Reset State 0x00 Control Register SP_CR Write only 0 04 Mode Register SP MR Read Write 0 0x08 Receive Data Register SP_RDR Read only 0 OxOC Transmit Data Register SP TDR Write only 0x10 Status Register SP SR Read only 0 0x14 Interrupt Enable Register SP_IER Write only 0x18 Interrupt Disable Register SP_IDR Write only Ox1C Interrupt Mask Register SP IMR Read only 0 0x20 Receive Pointer Register SP RPR Read Write 0 0x24 Receive Counter Register Read Write 0 0x28 Transmit Pointer Register SP TPR Read Write 0 0 2 Transmit Counter Register SP TCR Read Write 0 0x30 Chip Select Register 0 SP CSRO Read Write 0 0x34 Chip Select Register 1 SP_CSR1 Read Write 0 0x38 Chip Select Register 2 SP_CSR2 Read Write 0 Ox3C Chip Select Register 3 SP Read Write 0 1745D ATARM 04 Nov 05 ATMEL 193 AMEL 20 7 1 SPI Control Register Register Name SP_CR Access Type Write only Offset 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 swsr sbs SPIEN SPI Enable Code Label 8 SPIEN 0 No effect 1 Enables the SPI to transfer and receive data SPIDIS SPI Disable Code Label sP SPIDIS 0 No effect 1 Disables the SPI All pins are set in input mode and no data is received or transmitted If a transfer is in progress t
221. y and the SPI without CPU intervention Seven pins are associated with the SPI Interface When not needed for the SPI function each of these pins can be configured as a PIO Support for an external master is provided by the PIO Controller Multi driver option To config ure an SPI pin as open drain to support external drivers set the corresponding bits in the PIO MDSR register see An input filter can be enabled on the SPI input pins by setting the corresponding bits in the PIO IFSR The NPCSO NSS pin can function as a peripheral chip select output or slave select input Refer to Table 1 for a description of the SPI pins Figure 2 SPI Block Diagram Serial Peripheral Interface Parallel IO Controller MISO MOSI SPCK APB NPCSO NSS NPCSO NSS NPCS1 NPCS NPCS2 NPCS3 Advanced Interrupt Controller A MEL 185 Table 1 SPI Pins AMEL Pin Name Mnemonic Mode Function Master Serial data input to SPI Master IN Slave Cul Slave Serial data output from SPI Master Serial data output from SPI MOSI Slave Serial data input to SPI Clock output from SPI Serial Clock E Slave Clock input to SPI Peripheral Chip Selects NPCS 3 1 Master Select peripherals Master Output Selects peripheral Select Master Input low causes mode fault Slave Input chip select for SPI Notes 1 Aftera hardware reset the SPI clock is disabled b
222. y default The user must configure the Power Management Controller before any access to the User Interface of the SPI 2 After a hardware reset the SPI pins are deselected by default see Section 16 Parallel I O Controller on page 112 The user must configure the PIO Controller to enable the corresponding pins for their SPI function NPCSO NSS must be configured as open drain in the Parallel Controller for multi master operation 20 2 Master Mode In Master Mode the SPI controls data transfers to and from the slave s connected to the SPI bus The SPI drives the chip select s to the slave s and the serial clock SPCK After enabling the SPI a data transfer begins when the ARM core writes to the SP TDR Transmit Data Register Transmit and Receive buffers maintain the data flow at a constant rate with a reduced require ment for high priority interrupt servicing When new data is available in the Transmit Data Register the SPI continues to transfer data If the RDR Receive Data Register has not been read before new data is received the Overrun Error OVRES flag is set The delay between the activation of the chip select and the start of the data transfer DLYBS as well as the delay between each data transfer DLYBCT can be programmed for each of the four external chip selects All data transfer characteristics including the two timing values are programmed in registers CSRO to SP Chip Se

Atmel AT91CAP7A-STK Computer Hardware User Manual

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