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ARM CM940T Computer Hardware User Manual

1. After configuration or code updates you must 1 Remove the CONFIG link 2 Power cycle the development system ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 3 23 Hardware Description The configuration mode allows FPGA and PLD code to be updated as follows The FPGAs are volatile but load their configuration from flash memory Flash memory which itself does not have a JTAG port can be programmed by loading designs into the FPGAs and PLDs which handle the transfer of data to the flash using JTAG The PLDs are non volatile devices which can be programmed directly by JTAG 3 8 3 JTAG signals Figure 3 12 shows the pinout of the Multi ICE connector and Table 3 4 on page 3 25 provides a description of the JTAG signals 3V3 12 ava nTRST OND TDI GND TMS _ GND tek ___ GND RICK GND TDO __ GND nSRST GND DBGRQ GND DBGACK GND 19 20 Figure 3 12 Multi ICE connector pinout Note In the description in Table 3 4 on page 3 25 the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain In most cases this will be Multi ICE although hardware from third party suppliers can also be used to debug ARM processors 3 24 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description Table 3 4 JTAG signal des
2. The major components on the core module are as follows ARM0940T microprocessor core core module FPGA which implements SDRAM controller system bus bridge reset controller interrupt controller status configuration and interrupt registers volatile memory comprising upto256MB of SDRAM optional via DIMM socket 256KB SSRAM SSRAM controller clock generator system bus connectors Multi ICE debug connector 1 2 1 System architecture Figure 1 2 illustrates the architecture of the core module ARM core SSRAM FPGA SDRAM Multi ICE System bus connectors Figure 1 2 ARM Integrator CM940T block diagram Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Introduction 1 2 2 Core module FPGA The FPGA provides system control functions for the core module enabling it to operate as a standalone development system or attached to a motherboard These functions are outlined in this section and described in detail in Chapter 3 Hardware Description SDRAM controller The SDRAM controller is implemented within the FPGA This provides support for Dual In line Memory Modules DIMMs with a capacity of between 16 and 256MB See SDRAM controller on page 3 6 Reset controller The reset controller initializes the core and allows the core module to be reset from five sources reset button N motherboard other core modules Multi ICE
3. Note This power connection is not required when the core module is fitted to a motherboard ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 2 3 Getting Started 2 1 4 Connecting Multi ICE When you are using the core module as a standalone system Multi ICE debugging equipment can be used to download programs The Multi ICE setup for a standalone core module is shown in Figure 2 2 S O OO D Multi ICE server debugger Y _ Parallel cable Multi ICE unit C Power supply Core module wn Figure 2 2 Multi ICE connection to a core module Caution Because the core module does not provide non volatile memory programs are lost when the power is removed Multi ICE can also be used when a core module is attached to a motherboard If more than one core module is attached then the Multi ICE unit must be connected to the module at the top of the stack The Multi ICE server and the debugger can be on one computer or on two networked computers 2 4 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Getting Started 2 2 Attaching the ARM Integrator CM940T to a motherboard Attach the core module onto a motherboard for example the ARM Integrator SP by engaging the connectors HDRA and HDRB on the botto
4. 109 50 Bm GND mn G12 110 51 G5 G13 111 2 millet marna A 53 G7 EM GC 113 54 GND G15 114 ee Oe 56 Bm SVS 12V 116 57 5V 12V 117 2 ml 12V 118 59 5V E 12V Hal 119 60 3V3 12V 120 Figure A 3 HDRB plug pin numbering ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved A 5 Signal Descriptions A 2 3 Through board signal connections The signals on the pins labeled E 31 0 are cross connected between the plug and socket so that the signals are rotated through the stack in groups of four For example the first block of four are connected as shown in Table A 2 Table A 2 Signal cross connections example Plug Socket E0 connects to El El connects to E2 E2 connects to E3 E3 connects to EU For details about the signal rotation scheme see System bus signal routing on page 3 15 The signals on the pins labeled F 31 0 are connected so that pins on the socket are connected to the corresponding pins on the plug The signals on G 15 8 and G 5 0 are connected so that pins on the socket are connected to the corresponding pins on the plug Pins G 7 6 carry the JTAG TDI and TDO signals The signal TDO is routed through devices on each baord as it passes up through the stack see JTAG signals on page 3 24 A 6 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A A 2 4 HDRB signal descriptions Signal Descriptions Table A 3 describes the signals on the pins lab
5. By mounting the core module onto a motherboard you can build a realistic emulation of the system being developed Through board connectors allow up to four core modules to be stacked on one motherboard The core module can be used in the following ways as a standalone development system N mounted onto an ARM Integrator SP development motherboard mounted onto an ARM Integrator AP development motherboard integrated into a third party development or ASIC prototyping system Figure 1 1 on page 1 3 shows the layout of the ARM Integrator CM940T 1 2 O Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Introduction Core module motherboard connectors HDRB Reset button _ DIMM socket SDRAM DIMM Multi ICE connector QO DDD HHHH UTU DDD HHHH UTU D HHH HD UTU pOoOoDoooooDoOo Ooboaoonoo0oo0o00 Processor core 2000000001 Un 000000001 THT Power connector Core module motherboard Memory controller and connectors HDRA system bus bridge FPGA Figure 1 1 Integrator CM940T layout ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 1 3 Introduction 1 2 ARM Integrator CM940T overview
6. Clear Interrupt source pe Status Raw status nIRQ From other bit slices Figure 4 4 Interrupt control 4 4 1 CM_IRQ_STAT 0x10000040 CM_FIQ_STAT 0x10000060 The status register contains the logical AND of the bits in the raw status register and the enable register 4 4 2 CM_IRQ_RSTAT 0x10000044 CM_FIQ_RSTAT 0x10000064 The raw status register indicates the signal levels on the interrupt request inputs A bit set to 1 indicates that the corresponding interrupt request is active 4 4 3 CM_IRQ_ENSET 0x10000048 CM_FIQ_ENSET 0x10000068 The enable set locations are used to set bits in the enable register as follows set bits in the enable register by writing to the ENSET location for the required IRQ or FIQ controller 1 SET the bit 0 leave the bit unchanged N read the current state of the enable bits from the ENSET location 4 20 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference 4 4 4 CM_IRQ_ENCLR 0x1000004C CM_FIQ_ENCLR 0x1000006C The clear set locations are used to set bits in the enable register as follows clear bits in the enable register by writing to the ENCLR location for the required IRQ or FIQ controller 1 CLEAR the bit 0 leave the bit unchanged 4 4 5 Interrupt register bit assignment The bit assignments for the IRQ and FIQ status raw status and enable register are shown in Table 4 11 Table 4 11 IRQ and FIQ register bit assignme
7. Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 8 2 Debugging modes The core module is capable of operating in two modes normal debug mode configuration mode Normal debug mode During normal operation and software development the core module operates in debug mode The debug mode is selected by default when a jumper is not fitted at the CONFIG link see Figure 3 10 on page 3 21 In this mode the processor core and debuggable devices on other modules are accessible on the scan chain as shown in Figure 3 11 on page 3 22 Configuration mode In configuration mode the debuggable devices are still accessible and in addition all FPGAs and PLDs in the system are added into the scan chain This allows the board to be configured or upgraded in the field using Multi ICE or other JTAG debugging equipment To select configuration mode fit a jumper to the CONFIG link on the core module at the top of the stack see Figure 3 10 on page 3 21 This has the effect of pulling the nCFGEN signal LOW which illuminates the CFG LED yellow on each module in the stack and reroutes the JTAG scan path The LED provides a warning that the development system is in the configuration mode Note Configuration mode is guaranteed for a single core module attached to a motherboard but may be unreliable if more than one core module is attached The larger loads on the TCK and TMS lines may cause unreliable operation
8. Note The software interrupt described in this section is used by software to generate IRQs or FIQs It should not be confused with the ARM SWI software interrupt instruction See the ARM Architecture Reference Manual 4 22 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Appendix A Signal Descriptions This index provides a summary of signals present on the core module main connectors It contains the following sections HDRA on page A 2 HDRB on page A 4 Note For the Multi ICE connector pinout and signal descriptions see JTAG signals on page 3 24 ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved A 1 Signal Descriptions A 1 HDRA Figure A 1 shows the pin numbers of the HDRA plug and socket All pins on the HDRA socket are connected to the corresponding pins on the HDRA plug Pin numbers for 200 way plug 35 viewed from above board 37 1 101 2 TA 2 O oa 45 mgo DA sl 103 49 o Oa 2 Samtec TOLC series 57 3V3 Figure A 1 HDRA plug pin numbering A 2 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Signal Descriptions The signals present on the pins labeled A 31 0 B 31 0 and C 31 0 are described in Table A 1 Table A 1 Bus bit assignment for an AMBA ASB bus Pin label Name ASB Description A 31 0 System address bus System addres
9. Units FMAX Operating frequency 25 MHz Tcu Clock HIGH 19 ns TeL Clock LOW 19 ns Tco Clock to output signals generated and 16 0 ns sampled on same clock edge Clock to output signals generated and 8 0 ns sampled on different clock edge Tic Input to clock signals generated and 8 0 ns sampled on same clock edge Input to clock signals generated and 4 0 ns sampled on different clock edge Tppp Motherboard propagation delay for 1 0 ns guidance only TskEw Motherboard clock skew for guidance 1 0 ns only ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved B 3 Specifications B 3 Mechanical details The core module is designed to be stackable on a number of different motherboards Its size allows it to be mounted onto a CompactPCI motherboard while allowing the motherboard to be installed in a card cage Figure B 1 shows the mechanical outline of the core module 148 0 128 0 200 way connector 4 col x 50 row Plug on top and socket on underside Memory DIMM HDRB 130 way connector 4 col x 30 row She on top and socket on underside Memory DIMM connector is 25 type which overhangs the edge of the board Connector footprint Pin numbers for 200 way plug viewed from above board Ver O asi lH HS pa La Samtec TOLC series 101 102 103 ole 000 Detail B Pin numbers for 168 way SDRAM DIMM conn
10. are closely coupled to the processor core to ensure high performance The core module uses separate memory and system buses to avoid memory access performance being degraded by bus loading The SDRAM controller is implemented within the core module controller FPGA and a separate SSRAM controller is implemented with a Programmable Logic Device PLD The SDRAM can be accessed by the local processor by processors on other core modules and by other system bus masters The SSRAM can only be accessed by the local processor 1 24 Clock generator The core module uses two on board clocks N CPU clock up to 160MHz memory bus clock up to 66 MHz These clocks are supplied by two clock generator chips Their frequencies are selected via the oscillator control register CM_OSC within the FPGA A reference clock is supplied to the two clock generators and to the FPGA see Clock generators on page 3 17 The memory bus and system bus are asynchronous This allows each bus to be run at the speed of its slowest device without compromising the performance of other buses in the system Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Introduction 1 2 5 Multi ICE connector The Multi ICE connector enables JTAG hardware debugging equipment such as Multi ICE to be connected to the core module It is possible to both drive and sense the system reset line nSRST and to drive JTAG reset NTRST to the core from the Multi ICE con
11. if no move on store size and is it 32MB if no move on store size and is it 64MB if no move on store size and of row address lines of column address lines of banks bank density of SDRAM MB divided by 4 CAS latency of 2 CAS latency of 2 CAS latency of 2 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved Programmer s Reference not 64 CMP r5 0x80 is it 128MB BNE not128 if no move on MOV r6 0xe store size and CAS latency of 2 B writesize not128 if it is none of these sizes then it is either 256MB or there is no SDRAM fitted so default to 256MB MOV r6 0x12 store size and CAS latency of 2 writesize MOV r1 r1 ASL 8 get row address lines for SDRAM register ORR r2 r1l r2 ASL 12 OR in column address lines ORR r3 r2 r3 ASL 16 OR in number of banks ORR r6 r6 r3 OR in size and CAS latency LDR r0 CM_BASE point at module registers STR r6 r0 0x20 store SDRAM parameters 4 18 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference 4 4 Interrupt registers The core module provides a 3 bit IRQ controller and 3 bit FIQ controller to support the debug communications channel used for passing information between applications software and the debugger The interrupt control registers are listed in Table 4 10 Table 4 10 Interrupt controller registers Register Name Address Access Size Desc
12. in coprocessor 15 register 1 CP15c1 The value of the V bit at reset is determined by the level on an external pin VINITHI To maintain compatibility across all cores the default reset value maps the vector to begin at address O see the ARM940T Technical Reference Manual When running applications with high vectors at OxFFFF0000 to OxFFFFFFFF software must write the correct value to the coprocessor register However Integrator motherboards have no physical memory at this location This means that the MMU must be programmed to map an area of physical memory to this virtual address When the core module is being used with a motherboard an alternative is to implement an area of physical memory on an expansion card or logic module 4 6 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference 4 3 Core module registers The core module status and control registers allow the processor to determine its environment and to control some core module operations The registers listed in Table 4 2 are located at 0x 10000000 and can only be accessed by the local processor Table 4 2 Core module status control and interrupt registers Register Name Address Access Description CM_ID 0x 10000000 Read Core module identification register CM_PROC 0x 10000004 Read Core module processor register CM_OSC 0x 10000008 Read write Core module oscillator values
13. same location within the Integrator memory map Accesses to either the boot ROM or SSRAM are controlled by the REMAP bit and the motherboard detect signal nMBDET from the motherboard as shown in Table 4 1 on page 4 2 Remap The REMAP bit only has effect if the core module is attached to a motherboard nMBDET 0 It is controlled by bit 2 of the CM_CTRL register at Ox 1000000C and functions as follows REMAP 0 As itis after a reset The Boot ROM on the motherboard appears in the address range 0x0 to Ox3FFFF REMAP 1 The SSRAM appears in the 0x0 to Ox3FFFF address range 4 2 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference Motherboard detect The nMBDET signal operates as follows nMBDET 0 The core module is attached to a motherboard and accesses in the address range 0x0 to Ox3FFFF to the boot ROM or SSRAM are controlled by the REMAP bit nMBDET 1 The core module is not attached and accesses in the address range 0x0 to Ox3FFFF are routed to the SSRAM Note The SSRAM is local which means that it can only be read by the processor on the same core module It provides fast local memory for the local processor and cannot be accessed by other system bus masters 4GB AS Abort Motherboard Motherboard 272MB CM registers CM registers CM registers 256MB SDRAM SDRAM SDRAM 256KB SSRAM Boot ROM SSRAM Standalone Attached Attached after r
14. software For information about the reset controller see Reset controller on page 3 8 System bus bridge The system bus bridge provides an interface between the memory bus on the core module and the system bus on a motherboard It allows the local processor access to interface resources on the motherboard and to the SDRAM on other core modules It also allows access to the local SDRAM from the PCI bridge on the motherboard and processors on other core modules see System bus bridge on page 3 11 ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 1 5 Introduction Status and configuration space The status and configuration space contains status and configuration registers for the core module These provide the following information and control type of processor and whether it has a cache MMU or protection unit the position of the core module in a multi module stack SDRAM size address configuration and CAS latency setup core module oscillator setup interrupt control for the processor debug communications channel The status and control registers can only be accessed by the local processor For more information about the status and control registers see Chapter 4 Programmer s Reference 1 23 Volatile memory The volatile memory system includes an SSRAM device and a plug in SDRAM memory module referred to as local SDRAM when it is on the same core module as the processor These areas of memory
15. to meet the needs of real time systems Software configurable options include random or round robin cache line replacement algorithm write through or writeback cache operation N cache locking with granularity V th of cache size The caches and write buffers improve CPU performance and minimize accesses to off chip memory thus reducing overall system power consumption The ARM940T includes support for coprocessors allowing a floating point unit or other application specific hardware acceleration to be added The ARM9TDMI core executes both the 32 bit ARM and 16 bit Thumb instruction sets allowing you to trade between high performance and high code density It is binary compatible with ARM7TDMI ARM10TDML and StrongARM processors and is supported by a wide range of tools operating systems and application software The ARM940T also features a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation For more information about the ARM940T refer to the ARM940T Technical Reference Manual 3 2 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 2 SSRAM controller The SSRAM controller is implemented in a Xilinx 9572 PLD which enables the SSRAM to achieve single cycle operation In addition to controlling accesses to the SSRAM the controller generates the processor response signals BWAIT BERROR BLAST for all accesses to SSRAM N SDRAM status
16. 0000C The core module control register CM_CTRL is a read write register that provides control of a number of user configurable features of the core module 31 4 3 2 1 0 Table 4 5 describes the core module control register bits Table 4 5 CM_CTL register Bits Name Access Function 31 8 Reserved Use read modify write to preserve value 7 4 Reserved Use read modify write to preserve value 3 RESET Write This is used to reset the core module the motherboard on which it is mounted and any core modules in a stack A reset is triggered by writing a 1 Reading this bit always returns a 0 allowing you to use read modify write operations without masking the RESET bit 2 REMAP Read write This only has affect when the core module is mounted onto a motherboard When this is the case and this bit is a 0 accesses to the first 256KB 0x00000000 to 0x0003FFFF of memory are redirected into the motherboard 1 nMBDET Read This bit indicates whether or not the core module is mounted on a motherboard 0 mounted on motherboard 1 standalone 0 LED Read write This bit controls the green MISC LED on the core module 0 LED OFF 1 LED ON ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 4 11 Programmer s Reference 4 3 5 CM STAT 0x10000010 The core module status register CM_STAT is a read only register that can be read to determine where in a multi core module stack this core modu
17. 3 Lock register 4 13 MBDET bit 4 11 Memory volatile 1 6 Memory map 4 2 MEMSIZE 4 15 Microprocessor core 3 2 MISC LED control 4 11 Motherboard detect 4 3 Motherboard attaching the core module 2 5 Multi ICE 1 7 3 21 connecting 2 4 Multi ICE connector 1 3 N nLCLK 3 19 nMBDET 3 22 Normal debug mode 3 23 Notices FCC iii O Operating mode SDRAM 3 6 Oscillator register 4 9 Output divider 3 18 3 19 P Power connector 1 3 2 3 Powering an attached core module 2 6 Precautions 1 11 Preventing damage 1 11 Processor bus clock 3 19 Processor core clock 3 18 Processor register 4 8 Product feedback xi Product status ii Proprietary notice ii R Raw status register interrupt 4 20 REFCLK 3 17 3 20 Reference clock 3 20 Register addresses 4 7 Registers 1 6 CM_CTL 4 2 CM_CTRL 4 11 CM_FIQ_ENCLR 4 19 CM_FIQ_ENSET 4 19 CM_FIQ_RSTAT 4 19 CM_FIQ_STAT 4 19 CM_ID 4 5 4 8 CM_IRQ_ENCLR 4 19 CM_IRQ_ENSET 4 19 CM_IRQ_RSTAT 4 19 CM_IRQ_STAT 4 19 CM_LOCK 4 13 CM_OSC 3 18 3 19 4 9 CM_PROC 4 8 CM SDRAM 4 14 CM_SOFT_INTCLR 4 19 CM_SOFT_INTSET 4 19 CM_STAT 4 12 Related publications x REMAP bit 4 11 Remap effect of 4 2 Reset control bit 4 11 Reset controller 1 5 3 8 S SDRAM fitting 2 2 SDRAM access arbitration 3 6 SDRAM accesses 4 4 SDRAM controller 1 5 3 6 SDRAM global access 4 5 Index ii Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A SDRAM operat
18. 5A Hardware Description 3 7 2 Processor bus clocks LCLK and nLCLk The frequency of the processor bus clocks LCLK and nLCLK is determined by the frequency of 2XCLK The clock signal 2XCLK is divided by 2 by the SSRAM controller PLD to produce LCLK and nLCLK The frequency of LCLK is controllable in 0 5 MHz steps in the range 6MHz to 66MHz This is achieved by programming the VCO and output divider bits for the 2XCLK generator in the CM_OSC register The VCO divider is controlled by the L_VDW bits and the output divider is controlled by the L_OD bits The reference divider is fixed The maximum speed of 2XCLK is limited by the speed of the SSRAM PLD Table 3 3 shows the values placed on the divider input pins and how the clock speeds are obtained The bits marked L are programmable in the CM_OSC register N 1 are tied HIGH 0 are tied LOW Table 3 3 2XCLK divider values L_RDW R 6 0 L_VDW V 8 0 L_OD S 2 0 0 0 1 1 1 0 0 L L L L L L L L L L L 22 fixed value 4 124 lt 4 and gt 124 not allowed 2 10 12 132MHz in 1MHz steps for 2XCLK The frequency of LCLK can be derived from the formula freq L_VDW 8 L_OD where L_VDW is the VCO divider word for the processor bus clock L_OD is the output divider for the processor bus clock Note Values for L_VDW and L_OD can be calculated using the ICS525 calculator on the Microclock website For details about programming L_VDW an
19. 9 F29 100 41 E30 SNS GND DS 101 42 GND F30 102 43 E31 F31 103 44 NE C0 E GG 04 45 G1 GND 105 46 GND G9 106 47 G2 G10 107 48 G3 G11 108 49 G4 GND 109 so ann CNO II G1 110 51 G5 G13 111 52 G6 G14 112 53 G7 G16 113 54 as GND G15 114 55 BV 12V 115 a 12V 116 57 5V 12V 117 58 3V3 12V 118 59 5V El 12V 119 co NS 3v3 12V 120 Figure A 2 HDRB socket pin numbering A 4 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Signal Descriptions A2 2 HDRB plug pinout Figure A 3 shows the pin numbers of the HDRB plug on the top of the core module 1 61 2 GND FO 62 3 E2 Ft a 5 4 E3 F2 64 5 E0 GND ey 6 GND F3 66 7 ES F4 EE 57 8 E6 F5 68 9 E7 GND NE 5 10 GND F6 70 1 E4 F7 E 71 12 E9 F8 72 13 E10 GND a 73 14 GND F9 74 15 E11 F10 EN 75 16 E8 F11 76 17 E13 GND En 77 2 18 GND F12 78 Pin numbers for 120 way plug H Et SENS araa viewed from above board a ere a araa A 23 E17 F6 DE 24 E18 F17 84 25 E19 ca 5 26 GND F18 86 4 61 27 E16 F19 EEE 7 ne 28 E2 F20 88 Oo O 29 E22 GND o 30 GND F21 90 2 62 31 E23 F22 L Tag O AT 32 E20 F23 92 33 E25 GNO II 93 3 63 34 GND F24 94 TA a TT 35 E26 F25 ee O O 36 E27 F26 96 37 E24 GND En 38 GND Fay 98 39 E29 F28 EN 40 E30 F29 100 41 E31 GND a 101 1 42 ID F 2 Samtec TOLC series o en B ER 44 GO G8 104 45 Gi GND MEME 105 46 GND G9 106 47 G2 mi G10 L 107 48 G3 G11 108 49 G4 GND
20. ARM Integrator CM940T User Guide ARM ARM Integrator CM940T User Guide Copyright ARM Limited 1999 All rights reserved Release information Change history Description Issue Change 8 September1999 A New document Proprietary notice ARM the ARM Powered logo Thumb and StrongARM are registered trademarks of ARM Limited The ARM logo AMBA Angel ARMulator EmbeddedICE ModelGen Multi ICE ARM7TDMI ARM7TDMI S ARM9TDMI PrimeCell and STRONG are trademarks of ARM Limited All other products or services mentioned herein may be trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM Limited in good faith However all warranties implied or expressed including but not limited to implied warranties or merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Document
21. CM_CTRL 0x 1000000C Read write Core module control CM_STAT 0x 10000010 Read Core module status CM_LOCK 0x 10000014 Read write Core module lock CM_SDRAM 0x 10000020 Read write SDRAM status and control CM IRO STAT 0x10000040 Read Core module IRQ status register CM_IRQ_RSTAT 0x10000044 Read Core module IRQ raw status register CM_IRQ_ENSET 0x10000048 Read write Core module IRQ enable set register CM_IRQ_ENCLR 0x 1000004C Write Core module IRQ enable clear register CM_SOFT_INTSET 0x 10000050 Read write Core module software interrupt set CM_SOFT_INTCLR 0x 10000054 Write Core module software interrupt clear CM_FIQ_STAT 0x 10000060 Read Core module FIQ status register CM_FIQ_RSTAT 0x 10000064 Read Core module FIQ raw status register CM_FIQ_ENSET 0x 10000068 Read write Core module FIQ enable set register CM_FIQ_ENCLR 0x 1000006C Write Core module FIR enable clear register CM_SPD 0x 10000100 to 0x100001FC Read SDRAM SPD memory Note All registers are 32 bits wide and do not support byte writes Write operations must be wordwide Bits marked as reserved in the following sections should be preserved using read modify write operations ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 4 7 Programmer s Reference 4 3 1 CM_ID 0x10000000 The core module ID register CM_ID is a read only register that identifies the board manufacturer board type and revision 31 24 23 1615 1211 43 0 MAN ARCH FPGA BUILD REV Table 4 3 desc
22. G components are connected in the return path so that the length of track driven by the last component in the chain is kept as short as possible TMS Test mode select from JTAG equipment TMS controls transitions in the tap controller state machine TMS connects to all JTAG components in the scan chain as the signal flows down the module stack 3 26 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 8 4 Debug communications interrupts The ARM940T processor core incorporates EmbeddedICE hardware and provides a debug communications data register which is used to pass data between the processor and JTAG equipment The processor accesses this register as a normal 32 bit read write register and the JTAG equipment reads and writes the register using the scan chain For a description of the debug communications channel see the ARM940T Technical Reference Manual Interrupts can be used to signal when data has been written into one side of the register and is available for reading from the other side These interrupts are supported by the interrupt controller within the core module FPGA and can be enabled and cleared by accessing the interrupt registers see Interrupt registers on page 4 19 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 27 Hardware Description 3 28 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Chapter 4 Programmers Refe
23. OSC register 3 18 3 19 4 9 M_PROC register 4 8 M_SDRAM 3 7 M_SDRAM register 4 14 M_SOFT_INTCLR register 4 19 M_SOFT_INTSET register 4 19 M_SPD 3 7 M_STAT register 4 12 ONFIG LED 3 21 ONFIG link 3 21 onfiguration mode 3 23 onnecting Multi ICE 2 4 onnecting power 2 3 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved Index i Index Connectors HDR A and HDRB 1 3 Multi ICE 2 4 power 2 3 Controller clock 1 6 3 17 reset 1 5 3 8 SDRAM 1 5 3 6 SSRAM 3 3 Controllers FIQ 4 19 IRQ 4 19 Core module control register 4 11 Core module FPGA 1 5 Core module ID 2 6 Core module registers 4 7 Core module stack position 4 12 CORECLK 3 17 3 18 D Debug comms channel 4 19 Debugging modes 3 23 DIMM socket 1 3 Document confidentiality status ii E Electromagnetic conformity iii Enable register interrupt 4 20 4 21 Ensuring safety 1 11 Exception vector mapping 4 6 FCC notice iii FIFOs 3 11 FIQ controller 4 19 Fitting SDRAM 2 2 FPGA 1 5 Global SDRAM 4 5 H HDRA 3 15 HDRA and HDRB connectors 1 3 l ID core module 2 6 Interface system bus 1 5 Interrupt control 4 20 Interrupt register bit assignment 4 21 Interrupt registers 4 19 Interupt status 4 20 IRQ and FIQ register bit assignment 4 21 IRQ controller 4 19 J JTAG 3 21 JTAG debug 1 7 JTAG scan path 3 22 JTAG signals 3 24 JTAG connecting 2 4 L LCLK 3 17 3 19 Local SDRAM 4 4 Location of connectors 1
24. RM Limited 1999 All rights reserved ARM DUI 0125A Contents ARM Integrator CM940T User Guide Chapter 1 Chapter 2 Chapter 3 Electromagnetic conformity ss iii Preface About this document issus viii F rtherteading TT x Feedback tenkino la a aed eh dt ab nn ees abad xi Introduction 1 1 About the ARM Integrator CM940T core module 1 2 1 2 ARM Integrator CM940T overview eee eee 1 4 1 3 Links and INdicat rs diiniita 1 8 1 4 NOSE PONS oes seek nent nn nee rt tre nn oh ead 1 10 1 5 PRECAUTIONS rss timer en A 1 11 Getting Started 2 1 Setting up a standalone ARM Integrator CM940T 2 2 2 2 Attaching the ARM Integrator CM940T to a motherboard sss eee eee 2 5 Hardware Description 3 1 ARM940T Microprocessor Core nr 3 2 3 2 SSRAM controller ivi nig Mane Seinen o 3 3 3 3 Gore module FPGA ssni cnc ae elec eer el ata ee latas 3 4 3 4 SDRAM controller sense Seta ain ail nine teint 3 6 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved v Chapter 4 Appendix A Appendix B 3 5 Reset controll f sites tiennent ada 3 8 3 6 System DUS e e le ocioteca eee mad tn ethene 3 11 3 7 Clock denerators sine Ae en a N E e 3 17 3 8 M ilti ICE Supports ses me AG Mise MSN nat ete Serer ee 3 21 Programmer s Reference 4 1 Mernory GrganiZation 2sis Hier helene nimes 4 2 4 2 Exception vector mapping ss 4 6 4 3 Core module regiSterS ceecececeeeseeeseee
25. and configuration register space system bus bridge ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 3 3 Hardware Description 3 3 Core module FPGA The core module FPGA contains five main functional blocks SDRAM controller on page 3 6 Reset controller on page 3 8 System bus bridge on page 3 11 Core module registers on page 4 7 Debug interrupt controller see Debug communications interrupts on page 3 27 The FPGA provides sufficient functionality for the core module to operate as a standalone development system although with limited capabilities System bus arbitration system interrupt control and input output resources are provided by the system controller FPGA on the motherboard See the user guide for your motherboard for further information Figure 3 1 illustrates the function of the core module FPGA and shows how it connects to the other devices in the system SDRAM Status Clock Reset SSRAM control generator registers controller Memory bus SDRAM controller SSRAM controller ARM core System bus PLD bridge FPGA System bus Multi ICE Es System bus connectors HDRA HDRB Figure 3 1 FPGA functional diagram Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description At power up the FPGA loads its configuration data from a flash memory device Parallel data
26. ay provide additional information The following publications provide information about related ARM products and toolkits ARM 740T Technical Reference Manual DDI 0008 s ARM Integrator AP User Guide ARM DUI 0098 ARM Integrator SP User Guide ARM DUI 0099 ARM Multi ICE User Guide ARM DUI 0048 AMBA Specification ARM IHI 0011 ARM Architectural Reference Manual ARM DDI 0100 ARM Firmware Suite Reference Guide ARM DUI 0102 ARM Software Development Toolkit User Guide ARM DUI 0040 ARM Software Development Toolkit Reference Guide ARM DUI 0041 N ADS Tools Guide ARM DUL 0067 ADS Debuggers Guide ARM DUI 0066 ADS Debug Target Guide ARM DUI 0038 ADS Developer Guide ARM DUI 0056 N ADS CodeWarrior IDE Guide ARM DUI 0065 The following publication provides information about the clock controller chip used on the Integrator modules MicroClock OSCaR User Configurable Clock Data Sheet MDS525 MicroClock Division of ICS San Jose CA The following publications provide information and guidelines for developing products for Microsoft Windows CE Standard Development Board for Microsoft Windows CE 1998 Microsoft Corporation HARP Enclosure Requirements for Microsoft Windows CE 1998 Microsoft Corporation Further information on these topics is available from the Microsoft web site O Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Feedback ARM Limite
27. confidentiality status This document is Open Access This document has no restriction on distribution Product status The information in this documents is Final information on a developed product ARM web address http www arm com Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Electromagnetic conformity This section contains electromagnetic conformity EMC notices Federal Communications Commission Notice NOTE This equipment has been tested and found to comply with the limits for a class A digital device pursuant to part 15 of the FCC rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense CE Declaration of Conformity This equipment has been tested according to ISE TEC Guide 22 and EN 45014 It conforms to the following product EMC specifications The product herewith complies with the requirements of EMC Directive 89 336 EEC as amended ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved iii Copyright A
28. controllable in 1MHz steps in the range 12MHz to 160MHz This is achieved by setting the Voltage Controlled Oscillator VCO divider and output divider for the CORECLK generator via the CM_OSC register The VCO divider is controlled by the C_VDW bits and output divider is controlled by the C_LOD bits The reference divider value is fixed Table 3 2 shows the values placed on the divider input pins and how the clock speeds are derived The bits marked C are programmable in the CM_OSC register 1 are tied HIGH N 0 are tied LOW Table 3 2 CORECLK divider values C_RDW R 6 0 C_VDW V 8 0 C_OD S 2 0 0 0 1 1 1 0 0 C C C C C C C C C C C 22 fixed value 4 152 lt 4 and gt 152 not allowed 2 10 12 160MHz in 1MHz steps The frequency of CORECLK can be derived from the formula freq 2 C_VDW 8 C_OD where C_VDW is the VCO divider word for the core clock C_OD is the output divider for the core clock For details about programming C_VDW and C_OD see CM_OSC 0x10000008 on page 4 9 Note Values for C_VDW and C_OD can be calculated using the ICS525 calculator on the Microclock website The CORECLK is buffered with a PI49FCT3805 to convert the Phase Locked Loop PLL output to 3 3V signal level The clock is series terminated with a 33Q resistor and then drives a single load on the microprocessor core 3 18 Copyright ARM Limited 1999 All rights reserved ARM DUI 012
29. core module memory System bus writes The data routing for system bus writes to SDRAM is illustrated in Figure 3 6 Processor core SDRAM controller m SDRAM Motherboard Figure 3 6 System bus writes to SDRAM Write transactions from the system bus to the SDRAM normally complete in a single cycle on the system bus The data address and control information associated with the transfer are posted into the FIFO and the transfer into the SDRAM completes when the SDRAM is available If the FIFO is full then the system bus master receives a retract response indicating that the arbiter may grant the bus to another master and that this transaction must be retried later ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 13 Hardware Description System bus reads The data routing for system bus reads from SDRAM is illustrated in Figure 3 7 Processor core controller FIFO FIFO Motherboard Figure 3 7 System bus reads from SDRAM For system bus reads the address and control information also pass through the FIFO but the returned data from the SDRAM bypasses the FIFO The order of transactions on the system bus and the memory bus is preserved Any previously posted write transactions are drained from the FIFO that is writes to SDRAM are completed before the read transfer is performed 3 6 3 Multi
30. cription Name Description Function DBGRQ Debug request from JTAG equipment DBGRQ is a request for the processor core to enter the debug state It is provided for compatibility with third party JTAG equipment DBGACK Debug acknowledge to JTAG equipment DBGACK indicates to the debugger that the processor core has entered debug mode It is provided for compatibility with third party JTAG equipment DONE FPGA configured DONE is an open collector signal which indicates when FPGA configuration is complete Although this signal is not a JTAG signal it does effect nSRST The DONE signal is routed between all FPGAs in the system through the HDRB connectors The master reset controller on the motherboard senses this signal and holds all the boards in reset by driving nSRST LOW until all FPGAs are configured nCFGEN Configuration enable from jumper on module at the top of the stack nCFGEN is an active LOW signal used to put the boards into configuration mode In configuration mode all FPGAs and PLDs are connected to the scan chain so that they can be configured by the JTAG equipment nRTCKEN Return TCK enable from core module to motherboard nRTCKEN is an active LOW signal driven by any core module that requires RTCK to be routed back to the JTAG equipment If nRTCKEN is HIGH the motherboard drives RTCK LOW If nRTCKEN is LOW the motherboard drives the TCK signal back up the stack t
31. d L_OD see CM_OSC 0x10000008 on page 4 9 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 19 Hardware Description The LCLK clock signal is buffered by a 5 output low skew buffer PI49FCT3805 to drive five loads These are SDRAM_CLK 3 0 SSRAM CIK The nLCLK clock signal is a phase aligned inversion of the LCLK signal It is buffered by a 5 output low skew buffer PI49FCT3805 to four loads These are e ARM_BCLK_M PLD_BCLK_M e FPGA_BCLK_M LA_BCLK_M All clocks are series terminated with 330 resistors placed as close to the source as possible 3 7 3 FPGA reference clock REFCLK The REFCLK signal is used by the FPGA to generate the SDRAM refresh clock and SPD EEPROM clock This is a fixed frequency clock of 24MHz which is output from the reference pin of the second ICS525 chip U7 3 20 O Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 8 Multi ICE support The core module provides support for debug using JTAG It provides a Multi ICE connector and JTAG scan paths around the development system Figure 3 10 shows the Multi ICE connector and the CONFIG link Multi ICE connector CONFIG link CFGLED Sy Lp Figure 3 10 JTAG connector CONFIG link and LED The CONFIG link is used to enable in circuit programming of the FPGA and PLDs using Multi ICE see Debugging modes on page 3 23 The Multi ICE connector p
32. d detect pin Note Table A 3 shows signal descriptions for an AMBA ASB bus implementation A 8 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Appendix B Specifications This appendix contains the specifications for the ARM Integrator CM940T core module It contains the following sections Electrical specification on page B 2 Timing specification on page B 3 N Mechanical details on page B 4 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved B 1 Specifications B 1 Electrical specification Table B 1 shows the core module electrical characteristics for the system bus interface The core module uses 3 3V and 5V source The 12V inputs are supplied by the motherboard but not used by the core module Table B 1 Core module electrical characteristics Symbol Description Min Max Unit 3V3 Supply voltage interface signals 3 1 3 5 V 5V Supply voltage 4 75 5 25 V Vin High level input voltage 2 0 3 6 V VIL Low level input voltage 0 0 8 V Vox High level output voltage 24 V VoL Low level output voltage 0 4 V CIN Input capacitance 20 pF B 2 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A B 2 Timing specification Specifications Table B 2 provides the operating timing characteristics for the system bus interface signals Table B 2 Core module timing preliminary Symbol Description Min Max
33. d welcomes feedback both on the ARM Integrator CM940T core module and on the documentation Feedback on this document If you have any comments about this document please send email to errata arm com giving the document title the document number the page number s to which your comments refer an explanation of your comments General suggestions for additions and improvements are also welcome Feedback on the ARM Integrator CM940T If you have any comments or suggestions about this product please contact your supplier giving the product name an explanation of your comments ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved Xi xii Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Chapter 1 Introduction This chapter introduces the ARM Integrator CM940T core module It contains the following sections e About the ARM Integrator CM940T core module on page 1 2 e ARM Integrator CM940T overview on page 1 4 e Links and indicators on page 1 8 e Test points on page 1 10 e Precautions on page 1 11 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved Introduction 1 1 About the ARM Integrator CM940T core module The Integrator CM940T core module provides you with the basis of a flexible development system which can be used in a number of different ways With power and a simple connection to a Multi ICE debugger the core module provides a basic development system
34. eaeeeaeeseeeeeseeeeaeeeaeeeeaeeeeeseaeeteaeeeaeeeaes 4 7 4 4 Interrupt regis ES a 3 ies cta 4 19 Signal Descriptions A 1 DRASS A tes ete techn ee arto ede oe ee Sas da ees A 2 A 2 HDRB site avi ie ioe hi A nn ees ei els A 4 Specifications B 1 Electrical Sp cifications anh eee is B 2 B 2 Timing specification ui B 3 B 3 Mechanical details 2 i stscccca E ET B 4 vi Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Preface This preface introduces the ARM Integrator CM940T core module and its reference documentation It contains the following sections About this document on page viii Further reading on page x N Feedback on page xi ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved vii About this document This document describes how to set up and use the ARM Integrator CM940T core module Intended audience This document has been written for experienced hardware and software developers to aid the development of ARM based products using the ARM Integrator CM940T as part of a development system Organization This document is organized into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the core module Chapter 2 Getting Started Read this chapter for a description of how to set up and start using the core module Chapter 3 Hardware Description Read this chapter for a description of the header s hardware architecture including clocks re
35. ector shown O O Q O Q 0 YT 85 Measurement datum is line shown through pins Pin numbers for 200 way socket viewed from below board m ei 102 a 04 w TH H4 0 ny ara Samtec TOLC series Figure B 1 Board outline B 4 O Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Index The items in this index are listed in alphabetic order with symbols and numerics appearing at the end The references given are to page numbers A About this book feedback xi typographical conventions ix Access arbitration SDRAM 3 6 Accesses boot ROM 4 2 SSRAM 4 2 Accesses SDRAM 4 4 Alias SDRAM addresses 4 5 ARM web address ii Assmbled Integrator system 2 5 Block diagram 1 4 Boot ROM accesses 4 2 Bus bridge system 3 11 Bus clock processor 3 19 Bus operating modes 3 16 C Calculating the CORECLK speed 3 18 Calculating the LCLK speed 3 19 CAS latency setting 4 15 CE Declaration of Conformity iii Checking for valid SPD data 4 16 Clock generator 1 6 3 17 Clock reference 3 20 M_CTL register 4 2 M_CTRL register 4 11 M_FIQ_ENCLR register 4 19 M_FIQ_ENSET register 4 19 M_FIQ_RSTAT register 4 19 M_FIQ_STAT register 4 19 M_ID Register 4 8 C C C C C Cc C CM_ID register 4 5 C C C C C C C C C C C C C C C C C C M_IRQ_ENCLR register 4 19 M_IRQ_ENSET register 4 19 M_IRQ_RSTAT register 4 19 M_IRQ_STAT register 4 19 M_LOCK register 4 13 M_
36. eled E 31 0 F 31 0 and G 15 0 Table A 3 HDRB signal description Pin label Name Description E 31 28 SYSCLK 3 0 System clock ASB clock to each core module expansion card E 27 24 nPPRES 3 0 Processor present E 23 20 nIRQ 3 0 Interrupt request to processors 3 2 1 and 0 respectively E 19 16 nFIQ 3 0 Fast interrupt requests to processors 3 2 1 and 0 respectively E 15 12 ID 3 0 Core module stack position indicator E 11 8 Reserved s E 7 4 AGNT 3 0 System bus grant E 3 0 AREQ 3 0 System bus request F 31 0 Not connecetd Gl6 nRTCKEN RTCK AND gate enable G 15 14 CFGSEL 1 0 FPGA configuration select G13 nCFGEN Sets motherboard into configuration mode G12 nSRST Multi ICE reset open collector G11 FPGADONE Indicates when FPGA configurarion is complete open collector G10 RTCK Returned JTAG test clock G9 nSYSRST Buffered system reset G8 nTRST JTAG reset G7 TDO JTAG test data out G6 TDI JTAG test data in G5 TMS JTAG test mode select ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved A 7 Signal Descriptions Table A 3 HDRB signal description continued Pin label Name Description G4 TCK JTAG test clock G 3 1 MASTER 2 0 Master ID Binary encoding of the master currently performing a transfer on the bus Corresponds to the module ID and to the AREQ and AGNT line numbers G0 nMBDET Motherboar
37. ered N 16MB 32MB 64MB 128MB or 256MB To install an SDRAM DIMM 1 Ensure that the core module is powered down 2 Open the SDRAM retaining latches outwards 3 Press the SDRAM module into the edge connector until the retaining latches click into place Note The DIMM edge connector has polarizing notches to ensure that it is correctly oriented in the socket 2 1 2 Using the core module without SDRAM The core module can be operated without SDRAM because it has 256KB of SSRAM permanently fitted However in order to operate the core module with ARM debuggers you must change the internal variable t op_of_memory from the default setting of 0x00080000 512KB to 0x00040000 256KB before running programs that are linked with the standard libraries For further information about ARM debugger internal variables refer to the Software Development Toolkit Reference Guide 2 2 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Getting Started 2 1 3 Supplying power When using the core module as a standalone development system you should connect a bench power supply with 3 3V and 5V outputs to the power connector as illustrated in Figure 2 1 D a D T BV G r 2 3 3V E k T a PS 8 GND ra T O Figure 2 1 Power connector
38. eset after remap Figure 4 1 Effect of remap and motherboard detect ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 4 3 Programmer s Reference 4 1 3 SDRAM accesses The Integrator memory map provides a 256MB address space for SDRAM When a smaller sized SDRAM DIMM is fitted it is mapped repeatedly to fill the 256MB space For example a64MB DIMM appears four times as shown in Figure 4 2 OxOFFFFFFF 64MB Local SDRAM repeat image 64MB Local SDRAM repeat image Local SDRAM eae repeat image 64MB Local SDRAM 0x0003FFFF 256KB SSRAM Figure 4 2 SDRAM repeat mapping for a 64MB DIMM Local SDRAM The local processor can access the local SDRAM that is the SDRAM on the same core module at 0x00000000 to OXOFFFFFFF in the core module address space However the lowest 256KB 0x00000000 to 0x0003FFFE is hidden by the SSRAM or boot ROM depending upon whether the core module is attached to a motherboard and upon the state of the REMAP bit The SDRAM cannot be accessed within this address space although it can be accessed at one of its repeat images or at its alias location In the case of a 256MB DIMM which fills the local SDRAM space the first 256KB can only be accessed at the alias location see System bus accesses to SDRAM below 4 4 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A System bus accesses to SDRAM Programmer s Reference If the core module is mo
39. f SDRAM DIMMs do not comply with the JEDEC standard and do not implement the checksum byte The Integrator is not guaranteed to operate with non compliant DIMMs The code segment shown in Example 4 1 on page 4 17 can be used to correctly setup and remap the SDRAM 4 16 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A CM_BASE SPD_BASE lightled EQU EQU LDR MOV STR readspdbit LDR AND CMP BNE setupsdram LD LD LD LD LD MU MOV CM BN RB RB RB RB MOV not16 CMP BNE MOV not32 CMP BNE MOV Example 4 1 0x10000000 0x10000100 turn on header r0 CM_BASE r1l 5 rl r0 0xc setup SDRAM Programmer s Reference base address of Core Module registers base address of SPD information LED and remap load register set remap and memory base address led bits write the register check SPD bit is set rl r0 0x20 rl rl 0x20 r1 0x20 readspdbit work out the r0 SPD_BASE ri r0 3 v2 r0 4 7 r3 r0 5 r4 r0 31 A r5 11 13 r5 r5 ASL 2 A r5 0x10 not16 r6 0x2 writesize r5 0x20 A not 32 r6 0x6 A writesize r5 0x40 A not64 r6 0xa Z writesize read the status register mask SPD bit test if set 5 branch until the SPD memory has been read SDRAM size point at SPD memory number number number module calculate size size in MB is it 16MB
40. from the flash is serialized by the Programmable Logic Device PLD into the configuration inputs of the FPGA Figure 3 2 shows the FPGA configuration mechanism A 18 0 D 7 0 A FPGA OE __ configuration WE ROM flash CS Multi ICE Figure 3 2 FPGA configuration Multi ICE can be used to reprogram the PLD FPGA and flash when the core module is placed in configuration mode See Multi ICE support on page 3 21 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 5 Hardware Description 3 4 SDRAM controller The core module provides support for a single 16 32 64 128 or 256MB SDRAM DIMM 3 4 1 SDRAM operating mode The operating mode of the SDRAM devices is controlled with the mode set register within each SDRAM These registers are set immediately after power up to specify a burst size of four for both reads and writes N Column Address Strobe CAS latency of 2 cycles The CAS latency and memory size can be reprogrammed via the SDRAM control register CM_SDRAM at address 0x 10000020 See CM_SDRAM 0x10000020 on page 4 14 Note Before the SDRAM is used it is necessary to read the SPD memory and program the CM_SDRAM register with the parameters indicated in Table 4 8 on page 4 14 If these values are not correctly set then SDRAM accesses may be slow or unreliable 3 4 2 Access arbitration The SDRAM controller provides two ports to suppo
41. ght ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 7 Clock generators The core module provides its own clock generators and operates asynchronously with the motherboard The clock generator provides two programmable clocks processor core clock CORECLK N processor local memory bus clocks LCLK and nLCLK In addition a fixed frequency reference clock REFCLK is supplied to the FPGA These clocks are supplied by two MicroClock ICS525 devices and by the SSRAM controller PLD as illustrated in Figure 3 9 FPGA CM_OSC register 24MHz ICS525 ICS525 crystal U6 U7 ns pon Lo PCORECLK K LCLK SSRAM controller PLD gt nLCLK Figure 3 9 Core module clock generator The ICS525s are supplied with a reference clock signal from a 24MHz crystal oscillator The 2XCLK output from the first ICS525 U6 is supplied to the PLD and divided by two to produce the signals LCLK and nLCLK The output from U7 provides the CORECLK signal The reference output from U6 supplies the reference input to U7 and the reference output from U7 supplies the FPGA reference clock The output frequencies from the ICS525s are configured using divider input pins to produce a wide range of frequencies ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 17 Hardware Description 3 7 1 Processor core clock CORECLK The frequency of CORECLK is
42. hich leaves the board sensitive to electrostatic discharges and allows electromagnetic emissions Caution To avoid damage to the board you should observe the following precautions Never subject the board to high electrostatic potentials Always wear a grounding strap when handling the board N Only hold the board by the edges Avoid touching the component pins or any other metallic element Do not use the board near equipment which could be sensitive to electromagnetic emissions such as medical equipment a transmitter of electromagnetic emissions ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 1 11 Introduction 1 12 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Chapter 2 Getting Started This chapter describes how to set up and prepare the ARM Integrator CM940T core module for use It contains the following sections e Setting up a standalone ARM Integrator CM940T on page 2 2 e Attaching the ARM Integrator CM940T to a motherboard on page 2 5 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 2 1 Getting Started 2 1 Setting up a standalone ARM Integrator CM940T To set up the core module as a standalone development system 1 Optionally fit an SDRAM DIMM 2 Supply power 3 Connect Multi ICE 2 1 1 Fitting an SDRAM DIMM You should fit the following type of SDRAM module e PC66 or PC100 compliant 168pin DIMM unbuff
43. ights reserved 3 7 Hardware Description 3 5 Reset controller The core module FPGA incorporates a reset controller which enables the core module to be reset as a standalone unit or as part of an Integrator development system The core module can be reset from five sources N reset button N motherboard other core modules Multi ICE N software Figure 3 3 shows the architecture of the reset controller nSYSRST nMBDET Core Motherboard and other core modules SWRST BnRES M Sync K nSRST Reset e nDONE control PBRST Multi ICE FPGA Figure 3 3 Core module reset controller 3 8 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 5 1 Reset signals Table 3 1 describes the external reset signals Table 3 1 Reset signal descriptions Name Description Type Function BnRES M Processor reset Output The BnRES_M signal is used to reset the processor core It is generated from nSRST LOW when the core module is used standalone or nSYSRST LOW when the core module is attached to a motherboard It is asserted as soon as the appropriate input becomes active It is deasserted synchronously from the falling edge of the processor bus clock nDONE FPGA configured Input The nDONE signal is an inversion of the open collector signal FPGADONE which is generated by al
44. indicate that the CONFIG link is fitted ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 1 9 Introduction 1 4 Test points The core module provides two ground and five signal test points as an aid to debug These are illustrated in Figure 1 4 TP6 TPZ Voltage regulator nanan TP3 099909000 000909000 o 4 B S a TP2 Figure 1 4 Test points The functions of the test points are summarized in Table 1 2 Table 1 2 Test point functions Test point Name Function TP1 GND Ground TP2 GND Ground TP3 FCLKOUT Clock output from the ARM940T microprocessor core TP4 LBCLK Local memory bus clock TPS Core clock Clock supplied to the ARM940T microprocessor core TP6 VDD940T Output from voltage regulator TP7 ADJ ADJ pin of voltage regulator Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Introduction 1 5 Precautions This section contains safety information and advice on how to avoid damage to the core module 1 5 1 Ensuring safety Warning To avoid a safety hazard only Safety Extra Low Voltage SELV equipment should be connected to the JTAG interface 1 5 2 Preventing damage The core module is intended for use within a laboratory or engineering development environment It is supplied without an enclosure w
45. ing mode 3 6 SDRAM repeat mapping 4 4 SDRAM status and control register 4 14 SDRAM SPD memory 4 16 Serial presence detect 3 6 Setting CAS latency 4 15 Setting SDRAM size 4 15 Setup power connections 2 3 standalone 2 2 Software interrupt registers 4 22 Software reset 4 11 SPD memory 4 16 SPDOK bit 4 14 SSRAM accesses 4 2 SSRAM controller 3 3 Standalone core module 2 2 Status and configuration registers 1 6 Status register 4 12 Status register interrupt 4 20 Supplying power 2 3 System architecture 1 4 System bus operating modes 3 16 System bus bridge 1 5 3 11 System bus signal routing 3 15 T Typographical conventions ix U Using the core module with a motherboard 2 5 V VCO divider 3 18 3 19 Vector mapping 4 6 Volatile memory 1 6 W Web site ARM ii Index ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved Index iii Index Index iv Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A
46. l FPGAs when they have completed their configuration The FPGADONE signal is routed round the system through the HDRB connectors to the inputs of all other FPGAs in the system The signal nSRST is held asserted until nDONE is driven LOW nMBDET Motherboard detect Input The nMBDET signal is pulled LOW when the core module is attached to a motherboard and HIGH when the core module is used standalone When MBDET is LOW nSYSRST is used to generate the BnRES_M signal When nMBDET is HIGH nSRST is used to generate the BnRES_M signal PBRST Push button reset Input The PBRST signal is generated by pressing the reset button nSRST System reset Bidirectional The nSRST open collector output signal is driven LOW by the core module FPGA when the signal PBRST or software reset SWRST is asserted As an input nSRST can be driven LOW by Multi ICE If there is no motherboard present the nSRST signal is synchronized to the processor bus clock to generate the BnRES M signal nSYSRST System reset Input The nSYSRST signal is generated by the system controller FPGA on the motherboard It is used to generate the BnRES_M signal when the core module is attached to a motherboard It is selected by the motherboard detect signal nMBDET ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 9 Hardware Description 3 5 2 Software resets The core module FPGA provides a software reset which can be triggered by writing to the
47. le 4 4 CM_OSC register Bits Name Access Function 31 25 Reserved Use read modify write to preserve value 24 23 BMOD Read This field contains 00 which indicates that the processor bus mode is selected by writing to CM_CTRL register see CM_CTRL 0x1000000C on page 4 11 22 20 LOD Read write Memory clock output divider 000 divide by 10 001 divide by 2 default 010 divide by 8 011 divide by 4 100 divide by 5 101 divide by 7 110 divide by 9 111 divide by 6 19 12 L VDW Read write Processor bus clock VCO divider word Defines the binary value of the V 7 0 pins of the clock generator V 8 is tied low 00000100 6MHz default with OD 2 ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 4 9 Programmer s Reference Table 4 4 CM_OSC register continued Bits Name Access Function 11 Reserved Use read modify write to preserve value 10 8 COREOD Read write Core clock output divider 000 divide by 10 001 divide by 2 default 010 divide by 8 011 divide by 4 100 divide by 5 101 divide by 7 110 divide by 9 111 divide by 6 7 0 COREVCO Read write Core clock VCO divider word Defines the binary value of the V 7 0 pins of the clock generator V 8 is tied low 00000100 12MHz default with OD 2 4 10 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference 4 3 4 CM CTRL 0x100
48. le is positioned 31 8 7 0 Table 4 6 describes the core module status register bits Table 4 6 CM_STAT register Bit Name Access Function 31 8 Reserved Use read modify write to preserve value 7 0 ID Read Card number 0x00 core module 0 0x01 core module 1 0x02 core module 2 0x03 core module 3 OxFF invalid or no motherboard attached 4 12 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference 4 3 6 CM LOCK 0x10000014 The core module lock register CM_LOCK is a read write register that is used to control access to the CM_OSC register allowing it to be locked and unlocked This mechanism prevents the CM_OSC register from being overwritten accidently 31 17 16 15 0 Table 4 7 describes the core module lock register bits Table 4 7 CM LOCK register Bits Name Access Function 16 LOCKED Read This bit indicates if the CM_OSC register is locked or unlocked 0 unlocked 1 locked 15 0 LOCKVAL Read write Write the value 0x0000A05F to this register to enable write accesses to the CM_OSC register Write any other value to this register to lock the CM_OSC register ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 4 13 Programmer s Reference 4 3 7 CM _SDRAM 0x10000020 The SDRAM status and control register CM_SDRAM is a read write register used to set the configuration parameters for the SDRAM DIMM This control is necessa
49. ly to the motherboard installing the motherboard in a card cage or an ATX type PC case depending on type For further information refer to the user guide for the motherboard you are using 2 6 O Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Chapter 3 Hardware Description This chapter describes the on board hardware It contains the following sections ARM940T microprocessor core on page 3 2 N SSRAM controller on page 3 3 Core module FPGA on page 3 4 SDRAM controller on page 3 6 Reset controller on page 3 8 N System bus bridge on page 3 11 Clock generators on page 3 17 Multi ICE support on page 3 21 ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved Hardware Description 3 1 ARM940T microprocessor core The ARM940T cached processor macrocell is a member of the ARM9 Thumb family of high performance 32 bit system on a chip processors It provides the following ARM9TDMI RISC integer CPU 4KB instruction and data caches N write buffer protection unit N AMBA ASB bus interface The ARM940T processor employs a Harvard cache architecture and so has separate 4KB instruction and 4KB data caches Each cache has a 4 word line length The protection unit allows eight regions of memory to be defined each with individual cache and write buffer configurations and access permissions The cache system is software configurable to provide highest average performance or
50. m of the core module with the corresponding connectors on the top of the motherboard The lower side of the core module has sockets and the upper side of the core module has plugs to allow core modules to be mounted on top of one another maximum of four core modules can be Stacked on a motherboard Figure 2 3 illustrates an example development system with four core modules attached to an ARM Integrator SP motherboard Module 3 LS Module 2 Sy Module 1 Module 0 Motherboard Figure 2 3 Assembled Integrator system ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 2 5 Getting Started 2 2 1 2 2 2 Core module ID The ID of the core module is configured automatically by the connectors there are no links to set and depends on its position in the stack N core module 0 is installed first core module 1 is installed next and cannot be fitted without core module 0 core module 2 is installed next and cannot be fitted without core module 1 N core module 3 is installed next and cannot be fitted without core module 2 The ID of the core module also defines the ID of the microprocessor it carries and the system bus address of its SDRAM The position of a core module in the stack can be read from the CM_STAT register See CM_STAT 0x10000010 on page 4 12 Powering the assembled Integrator development system Power the assembled Integrator development system by connecting a bench power supp
51. nector See Multi ICE support on page 3 21 Note JTAG test equipment supplied by other vendors may also be used ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 1 7 Introduction 1 3 Links and indicators The core module provides one link and four surface mounted LEDs These are illustrated in Figure 1 3 MISC CONFIG FPGA OK S POWER El CFGLED Figure 1 3 Links and indicators 1 3 1 CONFIG link The core module has only one link marked CONFIG This is left open during normal operation It is only fitted when downloading new FPGA and PLD configuration information 1 8 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A 1 3 2 LED indicators Introduction The functions of the four surface mounted LEDs are summarized in Table 1 1 Table 1 1 LED functional summary Name Color Function MISC Green This LED is controlled via the control register see CM CTRL 0x1000000C on page 4 11 FPGA OK Green This LED illuminates when the FPGA has successfully loaded its configuration information following power on POWER Green This LED illuminates to indicate that a 3 3V supply is present CFGLED Orange This LED illuminates to
52. nt Bit Name Function 2 COMMTx Debug communications transmit interrupt This interrupt indicates that the communications channel is available for the processor to pass messages to the debugger 1 COMMRx Debug communications receive interrupt This interrupt indicates to the processor that messages are available for the processor to read 0 SOFT Software interrupt ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 4 21 Programmer s Reference 4 4 6 CM _SOFT_INTSET 0x10000050 CM_SOFT_INTCLT 0x10000054 The core module interrupt controller provides a register for controlling and clearing software interrupts This register is accessed using the software interrupt set and software interrupt clear locations The set and clear locations are used as follows Set the software interrupt by writing to the CM_SOFT_INTSET location 1 SET the software interrupt 0 leave the software interrupt unchanged Read the current state of the of the software interrupt register from the CM_SOFT_INTSET location A bit set to 1 indicates that the corresponding interrupt request is active N Clear the software interrupt by writing to the CM_SOFT_INTCLR location 1 CLEAR the software interrupt 0 leave the software interrupt unchanged The bit assignment for the software interrupt register is shown in Table 4 12 Table 4 12 IRQ register bit assignment Bit Name Function 0 SOFT Software interrupt
53. o the JTAG equipment nSRST System reset bidirectional nSRST is an active LOW open collector signal which can be driven by the JTAG equipment to reset the target board Some JTAG equipment senses this line to determine when a board has been reset by the user The open collector nRST reset signal may be driven LOW by the reset controller on the core module to cause the motherboard to reset the whole system by driving nSYSRST LOW This is also used in configuration mode to control the initialization pin nINIT on the FPGAs Though not a JTAG signal nSRST is described because it can be controlled by JTAG equipment nTRST Test reset from JTAG equipment This active low open collector is used to reset the JTAG port and the associated debug circuitry on the ARM940T processor It is asserted at power up by each module and can be driven by the JTAG equipment This signal is also used in configuration mode to control the programming pin nPROG on FPGAs ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 25 Hardware Description Table 3 4 JTAG signal description continued Name Description Function RTCK Return TCK to JTAG equipment Some devices sample TCK for example a synthesizable core with only one clock and this has the effect of delaying the time at which a component actually captures data RTCK is a mechanism for returning the sampled clock to the JTAG equipment so
54. ore module The bits are encoded as follows 00 Reserved 01 Reserved 10 2 cycles default 11 3 cycles Note Before the SDRAM is used it is necessary to read the SPD memory and program the CM_SDRAM register with the parameters indicated in Table 4 8 If these values are not correctly set then SDRAM accesses may be slow or unreliable See CM_SPD 0x10000100 to 0x100001FC on page 4 16 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 4 15 Programmer s Reference 4 3 8 CM SPD 0x10000100 to 0x100001FC This area of memory contains a copy of the SPD data from the SPD EEPROM on the DIMM Because accesses to the EEPROM are very slow the data is copied to this memory during board initialization to allow faster random access to the SPD data see Serial presence detect on page 3 6 The SPD memory contains 256 bytes of data the most important of which are as shown in Table 4 9 Table 4 9 SPD memory contents Byte Contents 2 Memory type 3 Number of row addresses 4 Number of column addresses 5 Number of banks 31 Module bank density MB divided by 4 18 CAS latencies supported 63 Checksum 64 71 Manufacturer 73 90 Module part number Check for valid SPD data as follows 1 Add together all bytes 0 to 62 2 Logically AND the result with OxFF 3 Compare the result with byte 63 If the two values match then the SPD data is valid Note A number o
55. posted into FIFO and the transfer on the system bus occurs some time later when that bus is available This means that system bus error responses to write transfers are not reported back to the processor as data aborts If the FIFO is full the processor receives a wait response until space becomes available Processor reads The data routing for processor reads from the system bus is illustrated in Figure 3 5 Processor core SDRAM SDRAM controller FIFO FIFO Motherboard Figure 3 5 Processor reads from the system bus For reads from the system bus the address and control information also pass through the FIFO The returned data from the system bus bypasses the FIFO The order of processor transactions is preserved on the system bus Any previously posted writes are drained from the FIFO that is completed on the system bus before the read transfer is performed The processor receives a wait response until the read transfer has completed on the system bus when it receives the data and any associated bus error response from the system bus For information about SDRAM addresses see SDRAM accesses on page 4 4 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 6 2 Motherboard accesses to SDRAM The second FIFO supports read and write accesses by system bus masters on the motherboard and other core modules to the local
56. processor The two FIFOs operate independently as described above and can be accessed at the same time This makes it possible for a local processor to read local SDRAM via the system bus through both FIFOs This feature can be used to support multiprocessor systems that share data in SDRAM because the processors can all access the same DRAM locations at the same addresses Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 6 4 System bus signal routing Module 3 Module 2 Module 1 Module 0 Motherboard The core module is mounted onto a motherboard via the connectors HDRA and HDRB As well as carrying all signal connections between the boards these provide mechanical mounting see Attaching the ARM Integrator CM920T to a motherboard on page 2 5 HDRA The signals on the HDRA connectors are tracked between the socket on the underside and the plug on the top so that pin 1 connects to pin 1 pin 2 to pin 2 and so on That is the signals are routed straight through HDRB A number of signals on the HDRB connectors are rotated in groups of four between the connectors on the bottom and top of each module This ensures that each processor or other bus master device on a module connects to the correct signals according to whether it is bus master 0 1 2 or 3 The ID for the bus master on a module is determined by the position of the module in the stack This signal rotation scheme i
57. rence This chapter describes the memory map and the status and control registers It contains the following sections Memory organization on page 4 2 Exception vector mapping on page 4 6 N Core module registers on page 4 7 Interrupt registers on page 4 19 ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 4 1 Programmer s Reference 4 1 4 1 1 Memory organization This section describes the memory map For a standalone core module the memory map is limited to local SSRAM SDRAM and core module registers For the full memory map of an Integrator development system which includes a motherboard you should refer to the user guide for the motherboard Core module memory map The core module has a fixed memory map which maintains compatibility with other ARM modules and Integrator systems Table 4 1 shows the memory map Table 4 1 ARM Integrator CM940T memory map nMBDET REMAP Address range Region size Description 0 0 0x00000000 to 0x0003FFFF 256KB Boot ROM on motherboard 0 1 0x00000000 to 0x0003FFFF 256KB SSRAM 1 X 0x00000000 to 0x0003FFFF 256KB SSRAM X X 0x00040000 to OXOFFFFFFF 256MB Local SDRAM X X 0x10000000 to 0x 10FFFFFF 16MB Core module registers 0 X 0x11000000 to OxFFFFFFFF 4GB to 272MB System bus address space 1 X 0x11000000 to OxFFFFFFFF 4GB to272MB Abort 4 1 2 Boot ROM and SSRAM accesses The boot ROM on the motherboard and the SSRAM on the core module share the
58. reset bit in the CM_CTRL register This generates the internal reset signal SWRST which generates nSRST and resets the whole system see CM_CTRL 0x1000000C on page 4 11 3 10 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description 3 6 System bus bridge The system bus bridge provides an asynchronous bus interface between the local system bus and system bus connecting the motherboard and other modules Inter module accesses are supported by two 16 x 74 bit FIFOs Each of the 16 entries in the FIFOs contains 32 bit data used for write transfers 32 bit address used for reads and writes 10 bit transaction control used for reads and writes 3 6 1 Processor accesses to the system bus The first FIFO supports read and write accesses by the local processor to the system bus which extends onto the motherboard and other modules Processor writes The data routing for processor writes to the system bus is illustrated in Figure 3 4 Processor core SDRAM gt SDRAM controller FIFO FIFO Motherboard Figure 3 4 Processor writes to the system bus ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 3 11 Hardware Description Write transactions from the processor to the system bus normally complete on the local memory bus in a single cycle The data address and control information associated with the transfer are
59. ribes the core module ID register bits Table 4 3 CM_ID register bit descriptions Bits Name Access Function 31 24 MAN Read Manufacturer 0x41 ARM 23 16 ARCH Read Architecture 0x00 Generic ARM7x0T or ARM9x0T 4 word SDRAM bursts 15 12 FPGA Read FPGA type 0x00 XC4036 11 4 BUILD Read Build value ARM internal use 3 0 REV Read Revision 0x0 Rev A 0x1 Rev B 4 3 2 CM_PROC 0x10000004 The core module processor register CM_PROC is a read only register that contains the value 0x00000000 This is provided for compatibility with processors that do not have a system control coprocessor CP15 For the ARM940T information about the processor can be obtained by reading coprocessor 15 register 0 CP15 c0 4 8 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference 4 3 3 CM_OSC 0x10000008 The core module oscillator register CM_OSC is a read write register that controls the frequency of the clocks generated by the two clock generators see Clock generators on page 3 17 In addition it provides information about processor bus mode setting 31 25 24 2322 2019 12 1110 87 0 Before writing to the CM_OSC register you must unlock it by writing the value Ox0000A05F to the CM_LOCK register After writing the CM_OSC register relock it by writing any value other than 0x0000A05F to the CM_LOCK register Table 4 4 describes the core module oscillator register bits Tab
60. ription CM IRO STAT 0x10000040 Read 3 bits Core module IRQ status register CM_IRQ_RSTAT 0x10000044 Read 3 bits Core module IRQ raw status register CM_IRQ_ENSET 0x 10000048 Read write 3 bits Core module IRQ enable set register CM_IRQ_ENCLR 0x 1000004C Write 3 bits Core module IRQ enable clear register CM_SOFT_INTSET 0x 10000050 Read write 1 bit Core module software interrupt set CM_SOFT_INTCLR 0x 10000054 Write 1 bit Core module software interrupt clear CM_FIQ_STAT Ox 10000060 Read 3 bits Core module FIQ status register CM_FIQ_RSTAT 0x 10000064 Read 3 bits Core module FIQ raw status register CM_FIQ_ENSET 0x 10000068 Read write 3 bits Core module FIQ enable set register CM_FIQ_ENCLR 0x 1000006C Write 3 bits Core module FIR enable clear register The IRQ and FIQ controllers each provide three registers for controlling and handling interrupts These are status register N raw status register enable register which is accessed using the enable set and enable clear locations The way that the interrupt enable clear and status bits function for each interrupt is illustrated in Figure 4 4 on page 4 20 and described in the following subsections The illustration shows the control for one IRQ bit The remaining IRQ bits and FIQ bits are controlled in a similar way ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved 4 19 Programmer s Reference Enable set Set Enable Enable clear
61. rovides a set of JTAG signals allowing third party JTAG debugging equipment to be used see JTAG signals on page 3 24 If you are debugging a development system with multiple core modules connect the Multi ICE hardware to the top core module ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 21 Hardware Description 3 8 1 JTAG scan path Figure 3 11 shows a simplified diagram of the scan path TDO Processor TDI core Multi ICE Core module TDO nMBDET Processor Core module TDI core HDRB HDRB TL Motherboard Figure 3 11 JTAG scan path simplified When the core module is used as a standalone development system the JTAG scan path is routed through the processor core and back to the Multi ICE connector When the core module is attached to a motherboard either directly or with other core modules the TDI signal from the top core module is routed down through the HDRB connectors to the motherboard The path is routed back up the stack through the processor core on each core module before being returned to the Multi ICE connector The motherboard detect signal nMBDET signal is used to control the routing for a standalone or an attached core module The PLDs and FPGAs are included in the scan chain when the core module is in configuration mode 3 22
62. rt reads and writes by the local processor core and by masters on the motherboard The SDRAM controller uses an alternating priority scheme to ensure that the processor core and motherboard have equal access see System bus bridge on page 3 11 3 4 3 Serial presence detect JEDEC compliant SDRAM DIMMs incorporate a Serial Presence Detect SPD feature This comprises a 2048 bit serial EEPROM located on the DIMM with the first 128 bytes programmed by the DIMM manufacturer to identify the following module type memory organization timing parameters The EEPROM clock SCL operates at 93 75kHz 24MHz divided by 256 The transfer rate for read accesses to the EEPROM is 100kbit s maximum The data is read out serially 8 bits at a time preceded by a start bit and followed by a stop bit This makes reading the EEPROM a very slow process because it takes approximately 27ms to read all 256 bytes However during power up the contents of the EEPROM are copied into 3 6 Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Hardware Description a 64 x 32 bit area of memory CM_SPD within the SDRAM controller The SPD flag is set in the SDRAM control register CM_SDRAM when the SPD data is available This copy can be randomly accessed at 0x 10000100 to 0x100001FC see CM_SPD 0x10000100 to 0x100001FC on page 4 16 Write accesses to the SPD EEPROM are not supported ARM DUI 0125A Copyright ARM Limited 1999 All r
63. ry because of the variety of module sizes and types available Writing a value to this register automatically updates the mode register on the SDRAM DIMM 31 20 19 16 15 12 11 NBANKS NCOLS me ex SPDOK MEMSIZE CASLAT Table 4 8 describes the SDRAM status and control register bits Table 4 8 CM SDRAM register Bits Name Access Function 31 20 Reserved Use read modify write to preserve value 19 16 NBANKS Read write Number of SDRAM banks Should be set to the same value as byte 5 of SPD EEPROM 15 12 NCOLS Read write Number of SDRAM columns Should be set to the same value as byte 4 of SPD EEPROM 11 8 NROWS Read write Number of SDRAM rows Should be set to the same value as byte 3 of SPD EEPROM 7 6 Reserved Use read modify write to preserve value 5 SPDOK Read This bit indicates that the automatic copying of the SPD data from the SDRAM module into CM_SPDMEM is complete 1 SPD data ready 0 SPD data not available Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Programmer s Reference Table 4 8 CM_SDRAM register continued Bits Name Access Function 4 2 MEMSIZE Read write These bits specify the size of the SDRAM module fitted to the core module The bits are encoded as follows 000 16MB 001 32MB 010 64MB default 011 128MB 100 256MB 101 Reserved 110 Reserved 1 0 CASLAT Read write These bits specify the CAS latency set for the c
64. s bus B 31 0 Not used C 31 0 System control bus See remainder of table C 31 16 Not used C15 BLOK Locked transaction C14 BLAST Last response C13 BERROR Error response C12 BWAIT Wait response Cll BWRITE Write transaction C10 Not used C 9 8 BPROT 1 0 Transaction protection type C7 Not used C 6 5 BURST 1 0 Transaction burst size C4 Not used C 3 2 BSIZE 1 0 Transaction width C 1 0 BTRANI1 0 Transaction type D 31 0 System data bus System data bus Note Table A 1 shows signal descriptions for an AMBA ASB bus implementation ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved A 3 Signal Descriptions A 2 HDRB The HDRB plug and socket have slightly different pinouts as described below A 2 1 HDRB socket pinout Figure A 2 shows the pin numbers of the socket HDRB on the underside of the core module viewed from above the core module 1 61 2 GND FO 62 3 El F1 63 4 E2 F2 64 5 E3 GND 65 6 GND F3 66 7 E4 F4 67 8 E5 F5 68 9 E6 GND 69 10 GND F6 70 11 E7 F7 71 12 E8 F8 72 13 E9 GND 73 14 GND F9 74 15 E10 F10 75 16 E11 F11 76 17 E12 GND 77 18 GND F12 78 19 E13 F13 78 20 Et4 F14 80 21 EIS GND 81 22 GND F15 82 23 E16 F16 83 24 E17 F17 84 25 E18 GND 85 26 GND F18 86 27 E19 F19 87 28 E20 F20 88 29 E21 GND 89 30 GND F21 90 31 E22 F22 91 a ES ON F gt 92 33 E24 GND 93 34 GND F24 94 35 E25 i F25 DNS 36 E26 F26 96 37 E27 GND 97 38 a CN a F27 98 39 E28 F28 99 40 E2
65. s illustrated in Figure 3 8 To on board devices Figure 3 8 Signal rotation on HDRB ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 3 15 Hardware Description The example in Figure 3 8 illustrates how a group of four signals labelled A B C and D are routed through a group of four connector pins up through the stack It highlights how signal C is rotated as it passes up through the stack and only utilized on module 2 All four signals are rotated and utilized in a similar way as follows signal A on core module 0 signal B on core module 1 N signal C used on core module 2 signal D used on core module 3 For details of the signals on the HDRB connectors see HDRB on page A 4 Note The JTAG signals are discussed in Multi ICE support on page 3 21 3 6 5 Bus operating modes The bus operating modes are programmed by writing to coprocessor 15 register 1 within the ARM940T microprocessor core The Integrator system supports asynchronous and FastBus clocking little endian addressing The Integrator system does not support synchronous clocking big endian addressing For details of how to set the bus operating parameters refer to the ARM940T Technical Reference Manual 3 16 O Copyri
66. sets and debug Chapter 4 Programmer Reference Read this chapter for a description of the header memory map and registers Appendix A Signal Descriptions Refer to this appendix for a description of the signals on the HDRA and HDRB connectors Appendix B Specifications Refer to this appendix for electrical timing and mechanical specifications viii Copyright ARM Limited 1999 All rights reserved ARM DUI 0125A Typographical conventions The following typographical conventions are used in this document bold Highlights ARM processor signal names within text and interface elements such as menu names May also be used for emphasis in descriptive lists where appropriate italic Highlights special terminology cross references and citations typewriter Denotes text that may be entered at the keyboard such as commands file names and program names and source code typewriter Denotes a permitted abbreviation for a command or option The underlined text may be entered instead of the full command or option name typewriter italic Denotes arguments to commands or functions where the argument is to be replaced by a specific value typewriter bold Denotes language keywords when used outside example code ARM DUI 0125A O Copyright ARM Limited 1999 All rights reserved ix Further reading ARM publications Other publications This section lists related publications by ARM Limited and other companies that m
67. that the clock is not advanced until the synchronizing device captured the data In adaptive clocking mode Multi ICE is required to detect an edge on RTCK before changing TCK In a multiple device JTAG chain the RTCK output from a component connects to the TCK input of the down stream device The RTCK signal on the module connectors HDRB returns TCK to the JTAG equipment If there are no synchronizing components in the scan chain then it is unnecessary to use the RTCK signal and it is connected to ground on the motherboard TCK Test clock from JTAG equipment TCK synchronizes all JTAG transactions TCK connects to all JTAG components in the scan chain Series termination resistors are used to reduce reflections and maintain good signal integrity TCK flows down the stack of modules and connects to each JTAG component However if there is a device in the scan chain that synchronizes TCK to some other clock then all down stream devices are connected to the RTCK signal on that component see RTCK TDI Test data in from JTAG equipment TDI goes down the stack of modules to the motherboard and then back up the stack labelled TDO connecting to each component in the scan chain TDO Test data out to JTAG equipment TDO is the return path of the data input signal TDI The module connectors HDRB have two pins labelled TDI and TDO TDI refers to data flowing down the stack and TDO to data flowing up the stack The JTA
68. unted on a motherboard the SDRAM is mapped to appear at the aliased module memory region of the combined Integrator system bus memory map The SDRAM can be accessed by all bus masters at its alias location and accessed by the local processor at both its local and alias locations The system bus address for a core module is automatically controlled by its position in the stack see Core module ID on page 2 6 Figure 4 3 shows the local and alias address of the SDRAM on four core modules System bus address OxBFFFFFFF SDRAM core module 3 0xB0000000 OXAFFFFFFF SDRAM core module 2 0xA0000000 All masters Ox9FFFFFFF SDRAM core module 1 0x90000000 Ox8FFFFFFF SDRAM core module 0 0x80000000 Local address OxOFFFFFFF 0x00000000 OxOFFFFFFF 0x00000000 OxOFFFFFFF 0x00000000 OxOFFFFFFF 0x00000000 Module 3 Module 2 Module 1 Module 0 Figure 4 3 Core module local and alias addresses By reading the CM_STAT register a processor can determine which core module it is on and therefore the alias location of its own SDRAM see CM_STAT 0x10000010 on page 4 12 ARM DUI 0125A Copyright ARM Limited 1999 All rights reserved 4 5 Programmer s Reference 4 2 Exception vector mapping The convention for ARM cores is to map the exception vectors to begin at address 0 However the ARM940T core allows the vectors to be moved to OxFFFF0000 by writing to the V bit

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