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AMD 10 Computer Hardware User Manual

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1. Symbol Parameter Condition Min Max Units Notes 0 5 x V 0 5xV VREF DC Input Reference Voltage CC CORE CC CORB mV 1 50 50 lyREF LEAK VREF Tristate Leakage Pullup VIN VREF Nominal 100 VREF LEAK_N VREF Tristate Leakage Pulldown ViN VREF Nominal 100 uA Vin Input High Voltage VRer 200 Vcc core 500 mV Vi Input Low Voltage 500 Vger 200 mV Vin VSS Tristate Leakage Pullu IN 1 mA LEAK_P 5 Ground N Tristate Leakage Pulldown VN 7 Vcc cont 1 mA Nominal CiN Input Pin Capacitance 4 7 pF RoN Output Resistance 0 90 x 1 1 X RsetN P Q 2 Rsetp Impedance Set Point P Channel 40 70 Q 2 Impedance Set Point N Channel 40 70 2 Notes nominally set 50 with actual values that are specific to motherboard design implementation Vcr must be created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed above 2 Measured at Vcc CORE 2 24 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications Chapter 6 31994A 1 August 2004 Electrical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 7 1 7 2 Table 5 This chapter describes the electrical characteristics that apply to all desktop AMD Sempron processors model 10 with 256K L2 cache Conventions Th
2. Organic Pin Grid Array PBGA Plastic Ball Grid Array PA Physical Address PCI Peripheral Component Interconnect PDE Page Directory Entry PDT Page Directory Table PGA Pin Grid Array PLL Phase Locked Loop PMSM Power Management State Machine POS Power On Suspend POST Power On Self Test RAM Random Access Memory ROM Read Only Memory RXA Read Acknowledge Queue SCSI Small Computer System Interface SDI System DRAM Interface SDRAM Synchronous Direct Random Access Memory SIMD Single Instruction Multiple Data SIP Serial Initialization Packet SMbus System Management Bus SPD Serial Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TTL Transistor Transistor Logic AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Appendix B Conventions and Abbreviations 87 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Table 27 Acronyms continued Abbreviation Meaning VAS Virtual Address Space VPA Virtual Page Address VGA Video Graphics Adapter USB Universal Serial Bus ZDB Zero Delay Buffer 88 Appendix B Conventions and Abbreviations 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Related Publications These documents provide helpful information about the AMD Sempron pro
3. 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet The formulas in Equation 3 and Equation 4 can be used to calculate the temperature offset for temperature sensors that do not employ series resistance cancellation The result is added to the value measured by the temperature sensor Contact the vendor of the temperature sensor being used for the value of n 7s Refer to the document On Die Thermal Diode Characterization order 25443 for further details Equation 3 shows the equation for calculating the lumped ideality factor nr lumped in sensors that do not employ series resistance cancellation Rr high TA Liow 414 spec 273 15 28 low n lumped n actual 5 Equation 4 shows the equation for calculating temperature offset Toffset in sensors that do not employ series resistance cancellation oae 273 15 1 n impe 4 rs Equation 5 is the temperature offset for temperature sensors that utilize series resistance cancellation Add the result to the value measured by the temperature sensor Note that the value of ng rs in Equation 5 may not equal the value used Equation 4 Cus 273 15 1 E 65 offset Ny TS Appendix A Thermal Diode Calculations 81 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 82 Appendix A Thermal Diode Calc
4. AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location 31994A 1 August 2004 Pin Name Description L P R Pin Name Description L P R 1 No Pin page 72 B24 Vcc coRE SADDOUT 12 P O G B6 VSS A5 SADDOUT 5 P O G 1828 Vcc_coRE A7 SADDOUT 3 P O 830 VSS A9 SDATA 55 P B P B2 AN SDATA 61 P B P 834 5 A13 SDATA 53 P B G B36 Vcc 15 SDATA 63 P B SADDOUT 7 AU SDATA 62 SADDOUT 9 P 016 A19 NC Pin page 72 5 SADDOUT 8 A21 SDATA 57 B 7 SADDOUT 2 P O G 25 SDATA 39 P BJ G 9 SDATA 54 P B P A25 SDATA 35 P By SDATAOUTCLK 3 27 SDATA 34 P B P Ci NC Pin page 72 A29 SDATA 44 G 15 SDATA 51 B P A31 NC Pin page 72 C17 SDATA 60 P B G A35 SDATAOUTCLK 2 P O P C19 SDATA 59 A35 SDATA 40 P G C21 SDATA 56 P BG A37 SDATA 30 P B P C23 SDATA 37 P B2 VSS C25 SDATA 47 P B G B4 Vcc coRE C27 SDATA 58 PIBIG B6 55 C29 SDATA 45 PIBIG B8 Vcc conE C531 SDATA 43 B10 VSS 55 SDATA 42 PIBIG B12 Vcc C35 SDATA 41 B14 VSS C37 SDATAOUTCLK 1 AE P O G B16 Vcc coRE D2 Vcc 18 VSS
5. 68 APIC Pins PICCLK PICD 1 0 68 GCEKEWDRST PH PE OUR GaAs 68 CLKIN RSTCLK SYSCLK Pins 69 CONNECT ed RESI te Es 69 COREFB and 69 CPU PRESENCES vo DERE PESE 69 DBRDY and DBREQ 69 PNG 69 EID 3 0 PInS 4 26 23 Rex upa REUS 70 FSB Sense 1 0 Pins 71 TS PT S2 2 L dae uos p nir atur aa acu cdita Qa youre Wie ect 71 IGNNES Pit 222 buts rii 71 INLIS BIB cote 44233 tete eet da X eeu Ss 71 INTR PH sen E CR DRM C UU 72 RR EE Where eu 72 K7CLKOUT and K7CLKOUT Pins 72 5 MUR Se Ee Se E 72 SR e s mati US 72 Table of Contents 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet NMI Piti 72 PGA Orientation 72 PLL Bypass and Test 72 PWROK PiInDn 2 one NEPOTES ees 73 SADDIN 1 0 and SADDOUT 1 0 Pins 73 Scati PIS s seem RU er 73 SMBEPI ce a eee eee 73 ics ke UNES IQ qued ees 73 SYSCLK and 5 5 73 THERMDA and THERMDC
6. This chapter describes the power management control system of the AMD Sempron Processor Model 10 The power management features of the processor are compliant with the ACPI 1 0b and ACPI 2 0 specifications Power Management States The AMD Sempron processor model 10 supports low power Halt and Stop Grant states These states are used by advanced configuration and power interface ACPI enabled operating systems for processor power management Figure 3 shows the power management states of the processor The figure includes the ACPI Cx naming convention for these states Execute HLT 10 49481881 C1 d pee 5 19415 1 aqold 55 71415 e Stop Grant Cache Snoopable I ing Prob ncoming Probe Stop Grant Cache Not Snoopable Sleep Probe Serviced Legend Hardware transitions Software transitions The AMD Athlon System Bus is connected during the following states 1 The Probe state 2 During transitions between the Halt state and the C2 Stop Grant state 3 During transitions between the C2 Stop Grant state and the Halt state 4 CO Working state Figure 3 AMD Sempron Processor Model 10 Power Management States Chapter 4 Power Management AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Working State Halt State Stop Grant
7. 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 8 Signal and Power Up Requirements The AMD Sempron processor model 10 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges 8 1 Power Up Requirements Signal Sequence and Figure 12 shows the relationship between key signals in the Timing Description system during a power up sequence This figure details the requirements of the processor 3 5 V Supply VCCA 2 5 V for PLL VCC CORE Processor Core Warm reset RESET 6 condition RA 2 s NB_RESET Y d PWROK FID 3 0 System Clock Figure 12 Signal Relationship Requirements During Power Up Sequence Notes 1 Figure 12 represents several signals generically by using names not necessarily consistent with any pin lists or schematics 2 Requirements 1 8 in Figure 12 are described in Power Up Timing Requirements on page 40 Chapter 8 Signal and Power Up Requirements 39 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Power Up Timing Requirements The signal timing requirements are as follows 1 RESET must be asserted before PWROK is asserted The AMD Sempron processor model 10 does not set the correct clock multiplier if PWROK is asserted prior to a RESET assertion It is recommended that RESET be a
8. Vcc coRE B20 Vcc coRE D VSS B22 VSS 08 60 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location continued Pin Name Description L P R Pin Name Description L P R 010 VSS EBS NC Pin page 72 E 012 Vcc 85 SDATAB1 PB 014 VSS 87 SDATA 22 P B G 016 Vcc coRE F2 VSS D18 VSS eem VSS D20 Vcc VSS 022 VSS 8 NC Pin page 72 024 Vcc coRE IFO 55 026 VSS F12 Vcc ee 028 Vcc coRE FM VSS 030 VSS FI6 Vcc ra D32 Vcc come I Fi8 VSS se 054 VSS F20 Vcc D36 55 F22 VSS EN El SADDOUT 11 P o 4 Vc core 234 2 E3 SADDOUTCLK P O G F26 VSS E5 SADDOUT 4 P O P F28 Q 7 SADDOUT 6 P O G F30 NC Pin page 72 E9 SDATA 52 P B P F32 Vcc core E11 SDATA 50 P B P Vcc E13 SDATA 49 4 P B G F36 15 SDATAINCLK 3 SADDOUT
9. 73 VCCA PIn u praus esr PME mctu S ve Ets 73 VID 4 0 Pins 74 VREESYS Pit iz assaka T ev 74 ZN and ZP Pins aeta e c RAI X a RE 75 Ordering Information 77 Standard AMD Sempron Processor Model 10 Products 77 Appendix A Thermal Diode Calculations 79 Ideal Diode Equation 79 Temperature Offset 80 Appendix B Conventions and Abbreviations 83 Stenals and Bits u ar a russe pier Rega EL D XR E E ea 83 Data 84 Abbreviations and 85 Related 89 Table of Contents AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 vi Table of Contents 31994A 1 August 2004 List of Figures AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Figure 1 Typical AMD Sempron Processor Model 10 System Block Diagr ni rok ue eR edt ne gis RR ERE 4 Figure 2 Logic Symbol Diagram 7 Figure 3 AMD Sempron Processor Model 10 Power Management States 9 Figure 4 AMD Athlon System Bus Disconne
10. episuiojyog 01 polN 10 5 2044 uoJdures 91 814 nv w w iv ov av av ov av vv z A X M 1 5 i 3 q jaj v LE oms EHYS LNS 6 05 140 ud N 90 9105 Iud 9005 605 19805 1005 xs LE 95 SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA 9t vis INS 0 005 045 5 Uns 105 N WOS A A 140 ws SE SSA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA SSA vt DIS UNS SHNS 0105 805 N 0805 L405 Ya suas 9005 6105 ZA N 00 EE 43 SSA SSA SSA N SSA DA SSA DA SSA DA SSA DA SSA DA N DA DA DA 43 1005 snmus 089 N N N N N N N N N N N ZA 18 195 N IN SSA DA SSA DA SSA DA SSA N N N SSA SSA 05 LENS ONS o N ww 66 SSA SSA SSA ON DA DA DA 82 LT ow N N N 20165 ges veas 46 9 DA DA DA DA SSA SSA SSA SSA 9 N N M ON 0 seras 60 v SSA SSA SSA SSA DA DA DA DA LA EZ DNN YA N IS 1 805 sem EZ 44 DA DA DA DA SSA SSA SSA SSA 44 1 OL um N 9eH0S 9905 15 10 A nog 00 SSA SSA S
11. AMD Sempron Processor Model 10 With 256K L2 Cache Data Sheet Sempron 2004 Advanced Micro Devices Inc rights reserved The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and prod uct descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other applica tion in which the failure of AMD s product could create a situation where per sonal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice Tra
12. Processor Model 10 with 256K L2 Cache Specifications on page 21 Table 3 333 FSB AMD Athlon System Bus AC Characteristics on page 23 Table 4 333 FSB AMD Athlon System Bus DC Characteristics on page 24 and CLKFWDRST Pin on page 68 Chapter 7 Electrical Data 25 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Table5 Interface Signal Groupings continued SCANSHIFTEN SCANINTEVAL ANALOG Signal Group Signals Notes See General AC and DC Characteristics on page 32 INTR Pin on page 72 NMI Pin on page 72 SMI Southbridge INTR NMI SMI INIT 20 Pin on page 73 INIT Pin page 71 A20M Pin 8 FERR IGNNE STPCLK FLUSH on page 68 FERR Pin on page 69 IGNNE Pin on page 71 STPCLK Pin on page 73 and FLUSH Pin on page 71 JTAG TMS TCK TRST TDI TDO See General AC and DC Characteristics on page 32 PLLBYPASS PLLTEST PLLMONI See General AC and DC Characteristics on page 32 Test PLLMON2 SCANCLK1 SCANCLK2 PLL Bypass and Test Pins on page 72 Scan Pins on page 75 Analog Pin on page 68 Miscellaneous DBREQ DBRDY PWROK See General AC and DC Characteristics on page 32 DBRDY and DBREQ Pins on page 69 PWROK Pin on page 73 See APIC Pins AC and DC Characteristics on page 37
13. ACPI Meaning Advanced Configuration and Power Interface AGP Accelerated Graphics Port APCI AGP Peripheral Component Interconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input Output System BIST Built In Self Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Array DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Direct Random Access Memory EIDE Enhanced Integrated Device Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In First Out GART Graphics Address Remapping Table HSTL High Speed Transistor Logic IDE Integrated Device Electronics ISA Industry Standard Architecture JEDEC Joint Electron Device Engineering Council Joint Test Action Group 86 Appendix B Conventions and Abbreviations 31994A 1 August 2004 Table 27 Acronyms continued Abbreviation Meaning LAN Large Area Network LRU Least Recently Used Low Voltage Transistor Transistor Logic MSB Most Significant Bit MTRR Memory Type and Range Registers MUX Multiplexer Non Maskable Interrupt
14. AJ33 SD 13 SDATA 13 AA37 SAO 0 SADDOUT 0 J SD 14 SDATA 14 AC35 SAO 1 SADDOUT 1 J3 SD 15 SDATA 15 35 2 SADDOUT 2 C7 SD 16 16 037 SAO 3 SADDOUT 3 A7 SD 17 SDATA 17 035 0 4 SADDOUTLI4 E5 SD 18 SDATA 18 N37 SAO 5 SADDOUT 5 A5 SD 19 SDATA 19 J33 SAO 6 SADDOUT 6 E7 SD 20 SDATA 20 G33 SAO 7 SADDOUT 7 4 CI SD 21 SDATA 21 G37 SAO 8 SADDOUT 8 C5 SD 22 SDATA 22 E37 SAO 9 SADDOUT 9 C3 SD 23 23 G35 SAO 10 SADDOUT 10 Gl SD 24 SDATA 24 Q33 SAO 11 SADDOUT 11 El SD 25 SDATA 25 N33 SAO 12 SADDOUT 12 A3 SD 26 SDATA 26 L33 SAO 13 SADDOUT 13 G5 SD 27 SDATA 27 N35 SAO 14 SADDOUT 14 G3 SD 28 SDATA 28 L37 SAOC SADDOUTCLK E3 SD 29 29 J37 SCNCK1 SCANCLK1 51 0 30 SDATA 30 A37 SCNCK2 SCANCLK2 55 031 SDATA 31 E35 SCNINV SCANINTEVAL 53 SD 32 32 E31 SCNSN SCANSHIFTEN Q5 SD 33 SDATA 33 E29 SD 0 SDATA 0 5 SD 34 SDATA 34 A27 SD 1 SDATA 1 W37 SD 35 35 25 SD 2 SDATA 2 W35 SD 36 SDATA 36 E21 54 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin Abbreviation Full Name Pin 0457 SDATA 37 C23 SDOC 2 SDATAOUTCLK 2 A33 SD 38 SDATA 38
15. For more information refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 The FID 3 0 signals are open drain processor outputs that are pulled High on the motherboard and sampled by the chipset to determine the SIP serial initialization packet that 1s sent to the processor The FID 3 0 signals are valid after PWROK is asserted The FID 3 0 signals must not be sampled until they become valid See the AMD Athlon and AMD Duron M System Bus Specification order 21902 for more information about Serialization Initialization Packets and SIP protocol The processor FID 3 0 outputs are open drain and 2 5 V tolerant To prevent damage to the processor do not pull these 70 Pin Descriptions Chapter 10 31994A 1 August 2004 FSB Sense 1 0 Pins FLUSH Pin IGNNE Pin INIT Pin AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet signals High above 2 5 V Do not expose these pins to a differential voltage greater than 1 60 V relative to the processor core voltage Refer to _2 5 Generation Circuit found in the section Motherboard Required Circuits of the AMD Athlon Processor Motherboard Design Guide order 24363 for the required supporting circuitry See Frequency Identification FID 3 0 on page 27 for the DC characteristics for FID 3 0 FSB Sense 1 0 pins are either open circuit logic level of 1
16. ZN AC5 and ZP AE5 are the push pull compensation circuit pins In Push Pull mode selected by the SIP parameter SysPushPull asserted ZN is tied to with a resistor that has a resistance matching the impedance Zo of the transmission line ZP is tied to VSS with a resistor that has a resistance matching the impedance Zo of the transmission line Chapter 10 Pin Descriptions 75 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 76 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet n Ordering Information Standard AMD Sempron Processor Model 10 Products AMD standard products are available in several operating ranges The ordering part numbers OPN are formed by a combination of the elements as shown in Figure 17 SD C 2800 D U T 3 D s Front Side Bus D 333 Size of L2 Cache 3 256 Kbytes Die Temperature T 90 C Operating Voltage U 1 60 V Package Type D OPGA Model Number 2800 operates at 2000 MHZ 2200 operates at 1500 MHZ Maximum Power C Desktop Processor Architecture Segment SD AMD Sempron Processor Model 10 with QuantiSpeed Architecture for Desktop Products Note 1 Spaces are added to the number shown above for viewing clarity only 2 This processor is available only with an advanced 333 FSB Fi
17. or are pulled to ground logic level of 0 on the processor package with a 1 resistor In conjunction with a circuit on the motherboard these pins may be used to automatically detect the front side bus FSB setting of this processor Proper detection of the FSB setting requires the implementation of a pull up resistor on the motherboard Refer to the AMD Athlon Processor Based Motherboard Design Guide order 24363 and the technical note FSB Sense Auto Detection Circuitry for Desktop Processors 4 TN26673 for more information Table 22 is the truth table to determine the FSB of desktop processors Table 22 Front Side Bus Sense Truth Table FSB Sense 1 FSB Sense 0 Bus Frequency 1 0 RESERVED 1 1 133 MHz 0 1 166 MHz 0 0 200 MHz The FSB Sense 1 0 pins are 3 3 V tolerant FLUSH must be tied to with a pullup resistor If a debug connector is implemented FLUSH is routed to the debug connector IGNNEZ is an input from the system that tells the processor to ignore numeric errors INIT is an input from the system that resets the integer registers without affecting the floating point registers or the internal caches Execution starts at 0 FFFF FFFOh Chapter 10 Pin Descriptions 71 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 INTR Pin JTAG Pins K7CLKOUT and K7CLKOUT Pins Key Pins NC Pins NMI
18. outputs are used to dictate the Vcc voltage level The VID 4 0 pins are strapped to ground or left unconnected on the processor package The VID 4 0 pins are pulled up on the motherboard and used by the DC DC converter The VID codes and corresponding voltage levels are shown in Table 23 Table 23 VID 4 0 Code to Voltage Definition VID 4 0 Vcc cont V VID 4 0 Vcc V 00000 1 850 10000 1 450 00001 1 825 10001 1 425 00010 1 800 10010 1 400 00011 1 775 10011 1 575 00100 1 750 10100 1 550 00101 1 725 10101 1 325 00111 1 675 10111 1 275 01000 1 650 11000 1 250 01001 1 625 11001 1 225 01010 1 600 11010 1 200 01011 1 575 11011 1 175 01100 1 550 11100 1 150 01101 1 525 11101 1 125 01110 1 500 11110 1 100 01111 1 475 11111 No CPU For more information see the Required Circuits chapter of the AMD Athlon M Processor Based Motherboard Design Guide order 24363 VREFSYS W5 drives the threshold voltage for the system bus input receivers The value of VREFSYS is system specific In addition to minimize Vcc copre noise rejection from VREFSYS include decoupling capacitors For more information see the AMD Athlon M Processor Based Motherboard Design Guide orderit 24363 74 Pin Descriptions Chapter 10 31994A 1 August 2004 ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
19. www amd com Table 13 shows the AMD Sempron processor model 10 characteristics of the on die thermal diode For information about calculations for the ideal diode equation and temperature offset correction see Appendix A Thermal Diode Calculations on page 77 Table 13 Thermal Diode Electrical Characteristics Symbol 1 Nom Max Units Notes l Sourcing current 5 300 pA 1 nt lumped pes ideality 1 00000 1 00374 1 00900 2 3 4 Nf actual Actual ideality factor 1 00261 3 4 Ry Series Resistance 0 93 Q 3 4 Notes 1 The sourcing current should always be used in forward bias only 2 Characterized at 95 C with a forward bias current pair of 10 pA and 100 uA AMD recommends using a minimum of two sourcing currents to accurately measure the temperature of the thermal diode 3 Not 100 tested Specified by design and limited characterization 4 The lumped ideality factor adds the effect of the series resistance term to the actual ideality factor The series resistance term indicates the resistance from the pins of the processor to the on die thermal diode The value of the lumped ideality factor depends on the sourcing current pair used Chapter 7 Electrical Data 35 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Thermal Protection Characterization The following section describes parameters relating to thermal protection
20. 1 August 2004 2 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Interface Signals 2 1 2 2 This section describes the interface signals utilized by the AMD Sempron processor model 10 Overview The AMD Athlon system bus architecture is designed to deliver excellent data movement bandwidth for next generation x86 platforms as well as the high performance required by enterprise class application software The system bus architecture consists of three high speed channels a unidirectional processor request channel a unidirectional probe channel and a 64 bit bidirectional data channel source synchronous clocking and a packet based protocol In addition the system bus supports several control clock and legacy signals The interface signals use an impedance controlled push pull low voltage swing signaling technology contained within the Socket A socket For more information see AMD Athlon System Bus Signals on page 6 Chapter 10 Pin Descriptions on page 49 and the AMD Athlon and AMD Duron System Bus Specification order 21902 Signaling Technology The AMD Athlon system bus uses a low voltage swing signaling technology that has been enhanced to provide larger noise margins reduced ringing and variable voltage levels The signals are push pull and impedance compensated The signal inputs use differential receivers that require a reference voltage The reference sign
21. 10 PIOJP E17 SDATA 48 P B P G SADDOUT 14 P O G E19 SDATA D58 B G G SADDOUT 1 P O E21 SDATA 36 P B PG Key Pin page 72 E23 SDATA 46 P B P G9 Key Pin page 72 E25 NC Pin page 72 G NC Pin page 72 gee E27 SDATAINCLK 2 P 1 G 613 NCPin page72 E29 SDATA 33 P B P G15 Key Pin page 72 E31 SDATA 32 P B P Key Pin page 72 Chapter 10 Pin Descriptions 61 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location continued 31994A 1 August 2004 Pin Name Description L P R Pin Name Description L P R G19 NC Pin page 72 NP RR SOLAR NC Pin page 72 8 G21 NC Pin page 72 1117 VID 4 page 74 0 0 G23 Key Pin page 72 NC Pin page 72 G25 KeyPin page 72 1113 SDATA 19 P B G G27 NCPin page72 1055 SDATAINCLK I P l P G29 NC Pin page 72 J37 SDATA 29 P G31 NC Pin page 72 VSS G33 SDATA 20 P B 5 lt G35 SDATA 23 P B G K6 VSS G37 SDATA 21 G K8 NC Pin page 72 H2 Vcc_core K30 NCPin page72 H4 Vcc coRE 2 Vcc cone H6 NC Pin pa
22. 25 27 29 31 33 35 37 A 234267 840 42 a e a BOTTOM VIEW A1 CORNER SEE NOTES TOP VIEW rp COMPONENTS P i de PADS L N k 4 A1 T me T L Nx b 0064 G c A 8 2N A SIDE VIEW GENERAL NOTES 1 All dimensions are specified in millimeters mm 2 Dimensioning and tolerancing per ASME Y14 5M 1994 This corner is marked with a triangle on both sides of the package to identify the pin A1 corner for orientation purposes Symbol M determines pin matrix size and N is number of pins AN Dimension b is measured at maximum solder pin diameter on a plane parallel to datum C Figure 13 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Diagram Chapter 9 Mechanical Data 45 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 9 3 AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Dimensions Table 18 shows the part number 27493 OPGA package dimensions in millimeters assigned to the letters and symbols shown in the 27493 package diagram Figure 14 on page 47 Table 18 Dimensions for the AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Letter or Minimum Maximum Letteror Minimum Maximum Symbol Dimension Dimension Symbol Dimension Dimension D E 49 27 49 78 G H 4 50 DWEI 45 72 BSC A 1 9
23. 6 1 ns 5 Input Time to Acquire 20 0 ns 7 8 Input Time to Reacquire 40 0 ns 9 15 TgisE Signal Rise Time 1 0 3 0 V ns 6 TFALL Signal Fall Time 1 0 3 0 V ns 6 Pin Capacitance 4 12 pF Tvaup Time to data valid 100 ns 14 Notes 1 Characterized across DC supply voltage range 2 Values specified at nominal cogg Scale parameters between Vec coge minimum and cogg maximum 3 lg and are measured at Vo maximum and minimum respectively 4 Synchronous inputs outputs are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized Z asynchronous operation the signal must persist for this time to enable capture 8 This value assumes RSTCLK period is 10 ns gt TBIT 2 fRST 9 The approximate value for standard case in normal mode operation This value is dependent on RSTCLK frequency divisors Low Power mode and core frequency Reassertions of the signal within this time are not guaranteed to be seen by the core This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase This value assumes RSTCLK and K7CLKOUT are running at the same frequency though the processor is capable of other configurations Time to valid is for any open drain pins See requirements 7 and 8 in the Power Up Timing Requirements chapter for more information Chapter
24. 7 Electrical Data 33 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 7 11 Open Drain Test Circuit Figure 11 is a test circuit that may be used on automated test equipment ATE to test for validity on open drain pins Refer to Table 12 General AC and DC Characteristics on page 32 for timing requirements Vrermination 500 3 Open Drain Pin lo Output Current Notes Viermination 1 2 V for VID and FID pins Vrermination 1 0 V for APIC pins 2 lgj 6 mA for VID and FID pins Io 9 MA for APIC pins Figure 11 General ATE Open Drain Test Circuit 34 Electrical Data Chapter 7 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 7 12 Thermal Diode Characteristics Thermal Diode Electrical Characteristics The AMD Sempron processor model 10 provides a diode that can be used in conjunction with an external temperature sensor to determine the die temperature of the processor The diode anode THERMDA and cathode are available as pins on the processor as described in THERMDA and THERMDC Pins on page 73 For information about thermal design for the AMD Sempron processor model 10 including layout and airflow considerations see the AMD Processor Thermal Mechanical and Chassis Cooling Design Guide order 23794 and the cooling guidelines on http
25. J2 pow JOHL ou n 1 DA DA DA DA 105592014 GINV sp 5 14 140s N VOHL 205 ANINDS pw SSA SSA SSA SSA DA DA DA DA O suns Lus visas N NJ NSIOS 0 4 DA DA DA DA SSA SSA SSA SSA d N 5 155 sus N NJ 4 N W SSA SSA SSA SSA DA DA DA DA W 1 ON 905 ON elan Lolan 1 y DA DA DA N N SSA SSA SSA y 14205 6105 N N 1405 05 f H SSA SSA N N N SSA DA SSA DA SSA DA SSA DA N N N DA DA H 9 5 5 00405 N N N NJ N N N N NJ NJ EL OVS 140 9 1 DA DA DA N DA SSA DA SSA DA SSA DA SSA DA SSA N SSA SSA SSA d 3 085 16805 N 105 N 9 0 9205 8905 ZA 06 6005 05405 75 05 9 0 S 05 805 us 1 4 SSA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA DA q 2 10005 140 8510 10405 1505 9585 6905 09405 15805 N 200 veis 05 6 0 S ows 9 8 DA SSA DA SSA IDA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA 8 V oe as Ov as 24000 N YERS AH 15405 N 79405 ENOS 5505 19405 5 05 05 ze 9 se ve ce ze te oe oz ez zz sz vz ez L oz or a af of st m et 6 8 4 9 s r z l Chapter 10 Pin Descriptions 50 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004
26. NC AA5 NC AN7 NC AA31 NC AN9 NC 7 ANTI NC AC31 NC AN25 NC AD8 NC AN27 NC AD30 NMI AN3 NC AE7 PICCLK NI NC AEST PICD 0 PICD 0 N3 NC AF6 PICD 1 PICD 1 N5 NC AF8 PLBYP PLLBYPASS AJ25 NC AF10 PLBYC PLLBYPASSCLK 15 NC AF28 PLBYC PLLBYPASSCLK AL15 NC AF30 PLMNI AN13 NC AF32 PLMN2 PLLMON2 AL13 NC AG5 PLIST PLLTEST AG NC AG19 PRCRDY PROCREADY AN23 NC 21 PWROK 23 RESET AG3 NC AG25 RCLK RSTCLK AN19 NC AH8 RCLK RSTCLK AL19 NC AJ7 SAI 0 SADDIN 0 AJ29 NC AJ9 SAI 1 SADDIN 1 AL29 NC AJ11 SAI 2 SADDIN 2 AG33 NC AJ15 SAHES SADDIN 3 AJ37 NC AJ17 SAHFA SADDIN 4 AL35 Chapter 10 Pin Descriptions 53 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 19 Pin Name Abbreviations continued 31994A 1 August 2004 Abbreviation Full Name Pin Abbreviation Full Name Pin SAHE5 SADDIN 5 HF AE33 SD 3 SDATA 3 Y35 SAI 6 SADDIN 6 AJ55 SD 4 SDATA 4 U35 SAHF7 SADDIN 7 AG37 SD 5 SDATA 5 U33 SAHF8 SADDIN 8 4F AL33 SD 6 SDATA 6 37 SADDIN 9 AN37 SD 7 SDATA 7 35 10 SADDIN 10 AL37 SD 8 SDATA 8 AA33 SAI 11 SADDIN 11 AG35 SD 9 SDATA 9 AE37 SAI 12 SADDIN 12 7 AN29 SD 10 SDATA 10 AG33 SAI 13 SADDIN 13 4 AN35 SD 11 SDATA 11 AC37 SAI 14 SADDIN 14 AN31 SD 12 SDATA 12 Y37 SAIC SADDINCLK
27. Pin page 72 S3 SCANINTEVAL page 73 P l N31 NC Pin page 72 SCANCLK2 page 75 PI Eus N33 SDATA 25 P B 7 THERMDA page 73 N35 SDATA 27 P B P 531 NC Pin page 72 N37 SDATA 18 P G 533 SDATA 7 G 5 1535 SDATA 15 P P4 VSS 11837 SDATA 6 PIBIG P6 VSS 2 VSS S Z P8 VSS 114 VSS sa Ep P30 come TS VSS P32 cont 118 VSS P34 Vcc T30 Vcc Bst ss P36 Vcc_corE 132 01 page72 P 1 134 Vcc Q3 TMS page72 P 136 core 05 SCANSHIFTEN page 73 P l IUI TDI page 72 P l 07 page 72 U3 TRST page 72 P IY 031 NC Pin page 72 TDO page 72 PO Q33 SDATA 24 P B P U THERMDC page73 055 SDATA 17 P B G U31 NC Pin page 72 057 SDATA 16 P B G 133 SDATA 5 P B R2 conE 935 SDATAJHJ R4 Vcc_coRE 7 NCPin page72 R6 coRE 2 Vcc_coRE ZEE ES R8 Vcc V4 Vcc_coRE R30 VSS 6 Vcc_coRE R32 155 8 Vcc_coRE ss Chapter 10 Pin Descriptions 65 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location continue
28. States The following sections provide an overview of the power management states For more details refer to the AMD Athlon and AMD Duron System Bus Specification order 21902 Note In all power management states that the processor is powered the system must not stop the system clock SYSCLK SYSCLKt to the processor The Working state is the state in which the processor is executing instructions When the processor executes the HLT instruction the processor enters the Halt state and issues a Halt special cycle to the AMD Athlon system bus The processor only enters the low power state dictated by the CLK_Ctl MSR if the system controller Northbridge disconnects the AMD Athlon system bus in response to the Halt special cycle If STPCLK is asserted the processor will exit the Halt state and enter the Stop Grant state The processor will initiate a system bus connect if it is disconnected then issue a Stop Grant special cycle When STPCLK is deasserted the processor will exit the Stop Grant state and re enter the Halt state The processor will issue a Halt special cycle when re entering the Halt state The Halt state is exited when the processor detects the assertion of INITZ RESET SMI or an interrupt via the INTR or NMI pins or via a local APIC interrupt message When the Halt state is exited the processor will initiate an AMD Athlon system bus connect if it is disconnected The processor enters the Stop Grant
29. ale AH30 FSB_Sense 1 page 71 O G 16 VSS AH32 VSS AKI8 AH34 VSS 20 VSS ZEN IC AH36 VSS 22 con IGNNE page 71 AK24 VSS AJ3 INIT P 1 26 Vcc core jo AJ5 Vcc comE 28 VSS AJ NCPin page72 AK30 Vcc gt AJ9 NC Pin page 72 J AK32 VSS NC Pin page72 AK34 Vcc AJ Analog 68 AK36 Vcc ERES 5 NCPin page 72 INTR page 72 P NCPin page 72 FLUSH page 71 P 9 NCPin page72 AL5 core ses 21 CLKFWDRST page 68 P I P A7 NC Pin page 72 EE AJ23 page 73 NC Pin page 72 AJ25 PLLBYPASS page 72 P l NCPin page 72 sul ae 27 NCPin page 72 PLLMON2 page 72 010 29 SADDIN 0 page73 P 5 PLLBYPASSCLK 72 P I AJ31 SFILLVALID P I G ALI7 CLKIN page 69 P AJ53 SADDINCLK P l G AL19 RSTCLK page 69 P AJ35 SADDIN 6 P P AL21 K7CLKOUT page 72 P O AJ37 SADDINDJ P G 12 CONNECT page69 P 66 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Lo
30. an approved heat sink Any heat sink design should avoid loads on corners and edges of die The OPGA package has compliant pads that serve to bring surfaces in planar contact Tool assisted zero insertion force sockets should be designed so that no load is placed on the ceramic substrate of the package Table 16 shows the mechanical loading specifications for the processor die It is critical that the mechanical loading of the heat sink does not exceed the limits shown in Table 16 Table 16 Mechanical Loading Location Dynamic MAX Static MAX Units Note Die Surface 100 30 Ibf 1 Die Edge 10 10 Ibf 2 Notes 1 Load specified for coplanar contact to die surface 2 Load defined for a surface at no more than a two degree angle of inclination to die surface Chapter 9 Mechanical Data 43 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 9 2 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Dimensions Table 17 shows the part number 27488 OPGA package dimensions in millimeters assigned to the letters and symbols used in the 27488 package diagram Figure 13 on page 45 Table 17 Dimensions for the AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Letter or Minimum Maximum Letteror Minimum Maximum Symbol Dimension Dimension Symbol Di
31. d 2 lt lt 1 601 3 VoL Output Low Voltage 300 400 mV lgAK p Tristate Leakage Pullup Vin VSS Ground 1 mA lo Output Low Current Voy Max 9 mA Notes 1 Characterized across DC supply voltage range 2 The 2 625 V value is equal to 2 5 V plus a maximum of five percent 3 Refer to CC 2 5V Generation Circuit found in the section Motherboard Required Circuits of the AMD Athlon Processor Based Motherboard Design Guide order 24363 4 Edge rates indicate the range for characterizing the inputs Chapter 7 Electrical Data 37 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 15 APIC Pin AC and DC Characteristics continued 31994A 1 August 2004 Characterized across DC supply voltage range Symbol Parameter Description Condition Min Max Units Notes Signal Rise Time 1 0 3 0 V ns 3 Tr Signal Fall Time 1 0 3 0 V ns 3 Tsu Setup Time 1 ns Tup Hold Time 1 ns Pin Capacitance 4 n pF Notes 2 The 2 625 V value is equal to 2 5 V plus a maximum of five percent 3 Refer to CC 2 5V Generation Circuit found in the section Motherboard Required Circuits of the AMD Athlon Processor Based Motherboard Design Guide order 24363 4 Edge rates indicate the range for characterizing the inputs 38 Electrical Data Chapter 7
32. is only issued after a subsequent CLKFWDRST is deasserted processor wake up event Figure 7 Processor Connect State Diagram Chapter 4 Power Management 17 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 4 3 Clock Control The processor implements a Clock Control CLK Ctl MSR address C001 001Bh that determines the internal clock divisor when the AMD Athlon system bus is disconnected Refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 for more details on the CLK_Ctl register 18 Power Management Chapter 4 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 5 CPUID Support AMD Sempron processor model 10 version and feature set recognition can be performed through the use of the CPUID instruction that provides complete information about the processor vendor type name etc and its capabilities Software can make use of this information to accurately tune the system for maximum performance and benefit to users For information on the use of the CPUID instruction see the following document m AMD Processor Recognition Application Note order 20734 Chapter 5 CPUID Support 19 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 20 CPUID Support Chapter 5
33. processor model 10 Table 10 Absolute Ratings Parameter Description Min Max conE Processor core voltage supply 0 5V Vec_core Max 0 5 V VCCA Processor PLL voltage supply 0 5V VCCA Max 0 5 V VpiN Voltage on any signal pin 0 5 V Vcc cone 0 5 V TsTORAGE Storage temperature of processor 409C 100 C 30 Electrical Data Chapter 7 31994A 1 August 2004 7 9 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet SYSCLK and SYSCLK DC Characteristics Table 11 shows the DC characteristics of the SYSCLK and SYSCLK differential clocks The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK signal represents CLKIN and RSTCLK tied together For more information about SYSCLK and SYSCLK see SYSCLK and SYSCLK on page 73 and Table 19 Abbreviations on page 52 Table 11 SYSCLK and SYSCLK DC Characteristics Pin Name Symbol Description Min Max Units Vthreshold pc Crossing before transition is detected DC 400 mV Vrhreshold Ac Crossing before transition is detected AC 450 mV p Leakage current through P channel pullup to Vcc coge 1 liga Leakage current through N channel pulldown to VSS Ground 1 mA Differential signal crossover ec cove 100 mV Capacitance 4 25 pF Note Thefollowing processor inputs have twice the listed capacitance because
34. requires the processor to service a probe after the system bus has been disconnected it must first initiate a system bus connect In addition to the legacy STPCLK signal and the Halt and Stop Grant special cycles the AMD Athlon system bus connect protocol includes the CONNECT PROCRDY and CLKFWDRST signals and a Connect special cycle AMD Athlon system bus disconnects are initiated by the Northbridge in response to the receipt of a Halt or Stop Grant Reconnect is initiated by the processor in response to an 12 Power Management Chapter 4 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet interrupt for Halt or STPCLK deassertion Reconnect is initiated by the Northbridge to probe the processor The Northbridge contains BIOS programmable registers to enable the system bus disconnect in response to Halt and Stop Grant special cycles When the Northbridge receives the Halt or Stop Grant special cycle from the processor and if there are no outstanding probes or data movements the Northbridge deasserts CONNECT a minimum of eight SYSCLK periods after the last command sent to the processor The processor detects the deassertion of CONNECT on a rising edge of SYSCLK and deasserts PROCRDY to the Northbridge In return the Northbridge asserts CLKFWDRST in anticipation of reestablishing a connection at some later point Note The Northbridge must disconnect the processor from the
35. 17 REF D2 742 REF Al 0 977 1 177 03 3 30 3 60 A2 0 80 0 88 D4 10 78 11 33 0 116 05 10 78 11 33 A4 1 90 D6 8 15 8 68 oP 6 60 D7 12 33 12 88 ob 0 43 0 50 D8 3 05 3 35 ob1 1 40 REF D9 12 71 13 26 S 1 455 2 375 E2 13 61 REF L 3 05 3 31 E3 2 35 2 65 M 37 E4 7 87 8 42 N 453 E5 7 87 8 42 e 1 27 BSC E6 11 41 11 96 el 2 54 BSC E8 13 28 13 83 Mass 11 0 g REF E9 1 66 1 96 Note 1 Dimensions are given in millimeters 2 Themass consists of the completed package including processor surface mounted parts and pins 46 Mechanical Data Chapter 9 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet D j Ls 2215 G 4X 9 9 9 9 15966966 90 9 WOO COO OO CES OOOO COO 3999265 690924 6 6 6 9 9026 6 9 9 4 9 9 2 6 6 5 9 95 1 153 557 s 9 T qa aas T ag Pan 223 25 27 2579 o9 3 38 37 A SEE NOTES BOTTOM VIEW TOP VIEW 22 COMPONENTS COMPLIANT PADS 20 64 G G AIB ZX A SIDE VIEW GENERAL NOTES 1 All dimensions are specified in millimeters mm 2 Dimensioning and tolerancing per ASME Y 14 5M 1994 This corner is marked with a triangle on both sides of the package identifies pin A1 corner and can be used for handling and orientation purposes Symbol M determines pin matrix size and N is number of pins Dimension b is measured at maximum solder pin
36. 19 Pin Name Abbreviations continued 31994A 1 August 2004 Abbreviation Full Name Pin Abbreviation Full Name Pin Vcc coRE F24 VCC Vcc_CORE X30 VCC Vcc_CORE F28 VCC Vcc_coRE X32 VCC Vcc_CORE F32 VCC Vcc_CORE X34 VCC Vcc_CORE F34 VCC Vcc_coRE X36 VCC Vcc_coRE F36 VCC 72 VCC Vcc_coRE H2 VCC Vcc_coRE 74 VCC coRE H4 VCC Vcc_coRE 76 VCC coRE H12 VCC Vcc_coRE 78 VCC Vcc_coRE H16 VCC AB30 VCC 20 VCC AB32 VCC Vcc_CORE H24 VCC Vcc_coRE AB34 VCC Vcc_CORE K32 VCC Vcc_coRE AB36 VCC Vcc_CORE K34 VCC Vcc_CORE AD2 VCC Vcc_CORE K36 VCC Vcc_coRE AD4 VCC Vcc_coRE M2 vcc Vcc_coRE AD6 VCC Vcc_coRE M4 VCC AF14 VCC 6 VCC AF18 VCC 8 VCC AF22 VCC P30 VCC AF26 VCC Vcc_coRE P32 VCC AF34 VCC Vcc_coRE P34 VCC AF36 VCC Vcc coRE P36 VCC Vcc_CORE AH2 VCC Vcc_coRE R2 VCC Vcc_coRE AH4 VCC Vcc_CORE R4 VCC Vcc_CORE AH10 VCC Vcc conE R6 VCC Vcc_coRE AH14 VCC Vcc_CORE R8 VCC Vcc_coRE AH18 VCC Vcc_coRE T30 VCC 22 VCC Vcc_coRE T32 VCC Vcc AH26 VCC T34 VCC Vcc_coRE AK10 VCC Vcc_coRE T36 VCC Vcc_coRE AK14 VCC Vcc_coRE V2 VCC Vcc AK18 VCC Vcc_CORE V4 VCC Vcc_CORE AK22 VCC
37. 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications This chapter describes the electrical specifications that are unique to the advanced 333 front side bus FSB AMD Sempron Processor Model 10 with 256K L2 cache Electrical and Thermal Specifications for the AMD Sempron Processor Model 10 with 256K L2 Cache Table 1 shows the electrical and thermal specifications in the working state and the S1 Stop Grant state for this processor Table 1 Electrical and Thermal Specifications for the AMD Sempron Processor Model 10 with 256K 1500 2200 L2 Cache Icc Processor Current Frequency in MHz CC CORE Thermal Power Maximum Die Model Number Working State CO Stop Grant 11 2 3 4 Temperature Maximum Typical Maximum Typical Maximum Typical 2000 2800 1 60 V 38 75 8 10 4 94 49 4 W 90 See Figure 3 AMD Sempron Processor Model 10 Power Management States on page 9 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical Stop Grant current that is currently about one third of the maximum specified current These currents occur when the AMD Athlon system bus is disconnected and has a low power ratio of 1 8 for Stop Grant dis
38. 50 mV Vcc Ac Max Maximum excursion above Vcc NOM 150 mV Vcc Ac MIN Maximum excursion below Vcc CORE NOM 100 mV AC Maximum excursion time for AC transients 10 us Negative excursion time for AC transients 5 us Note All voltage measurements are taken differentially at the COREFB COREFB pins 28 Electrical Data Chapter 7 31994A 1 August 2004 CORE AC MAX CORE DC MAX coRE CORE DC MIN CORE AC MIN ICORE MAX ICORE MIN AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Figure 9 shows the processor core voltage Vcc coRE waveform response to perturbation The Ac negative AC transient excursion time and Ac positive AC transient excursion time represent the maximum allowable time below or above the DC tolerance thresholds lax AC tmin dl dt Figure 9 Vcc Voltage Waveform Chapter 7 Electrical Data 29 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 7 8 Absolute Ratings 31994A 1 August 2004 The AMD Sempron processor model 10 should not be subjected to conditions exceeding the absolute ratings as such conditions can adversely affect long term reliability or result in functional damage Table 10 lists the maximum absolute ratings of operation for the AMD Sempron
39. 8 shows the AC and DC characteristics for VCCA For more information see Pin on page 73 Table 8 VCCA AC and DC Characteristics Symbol Parameter Min Nominal Max Units Notes V VCCA Pin Volt 225 2 5 SUR E VCCA In Voltage Vec_core lt 1 60 V 2 lycca VCCA Pin Current 0 50 mA GHz 3 Notes 1 Minimum and Maximum voltages are absolute No transients below minimum nor above maximum voltages are permitted 2 For more information refer to the AMD Athlon Processor Based Motherboard Design Guide order 24363 3 Measured at 2 5 V 7 6 Decoupling See the AMD Athlon Processor Based Motherboard Design Guide order 24363 or contact your local AMD office for information about the decoupling required on the motherboard for use with the AMD Sempron processor model 10 Chapter 7 Electrical Data 27 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 7 1 Vec Characteristics Table 9 shows the AC and DC characteristics for Vcc See Figure 9 on page 29 for a graphical representation of the wave form Table9 Vcc AC and DC Characteristics 31994A 1 August 2004 Symbol Parameter Limit in Working State Units Vcc MAX Maximum static voltage above Vcc CORE NOM 50 mV DC MIN Maximum static voltage below Vcc CORE NOM
40. AMD Athlon system bus before issuing the Stop Grant special cycle to the PCI bus or passing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransport technologv This note applies to current chipset implementation alternate chipset implementations that do not require this are possible Note In response to Halt special cycles the Northbridge passes the Halt special cycle to the PCI bus or Southbridge immediately The processor can receive an interrupt after it sends a Halt special cycle or STPCLK deassertion after it sends a Stop Grant special cycle to the Northbridge but before the disconnect actually occurs In this case the processor sends the Connect special cycle to the Northbridge rather than continuing with the disconnect sequence In response to the Connect special cycle the Northbridge cancels the disconnect request The system is required to assert the CONNECT signal before returning the C bit for the connect special cycle assuming CONNECT has been deasserted For more information see the AMD Athlon and AMD Duron System Bus Specification order 21902 for the definition of the C bit and the Connect special cycle Chapter 4 Power Management 13 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Figure 4 shows STPCLK assertion resulting in the processor in the Stop Grant state and the AMD Athlon sys
41. APIC and are driven to the Southbridge ora dedicated I O APIC The pin PICCLK must be driven with a valid clock input Refer to VCC_2 5V Generation Circuit found in the section Motherboard Required Circuits of the AMD Athlon Processor Motherboard Design Guide order 24363 for the required supporting circuitry For more information see Table 15 APIC Pin AC and DC Characteristics on page 37 CLKFWDRST resets clock forward circuitry for both the system and processor Chapter 10 Pin Descriptions 68 31994A 1 August 2004 CLKIN RSTCLK SYSCLK Pins CONNECT Pin COREFB and COREFB Pins CPU_PRESENCE Pin DBRDY and DBREQ Pins FERR Pin AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Connect CLKIN with RSTCLK and name it SYSCLK Connect CLKIN with RSTCLK and name it SYSCLK Length match the clocks from the clock generator to the Northbridge and processor See SYSCLK and SYSCLK on page 73 for more information CONNECT is an input from the system used for power management and clock forward initialization at reset COREFB and COREFB are outputs to the system that provide processor core voltage feedback to the system CPU PRESENCEX is connected to VSS on the processor package If pulled up on the motherboard CPU PRESENCE may be used to detect the presence or absence of a processor in the Socket A style socket DBRDY and DBREQ are routed to
42. C27 SDOC 3 SDATAOUTCLK 3 C11 SD 39 SDATA 39 23 SDOV SDATAOUTVALID AL31 SD 40 SDATA 40 A35 SFILLV SFILLVALID AJ31 SD 41 SDATA 41 C35 AN5 SD 42 SDATA 42 C33 STPC STPCLK ACI SD 43 SDATA 43 C31 TCK 01 SD 44 SDATA 44 A29 TDI UI SD 45 SDATA 45 29 TDO U5 SD 46 SDATA 46 E23 THDA THERMDA S7 SD 47 SDATA 47 C25 THDC THERMDC U7 SD 48 SDATA 48 E17 TMS Q3 SD 49 SDATA 49 E13 TRST U3 SD 50 SDATA 50 VCC Vcc_coRE B4 SD 51 SDATA 51 15 VCC 8 SD 52 SDATA 52 9 VCC 12 SD 53 53 A13 VCC Vcc_coRE 16 SD 54 SDATA 54 C9 VCC Vcc_coRE B20 SD 55 55 9 VCC Vcc_coRE B24 SD 56 SDATA 56 C21 VCC Vcc_coRE B28 0457 SDATA 57 A21 VCC B32 SD 58 SDATA 58 E19 VCC B36 SD 59 SDATA 59 C19 VCC Vcc_CORE D2 SD 60 SDATA 60 C17 VCC 04 SD 61 SDATA 61 11 VCC 08 SD 62 SDATA 62 17 VCC 012 0463 SDATA 63 15 VCC Vcc_coRE D16 SDIC 0 SDATAINCLK 0 W33 VCC D20 SDIC 1 SDATAINCLK 1 155 VCC Vcc D24 SDIC 2 SDATAINCLK 2 E27 VCC Vcc D28 SDIC 3 SDATAINCLK 3 E15 VCC Vcc_coRE D32 SDINV SDATAINVALID AN33 VCC Vcc F12 SDOC 0 SDATAOUTCLK O AE35 VCC F16 SDOC 1 SDATAOUTCLK I C37 VCC cont F20 Chapter 10 Pin Descriptions 55 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table
43. L2 cache the new value brand for every day computing performs at the top of its class Using QuantiSpeed architecture this processor is designed to power over 60 000 home and business applications and it is compatible with various operating systems including Linux and all existing Windows operating systems The AMD Sempron processor model 10 with 256K of L2 cache based on proven 0 13 micron technology integrates the innovative design with the manufacturing expertise of AMD The processor delivers excellent performance and low power while maximizing system value and maintaining the stable and compatible Socket infrastructure of the AMD Sempron processor The 4 digit model numbering system helps identify overall software performance the higher the number the better the performance Detailed technical documentation and performance benchmarks are available at www amd com Visit the AMD Sempron processor product comparison site for more production information Delivered in an OPGA package the AMD Sempron processor model 10 with 256K of L2 cache has full featured capabilities that deliver the integer floating point and 3D multimedia performance for highly demanding applications running on x86 system platforms The AMD Sempron processor model 10 with 256K of L2 cache delivers compelling performance for over 60 000 cutting edge software applications that include m high speed smooth stream Internet capability digital content c
44. LKFWDRST 6 A probe needs service 7 PROCRDY is asserted Three SYSCLK periods after CLKFWDRST is deasserted Although reconnected to the system interface the 8 Northbridge must not issue any non NOP SysDC commands for a minimum of four SYSCLK periods after deasserting CLKFWDRST Figure 6 Northbridge Connect State Diagram 16 Power Management Chapter 4 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Connect 6 B 1 2 B Connect Pending 2 Disconnect Pending 5 Connect Pending 1 3 A Disconnect 4 C Condition Action CONNECT is deasserted by the Northbridge for a A CLKFWDRST is asserted by the Northbridge previously sent Halt or Stop Grant special cycle B Issue a Connect special cycle Processor receives a wake up event and must cancel Return internal clocks to full speed and assert the disconnect request C PROCRDY 3 Deassert PROCRDY and slow down internal clocks Note Processor wake up event or CONNECT asserted by The Connect special cyde is only issued after a 4 Northbridge processor wake up event interrupt or STPCLK 8e deassertion occurs If the AMD Athlon system 5 CLKFWDRST is deasserted by the Northbridge bus is connected so the Northbridge can probe the processor a Connect special cycle is not issued at 6 Forward clocks start three SYSCLK periods after that time it
45. MD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 1 Electrical and Thermal Specifications for the AMD Sempron Processor Model 10 with 256K L2 Cache 21 Table2 333 FSB SYSCLK and SYSCLK AC Characteristics 22 Table3 333 FSB AMD Athlon System Bus AC Characteristics 23 Table 4 333 FSB AMD Athlon System Bus DC Characteristics 24 Table 5 Interface Signal Groupings 25 Table 6 VID 4 0 DC Characteristics 26 Table 7 FID 3 0 DC Characteristics 27 Table 8 VCCA AC and DC Characteristics 27 Table 9 AC and DC 28 Table 10 Absolute Ratings 30 Table 11 SYSCLK and SYSCLK DC Characteristics 31 Table 12 General AC and DC Characteristics 32 Table 13 Thermal Diode Electrical Characteristics 35 Table 14 Guidelines for Platform Thermal Protection of the v de ue ed eds RESER xe E 37 Table 15 APIC Pin AC and DC Characteristics 37 Table 16 Mechanical 43 Table 17 Dimensions for the AMD Sempron Processor Model 10 Part Number 27488 OPGA Package 44 Table 18 Dimensions for the AMD Sempron Processor Model 10 P
46. N page 75 pm ll Y33 NC Pin page 72 JAG INC Y35 SDATA 3 P B G AGI NC Pin page 72 Y37 SDATA 12 B AG3 SDATA IO P B P Z2 Vcc SDATA M R PIBIG 74 conE SDATA 11 64 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location continued Pin Name Description L P R Pin Name Description L R AD2 Vcc_core NCPin page72 Vcc cone 2 NCPin page72 AD6 Vcc comE Vcc cone AD8 NCPin page72 AF36 Vcc AD30 NCPin page 72 FERR page 69 P AD32 VSS amp 25 AG RESET AD34 VSS 5 NCPin page 72 AD36 VSS AG Key Pin page 72 A20M P I AG9 KeyPin page 72 AE3 PWROK 11 COREFB page 69 5 7 page75 P 1 page69 AE7 NC 15 Key Pin page 72 AES1 NC Pin page 72 AGI7 Key Pin page 72 AE33 SADDIN 5 P 1 G 19 NC Pin page 72 AE35 SDATAOUTCLK 0 P P AGI NCPin page72 AE37
47. Pin PGA Orientation Pins PLL Bypass and Test Pins INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8 bit interrupt vector and starts execution at that location TCK TMS TDI TRST and TDO are the JTAG interface Connect these pins directly to the motherboard debug connector Pull TDI TCK TMS and TRST up to corg with pullup resistors K7CLKOUT and K7CLKOUT are each run for two to three inches and then terminated with a resistor pair 100 ohms to and 100 ohms to VSS The effective termination resistance and voltage are 50 ohms and 2 These 16 locations are for processor type keying for forwards and backwards compatibility G7 G9 G15 G17 G23 G25 N7 Q7 Y7 AA7 AG7 AG9 AG15 AG17 AG27 and AG29 Motherboard designers should treat key pins like NC No Connect pins A socket designer has the option of creating a top mold piece that allows PGA key pins only where designated However sockets that populate all 16 key pins must be allowed so the motherboard must always provide for pins at all key pin locations See NC Pins for more information The motherboard should provide a plated hole for an NC pin The pin hole should not be electrically connected to anything NMI is an input from the system that causes a non maskable interrupt No pin is present at pin locations A1 and AN1 Motherboard designe
48. SA SSA mal suo 9 DA DA DA DA 00 6l om 20 N 01 89405 05 l 81 DA DA DA DA 406569204 d 0010 SSA SSA SSA SSA 81 um ADD NN 80005 09415 195 91 SSA SSA SSA SSA DA DA DA DA 91 SL N NJ I 16405 eas Gl tl DA DA DA DA SSA SSA SSA SSA tl EL inma SONY 480 N 6905 ON 59 El 4l SSA SSA SSA SSA DA DA DA DA 41 LL ow N N 140 N 0 0 200 pus 01 DA DA DA ON SSA SSA SSA 01 6 N 1905 095 saas 6 8 N N N N N SSA DA SSA DA SSA DA SSA DA N N N DA DA 8 N N N M o VOHL NJ elan vlan 940 uns 50 Z 9 SSA no N SSA SSA DA SSA SSA DA SSA N SSA SSA SSA 9 S ams DA NZ N IN s mn DIS NSIS alan N EL OVS 0 t SSA SSA DA SSA SSA SSA DA SSA SSA SSA DA SSA Y 13534 elan ANINDS 140 05 015 805 5 6 DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA l YIN nn NOV als DDIOS olan 0 015 0140 1140 HONS l nv w w a ov av av av ov av we 1 z a x M 10 5 N w 1 5 i 3 q a v 51 tions Ip Pin Descr Chapter 10 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sh
49. SDATA 9 P G AG23 NCPin page 72 AF2 VSS 625 page 72 AF4 VSS AG27 Key Pin page 72 AF6 NC Pin page 72 AG9 Key Pin page 72 AF8 NC Pin page 72 AG31 FSB Sense 0 page 71 G AF10 NC Pin page 72 AG33 SADDIN 2 4 P G AF2 VSS 35 SADDIN I1 P G AF14 Vcc_core AG37 SADDIN 7 P P AF16 VSS 2 Vcc core AF18 Vcc cone AF20 VSS AMD Pin page 68 AF22 Vcc_core AH8 NCPin page72 AF24 VSS 10 Vcc AF26 Vcc_corE VSS AF28 NCPin page72 AHM Vcc core Chapter 10 Pin Descriptions 65 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location continued 31994A 1 August 2004 Pin Name Description L P R Pin Name Description L P 16 VSS 5 AK2 VSS 18 Vcc_coRE VSS AH20 VSS gt fus AK6 CPU_PRESENCE page 69 r AH22 Vcc _coRE AK8 page72 AH24 VSS Eis AH26 Vcc cont VSS AH28 VSS
50. The implementation of thermal control circuitry to control processor temperature is left to the manufacturer to determine how to implement Thermal limits in motherboard design are necessary to protect the processor from thermal damage TsuurpowN is the temperature for thermal protection circuitry to initiate shutdown of the processor Tsp pgrAy is the maximum time allowed from the detection of the over temperature condition to processor shutdown to prevent thermal damage to the processor Systems that do not implement thermal protection circuitry or that do not react within the time specified by Tsp pprAy cause thermal damage to the processor during the unlikely events of fan failure or powering up the processor without a heat sink The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event Thermal protection circuitry reference designs and thermal solution guidelines are found in the following documents AMD Athlon Processor Based Motherboard Design Guide order 24363 AMD Thermal Mechanical and Chassis Cooling Design Guide order 23794 See http www amd com for more information about thermal solutions 36 Electrical Data Chapter 7 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 14 shows the and Tsp pgr Ay Specifications for circuitry i
51. Vcc conE V6 VCC Vcc_coRE AK26 VCC Vcc_CORE V8 VCC Vcc_coRE AK30 56 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin Abbreviation Full Name Pin Vcc coRE AK34 VSS D22 VCC Vcc_CORE AK36 VSS D26 VCC Vcc_CORE AJ5 VSS D30 VCC Vcc_CORE AL5 VSS D34 VCC Vcc_CORE AM2 VSS D36 VCC Vcc_coRE AM10 VSS F2 VCC 14 VSS F4 VCC AM18 VSS F6 VCC Vcc_coRE AM22 VSS F10 VCC 26 VSS F14 VCC Vcc_CORE AM22 VSS F18 VCC Vcc_CORE AM26 VSS F22 VCC Vcc conE AM30 VSS F26 VCC Vcc_CORE AM34 VSS H14 VCCA 25 VSS H18 VID 0 L1 VSS H22 VID 1 L5 VSS H26 VID 2 L5 VSS H34 VID 3 L7 VSS H36 VID 4 VSS K2 VREF_S VREF_SYS W5 VSS K4 VSS B2 VSS K6 VSS B6 VSS M30 VSS B10 VSS M32 VSS B14 VSS M34 VSS B18 VSS M36 VSS B22 VSS P2 VSS B26 VSS P4 VSS B30 VSS P6 VSS B34 VSS P8 VSS D6 VSS R30 VSS D10 VSS R32 VSS 014 VSS R34 VSS D18 VSS R36 Chapter 10 Pin Descriptions 57 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Table 19 Pin Name Abbreviations continued Table 19 Pin Name Abbreviations
52. al is used by the receivers to determine if a signal is asserted or deasserted by the source Termination resistors are not needed because the driver is impedance matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold For more information about pins and signals see Chapter 10 Pin Descriptions on page 49 Chapter 2 Interface Signals 5 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 2 3 Push Pull PP Drivers The AMD Sempron processor model 10 supports push pull PP drivers The system logic configures the processor with the configuration parameter called SysPushPull 1 PP The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins See ZN and ZP Pins on page 75 for more information 2 4 AMD Athlon System Bus Signals The AMD Athlon system bus is a clock forwarded point to point interface with the following three point to point channels m A 13 bit unidirectional output address command channel m A 13 bit unidirectional input address command channel m 72 bit bidirectional data channel For more information see Chapter 6 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications on page 21 Chapter 7 Electrical Data on page 25 and the AMD Athlon and AMD Duron System Bus Sp
53. art Number 27493 OPGA Package 46 Table 19 Pin Name Abbreviations 52 Table 20 Cross Reference by Pin Location 60 Table 21 FID 3 0 Clock Multiplier Encodings 70 Table 22 Front Side Bus Sense Truth 71 Table 23 VID 4 0 Code to Voltage Definition 74 Table 24 Constants and Variables for the Ideal Diode Equation 79 Table 25 Constants and Variables Used in Temperature Offset Equations yu ek Pate ee whee qasa 80 Table 26 5 85 T ble 27 ACrony MS seses vetu er eg be he ege eR boxe pU 86 List of Tables ix AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 X List of Tables 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Revision History Date August 2004 Rev 1 Description Initial release of the AMD Sempron Processor Model 10 Data Sheet Revision History Xi AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Xii Revision History 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Overview The AMD Sempron processor model 10 with 256K of
54. cation continued Pin Name Description L P R Pin Name Description L P R AL25 NCPin page 72 AM32 VSS 127 NCPin page72 AM34 Vcc core E 5 AL29 SADDIN I page73 P AM36 VSS P AL31 SDATAOUTVALID P No Pin page 72 AL33 SADDIN 8 P AN3 P AL35 SADDIN 4 P I GIAN SMI AL37 SADDIN 10 P G AN7 NC Pin page 72 AM2 Vcc NCPin page72 AM4 VSS NC Pin page 72 ai Gece e 6 VSS ANIS page 72 AM8 NCPin page 72 15 PLLBYPASSCLK page 72 Poy et 10 ANU CLKIN page69 P I P 12 VSS 19 RSTCLK page 69 14 Vcc K7CLKOUT page72 0 16 VSS AN23 PROCRDY P 18 AN25 page72 20 VSS AN27 NC Pin page 72 ERES 22 cone 29 SADDIN I2HE AM24 VSS AN31 SADDIN 14 P l G AM26 AN33 SDATAINVALID P l P AM28 VSS ZEN E AN35 SADDIN 15HF P l AM30 Vcc AN37 SADDIN 9 P Chapter 10 Pin Descriptio
55. cessor frequency indicated by the FID 3 0 code The SIP is sent to the processor using the SIP protocol This protocol uses the PROCRDY CONNECT and CLKFWDRST signals that are synchronous to SYSCLK For more information about FID 3 0 see FID 3 0 Pins on page 70 Serial Initialization Packet SIP Protocol Refer to AMD Athlon and AMD Duron System Bus Specification order 21902 for details of the SIP protocol 8 2 Processor Warm Reset Requirements Northbridge Reset Pins RESET cannot be asserted to the processor without also being asserted to the Northbridge RESET to the Northbridge is the same as PCI RESET The minimum assertion for PCI RESET is one millisecond Southbridges enforce a minimum assertion of RESET for the processor Northbridge and PCI of 1 5 to 2 0 milliseconds 42 Signal and Power Up Requirements Chapter 8 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Mechanical Data The AMD Sempron processor model 10 connects to themotherboard through a Pin Grid Array PGA socket named Socket A This processor utilizes the Organic Pin Grid Array OPGA package type described in this chapter For more information see the AMD Athlon M Processor Based Motherboard Design Guide order 24363 Die Loading The processor die on the OPGA package is exposed at the top of the package This feature facilitates heat transfer from the die to
56. cessor model 10 and can be found with other related documents at the AMD Web site http www amd com m AMD Athlon Processor x86 Code Optimization Guide order 22007 m AMD Processor Recognition Application Note order 20734 Methodologies for Measuring Temperature on AMD Athlon and AMD Duron M Processors order 24228 m AMD Thermal Mechanical and Chassis Cooling Design Guide order 23794 m Builders Guide for Desktop Tower Systems order 26003 Other Web sites of interest include the following m JEDEC home page www jedec org m IEEE home page www computer org m AGP Forum www agpforum or Appendix B Conventions and Abbreviations 89 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 90 Appendix B Conventions and Abbreviations
57. connect and a low power ratio of 1 8 Halt disconnect applied to the core dock grid of the processor as dictated by a value of 2003 1225h programmed into the Clock Control CLK MSR For more information refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 The Stop Grant current consumption is characterized at 50 and not tested Thermal design power represents the maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal Vcc Thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature Chapter6 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications 21 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 6 2 333 FSB AMD Sempron Processor Model 10 SYSCLK and SYSCLK AC Characteristics Table 2 shows the SYSCLK SYSCLK differential clock AC characteristics of this processor Table 2 333 FSB SYSCLK and SYSCLK AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes Clock Frequency 50 166 MHz 1 Duty Cycle 30 70 t Period 6 ns 2 3 t High Time 1 0 ns t Low Time 1 0 ns ty Fall Time 2 ns t Rise Time 2 ns Period Stability 300 ps Notes 7 The AMD Athlon system bus opera
58. continued Abbreviation Full Name Pin Abbreviation Full Name Pin VSS 2 VSS AH12 VSS T4 VSS AH16 VSS T6 VSS AH20 VSS T8 VSS AH24 VSS V30 VSS AH28 VSS V32 VSS AH32 VSS V34 VSS AH34 VSS V36 VSS AH36 VSS X2 VSS AK2 VSS X4 VSS AK4 VSS X6 VSS AK12 VSS X8 VSS AK16 VSS 750 VSS AK20 VSS 752 VSS AK24 VSS 754 VSS AK28 VSS 756 VSS AK32 VSS AB2 VSS AM4 VSS AB8 VSS AM6 VSS AB4 VSS 12 VSS AB6 VSS AM16 VSS AD32 VSS 20 VSS AD34 VSS AM24 VSS AD36 VSS AM28 VSS AF2 VSS AM32 VSS AF4 VSS AM36 VSS AF12 ZN AC5 VSS AF16 ZP AE5 58 Pin Descriptions Chapter 10 31994A 1 August 2004 10 2 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 on page 60 cross references Socket pin location to signal name The L Level column shows the electrical specification for this pin P indicates a push pull mode driven by a single source indicates open drain mode that allows devices to share the pin Note The AMD Sempron processor supports push pull drivers For more information see Push Pull PP Drivers on page 6 The P Port column indicates if this signal is an input I output O or bidirectional B signal The R Reference column indicates if this signal should be referenced to VSS G or VCC CORE P planes for the purpose of signal routing with respect to the current return paths Chapter 10 Pin Descriptions 59
59. ct Sequence in the Stop Grant State 14 Figure 5 Exiting the Stop Grant State and Bus Connect Sequence 15 Figure 6 Northbridge Connect State Diagram 16 Figure 7 Processor Connect State Diagram 17 Figure 8 SYSCLK Waveform 22 Figure 9 coRz Voltage 29 Figure 10 SYSCLK and SYSCLK Differential Clock Signals 31 Figure 11 General ATE Open Drain Test Circuit 34 Figure 12 Signal Relationship Requirements During Power Up Sequence se shea ee TRS AAG date Ee RR S REESE 39 Figure 13 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package 45 Figure 14 AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Diagram 47 Figure 15 AMD Sempron Processor Model 10 Pin Diagram Topside View pou ec ROSS OR RED Oe OE e e RID 50 Figure 16 AMD Sempron Processor Model 10 Pin Diagram Bottomside View 51 Figure 17 OPN Example for the AMD Sempron Processor Model 10 with 256K L2 77 List of Figures vii AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 viii List of Figures 31994A 1 August 2004 List of Tables A
60. d 31994A 1 August 2004 Pin Name Description L P R Pin Name Description L P R V30 VSS 26 Vcc_coRE ev ks d IS V32 VSS Z8 Vcc_coRE V34 VSS 1780 VSS V36 VSS 1182 VSS WI FID 0 page 70 754 VSS M W FID 1 page 70 0 0 756 VSS W5 VREFSYS page 74 DBRDY page 69 P O W7 NC Pin page 72 DBREQ page 69 P W31 NCPin page 72 5 NC esa W33 SDATAINCLK 0 P 7 Key Pin page 72 W35 SDATA 2 B G 1 NCPin page 72 W37 SDATA 1 B P B P X2 VSS 5 SDATA O PIBIG X4 VSS AA37 SDATA 13 P B G X6 VSS 2 VSS X8 VSS AB4 VSS X30 Vcc 6 VSS X32 Vcc cone ABB VSS A cap X34 Vcc cone X36 Vcc_corE AB32 Vcc_core EM E FID 2 page70 O O AB34 FID 5 page70 O O AB36 Ws Y5 NC Pin page 72 STPCLK page 73 P Y7 Key Pin page 72 PLLTEST page 72 PO ul Y31 NC Pin page 72 JAG Z
61. demarks AMD the AMD Arrow logo AMD Athlon AMD Duron AMD Sempron and combinations thereof QuantiSpeed and 3DNow are trademarks of Advanced Micro Devices Inc HyperTransport is a licensed trademark of the HyperTransport Technology Consortium MMX is a trademark of Intel Corporation Windows is a registered trademark of Microsoft Corporation Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table of Contents Revision History xi 1 OVERVIEW Lu Weed a e e re a ne T e a 1 11 QuantiSpeed Architecture 3 2 Interface Signals 5 2 1 OVERVIEW ed PRE RE E 4 5 2 2 Signaling 1 5 2 3 Push Pull PP Drivers 6 2 4 AMD Athlon System Bus 15 6 Logic Symbol 7 4 Power 9 4 1 Power Management States 9 Working 10 Halt State k uuu m u Remedies 10 Stop Grant States 10 Probe State e HEREIN eges 12 4 2 Conn
62. diameter on a plane parallel to datum C AN in front of package variation denotes non qualified package per AMD 01 002 3 7 The following features are not shown on drawings a Marking on die label on package b Laser elements ink swatch c Die and passive fudicials 8 The die is centered on the package Figure 14 AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Diagram Chapter 9 Mechanical Data 47 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 48 Mechanical Data Chapter 9 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 10 Pin Descriptions This chapter includes pin diagrams of the organic pin grid array for the AMD Sempron processor model 10 a listing of pin name abbreviations and a cross referenced listing of pin locations to signal names 10 1 Pin Diagram and Pin Name Abbreviations Figure 15 on page 50 shows the staggered Pin Grid Array PGA for the AMD Sempron processor model 10 Because some of the pin names are too long to fit in the grid they are abbreviated Figure 16 on page 51 shows the bottomside view of the array Table 19 on page 52 lists all the pins in alphabetical order by pin name along with the abbreviation where necessary Chapter 10 Pin Descriptions 49 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 Au
63. e conventions used in this chapter are as follows m Current specified as being sourced by the processor is negative m Current specified as being sunk by the processor is positive Interface Signal Groupings The electrical data in this chapter is presented separately for each signal group Table 5 defines each group and the signals contained in each group Interface Signal Groupings Signal Group Power Signals VID 4 0 VCCA COREFB COREFB Notes See Voltage Identification VID 4 0 on page 26 VID 4 0 Pins on page 74 VCCA AC and DC Characteristics on page 27 Vcc Characteristics on page 28 VCCA Pin on page 73 and COREFB and COREFB Pins on page 69 Frequency FID 3 0 See Frequency Identification FID 3 0 on page 27 and FID 3 0 Pins on page 70 System Clocks SYSCLK SYSCLK Tied to CLKIN CLKIN and RSTCLK RSTCLK PLLBYPASSCLK PLLBYPASSCLK See Table 11 SYSCLK and SYSCLK DC Characteristics on page 31 Table 3 333 FSB AMD Athlon System Bus AC Characteristics on page 23 SYSCLK and SYSCLK on page 73 and PLL Bypass and Test Pins on page 72 AMD Athlon System Bus SADDIN 14 2 SADDOUT 14 2 SADDINCLK SADDOUTCLK SFILLVAL SDATAINVAL SDATAOUTVAL 63 0 SDATAINCLK 3 0 SDATAOUTCLK 3 0 CLKFWDRST PROCRDY CONNECT See 333 FSB AMD Sempron
64. ecification order 21902 6 Interface Signals Chapter 2 31994A 1 August 2004 j AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor This diagram shows the logical grouping of the input and output signals Clock SYSCIK SYSCLK 4 gt SDATA 65 0 4E VID 4 0 gt SDATAINCLK 3 0 COREFB amp Voltage Data 2 5 SDATAOUTCLK 3 0 4 COREFB f Control ata SDATAINVALID PWROK SDATAOUTVALID Frequency p SFILLVALID PDISQE Control FSB SENSETO Front Side Bus Autodetect M SADDIN 142 Probe SysCMD SADDINCLK AMD Sempron FERR Processor Model 10 4 Request 1 SADDOUT 14 2 lt q 54 4 SADDOUTCLK INIR 0777 Legacy NMI 4 PROCRDY ue Power gt CLKFWDRST Management CONNECT and Initialization gt THERMDA i 1 Thermal RESET THERMDC J Diode PICCLK PICD 1 0 PE APIC Figure 2 Logic Symbol Diagram Chapter 3 Logic Symbol Diagram AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 8 Logic Symbol Diagram Chapter 5 31994 1 August 2004 4 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management 4 1 Note 94044 8
65. ect and Disconnect Protocol 12 Connect 1 12 Connect State 16 4 3 Clock Control 2 gu RD una Staat a 18 CPUID SUpDOEt Rein 19 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache 21 6 1 Electrical and Thermal Specifications for the AMD Sempron Processor Model 10 with 256K E2 Cach68 a dd ac bes een de EA IO BARRE 21 6 2 333 FSB AMD Sempron Processor Model 10 SYSCLK and SYSCLK AC Characteristics 22 6 3 333 FSB AMD Athlon System Bus AC Characteristics 23 6 4 333 FSB AMD Athlon System Bus DC Characteristics 24 7 Electrical PCR OER HR 25 7 1 Conventlons vong qu dug e e uya 25 7 2 Interface Signal Groupings 25 7 3 Voltage Identification VID 4 0 26 7 4 Frequency Identification FID 3 0 27 7 5 AC and DC 27 7 6 Decoupling ee Ru E EX 27 7 7 Vcc Cone 28 7 8 Absolute 30 Table of Contents lii AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 7 9 SYSCLK and SYSCLK DC Character
66. eet Table 19 Pin Name Abbreviations 31994A 1 August 2004 Abbreviation Full Name Pin Abbreviation Full Name Pin A20M AE1 KEY 7 AMD AH6 KEY AG7 ANLOG ANALOG AJ13 KEY AG9 CLKFR CLKFWDRST AJ21 KEY 15 CLKIN ANT7 KEY 17 CLKIN ALT KEY AG27 CNNCT CONNECT 125 AG29 COREFB 19 COREFB AGI3 NC A31 CPR CPU_PRESENCE AK6 NC C13 DBRDY AAI NC E25 DBREQ AA3 NC E33 FERR AGI NC F8 FID 0 WI NC F30 FID 1 W3 NC G11 FID 2 Yi NC 1 FID 3 NC G19 FLUSH AL3 NC 021 FSBO FSB Sense 0 AG31 NC G27 FSBI FSB Sense 1 AH30 NC G29 IGNNE NC G31 INIT AJ3 NC H6 INTR H8 7 K7CLKOUT AL21 NC H10 K7CO K7CLKOUT 21 28 G7 NC H30 KEY G9 NC H32 KEY 15 J5 KEY G17 NC J31 KEY G23 NC K8 KEY G25 NC K30 KEY N7 NC L31 KEY Q7 NC L35 KEY Y7 NC N31 52 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin Abbreviation Full Name Pin h Cc pe Jc NC S31 NC AJ27 NC U31 NC AK8 NC U37 NC 17 W7 NC AL9 NC W31 NC AL11 NC Y5 NC AL25 NC Y31 NC AL27 NC Y33 NC AM8
67. ence The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus 1 The Southbridge deasserts STPCLK informing the processor of a wake event When the processor recognizes STPCLK deassertion it exits the low power state and asserts PROCRDY notifying the Northbridge to connect to the bus The Northbridge asserts CONNECT 4 The Northbridge deasserts CLKFWDRST synchronizing the forwarded clocks between the processor and the Northbridge The processor issues a Connect special cycle on the system bus and resumes operating system and application code execution Chapter 4 Power Management 15 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Connect State Figure 6 below and Figure 7 on page 17 show the Northbridge Diagram and processor connect state diagrams respectively 4 2 A Disconnect Disconnect Pending Requested 5 B Reconnect Pending Pending 2 Probe Pending 1 Condition Action 1 A disconnect is requested and probes are still pending A Deassert CONNECT eight SYSCLK periods 2 A disconnect is requested and no probes are pending after last SysDC sent 3 A Connect special cycle from the processor Assert CLKFWDRST 4 No probes are pending Assert CONNECT 5 PROCRDY is deasserted Deassert C
68. for example AD 31 0 Bit Values Bits can either be set to 1 or cleared to 0 Hexadecimal and Binary Numbers Unless the context makes interpretation clear hexadecimal numbers are followed by an h and binary numbers are followed by a b 84 Appendix B Conventions and Abbreviations 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Abbreviations and Acronyms Table 26 contains the definitions of abbreviations used in this document Table 26 Abbreviations Abbreviation Meaning A Ampere F Farad G Giga Gbit Gigabit Gbyte Gigabyte H Henry h Hexadecimal K Kilo Kbyte Kilobyte M Mega Mbit Megabit Mbyte Megabyte MHz Megahertz m Milli ms Millisecond mW Milliwatt u Micro Microampere Microfarad uH Microhenry us Microsecond uV Microvolt n nano nA nanoampere nF nanofarad nH nanohenry ns nanosecond ohm Ohm p pico pA picoampere Appendix B Conventions and Abbreviations 85 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 26 Abbreviations continued Abbreviation Meaning pF picofarad pH picohenry ps picosecond S Second V Volt W Watt 31994A 1 August 2004 Table 27 contains the definitions of acronyms used in this document Table 27 Acronyms Abbreviation
69. fore RESET is deasserted In practice all Southbridges enforce this requirement If NB_RESET does not assert until after RESET has deasserted the processor misinterprets the CONNECT assertion due to NB_RESET being asserted as the beginning of the SIP transfer There must be sufficient overlap in the resets to ensure that CONNECT is sampled asserted by the processor before RESET is deasserted The FID 3 0 signals are valid within 100 ns after PWROK is asserted The chipset must not sample the FID 3 0 signals until they become valid Refer to the AMD Athlon Processor Based Motherboard Design Guide order 24363 for the specific implementation and additional circuitry required The FID 3 0 signals become valid within 100 ns after is asserted Refer to the AMD Athlon M Processor Based Motherboard Design Guide order 24363 for the specific implementation and additional circuitry required Chapter 8 Signal and Power Up Requirements 41 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Clock Multiplier Selection FID 3 0 The chipset samples the FID 3 0 signals in a chipset specific manner from the processor and uses this information to determine the correct serial initialization packet SIP The chipset then sends the SIP information to the processor for configuration of the AMD Athlon system bus for the clock multiplier that determines the pro
70. ge72 4 Vcc core zu EN H8 NC Pin page72 K36 Vcc core a NN s H10 NC Pin page 72 HLI VID 0 page 74 H12 cont 113 VID 1 page74 O O H14 VSS 15 VID 2 page 74 H16 17 VID 5 74 0 0 H18 VSS 31 NC Pin page 72 H20 26 BJP H22 VSS 3 635 NC Pin page 72 Ger H24 Vcc cone L37 SDATA D8 P B P H26 VSS M2 Vcc s eels H28 NC Pin page72 4 Vcc core 54144 2 50 NCPin page72 6 Vcc core E H32 NCPin page72 M8 Vcc core L eed H34 VSS M30 VSS H36 VSS M32 VSS SADDOUT 0 page 73 P O 34 VSS sims J3 SADDOUT 1 page 73 P O M36 VSS 62 Pin Descriptions Chapter 10 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 20 Cross Reference by Pin Location continued Pin Name Description L P R Pin Name Description L P R 1 68 O 4 VSS PICD 0 page 68 O B 836 VSS melos N5 PICD 1 page68 O B 51 SCANCLK1 page 73 L N7 Key
71. gure 17 OPN Example for the AMD Sempron Processor Model 10 with 256K L2 Cache Chapter 11 Ordering Information 77 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 78 Ordering Information Chapter 11 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Appendix A Thermal Diode Calculations This section contains information about the calculations for the on die thermal diode of the AMD Sempron processor model 10 For electrical information about this thermal diode see Table 13 Thermal Diode Electrical Characteristics on page 35 Ideal Diode Equation The ideal diode equation uses the variables and constants defined in Table 24 Table 24 Constants and Variables for the Ideal Diode Equation Equation Symbol Variable Constant Description Nt lumped Lumped ideality factor k Boltzmann constant q Electron charge constant T Diode temperature Kelvin VBE Voltage from base to emitter lc Collector current Is Saturation current Appendix A Thermal Diode Calculations 79 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Equation 1 shows the ideal diode calculation Vor lumped lt T 4 1 q 1 Sourcing two currents using Equation 1 derives the difference in the base to emitter voltage that leads to findi
72. gust 2004 pisdol wesseig 01 JIPON 105592014 uoJdures SL 1814 Z ve joe z o e jez o for fer fa a fa je u for 6 8 9 s r z l NV ws sS uns N N 0001 NID NN N N qns IWN NV WV SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA N SSA SSA DA WV ous BHNS 1005 N N DND Pn ID DM INNIA N N N DA asma V DA DA SSA DA SSA DA SSA DA SSA DA SSA DA SSA DA N no SSA SSA NV V 9 15 nnus 08 N Hd m ON N N N N N DA HV SSA SSA SSA 1851 SSA DA SSA DA SSA DA SSA DA SSA DA N aw DA DA HV 9V ums 0354 My N N N N 140 4340 N OV JV DA DA N N N DA SSA DA SSA DA SSA DA SSA N N N SSA SSA JV AV ss 042005 SHNS N N d mov JV SSA SSA SSA N N DA DA DA dy 2 15 vids ol as N N NZ 1514 pus V av DA DA DA DA SSA SSA SSA SSA av LL ABUS o 0s 6 N N Aman VV 7 SSA SSA SSA SSA DA DA DA DA Z auis 005 ON ON ela X DA DA DA DA SSA SSA SSA SSA X M s uns 00105 ON d ON M A SSA SSA SSA SSA opis 01 DA DA DA DA A nio vis sis N 01
73. ication order 21902 SCANSHIFTEN SCANCLK1 SCANINTEVAL and SCANCLK2 are the scan interface This interface is AMD internal and is tied disabled with pulldown resistors to ground on the motherboard SMI is an input that causes the processor to enter the system Management mode STPCLK is an input that causes the processor to enter a lower power mode and issue a Stop Grant special cycle SYSCLK and SYSCLK are differential input clock signals provided to the PLL of the processor from a system clock generator See CLKIN RSTCLK SYSCLK Pins on page 69 for more information Thermal Diode anode and cathode pins are used to monitor the actual temperature of the processor die providing more accurate temperature control to the system See Table 13 Thermal Diode Electrical Characteristics on page 35 for more information VCCA is the processor PLL supply For information about the VCCA pin see Table 5 VCCA AC and DC Characteristics on page 35 and the AMD Athlon Processor Based Motherboard Design Guide order 24363 To prevent damage to the processor do not pull this signal High above 2 5 V Do not expose this pin to a differential voltage greater than 1 60 V relative to the processor core voltage Chapter 10 Pin Descriptions 73 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 VID 4 0 Pins VREFSYS Pin The VID 4 0 Voltage Identification
74. istics 31 7 10 General AC and DC Characteristics 32 711 Open Drain Test 34 712 Thermal Diode Characteristics 35 Thermal Diode Electrical Characteristics 35 Thermal Protection Characterization 36 713 APIC Pins AC and DC Characteristics 37 8 Signal and Power Up Requirements 39 8 1 Power Up Requirements 39 Signal Sequence and Timing Description 39 Clock Multiplier Selection FID 3 0 42 8 2 Processor Warm Reset Requirements 42 Northbridge Reset Pins 42 9 Mechanical Data 43 9 1 Die Loading sunu IR PRR a gg s 43 9 2 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Dimensions 44 9 3 AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Dimensions 46 10 Pin Descriptions 49 10 1 Pin Diagram and Pin Name Abbreviations 49 10 2 Pin Eisb Ete de qO ERI NS 59 10 3 Detailed Pin Descriptions 68 A20NI PI cute beset ele os Bee ee 68 AMD Pinas 2 385 upa A 68 AMD Athlon System Bus Pins 68 Analog Pines usus hana
75. m and minimum respectively 4 Synchronous inputs outputs are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized Z In asynchronous operation the signal must persist for this time to enable capture 8 This value assumes RSTCLK period is 10 ns gt 2 fRST 9 The approximate value for standard case in normal mode operation 10 This value is dependent on RSTCLK frequency divisors Low Power mode and core frequency 11 Reassertions of the signal within this time are not guaranteed to be seen by the core 12 This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase 13 This value assumes RSTCLK and K7CLKOUT are running at the same frequency though the processor is capable of other configurations 14 Time to valid is for any open drain pins See requirements 7 and 8 in the Power Up Timing Requirements chapter for more information 32 Electrical Data Chapter 7 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Table 12 General AC and DC Characteristics continued N A WN Symbol Parameter Description Condition Min Max Units Notes Tsy Sync Input Setup Time 2 0 ns 4 5 Typ Sync Input Hold Time 0 0 ps 4 5 TpELAY Output Delay with respect to RSTCLK 0 0
76. mension Dimension D E 49 27 49 78 E9 1 66 1 96 D1 E1 45 72 BSC G H 4 50 D2 7 42 REF A 1 942 REF D3 3 30 3 60 1 1 00 1 20 D4 10 78 11 33 2 0 80 0 88 D5 10 78 11 33 0 116 D6 8 15 8 68 A4 1 90 D7 12 33 12 88 oP 6 60 D8 3 05 3 35 ob 0 43 0 50 D9 12 71 13 26 ob1 1 40 REF E2 13 61 REF S 1 455 2 375 2 35 2 65 L 3 05 3 31 E4 7 87 8 42 M 37 E5 7 87 8 42 N 453 E6 11 41 11 96 e 1 27 BSC E7 11 41 11 96 el 2 54 BSC E8 13 28 13 83 Mass 11 0 g REF Note 1 Dimensions are given in millimeters 2 Themass consists of the completed package including processor surface mounted parts and pins 44 Mechanical Data Chapter 9 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet KS D8 3X _G 4X AN H LM E S D sS Sessea S S S S EAM Am Aw 609 2 99292292290 6266866260 4 ES 3X i 68252 62765828509 RRR OROKOR ROM e L 1 990900 eo SOOO 99 9 9 9 T 165950595 SOE o 5989580 ce esesese ji 64 coace v EB 3X DN 66398080 ORNAMAN Tub TS a NET 6999 90 685958 a 85 9 9599980 ral 6 ioo 9o ES 95555520 85885830 L 9995 EXE K 4 e 00 e ali TERES IO T qb 9 950595 OOOO COC 9 5 9 9 r 969 6 9 9682 99 REIRE metet sa MCCOOK OSS 2 4 1 5 T 9 44738 15 17 19 21 23
77. mory technologies The high speed execution core of the AMD Sempron processor model 10 includes multiple x86 instruction decoders a dual ported 128 Kbyte split level one L1 cache an exclusive 256 Kbyte L2 cache three independent integer pipelines three address calculation pipelines and a superscalar pipelined out of order three way floating point engine The floating point engine is capable of delivering top of the class performance on numerically complex applications The AMD Sempron processor model 10 with 256K of L2 cache also includes QuantiSpeed architecture a 333 MHz 2 7 Gigabyte per second AMD Athlon system bus and 3DNow Professional technology The AMD Athlon system bus combines the latest technological advances such as point to point topology source synchronous packet based transfers and low voltage signaling to provide an extremely powerful scalable bus for an x86 processor 2 Overview Chapter 1 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet QuantiSpeed Architecture Summary The following design features summarize the QuantiSpeed architecture of the AMD Sempron processor model 10 with 256K of L2 cache m nine issue superpipelined superscalar x86 processor microarchitecture designed for increased instructions per cycle IPC and high clock frequencies m Pipelined floating point unit that executes all x87 floating point MMX SSE and 3DNo
78. n motherboard design necessary for thermal protection of the processor Table 14 Guidelines for Platform Thermal Protection of the Processor Symbol Parameter Description Max Units Notes TsuurpowN Thermal diode shutdown temperature for processor protection 125 12 3 Maximum allowed time from Tsuurpows detection to processor shutdown 500 ms 1 3 Notes 1 The thermal diode is not 100 tested it Is specified by design and limited characterization 2 The thermal diode is capable of responding to thermal events of 40 C s or faster 3 The AMD Sempron processor model 10 provides a thermal diode for measuring die temperature of the processor The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event Refer to AMD Athlon Processor Based Motherboard Design Guide order 24363 for thermal protection circuitry designs 7 13 APIC Pins AC and DC Characteristics Table 15 shows the AMD Sempron processor model 10 AC and DC characteristics of the APIC pins Table 15 APIC Pin AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes Vin Input High Voltage BE 238 b cont lt lt 1 6011 3 Vit Input Low Voltage 300 700 mV 1 Output High Voltage 88
79. ng the diode temperature as shown in Equation 2 The use of dual sourcing currents allows the measurement of the thermal diode temperature to be more accurate and less susceptible to die and process revisions Temperature sensors that utilize series resistance cancellation can use more than two sourcing currents and are suitable to be used with the AMD thermal diode Equation 2 1s the formula for calculating the temperature of a thermal diode T Vas Vasa k La Temperature 0ffset Correction A temperature offset may be required to correct the value measured by a temperature sensor An offset is necessary if a difference exists between the lumped ideality factor of the processor and the ideality factor assumed by the temperature sensor The lumped ideality factor can be calculated using the equations in this section to find the temperature offset that should be used with the temperature sensor Table 25 shows the constants and variables used to calculate the temperature offset correction Table 25 Constants and Variables Used in Temperature Offset Equations Equation Symbol Variable Constant Description actual Actual ideality factor Nt lumped Lumped ideality factor Nt Ts Ideality factor assumed by temperature sensor Ihigh High sourcing current llow Low sourcing current spec Die temperature specification Toffset Temperature offset 80 Appendix A Thermal Diode Calculations
80. ns 67 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 10 3 Detailed Pin Descriptions A20M Pin AMD Pin AMD Athlon System Bus Pins Analog Pin APIC Pins PICCLK PICD 1 0 CLKFWDRST Pin The information in this section pertains to Table 20 on page 60 A20M is an input from the system used to simulate address wrap around in the 20 bit 8086 AMD Socket A processors do not implement a pin at location AH6 All Socket A designs must have top plate or cover that blocks this pin location When the cover plate blocks this location a non AMD part e g PGA370 does not fit into the socket However socket manufacturers are allowed to have a contact loaded in the AH6 position Therefore motherboard socket design should account for the possibility that a contact could be loaded in this position See the AMD Athlon and AMD Duron System Bus Specification order 21902 for information about the system bus pins PROCRDY PWROK RESET SADDIN 14 2 SADDINCLK SADDOUT 14 2 SADDOUTCLK SDATA 63 0 SDATAINCLK 3 0 SDATAINVALID SDATAOUTCLK 3 0 SDATAOUTVALID SFILLVALID Treat this pin as a NC The Advanced Programmable Interrupt Controller APIC isa feature that provides a flexible and expandable means of delivering interrupts in a system using an AMD processor The pins PICD 1 0 are the bidirectional message passing signals used for the
81. ntions and Abbreviations 83 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Data Terminology The following list defines data terminology Quantities word 1 two bytes 16 bits Adoubleword is four bytes 32 bits lt A quadword is eight bytes 64 bits Addressing Memory is addressed as a series of bytes on eight byte 64 bit boundaries in which each byte can be separately enabled Abbreviations The following notation is used for bits and bytes Kilo K as in 4 Kbyte page Mega M as in 4 Mbits sec Giga as in 4 Gbytes of memory space See Table 26 on page 85 for more abbreviations Little Endian Convention The byte with the address xx xx00 is in the least significant byte position little end In byte diagrams bit positions are numbered from right to left the little end is on the right and the big end is on the left Data structure diagrams in memory show low addresses at the bottom and high addresses at the top When data items are aligned bit notation on a 64 bit data bus maps directly to bit notation in 64 bit wide memory Because byte addresses increase from right to left strings appear in reverse order when illustrated Bit Ranges In text bit ranges are shown with a dash for example bits 9 1 When accompanied by a signal or bus name the highest and lowest bit numbers are contained in brackets and separated by a colon
82. ocessor resumes execution at the instruction boundary where STPCLK was initially recognized If RESET is sampled asserted during the Stop Grant state the processor exits the Stop Grant state and the reset process begins There are two mechanisms for asserting STPCLK hardware and software The Southbridge can force STPCLK assertion for throttling to protect the processor from exceeding its maximum case temperature This is accomplished by asserting the THERM input to the Southbridge Throttling asserts STPCLK for a percentage of a predefined throttling period STPCLK is repetitively asserted and deasserted until THERM is deasserted Software can force the processor into the Stop Grant state by accessing ACPI defined registers typically located in the Southbridge The operating system places the processor into the C2 Stop Grant state by reading the P_LVL2 register in the Southbridge If an ACPI Thermal Zone is defined for the processor the operating system can initiate throttling with STPCLK using the ACPI defined P_CNT register in the Southbridge The Northbridge connects the AMD Athlon system bus and the processor enters the Probe state to service cache snoops during Stop Grant for C2 or throttling Chapter 4 Power Management II AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Probe State In C2 probes are allowed as shown in Figure 3 on page 9 The Stop G
83. oul and APIC Pins PICCLK PICD 1 0 on page 68 See Table 13 Thermal Diode Electrical Characteristics Thermal THERMDA THERMDC on page 35 and THERMDA and THERMDC Pins on page 73 7 5 Voltage Identification VID 4 0 Table 6 shows the VID 4 0 DC Characteristics For more information on VID 4 0 DC Characteristics see VID 4 0 Pins on page 74 Table 6 VID 4 0 DC Characteristics Parameter Description Min Max lot Output Current Low 6 mA Vou Output High Voltage 5 25 V Note The VID pins are either open circuit or pulled to ground It is recommended that these pins are not pulled above 5 25 V which is 5 0 V 5 26 Electrical Data Chapter 7 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 7 4 Frequency Identification FID 3 0 Table 7 shows the FID 3 0 DC characteristics For more information see FID 3 0 Pins on page 70 Table 7 FID 3 0 DC Characteristics Parameter Description Min Max lot Output Current Low 6 mA Vou Output High Voltage lt 1 60 V Note The FID pins must not be pulled above 2 625 V which is equal to 2 5 V plus a maximum of five percent 2 Refer to VCC 2 5V Generation Circuit found in the section Motherboard Required Circuits of the AMD Athlon Processor Based Motherboard Design Guide order 24363 7 5 AC and DC Characteristics Table
84. rant state is also entered for the S1 Powered On Suspend system sleep state based on a write to the SLP and SLP EN fields in the ACPI defined Power Management 1 control register in the Southbridge During the S1 Sleep state system software ensures no bus master or probe activity occurs The Southbridge deasserts STPCLK and brings the processor out of the S1 Stop Grant state when any enabled resume event occurs The Probe state is entered when the Northbridge connects the AMD Athlon system bus to probe the processor for example to snoop the processor caches when the processor is in the Halt or Stop Grant state When in the Probe state the processor responds to a probe cycle in the same manner as when it is in the Working state When the probe has been serviced the processor returns to the same state as when it entered the Probe state Halt or Stop Grant state When probe activity is completed the processor only returns to a low power state after the Northbridge disconnects the AMD Athlon system bus again 4 2 Connect and Disconnect Protocol Connect Protocol Significant power savings of the processor only occur if the processor is disconnected from the system bus by the Northbridge while in the Halt or Stop Grant state The Northbridge can optionally initiate a bus disconnect upon the receipt of a Halt or Stop Grant special cycle The option of disconnecting is controlled by an enable bit in the Northbridge If the Northbridge
85. reation digital photo editing and digital video image compression video encoding for streaming over the Internet soft DVD commercial 3D modeling workstation class computer aided design CAD commercial desktop publishing speech recognition Chapter 1 Overview 1 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 The AMD Sempron processor model 10 with 256K of L2 cache is binary compatible with existing x86 software and backwards compatible with applications optimized for MMX SSE and 3DNow technology Using a data format and single instruction multiple data SIMD operation based on the MMX instruction model the AMD Sempron processor model 10 can produce as many as four 32 bit single precision floating point results per clock cycle The 3DNow Professional technology implemented in the AMD Sempron processor model 10 with 256K of L2 cache includes integer multimedia instructions and software directed data movement instructions for optimizing such applications as digital content creation and streaming video for the internet as well as instructions for digital signal processing DSP and communications applications The AMD Sempron processor model 10 with 256K of L2 cache features a seventh generation microarchitecture with an integrated exclusive L2 cache which supports the growing processor and system bandwidth requirements of emerging software graphics I O and me
86. rs should not allow for a PGA socket pin at these locations For more information see the AMD Athlon M Processor Based Motherboard Design Guide order 24363 PLLTEST PLLBYPASS PLLMON1 PLLMON2 PLLBYPASSCLK and PLLBYPASSCLK are the PLL bypass and test interface This interface is tied disabled on the motherboard All six pin signals are routed to the debug connector All four processor inputs PLLTEST PLLBYPASS PLLMON1 PLLMON2 are tied to coreg with pullup resistors 72 Pin Descriptions Chapter 10 31994A 1 August 2004 PWROK Pin SADDIN 1 0 and SADDOUT I 0 Pins Scan Pins SMI Pin STPCLK Pin SYSCLK and SYSCLK THERMDA and THERMDC Pins VCCA Pin AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet The PWROK input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification For more information Chapter 8 Signal and Power Up Requirements on page 39 The AMD Sempron processor model 10 does not support SADDIN 1 0 SADDOUT 1 0 SADDIN 1 is tied to VCC with pullup resistors if this bit is not supported by the Northbridge future models can support SADDIN 1 SADDOUTT 1 0 are tied to VCC with pullup resistors if these pins are supported by the Northbridge For more information see the AMD Athlon and AMD Duron System Bus Specif
87. s asserted When PWROK is asserted the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the PLL The reference system 40 Signal and Power Up Requirements Chapter 8 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet clock must be valid at this time The system clocks are designed to be running after 3 3 V has been within specification for three milliseconds PWROK assertion to deassertion of RESET The duration of RESET assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1 ns phase error The processor PLL begins to run after PWROK is asserted and the internal clock grid is switched from the ring oscillator to the PLL The PLL lock time may take from hundreds of nanoseconds to tens of microseconds It is recommended that the minimum time between PWROK assertion to the deassertion of RESET be at least 1 0 milliseconds Southbridges enforce a delay of 1 5 to 2 0 milliseconds between PWRGD Southbridge version of PWROK assertion and NB_RESET deassertion PWROK must be monotonic and meet the timing requirements as defined in Table 12 General AC and DC Characteristics on page 32 The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWROK NB_RESET must be asserted causing CONNECT to also assert be
88. sserted at least 10 nanoseconds prior to the assertion of PWROK In practice Southbridge asserts RESET milliseconds before PWROK is asserted 2 All motherboard voltage planes must be within specification before PWROK is asserted PWROK is an output of the voltage regulation circuit on the motherboard PWROK indicates that Vcc and all other voltage planes in the system are within specification The motherboard is required to delay PWROK assertion for a minimum of three milliseconds from the 3 3 V supply being within specification This delay ensures that the system clock SYSCLK SYSCLK is operating within specification when PWROK is asserted The processor core voltage must be within specification as dictated by the VID 4 0 pins driven by the processor before PWROK is asserted Before PWROK assertion the AMD Sempron processor is clocked by a ring oscillator The processor PLL is powered by VCCA The processor PLL does not lock if VCCA is not high enough for the processor logic to switch for some period before PWROK is asserted VCCA must be within specification at least five microseconds before PWROK is asserted In practice VCCA Vcc core and all other voltage planes must be within specification for several milliseconds before PWROK is asserted After PWROK is asserted the processor PLL locks to its operational frequency 3 The system clock SYSCLK SYSCLK must be running before PWROK i
89. state upon recognition of assertion of STPCLK input After entering the Stop Grant state the processor issues a Stop Grant special bus cycle on the AMD Athlon system bus The processor is not in a low power state at this time because the AMD Athlon system bus is still connected After the Northbridge disconnects the AMD Athlon system bus in response to the Stop Grant special bus cycle the processor enters a low power state dictated by the CLK Ctl MSR If the Northbridge needs to probe the processor during the Stop Grant state while the system bus is disconnected it I0 Power Management Chapter 4 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet must first connect the system bus Connecting the system bus places the processor into the higher power probe state After the Northbridge has completed all probes of the processor the Northbridge must disconnect the AMD Athlon system bus again so that the processor can return to the low power state During the Stop Grant states the processor latches INIT INTR NMI SMI or a local APIC interrupt message if they are asserted The Stop Grant state is exited upon the deassertion of STPCLK or the assertion of RESET When STPCLK is deasserted the processor initiates a connect of the AMD Athlon system bus if it is disconnected After the processor enters the Working state any pending interrupts are recognized and serviced and the pr
90. t Fall Slew Rate 1 3 V ns 1 Output skew with respect to a T SSEN DIFFEDGE different clock edge Im ps T 2 Forward SU Input Data Setup Time 300 ps 3 Clocks Tup Input Data Hold Time 300 ps 3 Cin Capacitance on input clocks 4 25 pF Cour Capacitance on output clocks 4 12 pF TvAL RSTCLK to Output Valid 800 2000 ps 4 5 Sync Tsu Setup to RSTCLK 500 ps 4 6 Tup Hold from RSTCLK 500 ps 4 6 Notes 1 Rise and fall time ranges are guidelines over which the has been characterized 2 Tskew pirrepge the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock as measured at the package with respect to different clock edges Input SU and HD times are with respect to the appropriate Clock Forward Group input clock The synchronous signals include PROCRDY CONNECT and CLKFWDRST Ta 15 RSTCLK rising edge to output valid for PROCRDY Test Load is 25 pF Tsy is setup of CONNECT CLKFWDRST to rising edge of RSTCLK Typ Is hold of CONNECT CLKFWDRST from rising edge of RSTCLK S amp KW Chapter6 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications 23 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 6 4 333 FSB AMD Athlon System Bus DC Characteristics Table 4 shows the DC characteristics of the AMD Athlon system bus for this processor Table 4 333 FSB AMD Athlon System Bus DC Characteristics
91. tem bus disconnected STPCLK AMD Athlon System Bus CONNECT PROCRDY CLKFWDRST PCI Bus Figure 4 AMD Athlon System Bus Disconnect Sequence in the Stop Grant State An example of the AMD Athlon system bus disconnect sequence is as follows 1 The peripheral controller Southbridge asserts STPCLK to place the processor in the Stop Grant state 2 When the processor recognizes STPCLK asserted it enters the Stop Grant state and then issues a Stop Grant special cycle 3 When the special cycle is received by the Northbridge it deasserts CONNECT assuming no probes are pending initiating a bus disconnect to the processor 4 The processor responds to the Northbridge by deasserting PROCRDY 5 The Northbridge asserts CLKFWDRST to complete the bus disconnect sequence 6 After the processor is disconnected from the bus the processor enters a low power state The Northbridge passes the Stop Grant special cycle along to the Southbridge 14 Power Management Chapter 4 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state connects the processor to the AMD Athlon system bus and puts the processor into the Working state 15415 O O OO CONNECT QKRWDRST x Figure 5 Exiting the Stop Grant State and Bus Connect Sequ
92. tes at twice this clock frequency 2 Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed loop jitter bandwidth to allow the PLL to track the jitter The 20dB attenuation point as measured into a 20 or 30 pF load must be less than 500 kHz 3 Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency spread spectrum clock generators In no cases can the AMD Athlon system bus period violate the minimum specification above AMD Athlon system bus clock inputs can vary from 100 of the specified frequency to 99 of the specified frequency at a maximum rate of 100 kHz Figure 8 shows a sample waveform of the SYSCLK signal Vrhreshold AC Figure 8 SYSCLK Waveform 22 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications Chapter 6 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 6 3 333 FSB AMD Athlon System Bus AC Characteristics The AC characteristics of the AMD Athlon system bus of this processor are shown in Table 3 The parameters are grouped based on the source or destination of the signals involved Table 3 555 FSB AMD Athlon System Bus AC Characteristics Group Symbol Parameter Min Max Units Notes Output Rise Slew Rate 1 3 V ns 1 All Signals Outpu
93. the debug connector DBREQ is tied to Vcc with a pullup resistor FERR is an output to the system that is asserted for any unmasked numerical exception independent of the NE bit in CRO FERR is a push pull active High signal that must be inverted and level shifted to an active Low signal For more information about FERR and FERR see the Required Circuits chapter of the AMD Athlon Processor Based Motherboard Design Guide order 24363 Chapter 10 Pin Descriptions 69 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 FID 3 0 Pins FID 3 Y3 FID 2 Y1 FID 1 W3 and FID 0 W1 are the 4 bit processor clock to SYSCLK ratio Table 21 describes the encodings of the clock multipliers on FID 3 0 Table 21 FID 3 0 Clock Multiplier Encodings FID 3 0 Processor Clock to SYSCLK Frequency Ratio 0000 11 0001 11 5 0010 12 0011 gt 12 5 0100 5 0101 5 5 0110 6 0111 6 5 1000 7 1001 7 5 1010 8 1011 8 5 1100 9 1101 9 5 1110 10 1111 10 5 Notes 1 All ratios greater than or equal to 12 5x have the same FID 3 0 code of 0011b which causes the SIP configuration for al ratios of 12 5x or greater to be the same 2 BIOS initializes the CLK Ctl MSR during the POST routine This CLK setting is used with all FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor
94. they connect to two input pads SYSCLK and SYSCI SYSCLK connects to CLKIN RSTCLK SYSCLK connects to CLKIN RSTCLK Figure 10 shows the DC characteristics of the SYSCLK and SYSCLK signals Vrhreshold pc 400 mV Figure 10 SYSCLK and SYSCLK Differential Clock Signals Vthreshold ac 450mV Chapter 7 Electrical Data 3l AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 7 10 General AC and DC Characteristics Table 12 shows the AMD Sempron processor model 10 AC and DC characteristics of the Southbridge JTAG test and miscellaneous pins Table 12 General AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes 2 Input High Voltage u V 1 2 i du ia ee 200 mV 300 mV Vit Input Low Voltage 300 350 mV 12 V V V Output High Voltage CC CORE CC CORE mV 400 300 VoL Output Low Voltage 300 400 mV Vin VSS l Tristate Leakage Pullu IN 1 mA LEAK P 8 p Ground lakn Tristate Leakage Pulldown VN 7 cone 600 Nominal lou Output High Current 6 mA 3 lo Output Low Current 6 mA 3 Notes 1 Characterized across DC supply voltage range 2 Values specified at nominal Scale parameters between coge minimum and cogg maximum 3 lg and measured at Vg maximu
95. ulations 31994A 1 August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Appendix B Conventions and Abbreviations Signals and Bits This section contains information about the conventions and abbreviations used in this document Active Low Signals Signal names containing a pound sign such as SFILL indicate active Low signals They are asserted in their Low voltage state and negated in their High voltage state When used in this context High and Low are written with an initial upper case letter Signal Ranges In a range of signals the highest and lowest signal numbers are contained in brackets and separated by a colon for example D 63 0 Reserved Bits and Signals Signals or bus bits marked reserved must be driven inactive or left unconnected as indicated in the signal descriptions These bits and signals are reserved by AMD for future implementations When software reads registers with reserved bits the reserved bits must be masked When software writes such registers it must first read the register and change only the non reserved bits before writing back to the register Three State In timing diagrams signal ranges that are high impedance are shown as a straight horizontal line half way between the high and low levels Invalid and Don t Care In timing diagrams signal ranges that are invalid or don t care are filled with a screen pattern Appendix B Conve
96. w instructions m Hardware data pre fetch that increases and optimizes performance on high end software applications utilizing high bandwidth system capabilities m Advanced two level translation look aside buffer TLB structures for both enhanced data and instruction address translation The AMD Sempron processor model 10 with QuantiSpeed architecture incorporates three TLB optimizations the L1 DTLB increases from 32 to 40 entries the L2 ITLB and L2 DTLB both use exclusive architecture and the TLB entries can be speculatively loaded The AMD Sempron processor model 10 delivers excellent system performance in a cost effective industry standard form factor The AMD Sempron processor model 10 is compatible with motherboards based on Socket A Figure 1 on page 4 shows a typical AMD Sempron processor model 10 with 256K L2 cache system block diagram Chapter 1 Overview 3 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1 August 2004 Thermal Monitor AMD Sempron Proces sor Model 10 AMD Athlon System Bus AGP Memory Bus System Controller Northbridge SDRAM or DDR PCI Bus Peripheral Bus Con troller Southbridge LAN SCSI Modem Audio LPC Bus Dual EIDE BIOS Figure 1 Typical AMD Sempron Processor Model 10 System Block Diagram 4 Overview Chapter 1 31994A

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