Agilent Technologies FS4100 Computer Drive User Manual
Contents
1. e Analyzing the Universal Serial Bus chapter introduces you to the USB Analysis Probe and lists the minimum equipment required and accessories supplied for USB analysis Characteristics common to state and timing analysis are also detailed The State Analysis chapter explains how to configure the USB Analysis Probe to perform state analysis on your USB The Timing Analysis chapter explains how to configure the USB Analysis Probe to perform timing analysis on your USB The General Information chapter provides some general information including the operating characteristics for the USB Analysis Probe module and the cable header pinout Analyzing the Universal Serial Bus Duplicating the Master Diskette Accessories Supplied This chapter introduces you to the USB Analysis Probe and lists the minimum equipment required and accessories supplied for Universal Serial Bus analysis This chapter also contains information that is common to both state and timing analysis Before you use the USB Analysis Probe software make a duplicate copy of the master diskette Then store the master diskette and use the back up copy to configure your logic analyzer This will help prevent the possibility of losing or destroying the original files in the event the diskette wears out is damaged ora file is accidentally deleted To make a duplicate copy use the Duplicate diskette operation in the disk menu of your logic analyzer For more inf2. 1 x J WE Pod B2 1 E x JT CK2 Ciks C9S 1 T CKI Ciks C11S 4 xj al mmjej Add Bus Signal Delete Delete All Define Probes Import Netlist System Summary OK Cancel Help Astart aie Aap Ghinbox mi Gyhiyawmn f F51104 2 ffjesuiza 1 c pocum Bge sam ii Offlinel Note In the above picture under Logic analvzer pods the first pod goes to the Odd pod and the second goes to the Even pod of the termination adapter e g Pod B1 goes to odd termination adapter pod and B2 goes to the even termination adapter pod 14 1680 90 900 167xx Configuration files 167xx Analyzer 169xx Analyzer 16550 16710 1 2 CUSB41_ 1 16555 6 7 CUSB41_2 16715 6 7 1674x 1675x CUSB41_3 1680 90 State 1680 90 16750 1 2 CUSB41_6 1691x State 1680 90 Timing 1680 90 16750 1 2 CUSB41_7 1691x Timing Offline Analysis Data that is saved on a 167xx analyzer in fast binary format or 16900 analyzer data saved as a ala file can be imported into the 1680 90 900 environment for analysis You can do offline analysis on a PC if you have the 1680 90 900 operating system installed on the PC if you need this software please contact Agilent Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to use the analyzer to capture data If you have already used the license that was included with your
3. 023 3 248 us IN ADDR 00 END_POINT 0 2 016 us NO ACKNOWLEDGE 994 480 us SOF FRAME 024 3 248 us IN ADDR 00 END_POINT 0 4 024 us DATALI 0112 1 336 us DATAL 0100 1 312 us DATAL 0000 1 328 us DATAL 0800 752 000 ns DATA CRC CBE7 2 000 us ACKNOWLEDGE 985 752 us SOF FRAME 025 999 752 us SOF FRAME 026 3 248 us OUT ADDR 00 END_POINT 0 OUT 3 328 us DATA CRC 0000 CRC DATA The following Analysis Probe related error messages are reported by the USB inverse assembler FAILED TO IDENTIFY PID This error will be reported by the inverse assembler if the USB Analysis Probe hardware reports a status code that is undefined If this error occurs please contact the FuturePlus Systems factory By design the USB Analysis Probe will detect and report CRC and serial bit stuffed errors The PID variable chart details the CRC and serial bit stuff errors detected It is a protocol violation to omit the stuffed zero when the last 6 bits of a packet are ones although the packet data is correct and complete The Analysis Probe may not indicate that a serial stuffed bit error occurred in this scenario 27 The USB Analysis Probe will also detect invalid PIDS bad PIDS and SOF tokens sent at slow speed The Analysis Probe implements an error summary status called ANY ERROR this status will be sent to the Analyzer if any of the above error conditions is detected by the Analysis Probe 28 Timing Analysis Installation Quick Reference
4. Installation Quick Reference Acquiring Data POD 3 Description End of Packet State Machine Load Byte Count State Machine USB Analysis Probe Test Points POD 4 Description The Waveform Display GENERAL INFORMATION Characteristics Standards Supported Power Requirements Logic Analyzer Required Number of Probes Used Supported speeds Signal loading Operations Environmental Temperature Altitude Humidity Testing and Troubleshooting Servicing Signal Connections 22 23 25 25 26 26 27 27 29 30 30 32 33 34 34 How to reach us For Technical Support FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL 603 471 2734 FAX 603 471 2738 On the web http www futureplus com For Sales and Marketing Support FuturePlus Systems Corporation TEL 719 278 3540 FAX 719 278 9586 On the web http www futureplus com FuturePlus Systems has technical sales representatives in several major countries For an up to date listing please see http www futureplus com contact html Agilent Technologies is also an authorized reseller of manv FuturePlus products Contact anv Agilent Technologies sales office for details Product Warranty Limitation of warranty This FuturePlus Systems product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment During the warranty period FuturePlus Systems will at its option either replace or r
5. OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for FuturePlus Systems products For assistance contact the factory Introduction How to Use This Manual The USB Analysis Probe module provides a complete interface between any point on the USB and an Agilent Logic Analyzer The Analysis Probe interface receives the USB serial bit stream and converts it to an understandable parallel bus that is then acquired by the logic analyzer The USB Analysis Probe is a passive bus monitor which does not assert any signals on the USB The USB signals are received with a USB compliant transceiver The power for the Analysis Probe logic and transceiver is taken from the logic analyzer Thus the Analysis Probe does not draw power from the USB wire The USB Analysis Probe software configures all the logic analyzer menus for compatibility with the USB Analysis Probe When the configuration file is loaded and the analyzer is set to STATE mode an inverse assembler is also loaded which decodes USB packets into easy to read mnemonics The USB Analysis Probe also provides access to the actual USB wire for both digital and analog measurements D D GND USB Power and the transceiver outputs of VP VM and RCV are also provided on the test points This manual is organized to help you quickly find the information you need
6. The logic analyzer will flash Slow or Missing Clock if the USB Analysis Probe provided master clock signal is not being detected by the logic analyzer This will occur if the USB is IDLE or in an extended suspend state To accurately determine the state of the USB refer to the Timing analysis chapter in this manual Captured data is as shown in the following figure The following figure displays the state listing after disassembly The inverse assembler is constructed so the mnemonic output closely resembles the actual commands status conditions messages and phases specified in the Universal Serial Bus specification Symbols on the PID variable have also been defined to help aid in analysis The non disassembled state listing displays USB mnemonics in addition to data All data address endpoint and frame number fields are displayed in hex 26 Analysis Probe related error messages USB CRC and Serial Bit Errors File Window Edit Options Markers Invasm Source a lt Drag gt to copy Drag and drop gt to move marker lt Right click gt to view FUTUREPLUS SYSTEMS 1997 USB BUS TRANSACTIONS REV 1 1 1 SOF 999 752 us SOF FRAME 022 ie 3 248 us SETUP ADDR 00 END POINT 0 SETUP 3 920 us GET_DESCRIPTOR DATAO Direction Device to Host Tupe Standard Recipient Device 1 336 us Descriptor Type Device 1 352 us wIndex 0000 1 312 us Length 0012 768 000 ns DATA CRC 072F 1 752 us ACKNOWLEDGE 986 064 us SOF FRAME
7. impart Wizard This wizard Wa guide you through the steps of importing 16700 Fast Binary format data int system Is the system already set up correctly for the 16700 data you wish to import Yes C No For Help press F1 Astr H E e IAA A lI Giinbox mi Gjepct x v B Fs1104 2 F51123_1 4 Microsoft al Status I EloMinel Offline SP zom After clicking next you must browse for the fast binary data file you want to import Once you have located the file and clicked start import the data should appear in the listing After the data has been imported you must load the protocol decoder before you will see any decoding To load the decoder select Tools from the menu bar when the drop down menu appears select Inverse Assembler then choose the name of the decoder for your particular product The figure below is a general 16 picture please choose the appropriate decoder for the trace you are working with PACE File Edit View Setup Tools Markers Run Stop Waveform Window Help Deusa EE New Inverse Assembly USB11 Inverse Assembler zi m EH New Bus Analysis gt PCI X Inverse Assembler MM to m2 36ns BB New Fiter Colorize SODDR2 Protocol Decoder DDR SODIMM Inverse Assembler EC Inverse Assembler Ctrl F USB20 Inverse Assembler DDRBasic Protocol Decoder S Overview Re order Delete etc AItHO isti DDR Inverse Assembler
8. that the on board serial ROM has successfully loaded the FPGA and that the USB Analysis Probe is ready for USB analysis The VCC LED on the USB Analysis Probe indicates that power is applied from the logic analyzer to the USB Analysis Probe logic For correct operation of the USB Analysis Probe the VCC LED must be lit 10 Connecting to the USB Analysis Probe Installing the USB Analysis Probe The following explains how to connect the logic analyzer to the USB Analysis Probe for either state or timing analysis 1 Remove the probe tip assemblies from the logic analyzer cables 2 Plug the logic analyzer cables into the USB Analysis Probe cable headers as shown in the appropriate following tables Logic Analyzer USB Analysis Comment Probe Master POD 1 State analysis POD 2 State analysis POD 3 Header 3 Timing analysis The USB Analysis Probe can be installed in any segment of the Universal Serial Bus However to view all packets from the Host the USB Analysis Probe must be placed between the Host and the USB Hub or USB device The following steps explain how to install the USB Analysis Probe onto the Universal Serial Bus 1 Install the logic analyzer cables as described in the previous section 2 Plug the USB Analysis Probe IN cable to the upstream Host or Hub The USB Analysis Probe OUT connector can be connected down stream to either a Hub or device or it can be left unconnected 3 Turn on the logic
9. zero condition 31 State Name State Encoding EOPR_STATE J state transition detected Valid end of packet SLOW_SEO FI RST First slow speed single ended zero condition detected SLOW_SEO_S ECOND First slow speed single ended zero condition detected packet condition occurring on the USB BAD EOPR ST 111 Incorrect ATE transition for single ended zero detected NOTE FEOPR will be generated in this case so that the next packet can be detected Users can look for this state if thev suspect a bad end of The load bvte count state machine is encoded as follows State Name State Encoding IDLE 0000 IDLE Have received end of svnc and currentiv receiving PID State Name State Encoding 32 Load Byte Count State Machine DELAV 1 0010 State delaved bv one clock tic DELAV 2 0011 State delayed by two clock tics SOF OR ADR 0100 Receiving address for token packet or Frame number SOF OR EP 0101 Receiving endpoint for token packet or the remainder of the frame number for start of frame CRC 0110 Receiving CRC data PRE DATA 0111 About to receive data DATA 1000 Receiving data available to be viewed with spare probes from the logic analyzer or a scope probe Test Points The format menu has been configured to include POD4 Pod 4 allows the user by means of attaching a flying led set to the stake pins to view the signals that 33 POD 4 Description the transc
10. FuturePlus Systems Corporation 06 Agilent Technologies we Innovating the HP Way Premier Solution Partner Hen UNIVERSAL SERIAL BUS USB Analysis Probe Users Manual FS4100 For Agilent Logic Analyzers Revision 2 7 FuturePlus Systems is a trademark of FuturePlus Systems Corporation Copyright 1998 FuturePlus Systems Corporation HOW TO REACH US PRODUCT WARRANTY Limitation of warranty Exclusive Remedies Assistance INTRODUCTION How to Use This Manual ANALYZING THE UNIVERSAL SERIAL BUS Duplicating the Master Diskette Accessories Supplied Minimum Equipment Required Revisions Signal Naming Conventions The USB Analysis Probe Switches and Diodes The Slow Speed Only Switch and LED USB Busy LED Ready LED VCC LED Connecting to the USB Analysis Probe Installing the USB Analysis Probe Setting up the Analyzers installed in the 16500 mainframe Setting up the 167xx Analyzer Setting up the 1680 90 900 Analyzer 1680 90 900 licensing Loading 1680 90 900 configuration files 1680 90 900 167xx Configuration files Offline Analysis The Format Menu 11 12 12 13 13 13 15 15 18 The STAT variable The ADDR and DATA variables The PID variable The CTLCMD variable COMBINATION MODE Bad EOP Detection Low Speed High Speed detection STATE ANALYSIS Installation Quick Reference Acquiring Data The State Display Analysis Probe related error messages USB CRC and Serial Bit Errors
11. L n a n PCI Inverse Assembler m n ii b 1 o E51117 F52332 DDR2 Protocol Decoder o o 7 i o i MegaCorp 999 Inverse Assembler o o 0 o HT Inverse Assembler Inverse Assembler o T U NG ILL f a Overview Hl Slot B DDR Waveform FE Slot B DDR Listing Status i Offline Astar ws e HG Qe linbox Mi BJENPCI X Hi es1104_2 F51123_1 amicrosoft SEtomine ki Fo 47 em After the decoder has loaded select Preferences if required from the overview screen and set the preferences to their correct value in order to decode the trace properly This is a general requirement some decoders do not have preferences if this is the case then no preference setting is necessary 17 The Format Menu The USB Analysis Probe diskette sets up the format menu as shown in the following table This format is the same for both Timing and State Analysis Pods 1 and 2 are for STATE analysis and POD 3 is useful for Timing analysis rev jo J The STAT variable The STAT variable is used by the USB inverse assembler to decode USB transactions t should not be changed or deleted from the format menu The ADDR and DATA The ADDR variable is the address and endpoint as variables decoded from the USB serial bit stream The DATA variable is the Data associated with a Data0 or Datat packet For ease of triggering the address and endpoint seen in the token packets Setup In and Out are latched by
12. Pod 3 of the USB Analysis Probe contains signals that describe in more detail the actual state of the USB wire The following procedure describes the major steps required to perform timing analysis measurements with the USB Analysis Probe module 1 4 After removing the probe tip assemblies plug logic analyzer header 3 into Analysis Probe header 3 Plug the USB Analysis Probe IN cable to the upstream Host or Hub The USB Analysis Probe OUT connector can be connected down stream to either a Hub or device or it can be left unconnected Position the LOW SPEED ONLY switch to the ON position LED lit if the USB Analysis Probe is on a low speed only segment Position the LOW SPEED ONLY switch to the off position led doused if the USB Analysis Probe is ona full speed link Turn on the logic analyzer so that the VCC and READY LEDs on the USB Analysis Probe are lit NOTE Connect the USB Analysis Probe to the USB wire as described in step 2 prior to powering up the logic analyzer 29 Acquiring Data Touch RUN and the logic analyzer will begin to acquire data The analyzer will continue to acquire data and will display the data when the analyzer memory is full the trigger specification is TRUE or when you touch STOP The logic analyzer will flash Waiting for Trigger or occurrences remaining in level x where x is number of the unsatisfied trigger level if the trigger condition is not satisfied POD 3 Descri
13. T AT END OF RESUME SIGNALING RESUME 111010 JSTATE SENT AT END SATE OF RESUME SIGNALING 110111 DETECTED INCORRECT J STATE AS EOP SIGNALING AT SLOW SPEED The CTLCMD variable The CTLCMD variable decodes the Setup Data into the appropriate command Standard Device Requests GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DESCRIPTOR SET_DESCRIPTOR 21 Standard Device Requests GET_CONFIGURATION SET_CONFIGURATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME COMBINATION The default mode set up by the software shipped with MODE the Analysis Probe is the following configuration 1M Sample LAC Configuration Run Analyzer Analyzer 2 Name USB_ST Name USE_TH Unassigned Pods Bad EOP Detection If the FS4100 operating in full speed mode detects a valid SEO for at least 6Ons but a valid J STATE does not follow it will do the following 1 Detect an end of packet FEOPR TRUE in Timing mode 2 Pass the packet up to the logic analyzer 3 Passa POSSIBLE BAD EOP status to the analyzer If the FS4100 operating in slow speed mode detects a valid SEO for at least 300ns but a valid J STATE does not follow it will do the following 1 Detect an end of packet FEOPR TRUE in Timing mode 2 Pass the packet up to the logic analyzer 22 Low Speed High Speed detection 3 Pass a POSSIBLE BAD EOP status to the Analyzer A status of POSSIBLE BAD EOP should be treated as
14. USB Analysis Probe presents one USB transceiver load onto the USB The Analysis Probe IN and OUT connectors D D GND and VCC are daisy chained so that the USB traffic is not interrupted All signal etch length trace velocity and impedance is within specification Operations All Universal Serial Bus operations supported 35 Environmental Temperature Altitude Humidity Testing and Troubleshooting Servicing Signal Connections Operating 0 to 55 degrees C 32 to 131 degrees F Non operating 40 to 75 degrees C 40 to 167 degrees F Operating 4 6000m 15 000 ft Non operating 15 3000m 50 000 ft Up to 90 non condensing Avoid sudden extreme temperature changes which would cause condensation on the Analysis Probe module There are no automatic performance tests or adjustments for the USB Analysis Probe module Ifa failure is suspected in the USB Analysis Probe contact the factory or your FuturePlus Systems authorized distributor The repair strategy for the USB Analysis Probe is replacement However if parts of the USB Analysis Probe module are damaged or lost contact the factory for a list of replacement parts The USB Analysis Probe module monitors signals for both state and timing analysis The below figure displays how the cable headers are numbered 39 37 35 33 31 29 27 25 23 2119171513119 75 31 40 38 36 34 32 30 28 26 24 22 20 18 16 1412108642 The following tables list the USB Analysi
15. analyzer on so that the VCC and READY LEDs on the USB Analysis Probe are lit NOTE Connect the USB Analysis Probe to the USB wire as described in step 2 prior to powering up the logic analyzer 11 Setting up the Analyzers installed in the 16500 mainframe Setting up the 167xx Analyzer The logic analyzer can be configured for USB analysis by loading the USB configuration file Loading this file will load the Universal Serial Bus inverse assembler and configure your logic analyzer for USB analysis 1 Install the 16500 USB Analysis Probe Software for the FS4100 flexible diskette in the disk drive of the logic analyzer 2 Configure the menu to Load the analyzer with the appropriate configuration file see table below 16555 16710 1 2 USB555 USB550 3 Execute the load operation to load the file into the target logic analyzer NOTE Do not select ALL or SYSTEM as the target of the load operation select the logic analyzer that is connected to the USB Analysis Probe The 16600 16700 requires a special install procedure to install the FS4100 software To accomplish this insert the diskette labeled 16700 702 Installation disk for the FS4100 into the 16700 702 diskette drive From the SYSTEM ADMINISTRATION TOOLS select INSTALL under SOFTWARE From the SOFTWARE INSTALL screen select the FLEXIBLE DISK and APPLY The package FS4100 will now appear Select it and then select INSTALL This procedure does not need to
16. be repeated It only needs to be done the first time the USB Analysis Probe is used When this has completed restart the logic analysis session and either invoke the Setup Assistant from the logic analyzer screen or load the appropriate configuration file from the Configs FuturePlus FS4100 directory The Setup Assistant will guide you in configuring the logic analyzer Select FuturePlus from the list on the left of the Setup Assistant screen and then USB from the list that then appears If you prefer to load the 12 Setting up the 1680 90 900 Analyzer 1680 90 900 licensing Loading 1680 90 900 configuration files configuration file yourself see table below for a list of analyzers and corresponding configuration files Note The Logic Analysis System s Operating System must be version A 01 40 00 with patches 034 and 035 or higher to be compatible with the software provided on the installation diskette for the 167xx The 1680 90 900 Analyzer is a PC based application that requires a PC running the Windows OS or a 16900 frame Before installing the protocol decoder for the USB protocol on a PC you must install the Agilent logic analyzer software Once the Agilent logic analyzer software is installed you can install the FS4100 protocol decoder by placing the CD ROM disk into the CD ROM drive of the target computer or Analyzer and executing the exe setup program that is contained on the disk The exe setup file can be execute
17. cautionary and the user would be advised to view the received signals in timing mode by doing the following 1 Attach POD 3 of the analyzer to POD 3 of the USB Analysis Probe 2 Attach a flying lead set to stake pins RCV VP and VM 3 In state mode trigger on PID POSSIBLE BAD EOP Using the arming control trigger the timing Analyzer from the State Analyzer 4 Once the State Analyzer Triggers switch to Timing Analyzer Waveform 2 The USB Analysis Probe can switch automatically from high speed to low speed upon the detection of the Preamble PID The Analysis Probe then detects only low speed traffic Upon the receipt of a low speed acknowledge or an internal time out greater than 16 low speed bit times The Analysis Probe will switch back to high speed The following explains in more detail the sequences the Analysis Probe looks for in making the decision whether to switch from high speed to low speed and back Sequence 1 1 Detection of a PREAMBLE switch to low speed 2 Look for SETUP or OUT packet in low speed then switch back to high speed 3 Look for PREAMBLE upon detection switch to low speed 4 Look for a single DATA packet or handshake or time out 5 On receipt of a DATA packet look for a handshake or time out 6 On receipt of a handshake or the occurrence of a time out the pre processor switches back to high speed 23 Sequence 2 1 Detection of a PREAMBLE switch to low speed 2 Loo
18. d from within the File Explorer PC Utility You must navigate to the exe file on the CD ROM disk and then double click the exe file name from within the File Explorer navigation panel The installation procedure does not need to be repeated It only needs to be done the first time the Analysis Probe Adapter is used The USB Inverse Assembler is a licensed product that is locked to a single hard drive The licensing process is performed by Agilent There are instructions on this process on the SW Entitlement certificate provided with this product When the software has been licensed you should be ready to load a configuration file You can access the configuration files by clicking on the folder that was placed on the desktop When you click on the folder it should open up to display all the configuration files to choose from If you put your mouse cursor on the name of the file a description will appear telling you what the setup consists of once you choose the configuration file that is appropriate for your configuration the 16900 operating system should execute The protocol decoder automatically loads when the configuration file is loaded If the decoder does not load you may load it by selecting tools from 13 the menu bar at the top of the screen and select the decoder from the list After loading the configuration file of choice go into the format specification of the configuration by choosing Setup from the menu bar and th
19. eiver is generating in response to the USB traffic POD 4 channel jj Signal Name RCV Differential data signal from the USB transceiver VM Signal from the USB transceiver VP Signal from the USB transceiver The Waveform Captured data is displayed as shown in the following Display figure l 100 500MHz LA B l Haveform 1 aca Control Cancel PID x gt crc DATA CRC ERR oft Symbol Symbol 0 gt CRC DATA CRC ERR Screen sec Div Delay Markers Xoto Oo Trig to EA ta 0 200 ns po AQ us Time 2 ee us EE 62 Us EER 80 us LILILILILILI USBRSMa 34 General Information This chapter provides additional reference information including the characteristics and signal connections for the USB Analysis Probe module Characteristics The following operating characteristics are not specifications but are typical operating characteristics for the USB Analysis Probe Standards Supported The Universal Serial Bus Specification Revision 1 0 Power Requirements The USB Analysis Probe does not draw power from the USB wire All power is provided by the logic analyzer Logic Analyzer Required 166x 167x 1655x Number of Probes Used USB State Analysis 2 PODS USB Timing Analysis 3 PODS Supported speeds The USB Analysis Probe supports both full speed and low speed operation Signal loading The
20. en selecting Bus Signal in the drop down menu When the format specification appears press Define Probes at the bottom of the screen The Define Probes feature will describe how to hook the analyzer cards to the connections on the target The following figure shows what the Define Probes screen looks like The figure below may differ from your display this is an example of how the display looks in general Analyzer Setup for Embedded DDR2 J pa laj x Buses Signals Sampling l Enter buses and signals and the channels they correspond to VU ie port At Display aj aj Threshold User 900 mv Threshold User 900 mv Bus Signal Name ee sel Master Clock Master Clock 10 SUH R169 6 TES FF 210 HHH RMM SF TES F216 GEBRIS 65 43210 kereslete fee utasa facae arjo 6 Efectos eee oak es eee 5 DDR2 Commande Ciks C1 1 J ADDRESS poss Ca TT ADDRESS PodB1 15 0 VAISS Bank Addres Pod B216 4 DATALow Pod D3S 6 3 DATAHi Pod C3S 14 READdataLcPod D3MI6 3 READ ath iPod Coeds E53784 34 ch single end Slot B Pod 1 Slot B Pod 2 IC DASB 0 PodDISM2 E5378A 34 ch single end SlotB Pod 3 Slot D Pod 1 IC ReadDASS IPod D3M 12 E ingle end Slot D Pod 3 Slot C Pod 1 IC DQS17 9 Pod Atsit 0 ES ch single enc Slot C Pod 3 Slot A Pod 1 IC ReadDQS17 Pod A1M 1 0 Command Pod B2 3 1 50 Ciks C2 51 Pod B2 7 52 Pod B2 8 53 Pod B2 9 LESI ReadCB Pod A1M 3 2 cB Pod 41518 2 JT RAS Pod B2 3 I cas Pod B2 2
21. epair products proven to be defective For warranty service or repair this product must be returned to the factory For products returned to FuturePlus Systems for warranty service the Buyer shall prepay shipping charges to FuturePlus Systems and FuturePlus Systems shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to FuturePlus Systems from another country FuturePlus Systems warrants that its software and hardware designated by FuturePlus Systems for use with an instrument will execute its programming instructions when properly installed on that instrument FuturePlus Systems does not warrant that the operation of the hardware or software will be uninterrupted or error free The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the 5 Exclusive Remedies Assistance product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED FUTUREPLUS SYSTEMS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE REMEDIES PROVIDED HEREIN ARE BUVER S SOLE AND EXCLUSIVE REMEDIES FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL
22. is Probe to perform timing analysis Installation Quick The following procedure describes the major steps Reference required to perform measurements with the USB Analysis Probe module The following explains how to connect the logic analyzer to the USB Analysis Probe for state analysis 1 Remove the probe tip assemblies from the logic analyzer cables 2 Plug the logic analyzer cables into the USB Analysis Probe cable headers as shown in the following table Logic Analyzer USB Analysis Comment Probe Master POD 1 Header 1 State analysis USB_ST POD 2 Header 2 State analysis USB_ST 3 Plug the USB Analysis Probe IN cable to the upstream Host or Hub The USB Analysis 25 Acquiring Data The State Display Probe OUT connector can be connected down stream to either a Hub or device or it can be left unconnected 4 Turn on the logic analyzer so that the VCC and READY LEDs on the USB Analysis Probe are lit NOTE Connect the USB Analysis Probe to the USB wire as described in step 2 prior to powering up the logic analyzer 5 Load the USB Analysis Probe software for the appropriate logic analyzer The logic analyzer is now ready for STATE analysis Touch RUN and as soon as there is activity on the bus the logic analyzer will begin to acquire data The analyzer will continue to acquire data and will display the data when the analyzer memory is full the trigger specification is TRUE or when you touch STOP
23. k for IN packet and a following DATA packet and then switch back to high speed If a DATA packet is not received within the time out period 18 bit times the Analysis Probe will switch back to high speed 3 In high speed look for PREAMBLE and handshake If the Analysis Probe is placed on a low speed only segment the low speed only switch must be placed in the on position LED lit This is because on a low speed only segment the Host or Hub will not send a Preamble PID NOTE The low speed only switch need only be placed in the ON position if the Analysis Probe is placed on a LOW SPEED ONLY SEGMENT no high speed traffic present If users are on a mixed high speed low speed segment and suspect that low speed high speed USB specification protocol is not being adhered to the following steps should be taken 1 Acquire USB traffic with the Analysis Probe Low Speed only switch in the OFF position 2 Acquire USB traffic with the Analysis Probe Low Speed Only switch in the ON position 3 Note any differences and refer to timing mode to determine any out of specification conditions 24 State Analysis This chapter explains how to configure the USB Analysis Probe to perform state analysis on the Universal Serial Bus The configuration software on the flexible diskette sets up the format specification menu of the logic analyzer for compatibility with the USB Analysis Probe The next chapter explains how to configure the USB Analys
24. ormation refer to the reference manual for your logic analyzer The USB Analysis Probe product consists of the following accessories e The USB Analysis Probe interface hardware e The inverse assembly and configuration software on a 3 5 inch diskette e This operating manual Minimum Equipment Required Revisions Signal Naming Conventions The USB Analysis Probe Switches and Diodes The Slow Speed Only Switch and LED USB Busy LED Ready LED VCC LED The minimum equipment required for analysis of a Universal Serial Bus consists of the following equipment e A 166x 167x 1680 90 1671x 1674X 1655x or 1675x logic analyzer e The USB Analysis Probe Product e A USB target wire This manual applies to Hardware revisions ACE or later and software revision 3 0 or later This operating manual uses the same signal notation as the UNIVERSAL SERIAL BUS SPECIFICATION REVISION 1 0 The USB Analysis Probe contains one switch and four LEDs The slow speed switch should be in the ON position LED ON when the USB Analysis Probe is on a slow speed only wire or slow speed only segment of the USB When attached to a high speed segment or mixed segment slow speed and high speed traffic the switch should be in the OFF position LED OFF The USB Busy LED is lit when the USB Analysis Probe is actively receiving packets from the USB wire The LED may appear dim if the traffic load is light The Ready LED indicates
25. package on a 1680 90 900 analyzer and would like to have the offline analysis feature on a PC you may buy additional licenses please contact FuturePlus sales department In order to view decoded data offline after installing the 1680 90 900 operating system on a PC you must install the FuturePlus software Please follow the installation instructions for Setting up 1680 90 900 analyzer Once the FuturePlus software has been installed and licensed follow these steps to import the data and view it From the desktop double click on the Agilent logic analyzer icon When the application comes up there 15 will be a series of questions answer the first question asking which startup option to use select Continue Offline On the analyzer type question select cancel When the application comes all the way up you should have a blank screen with a menu bar and tool bar at the top For data from a 1680 90 900 analyzer open the ala file using the File Open menu selections and browse to the desired ala file For data from a 16700 choose File gt Import from the menu bar after selecting import select yes when it asks if the system is ready to import 16700 data Offline Agilent Logic Analyzer Bie Edit View Setup Tools Markers Run Stop lt No Active Windows Window Help Dsaa aae le Taja b ee V74Z gt gt a e ws l 16700 Fast Binary Data Import Wizard Welcome to the 16700 Fast Binary D ata
26. ption Pod 3 was included in the USB Analysis Probe to give the user a detailed look at the USB wire The USB Analysis Probe interface contains its own fully compliant USB serial interface engine SIE The state bits for the USB state machines for this SIE are available on POD 3 In addition the recovered clock recovered data start of frame end of packet end of sync and low speed high speed detect signals are available These signals are useful for e Shadowing the state of the target USB SIE when that SIE state is unavailable e Comparing the state of the target USB SIE with that of the Analysis Probe SIE e Making accurate time measurements of USB events e Accurate USB protocol violation detection e Accurate USB signaling violation detection POD 3 channel 3 channel Signal Name Name Signal Name Description poo same jew 2 Recovered Clock Recovered Serial Data 30 POD 3 channel jj Signal Name 14 SOFTIC Start of Frame 1 millisecond timer generated from recovered start of frame 13 11 EOP2_0 End of Packet state machine 10 7 LBC3_0 Load Byte State Machine Detect eo The end of packet state machine state encodings are End of Packet State as follows Machine State Name State Encoding Idle state SEO_FIRST First sample of the single ended zero condition SEO_SECOND 010 Second sample of the single ended zero condition SEO_THIRD 110 Third or more sample of the single ended
27. s Probe cable headers and the corresponding Universal Serial Bus signals 36 Analysis Probe Logic Analyzer USB Analysis Cable Header and channel number Probe Signal Pin number name Header 3 pin3 CLK 16 CLK12 PS re comest LBC lt 0 gt a sr s eee a a o prose LSDET 0 unused 37 Cable Header and channel number Probe Signal Pin number name P 5 nocomest 7 15 STAT4 15 11 STATO 17 10 ADRO6 ANG FI 7 erja se oe at spor sare 38 Analysis Probe Logic Analyzer USB Signal name Cable Header and channel number Pin number Fs fem ee p D11 D10 39
28. the USB Analysis Probe and held through the reporting of the data for the DATAO and DATA packets The PID variable The PID variable describes the PID and various errors detected by the USB Analysis Probe This variable is most effectively used for triggering and are available to be used in combination with any other variable defined in the FORMAT menu Symbol Binary Code Comment 19 RESET END 111001 RESET DEASSERTS INVALID 011101 INVALID PID RECEIVED BAD PID 011110 BAD PID RECEIVED SUSPEND 411110 SUSPEND CONDITION DETECTED RESUME 111101 RESUME CONDITION DETECTED 411011 KEEP ALIVE 001001 SETUP PACKET WITH SERIAL BIT STUFFED ERROR DETECTED IN SBS ERROR 001010 IN PACKET WITH SERIAL BIT STUFFED ERROR DETECTED 001011 OUT PACKET WITH SERIAL BIT STUFFED ERROR DETECTED 001100 START OF FRAME SERIAL BIT STUFFED ERROR DETECTED 001101 DATAO PACKET WITH SERIAL BIT STUFFED ERROR DETECTED 001110 DATA1 PACKET WITH SERIAL BIT STUFFED ERROR DETECTED 001111 CRC DATA WITH SERIAL BIT STUFFED ERROR DETECTED 010001 SETUP PACKET WITH CRC ERROR DETECTED IN CRC ERROR 010010 IN PACKET WITH CRC 20 ERROR DETECTED SOF CRC 010100 START OF FRAME ERROR PACKET WITH CRC ERROR DETECTED OUT CRC 010011 OUT PACKET WITH CRC ERROR ERROR DETECTED CRC DATA 010111 CRC DATA WITH CRC CRC ERR ERROR DETECTED ANY ERROR 111000 ERROR SUMMARY BIT SLOW SOF 011111 SOF TOKEN DETECTED AT SLOW SPEED RESUME SEO 111100 SEO SEN
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