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Agilent Technologies 16700 Musical Instrument Amplifier User Manual

1. Figure 4 7 Connector panel of the 16534A oscilloscope module 32 Data Acquisition and Stimulus Pattern Generation Modules Digital Stimulus and Response in a Single Instrument Configure the logic analysis system to provide both stimulus and response in a single instrument For example the pattern generator can simulate a circuit initialization sequence and then signal the state or timing analyz er to begin measurements Use the compare mode on the state analyzer to determine if the circuit or subsys tem is functioning as expected An oscilloscope module can help locate the source of timing problems or troubleshoot signal problems due to noise ringing overshoot crosstalk or simultaneous switching Key Characteristics Agilent Model 16720A Maximum clock full half channel Parallel Testing of Subsystems Reduces Time to Market By testing system subcomponents before they are complete you can fix problems earlier in the development process Use the Agilent 16720A as a substitute for missing boards integrated circuits ICs or buses instead of waiting for the missing pieces Software engineers can create infrequently encountered test conditions and verify that their code works before complete hardware is available Hardware engineers can generate the patterns necessary to put their circuit in the desired state operate the circuit at full speed or step the circuit t
2. labels The labels can even come from lt Decimal Decimal B different analyzers 20 66 Al 19 67 J 68 File Window Edit Options Invas Source Help 66676069 AD A d 1 6A o SO T E mn n a l PEATE e ee A 60 6E 6F 70 6E6F7071 AF C 71 72 74 5 72737475 BO D 75 4 76 3 77 2 738 76777879 B1 E 79 2 7c 3 7A787C7D0 B2 F 7 4 7E 5 7F 44 000 n 40 000 n 9 9 Output of Custom Tool 3 333 3 3 SR HRSS DRO aS 8 gt po Parameters Tool Development Kit lt 1 gt At left are the parameter window and Alignment Offset MUX Factor Select Order First ADDR value is Most Least Significant message display created by the custom tool in this example Parameters allow the user to control different aspects of what the tool does to the acquired trace The user can change the parameters and hit the execute button to change the output of the tool The output dialog to the left displays information generated by the tool aie ACCA ra J Original ADDR length MuxFactor used 4 New mixed ADOR length 32 H Parameter and Output Windows Figure 5 23 Post Processing and Analysis Tool Sets Tool Development Kit Custom Tool Development Select this button to cause the compiled code Environment to operate on the acquired data This is the main window for developing code with the tool development kit File Window Edit View
3. Timer reset latency 60 ns 60 ns Data in to BNC port out delay latency 150 ns 150 ns Flag set reset to evaluation latency 110 ns 110 ns Environmental Operating temperature 0 deg C to 45 deg C 99 State Timing Modules Specifications and Characteristics Agilent Technologies 16760A Supplemental Specifications and Characteristics continued Eye scan mode 1 5 Gb s mode 800 Mb s mode Maximum clock rate 1 5 Gb s 800 Mb s Sample position range relative 5ns to 10 ns 4 ns to 4 ns to clock Sample time position resolution 12 ps 12 ps Sample position time accuracy 50 ps 0 01 sample position 50 ps 0 01 sample position Number of channels 16 number of modules 34 number of modules 1 Input dynamic range 3 0 Vdc to 5 0 Vdc 3 0 Vdc to 5 0 Vdc Threshold range 3 0 Vdc to 5 0 Vdc 3 0 Vdc to 5 0 Vdc Threshold resolution 2 mV 2 mV Threshold accuracy 30 mV 1 of setting 30 mV 1 of setting Equivalent rise time 1 150 ps 150 ps Equivalent bandwidth 1 2 33 GHz 2 33 GHz Minimum detectable pulse width 500 ps 750 ps at minimum signal amplitude 1 Jitter 10 ps RMS 10 ps RMS Noise floor 25 mV p p 25 mV p p Channel to channel skew maximum 100 ps 100 ps between any two channels 1 E5378A E5379A and E5382A probes only Qualified eye scan mode Channels available Timing In the qualified eye scan mode a sing
4. Trigger sensitivity See notes e dc to 50 MHz 50 MHz to 500 MHz 0 06 full scale 0 13 full scale Input resistance 1MQ 1 50Q 1 Specifications refer to the input to the BNC connector Notes Specifications apply only within 10 C of the temperature at which the most recent calibration was performed Specifications apply only after operational accuracy calibration is performed in the frame in which the oscilloscope module is installed Display magnification is used below 56 mV full scale For sensitivities from 16 mV to 56 mV full scale full scale is defined as 56 mV Characteristics General Maximum sampling rate 2 GSa s Number of channels 2 to 8 using the same time base and trigger Up to 10 channels may be installed in a single 16700 frame or up to 20 in a single system using a 16701 expansion frame Waveform record length 32768 points 101 Oscilloscope Modules Specifications and Characteristics 16534A Characteristics Vertical Voltage Vertical sensitivity range 16 mV full scale to 40 V full scale Vertical resolution 8 bits full scale Rise time calculated from bandwidth 700 ps dc gain accuracy 1 25 of full scale 0 08 per C difference from calibration temperature dc offset range Vertical sensitivity 16 mV full scale to 400 mV full scale 400 mV full scale to 2 0 V full scale 2 0 V full scale to 10 V full s
5. For Infiniium scope model number Software version for 16700 series logic analyzer Software version for oscillo Infiniium oscilloscope 54810A 54815A 54820A 54825A 54835A 54845A 54856A 54830B 54831B 54832B A 02 20 00 or higher A 02 50 00 or higher A 04 00 or higher A 01 00 or higher T Figure 5 25 Infiniium oscilloscope waveforms are displayed in the 16700 logic analyzer waveform display window along with logic analyzer timing wave forms accurately time correlated 74 The E5850A requires the versions of operating software indicated in the table Mainframe Specifications and Characteristics Agilent 16700 Series Technical Information System Software All features and functionality described in this document are available with system software version A 02 20 00 Mass Storage Hard Disk Drive 9 GB formatted disk drive Floppy Disk Drive e Capacity e Media e Formats 1 44 MB formatted 3 5 inch floppy MS DOS Read write format LIF Read only Internal System RAM Standard Option 003 Must be ordered at time of frame purchase Supported Monitor Resolutions Standard 128 MB 256 MB total 640 x 480 through 1280 x 1024 The 16702B has a built in 800 x 600 12 1 26 2mm diagonal monitor Option 003 Must be ordered at time of frame purchase Adds support for up to 1600 x 1200 LAN IEEE 802 3 Physical Connectors Protoco
6. Zlogic esds auto c line 132 error missing after statement 1456 logic eads auto c Line 223 warning double assigned to unsigned int 276 Output tab CC logic eads auto c line 227 warning double assigned to unsigned int 276 eee Error exit code 1 Figure 5 24 TDK development environment 71 Post Processing and Analysis Tool Sets Tool Development Kit Product Characteristics Analyzer compatible custom tools will run on any 16700 Series analyzer running version A 01 40 00 or greater In some rare instances changes in the operating system can require that your tools be recompiled in order to run on that version of the operating system Analysis and Stimulus Modules The tool development kit supports the following Agilent Technologies measurement modules e 16715A 16716A 16717A 16718A 16719A 16750A 16751A 16752A e 16710A 16711A 16712A e 16557D e 16556A D 16555A D e 16554A e 16550A e 16534A 16533A e 16517A 16518A e 16522A 16720A e 16740A 16741A 16742A C Compiler The libraries provided with the C compiler allow you to perform stan dard operations such as creating ASCII or binary files reading from these files writing or appending to these files and IEEE 764 floating point operations 72 Provided Functions Agilent Technologies provides a rich library of functions that allow you to copy data sets create new data sets with new labels and t
7. Provides same format as listing display including inverse assembled data Available via RPI and File Out Used to load large amount of stimulus gt 1M into the 16720A pattern generator Time Correlation Resolution 2ns Port In Out Connectors BNC Mainframe Specifications and Characteristics Agilent 16700 Series Technical Information continued Port In Levels TTL ECL or user defined Input Resistance 4 KQ Input Voltage 6V at 1 5 mA to 6V at 1 6 mA Port Out Levels 3V TTL compatible into 50 Q Functions Latched latch operation is module dependent Pulsed width from 66 ns to 143 ns Target Control Port Number of signals 8 Levels 3V TTL compatible Connector 2 rows of 5 pins 0 1 inch centers Operating Environment Temperature Instrument Disk Media Probes Cables 0 C to 50 C 32 F to 122 F 10 C to 40 C 50 F to 104 F 0 C to 65 C 32 F to 149 F Altitude To 3000m 10 000 ft Humidity 8 to 80 relative humidity at 40 C 104 F Printing Printer Interface Parallel interface for Centronics compatible printers Printers Supported PostScript printers and printers which support the HP Printer Control Language PCL Graphics Graphics can be printed directly to the printer or to a file Graphic files can be created in black and white or color TIFF format PostScript PCX or XWD formats 77 Mainframe Specifications and C
8. Product Description The tool set s main advantage is its ability to allow you to observe soft ware execution without halting the system or adding instructions to the code The tool set uses information provided in your compiler s object file to build a database of source files line numbers and symbol information to reference to logic analyzer traces The tool set can also be used to set up the logic analyzer trace by simply pointing and clicking on a source line Once the tool set is enabled on your 16700 Series system you can support new processors by changing analysis probes and verifying object file com patibility Multiple processor systems are also supported a Analyzer Trace Figure 5 2 The source correlation tool set allows you to observe software execution without halting the system or adding instructions to the code 41 Post Processing and Analysis Tool Sets Source Correlation When You Want L L Displayed File hplogic demo 960_deno_board source eos2 c to Trace maini t boot qi on a variable to see what caused data init systeni IEE corruption proc spec init 12 for 1521 L updete_susten Z pu checks on a function to determine where it is being HA num_cnecks e update_diselay lt num_checks c F called from in order to understand the context E vars sti of a system error EET AE EETA ETEA AN FUNCTION update display i gt PARMS counter
9. State Overview Tool Narrow in on an area of interest Pinpoint regions of high memory activity to using built in qualification and zoom determine which routines or operations are functions responsible for throughput bottlenecks MB Analog Distribution T RR File Window Graph Options De Oe S ee mralyete Mixed Signal TS PS ES floualify data State Overview reset Measure memory coverage or stack usage by observing whether memory locations are accessed You can also quently used 49CC 4BC3 Data Values Display Information Bucket Information Qualified States 32 768 Hits d 142 5 94 Total Acquisitions 1 Hits t 142 0 43 Total Display 7 30 Range 4B04 4B09 Displayed States 2 392 Min Max 4B08 4B08 Base Hex oO Figure 5 12 Identify which events occur most frequently detect which peripherals are most fre 57 Post Processing and Analysis System Performance Analysis State Interval Tool Display just the symbols you want to evaluate by using the symbol navigation utility The util ity automatically configures the too vari for the selected function and able names from large symbol files created by complex software proj ects To help simplify your display delete all functions below a selected point with a single mouse click 58 Sort and display symbols alphabetically by event name or by the number of hits R State Interval Lo T File Win
10. Canada tel 877 894 4414 fax 905 282 6495 China tel 800 810 0189 fax 800 820 2816 Europe tel 31 20 547 2323 fax 31 20 547 2390 Japan tel 81 426 56 7832 fax 81 426 56 7840 Korea tel 82 2 2004 5004 fax 82 2 2004 5115 Latin America tel 305 269 7500 fax 305 269 7599 Taiwan tel 0800 047 866 fax 0800 286 331 Other Asia Pacific Countries tel 65 6375 8100 fax 65 6836 0252 Email tm_asia agilent com Product specifications and descriptions in this document subject to change without notice agilent Technologies Inc 2002 Printed in USA June 25 2002 5968 9661E 7 Agilent Technologies
11. Emulation Modules Emulation Control Interface The emulation control interface is accessed from the power up screen of the Agilent 16700 Series system The interface is included with the Agilent E5901A B emulation modules Designed for hardware engineers this graphical user interface provides the following features e Control over processor execution run break reset step e Register display modification e Memory display modification in various formats including disas sembly for code visualization Memory modification or memory block fill can be done to check processor memory access or to reinitialize memory areas e Multiple breakpoint configuration hardware software and processor internal breakpoint registers e Code download to the target e Command scripts to reproduce test sequences The ability to trigger a measure ment module on a processor break or to receive a trigger from the logic analysis system s measure ment modules Integrated Debugger Support When the hardware turn on phase is completed the same Agilent emula tion module can be connected to high level debuggers for C or C software development You can achieve the functionality of a full featured emulator by using a third party debugger to drive the installed Agilent emulation module This gives you complete microproces sor execution control run control 38 File Starting Address 000148B0 00
12. IntuiLink Programming Examples Provided with IntuiLink Visual Basic Examples have been included for use with Visual Basic 5 0 or higher These examples perform simple functions such as system checks oscilloscope measurements pass fail tests using stored configuration and pattern generator stimulus files and stimulus response tests They also can capture and retrieve data for off line analysis Visual C Examples have been included for use with Visual C 5 0 or higher to perform simple functions such as system check capturing and retrieving data for off line analysis LabVIEW An instrument library has been included for use with LabVIEW 5 1 or higher This library contains five LabVIEW samples that provide a starting point for creating your own LabVIEW programs Load Run Save loads a configuration runs a measurement then saves results to a file Analyzer Listing runs the logic analyzer and displays data in a table Pass Fail runs the logic analyzer and compares the measurement data against a standard Scope Waveform runs the oscilloscope module and displays waveform data Scope Measurements runs the oscilloscope module and displays a number of oscilloscope measurements HP VEE An instrument library has been included for use with HP VEE 5 0 or higher that provides a starting point for creating your own application e Load Run Save loads a configuration runs a measurement then saves results
13. 10473A and 10498A 3 3 V clock pod and 6 lead set 10477A and 10498A e 3 state TTL 3 3 V data pod and 6 lead set 10483A and 10498A ECL clock pod and 6 lead set 10463A and 10498A ECL terminated pod and 6 lead set 10464A and 10498A e ECL unterminated pod and 50 Q shield coaxial lead set 10465A and 10347A e 5V PECL clock pod and 6 lead set 10468A and 10498A e 5V PECL data pod and 6 lead set 10469A and 10498A 3 3 V LVPECL clock pod and 6 lead set 10470A and 10498A 3 3 V LVPECL data pod and 6 lead set 10471A and 10498A e 1 8 V clock pod and 6 lead set 10475 and 10498A e 1 8 V 3 state data pod and 6 lead set 10476 and 10498A LVDS clock pod and 6 LVDS lead set E8140A and E8142A LVDS data pod and 6 LVDS lead set E8141A and E8142A e Add service manual Convert to one year on site warranty e 3 years return for repair service e 5 years return for repair service 121 Ordering Information Accessories for Agilent 16720A Pattern Generator Modules Accessories Description Accessories Description Model Number Model Number 10460A TTL clock pod 10476A 3 state 1 8 volt data pod 10461A TTL data pod 10477A 3 3 volt clock pod 10462A 3 state TTL CMOS data pod 10483A 3 state TTL 3 3 volt data pod 10463A 10463A ECL clock pod 10498A 8 channel probe lead set 6 long 10464A ECL data pod t
14. 16760A V V V A variety of measurement modules allow you to select the optimum combination of performance features and price to meet your specific needs now and in the future Data Acquisition and Stimulus State Timing Modules Improve Your Productivity with an Intuitive User Interface Agilent Technologies has made the user interface easy to understand and use Now you can spend more time making measurements and less time setting up the logic analyzer Timing Zoom provides 2 GSa s timing analysis simultaneous with state or Format allows you to conventional timing analysis on all group signals into buses channels Sampling rate and position Trigger defines what relative to trigger are adjustable E lt data is acquired 16716A 16717A 16740A 16741A S a Eei a 16742A 16750A 16751A and analyzer will acquire the data 16752A only Measurement configuration and Rio Analyzer lt q gt IZM Sample 333MYz Staterz GHz Timing Zoom C m data files can be loaded directly into Pek Window H TT eir the logic analyzer ECEE ea fo oe etc r delete or replace an event C OZ ais E im in eee fmalyzer Nave on ZES Menu tabs provide a logical progression through the setup of O Timing Mode Asynchronous sampling clocked internally by analyzer your measurement State Mode Synchronous sampling clocked by the Device Under Test State Mode Controls 333 MHz 32M State D Trigger Position Center E State and timing mode s
15. Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations Trigger actions Goto Trigger and fill memory Trigger and goto Timer start stop pause resume Global counter increment reset Occurrence counter reset Flag set clear Goto Trigger and fill memory Trigger and goto Timer start stop pause resume Global counter increment reset Occurrence counter reset Flag set clear Maximum global counter 16 777 215 16 777 215 Maximum occurrence counter 16 777 215 16 777 215 Maximum pattern range width 32 bits 32 bits Timer value range 100 ns to 5497 seconds 100 ns to 5497 seconds Timer resolution 5 ns 5 ns Timer accuracy 10 ns 01 10 ns 01 Greater than duration 6 ns to 100 ms in 6 ns increments 6 ns to 100 ms in 6 ns increments Less than duration 12 ns to 100 ms in 6 ns increments 12 ns to 100 ms in 6 ns increments Timer reset latency 70 ns 70 ns Data in to trigger out BNC port 150 ns typical 150 ns typical Flag set reset to evaluation 110 ns typical 110 ns typical All specifications noted by an asterisk are the performance standards against which the product is tested 94 State Timing Modules Specifications and Characteristics Agilent Technologie s 16760A Supplemental Specifications and Characteristics Probes E5378A Single ended E5379A Differential E5380A Mictor E5382A Single Ende
16. loop counter passed in Fram main a f DESCRIPTION on a line number to determine if a f e clear out the history buffer and update the current ascii dia NA p D of operating data asciit_old_data specific code segment is ever executed Snunpaaspnnnnasgnpngaagnanneaggnangagpnnnnggnnnngaspnngneegnnnges Pere deria counter hes ME_update_display 1 h70 4f C1 counter X 32 gt gt 72 2 Clear out the control history buffer clesr hist buffi 75 if counter X 32 randi X32 gt t ve Laza Output variables in clear text as well as controlling and controlled variables 7 ab func needed amp T strnopyl sscii_old dats 0 HEAT 16 else U Simply Click to trace about a variable function or ae line number to halt processor execution with an integrated emulation module when the trace event occurs to use text search to quickly navigate through hundreds of symbols To recall previous entries when rotating through debug tests to specify alignment conditions for processors that don t include lower address bits on the bus This is necessary if your processor uses bursting or byte enables when fetching instructions to use address offsets for code that is dynamically loaded or moved from ROM to RAM during a boot up sequence Figure 5 3 42 Post Processing and Analysis Tool Sets Source Correlation Once You Acquire the Trace step through the trac
17. to deliver the following features Automatic de skew Measurements between the logic analyzer and Infiniium oscillo scope are automatically de skewed in time This saves you time and gives you confidence in the meas urement results Combined waveform display The Infiniium oscilloscope wave forms are displayed in the wave form display window on the 16700 logic analyzer along with timing analyzer waveforms This allows you to instantly visualize time relationships among oscilloscope and timing measurements Global markers The global markers in the 16700 may be used to measure time among all measurements made in the logic analyzer and Infiniium oscilloscope measurements File Mirdow Edit Options o RIT a Goto Markers Search Commenta Analysis Mixed Signal B zare Hep Ties H rren Trigner EB Owens aj 200p Tise H froe I Aje 9 404 na 219 005 ns Compatibility acb div Baia 1 20 000 nw r e 5 to u Tracking markers The Infiniium oscilloscope s time markers track the global markers in the 16700 logic analyzer If you wish to view a waveform in greater detail on the oscilloscope s display or measure a voltage level using the oscilloscope s voltage markers this feature allows you to relate information on the oscillo scope s display precisely to corre sponding information on the logic analyzer display Figure 5 26 E5850A time correlation fixture
18. you may run into elusive 16742A 16750A 16751A Vary the Timing Zoom sample rate from 250 MHz to 2 GHz hardware problems Capturing glitches and verifying that your modules Efficiently characterize hardware with 500 ps resolution and 16752A state timing Vary the placement of Timing Zoom data around the trigger point design meets critical setup hold times can be difficult without the proper tools With Timing Zoom you have access to the industry s most powerful tool for high speed digital debug 2 GHz timing and high speed state HE Counter StateListing LTS Ee File Window Edit Options Invasm lee oO S le Counter sse State Number markers to time correlate 280 000 ns events across 248 000 ns multiple displays CE E8 220 000 ns 6 EJ 188 000 ns 5 EA 156 000 ns 4 EB 124 000 ns 3 EC 92 000 ns 2 ED 64 000 ns 32 000 ns HM TimingZoom lt 1 gt File Window Edit Options Counter_TZ Counter_TZ J Clock_TZ Timing Zoom labels are automatically created and marked with an _TZ extension Figure 4 3 Verifying critical edge timing in your system is easy with Agilent Technologies 2 GHz Timing Zoom technology Now it s easy to capture simultaneous information through a single connection Le Lope mimes e Pl _ 23 Data Acquisition and Stimulus State Timing Modules Eye Finder It takes less than a minute to run Agilent s eye finder
19. 000 U S dollars in trade in credit The total trade in credit may not exceed 100 of the cost of the eli gible new product s Any credit in excess of that amount may not be applied toward a later purchase Trade in credit amounts and prod uct eligibility are subject to change at any time without advance notice not eligible for purchase under this program All trade in products must be in working condition and have no interior exterior or performance modifications To ensure timely release of credit all trade in products must be returned to Agilent within 30 days after receipt of the newly pur chased Agilent product Customer is responsible for all costs associated with shipping the trade in product s to Agilent Additional requirements may apply Please contact your local Agilent sales office for information 115 Orderin g Information Mainframes and Mainframe Accessories Product Number Description Includes 16700B Modular mainframe with five measurement One DIN keyboard module slots and one emulation or multiframe One three button DIN mouse module slot One ten conductor flying lead cable for target control port Training kit One internal CD ROM drive One internal 3 5 floppy drive 16702B Modular frame with built in 800x600 LCD display Same as 16700B plus with touchscreen Includes five measurement 12 1 touchscreen display slots and one emulation or multiframe Display knob
20. 230 V 48 to 66 Hz 610 W max 16701A 115 230 V 48 to 66 Hz 545 W max 16702A 115 230 V 48 to 66 Hz 610 W max Weight Max Net Max Shipping 16700A 12 7 kg 27 0 lb 34 2 kg 75 4 Ibs 16701A 10 4 kg 23 0 Ib 32 0 kg 70 6 Ibs 16702A 15 2 kg 32 4 lb 36 7 kg 80 8 Ibs Weight of modules ordered with mainframes will add 0 9 kg 2 0 Ib per module 3 5 Inch Floppy Disk Drive 5566 BEBBE 0o80 eee Haw EET et o D On Off e Power Switch Screen Intensity Adjustment Keypads for Alpha Numeric Entry Figure 6 4 Agilent 16702A front panel Parallel Port LAN 10BaseT Monitor SCSI 2 Single Ended RS a LAN 10Base2 Five Slots for A g S ki 1 Two Slots for Measurement B l a Emulation Modules p gt 2 Modules S a i FS OOs EY Gp Target Control Port EF K X Port IN Keyboard ouse 548 64 21 6 h 556 3 21 9 Port OUT m 482619 0 L Figure 6 5 Back panel for Agilent models 16700A and 16702A 234 2 9 22 _ 425 7 16 76 LFS Figure 6 6 Exterior dimensions for the 16700A Series mainframe 82 Dimensions mm inches Expansion Frame Cable Connector Probing Solutions Specifications and Characteristics Probing Technical Speci
21. 2V and 47 Q series Clock output rate 300 MHz maximum Clock out delay only approximately 8 ns total in 14 steps 16720A only 11 ns maximum in 9 steps 16522A Clock input type ECL 10H116 with 50 KQ to 5 2v Clock input rate dc to 300 MHz Pattern input type ECL 10H116 with 50 KQ no connect is logic 0 Clock in to clock out approximately 30 ns Pattern in to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10474A CLK OUT CLK OUT WAIT 2 WAIT 1 WAIT 0 CLK IN NC NC 41Q CLKout gt 10H125 a 10H124 WAIT 10463A ECL CLOCK POD Terminated Unterminated A FOR USE WITH AGILENT PATTERN GENERATORS Gann gt 10H116 CLKin CLKin k VBB 50 kQ 5 2 V 5 2 V 10H116 330 Q 47Q CLKout gt 111 Pattern Generation Modules Specifications and Characteristics 10468A 5 volt PECL Clock Pod Clock output type Clock output rate 100EL90 5V with 348 ohm pulldown to ground and 42 ohm in series 300 MHz maximum Clock out delay only Clock input type approximately 8 ns total in 14 steps 16720A only 11 ns maximum in 9 steps 16522A 100EL91 PECL 5V no termination Clock input rate dc to 300 MHz Pattern input type 100EL91 PECL 5V no termination no connect is l
22. 3 3 The E5382A single ended flying lead probe set provides connections for 17 channels of the 16760A logic analyzer Figure 3 4 Surface mount IC clip 5090 4356 20 clips o Figure 3 5 0 5 mm IC clip 10467 68701 4 clips Figure 3 6 Wedge adapters connect to multiple pins of 0 5 mm or 0 65 mm OFP ICs Refer to Probing Solutions for Agilent Technologies Logic Analysis Systems publication number 5968 4632E for specific part numbers Refer to Probing Solutions for Agilent Technologies Logic Analysis Systems publication number 5968 4632E for specific solutions Probing Solutions Technologies Designing connectors into the target system Figure 3 8 Advantages Limitations Very reliable connections Requires advance planning in the design stage Saves time in making multiple connections Requires some dedicated board space Moderate incremental cost High density probing solutions Model Description Requires kit of 5 connectors Usable with number and 5 shrouds logic analyzers E5385A 100 pin probe with built in isolation networks for the logic analyzer 16760 68701 All except 16517A 16518A 16760A E5346A 34 channel 38 pin probe with built in E5346 68701 All except 16517A isolation networks for the logic analyzer 16518A 16760A E5351A 34 channel 38 pin adapter cable requires logic analyzer E5346 68701 All except 16517A isolation networks on the target 16518A 16760A E5339A 34 channel
23. Custom protocol definitions are used in both the trigger definition and packet display Display Features Color Filters and preferences gt Payload information Protocol layers Each protocol layer is displayed with a different color in the analyzer s lister display to allow easy viewing of protocol data Specific protocol layers and fields can be selected for viewing in the trace Provides many different views of the data Allows you to concentrate on the data of interest for a particular measurement Included after the header in a raw hex format Can be collapsed or expanded to create a custom view of the acquired data 47 Post Processing and Analysis Tool Sets Data Communications Edit or create a X Edit Protocol x protocol using the logic analyzer rotocol Name IEEE 802 3 Ethernet W Physical Layer user interface Field Definition Name Length Type PT Select a known protocol and add proprietary fields Dest Addr Ins Before Src Addr Length Type Ins After Mnemonic Field Type Protocol Indicator 4 Length bits ig 4 ir Format Hex Insert custom wrapper or field here Insert name num Format ber of bits and Hex Internet Protocol format for trigger Hex ARP Request and Hex ARP Response display Hex IPS Hex AppleTalk Datagram Hex Novell IPX Define any sym bols for both trigger and display of Add Modi
24. NEW Multiframe Configuration By connecting up to eight mainframes and expanders you can simultaneously view time correlated traces for all buses in a large channel count multibus system NEW Enhanced Mainframe Hardware Mainframe now includes a 40X CD ROM drive a 9 GB hard disk drive 100BaseT X LAN and 128 MB of internal system RAM optional 256 MB total Scalable System e State timing analyzers High speed timing Oscilloscopes Pattern generators gt Emulation modules gt Select the optimum combination of performance features and price that you need for your specific application today with the flexibility to add to your system as your measurement needs change View system activity from signals to source code Measurement Modules Interfaces The Agilent 16760A State Timing Module The Agilent 16750A 16751A and 16752A State Timing Modules The Agilent 16720A Pattern Generator With up to 1 5 Gb s state speed the 16760A lets you debug today s and tomorrow s ultra high speed digital buses NEW Eye scan gives a rapid comprehensive overview of signal integrity on hundreds of channels simultaneously With up to 400 MHz state speed and up to 32 MBytes of trace depth these modules help you address today s high performance measurement requirements See page 19 With up to 16 MVectors depth and 300 MVectors sec operation and up to 240 channels 1 of stimulus the 16720A provides a new level of capabi
25. Options Search Help Select this button to compile the code displayed in the Source Source Code Messages l Tool Info Code tab logic eads auto c define other program variables l unsigned numSamples 77 number of samples in each new DataSet char messagel100 2a String gearMessage S long long time Load a file created on another long long correlationTime 7 correlation time for DataSets system or create your code here int icelsiuss using the Source Code editor iny erty String invalidStr invalidStr Invalid Gear Position read runtime argument celsius io getArg O c Il io getArg O C Attach to the incoming dataset err de attach de if err gt L io printError err gt return 3 correlationTime ds getCorrelationTime 7 7 DataSets will be time correlated Compilation status is shown orr de seklimebias s at the bottom of the tool eres development kit Display window io printError err 72 return 3 Attach to the address label err lelAddressl attach ds ADDR gt if err gt L W S IS Compilation failed Line 129 Col 44 Runtime errors are displayed in the Runtime tab File Window Edit View Oytions Search Help Errors generated elas asl T during a compile Output generated are displayed in Saroa Udala Tool into during the tool s the Buildtime Bui ldt ime Runtime Output execution are tab displayed in the
26. Parallel Data Buses The data communications tool set shows parallel bus data at a protocol level on the logic analyzer Developers have the capability to find complex system level bus interaction problems in applications such as a switching or routing system Obtain Answers to the Following Questions e What is the time difference between two or more data paths and or a microprocessor e Did a packet make it through the switch or router e Why did a packet take so long to go through the switch or router e Where did an illegal packet come from e What is the latency on packet information e What is corrupting packets Product Description The Agilent Technologies B4640B data communications tool set adds protocol analysis capabilities to the logic analyzer for viewing parallel data buses e g UTOPIA or a propri etary data bus in a switching or routing system Each protocol layer is displayed with a different color in the logic analyzer lister display to allow easy viewing of the protocol data Payload information is included after the header in a raw hex format Filters are included to allow many different views of the data Protocol layers can be collapsed or expanded to create a custom view of the data acquired in the logic analyzer With the filters you can concentrate on the data of interest for a particular measurement The powerful protocol trigger macro allows easy trigger setup by eliminat ing the need t
27. Start of Frame Data Block Start label Pattern width Start pattern Specify the pattern that designates the start of a frame i Define Frame Serial Analysis lt 1 gt M bits 10110110111 LSB firs get immediate feed back as you configure lt Passed Data ist Bit Data Block O Remove stuffed after Pass entire data block Last Bit End of Frame Output Label Parallel Word width 8 Pass selected bits in data block Pass data from bit Through bit Through end of data block i Define Frame Serial Analysis lt 1 gt the tool set for your data This diagram changes as you make your framing and data block selections remove stuffed Os or 0 1s from the trace before other serial analysis functions are performed Some proto cols use bit stuffing to maintain clock synchronization Specify the portion of the data block for the serial to parallel Specify whether the end of frame occurs at the end of a data block of X bits or on a speci fied pattern I lt Passed Data ist Bit Data Block End of O End frame after data block offs End frame on pattern accept the default end of frame label End or enter a different name End label Pattern width End pattern End on pattern Start End conversion Last Bit Frame p k
28. With Off the Shelf Solutions for Many Common Microprocessors To help you design and debug your microprocessor based target systems Agilent offers different microproces sor specific products that let you get control and visibility over your microprocessor s internal and external data An analysis probe allows you to quickly connect an Agilent logic analyzer to your target system The analysis probe provides non intrusive capture and disassembly of micro processor and bus activity Analysis probes are available for over 200 microprocessors and microcon trollers Bus probes allow probing of popular bus architectures such as PCI AGP USB VXI SCSI and many others Flexible physical probing schemes give quick and reliable connections to almost any device on your prototype On Chip Emulation Tools Make Fixing Bugs Easier For specific microprocessor families that feature on chip emulation you can add a processor emulation module to your system to connect the on board debugging resources of the microprocessor to the logic analysis system The microprocessor s BDM or JTAG technology provides control over processor operation even if there is no software monitor on the target system This feature is particularly helpful during the development of your target system s boot code Figure 4 10 Agilent analysis probes make it easy to connect a logic analyzer to your target system 37 Data Acquisition and Stimulus
29. and analog measurements can help you in solving these tough problems Help s Eleje m ty Gad Channels am Scale 500 m div Offset 1 600 Y Scope controls and waveform display are inte grated into a single window making interac tive adjustment easy 500 m div 1 600 Y 2 00 GSa s Time and voltage markers allow you to measure signal details precisely Scale 5 00 ns div Delay Trigger icon indicates trigger level making it easy for you to adjust trigger level Channel C1 G Ground icon always shows you where ground is relative to signal Figure 4 5 All primary oscilloscope control settings including scale factors and trigger settings are visible simultaneously 30 Data Acquisition and Stimulus Oscilloscope Modules Automatic Measurements Quickly Characterize Signals The Agilent Technologies 16534A oscilloscope modules quickly charac terize signals with automatic meas urements of rise time voltage pulse width and frequency Markers Easily Set Up Timing and Voltage Margin Measurements Four independent voltage markers and two local time markers are avail able to quickly set up measurements of voltage and timing margins 2GSa s Oscilloscope C Scope lt C gt File Window Setup Autoscale Options The global time markers of the 16700 Series logic analysis systems let you correlate state timing and oscillo scope measurements to trac
30. be a combination of symbolics and hardware events Data qualification can be used to define the specific hardware context in which the analysis will be made Rng L SR File Window Graph Options Sort Help Pieler a VEL Time Interval Time Ranges Hits 207 81 us 207 831 14419 2 207 831 us 207 852 9 12 3 207 852 us 207 873 5 6 8 207 873 us 207 894 6 8 2 207 894 us 207 915 5 6 8 207 915 us 207 936 5 6 8 207 936 us 207 957 6 8 2 207 957 us 207 978 79 6 207 978 us 207 999 5 6 8 207 999 us 208 02 11 15 1 T T T T T 16 67 33 33 50 66 67 83 33 100 Display Information Total Acquisitions 1 Range 207 81 us 207 831 us Total Display 100 00 Min Max 207 81 us 207 83 us Total Buckets 10 Mean 207 822 us Figure 5 14 Determine a specific routine s execution times Data is displayed in histograms which can be exported to your host computer either as histograms or as tabular formatted text files Statistics such as maximum time minimum time standard deviation and mean help you document system behav ior Use accumulate mode to analyze the behavior of your system over a long period of time 59 Post Processing and Analysis Tool Sets System Performance Analysis Time Overview Tool Use Comments to document your trace The Comments field contents are saved with the configuration and data Use the markers in this window to correlate interrupts
31. can select from a variety of pods to provide the signal source needed for their logic devices The data pods clock pods and data cables use standard connectors The electrical characteristics of the data cables also are described for users with specialized applications who want to avoid the use of a data pod The 16720A can be configured in systems with up to five cards for a total of 240 channels of stimulus Direct Connection to Your Target System The pattern generator pods can be directly connected to a standard connector on your target system Use a 3M brand 2520 Series or similar connector The 16720A clock or data pods will plug right in Short flat cable jumpers can be used if the clearance around the connector is limited Use a 3M 3365 20 or equiv alent ribbon cable a 3M 4620 Series or equivalent connector on the 16720A pod end of the cable and a 3M 3421 Series or equivalent connector at your target system end of the cable Probing Accessories The probe tips of the Agilent 10474A 10347A and 10498A lead sets plug directly into any 0 1 inch grid with 0 026 inch to 0 033 inch diameter round pins or 0 025 inch square pins These probe tips work with the Agilent 5090 4356 surface mount grabbers and with the Agilent 5959 0288 through hole grabbers Other compatible probing accessories are listed in ordering information on page 121 Data Acquisition and Stimulus Emulation Modules Speed Problem Solving
32. gives you the ability to position the setup and hold window with 10 ps resolu tion Small amplitude signals Many high speed designs use small signal amplitudes to limit slew rates and reduce power Agilent s 16760A can make reliable measurements on signals as small as 200 mV p p Description Mechanical drawings electrical models e Differential signals Many high speed designs use differen tial signaling to minimize simultane ous switching noise and to provide immunity to crosstalk and noise The Agilent 16760A has differential inputs to allow you to acquire differential signals with complete confidence Single ended probes are also available Agilent helps you get started in the design stage To probe high speed signals with a logic analyzer you need to design the probe in when you are designing your PC board The following document from Agilent will help you design your system to take maximum advantage of the capabilities of the 16760A logic analyzer e Logic signal standards supported TTL LVTTL HSTL Class I amp II HSTL CLass III amp IV SSTL2 SSTL3 AGP 2X LVCMOS 1 5V LVCMOS 1 8V LVCMOS 2 5V LVCMOS83 3V CMOS 5V ECL LVPECL PECL User defined from 3V to 5V in 10mV increments Publication Number 16760 97007 general information on probes for the 16760A Designing High Speed Digital Systems for Logic Analyzer Probing Guidelines and design examples for designing 5988 2989EN log
33. is valid for 21 calendar days from first entry of the password in the license management window of the 16700 Series logic analysis system Licenses are managed from Licensing in the Admin tab of System Admin Licenses are reserved at the start of a measurement session They remain in use until the measurement session is terminated Passwords can be backed up to a floppy disk or network file Should the passwords on your 16700 Series logic analysis system hard drive become corrupted the tool set passwords can be reinstated by copying your backed up password file to system licensing license dat 73 Time Correlation with Agilent Infiniium Oscilloscopes E5850A Logic Analyzer Oscilloscope Time Correlation Fixture E5850A Logic Analyzer Oscilloscope Time Correlation Fixture The Agilent E5850A time correlation fixture allows you to make time cor related measurements between a 16700 logic analyzer and an Agilent 548XX Series Infiniium oscilloscope to solve the following types of prob lems more effectively e Verifying signal integrity e Tracking down problems caused by signal integrity e Verifying correct operation of A D and D A converters e Verifying correct logical and tem poral relationships between the analog and digital portions of a design Agilent s E5850A time correlation fixture works in conjunction with software in the 16700 family logic analyzers and any Agilent Infinitum 54800 Series oscilloscope
34. make eye diagram measurements quickly and easily on hundreds of channels simultaneously 16760A only Triggering for the VisiTrigger combines powerful trigger functionality with a user interface most elusive that is easy to understand and use Capturing complex sequences of problems events is as simple as pointing to the function you want to use and filling in the blanks to customize it to your specific situation Reliable Eye finder automatically adjusts the setup and hold on every channel measurements eliminating the need for manual adjustment and ensuring the highest on high speed confidence in accurate state measurements on high speed buses buses High speed Timing Zoom provides the data acquisition speed you need for high speed timing on microprocessors and buses all channels Choose the Logic Analyzer and Measurement Modules that Best Fit Your Application State Timing General 8 16 Bit 32 64 Bit High Timing Deep trace High Analysis of Modules purpose processor processor speed margin capture speed data intensive hardware debug debug or bus analysis or with timing computer systems and debug channel analysis characterize or state debug performance intensive setup hold analysis systems 16710A V V 16711A V V 16712A V V 16715A V V V 16716A V V V V V 16717A V V V V V 16740A V V V V V V 16741A V V V V V V 16742A V V V V V V 16750A V V V V V V 16751A V V V V V V 16752A V V V V V V
35. maximum in 9 steps 16522A Clock input type 74AVC16244 3 6V max Clock input rate Pattern input type dc to 200 MHz 74AVC16244 3 6V max no connect is logic 0 Clock in to clock out approximately 30 ns Pattern in to recognition Recommended lead set approximately 15 ns 1 clk period Agilent 10498A 10475A 1 8 volt Clock Pod Clock output type TAAVC16244 Clock output rate 200 MHz maximum Clock out delay only approximately 8 ns total in 14 steps 16720A only 11 ns maximum in 9 steps 16522A Clock input type 74AVC16244 3 6V max Clock input rate dc to 200 MHz Pattern input type 74AVC16244 3 6V max no connect is logic 0 Clock in to clock out approximately 30 ns Pattern in to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10498A 10472A 2 5 V CLOCK POD Seas A FOR USE WITH AGILENT PATTERN GENERATORS m BND _ WAITO CLK IN m 74AVC16244 A 74AVC16244 CLKout p WAIT ie Agilent 10475A 1 8 V CLOCK POD C A FOR USE WITH AGILENT PATTERN GENERATORS rm BND _ CLK OUT WAIT 2 WAIT 1 WAIT 0 CLK IN CLK OUT NC NC NC NC m 74AVC16244 CLKin CLKout d 74AVC16244 gt WAIT lt CLKin 112 Pattern Gen
36. only Conventional 667 333 MHz Transitional 333 MHz Timing Zoom 2 GHz Conventional 800 400 MHz Transitional 400 MHz Timing Zoom 2 GHz Conventional 800 400 MHz Transitional 400 MHz Conventional 800 MHz Transitional 400 MHz Channels module 68 68 68 34 Maximum channels on a single time base and trigger 340 5 modules 340 5 modules 340 5 modules 170 5 modules Memory depth half full channel 16715A 16717A 4 2M 2 16716A 1M 512K 2 16740A 2 1 M 2 16741A 8 4 M 2 16742A 32 16 M 2 16750A 8 4M 2 16751A 32 16M 2 16752A 64 32M 2 128 64M 5 Trigger resources 16750A Patterns 16 Ranges 15 Edge amp Glitch 2 Timers 2 per module 1 Occurrence Counter 4 Global Counters 2 Pattern 16 Ranges 15 Edge amp Glitch 2 Timers 2 per module 1 Occurrence Counter 2 Global Counter 2 Patterns 16 Ranges 15 Edge amp Glitch 2 Timers 2 per module 1 Occurrence Counter 4 Global Counters 2 At 800 Mb s 4 patterns or 2 ranges 4 flags arm in At 200 Mb s same as 16751A 16752A Other speeds refer to synchronous state analysis Flags 4 Flags 4 Flags 4 page 98 and asynchronous timing analysis page 100 Maximum trigger sequence levels 16 16 16 1 25 Gb s 2 800 Mb s 4 200 or 400 Mb s 16 Maximum trigger sequence speed 16715A 16716A 167 MHz 200 MHz 400 MHz 1 25 Gb s 16717A 333 MHz Trigg
37. parallel word Serial as EEE width up to 32 bits eLa j mja v S Disable Serial Analysis Enable Serial Analysis select the specific state in Input Labely Serial Output Label Parallel the trace where conversion begins x Ser ia Output label Parallel cA serial Word width Z Specify the order in which Start on state 10 g the bits occur in the serial data stream Bit Order MSB Most Significant MSB First LSB First Bit first LSB Least Significant Bit first Advanced Options i R Enable frame processing 5 v D Select input bit gE S j U E Enable clock recovery R Invert input data enable frame processing to extract all instances of a Execute Serial Analysis _ ___Cilose___ defined frame maintain or invert the capture serial data with or with input serial bit stream out an external clock reference Enable clock recovery for an incoming serial bit stream that has no external clock reference RS 232 is an example of a bus with clocking embedded within the serial bit stream Figure 5 16 62 Post Processing and Analysis Tool Sets Serial Analysis To Separate Frame Information from the Data Block i Define Frame Serial Analysis lt 1 gt End after N bits Start Data Block I lt Pass Entire Block gt 1 accept the default start of frame label Start or modify the label to a name of your choosing
38. part number each contains 5 mating connectors and 5 support shrouds E5378A Up to 1 57 mm 0 062 16760 68702 Up to 3 05 mm 0 120 16760 68703 E5379A Up to 1 57 mm 0 062 16760 68702 Up to 3 05 mm 0 120 16760 68703 E5380A Up to 1 57 mm 0 062 5346 68701 Up to 3 18 mm 0 125 5346 68700 29 Data Acquisition and Stimulus Oscilloscope Modules When integrated into the 16700 Series logic analysis systems the oscilloscope modules make powerful measurement and analysis more accessible so you can find the answers to tough debugging problems in less time Oscilloscope controls are easy to find and use Multiple Views of Target Behavior Isolate Problems Quicker Frequently a problem is detected in one measurement domain while the clues to the cause of the problem are found in another That s why the abil ity to view your prototype s behavior from all angles simultaneously from software execution to analog signals is essential for quickly gaining insight into problems HI 2GSa s Oscilloscope C Scope lt C gt File Window Setup Autoscale Options For example using a state analyzer you may observe a failed bus cycle A timing problem caused by a reflection on an incorrectly terminated line may be causing the bus cycle to fail By triggering an oscilloscope from the state analyzer you can quickly identi fy the cause The ability to cross trig ger and time correlate state timing
39. s Behavior A large external display option 001 with multiple resizable windows allows you to see at a glance more of your target system s operation A built in flat panel display in the 16702B fits in environments with limited space Color lets you highlight critical information so you can find it quickly Use one system to examine target operation from different perspec tives Multiple time correlated views of data let you confirm both signal integrity and software execution flow These views are invaluable in solving cross domain problems 10 LA ir saa Ales IOE Eac Ia s T COA CS A a aoe aoe T Morlo T o Press meri LUL jt File Window Edit Options Inwoce Source File Mindow Cor 2 ne TT Te Tea T l gt J mlsl2lv l Displayed File plogic desc leso_Center nource B60_demo_board update_ BS Winclude ATE TE 54 void update_mystee int pannan U je gat raw targets 7 pet Lar get ot Ma arget teer 75 Read the environment conditions rand_conditiona panes Kor rent temp js Set the func_nesded based on the actual environment conditi versus the desired environment cordition 7 sot_cutputet Bfunc_nesded current temp 7 Upstate the hdwrencede value so the external devices can ri to modify the environment Figure 2 5 You can quickly isolate the root cause of system problems by examining target operation across a wide analysis domain from sig
40. to a state listing or timing waveform R Time Overview No File Window Graph Options Ie eee Help I lt Drag gt scal lt Right click gt view options Il The Time Overview display can be used to show the occurance of interrupts In this example there are four interrupts that occur over a short period of time there are many interrupts that occur in a short p riod of time the system may not be able to handle alll of them and may exhibit random crashes Note that you canl use the markers in this window to correlate the interrupts to a state listing or timing waveform Qr TL 16 383 us Display Information Qualified Events 4 Total Acquisitions 1 Total Display 100 Displayed Events 4 Time per Bucket 58 753608 us Figure 5 15 View the frequency of events over time 60 Time Bucket Information Hits d 0 Hits 4t 0 0 Range 277 384840 us thru 336 138447 Elusive system crashes are often caused by too many interrupts occur ring over a short period of time If the software cannot handle all simultane ous service requests the system can exhibit random defects while leaving no clues as to their cause In this situ ation you need a tool that can meas ure and display interrupt loading Post Processing and Analysis Tool Sets Serial Analysis Solve Serial Communication Problems Your system may use serial buses to communicate between ICs and to transfer data to an
41. 0111 00000111 00000111 00000111 01100100 BOSE 01100010 eee 01100000 01011110 COUT RES 00000001 00000001 00000010 00000010 Figure 4 9 To fill the 16720A pattern generator s 8 MVector deep memory 16 MVector in half channel mode with data the stimulus must be in pattern generator binary format Stimulus files in PGB format can be loaded directly from the user interface Data Acquisition and Stimulus Pattern Generation Modules User Macro and Loop Simplify Creation of Stimulus Programs User macros permit you to define a pattern sequence once then insert the macro by name wherever it is needed Passing parameters to the macro will allow you to create a more generic macro For each call to the macro you can specify unique values for the parameters Each macro can have up to 10 parameters Up to 100 different macros can be defined for use in a single stimulus program Loops enable you to repeat a defined block of vectors for a specified number of times The repeat counter can be any value from 1 to 20 000 Loops and macros can be nested except that a macro can not be nested within another macro When nested each invocation of a loop or a macro is counted towards the 1 000 invoca tion limit At compile time loops and macros are expanded in memory to a linear sequence Convenient Data Entry and Editing Feature You can conveniently enter patterns in hex octal binary decimal and two s complement ba
42. 014900 00014904 00014908 Navigate Memory Disassembly Emulator 1 Update 00148B0 ll Data Column Width Page Forward File Navigate 40800044 cro 00000044 00014854 39808222 subi ri2 r13 7DDE 000148B8 7D8CF8AE lbzx r12 r12 r31 000148BC 396D8222 subi rii r13 7DDE 000148C0 7D6BFOAE lbzx rii rii r30 000148C4 7COCS800 cmpw cr r12 r11 000148C8 40800024 bge erd 00000024 000148CC 39808222 subi ri2 r13 7DDE 000148D0 7FACF SAE lbzx r29 r12 ral 000148D4 39608222 subi rii ri3 7DDE 00014808 39408222 subi r10 r13 7DDE 000148DC 7D4AFOAE lbzx ri r10 r30 000148E0 7D4BF9AE stbx PLO rii r31 000148E4 398D8222 subi ri2 ris 7DDE 000148E8 7FACFLAE sthx r29 r12 r30 000148EC 3BDEO001 addi r30 r30 0001 000148F0 4BFFFFBC b 00000044 000148F4 SBFFOOO1 addi r31 r31 0001 000148F8 4BFFFFA8 b 00000058 000148FC 83A1000C lwz r29 OO00C r1 gt 83010010 83E10014 8001001C r30 0010 r1 gt r31 0014 r1 gt LD DU L C1 2 Registers Emulator 1 Groups Options Update PC and Processor Control Help PC 00014664 MSR 00001042 HIDO 00000000 HID1 40000000 CR 80000000 FPSCR 00000000 XER 00000000 LR 00014504 CTR 000160d0 General Purpose 0 15 GPRO 000d8eb4 GPR1 ooo1FFaS GPR2 00024640 GPR3 GPR GPR11 000d8ebb 00000000 00000007 GPR4 00001111 GPRS 00000029 GPR6 0000000b SINR rae ae e OOF 00000003 C9 Run Control Emulator 1 C
43. 0B source correla tion tool set correlates a microproces sor execution trace window with a corresponding high level source code window The source correlation tool set enhances your software develop ment environment by providing mul tiple views of code execution and variable content under severe real time constraints Using the B4620B you can obtain answers to many of your questions concerning software code execution data tracking and software hardware integration Obtain Answers to the Following Questions Software Code Execution e What happened just before the target system crashed e What source code was executed at a specific point in time Your Development Environment Compile Relocatable Object Code l Link in A Absolute Object Code Symbol File Download S Edit Source File e What is the exact time between two user defined system events e What is the execution history leading up to or occurring after an area of interest Data Tracking e What is the exact history of a variable s value over time e Which routine s corrupted the data Software Hardware Integration e What is the root cause of a system failure hardware or software e Are timing anomalies found by the hardware engineer the cause of software problems e Is the software engineer working on the same problem as the hard ware engineer e What portion of the source code correlates to the problem the hardware engineer reported
44. 1 25 Gb s mode only the even numbered channels 0 2 4 etc are acquired 2 The resolution of the hardware used to assign time tags is 4 ns Times of intermediate states are calculated 97 State Timing Modules Specifications and Characteristics Agilent Technologies 16760A Supplemental Specifications and Characteristics continued Synchronous state 1 5 Gb s mode only 1 25 Gb s mode only 800 Mb s mode 400 Mb s mode 200 Mb s mode analysis continued available with E5378A available with E5378A and E5379A probes and E5379A probes Maximum trigger 2 2 4 16 16 sequence levels Maximum trigger 1 5 Gb s 1 25 Gb s 800 MHz 400 MHz 200 MHz sequencer speed Store qualification Default Default Default Default Default and per sequence level Maximum global counter N A N A N A N A 16 777 215 Maximum occurrence N A N A N A N A 16 777 215 counter Maximum pattern range 32 bits 3 32 bits 3 32 bits 3 32 bits 3 32 bits 3 term width Timer value range N A N A N A N A 100 ns to 4397 seconds Timer resolution N A N A N A N A 4ns Timer accuracy N A N A N A N A 10 ns 0 01 of value Timer reset latency N A N A N A N A 65 ns Data in to BNC port out 150 ns 150 ns 150 ns 150 ns 150 ns latency Flag set reset to evaluation N A N A N A N A 110 ns latency 1 In 1 25 Gb s mode only the even numbered channels 0 2 4 etc are acquired 2 The resolution of the hardware used to assign time tags is 4 ns T
45. 1 clock data 34 32 data and 2 clock data 17 16 data and 1 clock data All specifications noted by an asterisk are the performance standards against which the product is tested 1 A support shroud Agilent part number 16760 02302 for boards up to 0 062 thick or 16760 02303 for boards up to 0 120 thick is recommended A kit of 5 shrouds and 5 connectors is available as Agilent part number 16760 68702 for boards up to 0 062 thick or 16760 68703 for boards up to 0 120 thick 2 A kit of 5 Amp Mictor connectors and 5 support shrouds is available Agilent part number E5346 68701 A support shroud is available separately Agilent part number E5346 44701 3 If operated single ended minus inputs grounded the threshold can be adjusted from the user interface 4 Refer to specifications on specific modes of operation for details on how inputs can be used R 215 121 kg ka Sn Cj 20k 0 7pF 1pF 20k 0 6pF a R 30 0 75 V 0 75 V Model Number C R R Figure 6 15 E5382A input equivalent probe load with E5378A E5379A 1 5pF 120 30 5em damped wire see user s guide for load models F5380A 3pF 120 60 with other accessories Figure 6 14 E5378A E5379A E5380A input equivalent probe load 95 State Timing Modules Specifications and Characteristics Agilent Technologies 16760A Supplemental Specifications and Characteristics continued Synchronous Data Sampl
46. 100 MHz State 100 MHz Timing 1 M memory depth y y 16550A 100 MHz State 500 MHz Timing 4 8 K memory depth y y y y 16554A 100 MHz State 250 MHz Timing 512 K 1 M memory depth vV y y 16555A 16555D 110 MHz State 500 MHz Timing 2 4 M memory depth y y y 16556A 16556D 100 MHz State 400 MHz Timing 2 4 M memory depth y y y 16557D 140 MHz State 500 MHz Timing 2 4 M memory depth y V V 16710A 100 MHz State 500 MHz Timing 8 K memory depth y y 16711A 100 MHz State 500 MHz Timing 32 K memory depth y y 16712A 100 MHz State 500 MHz Timing 128 K memory depth y y 16715A 167 MHz State 667 MHz Timing 2 4 M memory depth y 16716A 167 MHz State 667 MHz Timing 2 GHz Timing Zoom y 512 K 1 M memory depth 16717A 333 MHz State 667 MHz Timing 2 GHz Timing Zoom y 2 4 M memory depth 16718A 333 MHz State 667 MHz Timing 2 GHz Timing Zoom y 8 16 M memory depth 16719A 333 MHz State 667 MHz Timing 2 GHz Timing Zoom y 32 64 M memory depth 16740A 200 MHz State 800 MHz Timing 2 GHz Timing Zoom y 2 1 M memory depth 16741A 200 MHz State 800 MHz Timing 2 GHz Timing Zoom y 8 4 M memory depth 16742A 200 MHz State 800 MHz Timing 2 GHz Timing Zoom y 32 16 M memory depth 16750A 400 MHz State 800 MHz Timing 2 GHz Timing Zoom y 4 8 M memory depth 16751A 400 MHz State 800 MHz Timing 2 GHz Timing Zoom y 16 32 M memory depth 16752A 400 MHz State 800 MHz Timing 2 GHz Timing Zoom y 32 64 M memory depth 16760A 1 25 Gb s State 800 MHz Timing 34 chan
47. 16700 Series Logic Analysis System E HH 7 ee Product Overview Debugging today s digital systems is tougher than ever Increased product requirements complex software and innovative hardware technologies make it difficult to meet your time to market goals The Agilent Technologies 16700 Series logic analysis systems provide the simplicity and power you need to conquer complex systems by combining state timing analysis oscilloscopes pattern generators post processing tool sets and emulation in one integrated system oh Agilent Technologies Table of Contents System Overview Modular Design page 3 Features and Benefits page 4 Selecting the Right System page 6 Mainframes Display page 7 Back Panel page 8 System Screens page 9 IntuiLink page 12 Probing Solutions Criteria for Selection page 13 Technologies page 14 Data Acquisition and Stimulus State Timing Modules page 17 Oscilloscope Modules page 30 Pattern Generation Modules page 33 Emulation Modules page 37 Post Processing and Analysis Tool Sets Software Tool Sets page 39 Source Correlation page 41 Data Communications page 45 System Performance Analysis page 54 Serial Analysis page 61 Tool Development Kit page 67 Licensing Information page 73 Time Correlation with Agilent Infiniium Oscilloscopes E5850A Logic Analyzer Oscilloscope Time Correlation Fixture page 74 Technical Specifications and Characteristics Mainframe page 75 Probing Solutions page
48. 16710A 11A 12A 16715A 16716A 16717A 18A 19A 16750A 51A 52A Maximum serial Ciocked data 1 64 Kbits 8 Kbits 32 Kbits 2 Mbits 512 Mbits 2 Mbits 8 Mbits 4 Mbits 16 Mbits trace depth 128 Kbits 32 Mbits 32 Mbits Unclocked data 2 16 32 Kbits 4Kbits 16Kbits 1 Mbit 256 Mbit 1 Mbit 4 Mbits 2 Mbits 8 Mbits 64 Kbits 16 Mbits 16 Mbits Maximum serial Ciocked data 3 1 Gbit s 100 Mbits s 167 Mbits s 167 Mbits s 333 Mbits s 400 Mbits s bus frequency Unclocked data 4 1 Gbit s 125 Mbits s 167 Mbits s 167 Mbits s 167 Mbits s 200 Mbits s Minimum serial Clocked data 20 Mbit s No limit No limit No limit No limit No limit bus frequency Unclocked data 5 765 Mbits s 5 Kbits s 50 bits s 50 bits s 50 bits s 50 bits s Information in Table above calculated according to notes 1 to 5 1 Maximum State Memory Depth 2 Maximum Timing Memory Depth 4 3 Maximum State Frequency 4 Maximum Timing Frequency 4 5 1 Maximum sample period x 20 66 Post Processing and Analysis Tool Sets Tool Development Kit Customize Your Measurements The ability to interpret and display information is vital to your project At times the information you need can be buried in the raw data of your measurement This might be due to one of several reasons e The use of a protocol encoded data or proprietary bus e Events that happen only under certain conditions e The need to analyze system performance e The need to analyze data across a large number o
49. 2 ns worst case 4 ns A FOR USE WITH AGILENT PATTERN GENERATORS Recommended lead set Agilent 10474A m BND _ 100 Q ECL TTL oo gt ZOO 9 OW O ER 10H125 Agilent 10462A 3 State TTL CMOS Data Pod Output type 74ACT11244 with 100 Q series 10H125 on non 3 state channel 7 2 ie Agilent 10462A 3 STATE TTL 3 state enable negative true 100 KQ to GND enabled on no connect GMOS DATA POD Maximum clock 100 MHz A FOR USE WITH AGILENT PATTERN GENERATORS Skew 1 typical lt 4 ns worst case 12 ns mman Recommended lead set Agilent 10474A z ILIIIIL N 3 STATE OUTPUTS SHH KK OW 9 OW O LLL 100 Q 74ACT11244 gt Agilent 10464A ECL Data Pod terminated Output type 10H115 with 330 Q pulldown 47 Q series e Agilent 10464A f ECL DATA POD Maximum clock 300 MHz TERMINATED a a Skew 1 typical lt 1 ns worst case 2 ns FOR USE WITH AGILENT PATTERN GENERATORS Recommended lead set Agilent 10474A m BND oo gt ZZno0ontaa o 420 es 10H115 348 Q 5 2V Pattern Generation Modules Specifications and Characteristics Agilent 10465A ECL Data Pod unterminated Output type 10H115 no termination Maximum clock 300 MHz Skew 1 typical lt 1 ns worst case 2 ns Recommended lead set Agilent 10347A 10H115 ss Agilent 1046
50. 3 1F40FE03 1F40FE03 1F00FE03 1F01FE03 1F00FE03 1F00FE03 1F01FE03 1FOOFEO3 1FOOFEO3 1BO6FEOB 1F40FE0B 1F40FE0B 1F40FE0B The output of the custom tool in this example is shown Notice that there is now data in the DATA column The custom tool was able to reconstruct the code flow after the trace was taken The code was reconstructed by using the branch trace messages and information in the SRecord file creat ed when the code was compiled The tool took the address of the appropri ate states in the trace data and found the corresponding code data in the SRecord file This created a trace that the MPC 555 inverse assembler could operate on properly MPC555 Inverse Assembly 3FA838 3FA9B8 000004 3FA608 3FA608 3FA608 3FA608 3FA608 3FA608 3FA60C 3FA608 3FA608 3FA610 3FA624 3F A624 3F A624 3FAG24 3FAG24 60000000 1F41FE0B Z3FA624 3FA624 3FA624 3FA624 3FA624 3FA640 3FA640 3FA640 3F A640 3FA640 3FA640 3FAG640 3FA640 3FA640 ZEAG4Q Original Trace 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1F40FE0B 1F40FE0B 1F41FE0B 1F40FE0B 1FOOFEOB 1BO6FEOB 1FOOFEOB 1FOOFEOB 1FOOFEOB 1F01FE0B 1FOOFEOB 1FOOFEOB 1F41FE0B 1F40FE0B IF 40FEOR By entering information here users can direct the tool to the correct SRecord file and control how much of the data the tool is to operate on
51. 378A E5379A probes E5378A E5379A probes E5378A E5379A E5382A 400 Mb s 200 Mb s on each channel 1 5 Gb s 1 25 Gb s probes 800 Mb s E5380A probe 600 Mb s Minimum clock interval 667 ps 800 ps E5378A E5379A probes 2 5 ns bns active edge to active edge 1 25 ns E5380A probe 1 67 ns Minimum state clock pulse N A N A E5378A E5379A probes 1 5 ns 1 5 ns width with clock polarity rising or falling 600 ps E5380A probe 800 ps Clock periodicity Clock must be periodic Clock must be periodic Periodic or aperiodic Periodic or aperiodic Periodic or aperiodic Number of clocks 1 1 1 1 1 Clock polarity Both edges Both edges Rising falling or both Rising falling or both Rising falling or both Minimum data pulse width 600 ps 750 ps E5378A E5379A E5382A probes 750 ps E5380A probe 1 5 ns 1 5 ns 1 5 ns Number of channels 1 With time tags Without time tags 16 x number of modules 8 16 x number of modules 8 34 x number of modules 16 34 x number of modules 16 34 x number of modules 16 x number of modules 16 x number of modules 34 x number of modules 34 x number of modules 34 x number of modules Maximum channels ona single time base and trigger 80 5 modules 80 5 modules 170 5 modules 153 5 modules 170 5 modules Maximum memory depth 128M samples 128M sample
52. 38 pin low voltage probe with E5346 68701 All except 16517A built in isolation networks for the logic analyzer Designed for signals 16518A 16760A with peak to peak amplitude as small as 250 mV E5378A 34 channel 100 pin single ended probe for 16760A 16760 68701 16760A only E5379A 17 channel 100 pin differential probe for 16760A 16760 68701 16760A only E5380A 34 channel 38 pin single ended probe for 16760A E5346 68701 16760A only Moderate density probing solutions The Agilent 01650 63203 isolation You may also add the isolation adapter contains the termination networks to the target PC board and networks for the logic analyzer The connect the logic analyzer cable 01650 63203 connects to a 3M 20 pin directly to a 40 pin 3M connector on connector on the target PC board the PC board Refer to Probing Refer to Probing Solutions for Solutions for Agilent Technologies Agilent Technologies Logic Analysis Logic Analysis Systems publication Systems publication number number 5968 4632E for design 5968 4632E for design guidelines guidelines in addition to part num and part numbers for mating bers for mating connectors and Figure 3 9 01650 63203 termination adapter connectors isolation networks Probing Solutions Technologies Using a processor or bus specific analysis probe Figure 3 10 Advantages Limitations Refer to Processor and Bus Support TTT TOT Agilent Technologies Logic Easiest and fastest connection to sup
53. 6A 3 State TTL 3 3 volt Data Pod Output type 74LVT244 with 100 Q series 10H125 on non 3 state channel 7 2 3 state enable negative true 100 KQ to GND enabled on no connect Maximum clock 200 MHz Skew 1 typical lt 3 ns worst case 7 ns Recommended lead set Agilent 10474A 100 Q 74LVT244 1 Typical skew measurements made at pod connector with approximately 10 pF 50 KQ load to GND worst case skew numbers are a calculation of worst case conditions through circuits Both numbers apply to any channel within a single or multiple module system 2 Channel 7 on the 3 state pods has been brought out in parallel as a non 3 state signal By looping this output back into the 3 state enable line the channel can be used as a 3 state enable 106 Agilent 10465A ECL DATA POD UNTERMINATED FOR USE WITH AGILENT PATTERN GENERATORS m BND _ Ponton oo 22 Agilent 10466A 3 STATE TTL 3 3V DATA POD a A FOR USE WITH AGILENT PATTERN GENERATORS m ann _ 3 STATE IN Pattern Generation Modules Specifications and Characteristics Agilent 10469A 5 volt PECL Data Pod Output type 100EL90 5V with 348 ohm pulldown to ground and 42 ohm in series Maximum clock 300 MHz Skew 1 typical lt 500 ps worst case 1 ns Recommended lead set Agilent 10498A 42Q a 100EL90 WAV AY gt 348 Q Ag
54. 83 State Timing Modules page 85 Oscilloscope Modules page 101 Pattern Generation Modules page 104 Trade In Trade Up page 115 Ordering Information page 116 Third Party Solutions page 123 Support Warranty and Related Literature page 124 Sales Offices Information page 125 System Overview Modular Design Modular Design Protects Your Module Choices Long Term Investment Modularity is the key to the Agilent 16700 Series logic analysis systems State Timing User Benefits Agilent offers a wide variety of state timing modules for a range of applications from high speed glitch capture to multi channel bus analysis long term value You purchase only the capability you need now then High Speed Timing expand as your needs evolve All modules are tightly integrated to Precisely characterize setup hold times over a wide channel count Capture data over many clock cycles while retaining the highest multi channel accuracy provide time correlated cross i Oscilloscopes domain measurements Identify signal integrity issues and characterize signals quickly with automatic measurements of rise time voltage pulse width and frequency Pattern Generation Use stimulus to substitute for missing system components or to provide a stimulus response test environment Emulation An emulation module connects to the debug port BDM or JTAG on your target You have full access to processor execution control features o
55. ERES File Navigate Help Read Registers e oem mee oe MPCS509 Emulation reset Figure 4 11 Emulation control interface Post Processing and Analysis Tool Sets Software Tool Sets Once the data is acquired you can rely on the post processing tools to rapidly consolidate data into displays that provide insight into your sys tem s behavior The tool sets described in the following pages are optional post processing software packages for the 16700 Series logic analysis systems Selecting the Right Tool Set Take a look at the tool set descrip tions below to see if they meet your needs If you don t immediately see what you need there is also the option of writing your own analysis application using the tool develop ment kit Best of all you can try out any one of these tool sets with no obligation to buy Application Product Name Model Number Detailed Information Debug your real time code at the source level Source Correlation B4620B Page 40 Correlate a logic analyzer trace with the high level source Tool Set code that produced it Set up the logic analyzer trace by simply pointing and clicking on a line of source code Debug your parallel data communication buses Data Communications B4640B Page 44 Display logic analyzer trace information at a protocol level Tool Set Powerful trigger macros allow triggering on standard or custom protocol fields Data bus width is limited only by the number of availabl
56. HB PL 107 Pattern Generation Modules Specifications and Characteristics Agilent 10476A 3 State 1 8 Volt Data Pod Output type T4AVC16244 3 state enable negative true 38 KQ to GND enabled on no connect Maximum clock 300 MHz Skew 1 typical lt 1 5 ns worst case 2 ns Recommended lead set Agilent 10498A 74AVC16244 gt Agilent 10483A 3 State 3 3 Volt Data Pod Output type 74AVC16244 3 state enable negative true 38 KQ to GND enabled on no connect Maximum clock 300 MHz Skew 1 typical lt 1 5 ns worst case 2 ns Recommended lead set Agilent 10498A T4AVC16244 L Agilent E8141A LVDS Data Pod Output type 65LVDS389 LVDS data lines 10H125 TTL non 3 state channel 7 3 state enable positive true TTL no connect enabled Maximum clock 300 MHz Skew typical lt 1 ns worst case 2 ns Recommended lead set E8142A Recommended lead set Agilent 10498A 3 3 V 1 Typical skew measurements made at pod connector with approximately 10 pF 50 KQ load to GND worst case skew numbers are a calculation of worst case conditions through circuits Both numbers apply to any channel 10 KQ 65LVDS389 ENABLE gt LVDS DATA OUT 3 STATE IN TTL within a single or multiple module system 108 10476A 3 STATE 1 8 V DATA POD in So vez x A FOR USE
57. PI also allows you to write Perl or other scripts to control the logic analyzer Use the sample programs provided to assist you in creating your own custom programs Figure 2 7 Transfer data into Microsoft Excel with just a click of the mouse Probing Solutions Criteria for Selection Why is Probing Important Your debugging tools perform three important tasks probing your target system acquiring data and analyzing data Data acquisition and analysis tools are only as effective as the physical interface to your target system Use the following criteria to see how your probing measures up How to Determine Your Requirements To determine what probing method is best to use you need to take the following into consideration e The number of signals to be probed e The ability to design probing connectors on the target PC board itself e Mechanical probing clearance requirements e Signal loading effects e Ease of attachment e Package type to be probed DIP Dual In line Package PGA Pin Grid Array BGA Ball Grid Array PLCC Plastic Leaded Chip Carrier PQFP Plastic Quad Flat Pack TQFP Thin Quad Flat Pack SOP Small Outline Package TSOP Thin Small Outline Package e Package Pin Pitch distance between pin centers Figure 3 1 A rugged connection lets you focus on debugging your target not your probe Immunity to Noise Impedance EMF noise is everywhere and can corrupt your data Active attenuator probi
58. Pointer to current temperature 140 References None isi gt 142 Returns Nothing CEEEETEErrT rererere 144 void Ed ry Figure 5 4 update_syste 0024 update_syster 0020 updat get_targets seet_tergetsrOOd ro Pe r2 O3E7 jget_targets 000B ath tet 3B q ME_get_torgets TTL Ts 2 Pe 63 FFFOS pen 03E7 00 FFFOS pon E7 00 FFFOS a elf target_tenp IA Error Transfer Size Invalid JA 00004 zget_target2 0010 addis 10 rt 03E7 3D pey 41 a0 pam O3E7 00 pom EF 00 sget_tergets d01d ibz r10 OBE7 ri gt as Pe 41 4c pen 03E7 40 pen E7 ap pen D7 zget_targets 0018 Undefined Dpcode 7C4103E7 zget_targets 001C Also Analyze a function s behavior without viewing calls to subroutines or interrupts by using the analyzer s filtering capabilities to focus on a specific part of the executed software Post Processing and Analysis Tool Sets Source Correlation Product Characteristics Data Sources All state and timing measurement modules supported by the 16700 Series logic analysis systems except the 16517A 518A serve as data sources for the source correlation tool set Microprocessor Support The source correlation tool set sup ports many of the most popular embedded microprocessors Non intrusive analysis probes for the 16700 Series systems provide reli able fast and convenient connections to your target system New microprocessors are constan
59. They can also indicate if the AT2 pin of the MPC 555 processor is in use Figure 5 22 Code reconstruction 3FA624 3F A624 3F A628 3F A624 3F A624 3FA62C 3F A640 3FA640 3FA640 3FA640 3FA640 3FA640 3FA644 3FA640 3FA640 3FA6498 SREC Path Start State End State Parameter Window of Custom Tool r10 r30 0002 cro r10 0000 cro OO3FAG24 r9 r30 0004 cro r9 0000 cro 00ZFAG640 r8 r30 0008 cro r8 0000 CrO OOZEAGSC 00000000 00000000 00000000 00000000 00000000 00000000 73CA0002 00000000 00000000 280A0000 00000000 00000000 41820014 00000000 00000000 00000000 73C90004 00000000 00000000 28090000 00000000 00000000 41820014 00000000 00000000 00000000 73C80008 00000000 00000000 28080000 00000000 00000000 41820014 1F40FE0B 1F40FE0B 1940FF03 1F40FF03 1F40FF03 1FOOFFO3 1DOOFFO3 1FOOFFO3 1FOOFFO3 1DO0FFO3 1FOOFFO3 1FOOFFO3 1900FFOB 1F40FFOB 1F40FFOB 1F40FFOB 1D40FFOB 1F40FFOB 1F40FFOB 1D40F FOB 1F40FFOB 1FOOFFOB 1900FFOB 1FOOFFOB 1FOOFFOB 1FOOFFOB 1D00FFOB 1FOOFFOB 1FOOFFOB 1D40FFOB 1F40FFOB 1F40FFOB 1940F FOB 69 Post Processing and Analysis Tool Sets Tool Development Kit Custom Tool Example Multiplex Data Custom tools can combine several lines of data acquired sequentially seam ma y EL under one label into one line of data Ma 5 Commen i Er However the data to be combined does not have to come from the same label it can come from different
60. WITH AGILENT PATTERN GENERATORS BND _ S SIII E 3 STATE ouTPUTS BII onnowntonN Oo LEE LL LLL 10483A 3 STATE 3 3 V DATA POD FOR USE WITH AGILENT PATTERN GENERATORS m BND TO g a A 5 3 STATEIN 7 c F G T 9 Ies Agilent E8141A LVDS DATA POD are A FOR USE WITH AGILENT PATTERN GENERATORS oao 22 GGrpviririit 3 STATE IN TTL 7 TTL T s Pattern Generation Modules Specifications and Characteristics Data Cable Characteristics Without a Data Pod The Agilent 16720A and 16522A data cables without a data pod provide an ECL terminated 1 KQ to 5 2V differential signal from a type 10E156 or 10E154 driver These are usable when received by a differential receiver preferably with a 100 Q termination across the lines These signals should not be used single ended due to the slow fall time and shifted voltage threshold they are not ECL compatible 16720A 3 25 V 470 Q 10E156 ar Differential 10E154 b x Output 470 Q 3 25 V 16522A 5 2 V 1kQ 10E156 nC Differential 106154 b Output 1kQ 5 2 V 16720A and 16522 CABLE PIN OUTS Gnd Ga 7 5 4 3 2 7 0 Data Cable Pod End 5 2 5 7 6 4 3 2 1 0 Gnd Gnd AAT Wari ward Nc CKN nc CLKOUT NC Clock Cable Pod End 5 2 5 warr2 WAIT WATO NC CLKIN NG CLKOUT NC 109 Pattern Generation Modules Specifications and Characteristics Clock Cable C
61. alid window you can run eye finder for maximum confidence If the clock in your system runs at 100 MHz or slower and the clock transitions are approxi mately centered in the data valid window you may not see any transi tion zones indicated in the eye finder display This is because eye finder only examines a time span of 10 ns 16760A 6 ns centered about the clock Examples of When to Run Eye Finder You should use eye finder in the following situations Probing a new target or probing different signals in the same target e Because eye finder examines the actual signals in the circuit under test you should run it whenever you probe a different bus or a different target Significant change of target temperature e The propagation delays and signal levels in your target system may vary with temperature If for example you place your target system in a controlled tempera ture chamber to evaluate its oper ation over a range of temperatures or to trouble shoot a problem that only occurs at high or low temper atures you should run eye finder after the target system stabilizes at the new ambient temperature 25 Data Acquisition and Stimulus State Timing Modules Features Supported in Agilent State and Timing Analysis Modules Agilent Module Number 16710A 16711A 16715A 16716A 16717A 16760A 16712A 16740A 16741A 16742A 16750A 16751A 16752A Eye finder y N N Visitrigger V Timing Zoo
62. aluated as in range not in range 2 Occurrence counters 4 Flags Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations Trigger actions Goto Trigger and fill memory Goto Trigger and fill memory Store qualification Default Default Maximum occurrence counter 16 777 215 16 777 215 Maximum pattern range width 32 bits 32 bits Data in to trigger out BNC port 150 ns typical 150 ns typical Flag set reset to evaluation 110 ns typical 110 ns typical Timing Mode Timing analysis sample rate half full channel 16715A 16716A 16717A 667 333 MHz 16740A 16741A 16742A 16750A 16751A 16752A 800 400 MHz Channel count 68 per module 68 per module Maximum channels on a single time base and trigger 340 340 Number of independent analyzers 2 can be setup in state or timing modes 2 can be setup in state or timing modes Sample period full channel 3 ns to 1 ms 2 5 ns to 1 ms Sample period half channel 1 5 ns 1 25 ns Minimum data pulse width for data capture Conventional timing 1 75 ns 1 5 ns Transitional timing 3 9 ns 3 8 ns For trigger sequencing 6 1 ns 5 1 ns Sample period accuracy 100 ps 01 of sample period 100 ps 01 of sample period Channel to channel skew lt 1 5ns lt 1 5ns Time interval accuracy sample period channel to channel skew 01 of time inte
63. arkers or the begin ning or end of the trace Markers allow you to quick ly search from frame to frame in the data view the data in the order in which the bits occur in the serial stream in this case LSB 65 Post Processing and Analysis Tool Sets Serial Analysis Product Characteristics Data Sources All state and timing measurement modules supported by the 16700 Series logic analysis systems serve without modification as data sources for the B4601B serial analysis tool set The particular measurement module used determines time resolu tion and accuracy Sample rate chan nel count memory depth and trigger ing are controlled by the user inde pendent of the serial analysis tool Serial Measurement Characteristics Because every trace is non intrusive and every event captured in the trace is time stamped you can correlate activity from your serial bus with other events in the target system The Agilent Technologies 16720A and 16522A pattern generator modules can be used to generate your own serial test data Maximum Parallel Word Width 32 bits Parallel Data Display Types Binary Octal Hex Decimal ASCII Twos Complement Off line Analysis and Post Processing All measurements can be saved using the file out tool Data can be recalled at any time for later analysis using any analysis or display tool Serial measurement data can be exported to your host computer as ASCII files 16517A 18A
64. cale 10 V full scale to 40 V full scale Offset range 2V 10V 50V 250 V Probe attenuation Any ratio from 1 1E 9 to 1 1E 6 Channel to channel isolation with channel sensitivities equal dc 50 MHz 50 MHz 500 MHz 40 dB 30dB Maximum safe input voltage 1MQ e 50Q 250 V dc peak ac lt 10 kHz 5 Vrms Characteristics refer to the input at the BNC connector 102 Oscilloscope Modules Specifications and Characteristics 16534A Characteristics Horizontal Time Time base ranges 0 5 ns div to 5 s div Time base resolution 10 ps Delay range pretrigger posttrigger 32 K x sample period gt 320 ms or 1 6E7 x sample period whichever is greater Time interval measurement accuracy forsampling rates other than maximum for bandwidth limited signals signal rise time gt 1 4 sampling rate on a single card on a single acquisition 0 005 of A T 2E 6 x delay setting 0 15 sample rate Time interval measurement accuracy for 2 3 or 4 Agilent 16533As or 16534As operating on a single time base for measurements made between channels on different cards at maximum sampling rate 0 005 of AT 2E 6 x delay setting 300 ps Trigger Trigger level range See notes 1 5 x full scale from center of screen Trigger modes gt Immediate Edge gt Pattern e Auto condition e Events delay gt Intermo
65. cimal Precedence 2 Hex Immediate Delay 0 Binary Normal Throughput 0 Binary Normal Reliability 0 Binary Normal Cost 0 Binary Normal Protocol view of MBZ 0 Binary T b Total Length 48 Decimal data acquired in Identification 0000 Hex logic analyzer Zero 0 Binary Do not fragment 0 Binary May Fragment 0 Binary Fragment Offset 0 Decimal Time To Live 2 Decimal Protocol 11 Hex User Datagram Protocol Header Checksum c8e5 Hex Sro Addr 15 19 0 3 Dest Addr 96 0 0 2 User Datagram Protocol Source Port 1857 Decimal Destination Port 1857 Decimal Length bytes 28 Decimal Checksum 1374 Hex Packet header data Packet header data Packet header data Packet header data Packet header data Packet header data Packet header data Packet header data Packet header data GOGO O G 6 9 6 6 G GGG Figure 5 10 Time tags for system level correlation of other data buses memory interfaces microprocessors etc 52 Post Processing and Analysis Tool Sets Data Communications Global markers measure time intervals between packets on separate parallel interfaces or timing between the data path and a microprocessor W Data Comm Trace RS Iason Tl Markers Fron 340 000 ns SSU 00096 trom Trigger E 180 000 ns IEEE 802 3 Ethernet V2 Dest Addr 00 01 00 00 00 00 Sre Addr 00 00 00 00 00 00 Length Type 0000 Hex Collapsed View Packet header data of protocol infor e
66. d bits 111111 LSB first Execute Cancel Figure 5 17 63 Post Processing and Analysis Tool Sets Serial Analysis To Acquire a Serial Bit Stream without an External Clock Reference set the sample period of your timing analyzer to take four or more samples for each serial bit accept the Samples default label or enter a new label name specify the embedded bit Se 7 time of the serial bit stream specify the incoming eee signal s data encoding method normal or NRZI Clock Recovery Algorithm 1 For analysis purposes the data is captured in conventional timing mode using the internal timing analyzer clock as the clock refer ence Set the sample period of the timing analyzer to take four or more samples for each serial bit How Clock Recovery Works Embedded bit time Incoming serial bit stream Timing analyzer samples with timing analyzer set Pes each serial bit to take five samples for 0 New Samples serial data Figure 5 19 64 Clock Recovery Serial Analysis lt 1 gt Clock Recovery Sample serial data that does not have a clock For best results set the timing analyzer Sample Period lt 1 4 serial Bit Time Sampled data label Bit Time Sample data every 10 000ns L and re sync on data edges Data Encoding Method Normal O NRZI tedge 0 level 13 Figure 5 18 3 Data edges transitions from 0
67. d Flying Leads Input resistance and Refer to figure 6 14 Refer to figure 6 14 Refer to figure 6 14 Refer to figure 6 15 Capacitance Maximum state data 1 5 Gb s 1 5 Gb s 600 Mb s 1 5 Gb s rate supported Mating connector Agilent part number 1253 3620 1 Agilent part number 1253 3620 1 Amp Mictor 38 2 None required Minimum voltage swing 250 mV p p Vint Vin gt 200 mV p p 300 mV p p 250 mV p p Input dynamic range 3 Vdc to 5 Vdc 3 Vdc to 5 Vdc 3 Vdc to 5 Vdc 3 Vdc to 5 Vdc Threshold accuracy 30 mV 1 of setting 30 mV 1 of setting 3 30 mV 1 of setting 30 mV 1 of setting Threshold range 3 0 V to 5 0 V 3 0 V to 5 0 V 3 0 V to 5 0 V 3 0 V to 5 0 V User supplied threshold 3 0 V to 5 0 V N A N A N A input range User supplied threshold gt 100K ohms N A N A N A input resistance Threshold control options User provided input If operated single ended Adjustable from user Adjustable from user Adjustable from user minus inputs grounded interface interface interface the threshold can be adjusted from the user interface Maximum nondestructive 40 Vdc 40 Vde 40 Vdc 40 Vdc input voltage Maximum input slew rate 5V ns 5 V ns 5 V ns 5 V ns Clock input Differential Differential Single ended Differential Number of inputs 4 34 32 data and 2 clock data 17 16 data and
68. d from peripheral devices Sifting through thousands of serial bits by looking at long vertical columns of captured 1 s and 0 s can be very tedious time consuming and error prone Obtain Answers to the Following Questions e Is the software sending the correct message e Is the communication hardware acting as expected e When multiple messages are involved in what order is data being transmitted e How does the serial bus activity correlate to the target system processor e What is causing the data corrup tion in the target system Product Description The Agilent Technologies B4601B seri al analysis tool set is a general pur pose tool that allows easy viewing and analysis of serial data The tool set enables you to e Convert acquired serial bit streams into readable parallel word formats e Time correlate real time serial traces to system activity e Remove stuffed bits from the data block e Process frame and data portions separately e Process serial data from a signal with or without an external clock reference e Capture and analyze high speed 1 GHz serial buses 61 Post Processing and Analysis Tool Sets Serial Analysis When You Want to Analyze Serial Bit Streams Specify which signal you want to accept the default output convert to parallel format by label Parallel or modify the selecting a specific bit of any label name for easy recognition available label Set the output
69. dard deviation Time Overview Display Number of hits Time bucket width State Overview Display Number of hits State bucket width Display Modes Sort by number of hits Sort alphabetically by event name Sort by time Sort alphabetically by event name Autoscale zoom Accumulate Mode No theoretical limit to the number of acquisitions in accumulate mode Any modification of the display will cause the display to revert back to the last data acquisition Object File Format Compatibility Object file formats are identical for SPA and the source correlation tool sets See page 43 Off Line Analysis and Post Processing All measurements can be saved using the file out tool Data can be recalled at any time for later analysis using any SPA or other tool Performance measurements can be exported to your host computer as histograms or as tabular formatted text files Processor Support Supports any analysis probe listed in Processor and Bus Support for Agilent Technologies Logic Analyzers pub no 5966 4365E Data Sources All measurement modules supported by the 16700 Series logic analysis systems serve without modification as data sources for the B4600B The particular module determines time resolution and accuracy Sample rate channel count memory depth and triggering are controlled by the user independent of the SPA tool set 56 Post Processing and Analysis Tool Sets System Performance Analysis
70. dow Graph Options Sort File Window Graph Options Sort 7 nei EES EEE v di Comments Help The State Interval display shows the amount of time the system is spending in each procedure or function It is useful in determining routines that are candidates for Define ranges Qualify data Include other Qualify data Include other Include other other CADDR Ranges Y HiLLS X7 stropy8 py 11 521 35 2 State Interval save_points ead_conditions do_sort interrupt_sim ascii_old_data old_data update_system set_outputs write_hdwr eetitargets curr_loc main num_checks 3 400 10 1 500 4 1 258 3 1 178 3 590 1 408 1 22440 204 0 1630 152 0 88 0 83 0 40 0 Display Information Qualified States 32 Total Acquisitions 1 Total Display 63 Total Buckets 92 4 6 8 6 8 2 72 6 5 3 3 1 DZ 765 95 12 5 25 37 5 50 62 5 75 87 5 100 Bucket Information Hits 11 521 35 16 Range 01C8A 01CC9 Functid oreo Pass the mouse over a histogram bar and bucket information gives you detailed information for each event Figure 5 13 Determine which functions use the most CPU cycles Post Processing and Analysis System Performance Analysis Time Interval Tool Because time interval measurements often depend upon hardware software interaction the event definition can
71. dule gt Triggers immediately after arming condition is met Triggers on rising or falling edge on channel 1 or channel 2 Triggers on entering or exiting a specified pattern across both channels Self triggers if trigger is not satisfied within approximately 50 ms after arming The trigger can be set to occur on the nth occurrence of an edge or pattern n lt 32000 Arms another measurement module or activates the port out BNC connector when the trigger condition is met Notes Specifications apply only within 10 C of the temperature at which the most recent calibration was performed Specifications apply only after operational accuracy calibration is performed in the frame in which the oscilloscope module is installed Display magnification is used below 56 mV full scale For sensitivities from 16 mV to 56 mV full scale full scale is defined as 56 mV 103 Pattern Generation Modules Specifications and Characteristics 16720A Pattern Generator Characteristics Maximum memory depth 16 MVectors Number of output channels at lt 300 MHz clock 24 Number of output channels at lt 180 MHz clock 48 Number of output channels at lt 200 MHz clock 24 Number of output channels at lt 100 MHz clock 48 Number of different macros 100 Maximum number of lines in a macro 1024 Maximum number of parameters in a macro 10 Maximum number of macro invocations 1000 Maximum loop count in a re
72. e MIL STD 45662A calibration with test data e Add service manual Add programming manual set for a 16500 not required for a 16700 e Convert standard warranty to one year on site warranty e Convert standard warranty to 90 day on site warranty Agilent Model Number 1144A Accessory Description 800 MHz active probe power for two Agilent 1144A active probes is provided by the Agilent 16533A and 16534A requires 01144 61604 power splitter to operate two 1144As 01144 61604 Power splitter Allows operation of two Agilent 1144A active probes from one Agilent 16533A or 16534A 1145A 750 MHz dual active probe power for Agilent 1145A active probes is provided by the Agilent 16533A and 16534A 1141A 200 MHz differential probe requires an Agilent 1142A power supply 1142A Probe power supply 10442A 10 1 500 ohm 1 2pF oscilloscope probe 10443A 20 1 1000 ohm 1 2pF oscilloscope probe Options for Agilent 16720A Pattern Generator Modules Agilent Option 011 Option Description e TTL clock pod and 6 lead set 10460A and 10498A 013 014 015 016 017 018 021 022 023 031 032 033 034 gt 041 042 051 052 0B3 e W17 W30 W50 e 3 state TTL CMOS data pod and 6 lead set 10462A and 10498A e TTL data pod and 6 lead set 10461A and 10498A 2 5 V clock pod and 6 lead set 10472A and 10498A e 2 5 V 3 state data pod and 6 lead set
73. e at the source code level or the assembly level Locate the cause of a problem by stepping backward from the point where you see a problem to its root quickly locate a specific function variable or text string The system maintains a history of previous text searches for quick recall click the source line which you want to trace about on your next acquisition set the data type to Symbols to view file and symbol names or line s to view file name and line number filter out unexe cuted code fetches from the inverse assembled trace to view executed code only using Agilent s advanced inverse assembly filtering for popular processors cause 126 1 ME_get_targets 1 Ramp the temperature targets up and doun 7 T 1 A SCroll or step through the time correlated source code left or inverse assembled trace listing right line 102 U re temperature gt temp_target L x Lemperature lt 2 alse i temperature MAKEBAR ARG1 29 MX_get_targets i 128 HARARE ERENT TESTERS T TO 129 Function read_conditions 131 Description Come up with new temperature values 132 Uses outside_temp and info about current 133 gt state of heat alr etc to create the new values 194 to create the new values 135 gt 136 Parameters 137 x pass_count Number of through the high Level loop a U temperature
74. e channels Optimize your target system s performance System Performance B4600B Page 53 Profile your target system s performance to identify system Analysis Tool Set bottlenecks and to identify areas needing optimization Solve your serial communication problems Serial Analysis B4601B Page 60 Convert serial bit streams to parallel format for easy viewing Tool Set and analysis Supports serial data with or without an external clock reference and protocols that use bit stuffing to maintain clock synchronization Works at speeds up to 1 GHz Customize your trace for greater insight Tool Development B4605B Page 66 Create custom tools using the C programming language Kit Custom tools can analyze captured data and present it in a form that makes sense to you Analysis systems do not require the tool development kit to run generated tools 39 Post Processing and Analysis Tool Sets Software Tool Sets Free Tool Set Evaluation To see which tool sets best fit your needs Agilent Technologies offers a free 21 day trial period that lets you evaluate any tool set as your work schedule permits Once you receive your tool you obtain a password that temporarily enables the tool Figure 5 1 For a free one time 21 day trial of any tool set simply type demo in the password field for the product you want to evaluate 40 Post Processing and Analysis Tool Sets Source Correlation Debug Your Source Code The Agilent B462
75. e value you receive while minimizing your risk and problems We strive to ensure that you get the test and measurement capabilities you paid for and obtain the support you need Our extensive support resources and services can help you choose the right Agilent products for your applications and apply them successfully Every instrument and system we sell has a global warranty Support is available for at least five years beyond the production life of the product Two concepts underlie Agilent s overall support policy Our Promise and Your Advantage Our Promise Our Promise means your Agilent test and measurement equipment will meet its advertised performance and functionality When you are choosing new equipment we will help you with product information including realistic performance specifications and practical recommendations from experienced test engineers When you use Agilent equipment we can verify that it works properly help with product operation and provide basic measurement assistance for the use of specified capabilities at no extra cost upon request Many self help tools are available Your Advantage Your Advantage means that Agilent offers a wide range of additional expert test and measurement services which you can purchase according to your unique technical and business needs Solve problems efficiently and gain a competitive edge by contracting with us for calibration extra cost upgrades out of warranty repairs and on
76. easurement modules to meet your application needs State Timing Logic Analyzers page 17 Oscilloscopes page 29 Pattern Generation page 32 Emulation page 36 Add post processing tool sets for analysis and insight page 38 Source correlation Data communications System performance analysis Serial analysis Tool development kit Support services and assistance page 123 e Training classes Consulting e On line support e Warranty extension Mainframes Display 12 1 LCD display with touch screen on Select a modifiable variable by touching Dedicated hot keys give instant access to the 16702B makes it easy to view a large it then turn the knob to quickly step the most frequently used menus displays number of waveforms or states through values for the variable and on line help Dedicated knobs for horizontal and vertical Touch Off button disables the touch Dedicated knobs for global markers help scaling and scrolling Adjust the display to screen and allows you to point out a track down tough problems A symptom get just the information you need to solve nomalies to a colleague without altering seen in one domain e g timing can be your problem the display settings tied to its cause in another domain e g analog Figure 2 1 The Agilent 16702B quickly tracks down problems in your design while saving precious bench space Mainframes Back Panel Connection f
77. eing combined or separately displayed as prescribed by you e Modify your scope trace using an algorithm developed by you such as an analog filter beat frequency or DSP algorithm Read or Write External Files e Accumulate information from repetitive traces taken by the ana lyzer in a file on your PC or UNIX workstation e Write specific types of states or trace data that have been analyzed to an Excel consumable ASCII file on your PC or UNIX workstation e Use information read from a file on your PC or UNIX workstation to modify the display of an analyzer trace 67 Post Processing and Analysis Tool Sets Tool Development Kit Custom Tool Example Added Text in Hil Listing Automotive SG Trace This example shows how a custom ls lhl m RST Lv T tool can convert data to text to pres ent information in an easy to under stand form The original trace comes from a control unit in an automobile Embedded in the data is information about the engine and transmission When MODE 0 DATA represents EEE GA engine information including RPM 12 gallons of fuel 4 7 P 0 Fuel to air fuel level fuel to air ratio and mani SOT PSTC CASAL EEN GD fold pressure When MODE 1 Overdrive DATA represents transmission infor pra aaa kaner mation including gear position and 0 gallons of fuel temperature 14 Fuel to air 62 PSI manifold Park 375 8 degrees Farer 3060_RPM 10 gallons of fuel 42 Fuel to air 14 PSI mani
78. elate directly to the names used for signals on your target and the functions and variables in your code Use captured logic analysis waveforms to generate simulation test vectors Easily find problems by comparing captured waveforms with simulated waveforms 1 240 channel system consists of five 16720A pattern generator modules with 48 channels per module Full channel mode runs at 180 MVectors s and 8 MVectors depth 300 MVectors s and 16 MVectors depth are offered in half channel mode System Overview Features and Benefits Data Transfer Documentation and Remote Programming Direct Link to Microsoft Excel via Agilent IntuiLink Automatically move your data from the logic analyzer into Microsoft Excel with just a click of the mouse See page 12 Use Microsoft Excel s powerful functions to post process captured trace data to get the insight you need Transfer Data for Offline Analysis Data Export Fast binary compressed binary from the FileOut tool provides highest performance transfer rate ASCII format provides same format as listing display including inverse assembled data Transparent File System Access Documentation Capability Access transfer and archive files Stay synchronized with your source code by mapping shared directories and file systems from your Windows 95 98 NT based PC directly onto the logic analyzer and vice versa Move data files to and from the logic analyzer for archiving or use elsew
79. elections S Acquisition Depth 32M_ specify how data is sampled pacer ais E Clock Setup Mode Master only JE Single location for access to all state acquisition options Convenient color coding helps you identify the signals in the interface with the physical connection to your device under test Figure 4 1 Setting up your logic analyzer has never been this easy Clocking for state measurements can be quickly defined using the clock setup menu 20 Data Acquisition and Stimulus State Timing Modules VisiTrigger Quickly Locates Your Most Elusive Problems VisiTrigger technology is a break through in logic analysis usability It combines increased trigger function ality with a user interface that is easy to understand and use Now with VisiTrigger capturing complex events is as simple as pointing to the trigger function and filling in the blanks Features and Applications VisiTrigger available in the 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A and 16760A state timing modules gt Use graphical views and sentence like structures to help you define a trace event gt Select trigger functions as individual trigger conditions or as building blocks to easily customize a trigger for your specific task gt Set global counters to count events such as the number of times a function executes or the number of accesses to an 1 0 port gt Set clear or evaluate flags by any m
80. endent of the other modules in the logic analysis system Signal IMB Coordinates System Module Activity A Signal IMB intermodule bus instruction acts as a trigger arming event for other logic analysis modules to begin measurements IMB setup and trigger setup of the other logic analysis modules determine the action initiated by Signal IMB Wait for Input Pattern The clock pod also accepts a 3 bit input pattern These inputs are level sensed so that any number of Wait instructions can be inserted into a stimulus program Up to four pattern conditions can be defined from the OR ing of the eight possible 3 bit input patterns A Wait also can be defined to wait for an intermodule bus event This intermodule bus event signal can come from any other module in the logic analysis system Data Acquisition and Stimulus Pattern Generation Modules 00M Patt Gen 300Mvector s Pattern Generator A 00000000 00000000 00000000 10001010 10010000 11100100 10010001 10010011 00101000 11110010 00100101 11110011 INIT END MAIN START 00000111 Map 00000111 00000111 00000111 01100100 K peda 0 04 WO E WM L WAIT UNTIL 01100010 won 01100000 nunun 01011110 ne 00000001 00000001 00000010 00000010 Figure 4 8 Stimulus vectors are defined in the Sequence menu tab In this example vector output halts until the WAIT UNTIL condition is satisfied 00000000 00000000 10010000 11100100 10010011 00101000 00100101 11110011 0000
81. er sequence level branching 4 way arbitrary IF THEN ELSE 4 way arbitary 4 way arbitrary IF THEN ELSE 800 or 1 25 Gb s none branching IF THEN ELSE branching 200 Mb s arbitrary branching IF THEN ELSE branching 400 Mb s dedicated next state branch or reset Number of state clocks qualifiers 4 4 4 1 state clock only Setup hold time 2 5 ns window adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps increments per channel 3 2 5 ns windows adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps increments per channel 3 2 5 ns window adjustable from 1 ns window adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps 2 5 1 5 ns to 1 5 2 5 ns increments per channel 3 10 ps increments per channel Threshold range TTL ECL user definable 6 0 V adjustable in 10 mV increments TTL ECL user definable 6 0 V adjustable in 10 mV increments TTL ECL user definable 6 0 V adjustable in 10 mV increments 3 0 V to 5 0 V adjustable in 10 mV increments All specifications noted by an asterisk are the performance standards against which the product is tested 1 State speeds greater than 167 MHz 16717A or 200 MHz 16750A 16751A 16752A 16760A require a trade off in features Refer to Supplemental Specifications and Characteristics on page 93 for more information 2 Memory depth doubles in half channel timing mode only 3 Minimum setup hold time specified for a
82. eration Modules Specifications and Characteristics 10477A 3 3 volt Clock Pod Clock output type T4AVC16244 Clock output rate 200 MHz maximum Clock out delay only approximately 8 ns total in 14 steps 16720A only 11 ns maximum in 9 steps 16522A Clock input type 74AVC16244 3 6V max 3 3 V CLOCK POD A FOR USE WITH AGILENT PATTERN GENERATORS rm BND BHH BI a oz2 SE UEEES aaa ob223330 LI LIII Ke NG Ke NC Ke NC Ke NC Clock input rate dc to 200 MHz Pattern input type Clock in to clock out 74AVC16244 3 6V max no connect is logic 0 approximately 30 ns Pattern in to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10498A E8140A LVDS Clock Pod Q ock output type 65LVDS179 LVDS and 10H125 TTL m 74AVC16244 CLKout A T4AVC16244 WAIT Agilent Clock output rate 200 MHz maximum LVDS and TTL E8140A LVDS CLOCK POD Clock out delay approximately 8 ns total in 14 steps A FOR USE WITH AGILENT PATTERN GENERATORS Clock input type 65LVDS179 LVDS with 100 ohm EE TTT 1 lIle Clock input rate dc to 150 MHz LVDS ea Pattern input type 10H124 TTL no connect logic 1 559535555 Clock in to clock out approximately 30 ns Pattern in to recognition approximately 15 ns 1 clk p
83. eriod Recommended lead set Agilent 10498A J 10H125 CLK OUT TTL gt 65LBDS179 CLK OUT LVDS p gt lt CLK IN LVDS 65LVDS179 100 Q Be et CLK IN LVDS J 10H124 lt WAIT IN TTL 114 lt CLKin gt Trade In Trade Up Advance to the Latest Technology with Agilent s Trade Up Program Comprehensive Economical Convenient gt Purchase from an extensive gt Upgrade for less gt Simply call your local Agilent list of Agilent test and gt Stretch your test sales office measurement products equipment budget Mention Agilent Promotion 4 65 Trade in a wide variety of Reduce support costs for gt Let us evaluate your savings test equipment for aging equipment opportunities substantial credit How to Upgrade for Less Purchase Trade in Receive Eligible New Agilent Product Similar 1 Agilent Product Agilent s buy back price 2 1 A similar product is considered to be part of the same product family for example oscilloscope for oscilloscope with comparable functionality and application 2 Agilent s buy back price varies based on the model option configuration and age of the trade in product Terms and Conditions s Refurbished Agilent equipment is This offer is void where prohibit ed This offer applies to end user cus tomers only Rental companies and equipment brokers are exclud ed This offer is applicable to the return of fewer than 10 products or 100
84. erminated 10347A 8 channel 50 ohm shielded coaxial probe lead set 10465A ECL data pod unterminated 5090 4356 Grabbers surface mount package of 20 10466A 3 state TTL 3 3V data pod 5959 0288 Grabbers through hole package of 20 10468A 5 volt PECL clock pod 10211A IC probe clip 24 pin dual in line package 10469A 5 volt PECL data pod 10024A IC probe clip 16 pin dual in line package 10470A 3 3 volt LVPECL clock pod E2421A SOIC clip adapter test kit Pomona 5514 10471A 3 3 volt LVPECL data pod E2422A Quad clip adapter test kit Pomona 5515 10472A 2 5 volt clock pod E8140A LVDS clock pod 10473A 3 state 2 5 volt data pod E8141A LVDS data pod 10474A 8 channel probe lead set 12 long E8142A LVDS lead set 10475A 1 8 volt clock pod Product Numbers and Option s for Agilent 16700 Series Post Processing Tool Sets Product or Option Number Description B4600B gt System Performance Analysis SPA Tool Set B4601B e Serial Analysis Tool Set B4605B Tool Development Kit B4620B Source Correlation Tool Set B4640B e Data Communications Tool Set Available for all Tool Sets 0D4 Do not install tool set instructs factory to ship tool set separately from any 16700 Series system on the order 122 Third Party Solutions Our solutions partners offer a wide array of accessory products for the Agilent Technologies logic analysis systems Agilent s solution partners offer complementary products cover ing probing clips specialized ana
85. ernet File System for Windows 95 98 NT based PCs When a tool set is ordered with a 16700 Series mainframe the tool set is shipped installed and ready to run Unless option 0D4 is ordered Tool set proof of receipt is provided by the entitlement certificate See page 121 for ordering information License Policy Tool Set Licensing Information The 16700 Series logic analysis systems tool set software is licensed for single unit use only Licenses are valid for the life of the tool set Software updates do not affect the license Nodelock Mode gt Tool set licenses are shipped or first installed as nodelocked applications Nodelocked means that use of the tool set license is only allowed on the single node 16700 Series analyzer on which it is installed Tool sets ordered with a 16700 Series mainframe will be installed with a permanent password and are ready to run For tool sets purchased as upgrades to existing 16700 Series mainframes you must access the Agilent password redemption web site to obtain a password Your entitlement certificate provides the web URL and alternate contact information Password turnaround is generally the same business day Free Tool Set Evaluation Temporary Demo License License Management Password Backup A single temporary license is available for any tool set type not previously licensed on a node The temporary password for any node on any tool set is demo The temporary license
86. esign automation tools such as SynaptiCAD s WaveFormer and VeriLogger These tools create stimulus using a combination of graphically drawn signals timing parameters that constrain edges clock signals and temporal and Boolean equations for describing complex signal behavior The stimulus also can be created from design simulation waveforms To take advantage of the full depth of the 16720A pattern generator data must be loaded into the module in the Pattern Generator Binary PGB for mat The SynaptiCAD tools allow you to convert VCD files into PGB files directly offering you an integrated solution that saves you time Synchronized Clock Output You can output data synchronized to either an internal or external clock The external clock is input via a clock pod and has no minimum frequency other than a 2 ns minimum high time The internal clock is selectable between 1 MHz and 300 MHz in 1 MHz steps A Clock Out signal is available from the clock pod and can be used as an edge strobe with a variable delay of up to 8 ns Initialize INIT Block for Repetitive Runs When running repetitively the vec tors in the initialize init sequence are output only once while the main sequence is output as a continually repeating sequence This init sequence is very useful when the circuit or subsystem needs to be initialized The repetitive run capabil ity is especially helpful when operat ing the stimulus module indep
87. examines the eye finder No special setup or signals coming from the circuit under additional equipment is required test and automatically adjusts the You only need to run eye finder logic analyzer s setup and hold once when the logic analyzer is set window on each channel Eye finder Up and connected to the target combined with 100 ps adjustment resolution 10 ps on 16760A on Agilent s logic analyzer modules yields the highest confidence in accurate state measurements on high speed buses Hi Sampling Positions C Analyzer lt C gt File Window EyeFinder Results Manual Setup Hold Eye Finder Setup Eye Finder Results Gray shading indicates 4 A 0 ns 1 5 Sampling Position regions where transitions are detected R nn a D aa L x X o LS x o Labell 6 meno x cl Lau x Eo Al M LIK GIGI ry MI al AJIA A A A A al al Blue bars indicate the sampling point selected by eye finder 7 AAAA A Ah AAA 1 le ry Stable Sampling Position Suggested Position Region for next analyzer Run from Eye Finder Figure 4 4 The eye finder display The eye finder display shows Times in the eye finder display are referenced to the incoming clock e Regions of transitions that were transitions The center of the display discovered on all channels labeled 0 ns corre
88. f repetitive measurements Product Description The Agilent Technologies B4605B tool development kit provides a complete environment for creating custom tools that processes data using the powerful search and filtering capabil ities of the logic analysis system Features of the tool kit include e Fast compiled and optimized C code e Push button compiling no make files e A rich library of functions that speeds development e Extensive examples of code e The creation of installable tools e One year of technical support for the B4605B Data is processed quickly by the cus tom tools because they consist of compiled optimized C code A C lan guage programming background is highly recommended A tutorial extensive examples and a rich library of functions are provided that help you easily access analyzer data and the tool s interface The custom tools can be used on any 16700 Series logic analysis system This allows you to purchase just one or two copies of the development kit and develop custom tools to support a large number of analyzers Enhance Data Displays e Color code specific states of your trace e Display some of your trace data in engineering units e Convert the raw trace of a propri etary bus to a transaction level trace of that bus Manipulate Data e Unravel interleaved data into two or more columns of data e Combine the traces of two differ ent analyzers into one trace with each column b
89. f the module through the built in emulation control interface or a third party debugger External Ports Target Control Port Use the target control port to force a reset of your target or activate a target interrupt Port in Port out A BNC connector allows you to trigger or arm external devices or to receive signals that can be used to arm acquisition modules within your logic analyzer ME System 167028 Logic Analysis File Window Select gt 1 Select gt EJE 16719A C2 6 Nultiframe Module 32M Sample 333MHz State 2GHz Timing Zoom 16700 MultiFrame Option Module Select gt 16712A bag E 128K Sample 100MHz State 500MHz Timing A Select gt we B 16534A i C 2GSa s Oscilloscope D poe Select gt 16517A D 4GHz Timing 1GHz State SSS Target Control Port Port In 16720A 300Mvector s Pattern Generator Port Out Ari ks Help Help enables you to access the online user s guide and measurement examples Figure 1 1 The system boot up screen shows you what modules are configured into your logic analysis system System Overview Features and Benefits System Capability NEW Touch Screen Interface The Agilent 16702B mainframe supports a large 12 1 inch LCD touch screen and redesigned front panel controls for an easy to operate self contained unit requiring minimal bench space and offering simple portability
90. fications POWERGND 2 1 5V SIGNALGND 4 3 CLK SIGNALGND 6 5 CLK2 SIGNALGND 8 7 D15 SIGNAL GND 10 9 D14 SIGNAL GND 12 11 D13 SIGNAL GND 14 13 D12 SIGNAL GND 16 15 D11 SIGNAL GND 18 17 D10 SIGNAL GND 20 19 D9 SIGNAL GND 22 21 D8 SIGNAL GND 24 23 D7 SIGNAL GND 26 25 D6 SIGNAL GND 28 27 D5 SIGNAL GND 30 29 D4 SIGNAL GND 32 31 D3 SIGNAL GND 34 33 D2 SIGNAL GND 36 35 D1 SIGNAL GND 38 37 D0 POWER GND 40 39 BV 1 5V 3 CLK1 5V 1 9 2 POWER GND 5 D14 CLK1 3 oo 4 SIGNAL GND 7 D12 CLK2 5 oo 6 SIGNAL GND 9 D10 D15 7 oo 8 SIGNAL GND 11 D8 D14 9 oo 10 SIGNAL GND 13 D6 D13 11 oo 12 SIGNAL GND 15 D4 D12 13 oo 14 SIGNAL GND 17 D2 D11 15 oo 16 SIGNAL GND 19 DO D10 17 oo 18 SIGNAL GND D9 19 oo 20 SIGNAL GND DR 21 oo 22 SIGNAL GND D7 23 oo 24 SIGNAL GND D6 25 oo 26 SIGNAL GND D5 27 oo 28 SIGNAL GND D4 29 oo 30 SIGNAL GND D3 31 oo 32 SIGNAL GND D2 33 oo 34 SIGNAL GND D1 35 oo 36 SIGNAL GND DO 37 oo 38 SIGNAL GND 5V 39 oo 40 POWER GND Figure 6 7 Pinout for state timing module pod cable and 100 KQ isolation adapter Agilent 01650 63203 5V 1 OO 2 CLK2 CLK1 3 O O 4 D15 D14 5 OO 6 D13 D12 7 OO 8 D11 D10 9 G 10 D9 D8 11 O O 12 D7 D6 13 O O 14 D5 D4 15 O O 16 D3 D2 17 O O 18 D1 DO 19 OO 20 GND Figure 6 8 Pinout for 20 pin connector Agilent 1251 8106 Probing Solutions Specificati
91. fold Overdrive 294 8 degrees Farer 660 RPM 1 gallons of fuel 14 Fuel to air 50 PSI manifold Overdrive 12 000 ns 377 6 degrees Farer 2940 RPM 16 000 ns Se E W Listing lt 2 gt SS S File Window Edit Options Invasm Source Help Ie oO eral Output of Custom Tool 32 000 28 000 24 000 20 000 16 000 12 000 8 000 4 000 Q 4 000 8 000 12 000 16 000 20 000 24 000 28 000 32 000 Se Hi Parameters Tool Development Kit lt 1 gt Temperature Units F or C 1 0 1 0 1 0 1 0 1 Q 1 0 1 0 2 0 1 0 OnNOOARW MY RIO Original Trace This custom tool allows the user to specify Fahrenheit or Centigrade for the engine temperature data Figure 5 21 Parameter Interface of Custom Tool 68 Post Processing and Analysis Tool Sets Tool Development Kit Custom Tool Example Microprocessor Code Reconstruction The original trace came from the bus of a MPC 555 processor As you can see no data was placed on the bus at the time of the trace because cache memory was turned on Normally it would not be possible to inverse assemble this trace 3FA838 3FA9B8 3FA608 3FA608 3FA608 3FA608 3FA608 3FA608 3FA608 3FA608 3F A608 3F A608 3F A624 3F A624 3F A624 3F A624 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1F40FE0B 1F40FE0B 1B45FE0
92. format is also supported For the most current information about supported compiler file for mats and processor support please contact your Agilent Technologies sales representative Source File Access The source correlation tool set must be able to access source files to pro vide source line referencing Source files can reside in multiple directories on the hard drive of your workstation PC or on the 16700 Series mainframe s internal hard disk You can access the files via NFS mounted disks or CIFS mounted disks To display the source file the tool set first looks for the source path name in the object file follows the path to access the source file and if not found looks for the source file in alternate user defined directories The 16700 Series logic analysis systems automatically place the following in the directory search path e NFS mounted directories e Directory paths specified in loaded symbol files e Directory paths specified in loaded source files Source Correlation Functionality e Source code and inverse assembled trace listing are time correlated e User can alternate between source viewer and browsing of other source files e Trace specification can be set up from the source viewer or file browser e For multiple processor systems each trace window can be time correlated to a source viewer Post Processing and Analysis Tool Sets Data Communications Monitor Packet Information on
93. fy Delete packets UK Cancel Edit or create a protocol using a text file 7 arpas l Start with stan dard protocol Tsau see Passe ee ees eS ee a a a definition and add custom fields with text file Name IEEE 602 3 Ethernet Y2 PhysicalLayer 1 Header Insert protocol layer name DA Dest Addr 46 Hardwarefddress Data SA Src Addr 48 HardwareAddress Data PT Length Type 16 Hex ProtocolIndicator Define protocol fields number of bits and format for trigger and display Internet Protocol h0800 ARP Request h0306 ARP Response h0935 AppleTalk Datagram Protocol h 09B Novell IPx h8137 IPS h2007 Define any user symbols to make triggering and dis play easier to use Figure 5 6 48 Post Processing and Analysis Tool Sets Data Communications New packet trigger macros Choose from a list of buses Trigger on simple IP address instead of setting up trig ger sequencer Specify what action to perform once a packet is found Specify protocol layer to trigger on Use any defined protocol fields as a trigger such as source address destination address etc Trigger Trigger Functions Default Storing Save Recall General State Telecom State Trigger function libraries Find Packet Advanced If then Advanced 2 way branch Advanced 3 way branch Advanced 4 way b
94. haracteristics Remote Programming Interface RPI RPI Overview Typical Applications Manufacturing Test Data Acquisition for Offline Analysis System Verification and Characterization Pass Fail Analysis Stimulus Response Tests Remote Programming 1 Set up the logic analyzer and save the test configuration Steps 2 Create a program that remotely Loads a test configuration Starts the acquisition process Checks measurement status verifies completion Acts on the results of the data acquisition gt Saves configuration and captured data Exports data Executes a compare Modifies the trigger setup or trigger value for the next acquisition Accesses the oscilloscope s automatic measurements Physical Connection Remote programming is done via the LAN connection Requirements 16700B Series RPI is standard with system software version A 02 00 00 or Analysis Systems higher PC Programming is done via Microsoft ActiveX COM automation Pentium family PC with one of the following e Windows 95 Windows 98 gt Windows NT 4 0 with Service Pack 3 or higher Visual Basic or Visual C Version 5 0 or higher UNIX Programming is done via TCP IP socket based ASCII commands 78 Mainframe Specifications and Characteristics Remote Programming Interface RPI continued Command Set Summary Commands available on both UNIX and PC System System Configuration Query Load Save Configuration and Data Start St
95. haracteristics Without a Clock Pod The Agilent 16720A and 16522A clock cables without a clock pod provide an ECL terminated 1 KQ to 5 2V differential signal from a type 10E164 driver These are usable when received by a differential receiver preferably with a 100 Q termination across the lines These signals should not be used single ended due to the slow fall time and shifted voltage threshold they are not ECL compatible 100 Q Clock In 11 13 15 Wait 1 2 3 IN 12 14 16 3 25 V 215 Q Clock Out 215 Q 3 25 V 110 Pattern Generation Modules Specifications and Characteristics Clock Pod Characteristics 10460A TTL Clock Pod Clock output type 10H125 with 47 Q series true amp inverted Clock output rate 100 MHz maximum Clock out delay only approximately 8 ns total in 14 steps 16720A only 11 ns maximum in 9 steps 16522A Clock input type TTL 10H124 Clock input rate dc to 100 MHz ie Agilent 10460A TTL CLOCK POD is a A FOR USE WITH AGILENT PATTERN GENERATORS r BND Pattern input type TTL 10H124 no connect is logic 1 Clock in to clock out approximately 30 ns Pattern in to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10474A 10463A ECL Clock Pod Clock output type 10H116 differential unterminated and differ ential with 330 Q to 5
96. he frequency of First step of analysis or that are candidates for routine s execution times events over time optimization process to duration measurements and verifies signal timing identify which events occur using the time interval tool specifications most frequently Applications Cache hit and miss Measures setup and hold Isolates defects such as analysis Bus headroom analysis can be made by examining ratio of active to idle status states Examines workload of each processor ina multi processor system to determine if system is balanced times the jitter between two edges or the variation between two bus states invalid pointers filtering Distribution of signal voltages can tell whether a digital signal is spending too much time in the switching region Evaluates the linearity of the output of a D A converter Displays Include Ability to be viewed simultaneously Filtering capabilities for removing portions of a trace that are not applicable to the analysis Maximum Number of Events No theoretical limit Up to 10 000 events tested with a standard configuration Number of events limited by size of the window e g pixels on the screen 55 Post Processing and Analysis Tool Sets System Performance Analysis Product Characteristics continued Supplemental Information SPA Tools State Interval Display Number of hits Time Interval Display Minimum time Maximum time Average time Stan
97. he histogram are selected by manually positioning a pair of cursors The cursors indicate the voltage level and the beginning and end times of the histogram Polygon A 4 point or 6 point polygon can be defined manually 28 Eye Scan lt 1 gt File Window L gt gt i a ms lt E ratuer lt a gt 92 18 complete ETA 1 min 59 sec Help Scale Display Measurements Info Comments t div 290 ps div t Offset Os V div 150 mV div Offset 90 V Auto Scale Clear Data Set Scan Channel Label lt All Labels gt aj K lt All 16 channels PEE Slope The slope tool indicates DV DT between two manually positions cursors Eye scan allows the user to set the following variables The number of clock cycles to be evaluated at each time and voltage region The display mode e Color graded e Intensity shaded e Solid color e Aspect ratio of the display e Time division s Time offset e Volts division e Voltage offset s Time resolution of measurement e Voltage resolution of measurement Results can be viewed for each individual channel A composite display of multiple channels and or multiple labels is also available Individual channels can be highlight ed in the composite view Eye scan data can be stored and recalled for later comparison or analysis Data Acquisition and Stimulus State Timing Modules Probing solutions to ma
98. here Save graphics in standard TIFF PCX and EPS formats Print screen shots and trace listings to a local or networked printer Save your lab notes and trace data in the same file by entering relevant information in the Comments tab of the display Remote Programming with Microsoft s COM Using Microsoft Visual Basic or Visual C Perform pass fail analysis stimulus response tests data acquisition for offline analysis and system verification and characterization tests Powerful yet efficient command set focuses on your programming tasks resulting in a shorter learning curve while maintaining necessary functionality System Software Features Post Processing Analysis Tools Rapidly consolidate large amounts of data into displays that provide insight into your system s behavior See page 38 Setup Assistant Tabbed Interface Multi Windowed View of Target System Activity Global Markers Quickly configure the logic analysis system for your target microprocessor See page 9 Groups like tasks together so you can quickly find and complete the task you want to perform gt Spend your time solving problems not setting up a measurement View your cross domain measurements time corrected on the same screen See page 10 Debug faster because you can view system activity at a glance Track a symptom in one domain e g timing to its cause in another domain e g analog Resizable Windows and Data View
99. hold time on individual channels after running eye finder 1 25 ns window 1 25 ns window Minimum state clock pulse width 1 2 ns 1 2 ns Time tag resolution 2 4ns 4ns Maximum time count between states 17 seconds 17 seconds Maximum state tag count 232 232 between states 2 Number of state clocks qualifiers 4 4 Maximum memory depth 16716A 512K 16740A 1M 16750A 4M 16715A 16717A 2M 16741A 4M 16751A 16M 16742A 16M 16752A 32M Maximum trigger sequence speed 167 MHz 200 MHz Maximum trigger sequence levels 16 16 All specifications noted by an asterisk are the performance standards against which the product is tested 1 Tested at input signal VH 0 9V VL 1 7V Slew rate 1V ns and threshold 1 3V 2 Time or state tags halve the acquisition memory when there are no unassigned pods 90 State Timing Modules Specifications and Characteristics Agilent Technologies 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Supplemental Specifications and Characteristics continued State Mode Trigger sequence level branching 16715A 16716A 16717A 167 Mb s State Mode 4 way arbitrary IF THEN ELSE branching 16740A 16741A 16742A 16750A 16751A 16752A 200 Mb s State Mode 4 way arbitrary IF THEN ELSE branching Trigger position Start center end or user defined Start center end or user defined Trigger resources 16 Patterns evalua
100. hrough a series of states 180 300 MHz Number of data channels full half channel 48 24 Channels Memory depth full half channels 8 16 MVectors Maximum vector width 5 module system full half channel 240 120 Bits Logic levels supported TTL 3 state TTL 3 3V 1 8V 3 state CMOS ECL 5V PECL 3 3V LVPECL LVDS Maximum binary vector set size 16 MVectors 24 channels Editable ASCII vector set size 1 MVectors 33 Data Acquisition and Stimulus Pattern Generation Modules Vectors Up To 240 Bits Wide Vectors are defined as a row of labeled data values with each data value from one to 32 bits wide Each vector is output on the rising edge of the clock Up to five 48 channel 16720A mod ules can be interconnected within a 16700 Series mainframe or expansion frame This configuration supports vectors of any width up to 240 bits with excellent channel to channel skew characteristics see specific data pod characteristics in Pattern Generation Modules Specifications starting on page 105 The modules operate as one time base with one master clock pod Multiple modules also can be configured to operate independently with individual clocks controlling each module 34 Depth Up to 16 MVectors With the 16720A pattern generator you can load and run up to 16 MVectors of stimulus Depth on this scale is most useful when cou pled with powerful stimulus generated by electronic d
101. ic analyzers probing into your target system 27 Data Acquisition and Stimulus State Timing Modules Eye scan In the eye scan mode the Agilent 16760A scans all incoming signals for activity in a time range centered on the clock and over the entire voltage range of the signal The results are displayed in a graph similar to an eye diagram as seen on an oscilloscope As timing and voltage margins continue to shrink confidence in signal integrity becomes an increasingly vital requirement of the design verification process Eye scan lets you acquire comprehensive signal integrity information on all the buses in your design under a wide variety of operating conditions in minimum time Qualified eye scan In the qualified eye scan mode a single qualifier input defines what clock cycles are to be acquired and what cycles are to be ignored in the eye scan acquisition For example you may wish to examine the eye diagram for read cycles only ignoring write cycles Cursors Two manually positioned cursors are available The readout indicates the time and voltage coordinates of each cursor Eye limit The eye limit tool is a single point cursor that can be positioned manu ally The readout indicates the inner eye limits detected at the time and voltage coordinates of the cursor Histogram The histogram tool indicates the rela tive number of transitions along a selected line The time range and voltage levels of t
102. ider a logic analyzer with the trigger resources you need to quickly set up your measurements After memory depth triggering is the most important aspect of a logic analyzer to consider On the one hand powerful triggering resources and algorithms will allow you to focus on potential problem sources without using up valuable memory On the other hand to be useful the trigger must be easy to set up Other Measurements In addition to the measurements made with an analysis probe consider whether you need to monitor other signals Be sure to allow enough channels to make those measurements For state measurements the state speed of the analyzer must be at least as high as the clock speed of your circuit You may want to test the margin in your circuit by operating it at higher than the nominal clock speed to determine if the analyzer has sufficient clock speed For timing measurements the timing analyzer rate should be from 2 10X the clock speed of your target Data Acquisition and Stimulus State Timing Modules Key Features of Agilent s State Timing Modules e Memory depth up to 128M samples at a price to meet your budget e State analysis up to 1 5 Gb s e Timing analysis up to 2 GHz e VisiTrigger combines powerful functionality with an intuitive user interface e Timing Zoom 2 GHz timing on all channels Eye finder for automatic setup and hold on all channels Multichannel Eye measurements Eye scan allows you to
103. ifferential 17 channel probe 012 add one E5380A Mictor compatible probe 013 add one E5382A single ended flying lead probe set 0B3 Add service manual available April 2001 ABJ MIL STD 45662A calibration with test data available April 2001 W17 Convert standard warranty to one year on site warranty 119 Ordering Information Agilent Wedge Probe Adapters IC Leg Spacing Number of Quantity of Probe Model Signals Probes Shipped Number 0 5mm 3 1 E2613A 0 5mm 3 2 E2613B 0 5mm 8 1 E2614A 0 5mm 16 1 E2643A 0 65 mm 3 1 E2615A 0 65 mm 3 2 E2615B 0 65 mm 8 1 E2616A 0 65 mm 16 1 E26144A Agilent Elastomeric Probing Solutions Package Type IC Leg Spacing Probe Model Number 240 pin POFP COFP 0 5mm E5363A Probe E5371A 1 4 flexible cab 208 pin POFP COFP 0 5mm E5374A Probe E5371A 1 4 flexible cab 176 pin POFP 0 5mm E5348A Probe E5349A 1 4 flexible cab 160 pin QFP 0 5mm E5377A Probe E5349A 1 4 flexible cab 160 pin POFP COFP 0 65 mm E5373A Probe E5349A 1 4 flexible cab 144 pin POFP COFP 0 65 mm E5361A Probe E5340A 1 4 flexible cab 144 pin TOFP 0 65 mm E5336A Probe E5340A 1 4 flexible cab 120 Ordering Information Options and Accessories for Agilent 16534A Oscilloscope Modules Agilent Option 001 e ABJ 0B0 e 1BP 0B3 OBF e W17 Option Description Add one Agilent 1145A dual active 750 MHz probe Japanese user s reference e Delete manuals
104. ilent 10471A 3 3 volt LVPECL Data Pod Output type 100LVEL90 3 3V with 215 ohm pulldown to ground and 42 ohm in series Maximum clock 300 MHz Skew 1 typical lt 500 ps worst case 1 ns Recommended lead set Agilent 10498A 42Q 100LVEL90 AVA gt 215 Q Agilent 10473A 3 State 2 5 Volt Data Pod Output type T4AVC16244 3 state enable negative true 38 KQ to GND enabled on no connect Maximum clock 300 MHz Skew 1 typical lt 1 5 ns worst case 2 ns Recommended lead set Agilent 10498A 7T4AVC16244 gt 1 Typical skew measurements made at pod connector with approximately 10 pF 50 KQ load to GND worst case skew numbers are a calculation of worst case conditions through circuits Both numbers apply to any channel within a single or multiple module system 2 Channel 7 on the 3 state pods has been brought out in parallel as a non 3 state signal By looping this output back into the 3 state enable line the channel can be used as a 3 state enable L Agilent 10469A PECL DATA POD A FOR USE WITH AGILENT PATTERN GENERATORS msn DIR 555585555 ee Agilent 10471A LVPECL DATA POD A FOR USE WITH AGILENT PATTERN GENERATORS m ano _ 10473A 3 STATE 2 5 V DATA POD FOR USE WITH AGILENT PATTERN GENERATORS m BND L o z ii E 3 STATE ouTPuTS BII obrrnowntona o LETT
105. imes of intermediate states are calculated 3 Maximum label width is 32 bits Wider patterns can be created by Anding multiple labels together Asynchronous Timing Analysis Maximum timing analysis sample rate Conventional Timing Analysis 800 MHz Transitional Timing Analysis 400 MHz Number of channels 34 x number of modules Sampling rates lt 400 MHz 34 x number of modules Sampling rates 400 MHz 34 x number of modules 17 1 Maximum channels on a single time base and trigger 170 5 modules 170 5 modules Sample period 1 25 ns 2 5 ns to 1 ms 1 Memory Depth 64 M Samples 32 M Samples 1 1 With all pods assigned in transitional store qualified timing minimum sample period is 5 ns and maximum memory depth is 16 M samples 98 State Timing Modules Specifications and Characteristics Agilent Technologies 16760A Supplemental Specifications and Characteristics continued Asynchronous Timing Analysis continued Sample period accuracy Conventional Timing Analysis 250 ps 0 01 of sample period Transitional Timing Analysis 250 ps 0 01 of sample period Channel to channel skew lt 1 5ns lt 1 5ns Time interval accuracy sample period channel to channel skew 0 01 of time interval sample period channel to channel skew 0 01 of time interval Minimum data pulse width 1 5 ns for data cap
106. ine position resolution provides unparalleled measurement accuracy at high frequencies Timing Resolution Timing analysis uses the logic analyzer s internal clock to determine when to sample Since timing analysis samples asynchronously to the system under test you should consider what accuracy you will need to verify your system Accuracy is made up of two elements sample speed and channel to channel skew Remember to evaluate both of these elements and be careful of logic analyzers that have a fast sample speed with a large channel to channel skew Transitional Timing If your system has bursts of activity followed by times with little activity you can use transitional timing to capture a longer trace In transitional timing the analyzer samples data at regular intervals but only stores the data when there is a transition on one of the signals Data Acquisition and Stimulus State Timing Modules Considerations for Choosing Modules continued Channel Count Determine the number of signals you want to analyze on your system under test You will need this number of channels in your logic analyzer Even if you have enough channels to view all the signals in your system today you should consider logic analysis systems that allow you to add more channels for your future application needs Memory Depth gt Complex architectures and bus protocols make your debugging job increasingly challenging Split transactions multiple ou
107. ing tWidth Figure 6 17 Data Sampling Individual Height Data E Data Channel vie ae tSetup tHold vThreshold Sampling _t 0vV Position tSample User Adjustable Clock Channel Note 1 Specifications for Each Input Parameter Minimum Description Notes 800 1250 1500 Mb s modes 200 400 Mb s modes Data tWidth 500 ps 1 25 ns Eye width in system under test 2 toClock tSetup 250 ps 625 ps Data setup time required before tSample tHold 250 ps 625 ps Data hold time required after tSample All vHeight 1 100mV 100mV E5379A 100 pin differential probe 3 Inputs 250 mV 250 mV E5378A 100 pin single ended probe 4 E5382A single ended flying lead probe set 300mV 300mV E5380A 38 pin single ended probe User Adjustable Settings for Each Input Parameter Adjustment Range 1500 Mb s mode 1250 Mb s mode 800 Mb s mode 400 Mb s mode 200 Mb s mode Data Adjustment Resolution 10 ps 10 ps 10 ps 100 ps 100 ps to Clock tSample 5 Oto 4ns 2 5 to 2 5 ns 2 5 to 2 5 ns 3 2 to 3 2 ns 3 5 to 3 ns All vThreshold 6 10 mV resolution 10 mV resolution 10 mV resolution 10 mV resolution 10 mV resolution Inputs 3to 5 V 3to 5 V 3to 5V 3to 5 V 3to 5 V All specifications noted by an asterisk in the table are the performance standards against which the product is tested 1 The analyzer can be configured to sample on the rising edge the falling edge or both edges of the clock If both edges are used with a single ended cl
108. ion 110 ns typical 110 ns typical All specifications noted by an asterisk are the performance standards against which the product is tested 91 State Timing Modules Specifications and Characteristics Agilent Technologies 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Supplemental Specifications and Characteristics continued State Mode Maximum state acquisition rate on each channel 16715A 16716A 16717A 167 Mb s State Mode 333 Mb s 16750A 16751A 16752A 400 Mb s State Mode 400 Mb s Channel count Number of modules x 68 34 Number of modules x 68 34 Maximum channels on a single time base and trigger 306 306 Number of independent analyzers 1 when 333 MHz state mode is selected the second analyzer is turned off 1 when 400 MHz state mode is selected the second analyzer is turned off Minimum master to master clock time 1 3 003 ns 2 5 ns Setup hold time 1 single clock single edge 2 5 ns window adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps increments per channel 2 5 ns window adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps increments per channel Setup hold time 1 single clock multi edge 3 0 ns window adjustable from 5 0 2 0 ns to 1 5 4 5 ns in 100 ps increments per channel 3 0 ns window adjustable from 5 0 2 0 ns to 1 5 4 5 ns in 100 ps increments per channel Setup hold time on i
109. ions Protocol Filters and Viewing Preferences W invasm Filter Data Comm Trace Network Protocol Decoder Filter ates Frame 10 Slot A Analyzer lt A gt Show States Of Type R Idle non packet states B Packet header data states B Packet data states Filter captured data to only view key data for measurement HM End of packet states Reset B Invasm Preferences Data Comm Trace Choose to view payload data with header information Select which protocol layers and fields to view in trace E Network Protocol Decoder Preferences Frame 10 Slot A Analyzer lt A gt Decode Settings Show All Fields For Max length of packet 300 bytes M IEEE 802 3 Ethernet 2 O Use short field names mnemonics O High performance mode Decode Bus Figure 5 9 Internet Protocol Internet Cntrl Msg Protocol Transmission Control Protocol User Datagram Protocol ARP Request ARP Response IPS AppleTalk Datagram Novell IPX 51 Post Processing and Analysis Tool Sets Data Communications E Data Comm Trace SBR File Window Edit Options Invasm Source Help Vee ee Label OK E uhen Present Advanced searching Network Protocol Decoder IEEE 802 3 Ethernet V2 32 940 us Di f Dest Addr 01 00 5e 00 00 02 isplay 0 Sre Addr 00 10 21 47 78 0d protocol levels Length Type 0800 Hex Internet Protocol Internet Protocol Version 04 Octal Header Length 5 De
110. k prob lems across multiple measurement domains EE ey Help Pee VEL T Memories Measure Period 15 Vtop 3 0071 V Vmax Frequency 66 Vbase 96 386 mY Vmin Risetime L Vamp 2 9107 V Vpp Falltime 1 5 Vavet 1 4467 V Vderms t Width d Preshoot 3 501 Tmax Width 7 Overshoot 11 973 Tmin Automatic measurements 7 save time in characterizing signal parameters 2 00 GSa s Scale 5 00 ns div Delay 25 000 ns Channel C1 a Figure 4 6 Automatic measurements and markers let you make faster analysis 31 Data Acquisition and Stimulus Oscilloscope Modules More Channels When You Need Them You can combine up to four 16534A oscilloscope modules to provide up to eight channels on a single time base When you operate in this mode you can use the master module for triggering External trigger input and output are used to connect up to four oscilloscope modules providing up to eight channels on a single time base Calibrator output used for operational accuracy calibration Probe power output provides power for 1145A dual active probe or two 1141A active probes Channel 1 input Channel 2 input ECL EXT _OUT N TRIG e AC DCCAL PROBE POWER ZX CHANTS 2 1MW 7pF 250V MAX OR 50W 5Vrms MAX 16534A 2 GSa s OSCILLOSCOPE US35021924 16534A MADE INTHE USA __ il IN MH H
111. le qualifier input defines what clock cycles are to be acquired and what cycles are to be ignored in eye scan acquisition Qualified eye scan is supported in the 16760A in 800 Mb s eye scan mode only Qualified eye scan is only available for double edged clock double data rate 100 The following channels are not available for qualified eye scan measurements Master module Pod 1 Master module Pod 2 Bit 0 Bit 14 Bit 1 Bit 15 Bit 2 K clock the qualifier input itself All channels on all boards other than the master board are available for qualified eye scans The analyzer samples the qualifica tion signal at the beginning of each clock cycle i e at the first of each pair of data transfers The analyzer can be configured to treat either the rising edge or the falling edge of the clock as the first edge of each clock cycle The qualifier should remain stable for the entire duration of each burst The qualifier must be pipelined delayed by one clock cycle before transmittal to the analyzer Oscilloscope Modules Specifications and Characteristics 16534A Specifications Bandwidth dc to 500 MHz dc offset accuracy 1 of offset 2 of full scale dc voltage measurement accuracy 1 5 of full scale offset accuracy Time interval measurement accuracy at maximum sampling rate on a single scope card on a single acquisition 0 005 of D T 2E 6 x delay setting 100 ps
112. lity that makes complex device substitution a reality Supports TTL CMOS 3 3V 1 8V LVDS 3 state ECL PECL and LVPECL High Speed Bus Measurements Made Simple with Eye Finder Technology Agilent s eye finder technology automatically adjusts the setup and hold on every channel eliminating the need for manual adjustment and ensuring accurate state measurements on high speed buses Timing Zoom Technology Simultaneously acquire data at up to 2 GHz timing and 400 MHz state through the same connection Timing Zoom is available across all channels all the time See page 23 VisiTrigger Technology Processor and Bus Support Direct Links to Industry Standard Debuggers and High Level Language Tools Direct Links to EDA Tools e Use graphical views and sentence like structure to help you define a trace event gt Select trigger functions as individual trigger conditions or as building blocks to easily customize a trigger for your specific task gt Get control over your microprocessor s internal and external data Quickly and reliably connect to the device under test See page 36 Debuggers provide visibility into software execution for systems running software written in C and C as well as active microprocessor execution control run control Import symbol files created by your language tool Symbols allow you to set up trigger conditions and review waveform and state listings in easily recognized terms that r
113. ls Supported 16700B Series 10BaseT 100BaseT X ethertwist RJ 45 16700A Series 10BaseT ethertwist RJ 45 10Base2 BNC TCP IP NFS CIFS Windows 95 98 NT 1 FTP NTP PCNES X Window Support X Window system version 11 release 6 as a client and server 1 User and share level control supported for Windows NT 4 0 Share level control only supported for Windows 95 98 75 Mainframe Specifications and Characteristics Agilent 16700 Series Technical Information continued 76 Web Server Supported from Instrument Web Page Measurement status check remote display installation of PC application software link to Agilent s Test and Measurement site PC Requirements Pentium family PC 200 MHz 32 MB RAM running Windows 95 Windows 98 or Windows NT 4 0 with service pack 3 or higher Supported Web Browsers on Your PC or Workstation Internet Explorer 4 0 or higher Netscape 4 0 or higher IntuiLink Support Installation of PC Application Software Directly from instrument web page MS Excel Excel 97 Version 7 0 or later Excel limits maximum trace depth to 64K per sheet Available Data Formats Fast Binary Compressed Binary Format High performance transfer rate Includes source code to parse data Available via File Out Uncompressed Binary ASCII Pattern Generator Binary Intermodule Bus IMB Includes utility routines Available via RPI
114. lysis probes for over 200 microprocessors and software tools for ASIC emula tion and test system design See the Processor and Bus Support For Agilent Technologies Logic Analyzers p n 5966 4365 document for contact information concerning these vendors Solutions Partner Advanced Logic Design ALD Application Focus Product design services digital Contact Information www ald com Aptix ASIC emulation www aptix com JM Engineering JME Probing solutions for SMT parts www jmecorp com American Arium Advanced RISC Machines ARM Intel emulators and probes Microprocessor core IP Www arium com www arm com CAD UL Software programming tools www cadul com Corelis Analysis probes for various www corelis com microprocessors and buses Diagonal Manufacturing test suite www diagonal com software Emulation Technologies ET Probing www emulation com Europe Technologies Embedded system design tools and services www europe technologies com FuturePlus Systems Analysis probes for computer buses www futureplus com Green Hills Software Inc GHS Debugger and compiler software for Motorola microprocessors www ghs com Ironwood High density VLSI interconnect solutions www ironwoodelectronics com Lital Electronics Inc Mil spec computer boards www lital com Mobile Media Research PCMCIA focused development tools w
115. m Transitional timing y V V Context Store V Eye Scan J 26 Data Acquisition and Stimulus State Timing Modules Agilent 16760A Extending Logic Analysis to New Realms e Differential inputs single ended probes also available e State analysis up to 1 5 Gb s e Setup and hold time of 500 ps Input signal amplitude as low as 200 mV p p Logic analysis at state speeds up to 1 5 Gb s imposes a stringent set of criteria for a logic analyzer s Probing Agilent s 16760A uses an innovative probing system with only 1 5 pF of probe tip capacitance including the connector The connector is a joint design between Agilent and Samtec optimized especially for logic analysis measurements Ground pins located between every pair of signal pins provide excellent channel to channel isolation at high speeds Setup and hold Publication Title User s Guide Agilent Technologies E5378A E5379A and E5380A Probes for the 16760A Logic Analyzer As state speeds go up the data valid window shrinks To make reliable measurements a logic analyzer s combined setup and hold window must be smaller than the data valid window of the signals it is acquiring Agilent s 16760A has a combined setup and hold time of 500 ps to match the data valid window of very high speed buses To position the analyzer s setup and hold window inside the data valid window requires very fine adjust ment resolution The 16760A
116. nals to source code Mainframes System Screens Expanding Possibilities with Network Connectivity Web enabled instrumentation gives you the freedom to access the system anywhere anytime Have you ever needed to check ona measurement s status while you were in a remote location Now you can With a Web Enabled Logic Analysis System You Can sid cna v T install Agilent IntuiLink to seamlessly access Agilent s Web site for the latest transfer data from the system to a PC online manuals and technical information access the logic analysis 44 Welcome to Agilent Technologies Web Enabled Site Microsoft Internet Explorer provided by Hewlett Packard system s Web page from Eile Edt View Go Favorites Help your browser by using the 4e gt Al a fa g R d B instrument s hostname as Back Fonvard Stop Refresh Home Search Favorites History Channels Fullscreen Mal a URL Ae rarae es Download Intyilink ClearCase Support Advanced Products Agilent Site Agilent Technologies PQ iUUNT iS RTE UE Nes 9 1 access the system s user interface directly from with welcome Page Welcome to your in your browser giving you i control of all analysis ae Web Enable Logic Analyzer unctions X Window Control a Your Current Connection Is SSS uri http vikingbO2 cos agilent com remotely check current 130 29 67 17 measurement status to find Pan out if the system has Status has been usi
117. nctions Settings Overview Status Save Recall General Timing Trigger function libraries Find pattern Find edge AND pattern Ut E M aa Find width violation on pattern pulse Find Nth occurrence of an edge edge 2 eS Replace l Insert before l Insert after J Delete L D Trigger Sequence 1 LP ADDR In range 00000044 000042A9 Hex And DATA XXXX03E7 Hex occurs 1 time then Counter 1 Increment Goto 3 Else if ADDR gt 000042069 Hex then Timer 1 Start from reset Goto Next Else if ADDR lt 00000044 Hex then Goto 1 2 FIND EDGE AND PATTERN Find TS Edge q and ADDR XXXX43C5 Hex then Flag 1 Set Trigger and fill meno Flags can be set cleared and evaluated by any 16715A 16A 17A 40A 41A 42A 50A Values can be easily entered directly into 51A 52A 60A module in the frame This the trigger description allows you to set up a trigger that is depend ent on activity from more than one bus in the system Figure 4 2 Set up your trigger in terms of the measurements you want to make Data Acquisition and Stimulus State Timing Modules 2 GHz Timing Zoom Provides High Features and Applications Speed Timing Analysis Across All Timing Zoom Simultaneously acquire up to 16K of data at 2 GHz timing and Channels All the Time available in the 16716A 400 MHz state across all channels all the time through the same When you re pushing the speed 16717A 16740A 16741A connection envelope
118. ndividual channels after running eye finder 1 25 ns window 1 25 ns window Minimum state clock pulse width 1 2 ns 1 2 ns Time tag resolution 2 4ns 4ns Maximum time count between states 17 seconds 17 seconds Number of state clocks 1 1 Maximum memory depth 16717A 2M 16750A 4M 16751A 16M 16752A 32M Maximum trigger sequence speed 333 MHz 400 MHz Maximum trigger sequence levels 15 15 Trigger sequence level branching Dedicated next state branch or reset Dedicated next state branch or reset Trigger position Start center end or user defined Start center end or user defined All specifications noted by an asterisk are the performance standards against which the product is tested 1 Tested at input signal VH 0 9V VL 1 7V Slew rate 1V ns and threshold 1 3V 2 Time or state tags halve the acquisition memory when there are no unassigned pods 92 State Timing Modules Specifications and Characteristics Agilent Technologies 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Supplemental Specifications and Characteristics continued State Mode Trigger resources 16715A 16716A 16717A 167 Mb s State Mode 8 Patterns evaluated as 4 gt lt gt lt 4 Ranges evaluated as in range not in range 2 Occurrence counters 4 Flags 16750A 16751A 16752A 400 Mb s State Mode 8 Patterns evaluated as gt lt gt lt 4 Ranges ev
119. nel y 64 M memory depth Discontinued products 118 Ordering Information Measurement Module Compatibility Table continued Measurement Model Description 16700 16600 16500C 16500A B Module Category Number Series Series Oscilloscope 16530A 16531A 2 Channel 100 MHz Bandwidth 400 MSa s V V 4 K memory depth 16532A 2 Channel 250 MHz Bandwidth 1 GSa s V V 8 K memory depth 16533A 2 Channel 250 MHz Bandwidth 1 GSa s V V V 32 K memory depth 16534A 2 Channel 500 MHz Bandwidth 2 GSa s V V V 32 K memory depth High Speed Timing 16515A 16516A 1 GHz Timing 8 K memory depth y y 16517A 16518A 4 GHz Timing 1GHz Synchronous State y y y y 64 K memory depth Pattern Generator 16520A 16521A 50 MV s 4 K memory 12 Channel y y 16522A 200 MV s 258 K memory 100 MHz in 40 Channel y y y 200 MHz in 20 Channel 16720A 300 MV s 180 MHz in 48 Channel 16 MV memory y 300 MHz in 24 Channel 8 MV memory Emulation E5901A Emulation Module Products y y E5901B Emulation Module Products y Discontinued products Options for Agilent 16700 Series State Timing Modules Agilent Module Product Numbers Option Option Description 16517A 16518A 0B3 Add service manual 16710A 1BP MIL STD 45662A calibration with test data 16711A W17 Convert standard warranty to one year on site warranty 16712A 16715A 16716A 16717A 16750A 16751A 16752A 16760A 010 add one E5378A single ended 34 channel probe 011 add one E5379A d
120. ng can be particularly susceptible to noise effects Agilent Technologies designs probing solutions with high immunity to transient noise High input impedance will minimize the effect of probing on your circuit Although many probes are acceptable for lower frequencies capacitive loading dominates at higher frequencies Ruggedness A flimsy probe will give you unintended open circuits Agilent Technologies probes are mechanically designed to relieve strain and ensure a rugged and reliable connection Connectivity A multitude of device packages exist in the digital electronics industry Check our large selection of probing solutions designed for specific chip packages or buses As an alternative we offer reliable termination adapters that work with standard on target connectors Probing Solutions Technologies Choose the Optimum Probing Strategy for Your Application Connecting to individual test points with flying leads Advantages Most flexible method Flying lead probes are included with logic analyzer module except 16760A Figure 3 2 Limitations Can be time consuming to connect a large number of channels Least space efficient method Connecting to all the pins of a quad flat pack QFP package Advantages Rapid access to all pins of fine pitch OFP package Very reliable connections 14 Figure 3 7 Limitations Requires minimal keepout area NEW Figure
121. ng mode only 2 Minimum setup hold time specified for single clock single edge acquisition Single clock multi edge setup hold add 0 5 ns Multi clock multi edge setup hold window add 1 0 ns 86 State Timing Modules Specifications and Characteristics Agilent Technologies 16710A 16711A 16712A Supplemental Specifications and Characteristics Probes general purpose lead set Input resistance 100 KQ 2 Parasitic tip capacitance 1 5 pF Minimum voltage swing 500 mV peak to peak Threshold accuracy 100 mV 3 of threshold setting Maximum input voltage 40 V peak State Analysis Minimum state clock pulse width 3 5 ns Time tag resolution 1 8ns Maximum time count between states 34 seconds Maximum state tag 4 29 x 109 states count between states 1 Minimum master to master clock time 16710A 16711A 16712A 10 ns Minimum master to slave clock time 0 0 ns Minimum slave to master clock time 4 0 ns Context store block sizes 16710A 11A 12A only 16 32 64 states Timing Analysis Sample period accuracy 0 01 of sample period Channel to channel skew 2 ns typical Time interval accuracy sample period channel to channel skew 0 01 of time interval reading Minimum detectable glitch 3 5 ns All specifications noted by an asterisk are the performance standards against which the product is tested 1 Time o
122. ng the logic analyzer K since 01 03 01 at 11 09 pm triggered Shared ars quickly check instrument status to determine if the ese system is available for use Z Figure 2 6 Your logic analyzer is its own web site From the Home Page you can perform multiple remote functions Mainframes IntuiLink Agilent IntuiLink Moves Your Data Automatically into Microsoft Excel for Advanced Offline Analysis IntuiLink is shipped with each logic analysis system and can be down loaded to your PC from the system s own web page Use the Agilent IntuiLink tool bar to connect to a logic analysis system Select from the available labels and specify the destination cell location in Microsoft Excel Use Microsoft Excel s powerful functions to post process captured trace data for the insight you need Be Git Yew Por Format Ince Da dee tee DSR aar ARG o o Target_Temp Temperature Variation Over Time fu Bit OH 2 F 9 4 J F Jw U K Sg HIE mmm l inten ee Import data from a current acquisition or data previously saved to a file via the File Out tool Programming IntuiLink also includes an Active X automation server to provide programmatic control of the logic analysis system from an external environment such as LabVIEW or the Microsoft VisualStudio environment of Visual Basic and Visual C tools The instrument s Remote Programming Interface or R
123. o connect to logic analyzer and correlation fixture oscilloscope Agilent 1184A Testmobile The Agilent 1184A testmobile gives you a convenient means of organizing and transporting your logic analysis system mainframes and accessories The testmobile includes the following e Drawer for accessories probes cables power cords Weight Max Net Max Shipping Figure 7 1 Agilent 1184A testmobile cart 1184A 48 0 kg 106 0 Ib 59 0 kg 130 0 Ibs 482 6 19 0 772 2 30 4 Dimensions mm inches Figure 7 2 Agilent 1184A testmobile cart dimensions Keyboard tray with adjustable tilt and height Mouse extension on keyboard tray for either right or left hand operation Locking casters for stability on uneven surfaces Strap to stabilize the monitor Load limits Top tray 68 2 kg 150 0 1b Lower tray 68 2 kg 150 0 1b Total 136 4 kg 300 0 1b 1714 1 30 5 594 4 s 117 Ordering Information Measurement Module Compatibility Table Measurement Model Description 16700 16600A 16500C 16500A B Module Category Number Series Series State and Timing 16510A 25 MHz State 100 MHz Timing 1 K memory depth y y 16510B 35 MHz State 100 MHz Timing 1 K memory depth y y 16540A 16541A 100 MHz State 100 MHz Timing 4 K memory depth y y 16540D 16541D 100 MHz State 100 MHz Timing 16 K memory depth y y 16542A
124. o manually configure the trigger sequencer for complex measurements All custom defined protocol fields or layers are support ed in the trigger macro All packets or cells are time stamped in the logic analyzer for time correla tion measurements with other system buses such as a microprocessor memory interface PCI bus or other UTOPIA bus All state listing and waveform displays in the logic ana lyzer are time correlated with global markers for a complete view of the system With this tool it is possible to trigger the logic analyzer with a microprocessor event and see what is happening on a parallel data bus with protocol information By monitoring multiple time correlat ed data buses you can monitor a packet entering one ASIC and see how long it takes for the packet to reach another part of the system The powerful trigger can also monitor a packet entering one port and trigger if the packet has not reached another port by a designated time 45 Post Processing and Analysis Tool Sets Data Communications Theory of Operation Use a logic analyzer to probe the system s parallel data buses e g UTOPIA Custom UTOPIA The analyzer needs access to e Data signals e Qualifying signals e Start of cell or packet bit e Synchronous clock for the bus Switch Fabric The synchronous bus clock samples data into the logic analyzer Qualifiers such as Data Valid allow the logic analyzer t
125. o reorganize the acquired data under these new labels or to include data or text derived from the acquired data The functions allow e Stopping a repetitive run e Filtering of the data e Randomly accessing the data e Searching the data e Displaying the data in one of eight colors e Accessing the trigger point e Accessing the acquired time or state of the data e Outputting text strings to the tool s display window e Outputting errors to the runtime window By using two of the provided func tions a simple user interface can eas ily be created that consists of label strings and input fields This allows the input of parameters during the tool s execution Post Processing and Analysis Tool Sets Licensing Information Licensing and Miscellaneous Description System Configuration Requirements Tool Set Control 16700 Series logic analysis system Desired tool set s Supported and compatible measurement hardware Locally control and view tool set measurements Remotely access any tool set from a PC or workstation through a web browser or X window emulation software File Access Ordering and Shipment Access source files or other development environment applications compiler debugger from the logic analyzer via Telnet NFS or mapped file systems and X Windows client server protocols Save or access files via the standard network capabilities of the logic analyzer such as FTP NFS or CIFS Common Int
126. o sample only on events of interest instead of all a S S With access to the Start of Cell or l l cycles Start of Packet bit on the data bus the analyzer starts looking at the beginning of a cell or packet With the protocol definition set up by the user the logic analyzer can sequence down into the cell or packet to find the desired protocol field to trigger on UTOPIA Level 1 Figure 5 5 Typical ATM Switch Design 46 Post Processing and Analysis Tool Sets Data Communications Product Characteristics Requires Applications 16700 Series logic analysis system with system software version A 01 50 00 or higher Trigger on a processor event and see what is happening on a parallel data bus with protocol information or vice versa Additional Information Supported Measurement Modules 16715A 16716A 16717A 16718A 16719A 16750A 16751A 16752A Protocols Supported Trigger Macro Maximum Parallel Bus Width gt Ethernet ATM TCP IP Stack gt Custom All custom defined protocol fields or layers are supported in the trigger macro Limited only by the number of available channels Example files for these protocols are provided with the product These standard files can be edited to include any custom protocol wrapper layers or fields Custom protocols are supported by entering the protocol setup information via the logic analyzer interface or a text file
127. oad for the Agilent 16715A 16716A 16717A 16718A 16719A 16750A 16751A 16752A general purpose lead set 89 State Timing Modules Specifications and Characteristics Agilent Technologies 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Supplemental Specifications and Characteristics State Mode Maximum state acquisition rate on each channel 16715A 16716A 16717A 167 Mb s State Mode 167 Mb s 16740A 16741A 16742A 16750A 16751A 16752A 200 Mb s State Mode 200 Mb s Channel count 68 per module 68 per module Maximum channels on a single time base and trigger 340 340 Number of independent analyzers 2 can be set up in state or timing modes 2 can be set up in state or timing modes Minimum master to 5 988 ns 5 ns master clock time 1 Minimum master to slave clock time 2ns 2ns Minimum slave to master clock time 2ns 2ns Minimum slave to slave clock time 5 988 ns 5 ns Setup hold time 1 single clock single edge 2 5 ns window adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps increments per channel 2 5 ns window adjustable from 4 5 2 0 ns to 2 0 4 5 ns in 100 ps increments per channel Setup hold time 1 multi clock multi edge 3 0 ns window adjustable from 5 0 2 0 ns to 1 5 4 5 ns in 100 ps increments per channel 3 0 ns window adjustable from 5 0 2 0 ns to 1 5 4 5 ns in 100 ps increments per channel Setup
128. ock input take care to set the clock threshold accurately to avoid phase error 2 Eye width and height are specified at the probe tip Eye width as measured by eye finder in the analyzer may be less and still sample reliably 3 For each side of a differential signal pSignal ko vHeight nSignal vhoight 2X a 4 The clock inputs in the E5378A and the E5382A may be connected differentially or single ended Use the E5379A vHeight spec for clock channel s connected differentially 5 Sample positions are independently adjustable for each data channel input A negative sample position causes the input to be synchronously sampled by that amount before each active clock edge A positive sample position causes the input to be synchronously sampled by that amount after each active clock edge A sampling position of zero causes synchro nous sampling coincident with each active clock edge 6 Threshold applies to single ended input signals Thresholds are independently adjustable for the clock input of each pod and for each set of 16 data inputs for each pod Threshold lim its apply to both the internal reference and to the external reference input on the E5378A 96 State Timing Modules Specifications and Characteristics Agilent Technologies 16760A Supplemental Specifications and Characteristics continued Synchronous state analysis 1 5 Gb s mode 1 25 Gb s mode 800 Mb s mode 400 Mb s mode 200 Mb s mode Maximum data rate E5
129. odule in the frame Flags allow you to set up a trigger that is dependent on activity from more than one bus in the system gt Specify four way arbitrary IF THEN ELSE branching Examples of Problems that Can be Captured Easily with VisiTrigger Description Typical Applications Graphic Pulse too narrow or too wide Line hangs at wrong level high or low K Min width K Max width 4 Asynchronous input for example an interrupt persists too long Strobe width is too narrow or too wide ie i Pulse too narrow Pulse too wide Time between two edges is e Excessive delay in responding to a bus grant request longer than specified e Excessive delay in responding to a data valid with a data acknowledged edge 1 edge 2 time Pattern lasts longer than a Abus hangs up at a given value w X specified time pattern time Pattern two exists within a gt An incorrect response to a read or write SOO i 4 pattern 1 specified time after pattern An incorrect output from a FIFO or bridge one is detected time x pattern 2 x A pattern exists for less N than a specified time respond A driver is not holding a bus value long enough for a receiver to pattern PS a time __ 21 Data Acquisition and Stimulus State Timing Modules VisiTrigger Your most commonly used triggers are just a mouse click away with the built in trigger functions VisiTrigger s gra
130. ogic 0 ti Agilent 10468A PECL CLOCK POD A FOR USE WITH AGILENT PATTERN GENERATORS Clock in to clock out Pattern in to recognition approximately 30 ns approximately 15 ns 1 clk period Recommended lead set Agilent 10498A 10470A 3 3 volt LVPECL Clock Pod Clock output type 100LVEL90 3 3V with 215 ohm pulldown to ground and 42 ohm in series Clock output rate 300 MHz maximum Clock out delay only approximately 8 ns total in 14 steps 16720A only 11 ns maximum in 9 steps 16522A Clock input type 100LVEL91 LVPECL 3 3V no termination Clock input rate dc to 300 MHz Pattern input type 100LVEL91 LVPECL 3 3V no termination no connect is logic 0 100EL91 aig Agilent 10470A LVPECL CLOCK POD A FOR USE WITH AGILENT PATTERN GENERATORS om BND CLK IN las 100LVEL90 Clock in to clock out approximately 30 ns Pattern in to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10498A 112 100LVEL91 100EL90 42 Q NAVV gt CLKout 348 Q CLKin 42 Q NAVV gt CLKout 215 Q lt CLKin Pattern Generation Modules Specifications and Characteristics 10472A 2 5 volt Clock Pod Clock output type T4AVC16244 Clock output rate 200 MHz maximum Clock out delay only approximately 8 ns total in 14 steps 16720A only 11 ns
131. ons and Characteristics Isolation Adapter 01650 63203 Isolation adapters that connect to the end of the probe cable are designed to perform two functions The first is to reduce the number of pins required for the header on the target board from 40 pins to 20 pins This process reduces the board area dedicated to the prob ing connection The second func tion is to provide the proper RC isolation networks in a very con venient package E5346A 38 pin Probe E5339A 38 pin Low Voltage Probe 84 Adapter RC Network 250 90 9k ohm ohm Signal To Logic Analyzer 8 2pF Pod Ground e HW___ Equivalent Load 370 ohm Signal 4 6pF 7 4pF Ground e T it Includes logic analyzer Figure 6 9 Termination adapter and equivalent load 370 ohm Signal T NAVV T 100k 3pF 9pF S ohm Ground e Figure 6 10 E5346A equivalent load 220 ohm Signal T NAVV T 50 5k Ground e Figure 6 11 E5339A equivalent load State Timing Modules Specifications and Characteristics Key Specifications and Characteristics Agilent Model Number Maximum state acquisition rate on each channel 16715A 16716A 16717A 16715A 16716A 167 Mb s 16717A 333 Mb s 1 16740A 16741A 16742A 200 Mb s 16750A 16751A 16752A 400 Mb s 1 16760A Full channel 800 Mb s Half channel 1 25 Gb s Maximum timing sample rate half full channel Timing Zoom 2 GHz 16716A 16717A
132. op Measurement Current Run Status Start Stop Query a Session Logic Analysis Modules Load Save Configuration and Data Trigger Setup Acquisition Data and Parameters Set Query Acquisition Mode Set Query Acquisition Depth Set Query Pod Assignment Add Delete Load Query Labels Set Query Trigger Position Modify Occurrence Count Oscilloscope Modules Load Save Configuration and Data Acquisition Data Parameters Query Automatic Measurements Trigger Setup Pattern Generator Load Save Configuration and Data Load ASCII file vectors or PGB pattern generator binary files 16720A only Modify Vector Set Query Clock Frequency Set Query Clock Out Delay Insert New Vector at Specific Position Delete Specific Vector Emulation Module Reset Processor Run Processor Break Processor Single Step Listing Tool Status Acquisition Data and Parameters Transfer Data includes inverse assembled information Compare Tool Execute Compare Set Compare Mask Query Compare Result Specify Range to Compare Abort Compare After Specified Number of Differences Return Labels and Values Where Differences Occur File Out Tool Transfer Data to File Select Range to Expert Additional Information Instrument Online Help Programming Information in instrument online help Web Sites Full remote programming documentation pdf available on the hard drive Sample programs are provided 79 Mainframe Specifications and Characteristics
133. or optional monitor Parallel printer port SCSI Il connection for an Up to 1600x1200 video external 18 GByte data drive or Five slots for resolution with option 003 10 100BaseT LAN autosensing external removable hard drive measurement modules Expander frame connection provides an Built in 40x CD ROM drive makes it easy Option slot for an emulation module or additional five slots for measurement to install or update system software for a multiframe module Multiframe modules processor support or tool sets option allows up to eight mainframes and expanders to be combined so that you can see all the buses in a complex target system Figure 2 2 The mainframe and expander frame provide advanced capabilities for debugging complex target systems 8 Mainframes System Screens Figure 2 3 Icons in the power up screen give you quick access to common tasks System Admin Setup Assistant Demo Center allows you to quick is a guided menu provides simple ly set up the instru system that helps demos of the most ment on your net you configure the commonly used work configure logic analysis sys features print servers setup tem for your target user accounts for microprocessor or security or install bus Online infor software updates mation guides you through the setup See figure 2 4 Figure 2 4 Setup Assistant gets you up and running quickly Mainframes System Screens See the Big Picture of Your Prototype System
134. peat loop 20000 Maximum number of repeat loop invocations 1000 Maximum number of Wait event patterns 4 Number of input lines to define a pattern 3 Maximum number of modules in a system 5 Maximum width of a vector in a 5 module system 240 bits Maximum width of a label 32 bits Maximum number of labels 126 Maximum number of vectors in binary format Minimum number of vectors in binary format 16 MVectors 4096 Lead Set Characteristics Agilent 10474A 8 channel Provides most cost effective lead set for the 16522A and probe lead set 16720A clock and data pods Grabbers are not included Lead wire length is 12 inches Agilent 10347A 8 channel Provides 50 Q coaxial lead set for unterminated signals probe lead set required for 10465A ECL Data Pod unterminated Grabbers are not included Agilent 10498A 8 channel Provides most cost effective lead set for the 16522A and probe lead set 16720A clock and data pods Grabbers are not included Lead wire length is 6 inches 104 Pattern Generation Modules Specifications and Characteristics Data Pod Characteristics Note Data Pod output parametrics depend on the output driver and the impedance load of the target system Check the device data book for the specific drivers listed for each pod Agilent 10461A TTL Data Pod Output type 10H125 with 100 Q series ie Agilent 10461A Maximum clock 200 MHz ETE CLOCK POD Sa Skew 1 typical lt
135. phical representation shows you how the trigger condition will be defined You can use trigger functions as building blocks to easily customize a trigger for your specific task Sequence levels allow you to develop a sequence of analyzer instructions to specify a trigger point or to qualify data and store only the information that interests you Each step in the sequence contains an IF THEN ELSE structure that can evaluate up to four logic events Each event can specify a combination of actions such as store sample increment counters reset timers trigger or go to another step in the sequence level Ranges provide a way to monitor program and data accesses within a specified area in memory Global counters can count events such as the number of times a function executes or accesses an I O port Timers can be set up to evaluate when one event happens too late or too soon with respect to another event In timing mode edge terms let you trigger on a rising edge falling edge either edge or a glitch Patterns and their logical combinations let you identify which states to store when to branch and when to trigger 22 View current information on the state of Save and recall up to ten of your the timers counters flags and the trigger custom trigger setups without loading sequence level a new configuration file File Window Edit Options cle ti BS BOS S e lel i Sampling Format Trigger Symba Trigger Fu
136. ported Moderate to significant incremental cost Analyzers publication number processors and buses Only useable for the specific processor or bus 5966 4365E for specific solutions May require moderate clearance around processor or bus Data Acquisition and Stimulus State Timing Modules Selecting the Correct Modules performance cost and the amount of to Meet Your Needs data you will be able to capture The Selecting the proper logic analyzer modules for your needs requires a following table explains these factors in greater detail series of choices concerning Considerations for Choosing Modules Microprocessor Bus Support Will you be using an analysis probe for a particular processor or bus If so a good starting point is the document Processor and Bus Support for Agilent Technologies Logic Analyzers publication number 5966 4365E available on the worldwide web at www agilent com find logicanalyzer This document provides the number of channels and state speed required for any particular analysis probe It also indicates which analysis modules are supported and how many are required State Speed gt State analysis uses a clock or strobe signal from your system under test to determine when to sample Because state analysis samples are synchronous with the system under test they provide a view of how your system is executing You can use state analysis to capture bus cycles from a microprocessor or I 0 bus and con
137. r state tags halve the acquisition memory when there are no unassigned pods 370 ohms I I N 1 I 1 pa ek 100K TBE 74pF Kas l I lt _ 0 l aS GROUND Figure 6 12 Equivalent probe load for the Agilent 16710A 16711A and 16712A general purpose lead set 87 State Timing Modules Specifications and Characteristics Agilent Technologies 16710A 16711A 16712A Supplemental Specifications and Characteristics continued Triggering Maximum trigger sequence speed 125 MHz maximum Maximum occurrence counter 1 048 575 Range width 32 bits each Timer value range 400 ns to 500 seconds Timer resolution 16 ns or 0 1 whichever is greater Timer accuracy 32 ns or 0 1 whichever is greater Operating Environment Temperature Agilent 16700 Series mainframes gt Instrument 0 C to 50 C 32 F to 122 F gt Probe lead sets and cables 0 C to 65 C 32 F to 149 F Humidity 80 relative humidity at 40 C Altitude Operating 4600m 15 000ft Nonoperating 15 300m 50 000ft All specifications noted by an asterisk are the performance standards against which the product is tested 88 State Timing Modules Specifications and Characteristics Agilent Technologies 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Supplemental Specifications and Characteristics Probes general purpose lead set Input resistance 100 KQ 2 Para
138. ranch W Event Editor Event Name HIP Address R Long Field Names View Packet Bits Protocol Stack IEEE 802 3 Ethernet V2 Internet Protocol Version Header Length Precedence Symbols Delay Symbols Throughput Symbols Reliability Symbols Cost MBZ Total Length XXXXX Identification XXXX Symbols o i D m Zero Packet Bits Do not fragment X May Fragment X O XXXXXXXXXXXXXXXX 1 XXXXXXXXXXXXXXXX Fragment Offset 2 XXXXXXXXXXXXXXXK S l 3 XXXXXXXXXXXXXXXX Time To Live XXX 4 XXXXXXXXXXXXXXXX 5 XXXXXXXXXXXXXXXX 6 0000100000000000 7 XXXXXXXXXXXXXXXX 8 XXXXXXXXXXXXXXXX 9 XXXXXXXXXXXXXXXX 10 XXXXXXXXXXXXXXXX 11 XXXXXXXXXXXXXXXX 12 XXXXXXXXXXXXXXXX 13 XXXXXXXXXXXXXXXX 14 XXXXXXXXXXXXXXXX 15 0000111100010011 16 0000001101110100 Protocol Don t Care Header Checksum XXXX Src Addr XXX XXX XXX XXX Dest Addr 15 19 3 116 Physical representation of bit fields to be triggered on n s This window is automatically updated when fields are edited mel Figure 5 7 Post Processing and Analysis Tool Sets Data Communications Use the bus editor feature to specify m Bus Editor Rx Bus what protocol runs on your bus This is helpful when probing more than one bus with a single state timing module Figure 5 8 50 Post Processing and Analysis Tool Sets Data Communicat
139. rval reading sample period channel to channel skew 01 of time interval reading Minimum detectable glitch 1 5 ns 1 5 ns Memory depth half full channel 16716A 1M 512K 16715A 16717A 4 2M 16750A 8 4M 16751A 32 16M 16752A 64 32M All specifications noted by an asterisk are the performance standards against which the product is tested 93 State Timing Modules Specifications and Characteristics Agilent Technologies 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Supplemental Specifications and Characteristics continued Timing Mode continued 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Maximum trigger sequence speed 167 MHz 200 MHz Maximum trigger sequence levels 16 16 Trigger sequence level branching 4 way arbitrary IF THEN ELSE branching 4 way arbitrary IF THEN ELSE branching Trigger position Start center end or user defined Start center end or user defined Trigger resources 16 Patterns evaluated as lt gt lt 2 lt 15 Ranges evaluated as in range not in range 2 Edge glitch 2 Timers per module 1 2 Global counters 1 Occurrence counter per sequence level 4 Flags 16 Patterns evaluated as gt lt 2 lt 15 Ranges evaluated as in range not in range 2 Edge glitch 2 Timers per module 1 2 Global counters 1 Occurrence counter per sequence level 4 Flags
140. s Magnify your view or zoom in on a boxed area of interest Resize waveforms and data or quickly change colors to highlight areas of interest Web Enabled System Network Security NEW Time Correlation with Infiniium 54800 Series Oscilloscopes Directly access the instrument s web page from your web browser See page 11 Remotely check the instrument s measurement status without disturbing the acquisition Remotely access monitor and control your logic analysis system Protect your networked assets and comply with your company s security requirements with individual user logins that provide system integrity Make time correlated measurements using an Agilent 16700 Series logic analyzer and an Agilent Infiniium 54800 Series oscilloscope View Infiniium oscilloscope waveforms in the 16700 logic analyzer s waveform display Use the 16700 logic analyzer s global markers to measure time between any domain in the 16700 and voltage waveforms acquired by the Infiniium oscilloscope System Overview Selecting the Right System Selecting a system for your application Select a mainframe page 7 Choose a system based on your needs Self contained unit or a unit with external mouse keyboard and monitor Expander frame for large channel count requirements Determine your probing requirements page 13 e Are you analyzing a microprocessor Do you need to probe a specific package type Select the m
141. s module slot Dedicated hot keys 16701B Expansion frame with five measurement module 1 ft and 3 ft interface cables slots and two emulation module slots Requires a 16700A B or 16702A B 1184A Testmobile 4 wheeled equipment cart specifically designed to carry the 16700 Series logic analyzer expansion frame and monitor Drawer keyboard tray mouse tray strap for stabilizing monitor Mainframe Options Option Description 16700B or 16700A or 16701B 16701A Number 16702B 16702A 001 Add 17 inch 1280x1024 monitor V V 003 Performance option Up to 256 MBytes total system y y RAM 4 MBytes total video RAM 256 MB 160 MB 004 Add external CD ROM drive and cable V 008 External auxiliary 18 GByte hard disk drive y y 009 Removable internal hard disk V V 012 Multiframe option y 0B3 Add service guide y 1CM Add rack mount kit all but 16702B y y y y AXC Equipment shelf 16702B only y ABJ Japanese localization y W17 Convert standard warranty to one year on site warranty y y y y W30 Extend standard warranty to three year return to Agilent warranty y y y y W50 Extend standard warranty to five year return to Agilent warranty y y y y Built in CD ROM drive standard on 16700B Series 116 Ordering Information E5850A Logic Analyzer Infiniium Oscilloscope Correlation Time Fixture Product Number Description Includes E5850A Logic analyzer Infiniium oscilloscope time All BNC cables needed t
142. s 64M samples 32M samples 32M samples Time tag resolution 4ns 2 4ns 2 4ns 2 4ns 2 4ns Maximum time count 17 seconds 17 seconds 17 seconds 17 seconds 17 seconds between states Trigger resources 3 Patterns on each pod evaluated as Z gt lt 2 lt on one pod or evaluated as across multiple pods or 3 Patterns on each pod evaluated as gt lt gt lt on one pod or evaluated as across multiple pods or 4 Patterns on each pod evaluated as gt lt gt lt on one pod or evaluated as across multiple pods or 8 Patterns evaluated as a 4 gt lt 2 lt 4 Ranges evaluated as in range not in range 2 Occurrence counters 16 Patterns evaluated as a 15 Ranges evaluated as in range not in range Timers 2 x number of 1 range on each pod 1 range on each pod 2 ranges on each pod 4 Flags modules 1 4 Flags 4 Flags 4 Flags Arm in 2 Global counters Arm in Armin Arm in 1 Occurrence counter per sequence level 4 Flags Arm in Trigger actions Trigger and fill memory Trigger and fill memory Trigger and fill memory Goto Goto Trigger and fill memory Trigger and fill memory Trigger and goto Store don t store sample Turn default storing on off Timer start stop pause resume Global counter increment reset Occurrence counter reset Flag set clear All specifications noted by an asterisk are the performance standards against which the product is tested 1 In
143. ses The data associated with an individual label can be viewed with multiple radixes to simplify data entry Delete Insert Copy and Merge commands are provided for easy editing Fast and convenient Pattern Fills give the programmer useful test patterns with a few key strokes Fixed Count Rotate Toggle and Random are available to quickly create a test pattern such as walking ones Pattern parameters such as Step Size and Repeat Frequency can be specified in the pattern setup 36 ASCII Input File Format Your Design Tool Connection The 16720A supports an ASCII file format to facilitate connectivity to other tools in your design environ ment Because the ASCII format does not support the instructions listed earlier they cannot be edited into the ASCII file User macros and loops also are not supported so the vectors need to be fully expanded in the ASCII file Many design tools will generate ASCII files and output the vectors in this linear sequence Data must be in Hex format and each label must represent a set of contiguous output channels Data in this ASCII format is limited to 1 MVectors in the 16720A Configuration The 16720A pattern generators require a single slot in a logic analysis system frame The pattern generator operates with the clock pods data pods and lead sets described later in this section At least one clock pod and one data pod must be selected to configure a func tional system Users
144. single clock single edge acquisition Multi clock multi edge setup hold window add 0 5 ns 4 There is one occurrence counter per trigger sequence level 5 Memory depth doubles in half channel 1 25 Gb s state mode only 85 State Timing Modules Specifications and Characteristics Key Specifications and Characteristics continued Agilent Model Number Maximum state acquisition rate on each channel 16710A 16711A 16712A 100 Mb s Maximum timing sample rate half full channel Conventional 500 250 MHz Transitional 125 MHz Channels module 102 Maximum channel count ona single time base and trigger 204 2 modules Memory depth half full channel 16710A 16 8K 1 16711A 64 32K 1 16712A 256 128k 1 Trigger resources Patterns 10 Ranges 2 Edge amp Glitch 2 Timers 2 Maximum trigger sequence levels State mode 12 Timing mode 10 Maximum trigger sequence speed 125 MHz Trigger sequence level branching Dedicated next state or single arbitrary branching Number of state clocks qualifiers 6 Setup hold time 4 0 ns window adjustable from 4 0 0 ns to 0 4 0 ns in 500 ps increments 2 per 34 channels Threshold range TTL ECL user definable 6 0 V adjustable in 50 mV increments All specifications noted by an asterisk are the performance standards against which the product is tested 1 Memory depth doubles in half channel timi
145. sis it can be used at any time to test and docu ment many other characteristics such as memory coverage and response time The SPA tool set generates statistical representations of the captured data It shows the amount and percent of time spent in each of the targeted functions or data locations Data is conveniently displayed in histograms and bar charts reducing the time you spend analyzing results and identify ing system bottlenecks Post Processing and Analysis Tool Sets System Performance Analysis Product Characteristics SPA Tools State Interval Display Time Interval Display Time Overview Display State Overview Display Generates Statistical representations of the captured data Shows the amount and percent of time spent in each of the targeted functions or data locations Provides Histogram of event Histogram of event times Overview of occurrence Overview of bus memory activity Display shows Display shows a rates over time activity Display shows the the percentage of hits distribution of the Measurements of the number of hits for each for each procedure execution time of a occurrence rate of any possible bus state function or event specific function or of event including states Events are the time between two interrupts over time defined as patterns or user defined events ranges associated with any set of data labels symbols Usage Helps prioritize functions Determines a specific Views t
146. site education and training as well as design system integration project management and other professional engineering services Experienced Agilent engineers and technicians worldwide can help you maximize your productivity optimize the return on investment of your Agilent instruments and systems and obtain dependable measurement accuracy for the life of those products Agilent T amp M Software and Connectivity Agilent s Test and Measurement software and connectivity products solutions and developer network allows you to take time out of connecting your instruments to your computer with tools based on PC standards so you can focus on your tasks not on your connections Visit www agilent com find connectivity for more information bY Agilent Email Updates www agilent com find emailupdates Get the latest information on the products and applications you select Microsoft is a U S registered trademark of Microsoft Corporation Netscape is a U S trademark of Netscape Corporation Windows and Windows NT are U S registered trademarks of Microsoft Corporation Pentium is a U S registered trademark of Intel Corporation UNIX is a registered trademark of the Open Foundation PostScript is a registered trademark of Adobe Systems www agilent com By internet phone or fax get assistance with all your test amp measurement needs Online assistance www agilent com find assist Phone or Fax United States tel 800 452 4844
147. sitic tip capacitance 1 5 pF Minimum voltage swing 500 mV peak to peak Minimum input overdrive 250 mV Threshold range 6V to 6V in 10 mV increments Threshold accuracy 65 mV 1 5 of settings Input dynamic range 10V about threshold Maximum input voltage 40V peak 5V Accessory current 1 3 amp maximum per pod Each group of 34 channels can be assigned to Analyzer 1 Analyzer 2 or remain unassigned Channel assignment 2 GHz Timing Zoom Agilent 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A only Timing analysis sample rate 2 GHz 1 GHz 500 MHz 250 MHz Sample period accuracy 50 ps Channel to channel skew lt 1 0 ns Time interval accuracy time interval reading sample period channel to channel skew 0 01 of Memory depth 16 K Trigger position Start center end or user defined Operating Environment Temperature Agilent 16700 Series frame 0 C to 50 C 32 F to 122 F Probe lead sets and cables 0 C to 65 C 32 F to 149 F Humidity 80 relative humidity at 40 C Altitude Operating 4600 m 15 000 ft Non operating 15 300 m 50 000 ft All specifications noted by an asterisk are the performance standards against which the product is tested i 370 ohms I I i V 1 l boila ale 100K 145p 74pF T hi 1 l I I I aoe i i GROUND Figure 6 13 Equivalent probe l
148. sponds to the selected clock transitions e The sampling point selected by eye finder If you want to select a different sample point on any individual channel just drag and drop the blue sample bar at the desired point 24 Data Acquisition and Stimulus State Timing Modules Eye Finder as an Analytical Tool Eye finder is very useful as a first pass screening test for data valid windows Because eye finder quickly examines all channels it is considerably faster than examining each channel with an oscilloscope After running eye finder you may want to use an oscilloscope to examine only those signals that are close to your desired specifications for setup and hold Eye finder also can quickly provide useful diagnostic or troubleshooting information If a channel has an unexpectedly small data valid window or an anomalous offset relative to clock this could be an indication of a problem or could be used to validate the cause of an intermittent timing problem Differences in the position of the stable region from one signal to another on a bus indicate skew An indication of excessive skew on eye finder can help isolate which channels you want to check with an oscilloscope or with the Timing Zoom 2 GHz timing analysis mode in your logic analyzer When Do You Need Eye Finder Eye finder becomes critical when the data valid window is lt 2 5 ns If you re unsure where your clock edge is relative to the data v
149. t header data mation using pref et header caca et header data erences et header data et header data et data et data et data et data et data Raw packet et data header aan Packet data information Packet data Packet data Packet data Packet data Packet data Packet data Packet data Packet data Raw payload Packet data pes Packet data information Packet data Packet data Packet data Packet data Packet data Packet data Packet data Packet data Packet data IEEE 802 3 Ethernet V2 Figure 5 11 53 Post Processing and Analysis Tool Sets System Performance Analysis Optimize System Performance Your design has to meet consistent performance requirements over a range of operating conditions and over a specific time period Using the system performance analysis tool set you can obtain answers to many of your questions concerning perform ance and responsiveness software execution coverage debug and sys tem parameter analysis etc Obtain Answers to the Following Questions Performance and Responsiveness e What functions monopolize micro processor bandwidth e What functions are never execut ed What is the relative workload of each processor in a multiple processor system e What is the minimum maximum and average execution time of a function including calls How many interrupts does the system receive per consecutive time slice e What is the response time of the targe
150. t system to an external event Software Execution Coverage e Do test suites provide thorough coverage of the application e Is this function or variable accessed by the application 54 Debug and System Parameter Analysis e Does this pointer address the right memory buffer e How does the system react when it receives too many simultaneous interrupts e Is the stack size adequate e Is the cache size adequate Analog Timing and Bus Measurements e What is the setup hold time of this signal or group of signals e Is the distribution of voltages for this analog signal acceptable e Is this signal spending too much time in the switching region e What bus states occur most often e What is the bus loading e How does the bus affect overall system performance e How much time is spent in bus arbitration e What is the histogram of bus transfer times Processor Cache Measurements e Which microprocessor bus states occur most often e Which peripherals are used most often e What is the profile of load sharing in a multiple processor system e How does the cache size affect system performance Product Description The Agilent Technologies B4600B sys tem performance analysis SPA tool set profiles an entire target system at all levels of abstraction from signals to high level source code It clearly identifies the components that affect the behavior of your system In addi tion to performance analy
151. tch the measurement capabilities Three probing options are available for the Agilent 16760A Each probe can be ordered by its individual Probes are not supplied as part of the standard 16760A Probes must be ordered separately either as options to the 16760A or individually by their respective model numbers model number or as an option to the 16760A The following table indicates both the model number and the option number Agilent Model Number 16760A Option Number Description Notes E5378A 010 100 pin single ended probe Requires a kit of mating connectors and shrouds see the next table to connect to target system E5379A 011 100 pin differential probe Two E5379A or two option 011 on the 16760A are required to support all 34 channels on a 16760A Requires a kit of mating connectors and shrouds see the next table to connect to target system E5380A 012 38 pin single ended probe compatible Maximum state analysis speed is 600 Mb s with target systems designed for the Minimum input amplitude is 300 mV p p Agilent E5346A Mictor adapter cable Requires a kit of mating connectors and shrouds see the next table to connect to target system E5382A 013 17 channel single ended flying lead Two E5382A are required to support all the channels probe set for the 16760A of a 16760A Connector and shroud kits for probes for the 16760A logic analyzer For probe model number For PC board thickness Probing connector kit
152. ted as lt gt lt 2 lt 15 Ranges evaluated as in range not in range 2 Timers per module 1 2 Global counters 1 Occurrence counter per sequence level 4 Flags 16 Patterns evaluated as lt gt lt 2 lt 15 Ranges evaluated as in range not in range 2 Timers per module 1 2 Global counters 1 Occurrence counter per sequence level 4 Flags Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations Trigger actions Goto Trigger and fill memory Trigger and goto Store don t store sample Turn on off default storing Timer start stop pause resume Global counter increment reset Occurrence counter reset Flag set clear Goto Trigger and fill memory Trigger and goto Store don t store sample Turn on off default storing Timer start stop pause resume Global counter increment reset Occurrence counter reset Flag set clear Store qualification Default and per sequence level Default and per sequence level Maximum global counter 16 777 215 16 777 215 Maximum occurrence counter 16 777 215 16 777 215 Maximum pattern range width 32 bits 32 bits Timers value range 100 ns to 5497 seconds 100 ns to 5497 seconds Timer resolution 5 ns 5 ns Timer accuracy 10 ns 01 10 ns 01 Timer reset latency 70 ns 70 ns Data in to trigger out BNC port 150 ns typical 150 ns typical Flag set reset to evaluat
153. tly being added to the list of supported CPUs For the most current informa tion about supported microproces sors please contact your Agilent Technologies sales representative or visit our web site http www agilent com find logic analyzer Object File Format Compatibility The 16700 Series logic analysis sys tems quickly and reliably read your specific object file format Agilent Technologies extensive experience with different file formats and sym bol representations ensures that your source code files are accurately cor related and your system is precisely characterized Source correlation and system per formance measurements do not require any change in your software generation process No modification or recompilation of your source code is required 44 You can load multiple object files Address offsets are also supported enabling system performance meas urements and source code level views of dynamically loaded software exe cution or code moved from ROM to RAM during a boot up sequence High level language tools that pro duce the following file formats are supported e Agilent CHP MRI IEEE696 e ELF DWARF e ELF Stabs e TI COFF e COFF Stabs e Intel OMF86 e Intel OMF96 e Intel OMF 286 e Intel OMF 386 which supports Intel80486 and Pentium Language Supports C name de mangling If your language system does not gen erate output in one of the listed for mats a generic ASCII file
154. to 1 or 1 to 0 in the timing analyzer trace are used to resynchronize the sampling 2 The timing analyzer data is sam pled in the middle of each bit according to the serial bit rate defined in the clock recovery window Resynchronize on edge 0000000000000000000001111111111111111110111111111 0 0 1 1 1 1 1 Post Processing and Analysis Tool Sets Serial Analysis Once the Serial Bit Stream is Acquired This example shows the conversion of an RS 232 serial bit stream The data sent to the printer includes the column header MACHINE configure the view the seria serial tool once for conversion in th your specific bus is easiest for yo then save the con form or listing figuration for future uses L ESS Parallel File Window Edit Options Invasm Sour to parallel ce File Window Edit Options Help IGI 1 139 as Delay 14 707 ms Figure 5 20 Wt vuu display the parallel data in binary hex octal deci mal ASCII or Twos Complement use the global markers and time tags to correlate real time serial traces to other system activity synchronize the start of the serial to parallel con version to the start of the frame pattern for your spe cific bus convert the data block into parallel words in this case 8 bit words find the Nth occurrence of specific frames or data relative to the trigger other m
155. to a file 80 Mainframe Specifications and Characteristics Agilent 16700B Series Physical 12 1 Built in LCD p 3 5 Inch Floppy Characteristics Display with Touch Disk Drive Screen A Power 16700B 115 230 V 48 to 66 Hz 610 W max On Off 16701B 115 230 V 48 to 66 Hz 545 W max H 16702B 115 230 V 48 to 66 Hz 610 W max Lu Power Switch Touch Screen On Off Weight Figure 6 1 Agilent 16702B front panel Max Net Max Shipping fare 12 7 kg 21 0 lo 25250 Parallel Port LAN 10BaseT 100BaseT X 16701B 10 4 kg 23 0 Ib 32 0 kg 70 6 Monitor SCSI 2 Single Ended Ibs RS 16702B 15 2 kg 32 4 Ib 36 7 kg 80 8 S N K Ibs Five Slots for Am J ee l z One Slot for Weight of modules ordered with mainframes will add Measurement Emulation or 0 9 kg 2 0 Ib per module Modules pE Multiframe Eat l Module Target Control Port AZAA N 40x CD ROM Port IN Keyboard Mouse Drive Port OUT Expansion Frame Cable Connector Figure 6 2 Back panel for Agilent models 16700B and 16702B a 551 2 21 7 425 7 16 75 Figure 6 3 Exterior dimensions for the 16700B Series mainframe Dimensions mm inches 81 Mainframe Specifications and Characteristics Agilent 16700A Series Physical Characteristics Built in LCD Display Power 16700A 115
156. tstanding transactions pipelining out of order execution and deep FIFOs all mean that the flow of data related to a problem can be distributed over thousands or millions of bus cycles The keys to useful insight are the combination of deep memory with responsive display refresh search rescaling and scrolling to help you find information and answers quickly Hardware assisted memory management in the Agilent 16740A 16741A 16742A 16750A 16751A 16752A and 16760A state and timing analysis modules makes quick work of refreshing the display rescaling scrolling and searching It takes only a few seconds to refresh rescale or scroll a 32M sample record Agilent Technologies offers a range of state and timing analyzer modules with memory depths up to 128M samples at prices to meet your budget Triggering The logic analyzer memory system is similar to a circular buffer When the acquisition is started the analyzer continuously gathers data samples and stores them in memory When memory becomes full it simply wraps around and stores each new sample in the place of the sample that has been in memory the longest This process will continue until the logic analyzer finds the trigger point The logic analyzer trigger stops the acquisition at the point you specify and provides a view into the system under test The primary responsibility of the trigger is to stop the acquisition but it can also be used to control the selective storage of data Cons
157. ture 5 1 ns for trigger sequencing 3 8 ns for data capture 5 1 ns for trigger sequencing Maximum trigger sequencer speed 200 MHz 200 MHz Trigger resources 16 Patterns evaluated as lt gt lt 2 lt 15 Ranges evaluated as in range not in range 2 Edge glitch 2 Timers per module 1 2 Global counters 1 Occurrence counter per sequence level 4 Flags Arm In 16 Patterns evaluated as lt gt lt 2 lt 15 Ranges evaluated as in range not in range 2 Edge glitch 2 Timers per module 1 2 Global counters 1 Occurrence counter per sequence level 4 Flags Arm In Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations Trigger actions Goto Trigger and fill memory Trigger and goto Timer start stop pause resume Global counter increment reset Occurrence counter reset Goto Trigger and fill memory Trigger and goto Timer start stop pause resume Global counter increment reset Occurrence counter reset Maximum global counter 16 777 215 16 777 215 Maximum occurrence counter 16 777 215 16 777 215 Timer value range 100 ns to 5497 seconds 100 ns to 5497 seconds Timer resolution 5 ns 5 ns Timer accuracy 10 ns 0 01 10 ns 0 01 Greater than duration 5 ns to 83 ms in 5 ns increments 5 ns to 83 ms in 5 ns increments Less than duration 10 ns to 83 ms in 5 ns increments 10 ns to 83 ms in 5 ns increments
158. vert the data into processor mnemonics or bus transactions using an Agilent Technologies inverse assembler gt Select a state acquisition system that provides the speed and headroom you need without breaking your budget Remember that a microprocessor will have an internal core frequency that is normally 2X 5X the speed of the external bus Headroom You may realize a better return on your investment if you consider possible future needs when purchasing analysis modules The things to consider are primarily state speed and memory depth Setup Hold e Logic analyzers require time for the data at the inputs to become valid setup time and time to capture the data hold time A lengthy setup and hold can make the difference between capturing valid data or data in transition gt Your device under test will ensure that data is valid on the bus for a defined length of time This is known as the data valid window Your target s data valid window must be large enough to meet the setup hold specifications of the logic analyzer The data valid window of most devices is generally less than half of the clock period Don t be fooled by typical setup and hold specifications for logic analyzers gt As bus speeds increase the time window during which data is stable decreases Jitter skew and pattern dependent ISI add more uncertainty and consume a greater portion of the data valid window at high speeds A logic analyzer with adjustable setup hold with f
159. ww mobmedres com Microtec Mentor Graphics Embedded Software Division Debuggers and compilers www mentor com embedded Pomona Electronics Supplier of accessories for electronic test instruments www pomonaelectronics com DIAB SDS Skyline SynaptiCAD WindRiver Debuggers compilers Probing and manufacturing services Waveform simulation analysis software Embedded RTOS development tools www diabsds com phone only 719 390 9425 www syncad com www windriver com 123 Support Warranty and Support and Services Agilent s support services comple ment your logic analysis system to provide a complete solution to your digital design and debug problems By taking advantage of Agilent s expertise you can concentrate on your particular design projects and applications rather than your debug tools resulting in increased produc tivity Related Literature Publication Title Related Literature Warranty Agilent hardware products are war ranted against defects in materials and workmanship for a period of one year from date of shipment Some newly manufactured Agilent products may contain remanufactured parts which are equivalent to new in per formance If you send us a notice of such defects during the warranty period we will either repair or replace hardware products that prove to be defective Publication Type Agilent software and firmware prod ucts that are designated b
160. y Agilent for use with a hardware product are warranted for a period of one year from date of shipment to execute their programming instructions when properly installed If you send us notice of defects in materials or workmanship during the warranty period we will repair or replace these products so long as the defect does not result from buyer supplied hardware or interfacing The warranty period is controlled by the warranty statement included with the product and begins on the date of shipment Publication Number Processor and Bus Support For Configuration Guide 5966 4365E Agilent Technologies Logic Analyzers Probing Solutions for Product Overview 5968 4632E Agilent Technologies Logic Analysis Systems Emulation and Analysis Solutions for Product Overview 5966 2866E the Motorola MPC 8XX Microprocessors Emulation and Analysis Solutions for Product Overview 5966 2868E the Motorola IBM PowerPC 6XX Microprocessors Emulation and Analysis Solutions for the Product Overview 5966 2867E Motorola IBM Power PC 740 750 Microprocessors Agilent E2487C Analysis Probe amp Agilent E2492B C E Product Overview 5968 2421E Probe Adapter for Intel Celeron Pentium II III and Pentium II III Xeon Processors Emulation and Analysis Solutions for Product Overview 5966 3442E ARM7 and ARM9 Microprocessors 124 Agilent Technologies Test and Measurement Support Services and Assistance Agilent Technologies aims to maximize th

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