Altera UG-01080 User guide
Contents
1. July 2009 Rev 0 06 Page 11 of 31 Once the FPGA has been programmed the SDALTEVK can be evaluated using the push button interface on the Cyclone Ill main board However if the terminal interface is desired for evaluation run the Nios II terminal program called nios2 terminal exe This program can be found in the bin folder of the Nios II root directory for example C altera 80 nios2eds bin nios2 terminal exe If the software loads correctly a terminal window will appear with a greeting message as shown below Shortcut Eo nios2 terminal exe nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB 1 device 1 instance nios2 terminal Use the IDE stop button or Ctrl C to terminate Unexpected Command Main Menu 1 I2G Read I2G Write Register Read Register Write I2G Bus Scan Put System in Standalone Mode Put System in Analogue Sync TPG Mode Put System in Analogue Sync Reclock Mode Put System in Analogue Sync alternate TPG Mode Put System in SDI Passthrough Mode Selected Mode 2 3 4 5 6 8 9 A L Figure 9 Nios Terminal Main Menu July 2009 Rev 0 06 Page 12 of 31 4 Evaluating Hardware The EVK is designed for flexible and accurate evaluation of LMH0340 and LMH0341 Evaluation can be performed using internal or external stimuli There is an internal pattern generator implemented in the FPGA that will generate test patterns t2. Part Numbers30 July 2009 Rev 0 06 Page 2 of 31 1 Overview The SDALTEVK enables rapid evaluation of the LMH0340 0341 serializer and deserializer in Serial Digital Interface SDI applications Other National devices also highlighted on this board are shown in Table 1 Table 1 National Semiconductor Devices on the SDALTEVK Device Quantity Description Function Reference Designator LMH0340 2 SD HD and 3G SDI serializer 4 SDI Serializer U1 U6 cable driver LMH0341 1 SD HD and 3G SDI deserializer SDI Deserializer U11 LMH0344 1 SD HD and 3G cable equalizer SDI Equalizer U13 LMH1981 1 Multi Format Video Sync Optional Clock U3 Separator Source LMH1982 1 Multi Rate Video Clock Optional Clock 09 Generator with Genlock Source DS90CP22 1 2x2 LVDS Cross Point Switch Clock Multiplexer 07 05901028 1 Dual LVDS to CMOS Optional Clock 05 Output DS90LV031 1 Quad 3V CMOS to LVDS Line Optional Clock 02 Driver Source LP3878 ADJ 1 Micropower 800mA Low Noise 2 5V Regulator U10 Adjustable Voltage Regulator LM20242 1 2A PowerWise Adjustable 3 3V Regulator U12 Frequency Synchronous Buck Regulator Examples of firmware are provided for the Standard Definition SMPTE 259M SD SDI interface the High Definition SMPTE 292M HD SDI interface and the 3G SMPTE 424M 3G SDI interface The video standards supported by the example firmware are shown in Table 2 Table 2
3. Hex Address Name Description Bits Bit Description 01 RESET STATUS Status bits of various 15 4 Reserved system resets 3 Deserializer Lock 2 Serializer Lock 1 CPU_RST_N 0 CPU_RST 02 RESET Control Reset Signals 15 0 Reserved CONTROL 5 1 3 Rx Video Registers Hex Address Name Description Bits Bit Description 03 RX VID STATUS Status bits of Rx video 15 4 Reserved 3 Vid Reset Flag Indicates that video reset has been asserted 2 Deser Flag Indicates that the deserializer lock has toggled 1 Descram Flag Indicates that the descrambler lock has toggled 0 Descram Locked Indicates that the descrambler is locked onto incoming video 04 RX VID STD Detected Video Standard 15 13 Reserved 12 SMPTE 352 Packet Detected 11 Reserved 10 8 Frequency detected 000 0 SD 270Mbps 001 1 HD 1 485 1 001 Gbps 010 2 HD 1 485 Gbps 011 3 HD 2 97 1 001 Gbps 100 4 HD 2 97 Gbps July 2009 Rev 0 06 Page 22 of 31 Hex Address Name Description Bit Description 7 4 Reserved 3 0 Format Detected 0000 0 PAL 150 0001 1 NTSC 159 0010 2 P720 50 0011 3 P720 60 0100 4 51080 24 0101 5 11080 50 0110 6 11080 60 0111 7 P1080 24 1000 8 P1080 25 1001 9 P1080 30 1010 A P1080 50 1011 B P1080 60 05 CRC STATUS CRC Error Check 15 Reserved 14 0 CRC Error Count 06 CRC CONTROL CRC Check Control 15 3 Reserved 2 Select Holdover Mode 1 Reset Status flags 0 Reset CRC Error Count 07 EDH STA
4. Video Standards Supported by Firmware Rate Video Standard SD NTSC PAL HD 720p50 720 59 720 60 1080523 98 1080524 1080150 1080159 1080160 1080 29 97 1080 30 3G 1080p50 1080p59 9 1080p60 A user interface allows for managing the FPGA firmware functions and the LMH0340 0341 1982 device registers 2 Evaluation Kit SDALTEVK Contents The SDALTEVK contains the following parts e SDALTEVK HSMC SDI ADAPTER Board e Screws standoffs and spacers for mounting the EVK to the Cyclone Ill Development Board July 2009 Rev 0 06 Page 3 of 31 The following is required to complete the evaluation kit e Altera Cyclone Ill Development Kit Altera Part Number DK DEV 3C120N National Semiconductor SDI compiled sof file from http www national com sdaltevk o Triple Rate Standalone mode with multiple format selection o Triple Rate pass thru mode with format detection o Pattern selection o Gen Lock function supported o Register programming supported Altera compiled sof file from ftp ftp altera com outgoing National SerDes an535 1 0 zip o Triple Rate pass thru mode e Quartus II 8 0 or newer http www altera com products e Nios EDS 8 0 http www altera com products e Oygwin from http www cygwin com e SDI cables e PC July 2009 Rev 0 06 Page 4 of 31 Hardware Setup The SDALTEVK printed circuit board is designed to interface with the HSMC connector on the Cyclone Development Boa
5. CJ Start Project ogra Version 8 0 amp MegaWizard Plug In Manager SOPC Builder View Quartus II Tcl Scripts Information Customize Documentation Options License Setup 5 System Processing Extralnfo Info Warning Critical Warning Error Suppressed Flag iB Message Location z Locate Open a Programmer window 9898 Idle meme Figure 7 Quartus Main Screen July 2009 Rev 0 06 Page 10 of 31 This will bring up the programming window shown below Click on the Hardware Setup button select the USB Blaster and click Close Use the Add File button to select the appropriate bit image to program the FPGA Make sure that the Program Configure box is checked and that the Mode menu has JTAG selected Press the Start button to program the FPGA Once the progress bar reaches 10095 the SDALTEVK is ready to use W Quartus II Chain1 cdf File Edit Processing Tools Window d Hardware Setup USB Blaster USB 0 Mode JTAG Progress Enable real time ISP to allow background programming for MAX II devices e pe gi ci EP3C120F780 OOBFFE64 FFFFFFFF Examine Auto Detect X Delet Add File B 2 Add Device po P Down For Help press F1 Figure 8 Quartus Programming Screen
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7. Install the Quartus 8 0 Software Execute the Quartus II 8 0 software installation program The program is called 80 quartus windows exe This will load the driver files onto the PC e Follow the install instructions prompted by the Quartus install daemon Install the Nios Il EDS 8 0 Software Execute the Nios EDS installation program The program is called 80 nios2eds windows exe e Follow the install instructions prompted by the Nios II install daemon The software installation is complete July 2009 Rev 0 06 Page 9 of 31 3 2 Startup Make sure all the software has been installed and the hardware is powered on and connected to the PC Run Quartus II by either by using the path C altera 80 quartus bin quartus exe or selecting it from the altera folder in the start menu Once the software has loaded go to the Tools menu and select Programmer Quartus II File Edit View Project Assignments Processing Run EDA Simulation Tool eue he gt le Run EDA Timing Analysis Tool re Launch Design Space Explorer o TimeQuest Timing Analyzer Advisors e Chip Planner Floorplan and Chip Editor Design Partition Planner Netlist Viewers 2 AAN CI SignalTap II Logic Analyzer Hierarchy B Files J Design Units In System Memory Content Editor TES Logic Analyzer Interface Editor 8 Flow Fat Design Sign ins 2 n
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9. vC327 y 47 m C334 T6345 d 335 ms c336 1 347 mn C349 C346 e we ee 348 CEES Riaz pa C354 p 0350 1 C361 4344 M gt gt gt one Y ca gt og DOG 000 atc OG O0006G OUT 29 C315 CITA R193 C387 49 Iudae C38 tn TS ELE lt 10677 19 Figure 5 Photograph of the back of the Cyclone III board showing location of the 100 Ohm Resistors July 2009 Rev 0 06 Page 7 of 31 2 3 SDALTEVK Board Description The HSMC SDI ADAPTER board features the 5 1 LMH0340 serializer IC with integrated cable driver the 1 5 LMH0344 deserializer IC and the LMH0344 adaptive cable equalizer IC all highlighted in orange These devices support SD HD or 3G SDI interfaces across 75 ohm coaxial cable which can interface with the board via BNC connectors J3 J8 J10 or J13 For added testing flexibility the additional components shown in blue allow for several different clocking schemes All of the clocking schemes are controlled by the DS90CP22 which is used to multiplex the various clock sources to the FPGA The LMH1981 receives analog video via BNC connector J2 and provides the HSYNC and VSYNC to the LMH1982 for clock generation The LMH1982 can also generate a clock based on a local 27 MHz oscillator By using the DS90LV031A an external clock can be applied to the card at SMA connector In order to observe the quality of the clock provided to the FPGA
10. which are then used to clock the LMH0340 serializer and provide an SDI test signal output which is genlocked to the Analog input cx Shortcut to nios2 terminal exe Configuring Genlock for PLL 1 NTSC 159 Waiting for Ref Valid Clock Valid Waiting for TOF Pulse Reducing PLL Charge Pumps Waiting a few seconds to reduce the ICP1 Bandwidth Main Menu 12 Read I2C Write Register Read Register Write I2C Bus Scan Put System in Standalone Mode Put System in Analogue Sync TPG Mode Put System in Analogue Sync Reclock Mode Put System in Analogue Sync alternate TPG Mode Put System in SDI Passthrough Mode Selected Mode Put System in Analogue Sync TPG Mode E 1 2 3 4 5 2 7 8 9 A a st Figure 14 Analog Sync TPG Mode 4 2 3 Analog Sync Reclock Mode In Analog Sync Reclock Mode you provide both an analog Sync input as in the Analog Sync TPG mode and an SDI input which is genlocked to the Analog Sync input The timing information is extracted from the analog signal and new serial clock is generated using the LMH1982 and this clock is used to reclock the data received through the SDI input port 4 2 4 Analog Sync alternate TPG Mode In Analog Sync Alternate TPG Mode the system operates similar manner to the Analog Sync TPG mode except that the output video format need not be the same as the analog sync input For example you could use an analog sync from an NTSC 525
11. ED 5 LED 6 LED 7 LED 8 Off Off Off Blink Off Indicates Current Mode Figure 22 Frequency Menu Push Button Functions and Board Status LED Indications Format Clock Frequency Number Active 13 5 74 47 MHz 74 25 MHz 148 35 MHz 148 5 Lines SD 000 HD 001 HD 010 3G 011 MHz 3G 100 0 0000 525 PAL 1 0001 486 2 0010 720 720 50 3 0011 720 P 720P59 94 720P60 4 0100 1080 S 1080523 9 1080524 8 5 0101 1080 1080150 6 0110 1080 1080159 94 1080160 7 0111 1080 1080 23 9 1080P24 8 8 1000 1080 P 1080P25 9 1001 1080 P 1080P29 9 1080P30 7 A 1010 1080 P 1080P50 B 1011 1080 P 1080P59 94 1080P60 Figure 23 Video Format and Clock Frequency Table Depending on the format the frequency specified in Figure 22 can refer to either the field or frame rate For interlaced images it is the field rate and for progressive and segmented frame it is the frame rate 5 1 FPGA Register Map This section describes the registers associated with the SDI Video Firmware Registers can be either status or control and are read or write respectively The registers are grouped into several main sections Miscellaneous Reset Rx Video Datapath Clocking Timing gr do m July 2009 Rev 0 06 Page 21 of 31 5 1 1 Miscellaneous Registers Hex Address Name Description Bits Bit Description 00 IPT ID ID Code 1234 Hex 15 0 ID Code 5 1 2 Reset Registers
12. Luma Pulse amp Bar July 2009 Frequency Swee Matrix Pathological Y C Full Range Ramp SMPTE RP219 Color Bars Rev 0 06 Page 29 of 31 6 Additional SDALTEVK documentation can be found on the EVK website 7 Schematics BOMs and Data Sheets All of the schematics BOMs and data sheets for the SDALTEVK can be found on the EVK website 8 Reference FPGA IP The reference FPGA IP source code and documentation can be found on EVK website 9 Up to Date Information For up to date information check this URL http www national com sdaltevk 10 Part Numbers Cyclone Ill Development Board DK DEV 3C120N http www altera com products devkits altera kit cyc3 html LMH0340 LMH0341 Evaluation Kit SDALTEVK July 2009 Rev 0 06 Page 30 of 31 Release 0 00 0 01 0 02 0 03 0 04 0 05 0 06 July 2009 Revision History Date s Revisions 58 19 2008 M Wolfe Creation 8 19 2008 Se Wolfe 1 draft 8 25 2008 Unger Updated able headings Column widths 8 28 2008 Unger Put revision history at the end Change font of the TOC to Ariel Inserted termination resistor instructions Minor wording changes on Table 1 9 02 2008 N Unger Updated Altera Part Number to DK DEV 3C120N 9 03 2008 Unger Recovered File Changed date format in the revision history 07 09 2009 Sauerwald Updated for December 2008 IP release Rev 0 06 Page 31 of 31 IMPORTANT N
13. National Semiconductor The Sight amp Sound of Information User Guide SDALTEVK HSMC SDI ADAPTER BOARD 9 Jul 09 Version 0 06 SDI Development Kit using National Semiconductor s LMH0340 serializer and LMH0341 deserializer July 2009 Rev 0 06 Page 1 of 31 1 Overview3 2 Evaluation Kit SDALTEVK Contents 3 3 Hardware Setup 5 3 1 CYCLONE DEVELOPMENT BOARD MAIN BOARD en 6 3 2 SDALTEVK BOARD 00 es 8 4 80ftware Setup 9 4 1 INSTALLATION ARAR 9 LEE IU I e 10 5 Evaluating Hardware 13 5 1 TEST 13 5 1 1 Standalone Video Generator Tests 13 5 1 2 Le Tel ore dE Lr cS 14 5 1 3 Video Pass through 200 202 0 2 2 40100000140065440 isse sitne einen 15 5 2 TERMINAL BASED SD HD 3G SDI EVALUATION ccce mene nennen nennen nennen nnne nennen enne nnns 15 5 2 1 T 16 5 212 Pass through Mode eerie e Disa 17 5 2 8 Genlocked eene nnn nennen Error Bookmark no
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15. TUS 1 EDH Error Check Status 15 Reserved Reg 14 10 Full Field error flags 9 5 Active Picture error flags 4 0 ANC flags 08 EDH STATUS 2 EDH Error Check Status 15 EDH Present Reg 2 14 12 EDH Detection Count indicates intermittent EDH 11 8 Full Frame CRC error count 7 4 Active Picture CRC error count 3 Full Field CRC Error detected 2 Active Picture CRC Error detected 1 Full Field CRC valid 0 Active Picture CRC valid July 2009 Rev 0 06 Page 23 of 31 Hex Address Name Description Bits Bit Description 09 EDHAP COUNT Extended Count of EDH 15 0 16 bit Active Picture EDH error Errors count 0A EDH FF COUNT Extended Count of EDH 15 0 16 bit Full Frame EDH error Errors count 0B AUDIO IN Input Audio Over SDI 15 4 Reserved STATUS Status 3 Group 4 detected 2 Group 3 detected 1 Group 2 detected 0 Group 1 detected 0C SMPTES35234 Extracted SMPTE352 Bytes 15 0 SMPTES52 Bytes 4 and 3 3 4 00 5 5212 Extracted SMPTE352 Bytes 15 0 SMPTE352 Bytes 2 and 1 1 2 0 AUDIO IN 125 Output Control 15 1 Reserved CONTROL 0 Enable 125 Output 5 1 4 Datapath Registers Hex Address Name Description Bit Description 10 DP STATUS Datapath Status Register 15 0 Reserved 11 DP CONTROL 15 Data Pat Bypass 14 7 Reserved 6 Insert CRC EDH Errors on output 5 Insert EDH Packets on output 4 Insert SMPTE352 Packets on output 3 Insert audio on output 2 Res
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17. Valid Range Ramp 11 3 YUV Full Range Ramp 3 Reserved 2 0 Pattern Select 000 0 100 Color Bars July 2009 Rev 0 06 Page 25 of 31 Hex Address Name Description Bits Bit Description 001 1 Sweep not implemented 010 2 Calculated Patterns 011 3 Pulse Bar 100 4 RP219 Pattern 101 5 SMPTE Bars Others 100 Color Bars 1B SMPTE 352 Allows bytes 3 and 4 of the 15 8 Byte 4 INSERT SMPTES52 packet to be set CONTROL 7 0 Byte 3 1C LINE PATTERN 16 MSB for line pattern 15 0 Update Value UPDATE 1 update 1D LINE PATTERN 16 LSB for line pattern 15 0 Update Value UPDATE 2 update 1E LINE PATTERN Adress and write enable for 15 Write Enable UPDATE ADDR pattern update 14 11 Reserved 10 0 Update adress 5 1 5 Clocking Hex Address Name Description Bits Bit Description 20 CLOCK STATUS Status of ALtera PLLs 15 3 Reserved ALTERA 2 Active clock specified whether the receive 0 or PLL 1 clock is for transmission 1 Tx PLL Locked 0 Rx PLL Locked 21 CLOCK Control Altera Clock 15 Select PLL 1 or Rx 0 Clock CONTROL selection ALTERA 14 0 Reserved 5 1 6 Video Timing Hex Address Name Description Bits Bit Description 23 CONTROL Control Genlock Mode 15 2 Reserved GENLOCK 1 0 Select System Mode 00 0 Use Received Video Timing 01 1 Use Genlock timing 10 2 Freerun User specified timing 11 3 Use Genlock timing with user specified format 24 GENLOCK Status of Gunlock Interface 15 P
18. daughter board is connected to the main board through the high speed mezzanine connector HSMC J8 This connector provides power control bus and data bus The main board communicates to a PC through a USB cable 11 AULIE IN ERE a Figure 3 Cyclone III Development Board 2 2 Cyclone Development Board Termination Resistors The Altera Cyclone III device does not have any internal termination on the receive LVDS 1 Termination resistors must be added to the Cyclone Ill board The terminations resistors must be placed as close to the FPGA s pin as possible The 3C120 host board has the layout footprints for the termination resistors Eleven 100 Ohm resistors in 0402 package size are required to install onto the host board The resistors are located on the bottom side of the board They are between the FPGA and the HSMC port A connector Figures 4 and 5 show the schematic and board location of the LVDS termination resistors July 2009 Rev 0 06 Page 6 of 31 R16 DNI HSMA RX D P8 R16 DNI HSMA RX D Pg R16 DNI HSMA RX D P10 HSMA IN P1 R185 R15 DNI HSMA RX D P11 HSMA 1 DNI R15 DNI HSMA RX D P12 HSMA CLK IN P2 R15 DNI HSMA RX D R147 LS ASMARXU NTT R15 DNI HSMA RX D P14 HSMA CLK IN N2 DNI R15 DNI HSMA RX D P15 R1 DNI HSMA RX D P16 Figure 4 Resistors on HSCM port A e C289 mu cos E C290 C291 297 e C298 LAE E C305 C314 p ERC3IS E z em C306 316 ome AEST
19. erved 1 Disable TPG Output Received video 0 Reserved 12 DP FORMAT Datapath Format Control 15 Force Format CONTROL 14 4 Reserved 3 0 Select Video Format see RX VID STD for values 13 DP FREQ Datapath Frequency Control 15 3 Reserved July 2009 Rev 0 06 Page 24 of 31 Hex Address Name Description Bits Bit Description CONTROL 2 0 Selected Frequency see RX VID FREQ for values 14 DP AUDIO OUT Control Audio Insertion 15 8 AFN Audio Frame Count Max CONTROL Module 7 4 Audio control packet rate 3 Reserved 2 Select internal tone generator 0 or 125 input 1 1 0 Select output audio group 15 AUDIO OUT Audio Output Status 15 0 Reserved STATUS 16 AUDIO OUT INCR Controls Increment Rate for 15 8 Channel 1 Frequency 1 Internal Tone Generator 7 0 Channel 2 Frequency 17 AUDIO OUT INCR Controls Increment Rate for 15 8 Channel 3 Frequency 2 Internal Tone Generator 7 0 Channel 4 Frequency 18 AUDIO OUT CSB Controls Audio CSB 15 8 Channel Status Block CRC 1 7 0 Channel Status Block Byte 2 19 AUDIO OUT CSB Controls Audio CSB 15 8 Channel Status Block Byte 1 2 7 0 Channel Status Block Byte 0 1A TEST PATTERN Select Output test Pattern 15 Reserved CONTROL 14 RP219 Pattern Select 3A 0 3B 1 13 12 RP219 Part 2 Pattern Select 00 0 2A 01 1 2B 10 2 Y Valid Range Ramp 11 3 YUV Full Range Ramp 11 6 Reserved 5 4 Select Calculate Patterns 00 0 Black 01 1 Pathological 10 2 Y
20. line 59 94 frame rate signal and generate an SDI output which is an HD 720P50 output July 2009 Rev 0 06 Page 17 of 31 4 2 5 Pass Through Mode Before selecting Pass through Mode from the main menu apply an SD HD or 3G SDI video signal from an external source to the SDALTEVK When Pass through Mode is selected from the main menu a message will appear notifying if an input signal of a supported format is detected and return to the main menu Shortcut to nios2 terminal exe nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB 1 device 1 instance nios2 terminal lt Use the IDE stop button or Ctrl C to terminate Unexpected Command Main Menu 1 I2C Read I2G Write Register Read Register Write I2G Bus Scan Put System in Standalone Mode Put System in Analogue Sync TPG Mode Put System in Analogue Sync Reclock Mode Put System in Analogue Sunc alternate TPG Mode Put System in SDI Passthrough Mode Selected Mode Put System in SDI Passthrough Mode E 2 3 E 5 2 ie 8 9 A A Figure 15 Pass through Mode Screen July 2009 Rev 0 06 Page 18 of 31 4 3 Push Button Based SD HD 3G SDI Evaluation The EVK can be configured for evaluation by using the push buttons on the Cyclone III main board only The push button interface allows the EVK to be configured in the same modes as the terminal interface option However only the Nios II terminal in
21. lock No reference or invalid reference Passthrough Input video not present or unrecognized 4 3 3 Datapath Menu This menu will be available in a future release If this menu is selected the LEDs will flash twice and the system will return to the main menu 4 3 4 Video Format Menu The Video Format Menu configures the push buttons to navigate through the supported video formats Users must select a video format with a compatible frequency in order for the system to be configured If the system is in Standalone Mode and a valid combination is selected the LEDs will flash once to indicate successful configuration In other modes the video format and frequency settings are ignored See the table below for the supported video formats and clock frequencies PBO 1 PB2 PB3 Cancel OK Up Down LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8 Off Off Blink Off Off Indicates Current Mode July 2009 Rev 0 06 Page 20 of 31 5 This menu configures the push buttons to cycle through supported clock frequencies Users must select a video format with a compatible frequency in order for the system to be configured If the system is in Standalone Mode and a valid combination is selected the LEDs will flash once to indicate successful configuration In other mode the video format and frequency settings are ignored PBO 1 PB2 PB3 Cancel OK Up Down LED 1 LED 2 LED 3 LED 4 L
22. nu a list of available video formats will appear To select a video format enter the two digit code that appears directly to the left of the format title Once a format is selected the terminal will return to the main menu and the SDALTEVK will then be operating sending a test pattern in the specified SDI video format Once the two digit code is selected the Selected format will be displayed followed by the Main Menu After the main menu a reminder of what mode the system is currently in will be shown cv Shortcut to nios2 terminal exe PAL P 728 1C 23 98Hz P 7208 2D 25Hz P 720 22 5 Hz 5 1888 14 23 98Hz I 1686 25 5 Hz P 18088 17 23 98Hz P 1686 28 25 Hz P 1888 44 50 Hz 1CSelected Format 726 Main Menu I2C Read I2C Write Register Read Register Write I2G Bus Scan Put System in Standalone Mode Put System in finalogue Sync TPG Mode Put System in Analogue Sync Reclock Mode Put System in Analogue Sync alternate TPG Put System in SDI Passthrough Mode Selected Mode Put System in Standalone Mode E 1 2 3 4 E 6 7 8 9 A a 6 Figure 13 Video Format Menu July 2009 Rev 0 06 Page 16 of 31 4 2 2 Analog Sync TPG mode In Analog Sync TPG mode the user provides an analog sync signal to the analog sync input on the evaluation board the BNC connector labeled Analog IN The LMH1981 extracts the sync information from this signal and passes it to the LMH1982 which generates video clocks for the FPGA
23. o verify signal transmission and signal integrity The pattern generator can generate various types of SD HD and 3G SDI static video patterns 4 1 Test Setups 4 1 1 Standalone Video Generator Tests In Standalone mode the system performance can be determined by the internal pattern generator This is done by connecting the serializer output TX1 on J8 to the deserializer input RX on J13 The loop through output of the deserializer can be connected to external test equipment such as a WFM700 or an oscilloscope Figure 10 Loop back Test Setup July 2009 Rev 0 06 Page 13 of 31 4 1 2 Genlock Tests When one of the genlocked modes is selected the system is configured to use an analog sync input to generate genlocked video The analog reference signal is applied to the EVK through BNC connector J2 If no analog reference is present the LMH1982 has been configured to automatically switch to the on board oscillator TELI L CEIL ER 190401304 Figure 11 Genlock Test Setup July 2009 Rev 0 06 Page 14 of 31 4 1 3 Video Pass through Tests In Pass through Mode the EVK uses the clock recovered by the LMH0341 from the SDI input as the reference clock The video data is then routed through the FPGA to the LMH0340 for transmission To configure the EVK for Pass through Mode connect the source generator to J13 of the deserializer and connect the terminating device to the serializer BNC connector J8 Refer to the diagram below The loop through d
24. rds Power control bus and LVDS bus signals are supplied to the daughter board through the HSMC connector The Cyclone Ill FPGA provides the SD HD 3G SDI and general purpose stacks as well as the control interface to a PC through a USB cable This evaluation system allows inexpensive FPGAs to deliver up to 3 Gbps on a coax cable SDALTEVK Cyclone 111 Host Development Board SDI Out Reclocked Loop Through HEG j Qu OO som y Salsa LMHO341 O e Adaptive 36 501 External Equalizer Deserializer Clock In HH H VSYNC SD Clock pgsocP22 OG pU PS 30 o Sync Clock Separator Generator LVDS Tx 1 Data 5 bit 99 88 TT x 1 Data SDI Out 1 OO OO wp Serializer e and Driver LVDS Tx 1 Clock OO OG i OO OO SDI out2 re LVDS Tx 2 Data 5 bit 30 50 G Serializer e e sun LVDS Tx 2 Clock 00 OO OO LM20242 LP3878 4 PowerWise GF Config Switches Status LEDs LDO Regulator Ol Figure 1 Evaluation Kit Block Diagram B 46v Power fl UsB interface Cyclone Development Board Video SDI Clock External OUT Figure 2 Evaluation Kit Connections July 2009 Rev 0 06 Page 5 of 31 2 1 Cyclone Ill Development Board Main Board Description The main board has a Cyclone III FPGA The FPGA provides the SD HD 3G SDI and general purpose stacks as well as the control interfaces through the supplied example firmware The
25. river can also be connected to the terminating device via BNC connector J10 1900130 Figure 12 Pass through Test Setup 4 2 Terminal Based SD HD 3G SDI Evaluation Below the terminal greeting message is the main menu The table below gives a brief description of the main menu options Table 3 Terminal Menu Options Menu Option Name Function 1 2 Read Read from a device register 2 2 Write Write to a device register 3 Register Read Read from an FPGA register 4 Register Write Write to an FPGA register 5 2 Bus Scan Returns 7 bit address of all devices on the serial control bus 6 Put System in Configures system for Standalone Mode Accesses format select Standalone Mode menu 7 Put System in Analog Generates clock from Analog sync input and uses this to drive Test Sync TPG mode Pattern Generator 8 Put System in Analog When supplied with an Analog Sync and a synchronous SDI input Sync Reclock Mode the system uses the gunlock feature of the LMH1982 to reclock the SDI video with a clock derived from the analog input 9 Put System in Analog Generates Test patterns synchronized to the SDI input Sync Alternate TPG mode A SDI Passthrough SDI video is received by the LMH0341 analysed and retransmitted Mode using the clock recovered from the LMH0341 July 2009 Rev 0 06 Page 15 of 31 4 2 1 Standalone Mode If Standalone Mode is selected from the main me
26. rogressive video on reference STATUS 14 12 SD HD 3G Format July 2009 Rev 0 06 Page 26 of 31 Address Name Description Bits 11 10 6 4 3 0 Bit Description Reserved Genlock reference present Genlock No Lock Genlock No Ref Reserved Genlock frequency as per RX VID FREQ Genlock format as per RX VID STD 25 VFORMAT STATUS Looks for Matching VFORMAT Sequences from the LMH1981 and Decodes Them 14 12 Reserved Decoded format type 000 0 Unknown 0011 PAL 010 2 NTSC 011 3 576P 100 4 480P 101 5 720P 110 6 10801 111 7 1080P Reserved Vformat received from LMH1981 26 LINE TIME COUNT Used to Determine Format See Genlock if module for details Line time count 16 MSB 27 STATUS GENFORMAT Format Used to Drive Timing Generator Reserved Frequency selected as per RX VID FREQ Reserved Format selected as per RX VID STD 28 STATUS TIMING Status of Timing Generator Input present Reserved Sync to input timing Reserved July 2009 Rev 0 06 Page 27 of 31 Hex Address Name Description Bits Bit Description 7 0 Counts when timing is resynchronized July 2009 Rev 0 06 Page 28 of 31 5 2 Supported Test Patterns The following test patterns are available from the SDI firmware in all SD HD and 3G formats 10096 Color Bars Black Luma Ramp SMPTE 75 Color Bars
27. t defined 5 3 PUSH BUTTON BASED SD HD 3G SDI EVALUATION c cccccccscsessesececececeessasececeeseesceesesaeseceeceseneseaaeseseeseeenea 19 5 3 1 Push Button Main Menu iiie eren eene anat nn an 19 532 System MOOG ei ian Eae p aprende e uen gae e Ln dud eee 20 5 3 3 Datapath ITE a aaa ataa a a 20 5 3 4 20 5 3 5 Se 21 4 FPGA REGISTER MAP nude Ra da D Ru ad 21 54 11 Miscellaneous 5 5 22 042 Reset Heglsters gunnar Dea oad wa ted cane iaa aa den ie er DR ta a fas ee et 22 5 43 RX Video Registers sites a sss 22 5 44 Registers 24 PONE 0 rie 26 5 4 6 Video TIMING 26 5 5 SUPPORTED TEST PATTERNS 29 6 Documentation 30 7 Schematics BOMs and Data Sheets30 8 Reference FPGAIP 30 9 Up to Date Information 30 10
28. terface allows for device and FPGA register access i Development Board Figure 16 LED and Push Button Locations 4 3 1 Push Button Main Menu After the FPGA has been programmed the push buttons default to the main menu options While in the main menu LED 1 will blink LED 6 7 or 8 will illuminate to indicate the current configuration of the EVK PBO PB 1 PB2 PB3 System Mode DP Settings Video Format Video Frequency LED 1 LED 2 LED 3 LED 4 LED5 LED6 LED 7 LED 8 Blink Off Off Off Off Genlock Passthroug Standalone h Figure 19 Main Menu Push Button Functions and Board Status LED Indications July 2009 Rev 0 06 Page 19 of 31 4 3 2 System Mode The System Mode menu contains the various configuration options for the EVK Use this menu to configure the EVK into one of the 3 previously discussed modes of operations PBO 1 PB2 PB3 Cancel Genlock Passthrough Standalone LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8 Off Blink Off Off Off Indicates Current Mode Once mode has been selected all of the LEDs will flash and the system will return to the main menu successful configuration is indicated by a single flash while two flashes indicate a failure If a failure occurs refer to the table below for the most common causes Configuration Typical Cause of Failure Standalone Incorrect format specified or mismatch between frequency and video format Gen
29. the clock can be routed to the DS90LV028A which will drive a CMOS clock out of SMA connector J5 Power is provided to the board via two separate power rails that travel across the HSMC connector from the Cyclone host board The Powerwise LM20242 adjustable frequency synchronous buck regulator supplies the 3 3V power for the evaluation card by using the 12V rail from the host board The LP3878ADJ low noise regulator uses the 3V power of the host board to supply the 2 5V power to the evaluation card u3a1dvOv IOS 2OWSH E 1012 2 19040130 Figure6 SDALTEVK July 2009 Rev 0 06 Page 8 of 31 3 Software Setup 3 1 Installation Make sure the Altera hardware is not connected to the PC The following installation instructions are for the Windows XP Operating System Quartus II 8 0 or newer is required to properly operate the SDALTEVK If the terminal interface is desired then Nios II EDS 8 0 or newer must also be installed on the PC If an older version of either Quartus II or Nios EDS is already installed make sure that it is updated before attempting to use the SDALTEVK If necessary please see http www altera com products to download the latest software In order to use the Nios II terminal interface Cygwin must be installed on the PC Visit http www cygwin com to download the latest version of Cygwin for free Make sure that the file cygwin1 dll is installed to the path C altera 80 nios2eds bin
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