PS4900/05 Backplane User Manual
Contents
1. Pin 1 Connects 3 3V on an ATX power supply to the 3 3V plane of the backplane Pin8 1 Connects PW OK on an ATX power supply to the FAL signal on the CompactPCI Host slot Pin9 1 Connects 5VSB on an ATX power supply to the DEG signal on the CompactPCI Host slot 30 PCAONN NA CPSR TTear Mannal Pin 14 1 Connects PS ON on an ATX power supply to the INHIBIT signal on the Control header Pin 16 1 Connects GND on an ATX power supply to the GND plane of the backplane Pin 18 1 Connects 5V on an ATX power supply to the 12V plane of the backplane through a jumper Pin 19 1 Connects 5V on an ATX power supply to the 5V plane of the backplane NOTE These signals are not standard ATX signals INH DEG and FAL are connected directly to the CompactPCI 8 power supply connectors Please see the CompactPCI 8 specification for a description of these signals 4 7 Regulatory and safety The PS4900 05 has been designed to comply with the following standards e EN 60950 UL 1950 A clearance of 2 5mm has been provided between AC voltages and chassis ground on all external layers A clearance of 5mm has been provided between AC and secondary voltages on all internal layers A clearance of 0 4mm has been provided between primary and secondary voltages on all internal layers 312. PSENDx l16 am s ABIOShroud SHx3 Em paes x an AMP 40635 ABZ Smo SHX Em pas xx CU r Basi j x iie MP je lb5 SMP pm Em E32 SMP me oS SIMPiSuwu Emi SIMPZShoud SHI 2 Em pas S Short Tail LT Long Tail HS Hot Swap LC Low Current 34 PANN NA CPSR TTear Mannal 6 Appendix B 6 1 CompactPCI Host slot P1 and P2 pinout Table 27 Host Slot P1 amp P2 Pinout N N a 2 2 2 2 2 2 2 nm z oO z oO Oo N A N R N N N N A olumn 2 a B c D E F GA4 z iw Zz iw z iw Oj O O O O OJ O OC OC O O OC O O OC O O O CLK6 CLK5 GND BRSVP2A18 BRSVP2A17 BRSVP2A16 BRSVP2A15 AD 35 AD 38 AD 42 AD 45 AD 49 AD 52 AD 56 AD 59 AD 63 C BE 5 VIO CLK4 CLK2 Zz Zz z Zz z D D AD 34 D AD 41 D AD 48 GND AD 55 D AD 62 GND BRSVP2B4 D CLK3 REQ1 GNT1 REQ2 GN D BRSVP2B18 D BRSVP2B16 Oo O Zz iw O o OJO z Oo 5 AD 1 3 3V AD 7 3 3V lt ENUM AD O ACK64 REQ64 5V AD 4 G D AD 9 to A 2 2 2 2 2 2 2 2 2o O z O o OJO w OJO O w oio z w z Oo z
3. 12V b B IPMB SDA TEMP4 4 PEMIINOK TACH3 PWM3 TEMP3 TEMP 3 3 TACH2 PWM2 TEMP2 TEMP 2 PEM20UTOK E enanox 2 TACHI PWM1 TEMP1 TEMP 1 PEM1OUTOK cmMRS __ cnn B IPMB SCL A IPMB SCL PWM4 12V a C IPMB SCL x C PMP IPMB PWR IPMB PWR HG IPMB PWR BEER ER Long Pins Medium Pins Short Pins 29 4 5 1 Configuring for use without an Alarm Card When an alarm card is not installed in slot 17 jumper shunts must be loaded in headers JP4 JP5 and JP6 If an alarm card is installed make sure all jumpers are removed The factory default configuration has these jumpers loaded Table 23 displays the allocation of signals on JP4 JP5 and JP6 The signals next to SBC are the signals that will be connected to if the shunt is installed Note that shunts are only required if the corresponding power supply connector is present Table 23 Power Signal Strapping Pus IN Sur INH2 FAL2N DEG2N sc INH amp FALN DEGN 4 6 Miscellaneous connectors 4 6 1 ATX power connector As an option a 20 pin ATX connector can be populated This connector JP10 can be utilized to power the backplane in a lab environment or to power external devices Current to each of the pins is limited to 9 amps Table 24 displays the connector footprint and pinout E 24 ATX Connector Pinout and Oi Le NA NR sy NN 3 3V uj
4. 1 GND 2 3 4 4 2 Power status and control The PS4900 05 routes all D EG FAL and INH signals as shown in Figure 7 Three headers JP4 JP5 and JP6 are provided for O r ing and routing of the DEG and FAL signals to the system slots The INH signals route to J100 Figure 7 Power Status and Control Signal Routing 4 e DEG lt e FAL PS1 gt INH lt DEG at 9 FAL gt INH Alarm a ul Card DEG FAL PS3 INH A e IDEGK FAL PS4 gt INH Jumpers System Slots To System Slots From INH Header Table 6 Table 7 and Table 8 display the configuration of the power supply configuration headers Tabik 6 IN H H eader 15 y Kaparel Table 8 DEGN Header Pin Pia Deci 7 If the SBCs support the INH DEGN and FALN signals and there is no Alarm Card in slot 17 these shunts should be populated If the Alarm Card is populated in slot 17 these shunts must be removed 3 4 4 3 Power supply inhibit J100 can be wired to a switch on the chassis which can be utilized in Inhibiting the secondary power This will not turn off the power supplies but only their output voltages When using a PC ATX power supply the header should be shorted to turn the power s
5. 5 Appendix A 5 1 47 Pin Positronic The large contacts size 16 in positions 45 46 and 47 have a current capacity of 40A each derated to 23A for a 30 C temperature rise The large contacts size 16 in positions 1 20 have a current capacity of 28A each derated to 16 5A for a 30 C temperature rise The small contacts size 22 have a capacity of 3A nominal each T able 25 displays the pinout outline and location of the 47 pin power supply connectors Table 25 Pinout outline and location of the 47 pin Positronic Connectors as viewed from connector side of the backplane or front of rack 51 GND 20 32mm 40 NB SA 41 3V SHARE FAL Backplane Top Edge i ac ne lo LO OoOo 0 G8 O6 NC esee qp 444342 44434 O OO 4408 llooo 414039 OO O0 383738 o O O 383736 OO O 353433 DO O 353433 OO O 323130 O O O 323130 O O O 292827 OO O 292827 O O O 262524 O O O 262524 O OO 232221 232221 5V SENSE BC a OO 69 3 5 7 x E 3V SENSE T e OO OO 35 SHARE OO OO TIN SENSE E 2 IPMB SCL A DEG Backplane Power Connector Location as viewed from the front of the cardcage 43 IPMB PWR 12V SHARE CHASSIS GND 46 AC_NEUT DC AC HOT DC The mechanical location of the power supply connectors conforms to the PICMG 2 11 R1 0 Power Interface Specification 32 Dpc
6. 3 4 4 2 on page 15 Table 21 and Table 22 show pin assignments for the Alarm Slot 27 Table 21 Pinout for Alarm Slot P3 Column Rw A4 B p j E JF io m sp Nb nd nd GND s ovp sv v Ev v GND GND pe Erg 2 Q Q Z J eio Z ojo eio Z z UA Q Q Z J Q Q J uU Q 2 eio Z z eio eoo Z ziz ojojo ooo Z ojojo 7 Q Z J Q Z J B_IPMB_SCL B_IPMB_SD IPMB_PWR IPMB PWR A SMB_ALERT IPMB PWR IPMB PWR A IPMB SCL A IPMB SD IPMB PWR C IPMB SEL C IPMB SDA Q Z J Q Z J EX 4 Q Z J Q Z J eio Z z eio Q J Q 28 PCAONN NA CPSR TTear Mannal t for Alarm Slot Pl and P2 Pinou Table 22 a rarour GND amp c oun GND d To GND LPa DA LPa DB LPb DA GND LPb DB ar ae 20 ore pe o ropa s ros 5V b Lew o ee gon 58 amon o Lew 3 3V a 3 3V b GND OOOO x CU e E O Tej x LL x umm z 6 Lo FAIN GND ma GND x C C j ND i e o oe pce 1 po So o e m a KEY 12V a B ENUMN B PRSTN A PRSTN uw oo uw 12V b PEM1 INH B SMB ALERT PEM2 INH A SMB ALERT 12V b A_IPMB_SDA
7. K aparel designs and produces custom solutions Specializing in high slot count hot swap and high availability systems K aparel CompactPCI 8 solutions are rapidly becoming the choice of major telecommunications and computer manufacturers around the globe Kaparel PS4900 05 backplane Your PS4900 05 is a 6U x 84HP 21 slot 16 761 x 10 33 10 layer custom backplane designed and manufactured by K aparel Corporation as part of its standard product offering The PS4900 05 is one of Kaparel s PS49X X family of PICMG 2 16 CPSB backplanes See Section 3 Quick Start on page 9 and Section 4 Understanding Y our Backplane on page 17 for details Contact information If you have questions about your new backplane or about K aparel in general please contact us by using the following information Phone Number 519 725 0101 Fax Number 519 725 0414 Email A ddress support kaparel com Web Address www kaparel com Mailing Address Kaparel Corporation 97 Randall D rive Waterloo O ntario Canada N2V 1C5 y Kaparel 1 4 Document conventions You will see the following icons periodically throughout this manual The Warning icon cautions you against an action or treatment that could threaten the responsiveness of the K aparel equipment or the integrity of your current work e The Note icon notifies you of information that will either make a Nese procedure easier or clarify an earlier description 1 5 Background i
8. O O O lOO S o o o o S e o o o o o s s s s D Slalalajalajalaljgia ajajajajajalg 5 95 9 5 11 3 9 9 9 9 39 3 ooo ooj O O O O O O z c C lt Z O S BD BD D S d d gt d d Os s s s e e O S S S S S S g SISI N xaaAaaaasaaadaaiau c a a a a a a z a s Gl l6l alalolololololo a ZOol OlO O OJO Z Oo e lt ee ojlo Oo D ro oo a a Figure 2 PS4900 Backplane Layout icoeorz omzcoiz OOO z icoocii oo at ioo 2i Oo Oo 10198uu02 1 SOd v EF n Oo O O 10128uu02 1 M0d SOQ v o 10129uu02 JOMOd SOd y 4f o o i E EAE P29 1 1 O e s cm m r LI rJP28 11700 35 DS A M es E ER A Ves chen ee ien e A 4 gt i gt gt gt e m9 aS Sg JP2 Pups JP6 o ox a2 9 SP a5 25 aS S ES 8 5 B22 Telco Telco AB19 Long B22 Short A25 Short B22 Short A25 Short B22 Long A25 Long AB19 DC
9. Oo oio e Zz iw Zz oO z iw z UO iw ojojo iw AD 12 3 3V SERR 3 3V DEVSEL 3 3V AD 18 AD 21 C BE 3 V AD 14 AD 13 GND CBE GND IPMB SDA PERR GND ND AD 15 GND IPMB SCL GND FRAME IO AD 3 AD 2 N AD 8 M66EN C BE 0 GND GND VIO AD 11 AD 10 GND a A N STOP LOCK GND IRDY TRDY KEY AD 17 GND AD 20 AD 19 AD 23 AD 22 GND AD 26 GND AD 30 REQO BRSVP1A5 IPMB_PWR INTA TCK V 5V Short Pins AD 25 AD 24 GND AD 29 GND PCI_PRESENT BRSVP1B5 HEALTHY INTB 5 12V C BE 2 G CLK0 AD 31 GND RST GND GNTO ITP Ns M GND INTC TRST Medium Pins ND ND INTD LongPin 35 6 2 CompactPCI Peripheral slot P1 and P2 pinout Table 28 Peripheral Slot P1 amp P2 Pinout ol mn a B C D E F O z e O z o O z o O z o OJO z Z O z O z iw eo z o OJO ojo O z is O z e O z e O 5 O Irro co Qi o loo co O N eo z O z o OJO z z ojo O z o O z o O z iw RSV RSV RSV RSV RSV BRSVP2A18 BRSVP2B18 BRSVP2A17 D BRSVP2A16 EBRSVP2B16 BRSVP2A15 D AD 35 AD 34 AD 38 D AD 42 AD 41 AD 45 D AD 49 AD 48 AD 52 D AD 56 AD 55 AD 59 D AD 63 AD 62 C BE 5 GND VIO BRSVP2B4 SV D RSV V S V s jz Zz z z Zz z
10. Zz B Zz iw ND De o N o E 2 o O z n lt O Oo z lt n a lt O ojo 5 AD 1 3 3V AD 7 3 3V lt REQ64 5V N TA G iw B Zz Oo z z ziziz Oj O O O O z o O z A 2 2 2 2 2 2 2 2 o 36 O O O O ojo O is O O O O C 5 O 5 N 9 ADI8 M66EN C BE 0 N VIO AD 11 AD 10 AD 15 AD 14 AD 13 A N lo N O 5 AD 12 3 3V SERR 3 3V DEVSEL 3 3V B D ND ND GND GND ND ND G GND GND GND IPMB_SCL V D STOP LOCK IRDY TRDY D D FRAME KEY IPMB_SDA PERR G GND csepp AD 20 AD 19 AD 18 AD 21 C BE 3 AD 26 AD 30 REQ BRSVP1A5 IPMB PWR INTA C 5V Short Pins AD 17 GND IDSEL G AD 29 PCI BRSVP1B5 HEALTHY INTB 5V 12V D GND GND GND D N N RST GN V R AD 31 INTC INTD C ND ND ND ND ND 4 A 3 Tis nc fom TRST Medium Pins Long Pins Dpc lt c4onn NA CPSR TTear Mannal 6 3 CompactPCI H 110 P4 pinout PS4900 only Table 29 H 110 P4 Pinout Row z a B j c Dp E JF 5 poem SOM SOM sone sea S 24 GA4 GA3 GA2 GA1 GA0 ND ND E ERES NENNEN EIE mss p S NC ee a NP NE G N i NP o l GN we7 we7 van GND KEY
11. izi iz iziz Oj ocj ocj oc ocO O O O EE N N N N 22 N N EE D D D D D D D D N N ojo Q ND ND O z is O z o 9 O z e OJOJOO z Z Z ojojo O z e N oio z o 9 z is oio ojo 9 z o OJO ojo O z is 9 z o a 2 2 2 2 2 2 2 2 2 38 o O O O O SG D G 2 9 z o O o OJO O z oio z z ojo 9 e Oo x prd O O z o OJO z z e Oo iw N B Zz D D ND iw N N N N N N N N N N D D D D D D D D D D D D D D B PANN NA CPSR TTear Mannal 7 Glossary The following list will provide some insight into terms used throughout this document 3U A half height CompactPCI slot or card 4 HP The width of a typical single wide CompactPCI 8 slot The distance between adjacent 4 HP slots is exactly 0 800 6U A full height CompactPCI slot or card 8 HP The width of a double wide CompactPCI slot This type of slot is commonly used for power supplies and SBC modules HP This terminology refers to a unit of width commonly used within the CompactPCI mechanical specifications One HP is 0 200 J1 J5 See P1 P5 P1 P5 The CompactPCI specification uses the terminology P1 P2 P3 P4 P5 J1 J2 J3 J4 a
12. must be done before starting to utilize your backplane is to perform a thorough inspection During the course of handling shipping and assembly pins shrouds mounting screws and other items could become damaged and or loose O perating a damaged backplane could cause serious damage to the backplane and or devices that interface to it Take afew minutes to visually inspect that all of the connector pins are straight shrouds are properly seated screws are tight etc Repair any bent pins shrouds loose screws etc before proceeding If damage to the backplane is deemed too extensive call K aparel Customer Service for assistance on how to proceed 3 2 Installing your backplane in a sub rack The PS4900 05 backplane mounts into a sub rack using M2 5 screws along the rows of mounting holes situated at the top and bottom end of each slot Install one screw in each hole and tighten securely D o not install a screw in the mounting hole s marked with digital ground if a connection between chassis safety ground and digital circuit ground is not 10 3 3 3 3 1 Dpc lt c4onn NA CPSR TTear Mannal desired Mounting holes that connects to digital ground are marked with the corresponding symbol on the bottom silkscreen Figure 4 illustrates an example If you are installing the optional backplane stiffeners K aparel part 83A100002 A 01 you must locate these where shown in Figure 2 on page 8 The rear side of the backpla
13. n Ru eg on 30 4 6 1 ATX power connector l eir e de t Qe pida ipt 30 4 7 Regulatory and safety ROBA SERERE UMOR AREA EC 31 S APPENDIX n 32 5 1 47 Pin POSTONI C adem a 32 Backplane COTTIGC DO YS Su cando u a eh Renate de f TN 33 APPENDIX B 35 y gt Kaparel 6 1 CompactPCI Host slot P1 and P2 Rr a rap 35 6 2 CompactPCI Peripheral slot P1 and P2 pinoutl eee 36 6 3 CompactPCIG H 110 P4 pinout PS4900 only 37 6 4 CompactPCI 2 16 Standard Fabric Slot connectors sees 38 f GLOSSARY m rr 39 1 1 1 1 2 1 3 Introduction The following section will give you a brief overview about your K aparel product It will also help you navigate our documentation efficiently This chapter will tell you about the following e Kaparel Corporation e Kaparel PS4900 05 backplane e Contact information Document conventions e Background information Kaparel Corporation Kaparel Corporation develops manufactures and globally markets CompactPCI hardware and software solutions From our pioneering work in CompactPCI bridge designs K aparel has quickly become a leader in all aspects of CompactPCI technology In addition to over 200 off the shelf standard products
14. 2 is assigned address 5 and J17 address 6 The power and status signals used by the PEMs is shown in Figure 6 and Table 4 13 Figure 6 PEM Connector Backplane Rear View Alignment Pin Socket Chassis Ground mamam AC Line DC mamam AC Neutral DC Return qc EE Y Alignment Pin Socket Chassis Ground Table 4 PEM Pinout Pin Signal Name Description PEM INH Alarm Card signal to the PEM to turn the output power on or off PEMZOUTOK Signal from the PEM to the Alarm Card indicating PEM output power status PEM INOK Signal from the PEM to the Alarm Card indicating PEM input power status PEM fully inserted enabling the PEM power output PEM PR PEM present signal to the Alarm Card D Digital ground 4 6 C_IPMB SCL System management data clock 8 C_IPMB SDA IMPB_PWR If the backplane is not equipped with PEM support connector J17 and J22 Mom Will not be populated Connector J12 will be populated instead 3 4 4 Miscellaneous headers 3 4 4 1 External reset The push button reset of the Host Slots are connected to individual 2 pin headers JP9 and JP10 These connectors allow for external reset switches or switch to be connected to the Host Slots JP9 is connected to Host Slot 1 JP10 is connected to Host Slot 9 Table 5 displays the pinout of the connectors 14 PANN NA CPSR TTear Mannal Table 5 Reset Connectors Fie Seve
15. 22 No 5 io N S 53 5 mo Nc Ne S a 5 el 5 ag 5 JP9 NS 2 2 Qs Qo o m 8 9 res z lt y Kaparel 3 Quick Start 3 1 Some older versions of the PS4900 05 will not contain all of the d functionality described in this manual Where ever possible the areas in question will have an asterisks highlighting the item in question The facilities present on your backplane will depend upon the actual model is that you have ordered Order specific options are highlighted by the dollar symbol The PS4900 05 backplanes are compliant with the PICMG 2 0 R3 0 CompactPCI amp Core Specification PICMG 8 2 16 R1 0 CompactPCI Packet Switching Backplane Specification and the PICMG 2 5 R1 0 Computer Telephony Specification PS4900 only providing a 5V or 3 3V 33MHz 64 bit CompactPCI bus on all P1 P2 connectors and a standard H 110 8Mbps bus on the P4 connectors of slots 2 7 and 10 15 PS4900 only This chapter will provide an overview of basic operating procedures including the following e Inspecting your backplane Installing your backplane in a sub rack Powering your backplane e Accessory connections e Installing modules in your backplane Inspecting your backplane Take great care when handling the backplane Improper handling could cause damage to the connector pins Always handle the backplane from the edges never the connectors The first item that
16. 5 is not designed for use with the PS1134 and PS1133 K aparel low profile CompactPCI bridges or the PS1130 K aparel Pallet i e it can be used only as a standalone unit Backplane connectors The complete list of connectors utilized on the backplane is listed in Backplane connectors Table 26 on page 33 Power connectors The PS4900 05 backplane distributes D C power 5V 3 3V 12V amp 12V to each slot through the internal 10z copper planes which connect to the 47 pin Positronic connectors J1 J2 J3 and J8 The AC DC input to the power supplies is provided by internal traces routed to support up to 8A current carrying capability from J12 or optionally from J17 and J22 The part numbers and reference designators for the power connectors are listed in Table 26 on page 33 The output provided by the optional PEMs is common to all power supplies The output provided by the power supplies is common to all of the CompactPCI6 slots The power supply units are connected in load sharing mode The large contacts size 16 have acurrent capacity of 40A each derated to 23A for a 30 C temperature rise The small contacts size 20 have a capacity of 28A each derated to 16 5A for a 30 C temperature rise The connector pinout assignments and mechanical location for power supplies is according to the PICMG 2 11 R1 0 Power Interface Specification Remote voltage sensing for the CompactPCI power rails is employed by default on the
17. 6 specification Table 30 on page 38 displays the pin assignments for Standard Fabric Slots 4 4 3 2 Node Slots Slots 1 7 and 9 15 on the PS4900 05 are D ual Link Node Slots As such all Node Slots support links to Fabrics a and b Node Slots are designated as Nodes 1 14 starting with the lowest numbered slot Table 14 displays the physical slot to Node mapping Table 14 N ode Slot Mapping Slot Node Link Slot Node Link pe 2 2 3 3 31 1 10 4 2 n H 5 5 5 3 12 12 6 6 M H 1 7 17 17 5 4 HM L8 ILE 1 1 5 Node Slots 1 and 9 are System Slots for the two CompactPCI 8 segments on the PS4900 05 Node Slots 2 7 and 10 15 also support 64 bit 33MHz CompactPCI 8 peripheral connections on P1 and P2 P3 is used for Link connections and BP I O as per the PICMG 2 16 specification 4 4 3 3 Shelf address headers To comply with the 2 16 CompactPCI Packet Switching Backplane specification there are two sets of 5 jumpers denoted JP1 and JP2 in Figure 2 that set the geographic address of the Fabric Slots Refer to Table 16 for the shelf address settings The user can define the address of the Fabric Slots by mounting shunts on headers JP1 and JP2 Table 16 displays the pinout of the headers while Table 17 displays possible settings for these jumpers 22 Dpc lt c4onn NA CPSR TTear Mannal Table 15 Shelf Address H eaders 1 G
18. A40nn NK CPLR Tiear Mannal Figure 3 PS4905 Backplane Layout I i Dow y y lt O Bu ie dis d Oo 10128uu02 JOMOd SOQ v f Oo o e 10120uu02 JAMO SOod y Oo O o e 1012euu02 1 SOQ v Lf Oo O o o JP28 i 557 m J00 JP4 LJP28 jee I It i O 22 3 JP5 JP6 x2 og 2 NS 5 lS SS mo Nc Nec AS ce amp elu a5 lt 5 wak x2 og 2g q 5 25 aos go ao as Qe E l e eC IS an aa att a aa a S ERENER NNNM OUO DN e a a Pu a 5 o2 2g as 25 Q 9 mo os as a T qt o o a2 g 2g q 5 5 a go mo m Qe i lt 4 73 wn o D o o 5 35 B5 8 S 8 5 o oS S9 OG lt rey x2 2 2 q ai ao Ss mo gr Qe Die A E ae o e Ly x 9 9 gt 2 NS 5 5 aos 6 ag i JP10 o on a2 2 22 a5 25 Bl d Sl m mo Nc Nc A aS e ag lt 5 D co o o Lg Ne Qe aS S 5 a 5 o 5 5 as 9 a3 m 5 5 o E t a2 ENS as Q5 ao S lt m IG o T i ix i SES Ns 8 5 m er mg 6d ee D PP UTU T TT T T E L A TOO S S h 9 E ed ec ga Ee SENE SS l A 1 v2 o2
19. BPWR PMB PWR As an PC based bus the SMBus is restricted by electrical loading limits to 19 devices nodes This limitation can be overcome by using C bridge devices to connect bus segments into a single logical bus Bridge devices may be used on the alarm card slot 17 to allow all slots and accessory devices to be connected by a single SMBus This feature will be configurable on the alarm card by the system developer IPMBO J4 connects to all backplane slots in the first segment slots 1 8 and the Alarm Card It consists of IPMB PWR pin A4 on P1 of all slots A IPMB SCL pin B17 and A IPMB SDA pin C17 IPMB1 J5 connects to all backplane slots in the second segment slots 9 16 and to the Alarm Card IPMB1 consists of IPMB PWR pin A4 on P1 B IPMB SCL pin D19 on P2 and B IPMB SDA pin C19 on P2 and B SMB ALERT pin E19 on P2 Table 20 displays the allocation of resources on the IPMB buses Table 20 IPMB Allocation Slot Device Bus A Bus A Bus B BusB Accessory IPMBO IPMB1 IPMB1 SMbus Slotti e e sit e j s o qe T ee i C d pw lp Se 26 Dpc lt c4onn NA CPSR TTear Mannal Slot Device Bus A Bus A Bus B Bus B Accessory IPMBO IPMB1 IPMBO IPMB1 SMbus The IPMB PWR line can be shorted to 5V through the jumpers JP28 JP29 Nese JP3 and JP7 in case a battery backup does not exist within the chassis for System Management functions de
20. Mannal Table 18 Shelf Address Configuration Shelf Pin 1 2 Pin 3 4 Pin 5 6 Pin 7 8 Pin 9 10 Address 1 Shorted Shorted Shorted Shorted Open 6 Shorted Shorted Opn Opn Shorted 7 Shorted Shorted Open Open e f Shorted Open Shorted f Shoned Shoe Shorted Open Shorted Shorted Open Open Shorted Shorted Shorted Open 4 4 5 System management buses The PS4900 05 backplane routes two System Management Buses as defined in the PICMG 2 9 R1 0 specification and a third system level bus The backplane supports system management on all slots power supplies PE Ms fans and alarm card The bus supports several configuration options Two independent IPMB Baseboard Management Controllers BMCs in slots 1 and 9 e BMC in Host slot 1 controlling all other slots and devices BMC in the alarm card slot slot 17 controlling all slots and devices The standard connector for PICMG System Management off board extension is the Molex 1 25mm pitch Micro Wire to Board and Wire to Wire series or mateable equivalent in a five pin configuration The reference receptacle for the System Management extension headers is Molex part number 51021 0500 or equivalent Table 19 displays the description of the connector used for the buses and their pinout 25 Table 19 Molex connector used for SMB and its pinout mm jJ B J 1 ATPMBSCL BIPMB SL ME B 2 GND 5 1 4 IPM
21. ND 2 FAB IABLSOAd 3 GND 4 FAB AB SGA3 5 GND 6 FAB ABLSGA2 7 GND 8 FABIABI SAI 9 GND I FAB AB SGAO Table 16 Fabric Address Configuration Shelf Pini2 Pin34 Pin56 Pin78 Pind 10 6 Shorted Shoned Open Open Shorted 8 Shorted Open Shotei Shorted Shorted 9 Shorted Open Shoned Shoned Open For proper system operation it is essential that the two jumper headers be set to the same geographic address If the backplane is equipped with an H 110 bus then these jumpers must be set to the H 110 shelf address 4 4 4 H 110 bus PS4900 only 4 4 4 1 H 110 pinout The PS4900 supports the H 110 Computer Telephony Bus on the P4 connector of slots 2 through 7 and 10 through 15 in conformance with the PICMG 2 5 R1 0 Computer Telephony Specification please refer to Appendix B Table 29 for details on pinout The H 110 bus is not routed to the System Slots This has been done to enable the use of SBCs cards that require the P4 connector for front and rear I O Passive terminations are 23 y Kaparel provided at both ends of the H 110 bus for the signals CT C8 A CT C8 B CT FRAME A CT FRAME B4 In addition to this the P5 area is reserved for H 110 related user I O This section is loaded with long tail transition connectors with shrouds on the rear side of the backplane to allow interfacing with rear cards None of the pins on the P5 area are buss
22. ND CT D30 N 3 3V CT D25 Cr pae oro v crosa GND CTD20 GND Ccrcap GND cr eee GND EIE GND GND oT 05 Loo um oo GND GND CT D5 eros cro ee ND GND 3 3V GND Short Pins Medium Pins LongPins Pins NIN OJO z 9 ojojo iw N s O z iw z ojo 9 w N oO T NP NP O UO Len N oo oo ojo ojo i e U iw O iw E O z iw j iw O iw T 24 ESL 9 e 6 37 6 4 CompactPCI 2 16 Standard Fabric Slot connectors Table 30 Standard Fabric P3 And P5 xi Of m wol Ala a IN alolo N N O z o 9 e O z O z e O z o 9 is oo z z O z e 9 z O z is O z o OJO z z 9 z e O z e O z o 9 z o OJO z z O z o is LA B C C C C C C C C C LP9_DB LP9_DB C C C C C C C C C C 3 5 9 P o O e O e O z e O o 9 z e O is oo z z ojo O iw O z e O O z e Io ojo O O e O is O z o OJO z z a C C C C C C C C C C p j N C C C C C C C LP9_DD LP9 DD ND ND z z zizi
23. PS4900 05 backplane V I O power Configuration of the V I O is factory defaulted depending upon customer request by shorting the V I O internal plane on the PCB to either the 5V or 3 3V plane The selection is realized by mounting standard stainless steel M2 5 screws in the corresponding holes marked for the corresponding voltage Figure 8 illustrates a typical V I O selection mechanism The V I O configuration is checked against the keying on the P1 backplane connector at the time of assembly and test at the factory The keying mechanism on P1 is used to prevent a board built with one buffer technology 3 3V or 5V from being inserted into a system designed for the other buffer technology 5V or 3 3V respectively E Please note that a 66 MHz platform should always be configured for 3 3V Ne Operation on the V I O according to the PICMG 8 2 0 R3 0 CompactPCI 9 Core Specification 17 Yi Kaparel The selectable V I O feature is not intended to be field upgradeable Therefore the V I O screws must be left in the factory default positions and the board retumed to the factory if switching to a different V I O is necessary Kaparel does not assume responsibility for changes of the V I O configuration of the backplane not made and tested at the factory Figure 8 V I O Selection 4 3 Slot keying The P1 and P4 on the backplane are keyed in accordance with the PICMG 2 10 R1 0 specification B
24. WEL IN DUG bt usate 11 3 3 3 power P900 Only ssossct netta ipeo fb OR RR PU 12 34 Accessory COTITIGCUOTIS susc esae tme par nde akawa pda age 12 nosis eRe D n ais t D cel Nani tat 12 942 A lani COT TE sop 13 3 4 3 Power Entry Module Support 13 3 4 4 Miscellaneous headers l n RA M Urs OR rM RUE 14 3 5 Installing modules in your Dackplane o I bea CI pug 16 4 UNDERSTANDING YOUR BACKPLANE nnns J 17 4 1 Backplane connectorsS dre i qr pee D AUR 17 411 Power conn eC OS y y lu au a tuvo Mosa itc a od a bb A dads 17 22 MATIC VOWEL gy sent etse besten edob sese e Tas hui lama va eres nts 17 2 3 SOE KO IIO n a morie aset niei rong ecole cl be Conv ene nn 18 4 4 Buses on the backplane mci eb oai aote ytondem s vierte iter 18 44 1 CompactP CTO DIS attt v ince en ice 18 44 2 Segment type identification l anna 21 44 3 CompactPCIG Ethernet fabric eene ttettnttntnntnnen 21 444 H 110 bus PS4900 only u eo 23 44 5 System management DUses I annassa 29 4 5 Alarm card Slot D 7 cus sauna aun u etae mE 27 4 5 1 Configuring for use without an Alarm Card I l eee 30 4 6 Miscellaneous connectorsS
25. ackplanes configured for 3 3V V I O have P1 on all slots keyed with the cadmium yellow RAL 1021 Code 1278 key Backplanes configured for 5V V I O have P1 on all slots keyed with the brilliant blue RAL 5007 Code 2348 key P4 on slots 8 and 16 are keyed with the blue lilac RAL 4005 Code 2478 key which signifies that they are configured as Standard 2 16 Fabric slots P4 on slots 1 and 9 are keyed with the nut brown RAL 8011 Code 4578 key which signifies that P4 is for user I O On the PS4900 P4 on slots 2 to 7 and 10 to 15 are keyed with the strawberry red RAL 3018 Code 3567 key which signifies that P4 is configured for H 110 On the PS4905 the P4 connectors are keyed with the nut brown RAL 8011 Code 4578 key which signifies that P4 is for user I O Keys on the modules must be inserted and set according to the above Failure to do so could result in damage to the backplane and or modules 4 4 Buses on the backplane 4 4 1 CompactPCI amp bus The PS4900 05 has 2 eight slot segments that provide 5V or 3 3V 33MHz 64 bit CompactPCI buses on the P1 P2 sections All aspects of the buses meet the PICMG 2 0 R3 0 CompactPCI amp Core Specification The backplane also complies with the PICMG 2 1 R1 0 Hot Swap Specification 18 Dpc lt c4onn NA CPSR TTear Mannal The first segment begins in slot 1 and extends to slot 8 The segment is Hosted in slot 1 and can accept a single slot wide 4HP SBC T
26. al This figure has been de rated for a 30C temperature rise with a minimum cable length of 11 3 Table 1 displays the connector s pinout 11 Altematively these terminals can also be used to connect a D C power supply D C and DC are connected to AC Neutral and AC Line respectively Please refer to the manufacturer s power supply specifications for exact details A clearance of 3 2mm is provided for any AC line on the backlane layers to any secondary circuits on the outside layers and 1 6mm on inside layers Ifthe backplane is equipped with PEM support connect J12 will not be hota populated Connectors J17 and J22 will be populated instead 3 3 3 H 110 power PS4900 only 3 4 3 4 1 The PS4900 provides two H 110 Computer Telephony buses on connector locations P4 and P5 of slots 2 7 and 10 15 All signal nets are isolated between the two CT buses Telephony power V bat V batRtn SELV bat SELVbatRtn VRG and VRG Rtn system power 45V 3 3V 12V 12V and all ground nets are common to both bus segments Telephony power is connected to the backplane on 1x3 Mate N Lok connectors J14 J15 and J16 Mating part is Amp 350766 1 Pinouts for these connectors is shown in Table 2 Table 2 H 110 CT Power Connections Connector Function J14 Vbat J15 VRG J16 SELVbat SELVbat Chassis Ground Chassis Ground Chassis Ground VRGRtn SELVbatRtn Accessory connections Fan control The PS4900 05 provides three f
27. an connectors J51 J52 and J53 for power and control of 12V DC fans The connectors provided are 6 position 2x3 Molex Mini Fit Junior connectors capable of providing 6A of continuous current de rated for 30C temp rise Mating connector is Molex 39 01 2060 Figure 5 illustrates the connector outline and pinout for the fan connectors Note that FAN 1 connections are on J51 on J52 and FAN3 on J53 12 PCAGNN NA CPSR TTear Mannal Figure 5 Fan Connectors J51 J52 J53 7 IPMB PWR 1 4 FANIL23 ALM a C_IPMB_SCL 2 5 13 184241 C IPMB SDA 3 6 GND 3 4 2 Alarm card I O For fans that require PWM TACH and possibly TEMP control connector P1 provides signaling for up to 4 of each device Table 3 displays the pinout for the connector Table 3 I O Signal Allocation Description Pin Pin Description _ 5V 1 11 2 3 4 5 6 7 8 9 10 3 4 3 Power Entry Module support Each PS4900 05 backplane can optionally support two K aparel Power Entry Modules PEMs in the rear of slots 18 and 20 These modules can be utilized used to provide filtered 48V DC or AC input power to the backplane power supplies Each PEM connector is capable of supplying 35A when fully derated The PEM connectors support G eographic Addressing Connector J2
28. bility with PCI X signaling at 66MHz clock rates By default all backplanes are configured for 33MHz PCI operation only For more information about PCI X capabilities please contact K aparel technical support 4 4 1 4 Resource allocation Table 12 displays the allocation of resources on the CompactPCI buses 20 PCAONN NA CPSR TTear Mannal Table 12 Resource Allocation Phys Slot Logic Bus IDSEL REQ GNT Map PCI CLK interrupt Geogr Slot Descr Slot Wdt Map Map Addr iption A BICID 1 FRPR UT 2523 JATBIC D pres Par PREGTPSNTO reirs D 45 C 3 PPB 3 PAD30 PREQ PGNTI PCLK6 CID 4 PPB 4 PAD29 PREQPGNT2 PCLKi B C D A 5 P 5 PAD28 PREQ PGNT3 PCLKZ A B C D 00101 e PB 5 rapa PRFQPGNT4 PCIK3 D A C onto 7 PPB 7 PAD26 PREQ PGNTS PCLK4 C D A B 0111 8 PPB 8 G PAD25 PREQ PGNTG PCLK0 B C D A 01000 L 1 L LL LLLLL 4 9 H 1 8 AJB C D OO 10 PSB 2 SAD3I SKEQ SGNTO SCLKO DA B C 01 1i PSB 3 SAD30 SREQ SGNTI SCLK6 C D A B 12 PSB 4 SAD29 SREQ SGNT2 SCLK2 B C D A 01100 13 PSB 5 SAD28 SREQ SGNT3 SCLK4 A B C D omor 1i PSB 6 SAD27 SREQ SGNT4 SCLKi D A B C OUO 15 PSB 7 SAD26 SREQ SGNTS SCLKS C D A B OU 15 PSB 8 64 SAD25 SREQ SGNT4 SCLKO B C D A 10000 PPB Peripheral on Primary Bus HPB Host on Primary Bus PSB Peripheral on Secon
29. dary Bus HSB Host on Secondary Bus 4 4 2 Segment type identification The PS4900 05 supports segment type identification as per the PICMG 2 0 R3 0 ECN 2 0 3 0 002 The backplane is configured for Nominal Right Table 13 displays the pin setting for identification Table 13 Identification Pin Settings Segment ST 1 ST 0 TypeName P2 D21 P2 E21 Nominal Right 4 4 3 CompactPCI Ethernet fabric The PS4900 05 backplane supports an Ethernet based switch fabric interconnect based on the PICMG 2 16 R1 0 CompactPCI 9 Packet Switched Backplane specification The PS4900 05 has support for two Standard Fabric Boards and fourteen D ual Link Node Boards All Links are capable of 10 100 or 1000 Mbps Ethernet signaling 21 yy Kaparel 4 4 3 1 Fabric Slots Slots 8 and 16 on the PS4900 05 are Fabric Slots Slot 8 is designated as Fabric a and slot 16 is Fabric b Standard Fabric Boards supporting up to 20 Links 19 Node Links and one Fabric to Fabric Link can be inserted although only 14 Links 1 14 are routed to Node Slots on the backplane The Fabric to Fabric Link is also supported The remaining Node Links 15 19 may be used on a rear transition module as long as all requirements of the PICMG 2 16 specification are met The Fabric Slots support CompactPCI peripheral connections on P1 and P2 Fabric Slot P3 P4 and P5 connectors are defined for Link connections and BP I O as per the PICMG 2 1
30. ed on backplane except for the row F ground and chassis ground pins 4 4 4 2 Decoupling Power decoupling for the H 110 bus is provided by one 47uF tantalum capacitor per slot for each of the 5V and 3 3V voltage rails in the P4 area between slots and 15uF tantalum capacitors for each of the 12V and 12V rails Additionally 100nF ceramic capacitors are provided at each slot 4 4 4 3 H 110 reset control Two resistors R107 and R14 are included to allow for the segmentation of the H 110 reset lines from the PRST signal on their corresponding segment By default these resistors are populated thereby connecting the H 110 resets to their corresponding CompactPCI PRST 4 signal R107 controls the H 110 reset on the first H 110 segment slots 2 7 and R14 controls the second 4 4 4 4 Shelf address header Because the PS4900 can be a part of a multi shelf CompactPCI 8 system there is one set of 5 jumpers denoted JP11 in Figure 2 on page 8 that set the shelf enumeration address of the backplane Refer to Table 18 for the shelf address settings The user can define the shelf address of the system by mounting shunts on jumper header JP11 Table 17 displays the pinout of the shelf address header while Table 18 displays possible settings for these jumpers Table 17 Shelf Address H eader 1 GND 2 SM 3 GND 4 SAB 5 GND 6 4 7 GN 8 AI 39 GND 4 SA 24 PCAONN NA CPSR TTear
31. he second segment begins in slot 9 and extends to slot 16 This segment is Hosted in slot 9 and also accepts a single slot wide SBC Signal M66EN is connected directly to GND to force 33MHz operation Signal 64EN is connected directly to GND to enable 64 bit transfers The pinouts for the P1 P2 CompactPCI 8 section are shown Appendix B Table 27 and Table 28 The PS4900 05 backplane uses 2mm male short tail connectors for the P1 P2 area The P1 connectors are A25 HotSwap and the P2 connectors are B22 Clock lines are supplied from the Host slots and are routed in conformance to the PICMG 2 0 R3 0 specification Each Peripheral slot gets an individual clock line from its System Slot The skew between different clock lines is minimized by matching the traces in length 6 5 and routing them on the same internal layer The PS4900 05 can act only as a stand alone backplane The backplane is not designed to support the PS1132 64 bit or PS1131 32 bit low profile K aparel CompactPCI bridges The PS4900 05 also does not support the PS1130 K aparel Pallet Bridge 4 4 1 1 Decoupling Power decoupling for the CompactPCI amp bus meets all Rev 3 0 CompactPCI 8 specification requirements providing 47uF of capacitance per slot for each of the 5V and 3 3V voltage rails in the P1 P2 area between slots 94uF of capacitance for the V I O voltage rail and 15uF capacitance for each of the 12V and 12V rails Additionally 100nF ceramic capaci
32. lt c4onn NA CPSR TTear Mannal 5 2 Backplane connectors Table 26 displays all of the connectors utilized on the backplanes Table 26 Connectors used on the PS4900 05 backplanes Description Reference Vendor Connector P N Rating Mating Connector N S x AMP 2794666 0 LC 34V 0 2 794657 0 LO Fan comedor Mole 138750023 9012800 fied MateN Lok AMP 350991 BS0661 x 53261 0590 94V O 87439 0500 x MP 6262 COTS A2SHS i m Vo E 2343256 ke No 4 Em 933 VO PSHO k L89 16 EPT Jii PSHOS k l16 AMP L3g3i WISTEL Pa Em Ei SCT e 2311235 x qeL71015 AMP 352522 vo ABIMIT Pe Em pea VO Er 23605 x kan MP N O J BS o Wm Em 030 CSC x Er 232305 MP BS o Em paws o E 232305 x kan am BILTEL Pe Em ps po EPF x AMP 36024 BOLT Pe Em 335 9W0 o 2327315 33 Description Reference Vendor Connector P N Rating Mating P N wasan o pmi 0 0000 lI Shu SHxi Em 90 PPL STIS PT 435554
33. nd J5 to refer to specific connector locations within a backplane slot and on a plug in card The prefix P denotes a connector on the backplane the prefix J denotes the mating connector on the CompactPCIG cards The connectors are numbered from P1 to P5 starting at the bottom of a 6U slot 39 te y gt Kaparel 97 Randall Drive CompactPCI Waterloo Ontario C d N2V 105 anos N Backplane Architecture Solutions
34. ne will also have silk screened locators to help in positioning the stiffeners Figure 4 illustrates the location Note that the stiffeners are not symmetrical and as such will only fit properly in one direction The vertical rib must be centered between the connectors Figure 4 Mounting H ole Stiffener Location Powering your backplane Backplane secondary power CompactPCI 8 power for the PS4900 05 backplane is supplied via four N 1 redundant 47 pin Positronic connectors located in the right hand section of the backplane The connectors accept hot swappable AC D C power supply units that comply with the PICMG 2 11 R1 0 specification The power supplies accept input as either AC or DC For more information on the 47 pin Positronic connectors see Appendix A Section 5 1 on page 32 3 3 1 1 Power supply configuration Depending upon your backplane model you can install up to four power supply modules in the 47 pin power connectors J1 J2 J3 and J8 Power supplies are assigned geographic addresses 0 to 3 J1 0 2 1 3 2 18 3 numbering from left to right when viewed from the front Possible configurations are e Two 6Ux8HP supplies Three 6Ux4HP supplies e Four 3Ux4HP supplies e Three 3Ux8HP supplies 3 3 2 AC DC power input One 2x3 style AMP Mate N Lok connector J12 is provided for AC DC input to the power supplies The maximum current from line to neutral is approximately 11 Amps 22 Amps tot
35. nformation When you design CompactPCI systems use the following documents for reference e PICMG 2 0 Rev 3 0 CompactPCI 9 Specification as amended by ECN 2 0 3 0 002 e PICMG 2 1 Rev 2 0 Hot Swap Specification e PICMG 2 5 R1 0 Computer Telephony specification e PICMG 2 10 R1 0 Keying of CompactPCI Boards and Backplanes e PICMG 2 11 R1 0 Power Interface Specification e PICMG 8 2 16 R1 0 CompactPC1 Packet Switching Backplane e PICMG 2 17 R1 0 StarFabric Specification e PICMG 2 9 R1 0 System Management specification e PCI Local Bus Specification Rev 2 2 e PCI Bridge Specification Rev 1 1 e IEEE Std 1101 1 1998 IEEE Std 1101 10 1996 IEEE Std 1101 11 1998 e PCI Hardware and Software Architecture amp Design 3 ed ISBN 0 929392 32 9 Dc lt c4onn NK CPSR TTear Mannal 2 Features The PS4900 05 backplane has been designed with the following features e Two 8 slot 64 bit CompactPCIG buses operating at 33MHz PCI or 66MHz PCI X e Selectable V I O 3 3V or 5V when configured for 33MHz CompactPCI 6 e PICMG 8 2 1 R2 0 compliant Full Hot Swap Provisions for up to four backplane stiffeners to control flex during card insertion e PICMG 2 5 R1 0 compliant H 110 CT buses on all Peripheral Slots PS4900 only e Support for 8HP System Boards at expense of one Peripheral Slot e Dual redundant Ethernet interconnect 2 Fabrics 16 Nodes as outlined in PICMG 2 16 R1 0 e Support for Rea
36. notes PS4905 only The third System Management Bus is routed from the Alarm Card connector to the IPMB capable accessories Sites for pull up resistors on the IPMB SCL and IPMB SDA lines are provided on the backplane for each of the 4 groups of signals These are populated with a value that will be determined after integration since it is dependent on the value of the total capacitance on the IPMB SCL and IPMB SDA lines The resistors are needed for the line loading on the IPMB bus introduced by each node on the IPMB bus The biasing of the lines must be kept between 700ns and 1400ns 4 5 Alarm card slot 17 Slot 17 supports an Alarm Card The slot is designed to support a rear mounted PS6700 or I Bus Alarm Card and a front mounted PS6701 The PS4900 05 provides connectors in CompactPCIG defined connector positions P1 P2 and P3 P1 and P2 front and rear The alarm slot supports PS670x only five SMBus connections as described in Section 44 5 The Alarm Card functionality with regard to SMBus connections is not yet defined but may be used to bridge all SMBus segments together into one functional bus The Alarm Card may also contain the SMBus Baseboard Management Controller The PS4900 05 alarm slot also connects to individual power supply D EG FAL and INH signals to allow the Alarm Card to monitor and control up to four power supplies PEM status and control signals are routed to the Alarm slot connectors as described in Section
37. ot be registered trademarks or copyrights of their respective companies and are used only for identification or explanation and to the owners benefit without intent or infringement PICMG CompactPCIG and the PICMG and CompactPCI logos are registered trademarks of the PCI Industrial Computer Manufacturers G roup Any changes or modifications to this product not expressly approved by the manufacturer could void any assurances of safety or performance and could result in violation of Part 15 of the FCC Rules For more information call 1 519 725 0101 Kaparel Corporation 97 Randall Drive Waterloo Ontario Canada N2V 1C5 www kaparel com Printed in Canada Table Of Contents 1 INTROD CTION PET TERUEL 5 S D SDS Sa un As 5 1 2 Kaparel PS4900 05 backplane cce tibt erit e Pr etie ted iilis 5 1 3 Contact nt OFD allOTLa e eie o et de eller ex dieti 5 1 4 Document conventions 2 a l etie n ket bata ebe b edu UA 6 1 5 Background information rebel ree ett knee delete de d er e iua 6 I T THREE 7 S QUICK START i2 dri ao ed 10 3 1 Inspecting your Dackplent dene bead e vu ten ud eei 10 3 2 Installing your backplane in a sub rack eerte 10 3 3 Powering your backplane s seen etta Bede etta etse e re tita rl eren 11 3 3 1 Backplane secondary pow er esee eee rre tretentententnntnn tasto ntentis 11 DO
38. r Transition Modules in all card slots e Configurable power slot support for two 6Ux8HP three 6Ux4HP three 3Ux8HP or four 3Ux4HP supplies All power slots support PICMG 2 11 R1 0 compatible power supply modules e Power input headers for H 110 V bat SELVbat and VRG power signals e ATX power header for auxiliary power input output e Three fan power connectors providing 12V and System Management support Support for K aparel and I Bus proprietary alarm cards in slot 17 e Support for two Kaparel Power Entry Modules PE Ms e AC DC power input header if PE Ms are not used e PICMG 29 R1 0 compliant System Management Bus SMBus support on all slots power supplies PE Ms fans and Alarm Card Support for C bridge function on Alarm Card to support gt 19 SMBus nodes Figure 1 illustrates front and rear system views Figure 2 and Figure 3 illustrate the major features of the backplanes showing approximate locations for all connectors O bjects drawn as solid lines are on the front side of the backplane O bjects drawn as dashed lines are on the rear Shaded objects are on both sides Figure 1 Module Allocation FRONT REAR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 2 a EIFE a og o S ZZZZzZzz q9ezzzzzzmQm zzz gt s z z z z z z lt z z z z z z lt 39 S o o o o 3 S S ooo 9 o olls v o o o ojo o 9 3 O
39. tors are provided at each slot 4 4 1 2 Slot identification A 5 bit physical slot number is used for the purpose of uniquely identifying each slot on the PS4900 05 backplane The geographic address is in a simple binary count format On the backplane the address is encoded by grounding or leaving unconnected different combinations of pins at each slot connector Table 10 displays the physical slot number its geographic address and the corresponding P2 pin settings Physical slot 0 is not used as numbering starts with 1 Please note that the geographic address of each CompactPC1 slot and each of Ey the power supply slots is hardwired on the backplane This is not to be confused with the shelf address of the system if equipped Mote 19 Table 10 Slot Address Settings Physical Geographic GA 4 GA 3 GA 2 GA 1 GA 0 Slot Address Pin 1 2 Pin3 4 Pin 5 6 Pin7 8 Pin9 10 Number P2 A22 P2 B22 P2 C22 P2 D22 P2 E22 6 6 Shored Shorted Open Open Shorted 8 Shorted Open Shorted Shorted Shorted 9 9 Shorted Open Shorted Shorted Open The power supplies also support geographic addressing Table 11 displays the allocation of addresses on the power supplies Table 11 Power Supply GA 1 2 3 4 G eographic addressing is not configurable on the PS4900 05 backplane 4 4 1 3 PCI X support The PS4900 05 backplanes are designed to support future compati
40. upply outputs ON Table 9 displays the pinout of the connector Table 9 Power Supply Inhibit Connector Signal Name 1 mne 2 2 GND 3 5 Installing modules in your backplane The PS4900 05 supports up to 16 add in CompactPCI H 110 cards and four power supplies Slots are numbered 1 through 16 from left to right as viewed from the front of the sub rack For more information on slot locations see Figure 2 on page 8 For more information on module allocation see Figure 10n page 7 Do not use excessive force when installing or removing modules from the chassis Use of excessive force can result in damage to the backplane and or module Should excessive force be required remove the module s and verify the alignment of the mechanicals and backplane There is no preset order to inserting modules into the backplane Refer to the module and or chassis User Manual s for more information on inserting modules The Host slots 1and 9 are configured for SBCs that support 2 16 Ethemet connections Inserting non 2 16 SBC into these slots may cause damage to the SBCs and or Fabric Boards 16 Dpc lt c4onn NA CPSR TTear Mannal 4 Understanding Your Backplane 4 1 4 2 The backplane provides for sixteen 16 single width plug in board slots on a 0 8 pitch and four 4 single width power supply slots There are two System Slots and fourteen Peripheral Slots The PS4900 0
41. y gt Kapar Ath ckplane Architecture Solutio PS4900 05 Backplane User Manual z Kaparel PS4900 05 Backplane User Manual Last revised 11 Nov 02 Part Number 01A000596 A 05 1999 2002 K aparel Corporation All rights reserved K aparel the K aparel logo are trademarks of K aparel Corporation No part of this manual including the products and or software described in it may be reproduced transmitted transcribed stored in any retrieval system or translated in any language in any form or by any means excluding documentation that is kept by the purchaser for backup purposes without the express written permission of K aparel Corporation Every effort has been made to ensure all information contained herein is accurate at the time of printing and is subject to change without notice and should not be construed as a commitment on the part of K aparel Corporation Neither K aparel nor its employees directors officers or agents are responsible for any damages direct or consequential to any and all equipment as a result of use of this product in a configured system All warranties expressed or implied are void if the product has been 1 repaired damaged modified or altered in any way unless such repair modification or alterations are authorized in writing by K aparel Corporation or 2 the serial number of the product is defaced or missing Products and corporate names appearing in this manual may or may n
Download Pdf Manuals
Related Search