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Texas SM320F2812-HT User's Manual

1. PIN pap _ D E PAD DIE PAD NAME 172 PIN NO Y CENTER 1O z PU PD DESCRIPTION HFG POWER SIGNALS Vpp 22 29 2927 6 42 6 Vpp 36 43 4395 4 42 6 Vpp 55 62 5361 5 1256 0 Vpp 73 86 5361 5 3496 4 Vpp 98 5361 5 4671 835 1 8 V or 1 9 V Core Digital Power Pins See Section 6 2 Recommended Operating 98 113 3861 3 5057 5 Conditions for voltage requirements Vpp 110 125 2451 9 5057 5 Vpp 125 141 663 7 5057 5 Vpp 140 156 42 6 3845 1 Vpp 150 169 42 6 2635 3 Vss 25 2517 7 42 6 Vss 31 38 3871 3 42 6 Vss 37 44 4490 7 42 6 Vss 51 58 5361 5 869 2 Vss 57 65 5361 5 1514 6 Vss 79 5361 5 2818 6 Vss 76 89 5361 5 3754 9 Vss X e Core and Digital I O Ground Pins Vss 97 112 3956 0 5057 5 Vss 103 118 3280 5 5057 5 Vss 111 126 2357 2 5057 5 Vss 133 1587 1 5057 5 Vss 126 142 569 0 5057 5 Vss 139 155 42 6 3915 2 Vss 159 42 6 3580 8 Vss 168 426 2705 4 30 37 3776 0 42 6 Vppio 63 73 5361 5 2226 0 B NE 205 2816 3 3 V I O Digital Power Pins 105 4784 7 5057 5 112 127 2262 5 5057 5 142 160 42 6 3510 7 3 3 V Flash Core Power Pin This pin should be connected to 3 3 V at all times 68 53615 27324 have been rot Thie pin i used as VODIO in ROM parts and must be connec
2. 1 4 1 61 0 ss nnne 49 3 9 PLL Based Clock Module 1 1 2 2241 49 3 10 External Reference Oscillator Clock Option 2 1 41 49 3 11 Watchdog Block 50 3 12 Low Power Modes Block 51 2 Contents Copyright 2009 2010 Texas Instruments Incorporated TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 APRIL 2010 4 5 tsar 52 4 1 2 CPU Timers 0 1 27 a e MEM DES 52 4 2 Event Manager Modules EVA EVB 1 1 6 66 nn nnn 55 4 2 1 General Purpose GP TIMERS smal con Rain ampi m Rn data uia 58 4 2 2 Full Compare Units 2 4 neminem sese senes nne 58 4 2 3 Programmable Deadband Generator 2 1 nennen 58 4
3. NAME ADDRESS SIZE x16 DESCRIPTION SCICCRA 0x00 7050 1 SCI A Communications Control Register SCICTL1A 0x00 7051 1 SCI A Control Register 1 SCIHBAUDA 0x00 7052 1 SCI A Baud Register High Bits SCILBAUDA 0x00 7053 1 SCI A Baud Register Low Bits SCICTL2A 0x00 7054 1 SCI A Control Register 2 SCIRXSTA 0x00 7055 1 SCI A Receive Status Register SCIRXEMUA 0x00 7056 1 SCI A Receive Emulation Data Buffer Register SCIRXBUFA 0x00 7057 1 SCI A Receive Data Buffer Register SCITXBUFA 0x00 7059 1 SCI A Transmit Data Buffer Register SCIFFTXA 0x00 705A 1 SCI A FIFO Transmit Register SCIFFRXA 0x00 705B 1 SCI A FIFO Receive Register SCIFFCTA 0x00 705C 1 SCI A FIFO Control Register SCIPRIA 0x00 705F 1 SCI A Priority Control Register 1 Shaded registers are new registers for the FIFO mode Table 4 9 SCI B Registers NAME ADDRESS SIZE x16 DESCRIPTION SCICCRB 0x00 7750 1 SCI B Communications Control Register SCICTL1B 0x00 7751 1 SCI B Control Register 1 SCIHBAUDB 0x00 7752 1 SCI B Baud Register High Bits SCILBAUDB 0x00 7753 1 SCI B Baud Register Low Bits SCICTL2B 0x00 7754 1 SCI B Control Register 2 SCIRXSTB 0x00 7755 1 SCI B Receive Status Register SCIRXEMUB 0x00 7756 1 SCI B Receive Emulation Data Buffer Register SCIRXBUFB 0x00 7757 1 SCI B Receive Data Buffer Register SCITXBUFB 0x00 7759 1 SCI B Transmit Data Buffer Register SCIFFTXB 0x00 775A 1 SCI B FIFO Tra
4. 109 6 22 SPI Master Mode External Timing Clock Phase 1 1 71 4 4 4 2 4 111 6 23 SPI Slave Mode External Timing Clock Phase 0 2 1 2222 113 6 24 SPI Slave Mode External Timing Clock Phase 1 I HI nnn 115 6 25 Relationship Between Parameters Configured in XTIMING and Duration of Pulse WF 6 26 XTIMING Register Configuration Restrictions 4 n mn nemen nnn 117 6 27 Valid and Invalid Timing nnns 117 6 28 XTIMING Register Configuration Restrictions 1 n emn nnn nnn 118 6 29 Valid and Invalid Timing when using Synchronous XREADY 118 6 30 XTIMING Register Configuration Restrictions 44 lt n em nnn 118 6 31 XTIMING Register Configuration Restrictions 1 1 1 I mn He nnn nnn 119 6 32 Asynchronous XREADY sese sese se ses snis sese sese se nene nun 118 6 33 XINTF Clock
5. enne n hehe nn hne se sess sese na 119 6 34 External Memory Interface Read Switching Characteristics 2 222 122 6 35 External Memory Interface Read Timing Requirements nm nmn nemen nnn 122 6 36 External Memory Interface Write Switching Characteristics 123 6 37 External Memory Interface Read Switching Characteristics Ready on Read 1 Wait State 125 6 38 External Memory Interface Read Timing Requirements Ready on Read 1 Wait State 6 39 Synchronous XREADY Timing Requirements Ready on Read 1 Wait State 125 6 40 Asynchronous XREADY Timing Requirements Ready on Read 1 Wait State 125 6 41 External Memory Interface Write Switching Characteristics Ready on Write 1 Wait State 128 6 42 Synchronous XREADY Timing Requirements Ready on Write 1 Wait State 128 6 43 Asynchronous XREADY Timing Requirements Ready on Write 1 Wait State 128 6 44 XHOLD XHOLDA Timing Requirements XCLKOUT XTIMCLK 132 6 45 XHOLD XHOLDA Timing Requirements XCLKOUT 1 2 XTIMCLK 8 4 133 6 46 DC Specifications
6. 82 5 1 Device and Development Support Tool Nomenclature 82 5 2 Documentation EEEE 83 6 Electrical Specifications er CEEE 85 6 1 Absolute Maximum Ratings 85 6 2 Recommended Operating Conditions 14 nnne nn nennen 86 6 3 Electrical Characteristics 2 1 6 14 lt 86 6 4 Current Consumption Power Supply Pins Over Recommended Operating Conditions During Low Power Modes at 150 MHz SYSCLKOUT 4 4 6 88 6 5 Current Consumption Graphs eee nnn nnne nnn rennen nenne nnn 89 6 6 Reducing Current CONSUMPTION ERE 90 6 7 Power Sequencing Requirements nnn nnne nnn nne 90 6 8 Signal Transition Levels 1 1 61 nn nnne 6 9 Timing Parameter Symbology 2 aces ce rent nnn ren ee dee anms 92 6 10 Gene
7. 1 31 3 2 3 Peripheral Bus nnne hene nensi messes sese sese 31 3 2 4 Real Time JTAG and Analysis 4 4 4 nnn 31 3 2 5 External Interface 32 EPA EMENSCU ME 32 32 7 LOMAS HO SARAMS ire err n ATA 32 39 2 8 Boot ROM nk natn avon XI KE 3 2 9 ae danas 33 3 2 10 Peripheral Interrupt Expansion PIE Block 34 3 2 11 External Interrupts XINT1 XINT2 XINT13 0 000 1 34 3 2 12 Oscillator and 1 0 66 34 3 2 13 Watchdog 34 3 2 14 E 34 3 2 15 Low Power Modes 34 3 2 16 Peripheral Frames 0 1 2 PFN 4 2 44 nne nnne 35 3 2 17
8. A All pending XINTF accesses are completed B Normal XINTF operation resumes Figure 6 35 External Interface Hold Waveform 132 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT www ti com 1 TEXAS SM320F2812 HT INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 45 XHOLD XHOLDA Timing Requirements XCLKOUT 1 2 XTIMCLK 2 3 4 MIN MAX UNIT la HL Hiz Delay time XHOLD low to Hi Z on all Address Data and Control 4tcoxriM te xco ns ta HL HAL Delay time XHOLD low to XHOLDA low Atc xriM 2lc xco ns ta HH HAH Delay time XHOLD high to XHOLDA high Atc xTIM ns la HH BV Delay time XHOLD high to Bus valid ns 1 2 3 4 When a low signal is detected on XHOLD all pending XINTF accesses are completed before the bus is placed in a high impedance state The state of XHOLD is latched on the rising edge of XTIMCLK After the XHOLD is detected low or high all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT Thus for this mode where XCLKOUT 1 2 XTIMCLK the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified Not production tested XCLKOUT 1 2 XTIMCLK Copyright 2009 2010 Texas Instruments Incorporated Electrical Specification
9. 1 1 4 21 1 messe sese sene 135 6 47 Specifications IL EET 136 6 48 Current Consumption 136 6 49 ADC Power Up DelayS P 137 6 50 Sequential Sampling Mode TIMING 2 139 6 51 Simultaneous Sampling Mode TIMING sss iurium cime crm terne toa ue cu dieere xui cis niei 140 6 52 McBSP Timing Requirements 142 6 53 McBSP Switching Characteristics 1 1 1 1 1 1 6 6 143 6 54 McBSP as SPI Master or Slave Timing Requirements CLKSTP 10b CLKXP 0 145 6 55 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 10b CLKXP 0 145 6 56 McBSP as SPI Master or Slave Timing Requirements CLKSTP 11b CLKXP 0 146 6 57 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 0 146 6 58 McBSP as SPI Master or Slave Timing Requirements CLKSTP 10b CLKXP 1 147 6 59 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 10b CLKXP 1 147 6 60 McBSP as SPI Master or Slave Timin
10. PARAMETER TEST CONDITIONS UNIT tweww 0 Pulse duration PWMx output high low 25 ns la PWM XCO Delay time XCLKOUT high to PWMx output switching XCLKOUT SYSCLKOUT 4 10 ns 1 See the GPIO output timing for fall rise times for PWM pins 2 PWM pin toggling frequency is limited by the GPIO output buffer switching frequency 20 MHz 3 PWM outputs may be 100 0 or increments of tenco with respect to the PWM period 4 Not production tested Table 6 14 Timer and Capture Unit Timing Requirements 2 9 MIN MAX UNIT Without input qualifier 2xt luris Pulse duration TDIRx low high dE 9800 cycles With input qualifier 1 x tasco Without input qualifier 2 x t lw CAP Pulse duration CAPx input low high E cycles With input qualifier 1 x tasco 107 tw TCLKINL Pulse duration TCLKINx low as a percentage of TCLKINx cycle time 40 60 96 tw TCLKINH Pulse duration TCLKINx high as a percentage of TCLKINx cycle time 40 60 96 te TCLKIN Cycle time TCLKINx 4 x te HCo ns 1 The QUALPRD bit field value can range from 0 no qualification through OxFF 510 SYSCLKOUT cycles The qualification sampling period is 2n SYSCLKOUT cycles where n is the value stored in the QUALPRD bit field As an example when QUALPRD 1 the qualification sampling period is 1 x 2 2 SYSCLKOUT cycles i e the input is sampled every 2 SYSCLKOUT cycles Six such samples are taken over five sampling w
11. 135 6 29 3 Current Consumption for Different ADC Configurations at 25 MHz ADCCLK 136 6 29 4 ADC Power Up Control Bit Timing em ehe nennen nnne 137 6 29 5 Detailed Description 138 6 29 5 1 Reference Voltage 138 6 29 5 2 Analog Inputs 4 1 21 2 nnn nnn 138 6 29 5 3 Converter 138 6 29 5 4 Conversion Modes 1 2 1 1 41 lt 138 6 29 6 Sequential Sampling Mode Single Channel SMODE 0 138 6 29 7 Simultaneous Sampling Mode Dual Channel SMODE 1 140 6 29 8 Definitions of Specifications and Terminology HII 141 6 29 8 1 Integral Nonlinearity 4 21 4 1 nnn 141 6 29 8 2 Differential Nonlinearity 1 Hm n eme menn nnne 141 6 29 8 3 ZrO OSU T 141 6 29 8 4 Gain Error saad nne a 141 6 29 8 5 Signal to Noise Ratio Distortion SINAD 2 4 4 141 6 29 8
12. 75 IppavrFLP Vpp3veL Current consumption during the Erase Program cycle Program 35 mA Ippp Vpp current consumption during Erase Program cycle 140 mA IppioP Vppio current consumption during Erase Program cycle 20 mA 1 Typical parameters as seen at room temperature using flash API V1 including function call overhead 2 Not production tested Table 6 63 Flash OTP Access Timing 2 PARAMETER MIN TYP MAX UNIT la tp Paged Flash access time 36 ns Random Flash access time 36 ns access time 60 ns 1 For 150 MHz PAGE WS 5 and RANDOM WS 5 For 135 MHz PAGE WS 4 and RANDOM WS 4 2 Not production tested Table 6 64 Minimum Required Wait States at Different Frequencies SYSCLKOUT MHz SYSCLKOUT ns PAGE WAIT STATE RANDOM WAIT STATE 3 150 6 67 5 5 120 8 33 4 4 100 10 3 3 75 13 33 2 2 50 20 1 1 30 33 33 1 1 25 40 0 1 15 66 67 0 1 1 Not production tested 2 Formulas to compute page wait state and random wait state t Page Wait State e round up to the next highest integer or 0 whichever is larger c SCO t UM round up to the next highest integer or 1 whichever is larger Random Wait State i 5 3 Random state must be greater than or equal to 1 Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 149 Submit Documentation Feed
13. NR 92 6 7 3 3 V Test Load 93 6 8 Clock TIMING saca mne antes ase eti an vada m s UOS ORE e 96 6 9 Power on Reset Microcomputer Mode XMP MC 0 See Note 98 6 10 Power on Reset in Microprocessor Mode XMP MC 1 99 6 11 Warm Reset in Microcomputer 99 6 12 Effect of Writing Into PEEGR 99 6 13 IDLE Entry and Exit 0 II III HI HII HI hme e nenne nnne nnne nnn nnn 100 6 14 STANDBY Entry and Exit HR EA E 102 6 15 HALT Wakeup Using XNMI 22 41 4 I hne hh ene eme e nmn nnne enn 104 6 16 PWM TIMING eR 105 6 17 DEAN 106 6 18 106 6 19 106 6 20 External Interrupt TIMING aei a ER 107 6 21 General Purpose Output TIMING tere ne 108 6 22 GPIO Input Qualifier Example Diagram for QUALPRD 1 22 2 2 2 2 2
14. Peripheral Registers Peripheral Registers ADC Registers LSPCLK Low Speed Prescaler SPC Low Speed Peripherals SCI A B SPI McBSP High Speed Prescaler High Speed Peripherals EV A B See Note A Clock Enables HSPCLK 12 Bit ADC Watchdog Block Modes Control 16 ADC Inputs A is the clock input to the CPU SYSCLKOUT is the output clock of the CPU They are of the same frequency Figure 3 6 Clock and Reset Domains Functional Overview Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 The PLL clocking watchdog and low power modes are controlled by the registers listed in Table 3 13 Table 3 13 PLL Clocking Watchdog and Low Power Mode Registers NAME ADDRESS SIZE x16 DESCRIPTION reserved Z0 8 reserved 0x00 7018 1 reserved 0x00 7019 1 HISPCP 0x00 701A 1 High Speed Peripheral Clock Prescaler Register for HSPCLK clock LOSPCP 0x00 701B 1 Low Speed Peripheral Clock Prescaler Register for LSPCLK clock PCLKCR 0x00 701C 1 Peripheral Clock Control Register reserved 0x00 701D 1 LPMCRO 0x00 701E 1 Low Power Mode Control Register 0 LPMCR1 0x00 701F 1 Low Power Mode Control Register 1 reserved
15. Block Start Address 0x00 0000 0x00 0040 0x00 0400 3 0x00 0800 o 6 0 00 0000 a i5 6 8 0x00 0 00 o ul 0x00 2000 5 E 0x00 6000 x 0x00 7000 0x00 8000 0x00 9000 M 0x00 A000 0x3D 7800 0x3D 7C00 0x3D 8000 7FF8 20 Ox3F 8000 o 2 5 22 0x3F A000 5 8 I sto F000 x Ox3F FFCO LEGEND A B C D E F On Chip Memory Data Space Prog Space MO Vector RAM 32 x 32 Enabled if VMAP 0 SARAM 1K x 16 M1 SARAM 1K x 16 Peripheral Frame 0 2K x 16 PIE Vector RAM 256 x 16 Enabled if VMAP 1 ENPIE 1 Reserved Reserved Reserved Peripheral Frame 1 4K x 16 Protected Reserved Peripheral Frame 2 4K x 16 Protected LO SARAM 4K x 16 Secure Block L1 SARAM 4K x 16 Secure Block Reserved OTP or ROM 1K x 16 Secure Block Reserved 1K 128 Bit Password HO SARAM 8K 16 Reserved Boot ROM 4K x 16 Enabled if MP MC 0 BROM Vector ROM 32 x 32 Enabled if VMAP 1 MP MC 0 ENPIE 0 Memory blocks are not to scale Reserved locations are reserved for future expansion Application should not access these areas Boot ROM and Zone 7 memory maps are active either in on chip or XINTF zone depending on MP MC not in both Peripheral Frame 0 Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only User program cannot access these memory maps in
16. 1 AVppREFBG Vpp 1 8v Vppi NOTES A 1 8 V or 1 9 V supply should ramp after the 3 3 V supply reaches at least 2 5 V B Reset XRS should remain low until supplies and clocks are stable See Figure 6 8 Power on Reset in Microcomputer Mode XMP MC 0 for minimum requirements C Voltage supervisor or LDO reset control trips reset XRS first when the 3 3 V supply is off regulation Typically this occurs a few milliseconds before the 1 8 V or 1 9 V supply reaches 1 5 V D Keepingreset low XRS at least 8 us prior to the 1 8 V or 1 9 V supply reaching 1 5 V keeps the flash module in complete reset before the supplies ramp down E Sincethe state of GPIO pins is undefined until the 1 8 V or 1 9 V supply reaches at least 1 V this supply should be ramped as quickly as possible after the 3 3 V supply reaches at least 2 5 V F Other than the power supply pins no pin should be driven before the 3 3 V rail has been fully powered up Figure 6 4 F2812 Typical Power Up and Power Down Sequence Option 2 6 8 Signal Transition Levels Note that some of the signals use different reference voltages see the recommended operating conditions table Output levels are driven to a minimum logic high level of 2 4 V and to a maximum logic low level of 0 4 V Figure 6 5 shows output levels Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 91 Submit Documentation Feedback
17. 10 0 Valid time SPISOMI data valid V SPCL SOMI M sra SPICLK low clock polarity 0 251 10 The MASTER SLAVE bit SPICTL 2 is set and the CLOCK PHASE bit SPICTL 3 is set 0 5tyspom 10 o LSPCLK 2 LSPCLK _ 4 SPIBRR 1 co eu SPlclock cycle time LSPCLK cycle time 3 Not production tested The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit SPICCR 6 Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 111 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 1 SPICLK clock polarity 0 Ea i SPICLK clock polarity 1 29AN Master Data ts vara KONA Data valia 10 4 gt 11 secon OOO ee AVAVAVAVAVAVAVAVAVAVAVAS AVAVAVAVAVAVAVAVAVAS SPISTE N see Note A A Inthe master mode SPISTE goes active 0 5tc SPC before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 25 SPI Master External Timing Clock Phase 1 112 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320
18. See Note B A The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen The waveform relationship shown in Figure 6 8 is intended to illustrate the timing parameters only and may differ based on configuration B XCLKOUT configured to reflect SYSCLKOUT Figure 6 8 Clock Timing 6 14 Reset Timing Table 6 9 Reset XRS Timing Requirements MIN NOM MAX UNIT tw RSL1 Pulse duration stable XCLKIN to XRS high cycles tw RSL2 Pulse duration XRS low Warm reset cycles WD initiated reset 5125 aut ene 2 reset pulse generated by 512 cycles la Ex Delay time address data valid after XRS high 32tc c cycles loscsr 9 Oscillator start up time 1 10 ms tsu xPLLDIS Setup time for XPLLDIS pin 16te c1 cycles th xPLLDIS Hold time for XPLLDIS pin 1615 cycles Hold time for XMP MC pin 16teci cycles thboot mode Hold time for boot mode pins 25201 cycles 1 If external oscillator clock source isused reset time has to be low at least for 1 ms after Vpp reaches 1 5 V 2 Not production tested 3 Dependent on crystal resonator and board design 4 The boot ROM reads the password locations Therefore this timing requirement includes the wakeup time for flash See the TMS320x281x Boot ROM Reference Guide literature number SPRUO95 and TMS320x281x System Control and Interrupts Reference Guide literature number SPRUO78 for further i
19. X X X X Figure 6 45 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 147 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com Table 6 60 McBSP as SPI Master or Slave Timing Requirements CLKSTP 11b CLKXP 1 MASTER SLAVE NO UNIT MIN MAX MIN MAX M58 tsupRv ckxL Setup time DR valid before CLKX low 10 8 10 ns M59 thyckxL DRV Hold time DR valid after CLKX low P 10 8P 10 ns M60 tsu FXL CKXL Setup time FSX low before CLKX low 16P 10 ns M61 tecKx Cycle time CLKX 2P 16P ns 1 Not production tested Table 6 61 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M53 tnckxH FXL Hold time FSX low after CLKX high P ns M54 td FXL CKXL Delay time FSX low to CLKX low 2P ns 56 tais ekxH DXHZ i gi time DX high impedance following last data bit from CLKX 6 7P 6 57 taexL pxv Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all SPI slave modes CLKX has to be minimum eight CLKG cycles Also CLKG should be LSPCLK 2 by setting CLKSM CLKGDV 1 With maximum
20. la sH sampling 2 5tc ApCCLK T 1 Acqps x value 0 15 tsu Sample Hold width Acquisition width 40 ns with 0 ADCTRL1 B 11 Delay time for first result to appear in the Result register Alc ADCCLK 1508 Delay time for successive results to 2 Acqps x 80 ns 1 Not production tested Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Electrical Specifications 139 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 29 7 Simultaneous Sampling Mode Dual Channel SMODE 1 In simultaneous mode the ADC can continuously convert input signals on any one pair of channels A0 BO to A7 B7 The ADC can start conversions on event triggers from the Event Managers EVA EVB software trigger or from an external ADCSOC signal If the SMODE bit is 1 the ADC does conversions on two selected channels on every Sample Hold pulse The conversion time and latency of the Result register update are explained below The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update The selected channels are sampled simultaneously at the falling edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum NOTE In Simultaneous mode the ADCIN channel pair select has
21. LSPCLK 3 Not production tested The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit SPICCR 6 LSPCLK 4 oF Copyright 2009 2010 Texas Instruments Incorporated SPIBRR 1 LSPCLK cycle time 0 5 0 5 0 0 5 O 5tyspom 0 51 o 9 o Electrical Specifications Submit Documentation Feedback Product Folder Link s SM320F2812 HT 109 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com NOTE Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I O buffer speed limit 20 MHz 1 gt SPICLK clock polarity 0 2 SPICLK clock polarity 1 M 4 OK Master out Data ts vals KNOY gt gt 9 Master In Data SPISOM Must Be vatia SPISTE see Note A A Inthe master mode SPISTE goes active 0 5tc SPC before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 24 SPI Master Mode External Timing Clock Phase 0 110 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320
22. XRS tw RSL Address Data Control Valid Execution tax 4 Begins From External Boot Address 0x3FFFCO Address Data Mi ant Cars Rh Control KB XXX XPLLDIS Sampling I lh XPLLDIS user Code Depende tsuxPLLDIS 4 XMP MC RR TOT ERR thoxmpmo Care Pins User Code Dependent See Note B Input Configuration State Depends on Internal PU PD NOTES A Upon power SYSCLKOUT is XCLKIN 2 if the PLL is enabled Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT XCLKIN 8 during this phase B The state of the GPIO pins is undefined i e they could be input or output until the 1 8 V or 1 9 V supply reaches at least 1 V and 3 3 V supply reaches 2 5 V Figure 6 10 Power on Reset in Microprocessor Mode XMP MC 1 98 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 M Na XCLKOUT XCLKIN 8 x XCLKIN 5 User Code Dependent cu lt wRsi2 M XRS N cx User Code Execution Phase lp irren i Bax Don t Care v fC Control peer
23. PLL Bypassed However the 2 module in the PLL block divides the clock input at the X1 XCLKIN pin by two before XCLKIN 2 feeding it to the CPU Achieved by writing a non zero value n into PLLCR register The 2 module in the PLL block now divides the output of the PLL by two before feeding it to the CPU PLL Disabled PLL Enabled XCLKIN x n 2 1 Not production tested 6 13 2 Output Clock Characteristics Table 6 8 XCLKOUT Switching Characteristics PLL Bypassed or Enabled NO PARAMETER MIN TYP MAX UNIT C1 terxco Cycle time XCLKOUT 6 679 ns C3 tixco Fall time XCLKOUT 2 ns C4 Rise time XCLKOUT 2 ns C5 twexcoL Pulse duration XCLKOUT low H 2 H 2 ns C6 twexcou Pulse duration XCLKOUT high H 2 H 2 ns Q7 ltp PLL lock time 9 131 072tyc A load of 40 pF is assumed for these parameters 0 55 The PLL must be used for maximum frequency operation Not production tested This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 95 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com gt C10 C9 TN See Note A k C1 m C5 le c4
24. XWRACTIVE tcxriM When first sampled if XREADY Synch is found to be high then the access completes If XREADY Synch is found to be low it is sampled again each until it is found to be high For each sample setup time from the beginning of the access can be calculated as D XWRLEAD XWRACTIVE 1 te xTIM tsu xRDYsynchL XCOHL where n is the sample number n 1 2 3 and so forth Table 6 43 Asynchronous XREADY Timing Requirements Ready on Write 1 Wait State MIN MAX UNIT lsu XRDYasynchL XCOHL Setup time XREADY Asynch low before XCLKOUT high low 11 ns th xRDYasynchL Hold time XREADY Asynch low 8 ns le XRDYasynchH Earliest time XREADY Asynch can go high before the sampling XCLKOUT edge 3 ns tsu xRDYasynchH XCOHL Setup time XREADY Asynch high before XCLKOUT high low 11 ns th xRDYasynchH XZCSH Hold time XREADY Asynch held high after zone chip select high 0 ns 1 Not production tested 2 The first XREADY Synch sample occurs with respect to E in Figure 6 33 XWRLEAD XWRACTIVE 2 When first sampled if XREADY Asynch is found to be high then the access completes If XREADY Asynch is found to be low it is sampled again each until it is found to be high For each sample setup time from the beginning of the access can be calculated as XWRLEAD XWRACTIVE 3 n tecxtim tsu XRDYasynchL XCOHL where n
25. gt M16 FSR ext 44 M18 M17 4 RDATDLY 00b Bit n 1 n 2 n 3 n 4 gt M18 RDATDLY 01b it n 1 n 2 n 3 M17 T gt M18 RDATDLY 10b Bit n 1 n 2 Figure 6 41 McBSP Receive Timing M1 M11 a 2 12 M13 K 12 id y MIS M5 5 FSX int Np LL M19 M M M20 FSX ext x 5 M10 gt gt 7 DX XDATDLY 00b X Bito RK Bit n 1 n 4 4 M7 X su X gt 3 XDATDLY 01b QU it n 1 n 2 n 3 M6 4 DE M7 7 DX XDATDLY 10b 50 2 Figure 6 42 McBSP Transmit Timing 144 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 6 30 2 McBSP as SPI Master or Slave Timing Table 6 54 McBSP as SPI Master or Slave Timing Requirements CLKSTP 10b CLKXP 0 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 MASTER SLAVE UNIT MIN MAX MIN MAX M30 tsu pRVoCKXL Setup time DR valid before CLKX low P 10 8P 10 ns M31 th cKXLODRV Hold time DR valid after CLKX low P 10 8P 10 ns M32 tsu BFXLOCKXH Setup time FSX low before CLKX high BP 10 ns M33 _ Cycle time CLKX 2P 16P ns 1 No
26. 0 225 gt lt lt e Bar di p E P 172 130 y DE 129 0 105 2 67 H A AAAS Ste AOI a 404073 04 10 404023 2 P 04 10 ommoogzr All linear dimensions are in inches millimeters This drawing is subject to change without notice Ceramic quad flatpack with flat leads brazed to non conductive tie bar carrier This package is hermetically sealed with a metal lid The leads are gold plated and can be solderdipped Leads not shown for clarity purposes Falls within JEDEC MO 113AE 3 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty
27. 1 2 1 2 nenne 28 3 3 External Interface Block Diagram 40 3 4 Interrupt SOUICES 42 3 5 Multiplexing of Interrupts Using the PIE Block 1 4 HI n nnn 43 3 6 Clock and Reset Domains 1 4 40 sse 46 3 7 OSG andi c qu 48 3 8 Recommended Crystal Clock Connection 49 3 9 Watchdog 50 4 1 asiste se xa Sana ciara tibns REM DAE NA ARMS ME ULUSM A MEE 92 4 2 CPU Timer Interrupts Signals and Output Signal See Notes 53 4 3 Event Manager A Functional Block Diagram See Note 41 11 2 2 4 58 4 4 Block Diagram of the F2812 ADC 61 4 5 ADC Pin Connections With Internal Reference See Notes and 62 4 6 ADC Pin Connections With External Reference 63 4 7 eCAN Block Diagram and Interface 1
28. 55 to 220 1 Continuous clamp current per pin is 2 mA 2 Long term high temperature storage and or extended use at maximum temperature conditions may result in a reduction of overall device life Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 85 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 2 Recommended Operating Conditions See MIN NOM MAX UNIT Device supply voltage I O 3 14 3 3 3 47 V uw m m 1 8 V 135 MHz 1 71 1 8 1 89 5 evice su voltage anne 1 9 V 150 MHz 1 81 1 9 2 Vss Supply ground 0 V Vppat VDDA2 ADC supply voltage 3 14 3 3 3 47 V VpDAIO d Flash programming supply VppavFL voltage 3 14 3 3 3 47 V Device clock frequency 1 9 V 5 2 150 MHz SYSOLKOUT system clock 1 8 V 5 2 135 All inputs except XCLKIN 2 V High level input voltage E B DDIO V XCLKIN at 50 uA max 0 7Vpp Vpp All inputs except XCLKIN 0 8 Vi Low level input voltage V XCLKIN at 50 pA max 0 3Vpp High level output source All 1 except Group 2 4 lou current 2 mA 2 4 V Group 2 8 Low level output sink current All I Os except Group 2 4 mA SE VoL Vor MAX Group 2 8 TA Ambient temperature 55 25 220 1 See Section
29. 6 66 4 8 67 4 9 McBSP Module With FIFO 70 4 10 Serial Communications Interface SCI Module Block 75 4 11 Serial Peripheral Interface Module Block Diagram Slave 12 2 2 78 4 12 GPIO Peripheral Pin Multiplexing enixa niu aas MEAE 81 5 1 28x Device NOMEN CIAatUre sse ssa nnn nnn 83 6 1 SM320F2812 HT Life Expectancy Curve exin E niei mee nsu n Enni 87 6 2 Typical Current Consumption Over eens eee nese eee nen nn hn nn nnnm nennen 89 6 3 Typical Power Consumption Over Frequency 90 6 4 F2812 Typical Power Up and Power Down Sequence Option 2 4 4 4 4 91 6 5 Qutput DRM AUAM elas INR UN RAMS 92 6 6 Input Levels eiae rain ta eran tana
30. 6 34 Write With Asynchronous XREADY ACCESS enn 130 6 35 External Interface Hold 132 6 36 XHOLD XHOLDA Timing Requirements XCLKOUT 1 2 1 133 6 37 ADC Analog Input Impedance Model E nn nnns nnn snnt nenne nnn 137 6 38 ADC Power Up Control Bit TIMING vencer amne gx 137 6 39 Sequential Sampling Mode Single Channel Timing mn 139 6 40 Simultaneous Sampling Mode Timing aisil 140 6 41 MCBSP Receive 144 6 42 McBSP Transmit Timing dna 144 6 43 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 145 6 44 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 146 6 45 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 147 6 46 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 148 6 List of Figures Copyright 2009 2010 Texas Instrum
31. 95 5361 5 4347 5 O Z Write Enable Active low write strobe The write strobe waveform is specified per zone basis by the Lead Active and Trail periods in the XTIMINGx registers D 41 48 4900 6 42 6 0 2 Read Enable Active low read strobe The read strobe waveform is specified per zone basis by the Lead Active and Trail periods in the XTIMINGx registers NOTE The XRD and XWE signals are mutually exclusive XR W 50 57 5361 5 755 0 O Z Read Not Write Strobe Normally held high When low XR W indicates write cycle is active when high XR W indicates read cycle is active XREADY 157 176 42 6 1972 4 PU Ready Signal Indicates peripheral is ready to complete the access when asserted to 1 XREADY can be configured to be a synchronous or an asynchronous input See the timing diagrams for more details 18 Introduction Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 2 3 Signal Descriptions continued NAME PIN NO 172 PIN HFG DIE PAD NO DIE PAD X CENTER um DIE PAD Y CENTER 0 22 Pu PD DESCRIPTION JTAG AND MISCELLANEOUS SIGNALS X1 XCLKIN 75 88 5361 5 3668 7
32. A 16 bit timer period register TxPR double buffered with shadow register for reads or writes A 16 bit timer control register TXCON for reads or writes Selectable internal or external input clocks A programmable prescaler for internal or external clock inputs Control and interrupt logic for four maskable interrupts underflow overflow timer compare and period interrupts selectable direction input pin TDIRx to count up or down when directional up down count mode is selected The GP timers can be operated independently or synchronized with each other The compare register associated with each GP timer can be used for compare function and PWM waveform generation There are three continuous modes of operations for each GP timer in up or up down counting operations Internal or external input clocks with programmable prescaler are used for each GP timer GP timers also provide the time base for the other event manager submodules GP timer 1 for all the compares and PWM circuits GP timer 2 1 for the capture units and the quadrature pulse counting operations Double buffering of the period and compare registers allows programmable change of the timer PWM period and the compare PWM pulse width as needed 4 2 2 Full Compare Units 4 2 3 4 2 4 4 2 5 58 There are three full compare units on each event manager These compare units use GP timer1 as the time base and generate six outputs for compare and PWM wavef
33. CLKGDV CLKSRG can be LSPCLK CLKX CLKR as source CLKSRG lt SYSCLKOUT 2 McBSP performance is limited by I O buffer switching speed Not production tested 4 Internal clock prescalers must be adjusted such that the McBSP clock CLKG CLKX CLKR speeds are not greater than the I O buffer speed limit 20 MHz 142 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 53 McBSP Switching Characteristics 2 3 NO PARAMETER MIN MAX UNIT M1 Cycle time CLKR X CLKR X int 2P ns M2 Pulse duration CLKR X high CLKR X int 0 50 Dp 50 ns M3 tw CKRXL Pulse duration CLKR X low CLKR X int C 50 5 ns CLKR int 0 4 M4 tackRH FRV Delay time CLKR high to internal FSR valid CLKR ext 3 ns CLKX int 0 4 5 Delay time CLKX high to internal FSX valid CLKX ext 3 ns M6 Disable time CLKX high to DX high impedance following last CLKX int 8 ldis CKXH DXHZ data bit CLKX ext 14 ns Delay time CLKX high to DX valid CLKX int 9 This applies to all bits except the first bit transmitted CLKX ext 28 CLKX int 8 M7 tackxH Dxv Delay time CLKX high to DX valid DXENA 0
34. GPIOB10 CAP6_QEPI2 59 67 5361 5 1691 3 Volz PU S GPIO or Timer GPIOB11 TDIRB I 69 81 5361 5 2990 9 2 Direction GPIOB12 TCLKINB I 70 82 5361 5 3081 5 Volz PU a or Timer Clock GPIO or Compare 4 GPIOB13 I 60 69 5361 5 1868 1 V O Z PU Output Trip ETEHD GPIO or Compare 5 GPIOB14 5 I 61 71 5361 5 2044 8 VO Z PU Output Trip GPIO or Compare 6 GPIOB15 C6TRIP I 62 72 5361 5 2135 4 VO Z PU Output Trip GPIOD OR EVA SIGNALS Timer 1 Compare GPIODO T1CTRIP_PDPINTA I 108 123 2690 0 5057 5 VO Z PU Output Trip Timer 2 Compare PLUR RO Output Trip or GPIOD1 T2CTRIP EVASOC 1 113 128 2167 8 5057 5 VO Z PU External ADC Start of Conversion EV A GPIOD OR EVB SIGNALS Timer 3 Compare GPIOD5 T3CTRIP_PDPINTB I 77 90 5361 5 3841 1 VO Z PU Output Trip Timer 4 Compare E Output Trip GPIOD6 T4CTRIP EVBSOC I 81 94 5361 5 4261 4 VO Z PU External ADC Start of Conversion EV B GPIOE OR INTERRUPT SIGNALS VaN GPIO or XINT1 or GPIOEO XINT1 XBIO I 146 164 42 6 3059 0 VO Z XBIO input GPIO or XINT2 or GPIOE1 XINT2_ADCSOC 1 148 166 42 6 2899 4 2 ADC start of conversion GPIOE2 XNMI XINT13 I 147 165 42 6 2979 2 VO Z PU 1 GPIOF OR SPI SIGNALS GPIO or SPI slave GPIOFO SPISIMOA 39 46 4709 9 42 6 V O Z in Anaster out GPIO or SPI slave GPIOF1 SPISOMIA 1 40 47 4805 3 42 6 2 out masterin GPIOF2 SPICLKA I O 33 40 4090 6 42 6 V O Z GPIO or SPI
35. by the DSP when a watchdog reset occurs During watchdog reset the XRS pin is driven low for the watchdog reset duration of 512 XCLKIN cycles The output buffer of this pin is an open drain with an internal pullup 100 pA typical It is recommended that this pin be driven by an open drain device TEST1 66 76 5361 5 2522 3 yo Test Pin Reserved for Tl On F281x devices TEST1 must be left unconnected TEST2 65 75 5361 5 2436 1 yo Test Pin Reserved for Tl On F281x devices TEST2 must be left unconnected Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Introduction 19 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Table 2 3 Signal Descriptions continued PIN NO DIE PAD _DIEPAD DIE PAD NAME 172 PIN NO X CENTER Y CENTER 10 202 Pu PD DESCRIPTION HFG i um JTAG test reset with internal pulldown TRST when driven high gives the scan system control of the operations of the device If this signal is not connected or driven low the device operates in its functional mode and the test reset signals are ignored NOTE Do not use pullup resistors on TRST it has an internal pulldown device In TRST 132 148 42 6 4684 8 PD a low noise environment TRST can be left floating In a high noise environment an a
36. v SPCH SIMO S clock polarity 1 9 c SPC S 1 The MASTER SLAVE bit SPICTL 2 is cleared and the CLOCK PHASE bit SPICTL 3 is cleared LSPCLK p LSPCLK 4 SPIBRR 1 tyspc SPlclock cycle time lico LSPCLK cycle time 3 Not production tested The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit SPICCR 6 ki 12 gt SPICLK clock polarity 0 SPICLK 0N 4M N clock polarity 1 gt 15 lt 16 SPISOM SPISOM Data Is valid 19 gt I4 20 SPISIMO Data SPISIMO Must Be Vaid SPISTE see Note A A Inthe slave mode the SPISTE signal should be asserted low at least 0 5tc SPC before the valid SPI clock edge and remain low for at least 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 26 SPI Slave Mode External Timing Clock Phase 0 Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 113 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 114 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812
37. 0x00 7020 1 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control amp Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register reserved 0x00 7024 1 WDKEY 0x00 7025 1 Watchdog Reset Key Register reserved 2 ep 3 WDCR 0x00 7029 1 Watchdog Control Register reserved ee 6 1 All of the above registers can only be accessed by executing the EALLOW instruction 2 The PLL control register PLLCR is reset to a known state by the XRS signal only Emulation reset through Code Composer Studio does not reset PLLCR Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 47 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 3 8 OSC and PLL Block Figure 3 7 shows the OSC and PLL block on the F2812 XPLLDIS XPLLDIS XRS XCLKIN X4 XCLKIN OSCCLK PLL Disabled gt CLKIN pouce 7 CPU SYSCLKOUT On Chip s Oscillator PLL OSC Bypass gt LL J PLL Block Figure 3 7 OSC and PLL Block The on chip oscillator circuit enables a crystal to be attached to the F2812 device using the X1 XCLKIN and X2 pins If a crystal is not used then an external oscillator can be directly connected to the X1 XCLKIN pin and the X2 pin is left unconnected The logic high level in this case should not
38. 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Electrical Specifications 103 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 1 k G k Device Status HALT Normal Flushing Pipeline PLL Lock up Time E Execution Wake up Latency xui o 0 7 NS X64 6 tw WAKE XNMI 4 t gt taint gt Oscillator Start up Time gt 32 SYSCLKOUT Cycles t XCLKOUT SYSCLKOUT NOTES A IDLE instruction is executed to put the device into HALT mode B The PLL block responds to the HALT signal SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped This 32 cycle delay enables the CPU pipe and any other pending operations to flush properly C Clocks to the device are turned off and the internal oscillator and PLL are shut down The device is now in HALT mode and consumes absolute minimum power When is driven active negative edge triggered shown as an example the oscillator is turned on but the PLL is not activated When XNMI is deactivated it initiates the PLL lock sequence which takes 131 072 X1 XCLKIN cycles When CLKIN to the core is enabled the device responds to the interrupt if enabled after a
39. 3 9 XREVISION Register Bit Definitions BIT S NAME TYPE RESET DESCRIPTION 15 0 REVISION R 0x0004 Current XINTF Revision For internal use reference Test purposes only Subject to change Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Functional Overview 41 SM320F2812 HT TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 3 6 Interrupts Figure 3 4 shows how the various interrupt sources are multiplexed within the F2812 device Peripherals SPI SCI McBSP ADC 41 Interrupts Watchdog Leur Low Power Modes Interrupt Control XINT1CR 15 0 INT1 to INT12 XINT1CTR 15 0 96 Interruptst Interrupt Control XINT2CR 15 0 C28x CPU XINT2CTR 15 0 TIMER 0 TIMER 2 for RTOS TIMER 1 for RTOS select enable Interrupt Control XNMICR 15 0 XNMICTR 15 0 t Out of a possible 96 interrupts 45 are currently used by peripherals Figure 3 4 Interrupt Sources Eight PIE block interrupts are grouped into one CPU interrupt In total 12 CPU interrupt groups with 8 interrupts per group equals 96 possible interrupts On the F2812 45 of these are used by peripherals as shown in Table 3 10 42 Functional Overview Copyright 2009 2010 Texas Instrum
40. 320 2812 5 INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Figure 4 11 is a block diagram of the SPI in slave mode SPIFFENA Receiver Overrun Overrun Flag INT ENA RX FIFO registers SPISTS 7 9 SPICTL 4 SPIRXBUF RX FIFO 0 RX FIFO 1 RX FIFO Interrupt SPIINT SPIRXINT RX Interrupt Logic RX FIFO 15 SPIRXBUF Buffer Register SPIFFOVF FLAG r SPIFFRX 15 TX FIFO registers 1 SPITXBUF TX Interrupt TXFIFO interrupt Logic TXFIFO 1 FFO 0 SPITXINT SPI INT FLAG SPITXBUF SPISTS 6 Buffer Register SPISIMO SPISOMI Talk SPICTL 1 Ls 2 1 Jo Clock SPI Bit Rate Polarity Phase LSPCLK SPIBRR 6 0 EAS sPIccR 6 _ sPIcTL 3 lt SPICLK gt t SPISTE is driven low by the master for a slave device SPISTEt gt Figure 4 11 Serial Peripheral Interface Module Block Diagram Slave Mode Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 4 8 GPIO MUX SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 The GPIO Mux registers are used to select the operation of shared pins on the F2812 device The pins can be individually selected to operate as Digital I O or connected to Peripheral signals v
41. 35 MHz XCLKIN tcl Cycle time 6 67 250 ns Frequency 4 150 MHz SYSCLKOUT tesco Cycle time 6 67 500 ns Frequency 2 150 MHz XCLKOUT Cycle time 6 67 2000 ns Frequency 0 5 150 MHz Vieni de Cycle time 6 67 13 30 ns Frequency 7500 150 MHz tem taco Cycle time 13 3 26 60 ns Frequency 37 54 75 MHz ADC clock te aDccLk Cycle time 2 40 ns Frequency 25 MHz SPI clock tospc Cycle time 50 ns Frequency 20 MHz McBSP tecka Cycle time 50 ns 20 2 XTIMCLK Cycle time 6 67 ns Frequency 150 MHz 1 This is the default reset value if SYSCLKOUT 150 MHz 2 The maximum value for ADCCLK frequency is 25 MHz For SYSCLKOUT values of 25 MHz or lower ADCCLK has to be SYSCLKOUT 2 or lower ADCCLK SYSCLKOUT is not a valid mode for any value of SYSCLKOUT 6 13 Clock Requirements and Characteristics 6 13 1 Input Clock Requirements The clock provided at the XCLKIN pin generates the internal CPU clock cycle Table 6 4 Input Clock Frequency PARAMETER MIN TYP MAX UNIT Resonator 20 35 f Input clock frequency Crystal 20 35 MHz XCLKIN 4 150 fi Limp mode clock frequency 2 MHz 1 Not production tested 2 Not guaranteed for Ta gt 125 C 94 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6
42. 5 XCLKIN Timing Requirements PLL Bypassed or Enabled NO MIN MAX UNIT C8 teci Cycle time XCLKIN 6 67 250 ns Up to 30 MHz 6 C9 lici Fall time XCLKIN ns 30 MHz to 150 MHz 2 Up to 30 MHz 6 C10 tcl Rise time XCLKIN ns 30 MHz to 150 MHz 2 C11 lw CIL Pulse duration X1 XCLKIN low as a percentage of tec 40 60 96 C12 Pulse duration X1 XCLKIN high as a percentage of tcc 40 60 96 1 Not production tested Table 6 6 XCLKIN Timing Requirements PLL Disabled NO MIN MAX UNIT C8 toc Cycle time XCLKIN 6 67 250 ns Up to 30 MHz 6 C9 ticn Fall time XCLKIN ns 30 MHz to 150 MHz 2 T Up to 30 MHz 6 C10 Rise time XCLKIN ns 30 MHz to 150 MHz 2 lt 120 2 40 60 11 lw CIL Pulse duration X1 XCLKIN low as a percentage of 96 120 XCLKIN lt 150 MHz 45 55 eh Pulse duration X1 XCLKIN high as a percentage of XCLKIN lt 120 MHz 40 60 tec 120 lt XCLKIN lt 150 MHz 45 55 1 Not production tested Table 6 7 Possible PLL Configuration Modes PLL MODE REMARKS SYSCLKOUT Invoked by tying XPLLDIS pin low upon reset PLL block is completely disabled Clock input to the XCLKIN CPU CLKIN is directly derived from the clock signal present at the X1 XCLKIN pin Default PLL configuration upon power up if PLL is not disabled The PLL itself is bypassed
43. GPIO A Toggle Register GPBDAT 0x00 70E4 1 GPIO B Data Register GPBSET 0x00 70E5 1 GPIO B Set Register GPBCLEAR 0x00 70E6 1 GPIO B Clear Register GPBTOGGLE 0x00 70E7 1 GPIO B Toggle Register reserved 0x00 70E8 1 reserved 0x00 70E9 1 reserved 0x00 70EA 1 reserved 0x00 70EB 1 GPDDAT 0x00 70EC 1 GPIO D Data Register GPDSET 0x00 70ED 1 GPIO D Set Register GPDCLEAR 0x00 70EE 1 GPIO D Clear Register GPDTOGGLE 0x00 70EF 1 GPIO D Toggle Register GPEDAT 0x00 70 0 1 GPIO E Data Register GPESET 0x00 70F1 1 GPIO E Set Register GPECLEAR 0x00 70F2 1 GPIO E Clear Register GPETOGGLE 0x00 70F3 1 GPIO E Toggle Register GPFDAT 0x00 70F4 1 GPIO F Data Register GPFSET 0x00 70F5 1 GPIO F Set Register GPFCLEAR 0x00 70F6 1 GPIO F Clear Register GPFTOGGLE 0x00 70F7 1 GPIO F Toggle Register GPGDAT 0x00 70F8 1 GPIO G Data Register GPGSET 0x00 70F9 1 GPIO G Set Register GPGCLEAR 0x00 70FA 1 GPIO G Clear Register GPGTOGGLE 0x00 70FB 1 GPIO G Toggle Register reserved em ae 4 1 Reserved location returns undefined values and writes are ignored 2 These registers are NOT EALLOW protected The above registers are typically accessed regularly by the user 80 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Figure 4 12 shows how the various register bits select the various modes of operation
44. General Purpose Input Output GPIO Multiplexer 35 3 2 18 32 Bit CPU Timers 0 1 2 0 5 15 66 66 sisse 35 3 2 49 Control Peripherals 1 nemen neminem si s se sese nenne 35 3 2 80 Serial Port Peripherals 1 1 41 1 2 1 11 1 66 nnne 36 3 3 Register Map 36 3 4 Device Emulation Registers 39 3 5 External Interface X INITE 39 3 5 1 TIMING Tel III 41 3 5 2 Register 1 2 41 3 6 aucem ETICA 42 3 6 1 External Interrupts tena tide aga ie Ee RR Rau 45 37 SYSTEM COonlIO UAR ERE RU MUR KS 46 38 OSC and PLL Block 1 4 1 1 66 48 3 8 4 Loss of Input Clock
45. Goce Execution LS AAA DOLLA LY tsu XPLLDIS th XPLLDIS Don t Care t vare xy GPIOF14 XPLLDIS Sampling User Code Dependent BORN Dont Care thoxmpymc 6 1 1999907 BERT Care MO XMP MC Ki RO 5500 th boot mode See Note Peripheral GPIO Function XF XPLLDIS GPIOF14 XF Boot ROM Execution Starts Boot Mode Pins Peripheral GPIO Function GPIO Pins as Input User Code Execution Starts Pins User Code Dependent GPIO Pins as Input State Depends on Internal PU PD User Code Dependent A After reset the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles SYSCLKOUT XCLKIN 2 and then samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function in ROM The BOOT Mode pins should be held high low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes If Boot ROM code executes after power on conditions in debugger environment the Boot code execution time is based on the current SYSCLKOUT speed The SYSCLKOUT is based on user environment and could be with or without PLL enabled Figure 6 11 Warm Reset in Microcomputer Mode X1 XCLKIN Write to PLLCR SYSCLKOUT I LJ LLELELELELELELELI M E or XCLKIN x 2 XCLKIN 2 XCLKIN x 4 Current CPU CPU Frequency
46. HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 58 McBSP as SPI Master or Slave Timing Requirements CLKSTP 10b CLKXP 1 MASTER SLAVE NO UNIT MIN MAX MIN MAX M49 tsu DRV CKXH Setup time DR valid before CLKX high P 10 8P 10 ns M50 tnckxH DRV Hold time DR valid after CLKX high P 10 8P 10 ns M51 tsu FXL CKXL Setup time FSX low before CLKX low 8P 10 ns M52 tc ckx Cycle time CLKX 2P 16P ns 1 Not production tested Table 6 59 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 10b CLKXP 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX tnckxH FXL Hold time FSX low after CLKX high 2P ns M44 taFxL ckxL Delay time FSX low to CLKX low P ns Disable time DX high impedance following last data bit from FSX M47 ldis FXH DXHZ high 9 9 6 6P 6 ns M48 taexL pxv Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all SPI slave modes CLKX has to be minimum eight CLKG cycles Also CLKG should be LSPCLK 2 by setting CLKSM CLKGDV 1 With maximum LSPCLK speed of 75 MHz CLKX maximum frequency is LSPCLK 16 that is 4 5 MHz and P 13 3 ns LSB M51 6 MSB M52 CLKX E 5 gt 4 m7 7 C Bin n3 X na X M9 wo pr
47. In other words the inputs should be stable for 5 x QUALPRD x 2 SYSCLKOUT cycles This would ensure six sampling windows for detection to occur Since external signals are driven asynchronously an 11 SYSCLKOUT wide pulse ensures reliable recognition Figure 6 22 GPIO Input Qualifier Example Diagram for QUALPRD 1 Table 6 20 General Purpose Input Timing Requirements MIN MAX UNIT With no qualifier 2 x tesco lw GPI Pulse duration GPIO low high All GPIOs 2 cycles With qualifier 1 x tesco IQT 1 Not production tested 2 Input Qualification Time IQT 5 x QUALPRD x 2 x tesco 108 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS SM320F2812 HT www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Jf SSF BF GP YF GPIOxn X X tw GPI gt Figure 6 23 General Purpose Input Timing NOTE The pulse width requirement for general purpose input is applicable for the XBIO and ADCSOC pins as well 6 19 SPI Master Mode Timing Table 6 21 SPI Master Mode External Timing Clock Phase 0 2 9 SPI WHEN SPIBRR 1 SPI WHEN SPIBRR 1 IS EVEN OR IS ODD AND SPIBRR 0 OR2 SPIBRR gt 3 HBBaco Stoo 127 0 5tespcym 10 0 0 5 10 c SPC M Cycle time SPICLK Puls
48. LSPCLK speed of 75 MHz CLKX maximum frequency is LSPCLK 16 that is 4 5 MHz and P 13 3 ns 3 CLKX low pulse width P D CLKX high pulse width P LSB M60 6 4 M61 CLKX LS V M53 gt M54 4 5 a M56 M57 gt 4 Mss DX Bin 02 X X na X M58 44 M59 DR Bini n2 X v3 JA Figure 6 46 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 148 Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 31 Flash Timing 6 31 1 Recommended Operating Conditions MIN NOM UNIT Flash endurance for the array Write erase cycles 0 C to 85 C 100 1000 cycles 2 One Time Programmable OTP endurance for the array Write 0 C to 85 1 write 4 Flash Timing Endurance is the minimum number of write erase or write cycles specified over a programming temperature range of 0 C to 85 C Flash may be read over the operating temperature range of the device Table 6 62 Flash Parameters at 150 MHz SYSCLKOUT 2 PARAMETER MIN UNIT 16 Bit Word 35 us Program Time 8K Sector 170 ms 16K Sector 320 ms 8K Sector 10 S Erase Time 16K Sector 11 S
49. Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 3 6 1 External Interrupts SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 3 12 External Interrupts Registers NAME ADDRESS SIZE x16 DESCRIPTION XINT1CR 0x00 7070 1 XINT1 control register XINT2CR 0x00 7071 1 XINT2 control register 0x00 7072 reserved 0x00 7076 5 XNMICR 0x00 7077 1 XNMI control register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register 0x00 707A reserved 0x00 707E 5 XNMICTR 0x00 707F 1 XNMI counter register Each external interrupt can be enabled disabled or qualified using positive or negative going edge For more information see the TMS320x281x System Control and Interrupts Reference Guide SPRUOTS Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Functional Overview 45 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 3 7 46 System Control TEXAS INSTRUMENTS www ti com This section describes the F2812 oscillator PLL and clocking mechanisms the watchdog function and the low power modes Figure 3 6 shows the various clock and reset domains in the F2812 device that are discussed Reset SYSCLKOUT Peripheral Reset CLKIN C28x CPU Peripheral Bus System Control Registers Peripheral Registers
50. Oscillator Input input to the internal oscillator This pin is also used to feed an external clock The 28x can be operated with an external clock source provided that the proper voltage levels be driven on the X1 XCLKIN pin It should be noted that the X1 XCLKIN pin is referenced to the 1 8 V or 1 9 V core digital power supply Vpp rather than the 3 3 V I O supply Vppio A clamping diode may be used to clamp a buffered clock signal to ensure that the logic high level does not exceed Vpp 1 8 V or 1 9 V or a 1 8 V oscillator may be used 2 74 87 5361 5 3582 6 Oscillator Output XCLKOUT 117 132 1701 2 5057 5 Output clock derived from SYSCLKOUT to be used for external wait state generation and as a general purpose clock source XCLKOUT is either the same frequency 1 2 the frequency or 1 4 the frequency of SYSCLKOUT At reset XCLKOUT SYSCLKOUT 4 The XCLKOUT signal can be turned off by setting bit 3 CLKOFF of the XINTCNF2 register to 1 TESTSEL 131 147 42 6 4764 6 PD Test Pin Reserved for TI Must be connected to ground 2 156 175 42 6 2077 8 yo PU Device Reset in and Watchdog Reset out Device reset XRS causes the device to terminate execution The PC points to the address contained at the location OxSFFFCO When XRS is brought to a high level execution begins at the location pointed to by the PC This pin is driven low
51. SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com The CAN registers listed in Table 4 6 are used by the CPU to configure and control the CAN controller and the message objects eCAN control registers only support 32 bit read write operations Mailbox RAM can be accessed as 16 bits or 32 bits 32 bit accesses are aligned to an even boundary Table 4 6 CAN Registers REGISTER NAME ADDRESS SIZE x32 DESCRIPTION CANME 0x00 6000 1 Mailbox enable CANMD 0x00 6002 1 Mailbox direction CANTRS 0x00 6004 1 Transmit request set CANTRR 0x00 6006 1 Transmit request reset CANTA 0x00 6008 1 Transmission acknowledge CANAA 0x00 600A 1 Abort acknowledge CANRMP 0x00 600C 1 Receive message pending CANRML 0x00 600E 1 Receive message lost CANRFP 0x00 6010 1 Remote frame pending CANGAM 0x00 6012 1 Global acceptance mask CANMC 0x00 6014 1 Master control CANBTC 0x00 6016 1 Bit timing configuration CANES 0x00 6018 1 Error and status CANTEC 0x00 601A 1 Transmit error counter CANREC 0x00 601C 1 Receive error counter CANGIFO 0x00 601E 1 Global interrupt flag 0 CANGIM 0x00 6020 1 Global interrupt mask CANGIF1 0x00 6022 1 Global interrupt flag 1 CANMIM 0x00 6024 1 Mailbox interrupt mask CANMIL 0x00 6026 1 Mailbox interrupt level CANOPC 0x00 6028 1 Overwrite protection control CANTIOC 0x00 602A 1 TX I O control CANRIOC 0x00 6
52. SPlclock cycletime Not production tested SPICLK clock polarity 0 SPICLK clock polarity 1 SPISOMI SPISIMO SPISTE see Note A LSPCLK 4 r __LSPCLK SPIBRR 1 The MASTER SLAVE bit SPICTL 2 is cleared and the CLOCK PHASE bit SPICTL 3 is set tico LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit SPICCR 6 513 SPISOMI Data Is Valid I 21 XXXXXXXXX 4 22 P 005509 SS SS QN AVAVAVAVAVAVAVAYVAS lt Data Valid XXX KK XX Ne In the slave mode the SPISTE signal should be asserted low at least 0 5tc SPC before the valid SPI clock edge and remain low for at least 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 27 SPI Slave Mode External Timing Clock Phase 1 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Electrical Specifications 115 Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 116 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010
53. TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 3 2 20 Serial Port Peripherals The F2812 supports the following serial communication peripherals eCAN This is the enhanced version of the CAN peripheral It supports 32 mailboxes time stamping of messages and is CAN 2 0B compliant McBSP This is the multichannel buffered serial port that is used to connect to E1 T1 lines phone quality codecs for modem applications or high quality stereo quality Audio DAC devices The McBSP receive and transmit registers are supported by a 16 level FIFO This significantly reduces the overhead for servicing this peripheral SPI The SPI is a high speed synchronous serial I O port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmable bit transfer rate Normally the SPI is used for communications between the DSP controller and external peripherals or another processor Typical applications include external I O or peripheral expansion through devices such as shift registers display drivers and ADCs Multi device communications are supported by the master slave operation of the SPI On the F2812 the port supports a 16 level receive and transmit FIFO for reducing servicing overhead SCI The serial communications interface is a two wire asynchronous serial port commonly known as UART On the F2812 the port supports a 16 level receive and transmit FI
54. The vector is automatically fetched by the CPU on servicing the interrupt It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers Hence the CPU can quickly respond to interrupt events Prioritization of interrupts is controlled in hardware and software Each individual interrupt can be enabled disabled within the PIE block 3 2 11 External Interrupts XINT1 XINT2 XINT13 XNMI The F2812 supports three masked external interrupts XINT1 2 13 XINT13 is combined with one non masked external interrupt XNMI The combined signal name is XNMI XINT13 Each of the interrupts can be selected for negative or positive edge triggering and can also be enabled disabled including the XNMI The masked interrupts also contain a 16 bit free running up counter which is reset to zero when a valid interrupt edge is detected This counter can be used to accurately time stamp the interrupt 3 2 12 Oscillator and PLL The F2812 can be clocked by an external oscillator or by a crystal attached to the on chip oscillator circuit A PLL is provided supporting up to 10 input clock scaling ratios The PLL ratios can be changed on the fly in software enabling the user to scale back on operating frequency if lower power operation is desired Refer to the Electrical Specification section for timing details The PLL block can be set in bypass mode 3 2 13 Watchdog The F2812 supports a watchdog timer The user software must regularly reset the
55. Timer 0 Counter Register TIMEROTIMH 0x00 0 01 1 CPU Timer 0 Counter Register High TIMEROPRD 0x00 0C02 1 CPU Timer 0 Period Register TIMEROPRDH 0x00 0 03 1 CPU Timer 0 Period Register High TIMEROTCR 0x00 0C04 1 CPU Timer 0 Control Register reserved 0x00 0C05 1 TIMEROTPR 0x00 0C06 1 CPU Timer 0 Prescale Register TIMEROTPRH 0x00 0 07 1 CPU Timer 0 Prescale Register High TIMER1TIM 0x00 0C08 1 CPU Timer 1 Counter Register TIMER1TIMH 0x00 0 09 1 CPU Timer 1 Counter Register High TIMER1PRD 0x00 1 CPU Timer 1 Period Register TIMER1PRDH 0x00 OCOB 1 CPU Timer 1 Period Register High TIMER1TCR 0x00 0 0 1 CPU Timer 1 Control Register reserved 0x00 OCOD 1 TIMER1TPR 0x00 OCOE 1 CPU Timer 1 Prescale Register TIMER1TPRH 0x00 OCOF 1 CPU Timer 1 Prescale Register High TIMER2TIM 0x00 0C10 1 CPU Timer 2 Counter Register TIMER2TIMH 0x00 0C11 1 CPU Timer 2 Counter Register High TIMER2PRD 0x00 0C12 1 CPU Timer 2 Period Register TIMER2PRDH 0x00 0C13 1 CPU Timer 2 Period Register High TIMER2TCR 0x00 0C14 1 CPU Timer 2 Control Register reserved 0x00 0C15 1 TIMER2TPR 0x00 0C16 1 CPU Timer 2 Prescale Register TIMER2TPRH 0x00 0C17 1 CPU Timer 2 Prescale Register High reserved 40 54 Peripherals Submit Documentation Feedback Product Folder Link s SM320F2812 HT Copyright 2009 2010 Texas Instruments Incorporated l www ti com TEXAS INSTRUMENTS SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 201
56. XCLKOUT high to address valid 2 ns ta xCOHL XWEL Delay time XCLKOUT high low to XWE low 2 ns ta xCOHL XWEH Delay time XCLKOUT high low to XWE high 2 ns la XCOH XRNWL Delay time XCLKOUT high to XR W low 1 ns ta xCOHL XRNWH Delay time XCLKOUT high low to XR W high 2 1 ns len XD XWEL Enable time data bus driven from XWE low 0 ns la xwEL XD Delay time data valid after XWE active low 4 ns th xA XZCSH Hold time address valid after zone chip select inactive high ns th XD XWE Hold time write data valid after XWE inactive high 2 3 ns lais XD XRNW Data bus disabled after XR W inactive high 4 ns 1 2 3 XCLKOUT XTIMCLK XCLKOUT 1 2 XTIMCLK Not production tested During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles TW Trail period write access See Table 6 25 Active i Lead 51 Trail gt a ta xcoHL xzcsH 9 XZCSOAND1 XZCS2 XZCS6AND7 gt I ta xcoH XA XA 0 18 gt K taxcoHL XWEH XWE 1 ae ta XCOHL XWEL XR W ta xWEL xD 1 len XD XWEL le laxcoHL xnNwH gt tdis xD XRNW He th xp XweH 0 0 15 MOKENA XREADY NOTES A before an access to meet
57. XTIMING register configuration restrictions Table 6 28 XTIMING Register Configuration Restrictions 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 21 gt 1 gt 0 gt 1 gt 0 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Synchronous XREADY Table 6 29 Valid and Invalid Timing when using Synchronous XREADY 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0 1 Invalid 1 0 0 1 0 0 0 1 Valid 1 1 0 1 1 0 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations f the XREADY signal is sampled in the Asynchronous mode USEREADY 1 READYMODE 1 then 1 Lead LR 2 taxtim LW gt tecxtim 2 Active AR 2 2 x AW 2 2 te XTIM NOTE Restriction does not include external hardware wait states 3 Lead Active LR AR24x LW AW 24 x lt Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions Table 6 30 XTIMING Register Configuration Restrictions 2 X2TIMING 0 1 XWRACTIVE XWRTRAIL 22 0 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD 21 22 0 21 1 Not production tested 2 No hardwa
58. and places it in the lowest possible power consumption mode Only a reset or XNMI wakes the device from this mode 3 2 16 Peripheral Frames 0 1 2 PFn The F2812 segregates peripherals into three sections The mapping of peripherals is as follows PFO XINTF External Interface Configuration Registers 2812 only PIE PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash Flash Control Programming Erase Verify Registers Timers CPU Timers 0 1 2 Registers CSM Code Security Module KEY Registers PF1 eCAN eCAN Mailbox and Control Registers PF2 SYS System Control Registers GPIO GPIO Mux Configuration and Control Registers EV Event Manager EVA EVB Control Registers McBSP McBSP Control and TX RX Registers SCI Serial Communications Interface SCI Control and RX TX Registers SPI Serial Peripheral Interface SPI Control and RX TX Registers ADC 12 Bit ADC Registers 3 2 17 General Purpose Input Output GPIO Multiplexer Most of the peripheral signals are multiplexed with general purpose I O GPIO signals This enables the user to use a pin as GPIO if the peripheral signal or function is not used On reset all GPIO pins are configured as inputs The user can then individually program each pin for GPIO mode or Peripheral Signal mode For specific inputs the user can also select the number of input qualification cycles This is to filter unwanted noise glitches 3 2 18 32 Bit CPU Timers 0 1 2 CPU Timers 0
59. exceed Vpp The PLLCR bits 3 0 set the clocking ratio Table 3 14 PLLCR Register Bit Definitions BIT S NAME TYPE XRS RESET DESCRIPTION 15 04 reserved R 0 0 00 SYSCLKOUT XCLKIN x n 2 where n is the PLL multiplication factor Bit Value n SYSCLKOUT 0000 PLL Bypassed XCLKIN 2 0001 1 XCLKIN 2 0010 2 XCLKIN 0011 3 XCLKIN x 1 5 0100 4 XCLKIN x 2 0101 5 XCLKIN x 2 5 3 00 DIV R W 0 0 0 0 0110 6 XCLKIN x 3 0111 7 XCLKIN x 3 5 1000 8 XCLKIN x 4 1001 9 XCLKIN x 4 5 1010 10 XCLKIN x 5 1011 11 Reserved 1100 12 Reserved 1101 13 Reserved 1110 14 Reserved 1111 15 Reserved 1 The PLLCR register is reset to a known state by the reset line If a reset is issued by the debugger the PLL clocking ratio is not changed 48 Functional Overview Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 3 8 1 Loss of Input Clock In PLL enabled mode if the input clock XCLKIN or the oscillator clock is removed or absent the PLL still issues a limp mode clock The limp mode clock continues to clock the CPU and peripherals at a typical frequency of 1 MHz to 4 MHz The PLLCR register should have been written to with a non zero value for this feature to work Normally when the input clocks are present the watchdog counter decrements to initiate a watchdog
60. for GPIO function GPxDAT SET CLEAR TOGGLE Register Bit s Digital Peripheral I O GPxQUAL GPxMUX GPxDIR High Register Register Bit Register Bit Impedance Control 4 SYSCLKOUT High Impedance Enable 1 gt 2 o lt Internal Pullup or Pulldown o A In the GPIO mode when the GPIO pin is configured for output operation reading the GPxDAT data register only gives the value written not the value at the pin In the peripheral mode the state of the pin can be read through the GPxDAT register provided the corresponding direction bit is zero input mode B Some selected input signals are qualified by the SYSCLKOUT The GPxQUAL register specifies the qualification sampling period The sampling window is 6 samples wide and the output is only changed when all samples are the same all 0 s or all 1 s This feature removes unwanted spikes from the input signal Figure 4 12 GPIO Peripheral Pin Multiplexing NOTE The input function of the GPIO pin and the input path to the peripheral are always enabled It is the output function of the GPIO pin that is multiplexed with the output path of the primary peripheral function Since the output buffer of a pin connects back to the input buffer any GPIO signal present at the pin is propagated to the peripheral module as well Therefore when pin is configured for GPIO operation the corresponding peripheral fu
61. function 4 2 8 Quadrature Encoder Pulse QEP Circuit Two capture inputs CAP1 and CAP2 for EVA CAP4 and CAP5 for EVB can be used to interface the on chip QEP circuit with a quadrature encoder pulse Full synchronization of these inputs is performed on chip Direction or leading quadrature pulse sequence is detected and GP timer 2 4 is incremented or decremented by the rising and falling edges of the two input signals four times the frequency of either input pulse With EXTCONA register bits the EVA circuit can use as a capture index pin as well Similarly with EXTCONB register bits the EVB QEP circuit can use CAP6 as a capture index pin 4 2 9 External ADC Start of Conversion EVA EVB start of conversion SOC can be sent to an external pin EVASOC EVBSOO for external ADC interface EVASOC and EVBSOC are MUXed with T2CTRIP and TACTRIP respectively Copyright 2009 2010 Texas Instruments Incorporated Peripherals 59 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 4 3 60 Enhanced Analog to Digital Converter ADC Module A simplified functional block diagram of the ADC module is shown in Figure 4 4 The ADC module consists of a 12 bit ADC with a built in sample and hold S H circuit Functions of the ADC module include e 12 bit ADC core with built in S H Analog input 0 0 V to 3 0 V V
62. is the sample number n 1 2 3 and so forth 128 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com XCLKOUT XTIMCLK XCLKOUT 1 2 XTIMCLK XZCSOAND1 XZCS2 XZCS6AND7 XA 0 18 RD XWE i WS Synch See SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 gt Note Notes A Active Lead 1 and B i gt D 1 1 ta xCOH XZCSL e ta xcoH XA la XCOHL XZCSH gt th xRDYsynchH xzcsH le ta xcoHL XWEL ta xcoHL XWEH ta xcoH XRNWL XR W ta xwEL XD ta xCOHL XRNWH 1 1 tdis xD XRNW 7 77 1 gt ten xD XWEL K nxpxwEH i XD 0 15 DOUT 1 1 1 1 1 i 1 1 1 1 1 i 1 1 1 1 1 i tsu XRDYsynchL XCOHL 4 1 1 1 1 1 i te XRDYsynchH i thoxRoveynchLy 8 tsu XRDHsynchH XCOHL i i 1 1 1 1 1 XREADY Synch 51 1 n 1 1 i ___ See Note D i 4 See Note E Legend SERRE 55562555524 Don t care Signal can be high or low during this time NOTES AIIXINTF accesses lead p
63. listed in Table 4 4 Table 4 4 ADC Registers NAME ADDRESS SIZE x16 DESCRIPTION ADCTRL1 0x00 7100 1 ADC Control Register 1 ADCTRL2 0x00 7101 1 ADC Control Register 2 ADCMAXCONV 0x00 7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x00 7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x00 7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x00 7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x00 7106 1 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x00 7107 1 ADC Auto Sequence Status Register ADCRESULTO 0x00 7108 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x00 7109 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00 710A 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x00 710B 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x00 7111 1 ADC Conversion Result Buffer Register 9 ADCRESULT10 0x00 7112 1 ADC Conversion Result Buffer Register 10 ADCRESULT 1 1 0x00 7113 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x00 7114 1 ADC Convers
64. mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according the industry standard classifications peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA HFG S CQFP F172 CERAMIC QUAD FLATPACK WITH NCTB
65. of 1K x 16 Each ANSI Compiler Assembler Linker SARAM Supports TMS320C24x 240x Instructions Boot ROM 4K x 16 Code Composer Studio IDE With Software Boot Modes DSP BIOS Standard Math Tables JTAG Scan Controllers Texas Instruments External Interface TI or Third Party Up to 1M Total Memory Evaluation Modules Programmable Wait States Broad Third Party Digital Motor Control Programmable Read Write Strobe Timing Support Three Individual Chip Selects Low Power Modes and Power Savings Clock and System Control IDLE STANDBY HALT Modes Supported Dynamic PLL Ratio Changes Supported Disable Individual Peripheral Clocks On Chip Oscillator Watchdog Timer Module Three External Interrupts Peripheral Interrupt Expansion PIE Block That Supports 45 Peripheral Interrupts 1 IEEE Standard 1149 1 1990 IEEE Standard Test Access Port TMS320C24x Code Composer Studio DSP BIOS C28x TMS320C2000 TMS320C54x TMS320C55x TMS320C28x are trademarks of Texas Instruments eZdsp is a trademark of Spectrum Digital Incorporated Copyright 2009 2010 Texas Instruments Incorporated Features 11 TEXAS SM320F2812 HT INSTRUMENTS SGU3062A JUNE 2009 REVISED APRIL 2010 www ti com 131 SUPPORTS EXTREME TEMPERATURE APPLICATIONS 2 12 Controlled Baseline One Assembly Test Site One Fabrication Site Available in Extreme 55 C 220 C Temperatur
66. parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated b
67. program space Protected means the order of Write followed by Read operations is preserved rather than the pipeline order Certain memory ranges are EALLOW protected against spurious writes after configuration TEXAS INSTRUMENTS www ti com External Memory XINTF Reserved XINTF Zone 0 8K x 16 XZCSOAND1 0x00 2000 XINTF Zone 1 8K x 16 XZCSOAND1 Protected 9x00 4000 Reserved XINTF Zone 2 0 5M x 16 XZCS2 0x08 0000 XINTF Zone 6 0 5M x 16 XZCS6AND7 0x10 0000 0x18 0000 Reserved Prog Space Ox3F C000 XINTF Zone 7 16K x 16 XZCS6AND7 Enabled if MP MC 1 XINTF Vector RAM 32 x 32 Enabled if 1 MP MC 1 ENPIE 0 Only one of these vector maps MO vector PIE vector BROM vector XINTF vector should be enabled at a time G Zones 0 and 1 and Zones 6 and 7 share the same chip select hence these memory blocks have mirrored locations 28 Functional Overview Submit Documentation Feedback Product Folder Link s SM320F2812 HT Figure 3 2 F2812 Memory Map See Notes A Through G Copyright 2009 2010 Texas Instruments Incorporated 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 3 1 Addresses of Flash Sectors in F2812 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 Ox3D 9FFF Sector J 8K x 16 Ox3D A000 0x3D BFFF Sector 1 8K x 16 Ox3D C000 Ox3D FFFF Sector H 16K
68. reset or WDINT interrupt However when the external input clock fails the watchdog counter stops decrementing i e the watchdog counter does not change with the limp mode clock This condition could be used by the application firmware to detect the input clock failure and initiate necessary shut down procedure for the system 3 9 PLL Based Clock Module The F2812 has an on chip PLL based clock module This module provides all the necessary clocking signals for the device as well as control for low power mode entry The PLL has a 4 bit ratio control to select different CPU clock rates The watchdog module should be disabled before writing to the PLLCR register It can be re enabled if need be after the PLL module has stabilized which takes 131 072 XCLKIN cycles The PLL based clock module provides two modes of operation Crystal operation This mode allows the use of an external crystal resonator to provide the time base to the device External clock source operation This mode allows the internal oscillator to be bypassed The device clocks are generated from an external clock source input on the X1 XCLKIN pin X1 XCLKIN 2 X1 XCLKIN 2 n 5 TT Cpe External Clock Signal see Note A Crystal see Note Toggling 0 Vpp NC a b A Tl recommends that customers have the resonator crystal vendor characterize the operation of their device with the DSP chip The resonator crystal vendor has t
69. t care for this example 126 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 1 1 1 D WS Asynch SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 See Notes Aand pg Lead gt a m Active i Tr ail Note C xcLKour xrTIMCLK NS CK XCLKOUT 1 2 XTIMCLK XZCSOAND1 XZCS2 XZCS6AND7 XA 0 18 4 ta XCOH XZCSL ta XCOH XA fa xcoHL XRDH lt la XCOHL XRDL XRD ta xcoHL xzcsH 1 a XWE XR W th XD XRD XD 0 15 lsu XRDYasynchL XCOHL gt 1 le XRDYasynchH th xRDYasynchH XZCSH 7 lt E th xRDYasynchL gt tsu XRDYasynchH XCOHL lt gt 555555555 555 9555604 XREADY Asynch T 4 See Note D 48 See Note gt Legend Don t care Signal can be high or low during this time 55555604 NOTES All XINTF accesses lead period begin on the rising edge of XCLKOUT When necessary the device inserts an alignment cycle before an access to meet this requirement B During alignment cycles all signals transitions to their inactive state C During i
70. ta XCOH EVBSOCL Delay time XCLKOUT high to EVBSOC low 1 x tesco cycle tw EVBSOCL Pulse duration EVBSOC low 32 x te HCO ns 1 XCLKOUT SYSCLKOUT 2 Not production tested duc EN ey ta xCOH EVBSOCL tw EVBSOCL EVBSOC V Figure 6 19 EVBSOC Timing 6 16 2 Interrupt Timing Table 6 17 Interrupt Switching Characteristics PARAMETER MIN MAX UNIT Without input 12 Delay time PDPINTx low PWM qualifier high impedance state n With input qualifier 1 x tesco pt Without input 3xt 2 Delay time CxTRIP TxCTRIP signals low qualifier c SCO 2 tacTRIP PWM HZ to PWM high impedance state mE 7 ne With input qualifier 2 x tesco IQT 2 Delay time INT low high to laa interrupt vector fetch quai 121 um 1 Input Qualification Time IQT 5 x QUALPRD x 2 x tesco 2 Not production tested 106 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 18 Interrupt Timing Requirements MIN MAX UNIT with no qualifier 2xt twan 7 Pulse duration INT input low high 28201 cycles with qualifier 1 x tesco IQT with no qualifier 2 x tesco tw PDP Puls
71. the EALLOW instruction The EDIS instruction disables writes This prevents stray code or pointers from corrupting register contents 3 The Flash Registers are also protected by the Code Security Module CSM Table 3 5 Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE x16 ACCESS TYPE SCAN Registers 0x00 6000 256 Some eCAN control registers and selected bits in 9 0x00 60FF 128 x 32 other eCAN control registers are EALLOW protected 0x00 6100 256 eCAN Mailbox RAM 0x00 61FF 128 x 32 Not EALLOW protected 0x00 6200 reserved 0x00 6FFE 3584 1 The eCAN control registers only support 32 bit read write operations All 32 bit accesses are aligned to even address boundaries Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Functional Overview 37 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Table 3 6 Peripheral Frame 2 Registers NAME ADDRESS RANGE SIZE x16 ACCESS TYPE reserved 0x00 700F 16 System Control Registers ai AE 32 EALLOW Protected reserved AE 16 SPI A Registers PD id 16 Not EALLOW Protected SCI A Registers 1 16 Not EALLOW Protected reserved 7 PE 16 External Interrupt Registers AE 16 Not EALLOW Protected reserved ELO ZR 64 GPIO Mux Registers 5 4 2 EALLOW Protected GPIO Data Registers he F
72. to a remote request message Automatic retransmission of a frame in case of loss of arbitration or error e 32 bit local network time counter synchronized by a specific message communication in conjunction with mailbox 16 Self test mode Operates in a loopback mode receiving its own message A dummy acknowledge is provided thereby eliminating the need for another node to provide the acknowledge bit NOTE For a SYSCLKOUT of 150 MHz the smallest bit rate possible is 23 4 kbps The 28x CAN has passed the conformance test per ISO DIS 16845 Contact TI for further details Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Peripherals 65 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 eCANOINT eCANI1INT Enhanced CAN Controller Message Controller Mailbox RAM 512 Bytes 32 Message Mailbox of 4 x 32 Bit Words eCAN Protocol Kernel TEXAS INSTRUMENTS www ti com Controls Address Data 32 Memory Management Unit CPU Interface Receive Control Unit Timer Management Unit eCAN Memory 512 Bytes Registers and Message Objects Control Receive Buffer Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3 3 V CAN Transceiver CAN Bus Figure 4 7 eCAN Block Diagram and Interface Circuit Table 4 5 3 3 V eCAN Transceivers for the SM320F
73. to be 0 0 1 1 A7 B7 and not in other combinations such as A1 B3 etc Sample n Sample 1 Analog Input on Channel Ax Analog Input on Channel Bv anccok U LT LT U LT U UF US LT LT Sample and Hold SH Pulse SMODE Bit k gt ta SH 4 gt t dschAQ_n 1 ADC Event Trigger from 1 4 3 EV or Other Sources 1 f taschaon 4 tdschBO_n 1 gt Figure 6 40 Simultaneous Sampling Mode Timing Table 6 51 Simultaneous Sampling Mode Timing AT 25 MHz ADC SAMPLE n SAMPLE n 1 CLOCK REMARKS 40 ns t Delay time from event 2 51 SH trigger to sampling SPe ADCCLK Sample Hold 1 Acqps x _ value 0 15 tsH width Acquisition Width 40 ns with Acqps 0 ADCTRL1 8 11 Delay time for first result la schAO n to appear in Result 4tc ADCCLK 160 ns register Delay time for first result la schBO n to appear in Result Stc ADCCLK 200 ns register Delay time for successive ta schAO_n 1 results to appear in Result zu x 120 ns register c ADCCLK 1 Not production tested 140 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APR
74. watchdog counter within a certain time frame otherwise the watchdog generates a reset to the processor The watchdog can be disabled if necessary 3 2 14 Peripheral Clocking The clocks to each individual peripheral can be enabled disabled so as to reduce power consumption when peripheral is not in use Additionally the system clock to the serial ports except eCAN and the event managers CAP and QEP blocks can be scaled relative to the CPU clock This enables the timing of peripherals to be decoupled from increasing CPU clock speeds 3 2 15 Low Power Modes The F2812 device is a full static CMOS device Three low power modes are provided IDLE Place CPU into low power mode Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating An enabled interrupt from an active peripheral wakes the processor from IDLE mode STANDBY Turn off clock to CPU and peripherals This mode leaves the oscillator and PLL functional An external interrupt event wakes the processor and the peripherals Execution begins on the next valid cycle after detection of the interrupt event 34 Functional Overview Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 HALT Turn off oscillator This mode basically shuts down the device
75. 0 4 2 Event Manager Modules EVA EVB The event manager modules include general purpose GP timers full compare PWM units capture units and quadrature encoder pulse QEP circuits EVA and EVB timers compare units and capture units function identically However timer unit names differ for EVA and EVB Table 4 2 shows the module and signal names used Table 4 2 shows the features and functionality available for the event manager modules and highlights EVA nomenclature Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h The paragraphs in this section describe the function of GP timers compare units capture units and QEPs using EVA nomenclature These paragraphs are applicable to EVB with regard to function however module signal names would differ Table 4 3 lists the EVA registers For more information see the TMS320x281x DSP Event Manager EV Reference Guide literature number SPRUO65 Table 4 2 Module and Signal Names for EVA and EVB EVA EVB EVENT MANAGER MODULES MODULE SIGNAL MODULE SIGNAL GP Timers GP Timer 1 T1PWM T1CMP GP Timer 3 T3PWM T3CMP GP Timer 2 T2PWM T2CMP GP Timer 4 T4PWM T4CMP Compare 1 PWM1 2 Compare 4 PWM7 8 Compare Units Compare 2 PWM3 4 Compare 5 PWMS9 10 Compare 3 PWM5 6 Compare 6 PWM11 12 Capture 1 CAP1 Capture 4 CAP4 Capture Units Capture 2 CAP2 Capture 5 CAP5 Capture 3 CAP3 Capture 6 CAP6 QEP1 QEP3 QEP Cha
76. 0 Texas Instruments Incorporated Peripherals 71 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com Table 4 7 McBSP Register Summary continued ADDRESS TYPE RESET VALUE 0x00 78xxh HEX DESCRIETION FIFO MODE REGISTERS applicable only in FIFO mode FIFO Data Registers McBSP Data Receive Register 2 Top of receive FIFO DRR2 00 0 0000 Read First FIFO pointers does not advance McBSP Data Receive Register 1 Top of receive FIFO pod oi Read Second for FIFO pointers to advance McBSP Data Transmit Register 2 Top of transmit FIFO DARE 02 ui 0x0000 Write First FIFO pointers does not advance McBSP Data Transmit Register 1 Top of transmit FIFO DARI 03 ii 0x000 Write Second for FIFO pointers to advance FIFO Control Registers MFFTX 20 R W 0xA000 McBSP Transmit FIFO Register MFFRX 21 R W 0x201F McBSP Receive FIFO Register MFFCT 22 R W 0x0000 McBSP FIFO Control Register MFFINT 23 R W 0x0000 McBSP FIFO Interrupt Register MFFST 24 R W 0x0000 McBSP FIFO Status Register 1 FIFO pointers advancing is based on order of access to DRR2 DRR1 and DXR2 DXR1 registers 72 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1
77. 02C 1 RX I O control CANTSC 0x00 602E 1 Time stamp counter Reserved in SCC mode CANTOC 0x00 6030 1 Time out control Reserved in SCC mode CANTOS 0x00 6032 1 Time out status Reserved in SCC mode 1 68 These registers are mapped to Peripheral Frame 1 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 4 5 Multichannel Buffered Serial Port McBSP Module The McBSP module has the following features Compatible to McBSP in TMS320C54x TMS320C55x DSP devices except the DMA features Full duplex communication Double buffered data registers which allow a continuous data stream Independent framing and clocking for receive and transmit External shift clock generation or an internal programmable frequency shift clock A wide selection of data sizes including 8 12 16 20 24 or 32 bits 8 bit data transfers with LSB or MSB first Programmable polarity for both frame synchronization and data clocks Highly programmable internal clock and frame generation Support A bis mode Direct interface to industry standard CODECs Analog Interface Chips AICs and other serially connected A D and D A devices Works with SPI compatible devices Two 16 x 16 level FIFO for Transmit channel Two 16 x 16 level FIFO for Receive channel The following application inte
78. 1 M S H 12 Bit Result Reg 7 70AFh ADC Module Result Reg 8 70B0h ADCINBO ADCINB7 Result Reg 15 70B7h ADC Control Registers Sequencer 1 Sequencer 2 Figure 4 4 Block Diagram of the F2812 ADC Module To obtain the specified accuracy of the ADC proper board layout is very critical To the best extent possible traces leading to the ADCIN pins should not run in close proximity to the digital signal paths This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs Furthermore proper isolation techniques must be used to isolate the ADC module power pins Vppai Vppa2 AVppnerao from the digital supply Figure 4 5 shows the ADC pin connections for the F2812 device NOTE 1 The ADC registers are accessed at the SYSCLKOUT rate The internal timing of the ADC module is controlled by the high speed peripheral clock HSPCLK 2 The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows ADCENCLK On reset this signal is low While reset is active low XRS the clock to the register still functions This is necessary to make sure all registers and modes go into their default reset state The analog module is in a low power inactive state As soon as reset goes high then the clock to the registers is disabled When the user sets the ADCENCLK signal high then the clocks to the registers is enabled and the analog module is enabled There i
79. 1 and 2 are identical 32 bit timers with presettable periods and with 16 bit clock prescaling The timers have a 32 bit count down register which generates an interrupt when the counter reaches zero The counter is decremented at the CPU clock speed divided by the prescale value setting When the counter reaches zero it is automatically reloaded with a 32 bit period value CPU Timer 2 is reserved for Real Time OS RTOS BIOS applications CPU Timer 1 is also reserved for TI system functions CPU Timer 2 is connected to INT14 of the CPU CPU Timer 1 can be connected to INT13 of the CPU CPU Timer 0 is for general use and is connected to the PIE block 3 2 19 Control Peripherals The F2812 supports the following peripherals which are used for embedded control and communication EV The event manager module includes general purpose timers full compare PWM units capture inputs CAP and quadrature encoder pulse QEP circuits Two such event managers are provided which enable two three phase motors to be driven or four two phase motors The event managers on the F2812 is compatible to the event managers on the 240x devices with some minor enhancements ADC The ADC block is a 12 bit converter single ended 16 channels It contains two sample and hold units for simultaneous sampling Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 35 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1
80. 10 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT SCIRXD Peripherals 75 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 4 7 Serial Peripheral Interface SPI Module The F2812 device includes the four pin serial peripheral interface SPI module The SPI is a high speed synchronous serial I O port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmable bit transfer rate Normally the SPI is used for communications between the DSP controller and external peripherals or another processor Typical applications include external I O or peripheral expansion through devices such as shift registers display drivers and ADCs Multidevice communications are supported by the master slave operation of the SPI The SPI module features include Four external pins SPISOMI SPI slave output master input pin SPISIMO SPI slave input master output pin SPISTE SPI slave transmit enable pin SPICLK SPI serial clock pin NOTE All four pins can be used as GPIO if the SPI module is not used Two operational modes master and slave Baud rate 125 different programmable rates Baud rate LSPCLK when BRR 0 SPIBRR 1 LSPCLK when BRR 0 1 2 3 4 Serial port performance is limited by I O buffer switching speed Internal prescalers mus
81. 108 Copyright 2009 2010 Texas Instruments Incorporated List of Figures 5 SM320F2812 HT 13 TEXAS INSTRUMENTS SGUSO62A JUNE 2009 REVISED APRIL 2010 www ti com 6 23 General Purpose Input 6 einciasicie 109 6 24 SPI Master Mode External Timing Clock Phase 0 20 4 2422 2 22 2222 222 22 2 110 6 25 SPI Master External Timing Clock Phase 1 nnne nnn nnn 112 6 26 SPI Slave Mode External Timing Clock Phase 0 1 1 112 2 114 6 27 SPI Slave Mode External Timing Clock Phase 1 11 116 6 28 Relationship Between XTIMCLK and SYSCLKOUT 6 6 120 6 29 Example Read Access 122 6 30 Example Write Access 2 7 2 122222 2 42 2422 022024 0 0 0 0 402 2222 2 2 2 2 124 6 31 Example Read With Synchronous XREADY Access 126 6 32 Example Read With Asynchronous XREADY Jar 6 33 Write With Synchronous XREADY meme se nemen en senes nn nnns 129
82. 15 8 is read as zeros Writing to the upper byte has no effect 76 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Enhanced feature e 16 level transmit receive FIFO Delayed transmit control The SPI port operation is configured and controlled by the registers listed in Table 4 10 Table 4 10 SPI Registers NAME ADDRESS SIZE x16 DESCRIPTION SPICCR 0x00 7040 1 SPI Configuration Control Register SPICTL 0x00 7041 1 SPI Operation Control Register SPISTS 0x00 7042 1 SPI Status Register SPIBRR 0x00 7044 1 SPI Baud Rate Register SPIRXEMU 0x00 7046 1 SPI Receive Emulation Buffer Register SPIRXBUF 0x00 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x00 7048 1 SPI Serial Output Buffer Register SPIDAT 0x00 7049 1 SPI Serial Data Register SPIFFTX 0x00 704A 1 SPI FIFO Transmit Register SPIFFRX 0x00 704B 1 SPI FIFO Receive Register SPIFFCT 0x00 704C 1 SPI FIFO Control Register SPIPRI 0x00 704F 1 SPI Priority Control Register 1 The 2 registers are mapped to Peripheral Frame 2 This space only allows 16 bit accesses 32 bit accesses produce undefined results Copyright 2009 2010 Texas Instruments Incorporated Peripherals 77 Submit Documentation Feedback Product Folder Link s SM320F2812 HT 78 5
83. 2 4 PWM Waveform Generation 1 2 58 4 2 5 Double Update PWM Mode 58 4 2 6 PWM Characteristics 1 1 1 1 16 59 4 2 7 Capture 1 1 1 6666 6 59 42 8 Quadrature Encoder Pulse QEP Circuit 59 4 2 9 External ADC Start of Conversion 1 59 4 3 Enhanced Analog to Digital Converter ADC Module 60 4 4 Enhanced Controller Area Network eCAN Module 1 1 1 3 65 4 5 Multichannel Buffered Serial Port McBSP Module 69 4 6 Serial Communications Interface SCI Module III I Inn 73 4 7 Serial Peripheral Interface SPI Module 76 28 c 79 5 52 222 2222
84. 2812 DSP PART NUMBER ace EA VREF OTHER SN65HVD230 3 3 V Standby Adjustable Yes 40 C to 85 C SN65HVD230Q 3 3 V Standby Adjustable Yes 40 C to 125 C SN65HVD231 3 3 V Adjustable Yes 40 to 85 C SN65HVD231Q 3 3 Adjustable Yes 40 C to 125 C SN65HVD232 3 3 V None None None 40 C to 85 SN65HVD232Q 3 3 V None None None 40 C to 125 C SN65HVD233 3 3 V Standby Adjustable None Diagnostic Loopback 40 C to 125 C SN65HVD234 3 3 V Standby amp Sleep Adjustable None 40 C to 125 C SN65HVD235 3 3 V Standby Adjustable None Autobaud Loopback 40 C to 125 C 66 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 6000h 603Fh 6040h 607Fh 6080h 60BFh 60COh 60FFh 6100h 6107h 6108h 610Fh 6110h 6117h 6118h 611Fh 6120h 6127h 61E0h 61E7h 61E8h 61EFh 61F0h 61F7h 61F8h 61FFh eCAN Memory 512 Bytes Control and Status Registers SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 eCAN Control and Status Registers Mailbox Enable CANME Mailbox Direction CANMD Transmission Request Set CANTRS Transmission Request Reset CANTRR Transmission Acknowledge CANTA Abort Acknowledge CANAA Received Message Pending CANRMP Received Mess
85. 555555555 5 RK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK NOTES A All XINTF accesses lead period begin on the rising edge of XCLKOUT When necessary the device inserts an alignmentcycle before an access to meet this requirement B During alignment cycles all signals transitions to their inactive state C For USEREADY 0 the external XREADY input signal is ignored D XA 0 18 holds the last address put on the bus during inactive cycles including alignment cycles Figure 6 29 Example Read Access 122 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com XTIMING register parameters used for this example SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 21 20 20 0 0 N A N A N A N A 1 Don t care for this example 6 24 External Interface Write Timing Table 6 36 External Memory Interface Write Switching Characteristics PARAMETER MIN MAX UNIT ta xCOH XZCSL Delay time XCLKOUT high to zone chip select active low 1 ns la XCOHL XZCSH Delay time XCLKOUT high or low to zone chip select inactive high 2 3 ns td XCOH XA Delay time
86. 6 21 External Interface XINTF Timing Each XINTF access consists of three parts Lead Active and Trail The user configures the Lead Active Trail wait states in the XTIMING registers There is one XTIMING register for each XINTF zone Table 6 25 shows the relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of XTIMCLK cycles Table 6 25 Relationship Between Parameters Configured XTIMING and Duration of Pulse 2 3 DURATION ns DESCRIPTION X2TIMING 0 X2TIMING 1 LR Lead period read access XRDLEAD XRDLEAD x 2 x tecxtim AR Active period read access XRDACTIVE WS 1 x XRDACTIVE x 2 WS 1 x tcxriv TR Trail period read access XRDTRAIL x textim XRDTRAIL x 2 x tcxriM LW Lead period write access XWRLEAD terxtim XWRLEAD x 2 x tecxtim AW Active period write access XWRACTIVE WS 1 XWRACTIVE x 2 WS 1 x tcxriM TW Trail period write access XWRTRAIL x tecxtim XWRTRAIL x 2 x lt 1 Not production tested 2 XTIM Cycle time XTIMCLK 3 WS refers to the number of wait states inserted by hardware when using XREADY If the zone is configured to ignore XREADY USEREADY 0 then WS 0 Minimum wait state requirements must be met when configuring each zone s XTIMING register These requirements are in addition to any timing requirements as
87. 6 7 for power sequencing of Vppalo Vppa1 Vppa2 AVppREFBG and VppavrL 2 Group 2 pins are as follows XINTF pins PDPINTA XCLKOUT EMUO and EMU1 In Revision C EVA GPIOAO0 GPIOA15 and GPIODO are 4 mA drive 6 3 Electrical Characteristics Over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT lon louMAX 2 4 V High level output voltage V OH 9 9 lon 50 pA VoL Low level output voltage lo MAX 0 4 V 1 06 including XRS Input With pullup 3 3 V except EVB b E NL gt Current GPIOB EVB 13 25 gs low level With pulldown Vppio 3 3 V 20 V 2 Input With pullup Vppio 3 3 V Vin Vpp 2 E H high With pulldown 3 3 V 28 50 80 level Vin Output current loz high impedance state off state VO or 0 V 2 pA Input capacitance 7 pF Co Output capacitance 7 pF 1 Minimum and maximum parameters are characterized for operation at TA 220 C unless otherwise noted but may not be production tested at that temperature Production test limits with statistical guardbands are used to ensure high temperature performance The following pins have no internal PU PD GPIOEO GPIOE1 GPIOFO0 GPIOF1 GPIOF2 GPIOF3 GPIOF12 GPIOG4 and GPIOGS 3 The following pins have an internal pull
88. 6 Effective Number of Bits ENOB 1 1 2 2 141 6 29 8 7 Total Harmonic Distortion THD 4 4 141 6 29 8 8 Spurious Free Dynamic Range SFDR 22 2 22 1 141 6 30 Multichannel Buffered Serial Port McBSP Timing 6 142 6 30 1 McBSP Transmit and Receive Timing 142 6 30 2 McBSP as SPI Master or Slave Timing mnm mener 145 6 31 Flash Timing he sse s ss 149 6 31 1 Recommended Operating Conditions 4 4 44 lt 149 7 151 4 Contents Copyright 2009 2010 Texas Instruments Incorporated TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 APRIL 2010 List of Figures 2 1 SM320F2612 DIS E3VOUL soe ee ec eo me eoa eua eese cox eu ue ue E eR NE 15 2 2 SM320F2812 172 Pin HFG CQFP Top 16 3 1 Functional Block 28 3 2 F2812 Memory Map See Notes A Through G
89. 6 reserved reserved McBSP McBSP reserved reserved SPI SPI INT7 reserved reserved reserved reserved reserved reserved reserved reserved INT8 reserved reserved reserved reserved reserved reserved reserved reserved INT9 reserved reseed ECAN1INT ECANOINT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA CAN CAN SCI B SCI B SCI A SCI A INT10 reserved reserved reserved reserved reserved reserved reserved reserved INT11 reserved reserved reserved reserved reserved reserved reserved reserved INT12 reserved reserved reserved reserved reserved reserved reserved reserved 1 Out of the 96 possible interrupts 45 interrupts are currently used the remaining interrupts are reserved for future devices However these interrupts can be used as software interrupts if they are enabled at the PIEIFRx level Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 43 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS Table 3 11 PIE Configuration and Control Registers www ti com NAME ADDRESS SIZE x16 DESCRIPTION PIECTRL 0x0000 0CEO 1 PIE Control Register PIEACK 0x0000 0CE1 1 PIE Acknowledge Register PIEIER1 0x0000 0CE2 1 PIE INT1 Group Enable Register PIEIFR1 0x0000 0CE3 1 PIE INT1 Group Fla
90. 62 42 6 3306 9 VO Z PU XD 14 136 152 42 6 4277 3 VO Z PU XD 13 95 110 4194 1 5057 5 VO Z PU XD 12 94 109 4318 1 5057 5 VO Z PU XD 11 72 85 5361 5 3382 2 VO Z PU XD 10 71 84 5361 5 3258 3 VO Z PU XDI9 67 77 5361 5 2608 4 VO Z PU XD 8 64 74 5361 5 2312 1 VO Z PU 16 bit XINTF Data Bus XD 7 53 60 5361 5 1045 9 VO Z PU XD 6 38 45 4586 0 42 6 VO Z PU XDI 5 35 42 4281 2 42 6 VO Z PU 32 39 3966 6 42 6 VO Z PU XD 3 29 36 3652 0 42 6 VO Z PU XD 2 26 33 3337 5 42 6 VO Z PU XD 1 23 30 3022 9 42 6 VO Z PU XD 0 20 27 2708 3 42 6 VO Z PU 1 Typical drive strength of the output buffer for all pins is 4 mA except for XCLKOUT XINTF EMUO and EMU1 pins which are 8 mA 2 I Input O Output Z High impedance 3 PU pin has internal pullup PD pin has internal pulldown Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Introduction 17 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com Table 2 3 Signal Descriptions continued NAME PIN NO 172 PIN HFG DIE PAD NO DIE PAD X CENTER um DIE PAD Y CENTER 10 22 Pu PD DESCRIPTION XMP MC 17 23 2308 2 42 6 PD Microprocessor Microcomputer Mode Select Switches between microprocessor and microcomputer mode When high Zone 7 is enabled on the external inter
91. 75 MHz 37 5 MHz Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Electrical Specifications 119 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6 28 XTIMINGO XTIMING1 XTIMING2 LEAD ACTIVE TRAIL gt 6 XTIMING7 C28x SYSCLKOUT XCLKOUT CPU XTIMCLK XINTCNF2 XINTCNF2 XTIMCLK CLKOFF XINTCNF2 CLKMODE t Default Value after reset Figure 6 28 Relationship Between XTIMCLK and SYSCLKOUT 120 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 22 XINTF Signal Alignment to XCLKOUT For each XINTF access the number of lead active and trail cycles is based on the internal clock XTIMCLK Strobes such as XRD XWE and zone chip select XZCS change state in relationship to the rising edge of XTIMCLK The external clock XCLKOUT can be configured to be either equal to or one half the frequency of XTIMCLK For the case where XCLKOUT XTIMCLK all of the XINTF strobes changes state with respect to the rising edge of XCLKOUT For the case where XCLKOUT one half XTIMCLK some strob
92. 832 3 42 6 2 GPIO or transmitted serial data GPIOF13 I 19 26 2613 0 42 6 2 GPIO or received serial data GPIOF OR XF CPU OUTPUT SIGNAL GPIOF 14 XF_XPLLDIS 0 137 153 42 6 4153 3 2 This pin has three functions 1 General purpose output pin 2 XPLLDIS This pin is sampled during reset to check if the PLL needs to be disabled The PLL will be disabled if this pin is sensed low HALT and STANDBY modes cannot be used when the PLL is disabled 3 GPIO GPIO function Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Introduction 25 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Signal Descriptions Continued 4 continued TEXAS INSTRUMENTS www ti com PIN NO PERIPHERAL DIE PAD Q 3 GPIO SIGNAL mM DIE PAD NO X CENTER Y CENTER VO Z PU PD DESCRIPTION GPIOG OR SCI B SIGNALS GPIO or SCI GPIOG4 SCITXDB 88 102 5098 0 5057 5 VO Z asynchronous serial port transmit data GPIO or SCI GPIOG5 SCIRXDB I 89 103 5003 3 5057 5 VO Z asynchronous serial port receive data NOTE Other than the power supply pins no pin should be driven before the 3 3 V rail has reached recommended operating conditions 26 Introduct
93. 9 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 3 2 Brief Descriptions 3 2 1 C28x CPU The C28x DSP generation is the newest member of the TMS320C2000 DSP platform The C28x is source code compatible to the 24x 240x DSP devices hence existing 240x users can leverage their significant software investment Additionally the C28x is a very efficient engine hence enabling users to develop not only their system control software in a high level language but also enables math algorithms to be developed using C C The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices This efficiency removes the need for a second processor in many systems The 32 x 32 bit MAC capabilities of the C28x and its 64 bit processing capabilities enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating point processor solution Add to this the fast interrupt response with automatic context save of critical registers resulting in a device that is capable of servicing many asynchronous events with minimal latency The C28x has an 8 level deep protected pipeline with pipelined memory accesses This pipelining enables the C28x to execute at high speeds without resorting t
94. AIO Analog 3 3 V ADC Analog I O Power Analog Ground 1 8 V Can use the same 1 8 V or 1 9 V Digital Ground supply as the digital core but separate the two with a ferrite bead or a filter ADC Digital Power Vssi NOTES A External decoupling capacitors are recommended on all power pins Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance Use 24 9 for ADC clock range 1 18 75 MHz use 20 for ADC clock range 18 75 25 MHz It is recommended that buffered external references be provided with a voltage difference of ADCREFP ADCREFM 21V 0 1 or better Dou External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up In this mode the accuracy of external reference is critical for overall gain The voltage ADCREFP ADCREFM determines the overall accuracy Do not enable internal references when external references are connected to ADCREFP and ADCREFM See the TMS320x281x DSP Analog to Digital Converter ADC Reference Guide literature number SPRUO60 for more information Figure 4 6 ADC Pin Connections With External Reference Copyright 2009 2010 Texas Instruments Incorporated Peripherals 63 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com The ADC operation is configured controlled and monitored by the registers
95. C Internal Timer 1 Compare Logic TiCTRIP PDPINTA T2CTRIP C2TRIP C3TRIP T1CON 1 EVASOC ADC External T1CON 15 11 6 3 2 Full Compare 1 Output SVPWM Full Compare 2 State Machine Full Compare 3 Peripheral Bus ACTRA 11 0 Output Logic COMCONA 15 5 2 0 ACTRA 15 12 DBTCONA 15 0 Timer 2 Compare COMCONA 12 i T1CON 13 11 T2PWM_T2CMP gt T2CON 5 4 GPTCONA 3 2 Prescaler T2CON 10 8 TCLKINA HSPCLK QEPDIR TDIRA CAP1_QEP1 Capture Units t 5 2 2 CAP3 QEPI1 Index Qual lt CAPCONA 15 12 7 0 A The EVB module is similar to the EVA module EXTCONA 1 2 Figure 4 3 Event Manager A Functional Block Diagram See Note A Copyright 2009 2010 Texas Instruments Incorporated Peripherals 57 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 4 2 1 General Purpose GP Timers There are two GP timers The GP timer x x 1 or 2 for EVA x 3 or 4 for EVB includes A 16 bit timer up down counter TxONT for reads or writes A 16 bit timer compare register TxCMPR double buffered with shadow register for reads or writes
96. CLKOUT high low to XRD inactive high 2 1 ns thoxA XZCSH Hold time address valid after zone chip select inactive high 2 ns thoxayxRD Hold time address valid after XRD inactive high 2 ns 1 Not production tested 2 During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles Table 6 35 External Memory Interface Read Timing Requirements MIN MAX UNIT Access time read data from address valid LR AR 14 ns ta XRD Access time read data valid from XRD active low AR 120 ns lsu XD XRD Setup time read data valid before XRD strobe inactive high 12 ns th XD XRD Hold time read data valid after XRD inactive high 0 ns 1 Not production tested 2 LR Lead period read access AR Active period read access See Table 6 25 Active Trail gt XCLKOUT XTIMCLK _f L S US Vf VJ VPLS VS XCLKOUT 1 2 XTIMCLK WE Lc cun PES ea a de ta XCOH XZCSL XZCSOAND1 XZCS2 taxcoHL xzcsH XZCS6AND7 lt ta xcoH XA i XA 0 18 j 7 7 K tqxcoHL XRDH 09 _ i i XR W o le taa taxrp 2 4 thoxpyxrD x15 XREADY 5555555 555555555552 855 5 555555555555 5 555555555555 5 555 555 555 5555555 55555 5 5
97. CLKX ext 14 ns Only applies to first bit transmitted when in Data DXENA 4 CLKX int P 8 Delay 1 or 2 XDATDLY 01b or 10b modes CLKX ext 14 int 0 Enable time CLKX high to DX driven DXENA 0 ME CLKX ext 6 en CKXH DX ns Only applies to first bit transmitted when in Data DXENA 1 CLKX int P Delay 1 or 2 XDATDLY 01b or 10b modes CLKX ext P 6 FSX int 8 Delay time FSX high to DX valid DXENA 0 14 d FXH DXV ns Only applies to first bit transmitted when in Data DXENA 4 FSX int P 8 Delay 0 XDATDLY 00b mode FSxX ex P 414 FSX int 0 Enable time FSX high to DX driven DXENA 0 FSX ext 6 M10 ten ExH DX 2 ns Only applies to first bit transmitted when in Data DXENA 4 FSX int Delay 0 XDATDLY 00b mode ESX ext P46 1 Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing references of that signal are also inverted 2P 1 CLKG in ns 3 Not production tested low pulse width P D CLKRX high pulse width P Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 143 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS 1 M11 k gt M2 M12 M13 gt 4 3 M12 CLKR ye M4 gt M4 14 lt CI 0 0 00 MSN
98. DPINTB pin status is reflected in bit 8 of COMCONB register e EXTCON register bits provide options to individually trip control for each PWM pair of signals 4 2 7 Capture Unit The capture unit provides a logging function for different events or transitions The values of the selected GP timer counter are captured and stored in the two level deep FIFO stacks when selected transitions are detected on capture input pins CAPx x 1 2 or 3 for EVA and x 4 5 or 6 for EVB The capture unit consists of three capture circuits Capture units include the following features One 16 bit capture control register CAPCONx R W One 16 bit capture FIFO status register CAPFIFOx Selection of GP timer 1 2 for EVA or 3 4 for EVB as the time base Three 16 bit 2 level deep FIFO stacks one for each capture unit Three capture input pins CAP1 2 3 for EVA CAP4 5 6 for EVB one input pin per capture unit All inputs are synchronized with the device CPU clock In order for a transition to be captured the input must hold at its current level to meet the input qualification circuitry requirements The input pins CAP1 2 and CAP4 5 can also be used as inputs to the circuit User specified transition rising edge falling edge or both edges detection Three maskable interrupt flags one for each capture unit The capture pins can also be used as general purpose interrupt pins if they are not used for the capture
99. E 32 Not EALLOW Protected ADC Registers 1 i 32 Not EALLOW Protected reserved DIN AE 736 EV A Registers on DOR 64 Not EALLOW Protected reserved 7 PER 192 EV B Registers Hee TUE 64 Not EALLOW Protected reserved Hen TR 528 SCI B Registers Mr E 16 Not EALLOW Protected reserved a 2 160 McBSP Registers T 64 Not EALLOW Protected reserved od 1984 1 Peripheral Frame 2 only allows 16 bit accesses All 32 bit accesses ignored invalid data be returned or written 38 Functional Overview Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 3 4 Device Emulation Registers SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals The registers are defined in Table 3 7 Table 3 7 Device Emulation Registers NAME ADDRESS RANGE SIZE x16 DESCRIPTION 0x00 0880 DEVICECNF 0x00 0881 2 Device Configuration Register reserved 0x00 0882 1 Not supported on Revision C and later silicon Device ID Register 0x0003 Silicon Rev C and D DEVICEID 0x00 0883 1 Device ID Register 0x0004 Reserved Device ID Register 0x0005 Silicon Rev E PROTSTART 0x00 0884 1 Block Protection Start Address Register PROTRANGE 0x00 0885 1 Block Protectio
100. Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third
101. F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 22 SPI Master Mode External Timing Clock Phase 1 2 9 SPI WHEN SPIBRR 1 SPI WHEN SPIBRR 1 IS EVEN OR IS ODD AND SPIBRR 0 OR 2 gt 3 high 0 5 0 5 0 5 LCO 10 0 5 0 5 co duet 2 low 0 5 0 5 0 5 LCO 10 0 5 0 51100 eae low 0 5 0 5te LCO 10 0 5tyseqm 0 ae di ser high 0 5 0 5te LCO 10 0 5tyseqm 0 Setup time SPISIMO data valid su SIMO SPCH M before SPICLK high clock 0 51 10 polarity 0 Setup time SPISIMO data valid u SIMO SPCL M before SPICLK low clock 0 51 10 polarity 1 0 5tespcym 10 5 T 10 5tesecym 10 c SPC M 10 4 Valid time SPISIMO data valid SPCH SIMO M after SPICLK high clock polarity 0 5 10 0 7 Valid time SPISIMO data valid v SPCL SIMO M after SPICLK low clock polarity 0 51 10 1 Setup time SPISOMI before isu SOMI SPCH M SPICLK high clock polarity 0 Setup time SPISOMI before u SOMI SPCL M SPICLK low clock polarity 1 0 5tespcym 10 Valid time SPISOMI data valid SPCH SOMIM after SPICLK high clock polarity 0 251
102. F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 20 SPI Slave Mode Timing Table 6 23 SPI Slave Mode External Timing Clock Phase 0 2 9 NO MIN MAX UNIT 12 1 Cycle time SPICLK Ateco 2 ns SPC LCO twiSPCH S Pulse duration SPICLK high clock polarity 0 0 5tspcyg 10 0 5tespc s 13 SPC SPC ns tw SPCL S Pulse duration SPICLK low clock polarity 1 0 10 0 5te sPC S tw SPCL S Pulse duration SPICLK low clock polarity 0 0 5 5 10 0 140 SPC SPC ns tw SPCH S Pulse duration SPICLK high clock polarity 1 0 5tyspc 10 0 5 lt 5 Delay time SPICLK high to SPISOMI valid 154 dSPCH SOMDS clock polarity 0 0 375tc spo s 10 E ta SPCL SOMI S Delay time SPICLK low to SPISOMI valid clock polarity 1 0 375tcspojs 10 t Valid time SPISOMI data valid after SPICLK low 0 751 16 v SPCL SOMI S clock polarity 0 SPC S Valid time SPISOMI data valid after SPICLK high 0 75t v SPCH SOMI S clock polarity 1 c SPC S tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 0 0 19 4 ns tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 1 0 t Valid time SPISIMO data valid after SPICLK low 0 51 20 v SPCL SIMO S clock polarity 0 5 5 t Valid time SPISIMO data valid after SPICLK high 0 51
103. FO for reducing servicing overhead 3 3 Register Map 36 The F2812 device contains three peripheral register spaces The spaces are categorized as follows Peripheral Frame 0 These are peripherals that are mapped directly to the CPU memory bus See Table 3 4 Peripheral Frame 1 These are peripherals that are mapped to the 32 bit peripheral bus See Table 3 5 Peripheral Frame 2 These are peripherals that are mapped to the 16 bit peripheral bus See Table 3 6 Functional Overview Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 3 4 Peripheral Frame 0 Registers NAME ADDRESS RANGE SIZE x16 ACCESS TYPE Device Emulation Registers 4 384 EALLOW protected reserved 128 FLASH Resists oa Code Security Module Registers Bi MEE 16 EALLOW protected reserved 2 SENE 48 XINTF Registers 32 Not EALLOW protected reserved a UOCE 192 CPU TIMERO 1 2 Registers do 2 64 Not EALLOW protected reserved REE 160 PIE Registers n 32 Not EALLOW protected PIE Vector Table 2 ODER 256 EALLOW protected Reserved d e 512 1 Registers in Frame 0 support 16 bit and 32 bit accesses 2 If registers are EALLOW protected then writes cannot be performed until the user executes
104. HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 24 SPI Slave Mode External Timing Clock Phase 1 2 3 NO MIN MAX UNIT 12 te SPC S Cycle time SPICLK 8tc LCO ns 1300 tw SPCH S Pulse duration SPICLK high clock polarity 0 O 5tcspo s 10 O 5tcisPc s ns tw SPCL S Pulse duration SPICLK low clock polarity 1 0 51 10 O 5tcsPc s 140 tw SPCL S Pulse duration SPICLK low clock polarity 0 O 5tcspo s 10 O 5tcsPc s ns tw SPCH S Pulse duration SPICLK high clock polarity 1 O 5tcspo s 10 O 5tcsPc s Setup time SPISOMI before SPICLK high clock polarity tsu SOMI SPCH S 0 gh y 0 125tcspc s p Setup time SPISOMI before SPICLK low clock polarit ns etup time efore ow clock polarity tsu SOMI SPCL S 1 P 0 12515 Valid time SPIS OMI data valid after SPICLK high 0 75t 13 v SPCH SOMI S clock polarity 0 s c SPC S ns t Valid time SPISOMI data valid after SPICLK low 075 v SPCL SOMI S clock polarity 1 c SPC S Setup time SPISIMO before SPICLK high clock polarity tsu SIMO SPCH S 0 P gh PERI 0 21 ns t Setup time SPISIMO before SPICLK low clock polarity 0 su SIMO SPCL S 1 i Valid time SPISIMO data valid after SPICLK high 0 5t SPCH SIMO S clock polarity 0 9 c SPC S 224 ns t Valid time SPISIMO data valid after SPICLK low 05 v SPCL SIMO S clock polarity 1 9 c SPC S spo
105. IL 2010 Table 6 51 Simultaneous Sampling Mode Timing continued AT 25 MHz ADC SAMPLE n SAMPLE n 1 CLOCK REMARKS t apccLk 40 ns Delay time for successive ld schBO n 1 results to appear in Result 3 Acqps x 120 ns register te ADCCLK 6 29 8 Definitions of Specifications and Terminology 6 29 8 1 Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale The point used as zero occurs 1 2 LSB before the first code transition The full scale point is defined as level 1 2 LSB beyond the last code transition The deviation is measured from the center of each particular code to the true straight line between these two points 6 29 8 2 Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value A differential nonlinearity error of less than 1 LSB ensures no missing codes 6 29 8 3 Zero Offset The major carry transition should occur when the analog input is at zero volts Zero error is defined as the deviation of the actual transition from that point 6 29 8 4 Gain Error The first code transition should occur at an analog value 1 2 LSB above negative full scale The last transition should occur at an analog value 1 1 2 LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last cod
106. IMCLK 2m 4 le ta xCOH XZCSL ta xCOHL XZCSH e 2 50 1 XZCS2 XZCS6AND7 i 1 e t d XCOH XA i th XRDYasynchH XZCSH gt Mig epu XRD 1 T 1 1 1 ke ta XCOHL XWEL gt ta xcoHL XWEH EN TUE RES ta xCOHL XRNWH i XWE gt ta xCOH XRNWL XR W 1 1 um n aid XD ten xD XWEL i K th xXD XWEH XD 0 15 S Y gt Isu XRDYasynchLXCOHL 4 fn XRDYasynchL f 55565560 D 4 RRR XREADY Asynch 1 4 See Note D i See Note E gt Legend Em Don t care Signal can be high or low during this time NOTES A All XINTF accesses lead period begin on the rising edge of XCLKOUT When necessary the device inserts an alignmentcycle before an access to meet this requirement B During alignment cycles all signals transitions to their inactive state C During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access can be calculated as XWRLEAD XWRACTIVE 3 n tsu XRDYasynchL XCOHL where n is the sample number n 1 2 3 and so forth E Reference for the first sample is with respect to this point X
107. KXH Setup time DR valid before CLKX high P 10 8P 10 ns 40 tnickxH DRV Hold time DR valid after CLKX high 10 8 10 ns M41 tsuEXL CKXH Setup time FSX low before CLKX high 16 10 ns M42 teckx Cycle time CLKX 2P 16P ns 1 Not production tested Table 6 57 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 0 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M34 tnickxL FXL Hold time FSX low after CLKX low P ns M35 d FXL CKXH Delay time FSX low to CLKX high 2P ns Disable time DX high impedance following last data bit M37 tdis CKXL DXHZ from CLKX low ga Mp 9 6 7P 6 ns M38 la FXL DXV Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 For all SPI slave modes CLKX has to be minimum eight CLKG cycles Also CLKG should be LSPCLK 2 by setting CLKSM CLKGDV 1 With maximum LSPCLK speed of 75 MHz CLKX maximum frequency is LSPCLK 16 that is 4 5 MHz and P 13 3 ns 9 M42 CLKX FSX LSB 41 4 MS p A M35 DR M39 mao Bito C Bini 0 X m3 na Figure 6 44 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 146 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812
108. L 2010 www ti com 6 20 SPI Slave Mode Timing sese ko RR TERT ER YR SR 113 6 21 External Interface XINTF Timing eee ee eee II I III II I I emn nne nen a a a a TIE 6 22 XINTF Signal Alignment to XCLKOUT 0 2 2 2 441666 66 121 6 23 External Interface Read Timing 66666 122 6 24 External Interface Write Timing n 123 6 25 External Interface Ready on Read Timing With One External Wait State 125 6 26 External Interface Ready on Write Timing With One External Wait State 128 6 27 XHOLD and XHOLDA sseisssessenswazarkbEawa 131 6 28 XHOLD XHOLDA Timing ny nu 132 6 29 Analog to Digital Converter n n en II mne nene nnn nennen 134 6 29 1 ADC Absolute Maximum Ratings 1 1 134 6 29 2 ADC Electrical Characteristics Over Recommended Operating Conditions
109. Managers EVA EVB software trigger or from an external ADCSOC signal If the SMODE bit is 0 the ADC does conversions on the selected channel on every Sample Hold pulse The conversion time and latency of the Result register update are explained below The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update The selected channel is sampled at every falling edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be one ADC clock wide minimum or 16 ADC clocks wide maximum Sample n 2 Sample n 1 Analog Input on Channel Ax or Bx Sample cleck Sample and Hold Le Ly Le SMODE Bit aa t gt lt p gt tdschx_n 1 4 ldschx ADC Event Trigger from EV or Other Sources uq c a 15 gt Figure 6 39 Sequential Sampling Mode Single Channel Timing 138 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 50 Sequential Sampling Mode Timing SAMPLE n SAMPLE n 1 AT 25 MHz ADC CLOCK tc apccLk 40 ns REMARKS Delay time from event trigger to laschx n 1 appear in the Result register Ic ADCCLK
110. McBSP Sample Rate Generator Register 1 MULTICHANNEL CONTROL REGISTERS MCR2 0 R W 0x0000 McBSP Multichannel Register 2 MCR1 00 R W 0x0000 McBSP Multichannel Register 1 RCERA R W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB OF R W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 10 R W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 11 R W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 12 R W 0x0000 McBSP Pin Control Register RCERC 13 R W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 14 R W 0x0000 McBSP Receive Channel Enable Register Partition D XCERC 15 R W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 16 R W 0x0000 McBSP Transmit Channel Enable Register Partition D RCERE 17 R W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 18 R W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 19 R W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 1A R W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 1B R W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 1C R W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 1D R W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 1E R W 0x0000 McBSP Transmit Channel Enable Register Partition H 1 DRR2 DRR1 and DXR2 DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode Copyright 2009 201
111. P3 VDD T4PWM_T4CMP XD 7 T3PWM_T3CMP Vss_ XR W PWM12 PWM11 PWM10 PWM9 PWM8 PWM7 Copyright 2009 2010 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com 2 5 Signal Descriptions SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 2 3 specifies the signals on the F2812 device All digital inputs are TTL compatible All outputs are 3 3 V with CMOS levels Inputs are not 5 V tolerant A 100 uA or 20 uA pullup pulldown is used Table 2 3 Signal Descriptions NO ip pap DIEPAD DIE PAD NAME 172 PIN NO X CENTER Y CENTER 10 20 PU PD DESCRIPTION HFG um um XINTF SIGNALS XA 18 154 173 42 6 2281 5 0 2 XA 17 152 171 42 6 2485 3 O Z XA 16 149 167 42 6 2819 6 0 2 XA 15 145 163 42 6 3182 9 O Z 14 141 157 42 6 3774 9 0 2 XA 13 138 154 42 6 4029 4 0 2 XA 12 135 151 42 6 4401 3 0 2 XA 11 129 145 255 7 5057 5 O Z XA 10 127 143 4744 5057 5 0 2 XA 9 122 138 996 5 5057 5 0 2 19 bit XINTF Address Bus XA 8 118 134 1492 4 5057 5 0 2 XA 7 116 131 1825 2 5057 5 0 2 6 109 124 2566 0 5057 5 O Z XA 5 106 121 2937 9 5057 5 0 2 XA 4 101 116 3518 7 5057 5 0 2 3 83 96 5361 5 4471 5 0 2 XA 2 78 91 5361 5 3927 2 0 2 1 42 49 5024 5 42 6 0 2 XA 0 18 24 2403 5 42 6 O Z XD 15 144 1
112. PIOA15 C3TRIP 1 121 137 1120 5 5057 5 Volz PU UNT 3 GPIOB OR EVB SIGNALS GPIOBO PWM7 O 44 51 5361 5 211 5 0 2 PU CUL GPIOB1 PWM8 O 45 52 5361 5 302 1 Volz PU CU ain bd GPIOB2 PWMe O 46 53 5361 5 392 7 Volz PU n GPIOB3 PWM10 O 47 54 5361 5 483 2 Volz PU 1 os GPIOB4 PWM11 O 48 55 5361 5 573 8 Volz PU ee 5 PWM12 O 49 56 5361 5 664 4 0 2 PU Ud ee GPIOB6 I 52 59 5361 5 955 3 Volz PU eid Tuners GPIOB7 TAPWM I 54 61 5361 5 1169 9 0 2 PU Ll 1 Typical drive strength of the output buffer for all pins except XCLKOUT XF XINTF EMUO and EMU1 pins is 4 mA typical 2 I Input Output Z High impedance 3 PU pin has internal pullup PD pin has internal pulldown Copyright 2009 2010 Texas Instruments Incorporated Introduction 23 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Signal Descriptions Continued 4 continued TEXAS INSTRUMENTS www ti com PIN NO PERIPHERAL DIE PAD 02 GPIO SIGNAL DIE PAD NO X CENTER Y CENTER 0 2 PU PD DESCRIPTION GPIOB8 CAP4_QEP3 56 64 5361 5 1428 4 Volz PU rain a eue GPIOB9 CAP5_QEP4 58 66 5361 5 1600 7 Volz PU r 42
113. Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 9 92 24V 80 20 0 4 V VoL Figure 6 5 Output Levels Output transition times are specified as follows Fora high to low transition the level at which the output is said to be no longer high is below 80 of the total voltage range and lower and the level at which the output is said to be low is 2096 of the total voltage range and lower Fora low to high transition the level at which the output is said to be no longer low is 20 of the total voltage range and higher and the level at which the output is said to be high is 8096 of the total voltage range and higher Figure 6 6 shows the input levels 20V Vin 90 10 0 8 V Figure 6 6 Input Levels Input transition times are specified as follows Fora high to low transition on an input signal the level at which the input is said to be no longer high is 9096 of the total voltage range and lower and the level at which the input is said to be low is 1096 of the total voltage range and lower Fora low to high transition on an input signal the level at which the input is said to be no longer low is 1096 of the total voltage range and higher and the level at which the input is said to be high is 9096 of the total voltage range and higher NOTE See the individual timi
114. Ready on Read 1 Wait State PARAMETER MIN MAX UNIT ta xCOH XZCSL Delay time XCLKOUT high to zone chip select active low 1 ns la XCOHL XZCSH Delay time XCLKOUT high low to zone chip select inactive high 2 3 ns la XCOH XA Delay time XCLKOUT high to address valid 2 ns la XCOHL XRDL Delay time XCLKOUT high low to XRD active low 1 ns ta XCOHL XRDH Delay time XCLKOUT high low to XRD inactive high 2 1 ns thoxA XZCSH Hold time address valid after zone chip select inactive high 2 ns thoxayxRD Hold time address valid after XRD inactive high ns 1 Not production tested 2 During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles Table 6 38 External Memory Interface Read Timing Requirements Ready on Read 1 Wait State MIN MAX UNIT Access time read data from address valid LR AR 14 ns la xRD Access time read data valid from XRD active low AR 12 ns lsu XD XRD Setup time read data valid before XRD strobe inactive high 12 ns th XD XRD Hold time read data valid after XRD inactive high 0 ns 1 Not production tested 2 LR Lead period read access AR Active period read access See Table 6 25 Table 6 39 Synchronous XREADY Timing Requirements Ready on Read 1 Wait State MIN UNIT lsu XRDYsynchL XCOHL Setup time XREADY Sync
115. SM320F2812 HT Digital Signal Processor Data Manual TEXAS INSTRUMENTS PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Literature Number SGUS062A June 2009 Revised April 2010 5 320 2812 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Contents 1 E 11 1 1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS 12 2 gm T 13 2 1 13 2 2 Device SUMMAN avant cant a UNAM ROV 14 2 3 Die t aor wa xa ea x KCN Rx e SR NR 19 2 4 Pin m 16 2 5 SIGMA DSSCMPOUONS iusso 17 3 22 22 2222 cate HMM 27 3 1 Memory 28 3 2 Brief 31 3 2 CPU RR OC ER GER ROC EROR AI TR PR ER RUE 31 3 2 2 Memory Bus Harvard Bus Architecture
116. T SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 47 AC Specifications TEXAS INSTRUMENTS www ti com 55 C to 125 C Ta 220 C PARAMETER UNIT TYP MAX TYP MAX SINAD Signal to noise ratio distortion 62 57 dB SNR Signal to noise ratio 62 57 dB THD Total harmonic distortion 68 68 dB ENOB SNR Effective number of bits 10 1 9 1 Bits SFDR Spurious free dynamic range 69 68 dB 1 Not production tested 2 Validated at the following conditions ADC Input Frequency 10 71 KHz XCLKIN 30 MHz PLLCR SYSCLK 150 MHz HSPCP 3 ADCCLK 25 MHz ADCCLKPS 1 ADCCLK 12 5 MHz CPS 0 ADCCLK 12 5 MHZ ACQ_PS SH 3 6 29 3 Current Consumption for Different ADC Configurations at 25 MHz ADCCLK Table 6 48 Current Consumption ADC OPERATING MODE CONDITIONS Mode A Operational Mode Iopa 2 Ipp1 40 mA 1 pA 0 5 mA BG and REF enabled PWD disabled 7 mA 0 5 Mode B clock enabled BG and REF enabled PWD enabled 1 0 5 Mode C ADC clock enabled BG and REF disabled PWD enabled 1 0 Mode D ADC clock disabled BG and REF disabled PWD enabled 1 Not production tested ADC module clock 25 MHz ADC performing a continuous conversion of all 16 channels in Mode A 136 Electrical S
117. T lt 25 MHz ADC clock lt SYSCLKOUT 2 4 The INL degrades for frequencies beyond 18 75 MHz 25 MHz Applications that require these sampling rates should use a 20 resistor as bias resistor on the ADCRESEXT pin This improves overall linearity and typical current drawn by the ADC is a few mA more than 24 9 kW bias 1 LSB has the weighted value of 3 0 4096 0 732 mV A single internal band gap reference 5 accuracy sources both ADCREFP and ADCREFM signals and hence these voltages track together The ADC converter uses the difference between these two as its reference The total gain error is the combination of the gain error shown here and the voltage reference accuracy ADCREFP ADCREFM software based calibration procedure is recommended for better accuracy See F2812 ADC Calibration Application Note literature number SPRA989 and Section 5 2 Documentation Support for relevant documents 7 In this mode the accuracy of external reference is critical for overall gain The voltage difference ADCREFP ADCREFM determines the overall accuracy 8 Voltages above Vppa 0 3 V or below 0 3 V applied to an analog input pin may temporarily affect the conversion of another pin To avoid this the analog inputs should be kept within these limits 99 Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 135 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 H
118. TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 4 6 Serial Communications Interface SCI Module The F2812 device include two serial communications interface SCI modules The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non return to zero NRZ format The SCI receiver and transmitter are double buffered and each has its own separate enable and interrupt bits Both can be operated independently or simultaneously in the full duplex mode To ensure data integrity the SCI checks received data for break detection parity overrun and framing errors The bit rate is programmable to over 65 000 different speeds through a 16 bit baud select register Features of each SCI module include Two external pins SCITXD SCI transmit output pin SCIRXD SCI receive input pin NOTE Both pins can be used as GPIO if not used for SCI Baud rate programmable to 64K different rates Baud rate LSPCLK when BRR 0 1 8 LSPCLK when BRR 0 16 Data word format One start bit Data word length programmable from one to eight bits Optional even odd no parity bit One or two stop bits Four error detection flags parity overrun framing and break detection Two wake up multiprocessor modes idle line and address bit Half or full duplex operation e Double buffered receive and transmit funct
119. TORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS MOREOVER EXCEPT AS SET FORTH ABOVE TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Functional Overview 33 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com IN NO EVENT SHALL BE LIABLE FOR ANY CONSEQUENTIAL SPECIAL INDIRECT INCIDENTAL OR PUNITIVE DAMAGES HOWEVER CAUSED ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES EXCLUDED DAMAGES INCLUDE BUT ARE NOT LIMITED TO LOSS OF DATA LOSS OF GOODWILL LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS 3 2 10 Peripheral Interrupt Expansion PIE Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs The PIE block can support up to 96 peripheral interrupts On the F2812 45 of the possible 96 interrupts are used by peripherals The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines INT1 to INT12 Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user
120. WRLEAD XWRACTIVE 2 tcxriM Figure 6 34 Write With Asynchronous XREADY Access XTIMING register parameters used for this example XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE N A N A N A 1 0 21 3 21 Asynch 1 N A Don t care for this example 130 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 27 XHOLD and XHOLDA f the HOLD mode bit is set while XHOLD and XHOLDA are both low external bus accesses granted the XHOLDA signal is forced high at the end of the current cycle and the external interface is taken out of high impedance mode On a reset XRS the HOLD mode bit is set to 0 If the XHOLD signal is active low on a system reset the bus and all signal strobes must be in high impedance mode and the XHOLDA signal is also driven active low When HOLD mode is enabled and XHOLDA is active low external bus grant active the CPU can still execute code from internal memory If an access is made to the external interface the CPU is stalled until the XHOLD signal is removed An external DMA request when granted places the following signals in a high impedance mode XA 18 0 XZCSOAND1 XD 15 0 XZCS2 XWE XRD XZCS6AND7 XR W All o
121. While PLL is Stabilizing Changed CPU Frequency Frequency With the Desired Frequency This Period PLL Lock up Time tp is 131072 XCLKIN Cycles Long Figure 6 12 Effect of Writing Into PLLCR Register Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 99 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 6 15 Low Power Mode Wakeup Timing Table 6 10 is also the IDLE Mode Wake Up Timing Requirements table TEXAS INSTRUMENTS www ti com Table 6 10 IDLE Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t Pulse duration external wake up Without input qualifier 2 X tesco Cycles w WAKE INT signal With input qualifier 1 x tysco iar Cycles Delay time external wake signal to program execution resume Wake up from Flash m Flash module in active state Without input qualifier 8 x tesco Cycles Wake up from Flash TE 2 Flash module ih active sete With input qualifier 8 x tesco IQT Cycles la WAKE IDLE Wake up from Flash Flash module in sleep state Without input qualifier 1050 x tesco Cycles Wake up from Flash e 2 Flash module in sleep state With input qualifier 1050 tesco IQT Cycles Wake up from SARAM Without input qualifier 8 x tesco Cycles Wake up from SARAM With input qualifier 8 x
122. acing with TTL and CMOS compatible components as well as with mixed voltage ICs such as power transistor gate drivers Just like 5 V based designs good engineering practice should be exercised to minimize noise and EMI effects by proper component layout and PCB design when 3 3 V DSP ADC and digital circuitry are used in a mixed signal environment with high and low voltage analog and switching signals such as a motor control system In addition software techniques such as Random PWM method can be used by special features of the Texas Instruments TI TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation This application report reviews designs of 3 3 V DSP versus 5 V DSP for low HP motor control applications The application report first describes a scenario of a 3 3 V only motor controller indicating that for most applications no significant issue of interfacing between 3 3 V and 5 V exists Cost effective 3 3 V 5 V interfacing techniques are then discussed for the situations where such interfacing is needed On chip 3 3 V ADC versus 5 V ADC is also discussed Sensitivity and noise effects in 3 3 V and 5 V ADC conversions are addressed Guidelines for component layout and printed circuit board PCB design that can reduce system s noise and EMI effects are summarized in the last section The TMS320C28x Instruction Set Simulator Technical Overview literature number SPRU608 describes the simulator available
123. age Lost CANRML Local Acceptance Masks LAM 32 x 32 Bit RAM Remote Frame Pending CANRFP Global Acceptance Mask CANGAM Message Object Time Stamps MOTS 32 x 32 Bit RAM Master Control CANMC Bit Timing Configuration CANBTC Message Object Time Out MOTO 32 x 32 Bit RAM eCAN Memory RAM 512 Bytes Mailbox 0 Error and Status CANES Transmit Error Counter CANTEC Receive Error Counter CANREC Global Interrupt Flag 0 CANGIFO Global Interrupt Mask CANGIM Global Interrupt Flag 1 CANGIF1 Mailbox Interrupt Mask CANMIM Mailbox 1 Mailbox Interrupt Level CANMIL Mailbox 2 Overwrite Protection Control CANOPC Mailbox 3 TX Control CANTIOC Mailbox 4 RX Control CANRIOC Time Stamp Counter CANTSC Time Out Control CANTOC Time Out Status CANTOS Mailbox 28 Mailbox 29 Mailbox 30 Mailbox 31 61E8h 61E9h Reserved Message Mailbox 16 Bytes Message Identifier MSGID 61EAh 61EBh Message Control MSGCTRL 61ECh 61EDh Message Data Low MDL 61EEh 61EFh Message Data High MDH Figure 4 8 eCAN Memory Map Copyright 2009 2010 Texas Instruments Incorporated Peripherals 67 Submit Documentation Feedback Product Folder Link s SM320F2812 HT
124. al memory or trying to boot load some undesirable software that would export the secure memory contents To enable access to the secure blocks the user must write the correct 128 bit KEY value which matches the value stored in the password locations within the Flash ROM If the boot mode selected is Flash HO or OTP then no external code is loaded by the bootloader Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic PU pin has an internal pullup No PU pin does not have an internal pullup NOTE For code security operation all addresses between Ox3F7F80 and OxSF7FF5 cannot be used as program code or data but must be programmed to 0x0000 when the Code Security Passwords are programmed If security is not a concern then these addresses may be used for code or data The 128 bit password at Ox8F 7FF8 Ox3F 7FFF must not be programmed to zeros Doing So would permanently lock the device Code Security Module Disclaimer The Code Security Module CSM included on this device was designed to password protect the data stored in the associated memory either ROM or Flash and is warranted by Texas Instruments in accordance with its standard terms and conditions to conform to 5 published specifications for the warranty period applicable for this device TI DOES NOT HOWEVER WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA S
125. alid 2 ns la XCOHL XWEL Delay time XCLKOUT high low to XWE low 2 ns la XCOHL XWEH Delay time XCLKOUT high low to XWE high 2 ns la XCOH XRNWL Delay time XCLKOUT high to XR W low 1 ns la XCOHL XRNWH Delay time XCLKOUT high low to XR W high 2 1 ns len XD XWEL Enable time data bus driven from XWE low 0 ns la XWEL XD Delay time data valid after XWE active low 4 ns th xa xzCSH Hold time address valid after zone chip select inactive high 2 ns th XD XWE Hold time write data valid after XWE inactive high Tw 2 9 ns tdis XD XRNW Data bus disabled after XR W inactive high 4 ns 1 Not production tested 2 During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles 3 TW trail period write access see Table 6 25 Table 6 42 Synchronous XREADY Timing Requirements Ready on Write 1 Wait State MIN UNIT tsu XRDYsynchL XCOHL Setup time XREADY Synch low before XCLKOUT high low 15 ns n XRDYsynchL Hold time XREADY Synch low 12 ns le XRDYsynchH Earliest time XREADY Synch can go high before the sampling XCLKOUT edge 3 ns lsu XRDYsynchH XCOHL Setup time XREADY Synch high before XCLKOUT high low 15 ns n XRDYsynchH XZCSH Hold time XREADY Synch held high after zone chip select high 0 ns 1 Not production tested 2 The first XREADY Synch sample occurs with respect to E in Figure 6 33 XWRLEAD
126. ange 25 to 40 Q 3 11 Watchdog Block The watchdog block on the F2812 is identical to the one used on the 240x devices The watchdog module generates an output pulse 512 oscillator clocks wide OSCCLK whenever the 8 bit watchdog up counter has reached its maximum value To prevent this the user disables the counter or the software must periodically write a 0x55 OxAA sequence into the watchdog key register which resets the watchdog counter Figure 3 9 shows the various functional blocks within the watchdog module WDCR WDDIS WDCR WDPS 2 0 WDCNTR 7 0 OSCCLK WDCLK s 8 Bit o Watchdog Counter CLR Clear Counter Internal Pullup WDKEY 7 0 Bad Key Generate Watchdog Output Pulse 55 Good Key 512 5 50 Key Detector gt Core reset Bad WDCHK SCSR WDENINT XRS lt 1 WDCR WDCHK 2 0 Key WDRST aleji See Note A A The WDRST signal is driven low for 512 OSCCLK cycles Figure 3 9 Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE STANDBY mode timer In STANDBY mode all peripherals are turned off on the device The only peripheral that remains functional is the watchdog The WATCHDOG module runs off the PLL clock or the oscillator clock The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY if enabled See Section 3 12 L
127. back Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com Table 6 64 Minimum Required Wait States at Different Frequencies 1 continued SYSCLKOUT MHz SYSCLKOUT ns PAGE WAIT STATE RANDOM WAIT STATE 3 4 250 0 1 150 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 7 Mechanical Data The following mechanical package diagram s reflect the most current released mechanical data available for the designated device s Copyright 2009 2010 Texas Instruments Incorporated Mechanical Data 151 Submit Documentation Feedback Product Folder Link s SM320F2812 HT z PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 28 May 2010 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Qty Eco Plan 2 Lead MSL Peak Temp 3 Samples Drawing Ball Finish Requires Login SM320F2812HFGS150 ACTIVE CFP HFG 172 1 TBD AU N A for Pkg Type Contact TI Distributor or Sales Office SM320F2812KGDS150A ACTIVE XCEPT KGD 0 36 TBD Call TI N A for Pkg Type Contact TI Distributor or Sales Office 0 The marketing status values are defined as follows ACTIVE Produc
128. ble PLL Configuration Modes esee 3 16 F2812 Low Power 2 2 0 22 4 1 CPU Timers 0 1 2 Configuration and Control Registers 4 2 Module and Signal Names for EVA and EVB 4 3 EVA Registers 4 4 615 e 4 5 3 3 V eCAN Transceivers for the SM320F2812 DSP 4 6 CAN R gist rs Map 4 7 McBSP Register 4 8 51 4 9 SGIFB REGISIEKS D 4 10 iulii 4 11 GPIO MIPCH6GSISIOES use ctu sicnt em eic ieri 4 12 GPIO D la Registers 6 1 Typical Current Consumption by Various Peripherals at 150 MHz 6 2 Recommended Low Dropout Regulators 6 3 Clock Table and 6 4 INPUT CIOCK FrEQUENCY eem c E 6 5 XCLKIN Timing Requirements PLL Bypassed or Enabled 6 6 XCLKIN Timing Requirements PLL Disabled 6 7 Possible PLL Configuration Modes 11 6 8 XCLKOUT Switching Characteristics PLL Bypassed or Enabled 6 9 Reset XRS Timing Requirements 6 10 IDLE Mode Switching Charac
129. clock GPIO or SPI slave GPIOF3 SPISTEA I O 34 41 4185 9 42 6 VO Z transmit enable GPIOF OR SCI A SIGNALS GPIO or SCI GPIOF4 SCITXDA 151 170 42 6 2565 1 VO Z PU asynchronous serial port TX data GPIO or SCI GPIOF5 SCIRXDA I 153 172 42 6 2361 3 VO Z PU asynchronous serial port RX data 24 Introduction Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Signal Descriptions Continued 4 continued GPIO PERIPHERAL SIGNAL PIN NO 172 PIN HFG DIE PAD NO DIE PAD X CENTER DIE PAD Y CENTER 10 22 9 DESCRIPTION GPIOF OR CAN SIGNALS GPIOF6 CANTXA 0 85 99 5361 5 4758 0 2 GPIO or eCAN transmit data GPIOF7 CANRXA I 87 101 5192 7 5057 5 2 GPIO eCAN receive data GPIOF OR McBSP SIGNALS GPIOF8 MCLKXA I O 27 34 3461 4 42 6 2 GPIO or transmit clock GPIOF9 MCLKRA I O 24 31 3146 8 42 6 2 GPIO or receive clock GPIOF10 MFSXA I O 25 32 3242 2 42 6 2 GPIO or transmit frame synch GPIOF11 MFSRA I O 28 35 3556 7 42 6 2 GPIO or receive frame synch GPIOF12 MDXA 0 21 28 2
130. configured by the application This allows applications running at slower frequencies to configure the flash to use fewer wait states Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register With this mode enabled effective performance of linear code execution is much faster than the raw performance indicated by the wait state configuration alone The exact performance gain when using the Flash pipeline mode is application dependent The pipeline mode is not available for the OTP block For more information on the Flash options Flash wait state and OTP wait state registers see the 7MS320x281x System Control and Interrupts Reference Guide SPRU078 3 2 7 10 L1 SARAMs The F2812 contains an additional 16K x 16 of single access RAM divided into three blocks 4K 4K 8K Each block can be independently accessed hence minimizing pipeline stalls Each block is mapped to both program and data space 3 2 8 Boot ROM 32 The Boot ROM is factory programmed with boot loading software The Boot ROM program executes after device reset and checks several GPIO pins to determine which boot mode to enter For example the user can select to execute code already present in the internal Flash or download new software to internal RAM through one of several serial ports Other boot modes exist as well The Boot ROM also contains standard tables such as SIN COS waveforms for use in math relate
131. ct Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 4 Peripherals The integrated peripherals of the F2812 are described in the following subsections Three 32 bit CPU Timers Two event manager modules EVA EVB Enhanced analog to digital converter ADC module Enhanced controller area network eCAN module Multichannel buffered serial port McBSP module Serial communications interface modules SCI A SCI B Serial peripheral interface SPI module e Digital and shared pin functions 4 4 32 Bit CPU Timers 0 1 2 There are three 32 bit CPU timers on the F2812 devices CPU TIMERO 1 2 CPU Timers 1 and 2 are reserved for the real time OS such as DSP BIOS CPU Timer 0 can be used in user applications These timers are different from the general purpose GP timers that are present in the Event Manager modules EVA EVB NOTE If the application is not using DSP BIOS then CPU Timers 1 and 2 can be used in the application EL 32 Bit Timer Period PRDH PRD SYSCLKOUT 16 Bit TCR 4 32 Bit Counter Timer Start Status Borrow TIMH TIM Timer Reload Borrow 4 A e Figure 4 1 CPU Timers 52 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Texas SM320F2812 HT NSTRUMENTS www ti co
132. d algorithms Table 3 3 shows the details of how various boot modes may be invoked See the TMS320x281x DSP Boot ROM Reference Guide SPRSO095 for more information Functional Overview Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 3 3 Boot Mode Selection BOOT MODE SELECTED SCITXDA MDXA SPISTEA SPICLK GPIO PU status 9 PU No PU No PU No PU Jump to Flash ROM address Ox3F 7FF6 A branch instruction must have been programmed here prior to 1 X X X reset to redirect code execution as desired Call SPI Boot to load from an external serial SPI EEPROM 0 1 x x Call 5 to load from SCI A 0 0 1 1 Jump to HO SARAM address 0x3F 8000 0 0 1 0 Jump to OTP address 0x3D 7800 0 0 0 1 Call Parallel_ Boot to load from GPIO Port B 0 0 0 0 1 2 3 3 2 9 Security The F2812 supports high levels of security to protect the user firmware from being reversed engineered The security features a 128 bit password hardcoded for 16 wait states which the user programs into the flash One code security module CSM is used to protect the flash ROM OTP and the 10 11 SARAM blocks The security feature prevents unauthorized users from examining the memory contents via the JTAG port executing code from extern
133. d or a filter ADC Digital Power Vssi t Provide access to this pin in PCB layouts Intended for test purposes only t TAIYO YUDEN EMK325F106ZH EMK325BJ106MD or equivalent NOTES A External decoupling capacitors are recommended on all power pins B Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance C Use 24 9 for ADC clock range 1 18 75 MHz use 20 for ADC clock range 18 75 25 MHz Figure 4 5 ADC Pin Connections With Internal Reference See Notes A and B NOTE The temperature rating of any recommended component must match the rating of the end product 62 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 ADCINA 7 0 ADCINB 7 0 ADCLO Test Pin ADCBGREFIN ADC 16 Channel Analog Inputs Analog Input 0 3 V With Respect to ADCLO Connect to Analog Ground 24 9 kQ 20 See Note o lt 1 2V See lt 1 1V Note D iuF 10uF T T 10 pF ADC External Current Bias Resistor ADCRESEXT ADC Reference Positive Input ADCREFP ADC Reference Medium Input ADCREFM VppA1 L Analog 3 3 V ADC Analog Power Analog 33V Vssa1 Vssa2 AVDDREFBG Analog 3 3 V ADC Reference Power AVSSREFBG VDD
134. d recommended to make the ADC analog reference circuit stable before conversions are initiated If conversions are started without these delays the ADC results shows a higher gain For power down all three bits can be cleared at the same time 2 Not production tested Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Electrical Specifications 137 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 29 5 Detailed Description 6 29 5 1 Reference Voltage The on chip ADC has a built in reference which provides the reference voltages for the ADC ADCVREFP is set to 2 V and ADCVREFM is set to 1 V 6 29 5 2 Analog Inputs The on chip ADC consists of 16 analog inputs which are sampled either one at a time or two channels at a time These inputs are software selectable 6 29 5 3 Converter The on chip ADC uses a 12 bit four stage pipeline architecture which achieves a high sample rate with low power consumption 6 29 5 4 Conversion Modes The conversion can be performed in two different conversion modes Sequential sampling mode SMODE 0 Simultaneous sampling mode SMODE 1 6 29 6 Sequential Sampling Mode Single Channel SMODE 0 In sequential sampling mode the ADC can continuously convert input signals on any of the channels Ax to Bx The ADC can start conversions on event triggers from the Event
135. dditional pulldown resistor may be needed The value of this resistor should be based on drive strength of the debugger pods applicable to the design A 2 2 kO resistor generally offers adequate protection Since this is application specific it is recommended that each target board is validated for proper operation of the debugger and the application TCK 133 149 42 6 4605 1 PU JTAG test clock with internal pullup JTAG test mode select TMS with internal pullup This serial control input is clocked IMS 129 13 nm sso RA into the TAP controller on the rising edge of TCK JTAG test data input TDI with internal pullup TDI is clocked into the selected T iss He 908 i register instruction or data on a rising edge of TCK JTAG scan out test data output TDO The contents of the selected register instruction TBO 124 140 50575 Oz or data is shifted out of TDO on the falling edge of TCK Emulator pin 0 When TRST is driven high this pin is used as an interrupt to or from ENSO 139 190 426 E Vorz PU the emulator system and is defined as input output through the JTAG scan Emulator pin 1 When TRST is driven high this pin is used as an interrupt to or from EMU 143 161 426 3430 9 10 2 i the emulator system and is defined as input output through the JTAG scan 20 Introduction Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Pr
136. die layout is shown in Figure 2 1 See Table 2 3 for a description of each pad s function ORAE BEE 146 pa E eee F14i120 A E GE Ed Ed EA Figure 2 1 SM320F2812 Die Layout Table 2 2 Bare Die Information DIE PAD DIE PAD DIE BACKSIDE BACKSIDE BIE SIZE DIE PAD SIZE COORDINATES THICKNESS aa u FINISH POTENTIAL 219 4 x 207 0 mils Silicon with 5572 0 x 5258 0 um 55 0 x 64 0 See Table 2 3 11 0 mils AlCu TiN backgrind Ground Copyright 2009 2010 Texas Instruments Incorporated Introduction 15 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 2 4 Pin Assignments The SM320F2812 172 pin HFG ceramic quad flatpack CQFP pin assignments are shown in Figure 2 2 See Table 2 3 for a description of each pin s function s a 54 EI OR 5 s es 66 J I lt c m 2 gt ow goguak Ekee oF ss sears SOS SP ESB Se SO OPS OSS 130 NO MO SVAN SSS S
137. down XMP MC TESTSEL and TRST 86 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 1 00 06 Electromigration Fail Mode 1 00 05 1 00E 04 IE 5 n 1 00E 02 PULL EEL I 70 150 Die Junction Temperature C Figure 6 1 SM320F2812 HT Life Expectancy Curve Notes 1 See data sheet for absolute maximum and minimum recommended operating conditions 2 Silicon operating life design goal is 10 years at 105 C junction temperature does not include package interconnect life Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 87 Submit Documentation Feedback Product Folder Link s SM320F2812 HT 5 320 2812 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 4 Current Consumption by Power Supply Pins Over Recommended Operating Conditions During Low Power Modes at 150 MHz SYSCLKOUT 55 to 125 C 220 C All peripheral clocks are enabled All PWM pins are toggled at 100 kHz Data is continuously transmitted out of the SCIA SCIB and 195 mA 230 mA 30 mA 40 mA 45 40 mA 275 mA 330 mA 17 mA CAN ports The hardware multiplier is exercised Code is running out of flash with 5 wait states F
138. e Range Extended Product Life Cycle Extended Product Change Notification Product Traceability Texas Instruments high temperature products utilize highly optimized silicon die solutions with design and process enhancements to maximize performance over extended temperatures Custom temperature ranges available Features Copyright 2009 2010 Texas Instruments Incorporated 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 2 Introduction This section provides a summary of the device features lists the pin assignments and describes the function of each pin This document also provides detailed descriptions of peripherals electrical specifications parameter measurement information and mechanical data about the available packaging 2 4 Description The SM320F2812 device member of the C28xE DSP generation is a highly integrated high performance solution for demanding control applications The functional blocks and the memory maps are described in Section 3 Functional Overview Throughout this document SM320F2812 is abbreviated as F2812 Please be aware that an important notice concerning availability standard warranty and use critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2009 2010 Texas Instruments Incorporated Products c
139. e SS SSE SS 0 86 XZCS6AND7 C TESTSEL CT 4 TRST Cr 4 Cro EMUO XA 12 XD 14 XPLLDIS XA 13 Vss 1 1 VDD ro XA 14 VDDIO r 2 XD 15 15 XINT1 XBIO 1 4 7 XNMI XINT13 XINT2_ADCSOC cr 15 16 Vpp I 1 SCITXDA XA 17 SCIRXDA I 18 Toc XHOLD XRS XREADY VDD1 3 Vss1 ADCBGREFIN Vssa2 L Vppa2 C ADCINA7 ADCINA6 ADCINAS ADCINA4 I ADCINA3 CC ADCINA2 ADCINA1 ADCINAO ADCLO Vssaio L 31 172 OPES STE POCA 8598988358895 9 44 UU OU UU UU 100000006000000001000909000000000001001000004 OOo aoxunorza xxm lt 50 lt 50645 lt lt 50 lt lt SP SSS SSR eB AaSSSGSOCGt Kw wOlHE 27 BH 5 2299999998858 gt nn oo lt lt S 9 5 lt lt PS Figure 2 2 SM320F2812 172 Pin HFG CQFP Top View 16 Introduction Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com XZCS2 CANTXA Vss 3 XWE 5 XHOLDA VDDIO 2 T3CTRIP_PDPINTB Vss X1 XCLKIN 2 VDD XD 11 XD 10 TCLKINB TDIRB VDD3VFL C4TRIP CAP6_QEPI2 CAP5_QEP4 Vss CAP4_QE
140. e duration PDPINTx input low E 2 cycles with qualifier 1 x tesco IQT ee with no qualifier 2xt twextrip Pulse duration CxTRIP input low 082091 cycles with qualifier 1 x tesco IAT EET with no qualifier 2xt twrxcrup Pulse duration TxCTRIP input low 3 08201 cycles with qualifier 1 x tesco IAT 1 Not production tested 2 Input Qualification Time IQT 5 x QUALPRD x 2 x tesco XCLKOUT see Note tw PDP tw CxTRIP tw TxCTRIP 5 9 TxCTRIP CxTRIP PDPINTx see Note gt ta PDP PWM HZ ta TRIP PWM HZ PWM see Note C XNMI XINT1 XINT2 OOOO ODO OOOO RILIR III II III IRIRI IIRIS A XCLKOUT SYSCLKOUT B TxCTRIP T1CTRIP T2CTRIP T3CTRIP TACTRIP CxTRIP C1TRIP C2TRIP C3TRIP C4TRIP C5TRIP or C6TRIP PDPINTx PDPINTA or PDPINTB C PWM refers to all the PWM pins in the device i e PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit A0 A15 Figure 6 20 External Interrupt Timing 6 17 General Purpose Input Output Output Timing Table 6 19 General Purpose Output Switching Characteristics PARAMETER MIN MAX UNIT ta xCOH GPO Delay time XCLKOUT high to GPIO low high All GPIOs 1 x tesco cycle traro 7 Rise time GPIO switching low
141. e duration SPICLK high W SPCH clock polarity 0 0 5 0 5te co w SPCL M w SPCL M W SPCH SPCH SIMO M SPCL SIMO M v SPCL SIMO M M SPCH SIMO M su SOMI SPCL su SOMI SPCH v SPCL SOMI M M SPCH SOMIM Pulse duration S clock polarity 1 Pulse duration S PICLK low PICLK low amp amp ii clock polarity 2 0 clock polarity 2 1 Delay time SPICLK hi Pulse duration SPICLK high igh to SPISIMO valid clock polarity 0 Delay time SPICLK low to SPISIMO valid clock polarity 1 Valid time SPISIMO data valid after SPICLK low clock pol arity 0 Valid time SPISIMO data valid after SPICLK high clock polarity 1 Setup time SPISOMI low clock polarity 0 Setup time SPISOMI high clock polarity before SPICLK before SPICLK Valid time SPISOMI data valid after SPICLK low clock arity 0 Valid time SPISOMI data valid after SPICLK high clock polarity 1 0 10 0 0 5 10 0 5tespcym 10 0 10 0 25tyspcym 10 0 25 10 4 0 5 0 5 10 0 5 0 5 10 0 5tespoym 0 5 10 0 0 5 10 1 The MASTER SLAVE bit SPICTL 2 is set and the CLOCK PHASE bit SPICTL 3 is cleared spo SPlclock cycle time
142. e transitions and the ideal difference between first and last code transitions 6 29 8 5 Signal to Noise Ratio Distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels 6 29 8 6 Effective Number of Bits For a sine wave SINAD can be expressed in terms of the number of bits Using the following formula _ SINAD 1 76 6 02 N it is possible to get a measure of performance expressed as N the effective number of bits Thus effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD 6 29 8 7 Total Harmonic Distortion THD THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels 6 29 8 8 Spurious Free Dynamic Range SFDR SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 141 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 30 Multichannel Buf
143. egister GPGDIR 0x00 70D9 1 GPIO G Direction Control Register reserved 0x00 70DA 1 reserved 0x00 70DB 1 reserved ODE 4 1 Reserved locations returns undefined values and writes is ignored 2 Not all inputs support input signal qualification 3 These registers are EALLOW protected This prevents spurious writes from overwriting the contents and corrupting the system If configured for Digital mode additional registers are provided for setting individual I O signals via the GPxSET registers for clearing individual I O signals via the GPxCLEAR registers for toggling individual signals via the GPxTOGGLE registers or for reading writing to the individual I O signals via the GPxDAT registers Table 4 12 lists the GPIO Data Registers For more information see the TMSS320x281x System Control and Interrupts Reference Guide literature number SPRUO78 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Peripherals 79 SM320F2812 HT TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Table 4 12 GPIO Data Registers 2 NAME ADDRESS SIZE x16 REGISTER DESCRIPTION GPADAT 0x00 70 0 1 GPIO A Data Register GPASET 0x00 70E1 1 GPIO A Set Register GPACLEAR 0x00 70E2 1 GPIO A Clear Register GPATOGGLE 0x00 70E3 1
144. ent The types of documentation available include data sheets and data manuals with design specifications and hardware and software applications Useful reference documentation includes TMS320C28x DSP CPU and Instruction Set Reference Guide literature number SPRU430 describes the central processing unit CPU and the assembly language instructions of the TMS320C28x fixed point digital signal processors DSPs It also describes emulation features available on these DSPs TMS320x281x Analog to Digital Converter ADC Reference Guide literature number SPRUOGO describes the ADC module The module is a 12 bit pipelined ADC The analog circuits of this converter referred to as the core in this document include the front end analog multiplexers MUXs sample and hold S H circuits the conversion core voltage regulators and other analog supporting circuits Digital circuits referred to as the wrapper in this document include programmable conversion sequencer result registers interface to analog circuits interface to device peripheral bus and interface to other on chip modules TMS320x281x Boot ROM Reference Guide literature number SPRUO95 describes the purpose and features of the bootloader factory programmed boot loading software It also describes other contents of the device on chip boot ROM and identifies where all of the information is located within that memory TMS320x281x Event Manager EV Reference Guide literature numbe
145. ents Incorporated TEXAS INSTRUMENTS www ti com List of Tables 2 1 Hardware 44 1 2 2 Bare Die nennen 2 3 Signal DESCIPUONS Em 3 1 Addresses of Flash Sectors 2812 3 2 MERCI EU 3 3 Boot Mode 5 E n ei eure 3 4 Peripheral Frame 0 Registers 4 3 5 Peripheral Frame 1 Registers 7 4 4 3 6 Peripheral Frame 2 Registers 2 4 3 7 Device Emulation 3 3 8 XINTF Configuration and Control Register Mappings 3 9 XREVISION Register Bit 3 10 PIE Peripheral Interrupts 244 4 1 3 11 PIE Configuration and Control Registers 2 3 12 External Interrupts Registers 2 1 22 2 3 13 PLL Clocking Watchdog Low Power Mode Registers 3 14 PLLCR Register Bit 3 15 Possi
146. ents Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 IFR 12 1 IER 12 1 INTM INTI INT2 p amp gt gt _ lt e e e e e e INTI gt INT12 gt gt gt Global Enable lt lt lt lt j lt lt lt 4 lt lt From lt lt lt Peripherals or lt lt lt q External 4 4 lt Interrupts lt j PIEACKx 4 lt 4 Enable Enable Fl Enable Flag PIEIERx 8 1 PIEIFRx 8 1 Figure 3 5 Multiplexing of Interrupts Using the PIE Block Table 3 10 PIE Peripheral Interrupts CPU PIE INTERRUPTS INTERRUPTS INTx 8 INTx 7 INTx 6 INTx 5 INTx 4 INTx 3 INTx 2 INTx 1 WAKEINT TINTO ADCINT PDPINTB PDPINTA INT1 LPM WD TIMER 0 ADC XINT2 XINT1 reserved EV B EV A INT2 reserved T1OFINT T1UFINT T1CINT T1PINT CMP2INT CMP1INT EV A EV A EV A EV A EV A EV A EV A INT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT EV A EV A EV A EV A EV A EV A EV A 4 T3UFINT T3CINT T3PINT CMP6INT CMPAINT EV B EV B EV B EV B EV B EV B EV B 5 reserved CAPINT6 CAPINT5 CAPINT4 T4OF INT T4UFINT T4CINT T4PINT EV B EV B EV B EV B EV B EV B EV B MXINT MRINT SPITXINTA SPIRXINTA INT
147. er Control Register A CMPR1 0x00 7417 1 Compare Register 1 CMPR2 0x00 7418 1 Compare Register 2 CMPR3 0x00 7419 1 Compare Register 3 CAPCONA 0x00 7420 1 Capture Control Register A CAPFIFOA 0x00 7422 1 Capture FIFO Status Register A CAP1FIFO 0x00 7423 1 Two Level Deep Capture FIFO Stack 1 CAP2FIFO 0x00 7424 1 Two Level Deep Capture FIFO Stack 2 CAP3FIFO 0x00 7425 1 Two Level Deep Capture FIFO Stack 3 CAP1FBOT 0x00 7427 1 Bottom Register Of Capture FIFO Stack 1 CAP2FBOT 0x00 7428 1 Bottom Register Of Capture FIFO Stack 2 CAP3FBOT 0x00 7429 1 Bottom Register Of Capture FIFO Stack 3 EVAIMRA 0x00 742C 1 Interrupt Mask Register A EVAIMRB 0x00 742D 1 Interrupt Mask Register B EVAIMRC 0x00 742E 1 Interrupt Mask Register C EVAIFRA 0x00 742F 1 Interrupt Flag Register A EVAIFRB 0x00 7430 1 Interrupt Flag Register B EVAIFRC 0x00 7431 1 Interrupt Flag Register C 1 The EV B register set is identical except the address range is from 0x00 7500 to 0x00 753F The above registers are mapped to Zone 2 This space allows only 16 bit accesses 32 bit accesses produce undefined results 2 New register compared to 24x 240x 56 Peripherals Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 GPTCONA 12 4 CAPCONA 8 01 4 EVAENCLK Control Logic EVATO AD
148. eriod begin on the rising edge of XCLKOUT When necessary the device inserts an alignment cycle before an access to meet this requirement B During alignment cycles all signals transitions to their inactive state C During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access can be calculated as XWRLEAD XWRACTIVE n 1 tc xriM tsuXRDYsynchL XCOHL where n is the sample number n 1 2 3 and so forth E Reference for the first sample is with respect to this point XWRLEAD XWRACTIVE tcoxriM Figure 6 33 Write With Synchronous XREADY Access XTIMING register parameters used for this example XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 1 1 1 0 XREADY N A N A N A 1 0 21 3 21 Synch 1 N A Don t care for this example Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 129 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com WS Asynch i i 4 Trail and 4 Active gt M Lead gt XCLKOUT XTIMCLK geet ee ee XCLKOUT 1 2 XT
149. es change state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT In the XINTF timing tables the notation XCOHL is used to indicate that the parameter is with respect to either case XCLKOUT rising edge high or XCLKOUT falling edge low If the parameter is always with respect to the rising edge of XCLKOUT the notation XCOH is used For the case where XCLKOUT one half XTIMCLK the XCLKOUT edge with which the change is aligned can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which the signal changes If this number of XTIMCLK cycles is even the alignment is with respect to the rising edge of XCLKOUT If this number is odd then the signal changes with respect to the falling edge of XCLKOUT Examples include the following Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT This is because all XINTF accesses begin with respect to the rising edge of XCLKOUT Examples XZCSL Zone chip select active low XRNWL XR W active low Strobes that change at the beginning of the active period aligns to the rising edge of XCLKOUT if the total number of lead XTIMCLK cycles for the access is even If the number of lead XTIMCLK cycles is odd then the alignment is with respect to the falling edge of XCLKOUT Examples XRDL XRD active low XWEL XWE active low Strobes that change at the beginning of the trail period aligns to the rising edge o
150. f XCLKOUT if the total number of lead active XTIMCLK cycles including hardware waitstates for the access is even If the number of lead active XTIMCLK cycles including hardware waitstates is odd then the alignment is with respect to the falling edge of XCLKOUT Examples XRDH XRD inactive high XWEH XWE inactive high Strobes that change at the end of the access aligns to the rising edge of XCLKOUT if the total number of lead active trail XTIMCLK cycles including hardware waitstates is even If the number of lead active trail XTIMCLK cycles including hardware waitstates is odd then the alignment is with respect to the falling edge of XCLKOUT Examples XZCSH Zone chip select inactive high XRNWH XR W inactive high Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 121 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 23 External Interface Read Timing Table 6 34 External Memory Interface Read Switching Characteristics PARAMETER MIN UNIT ta xCOH XZCSL Delay time XCLKOUT high to zone chip select active low 1 ns la XCOHL XZCSH Delay time XCLKOUT high low to zone chip select inactive high 2 3 ns la XCOH XA Delay time XCLKOUT high to address valid 2 ns ta XCOHL XRDL Delay time XCLKOUT high low to XRD active low 1 ns ta XCOHL XRDH Delay time X
151. face When low Zone 7 is disabled from the external interface and on chip boot ROM may be accessed instead This signal is latched into the XINTCNF2 register on a reset and the user can modify this bit in software The state of the XMP MC pin is ignored after reset 155 174 42 6 2157 6 PU External Hold Request XHOLD when active low requests the XINTF to release the external bus and place all buses and strobes into a high impedance state The XINTF releases the bus when any current access is complete and there are no pending accesses on the XINTF XHOLDA 80 93 5361 5 4137 4 O Z External Hold Acknowledge XHOLDA is driven active low when the XINTF has granted a XHOLD request All XINTF buses and strobe signals are in a high impedance state XHOLDA is released when the XHOLD signal is released External devices should only drive the external bus when XHOLDA is active low XZCSOAND1 43 50 5148 5 42 6 O Z XINTF Zone 0 and Zone 1 Chip Select XZCSOAND is active low when an access to the XINTF Zone 0 or Zone 1 is performed XZCS2 86 100 5361 5 4844 2 O Z XINTF Zone 2 Chip Select XZCS2 is active low when an access to the XINTF Zone 2 is performed XZCS6AND7 130 146 42 6 4888 6 O Z XINTF Zone 6 and Zone 7 Chip Select XZCS6AND7 is active low when an access to the XINTF Zone 6 or Zone 7 is performed 82
152. fast 12 bit ADC module with a fast conversion rate of 80 ns at 25 MHz ADC clock The ADC module has 16 channels configurable as two independent 8 channel modules to service event managers A and B The two independent 8 channel modules can be cascaded to form a 16 channel module Although there are multiple input channels and two sequencers there is only one converter in the ADC module Figure 4 4 shows the block diagram of the F2812 ADC module The two 8 channel modules have the capability to autosequence a series of conversions each module has the choice of selecting any one of the respective eight channels available through an analog MUX In the cascaded mode the autosequencer functions as a single 16 channel sequencer On each sequencer once the conversion is complete the selected channel value is stored in its respective RESULT register Autosequencing allows the system to convert the same channel multiple times allowing the user to perform oversampling algorithms This gives increased resolution over traditional single sampled conversion results Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 System High Speed Control Block Prescaler ADCENCLK HSPCLK SYSCLKOUT Analog MUX Result Registers ADCINAO Result Reg 0 70A8h Result Reg
153. fered Serial Port McBSP Timing 6 30 1 McBSP Transmit and Receive Timing Table 6 52 McBSP Timing Requirements 2 9 NO MIN UNIT 1 kHz McBSP module clock CLKG CLKX CLKR range 2000 MHz 50 ns McBSP module cycle time CLKG CLKX CLKR range 7 M11 Cycle time CLKR X CLKR X ext 2P ns M12 twokRx Pulse duration CLKR X high or CLKR X low CLKR X ext P 7 ns M13 Rise time CLKR X CLKR X ext 7 ns M14 trcknx Fall time CLKR X CLKR X ext 7 ns CLKR int 18 M15 tsuFRH CKRL Setup time external FSR high before CLKR low CLKR ext 5 ns CLKR int 0 M16 tnckRL FRH Hold time external FSR high after CLKR low CLKR ext 6 ns CLKR int 18 M17 tsupRv ckRL Setup time DR valid before CLKR low CLKR ext 2 ns CLKR int 0 M18 Hold time DR valid after CLKR low CLKR ext 6 ns CLKX int 18 M19 tsu FXH CKXL Setup time external FSX high before CLKX low CLKX ext ns CLKx int 0 M20 thyckxL FXH Hold time external FSX high after CLKX low CLKX ext 6 ns 1 Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing references of that signal are also inverted Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing references of that signal are also inverted CLKG CLKSRG 2 2P 1 CLKG in ns CLKG is the output of sample rate generator mux 1
154. g Reference Point 420 3 5 nH Output Unde 20 500 see note Device Pin r 40pF 1 85 pF see note NOTE The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect The transmission line is intended as a load only It is not necessary to add or subtract the transmission line delay 2 ns or longer from the data sheet timing Input requirements in this data sheet are tested with an input slew rate of 4 Volts per nanosecond 4 V ns at the device pin Figure 6 7 3 3 V Test Load Circuit Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 93 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 6 12 Device Clock Table www ti com This section provides the timing requirements and switching characteristics for the various clock options available on the F2812 DSP Table 6 3 lists the cycle times of various clocks Table 6 3 Clock Table and Nomenclature MIN NOM MAX UNIT On chip oscillator clock toso Cycle time an a Frequency 20
155. g Register PIEIER2 0x0000 0CE4 1 PIE INT2 Group Enable Register PIEIFR2 0x0000 0CE5 1 PIE INT2 Group Flag Register PIEIER3 0x0000 0CE6 1 PIE INT3 Group Enable Register PIEIFR3 0x0000 0CE7 1 PIE INT3 Group Flag Register PIEIER4 0x0000 0CE8 1 PIE INT4 Group Enable Register PIEIFR4 0x0000 0CE9 1 PIE INT4 Group Flag Register PIEIER5 0x0000 0CEA 1 PIE INT5 Group Enable Register PIEIFR5 0x0000 0CEB 1 PIE INT5 Group Flag Register PIEIER6 0x0000 0CEC 1 PIE INT6 Group Enable Register PIEIFR6 0x0000 0CED 1 PIE INT6 Group Flag Register PIEIER7 0x0000 0CEE 1 PIE INT7 Group Enable Register PIEIFR7 0x0000 0CEF 1 PIE INT7 Group Flag Register PIEIER8 0x0000 0CFO il PIE INT8 Group Enable Register PIEIFR8 0x0000 0CF1 il PIE INT8 Group Flag Register PIEIER9 0x0000 0CF2 1 PIE INT9 Group Enable Register PIEIFR9 0x0000 0CF3 1 PIE INT9 Group Flag Register PIEIER10 0x0000 0CF4 1 PIE INT10 Group Enable Register PIEIFR10 0x0000 0CF5 1 PIE INT10 Group Flag Register PIEIER11 0x0000 0CF6 1 PIE INT11 Group Enable Register PIEIFR11 0x0000 0CF7 1 PIE INT11 Group Flag Register PIEIER12 0x0000 0CF8 1 PIE INT12 Group Enable Register PIEIFR12 0x0000 0CF9 1 PIE INT12 Group Flag Register Reserved DES 6 Reserved 1 The PIE configuration and control registers are not protected by EALLOW mode The PIE vector table is protected 44 Functional Overview Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder
156. g Requirements CLKSTP 11b CLKXP 1 148 6 61 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 1 148 6 62 Flash Parameters at 150 MHz SYSCLKOUT 2 1 2 1 1 4 5 14 149 6 63 Flash OTP Access Timing 1 41 lt lt 66 149 8 List of Tables Copyright 2009 2010 Texas Instruments Incorporated 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 64 Minimum Required Wait States at Different Frequencies 1 1 1 41 lt 149 Copyright 2009 2010 Texas Instruments Incorporated List of Tables 9 SM320F2812 HT I TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 10 List of Tables Copyright 2009 2010 Texas Instruments Incorporated TEXAS INSTRUMENTS SM320F2812 HT www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Digital Signal Processor Check for Samples SM320F2812 HT 1 Features High Performance Static CMOS Technology 128 Bit Security Key Lock 150 MHz 6 67 ns Cycle Time Protects Flash ROM OTP and L0 L1 SARAM Low Power 1 8 V Core at 135 MHz 1 9 V Prevents Firmware Reverse Engineering Core at 150 MHz 3 3 V I O Des
157. h low before XCLKOUT high low 15 ns n XRDYsynchL Hold time XREADY Synch low 12 ns le XRDYsynchH Earliest time XREADY Synch can go high before the sampling XCLKOUT edge 3 ns lsu XRDYsynchH XCOHL Setup time XREADY Synch high before XCLKOUT high low 15 ns n XRDYsynchH XZCSH Hold time XREADY Synch held high after zone chip select high 0 ns 1 Not production tested 2 The first XREADY Synch sample occurs with respect to E in Figure 6 31 XRDLEAD XRDACTIVE taxtim When first sampled if XREADY Synch is found to be high then the access completes If XREADY Synch is found to be low it is sampled again each t xriyy until it is found to be high For each sample n the setup time D with respect to the beginning of the access can be calculated as D XRDLEAD XRDACTIVE n 1 tcriM tsu XRDYsynchL XCOHL where n is the sample number n 1 2 3 and so forth Table 6 40 Asynchronous XREADY Timing Requirements Ready on Read 1 Wait State 2 MIN MAX UNIT lsu XRDYAsynchL XCOHL Setup time XREADY Asynch low before XCLKOUT high low 11 ns n XRDYAsynchL Hold time XREADY Asynch low 8 ns Earliest time XREADY Asynch can go high before the sampling XCLKOUT le XRDYAsynchH 3 ns edge 1 Not production tested 2 The first XREADY Asynch sample occurs with respect to E in Figure 6 32 XRDLEAD XRDACTIVE 2 When first sampled if XREADY As
158. h FIFO 70 Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 4 7 provides a summary of the McBSP registers Table 4 7 McBSP Register Summary NAME ee VALUE DESCRIPTION DATA REGISTERS RECEIVE TRANSMIT 0 0000 McBSP Receive Buffer Register 0 0000 McBSP Receive Shift Register 0 0000 McBSP Transmit Shift Register Done 0 n 222 2 than 16 bits else ignore DRR2 McBSP Data Receive Register 1 DRR1 01 R 0x0000 og Second if the word size is greater than 16 bits else read DRR1 DATE ee UXDUDU 1 than 16 bits else ignore DXR2 McBSP Data Transmit Register 1 DXR1 03 0 0000 mur Second if the word size is greater than 16 bits else write to DXR1 McBSP CONTROL REGISTERS SPCR2 04 R W 0x0000 McBSP Serial Port Control Register 2 SPCR1 05 R W 0x0000 McBSP Serial Port Control Register 1 RCR2 06 R W 0x0000 McBSP Receive Control Register 2 RCR1 07 R W 0x0000 McBSP Receive Control Register 1 XCR2 08 R W 0x0000 McBSP Transmit Control Register 2 XCR1 09 R W 0x0000 McBSP Transmit Control Register 1 SRGR2 0A R W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0B R W 0x0000
159. he equipment and expertise to tune the tank circuit The vendor can also advise the customer regarding the proper tank component values that ensures start up and stability over the entire operating range Figure 3 8 Recommended Crystal Clock Connection Table 3 15 Possible PLL Configuration Modes PLL MODE REMARKS SYSCLKOUT Invoked by tying XPLLDIS pin low upon reset PLL block is completely disabled Clock input Pek Disabled to the CPU CLKIN is directly derived from the clock signal present at the X1 XCLKIN pin XCLKIN Default PLL configuration upon power up if PLL is not disabled The PLL itself is bypassed PLL Bypassed However the 2 module in the PLL block divides the clock input at the X1 XCLKIN pin by XCLKIN 2 two before feeding it to the CPU Achieved by writing a non zero value n into PLLCR register The 2 module in the PLL block HOLEN now divides the output of the PLL by two before feeding it to the CPU XCLKIN 3 10 External Reference Oscillator Clock Option The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below Fundamental mode parallel resonant C load capacitance 12 pF Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 49 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Cu Cio 24 pF Csnunt 6 pF ESR r
160. hrough the I O buffer to provide power on reset to all the modules inside the device See Figure 6 8 for power on reset timing Power Down Sequencing During power down the device reset should be asserted low 8 us minimum before the Vpp supply reaches 1 5 V This helps to keep on chip flash logic in reset prior to the Vppjo Vpp power supplies ramping down It is recommended that the device reset control from Low Dropout LDO regulators or voltage supervisors be used to meet this constraint LDO regulators that facilitate power sequencing with the aid of additional external components may be used to meet the power sequencing requirement See www spectrumdigital com for F2812 eZdsp schematics and updates 90 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 13 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 2 Recommended Low Dropout Regulators SUPPLIER PART NUMBER Texas Instruments TPS767D301 NOTE GPIO pins are undefined until Vpp 1 V and Vppio 2 5 V 25V see Note A See Note C 3 3 V 3 3 V _ 1 lt 10 1 8 1 8 1 5 1 9 V 1 9 V Vpp 1 av _ d gt 1 ms gt 8 us Note 5 See Note XRS Power Up Sequence Power Down Sequence TVpp 3av Vopavet
161. ia the GPxMUX registers If selected for Digital mode registers are provided to configure the pin direction via the GPxDIR registers and to qualify the input signal to remove unwanted noise via the GPxQUAL registers Table 4 11 lists the GPIO Mux Registers Table 4 11 GPIO Mux Registers 2 3 NAME ADDRESS SIZE x16 REGISTER DESCRIPTION GPAMUX 0x00 70CO 1 GPIO A Mux Control Register GPADIR 0x00 70C1 1 GPIO A Direction Control Register GPAQUAL 0x00 70C2 1 GPIO A Input Qualification Control Register reserved 0x00 70C3 1 GPBMUX 0x00 70 4 1 GPIO B Mux Control Register GPBDIR 0x00 70C5 1 GPIO B Direction Control Register GPBQUAL 0x00 70C6 1 GPIO B Input Qualification Control Register reserved 0x00 70C7 1 reserved 0x00 70C8 1 reserved 0x00 70C9 1 reserved 0x00 70CA 1 reserved 0x00 70CB 1 GPDMUX 0x00 70CC 1 GPIO D Mux Control Register GPDDIR 0x00 70CD 1 GPIO D Direction Control Register GPDQUAL 0x00 70CE 1 GPIO D Input Qualification Control Register reserved 0x00 70CF 1 GPEMUX 0x00 70DO 1 GPIO E Mux Control Register GPEDIR 0x00 70D1 1 GPIO E Direction Control Register GPEQUAL 0x00 70D2 1 GPIO E Input Qualification Control Register reserved 0x00 70D3 1 GPFMUX 0x00 70D4 1 GPIO F Mux Control Register GPFDIR 0x00 70D5 1 GPIO F Direction Control Register reserved 0x00 70D6 1 reserved 0x00 70D7 1 GPGMUX 0x00 70D8 1 GPIO G Mux Control R
162. ides a versatile and robust serial communication interface The eCAN module implemented in the C28x DSP is compatible with the CAN 2 0B standard active TMS320x281x 280x Peripheral Reference Guide literature number SPRU566 describes the peripheral reference guides of the 28x digital signal processors DSPs TMS320x281x 280x Serial Communication Interface SCI Reference Guide literature number SPRUO51 describes the SCI that is a two wire asynchronous serial port commonly known as a UART The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non return to zero NRZ format TMS320x281x 280x Serial Peripheral Interface SPI Reference Guide literature number SPRUO59 describes the SPI a high speed synchronous serial input output I O port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmed bit transfer rate The SPI is used for communications between the DSP controller and external peripherals or another controller 3 3 V DSP for Digital Motor Control Application Report literature number SPRA550 New generations of motor control digital signal processors DSPs lower their supply voltages from 5 V to 3 3 V to offer higher performance at lower cost Replacing traditional 5 V digital control circuitry by 3 3 V designs introduce no additional system cost and no significant complication in interf
163. ign Three 32 Bit CPU Timers 3 3 V Flash Voltage Motor Control Peripherals JTAG Boundary Scan Support Two Event Managers EVA EVB High Performance 32 Bit CPU TMS320C28x Compatible to 240xA Devices 16 x 16 and 32 x 32 MAC Operations Serial Port Peripherals 16 x 16 Dual MAC Serial Peripheral Interface SPI Harvard Bus Architecture Two Serial Communications Interfaces Atomic Operations SCIs Standard UART Fast Interrupt Response and Processing Enhanced Controller Area Network eCAN Unified Memory Programming Model Multichannel Buffered Serial Port McBSP 4M Linear Program Address Reach With SPI Mode 4M Linear Data Address Reach 12 Bit ADC 16 Channels Code Efficient in C C and Assembly 2 8 Channel Input Multiplexer TMS320F24x LF240x Processor Source Code Two Sample and Hold Compatible Single Simultaneous Conversions On Chip Memory Fast Conversion Rate 80 ns 12 5 MSPS Flash Devices Up to 128K x 16 Flash Four Up to 56 Individually Programmable 8K x 16 and Six 16K x 16 Sectors Multiplexed General Purpose Input Output ROM Devices Up to 128K x 16 ROM GPIO Pins 1K 16 ROM Advanced Emulation Features LO and L1 2 Blocks of 4K x 16 Each Analysis and Breakpoint Functions Single Access RAM SARAM Real Time Debug via Hardware 1 Block of 8K 16 SARAM Development Tools Include and 1 2 Blocks
164. indows each window being 2n SYSCLKOUT cycles For QUALPRD 1 the minimum width that is needed is 5 x 2 10 SYSCLKOUT cycles However since the external signal is driven asynchronously a 11 SYSCLKOUT wide pulse ensures reliable recognition 2 Maximum input frequency to the QEP min HSPCLK 2 20 MHz 3 Not production tested 4 Input Qualification Time IQT 5 x QUALPRD x 2 x tesco eee XI XM Xy see Note A ta pwM xco I twpwwy A XCLKOUT SYSCLKOUT Figure 6 16 PWM Output Timing mom _ see Note A XCLKOUT SYSCLKOUT Figure 6 17 TDIRx Timing Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 105 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Table 6 15 External ADC Start of Conversion EVA Switching Characteristics 2 PARAMETER MIN MAX UNIT ld XCOH EVASOCL Delay time XCLKOUT high to EVASOC low 1 x tesco cycle tw EVASOCL Pulse duration EVASOC low 32 x tc Hco ns 1 XCLKOUT SYSCLKOUT 2 Not production tested Z n ta xCOH EVASOCL tw EVASOCL EVASOC Figure 6 18 EVASOC Timing Table 6 16 External ADC Start of Conversion EVB Switching Characteristics 2 PARAMETER MIN MAX UNIT
165. ion Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com 3 Functional Overview SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Memory Bus Timer 0 CPU CPU CPU Timer 1 Timer 2 z N PIE 96 interrupts t External Interrupt Control XINT1 2 13 XNMI SCIA SCIB SPI lt _GPIO Pins McBSP 28 CPU EVA EVB Real Time JTAG Contro External Interface XINTF Address gt SARAM 1K x 16 59 M1 SARAM 1Kx 16 LO SARAM 4K x 16 L1 SARAM 4K x 16 Flash 128K x 16 16 Channels 12 Bit ADC XRS System Control otp XRS gt Venere 1K x 16 X1 XCLKIN Oscillator and PLL 12 T 4 2 Peripheral Clocking CHEN HO SARAM XF_XPLLDIS gt Low Power 8 16 Modos Memory Bus ZN Boot ROM WatchDog 4K 16 Peripheral Bus t 45 of the possible 96 interrupts are used on the device Protected by the code security module Figure 3 1 Functional Block Diagram Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Functional Overview 27 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 3 1 Memory Map
166. ion Result Buffer Register 12 ADCRESULT13 0x00 7115 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x00 7116 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x00 7117 1 ADC Conversion Result Buffer Register 15 ADCTRL3 0x00 7118 1 ADC Control Register 3 ADCST 0x00 7119 1 ADC Status Register reserved ee TE 4 1 64 Peripherals The above registers are Peripheral Frame 2 Registers Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 4 4 Enhanced Controller Area Network eCAN Module The CAN module has the following features Fully compliant with CAN protocol version 2 0B e Supports data rates up to 1 Mbps Thirty two mailboxes each with the following properties Configurable as receive or transmit Configurable with standard or extended identifier Has a programmable receive mask Supports data and remote frame Composed of 0 to 8 bytes of data Uses a 32 bit time stamp on receive and transmit message Protects against reception of new message Holds the dynamically programmable priority of transmit message Employs a programmable interrupt scheme with two interrupt levels Employs a programmable alarm on transmission or reception time out Low power mode Programmable wake up on bus activity Automatic reply
167. ions Transmitter and receiver operations can be accomplished through interrupt driven or polled algorithms with status flags Transmitter TXRDY flag transmitter buffer register is ready to receive another character andTX EMPTY flag transmitter shift register is empty Receiver RXRDY flag receiver buffer register is ready to receive another character BRKDT flag break condition occurred and RX ERROR flag monitoring four interrupt conditions Separate enable bits for transmitter and receiver interrupts except BRKDT 150MHz Max bitrate 9 375 106 b s NRZ non return to zero format Ten SCI module control registers located in the control register frame beginning at address 7050h Copyright 2009 2010 Texas Instruments Incorporated Peripherals 73 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com NOTE All registers in this module are 8 bit registers that are connected to Peripheral Frame 2 When a register is accessed the register data is in the lower byte 7 0 and the upper byte 15 8 is read as zeros Writing to the upper byte has no effect Enhanced features Auto baud detect hardware logic e 16 level transmit receive FIFO The SCI port operation is configured and controlled by the registers listed in Table 4 8 and Table 4 9 Table 4 8 SCI A Registers
168. lash is powered down oo is turned 155 mal 150 10 mA 1 WA All peripheral clocks are on except ADC Flash is powered down Peripheral clocks are turned off 5mA 10mA 20 uA 1 35 27 mA 40 mA 160 uA 200 pA 56 100 pA 320 Pins without internal PU PD are tied high low Flash is powered down Peripheral clocks are turned off Pins without an 70 pA 20 pA 9 8 mA 160 uA 200 uA 56 uA 100 pA 320 internal PU PD are tied high low Input clock is disabled 1 IDDA includes current into 1 Vppa2 AVppnErFBG pins 2 MAX numbers at 125 C and max voltage Vpp 2 0 V Vopio Vppa 3 6 V NOTE HALT and STANDBY modes cannot be used when the PLL is disabled 88 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 5 Current Consumption Graphs 250 200 lt x 150 9 5 100 50 pem 0 NM 3 0 20 40 60 80 100 120 140 160 SYSCLKOUT MHz e IDD B IDDIO 34 IDD3VFL e IDDA Total 3 3 V current A Test conditions are as defined in Table 6 5 for operational currents under nominal process voltage and temperature co
169. latency The HALT mode is now exited Normal operation resumes A instruction is executed to put the device into HALT mode B The PLL block responds to the HALT signal SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped This 32 cycle delay enables the CPU pipe and any other pending operations to flush perperly C Clocks to the device are turned off and the internal oscillator and PLL are shut down The device is now in HALT mode and consumes absolute minimum power D When XNMI is friven active negative edge triggered shown as an example the oscillator is turned on but the PLL is not activiated E When XNMI is deactiveted it initiates the PLL lock sequence which takes 131 072 X1 XCLKIN cycles F When CLKIN to the core is enabled the device responds to the interrupt if enabled after a latency The HALT mode is now exited G Normal operation resumes H XCLKOUT SYSCLKOUT Figure 6 15 HALT Wakeup Using XNMI 6 16 Event Manager Interface 6 16 1 PWM Timing PWM refers to all PWM outputs on EVA and EVB 104 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 13 PWM Switching Characteristics 2
170. lect XZCS6AND7 See Section 3 5 External Interface XINTF 2812 only for details Peripheral Frame 1 Peripheral Frame 2 and XINTF Zone 1 are grouped together so as to enable these blocks to be write read peripheral block protected The protected mode ensures that all accesses to these blocks happen as written Because of the C28x pipeline a write immediately followed by a read to different memory locations appears in reverse order on the memory bus of the CPU This can cause problems in certain peripheral applications where the user expected the write to occur first as written The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written the penalty is extra cycles are added to align the operations This mode is programmable and by default it protects the selected zones On the F2812 at reset XINTF Zone 7 is accessed if the XMP MC pin is pulled high This signal selects microprocessor or microcomputer mode of operation In microprocessor mode Zone 7 is mapped to high Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 29 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com memory such that the vector table is fetched externally The Boot ROM is disabled in this mode In microcomputer mode Zone 7 is disabled such that
171. m SGUS062A JUNE 2009 REVISED APRIL 2010 In the F2812 device the timer interrupt signals TINTO TINT1 TINT2 are connected as shown in Figure 4 2 CPU TIMER 0 CPU TIMER 1 Reserved for TI system functions CPU TIMER 2 Reserved for TI system functions A The timer registers are connected to the Memory Bus of the C28x processor B The timing of the timers is synchronized to SYSCLKOUT of the processor clock Figure 4 2 CPU Timer Interrupts Signals and Output Signal See Notes A and B The general operation of the timer is as follows The 32 bit counter register TIMH TIM is loaded with the value in the period register PRDH PRD The counter register decrements at the SYSCLKOUT rate of the C28x When the counter reaches 0 a timer interrupt output signal generates an interrupt pulse The registers listed in Table 4 1 are used to configure the timers For more information see the TMS320x281x System Control and Interrupts Reference Guide literature number SPRUO78 Copyright 2009 2010 Texas Instruments Incorporated Peripherals 53 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com Table 4 1 CPU Timers 0 1 2 Configuration and Conirol Registers NAME ADDRESS SIZE x16 DESCRIPTION TIMEROTIM 0x00 1 CPU
172. n Range Address Register 0x00 0886 reserved 0x00 09FF 378 3 5 External Interface XINTF This section gives a top level view of the external interface XINTF that is implemented on the F2812 device The external interface is a non multiplexed asynchronous bus similar to the C240x external interface The external interface on the F2812 is mapped into five fixed zones shown in Figure 3 3 Figure 3 3 shows the F2812 XINTF signals Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 39 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Data Space Prog Space XD 15 0 18 0 0 00 2000 XINTF Zone 0 8K x 16 XZCSOAND1 0x00 4000 XINTF Zone 1 8K 16 0x00 6000 0 08 0000 0 10 0000 XINTF Zone 6 XZCS6AND7 512 x 16 0x18 0000 0x3F C000 XINTF Zone 7 16K 16 __ mapped here if MP MC 1 0x40 0000 i i XWE gt XRD gt i AN XR W amp 4 XREADY XMP MC P XHOLD XHOLDA XCLKOUT gt 1 1 INSTRUMENTS www ti com A mapping of XINTF Zone 7 is dependent on the XMP MC device input signal and the MP MC mode bit bit 8 of XINTCNF2 register Zones 0 1 2 and 6 are always enabled B Each zone can be programmed with different
173. nactive cycles the XINTF address bus always hold sthe last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access can be calculated as XRDLEAD XRDACTIVE 3 n tecxtim tsuXRDYasynchL XCOHL where n is the sample number n 1 2 3 and so forth E Reference for the first sample is with respect to this point XRDLEAD XRDACTIVE 2 Figure 6 32 Example Read With Asynchronous XREADY Access XTIMING register parameters used for this example XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 21 3 21 1 0 N A N A N A Asynch 1 N A Don t care for this example Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 127 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 26 External Interface Ready on Write Timing With One External Wait State Table 6 41 External Memory Interface Write Switching Characteristics Ready on Write 1 Wait State PARAMETER MIN MAX UNIT ta xCOH XZCSL Delay time XCLKOUT high to zone chip select active low 1 ns la XCOHL XZCSH Delay time XCLKOUT high or low to zone chip select inactive high 2 3 ns la XCOH XA Delay time XCLKOUT high to address v
174. nctionality and interrupt generating capability must be disabled Otherwise interrupts may be inadvertently triggered This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO pins since a value of zero for or GPDDAT 5 PDPINTx puts PWM pins in a high impedance state The CxTRIP and TxCTRIP pins also put the corresponding PWM pins in high impedance if they are driven low as GPIO pins and bit EXTCONx 0 1 Copyright 2009 2010 Texas Instruments Incorporated Peripherals 81 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 5 Development Support Texas Instruments TI offers an extensive line of development tools for the C28x generation of DSPs including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The following products support development of F2812 based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE C C Compiler Code generation tools Assembler Linker Cycle Accurate Simulator Application algorithms Sample applications code Hardware Development Tools F2812 eZdsp JTAG based emulators SPI515 XDS510PP XDS510PP Plus XDS510 USB Universal 5 V dc power supply Documentation a
175. nd cables 5 1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle assigns prefixes to the part numbers of all TMS320 DSP devices and support tools Each TMS320 DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMS320F2812GHH Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS SM Fully qualified production device SMJ Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard wa
176. nditions B Ibp represents the total current drawn from the 1 8 V Vpp It includes a trivial amount of current 1 mA drawn by C IDDA represents the current drawn by VDDA1 and VDDA2 rails D Total 3 3 V current is the sum of Ippio IppsveL and Ippa It includes a trivial amount of current 1 mA drawn by VDDAIO Figure 6 2 Typical Current Consumption Over Frequency 700 600 500 g 400 300 200 100 0 0 20 40 60 80 100 120 140 160 SYSCLKOUT MHz s TOTAL POWER Figure 6 3 Typical Power Consumption Over Frequency Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 89 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 6 Reducing Current Consumption 28x DSPs incorporate a unique method to reduce the device current consumption A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application Table 6 1 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals Table 6 1 Typical Current Consumption by Various Peripherals at 150 MHz PERIPHERAL MODULE lbo CURRENT REDUCTION mA eCAN 12 EVA EVB ADC 89 SCI SPI 5 McBSP 13 1 All peripheral clocks are disabled upon reset Wri
177. nformation 96 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Vppio Vpp3vFL 25V VppAn Vppalo 3 3 V See Note B __ XCLKIN Sy a Ge 55500555509 PRR CKD XCLKIN a See Note XCLKOUT User Code Dependen toscsT gt XRS i tw RSL1 of Address Data Valid Internal Boot ROM Code Execution Phase Address Data 926020202000 260505026 00 000 0000000000 Control ta EX EUN User Code Execution Phase tsu XPLLDIS User Code Dependent XPLLDIS Sampling 4 gt th XPLLDIS ATAPECDS Doivt Care A GPIOF14 th XMP MC M MIMIM NI NI 55555555550 5555559 th boot mode See Note D User Code Dependent Boot Mode Pins GPIO Pins as Input Peripheral GPIO Function Based on Boot Code Y Y V Pins X a GPIO Pins as Input State Depends on Internal PU PD XXX User Code Dependent NOTES A The state of the GPIO pins is undefined i e they could be input or output until the 1 8 V or 1 9 V supply reaches at least 1 V and 3 3 V supply reaches 2 5 V B Vppan VppA1 Vppa2 and AVDDREFBG C Up
178. ng diagrams for levels used for testing timing parameters Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100 To shorten the symbols some of the pin names and other related terminology have been abbreviated as follows Lowercase subscripts and their meanings Letters and symbols and their meanings a access time H High cycle time period L Low d delay time V Valid f fall time X Unknown changing or don t care level h hold time Z High impedance r rise time Su setup time t transition time valid time pulse duration width Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 10 General Notes on Timing Parameters All output signals from the 28x devices including XCLKOUT are derived from an internal clock such that all output transitions for a given half cycle occur with a minimum of skewing relative to each other The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles For actual cycle examples see the appropriate cycle description section of this document 6 11 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document Tester Pin Electronics Data Sheet Timin
179. nnels QEP2 CER QEP4 GERI QEPI1 2 Direction TDIRA Direction TDIRB External Clock Inputs External Clock TCLKINA External Clock TCLKINB C1TRIP C4TRIP External Trip Inputs Compare C2TRIP Compare C5TRIP CSTRIP C6TRIP TICTRIP_PDPINTA 1 External Trip Inputs m TRIBUS T2CTRIP EVASOC 1 In the 24x 240x compatible mode the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Peripherals 55 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 4 3 EVA Registers TEXAS INSTRUMENTS www ti com NAME ADDRESS SIZE x16 DESCRIPTION GPTCONA 0x00 7400 1 GP Timer Control Register A TICNT 0x00 7401 1 GP Timer 1 Counter Register T1CMPR 0x00 7402 1 GP Timer 1 Compare Register T1PR 0x00 7403 1 GP Timer 1 Period Register T1CON 0x00 7404 1 GP Timer 1 Control Register T2CNT 0x00 7405 1 GP Timer 2 Counter Register T2CMPR 0x00 7406 1 GP Timer 2 Compare Register T2PR 0x00 7407 1 GP Timer 2 Period Register T2CON 0x00 7408 1 GP Timer 2 Control Register EXTCONA 0x00 7409 1 GP Extension Control Register A COMCONA 0x00 7411 1 Compare Control Register A ACTRA 0x00 7413 1 Compare Action Control Register A DBTCONA 0x00 7415 1 Dead Band Tim
180. nsmit Register SCIFFRXB 0x00 775B 1 SCI B FIFO Receive Register SCIFFCTB 0x00 775C 1 SCI B FIFO Control Register SCIPRIB 0x00 775F 1 SCI B Priority Control Register 1 Shaded registers are new registers for the FIFO mode 2 Registers in this table are mapped to peripheral bus 16 space This space only allows 16 bit accesses 32 bit accesses produce undefined results 74 Peripherals Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Figure 4 10 shows the SCI module block diagram Frame Format and Mode Parity Even Odd Enable TXWAKE 1 SCIHBAUD 15 8 Baud Rate MSbyte Register SCILBAUD 7 0 Baud Rate LSbyte Register LSPCLK Fexeror Figure 4 10 Serial Communications Interface SCI Module Block Diagram TX INT ENA Transmitter Data Buffer Register SCICTL2 0 8 interrupt TX FIFO 1 TX Interrupt Logic SCITXBUF 7 0 SCI TX Interrupt select logic TX FIFO registers SCIFFENA SCIFFTX 14 SCIRXD SCITXD Register RXWAKE RX BK INT ENA eive Buffer register RXRDY SCIRXBUF 7 0 8 RX FIFO _15 DL mf RX FIFO 1 RXFIFO 0 SCIRXBUF 7 0 RX FIFO registers RXFFOVF RX ERR INT ENA SCI RX Interrupt select logic Copyright 2009 20
181. nto STANDBY mode 32 SYSCLKOUT Cycles B The PLL block responds to the STANDBY signal SYSCLKOUT is held for approximately 32 cycles before being turned off This 32 cycle delay enables the CPU pipe and any other pending operations to flush properly mmoo The device is now in STANDBY mode The external wake up signal is driven active negative edge triggered shown as an example After a latency period the STANDBY mode is exited Normal operation resumes The device responds to the interrupt if enabled Figure 6 14 STANDBY Entry and Exit Timing 102 Electrical Specifications Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 12 HALT Mode Switching Characteristics PARAMETER MIN TYP MAX UNIT Delay time IDLE instruction executed to XCLKOUT tatDLE xcoH high 32 x tesco 45 x tesco Cycles tw WAKE XNMI Pulse duration XNMI wakeup signal 2 x Cycles tw WAKE XRS Pulse duration XRS wakeup signal 8 x tach Cycles tp PLL lock up time 131 072 Cycles Delay time PLL lock to program execution resume Wake up from flash ta wake Flash module in sleep state 1125 x tesco Cycles Wake up from SARAM 35 x tesco Cycles 1 Not production tested Copyright
182. o expensive high speed memories Special branch look ahead hardware minimizes the latency for conditional discontinuities Special store conditional operations further improve performance 3 2 2 Memory Bus Harvard Bus Architecture As with many DSP type devices multiple busses are used to move data between the memories and peripherals and the CPU The C28x memory bus architecture contains a program read bus data read bus and data write bus The program read bus consists of 22 address lines and 32 data lines The data read and write busses consist of 32 address lines and 32 data lines each The 32 bit wide data busses enable single cycle 32 bit operations The multiple bus architecture commonly termed Harvard Bus enables the C28x to fetch an instruction read a data value and write a data value in a single cycle All peripherals and memories attached to the memory bus prioritizes memory accesses Generally the priority of Memory Bus accesses can be summarized as follows Highest Data Writes Program Writes Data Reads Program Reads Lowest Fetches 3 2 3 Peripheral Bus To enable migration of peripherals between various Texas Instruments DSP families the F2812 adopts a peripheral bus standard for peripheral interconnect The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals Two version
183. oduct Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Table 2 3 Signal Descriptions continued PIN NO DIE PAD _DIEPAD DIE PAD NAME 172 PIN NO X CENTER Y CENTER 10 20 PU PDO DESCRIPTION HFG ADC ANALOG INPUT SIGNALS ADCINA7 163 186 42 6 1253 9 ADCINA6 164 188 42 6 1094 3 ADCINA5 165 190 42 6 954 0 Eight channel analog inputs for ADCINA4 166 192 42 6 794 4 Sample and Hold A The ADC pins should ADCINA3 167 194 42 6 654 1 not be driven before Vopa2 and Vppaio pins have been fully powered up ADCINA2 168 196 42 6 513 9 ADCINA1 169 197 42 6 434 1 ADCINAO 170 198 42 6 354 3 ADCINB7 9 13 1355 2 42 6 ADCINB6 8 11 1164 6 42 6 ADCINB5 7 10 1069 2 42 6 Eight channel analog inputs for ADCINB4 6 8 878 6 42 6 Sample and Hold B The ADC pins should ADCINB3 5 6 688 0 42 6 not be driven before the and V ins have been fully powered up ADCINB2 4 4 497 4 42 6 BPA BE P ADCINB1 3 3 402 1 42 6 ADCINBO 2 2 306 8 42 6 ADC Voltage Reference Output 2 V Requires a low ESR 50 mQ 1 5 ceramic bypass capacitor of 10 uF to analog ground Can accept external ADCREFP 11 15 1545 8 42 6 reference input 2 V if the software bit is enabled for thi
184. oltages above 3 0 V produce full scale conversion results Fast conversion rate 80 ns at 25 MHz ADC clock 12 5 MSPS 16 channel MUXed inputs e Autosequencing capability provides up to 16 autoconversions in a single session Each conversion be programmed to select any 1 of 16 input channels Sequencer can be operated as two independent 8 state sequencers or as one large 16 state sequencer i e two cascaded 8 state sequencers Sixteen result registers individually addressable to store conversion values The digital value of the input analog voltage is derived by Digital Value 0 when input x 0 V Digital Value pee when 0 v lt input lt 3 V Digital Value 4095 when input 2 3 V Multiple triggers as sources for the start of conversion SOC sequence SM software immediate start EVA Event manager multiple event sources within EVA EVB Event manager B multiple event sources within EVB Flexible interrupt control allows interrupt request on every end of sequence EOS or every other EOS e Sequencer can operate in start stop mode allowing multiple time sequenced triggers to synchronize conversions EVA EVB triggers can operate independently in dual sequencer mode e Sample and hold S H acquisition time window has separate prescale control The ADC module in the F2812 has been enhanced to provide flexible interface to event managers A and B The ADC interface is built around a
185. omments regarding this TMS320F281x TMS320C281x data manual literature number SPRS174 use the commentsatbooks sc ti com email address which is a repository for feedback For questions support contact the Product Information Center listed at http www ti com sc docs pic home htm site 6 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the SM SMJ320F 2812 DSP 6 1 Absolute Maximum Ratings Unless otherwise noted the list of absolute maximum ratings are specified over operating temperature ranges Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 6 2 is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability All voltage values are with respect to Vss VALUE UNIT Pad Md range Vppio Vopa2 VppAio and 0 3 to 4 6 V Supply voltage range 0 5 to 2 5 V VppaveL range 0 3 to 4 6 V Input voltage range Vin 0 3 to 4 6 V Output voltage range Vo 0 3 to 4 6 V Input clamp current lik Vin lt 0 or Vin gt Vppio 20 Output clamp current lox Vo lt 0 or Vo gt Vppio 20 mA Operating ambient temperature range 2 S Temp
186. on power up SYSCLKOUT is XCLKIN 2 if the PLL is enabled Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT XCLKIN 8 during this phase D After reset the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles SYSCLKOUT XCLKIN 2 and then samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function in ROM The BOOT Mode pins should be held high low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes If Boot ROM code executes after power on conditions in debugger environment the Boot code execution time is based on the current SYSCLKOUT speed The SYSCLKOUT is based on user environment and could be with or without PLL enabled See Note A Boot ROM Execution Starts Figure 6 9 Power on Reset in Microcomputer Mode XMP MC 0 See Note A Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 97 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Vppio VppsvFL Vopaio 25V 3 3 V VDD VDD1 1 8 V or 1 9 V 0 3V NQZ NA toscsr XCLKOUT _ NN XCLKIN 8 See Note A User Code Dependent
187. onform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 2 2 Device Summary Table 2 1 provides a summary of the device features Table 2 1 Hardware Features TEXAS INSTRUMENTS www ti com FEATURE F2812 Instruction Cycle at 150 MHz 6 67 ns Single Access RAM SARAM 16 bit word 18K 3 3 V On Chip Flash 16 bit word 128K On Chip ROM 16 bit word Code Security for On Chip Flash SARAM OTP ROM Yes Boot ROM Yes OTP ROM 1K x 16 Yes External Memory Interface Yes Event Managers A and B EVA and EVB EVA EVB General Purpose GP Timers 4 Compare CMP PWM 16 Capture CAP QEP Channels 6 2 Watchdog Timer Yes 12 Bit ADC Yes Channels 16 32 Bit CPU Timers 3 SPI Yes SCIA SCIB SCIA SCIB CAN Yes McBSP Yes Digital Pins Shared 56 External Interrupts 3 Supply Voltage 1 8 V Core 135 MHz 1 9 V Core 150 MHz 3 3 V I O Temperature Options S 55 to 220 C Yes 14 Introduction Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 2 3 Die Layout The SM320F2812
188. orm generation using programmable deadband circuit The state of each of the six outputs is configured independently The compare registers of the compare units are double buffered allowing programmable change of the compare PWM pulse widths as needed Programmable Deadband Generator Deadband generation can be enabled disabled for each compare unit output individually The deadband generator circuit produces two outputs with or without deadband zone for each compare unit output signal The output states of the deadband generator are configurable and changeable as needed by way of the double buffered ACTRx register PWM Waveform Generation Up to eight PWM waveforms outputs can be generated simultaneously by each event manager three independent pairs six outputs by the three full compare units with programmable deadbands and two independent PWMs by the GP timer compares Double Update PWM Mode The F2812 Event Manager supports Double Update PWM Mode This mode refers to a PWM operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently modifiable in each PWM period To support this mode the compare register that determines the position of the edges of a PWM pulse must allow buffered compare value update once at the beginning of a PWM period and another time in the middle of a PWM period The compare registers in F2812 Event Managers are all buffered and support three com
189. ow Power Modes Block for more details In IDLE mode the WDINT signal can generate an interrupt to the CPU via the PIE to take the CPU out of IDLE mode In HALT mode this feature cannot be used because the oscillator and PLL are turned off and hence so is the WATCHDOG Functional Overview Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 3 12 Low Power Modes Block The low power modes on the F2812 are similar to the 240x devices Table 3 16 summarizes the various modes Table 3 16 F2812 Low Power Modes MODE LPM 1 0 OSCCLK CLKIN SYSCLKOUT EXIT Normal X X on on on XRS WDINT IDLE 0 0 on on on Any Enabled Interrupt XNMI Debugger XRS WDINT XINT1 XNMI on T1 2 3 ACTRIP STANDBY watchdog still running on em C1 2 3 4 5 6T RIP SCIRXDA SCIRXDB CANRX Debugger 9 off XRS HALT 1 oscillator and PLL turned off off off XNMI watchdog not functional Debugger 1 The Exit column lists which signals or under what conditions the low power mode is exited A low signal on any of the signals exits the low power condition This signal must be kept low long enough for an interrupt to be recognized by the device Otherwise the IDLE mode is not exited and the device goes back into the indicated low po
190. pare value reload update value in buffer becoming active modes These modes have earlier been documented as compare value reload conditions The reload condition that supports double update PWM mode is reloaded on Underflow beginning of PWM period OR Period middle of PWM period Double update PWM mode can be achieved by using this condition for compare value reload Peripherals Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 4 2 6 PWM Characteristics Characteristics of the PWMs are as follows 16 bit registers Wide range of programmable deadband for the PWM output pairs Change of the PWM carrier frequency for PWM frequency wobbling as needed Change of the PWM pulse widths within and after each PWM period as needed External maskable power and drive protection interrupts e Pulse pattern generator circuit for programmable generation of asymmetric symmetric and four space vector PWM waveforms Minimized CPU overhead using auto reload of the compare and period registers The PWM pins are driven to a high impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification The PDPINTx pin after qualification is reflected in bit 8 of the COMCONx register PDPINTA pin status is reflected in bit 8 of COMCONA register P
191. pecifications 2 IDDA includes current into VppA1 AVpprersa 3 Test Conditions SYSCLKOUT 150 MHz Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 5 SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Ron Switch Rs ADCINO 1kQ e f Source Ch ac Signal 10 pF 1 25 pF 28x DSP Typical Values of the Input Circuit Components Switch Resistance Ron 1kQ Sampling Capacitor Cph 1 25 pF Parasitic Capacitance 10 pF Source Resistance 500 Figure 6 37 ADC Analog Input Impedance Model 6 29 4 ADC Power Up Control Bit Timing ADC Power Up Delay ADC Ready for Conversions PWDNBG PWDNREF tagean PWDNADC K Request for ADC Figure 6 38 Power Up Control Bit Timing Table 6 49 ADC Power Up Delays 2 MIN TYP UNIT t Delay time for band gap reference to be stable Bits 6 and 5 of the ADCTRLS3 register 7 8 10 nis BGR PWDNBG and PWDNREF are to be set to 1 before the ADCPWDN bit is enabled Delay time for power down control to be stable Bit 7 of the ADCTRL3 register ADCPWDN 20 50 us S PWD is to be set to 1 before any ADC conversions are initiated 1 ms 1 These delays are necessary an
192. r gt T 1 1 1 XRW 7 i if la A th XD XRD XD 0 15 ng tsu XRDYsynchL XCOHL 5 1 le XRDYsynchH th xRDYsynchL Sui th XRDYsynchH XZCSH gt lsu XRDHsynchH XCOHL 11 QO Tigges 555555555 5 5 5 XR EAD Y Synch 95001 See Note D 1 SeeNoteE Don t care Signal can be high or low during this time NOTES A All XINTF accesses lead period begin on the rising edge of XCLKOUT When necessary the device inserts an alignment cycle before an access to meet this requirement B During alignment cycles all signals transitions to their inactive state C During inactive cycles the XINTF address bus always holds the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access D can be calculated as D XRDLEAD XRDACTIVE n 1 tc xriM fsu XRDYsynchL XCOHL E Reference for the first sample is with respect to this point XRDLEAD XRDACTIVE where n is the sample number n 1 2 3 and so forth Figure 6 31 Example Read With Synchronous XREADY Access XTIMING register parameters used for this example XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 21 3 gt 1 1 0 Synch 1 N A Don
193. r Zone 1 can access as two 16 bit registers or one 32 bit register XTIMING2 0x00 0B24 2 Register Zone 2 can access as two 16 bit registers or one 32 bit XTIMING6 0x00 OB2C 2 XINTF Timing Register Zone 6 can access as two 16 bit registers or one 32 bit register XTIMING7 0x00 OB2E 2 e Register Zone 7 can access as two 16 bit registers or one 32 bit XINTCNF2 0x00 0B34 2 Ld Register can access as two 16 bit registers or one 32 bit XBANK 0x00 0B38 1 XINTF Bank Control Register XREVISION 0x00 1 XINTF Revision Register 3 5 1 Timing Registers XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency The timing parameters can be configured individually for each zone This allows the programmer to maximize the efficiency of the bus based on the type of memory or peripheral that the user needs to access All XINTF timing values are with respect to XTIMCLK which is equal to or one half of the SYSCLKOUT rate as shown in Figure 6 27 For detailed information on the XINTF timing and configuration register bit fields see the TMS320x281x DSP External Interface XINTF Reference Guide SPRU067 3 5 2 XREVISION Register The XREVISION register contains a unique number to identify the particular version of XINTF used in the product For the F2812 this register is configured as described in Table 3 9 Table
194. r SPRUOG5 describes the EV modules that provide a broad range of functions and features that are particularly useful in motion control and motor control applications The EV modules include general purpose GP timers full compare PWM units capture units and quadrature encoder pulse QEP circuits TMS320x281x External Interface XINTF Reference Guide literature number SPRU067 describes the external interface XINTF of the 281x digital signal processors DSPs TMS320x281x Multi channel Buffered Serial Ports McBSPs Reference Guide literature number SPRUO61 describes the McBSP available on the 281x devices The McBSPs allow direct interface between a DSP and other devices in a system TMS320x281x System Control and Interrupts Reference Guide literature number SPRUO78 describes the various interrupts and system control features of the 281x digital signal processors DSPs Copyright 2009 2010 Texas Instruments Incorporated Development Support 83 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 84 5320 281 280x Enhanced Controller Area Network eCAN Reference Guide literature number SPRUO74 describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments With 32 fully configurable mailboxes and time stamping feature the eCAN module prov
195. ral Notes on Timing Parameters 93 6 11 Test Load CIICUIE riim ori aoro rea west gu xara RR 93 6 12 Device 8 Doro SI E o rm 94 6 13 Clock Requirements and Characteristics 94 6 13 1 Input Clock Requirements nnne nnne nnne nnn nnn nnne nnn 94 6 13 2 Output Clock Characteristics nen senses nnn 95 6 14 Reset TIMING c rct 96 6 15 Low Power Mode Wakeup Timing eee cece ee eee I Hm mH nmn eme emen eme e nnne nnns 100 6 16 Event Manager Interface senses nennen 104 104 6 16 2 Interrupt Timing 2 4 11 4 4 41 106 6 17 General Purpose Input Output GPIO Output Timing 2 24 4 44 4 4 4 42 2 107 6 18 General Purpose Input Output GPIO Input Timing cesses 108 6 19 SPI Master Mode Timing 1 1 21 1 1 4 4 1 116 ehe se s nnn 109 Copyright 2009 2010 Texas Instruments Incorporated Contents 3 SM320F2812 HT 13 TEXAS INSTRUMENTS SGUSO62A JUNE 2009 REVISED APRI
196. re to detect illegal XTIMING configurations 118 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 or Table 6 31 XTIMING Register Configuration Restrictions XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 22 21 0 22 21 0 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Asynchronous XREADY Table 6 32 Asynchronous XREADY 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0 1 Invalid 1 0 0 1 0 0 0 1 Invalid 1 1 0 1 1 0 0 Valid 1 1 0 1 1 0 1 Valid 1 2 0 1 2 0 0 1 Valid 2 1 0 2 1 0 0 1 1 2 Not production tested No hardware to detect illegal XTIMING configurations Unless otherwise specified all XINTF timing is applicable for the clock configurations shown in Table 6 33 Table 6 33 XINTF Clock Configurations MODE SYSCLKOUT XTIMCLK XCLKOUT 1 SYSCLKOUT SYSCLKOUT Example 150 MHz 150 MHz 150 MHz 2 SYSCLKOUT 1 2 SYSCLKOUT Example 150 MHz 150 MHz 75 MHz 3 1 2 SYSCLKOUT 1 2 SYSCLKOUT Example 150 MHz 75 MHz 75 MHz 4 1 2 SYSCLKOUT 1 4 SYSCLKOUT Example 150 MHz
197. resume Wake up from Flash Flash module in active pi r 12 x tecn Cycles state q Wake up from Flash Flash module in active With input qualifier 12 x toy tw WAKE INT Cycles state la WAKE STBY W Wake up from Flash Without input Flash module in sleep qualifier 1125 x tesco Cycles state Wake up from Flash Flash module in sleep With input qualifier 1125 x tesco tw WAKE INT Cycles state 5 Without input Wake up from SARAM qualifier 12 x tc Cl Cycles Wake up from SARAM With input qualifier 12 tw WAKE INT Cycles 1 Not production tested 2 QUALSTDBY is a 6 bit field in the LPMCRO register 3 This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction Execution of an ISR triggered by the wake up signal involves additional latency Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Electrical Specifications 101 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 Device Status Wake up Signal A Ie Flushing Pipeline tw WAKE INT gt B y tapLE XCOH da WAKE STBY TEXAS INSTRUMENTS www ti com Seg F STANDBY STANDBY X Normal Execution vom NOTES A IDLE instruction is executed to put the device i
198. rfaces can be supported on the McBSP T1 E1 framers MVIP switching compatible and ST BUS compliant devices including MVIP framers H 100 framers SCSA framers OM 2 compliant devices AC97 compliant devices the necessary multiphase frame synchronization capability is provided IS compliant devices McBSP clock rate CLKG DENSIS 1 where CLKSRG source could be LSPCLK CLKX 2 2 Serial port performance is limited by I O buffer switching speed Internal prescalers must be adjusted such that the peripheral speed is less than the I O buffer speed limit 20 MHz maximum Copyright 2009 2010 Texas Instruments Incorporated Peripherals 69 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Figure 4 9 shows the block diagram of the McBSP module with FIFO interfaced to the F2812 version of Peripheral Frame 2 Peripheral Write Bus TXFIFO 15 Interrupt FIFO 1 TX FIFO 1 McBSP Transmit TX FIFO 0 TX FIFO 0 Interrupt Select Logic TX FIFO Registers d LSPCLK McBSP Registers and Control Logic 16 e RBR2 Register 16 DRR2 Recei McBSP Receive Interrupt Select Logic RX FIFO RX Interrupt Logic Interrupt LL Peripheral Read Bus Figure 4 9 McBSP Module Wit
199. rnal Interface XINTF This asynchronous interface consists of 19 address lines 16 data lines and three chip select lines The chip select lines are mapped to five external zones Zones 0 1 2 6 and 7 Zones 0 and 1 share a single chip select Zones 6 and 7 also share a single chip select Each of the five zones can be programmed with a different number of wait states strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not The programmable wait state chip select and programmable strobe timing enables glueless interface to external memories and peripherals 3 2 6 Flash The F2812 contains 128K x 16 of embedded flash memory segregated into four 8K x 16 sectors and six 16K x 16 sectors The F2810 has 64K x 16 of embedded flash segregated into two 8K x 16 sectors and three 16K x 16 sectors The device also contains a single 1K x 16 of OTP memory at address range 0x3D 7800 Ox3D 7BFF The user can individually erase program and validate a flash sector while leaving other sectors untouched However it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase program other sectors Special memory pipelining is provided to enable the flash module to achieve higher performance The flash OTP is mapped to both program and data space therefore it can be used to execute code or store data information NOTE The F2812 Flash and OTP wait states can be
200. rranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used Figure 5 1 provides a legend for reading the complete device name for any TMS320x28x family member 82 Development Support Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 SM 320 F 2812 HFG M PREFIX _ TEMPERATURE RANGE TMX experimental device 6 TMP prototype device S 55 C to 220 C TMS qualified device SM commercial processing SMJ MIL PRF 38535 QML PACKAGE 172 pin CQFP DEVICE FAMILY 320 TMS320 DSP Family KGD Die L DEVICE TECHNOLOGY 2810 Flash EEPROM 1 8 V 1 9 V Core 3 3 V I O 2812 ROM 1 8 V 1 9 V Core 3 3 V I O t Not all combinations of processing options temperature ranges and packages are available CQFP Ceramic Quad Flatpack Figure 5 1 28x Device Nomenclature 5 2 Documentation Support Extensive documentation supports all of the TMS320E DSP family generations of devices from product announcement through applications developm
201. s XHOLD ta HH Hah XHOLDA ta HL Hiz gt ta HH BV XR W XZCSOAND1 o RECS NEED c lt XZCS6AND7 M S XD 15 0 High Impedance lt 1 4 SeeNoteA See Note gt All pending XINTF accesses are completed B Normal XINTF operation resumes Figure 6 36 XHOLD XHOLDA Timing Requirements XCLKOUT 1 2 XTIMCLK 133 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com 6 29 On Chip Analog to Digital Converter 6 29 1 ADC Absolute Maximum Ratings VALUE UNIT Vssa1 Vssaz2 to Vppai VppA2 AVppneErBG 0 3 to 4 6 V Supply voltage range Vss1 to Vpp1 0 3 to 2 5 V Analog Input ADCIN Clamp Current total max 2 20 1 Unless otherwise noted the absolute maximum ratings are specified over operating conditions Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The analog inputs an internal clamping circuit that clamps the voltage to a diode drop above Vppa or below Vss The continuous clamp c
202. s mode 1 uF to 10 uF low ESR capacitor can be used in the external reference mode ADC Voltage Reference Output 1 V Requires a low ESR 50 mQ 1 5 ceramic bypass capacitor of 10 uF to analog ground Can accept external ADCREFM 10 14 1450 5 42 6 reference input 1 V if the software bit is enabled for this mode 1 uF to 10 uF low ESR capacitor can be used in the external reference mode ADC External Current Bias Resistor ADCRESEXT 16 22 2212 9 42 63 24 9 5 Test Pin Reserved for TI Must be left ADCBGREFIN 160 180 42 6 1680 9 unconnected AVSSREFBG 12 17 1831 7 42 6 ADC Analog GND AVDDREFBG 13 18 1736 4 42 6 ADC Analog Power 3 3 V Common Low Side Analog Input Connect ADCLO 171 199 42 6 274 5 to analog ground Vssat 15 21 2117 6 42 6 ADC Analog GND Vssa2 161 182 42 6 1550 7 ADC Analog GND VppA1 14 19 1927 0 42 6 ADC Analog 3 3 V Supply 162 184 42 6 1394 2 ADC Analog 3 3 V Supply Vssi 159 178 42 6 1830 8 ADC Digital GND 158 177 42 6 1901 0 ADC Digital 1 8 V or 1 9 V Supply 1 1 211 5 42 6 3 3 V Analog I O Power Pin Vssaio 172 200 42 6 204 3 Analog I O Ground Pin Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Introduction 21 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com Table 2 3 Signal Descriptions continued
203. s a certain time delay ms range before the ADC is stable and can be used HALT This signal only affects the analog module It does not affect the registers If low the ADC module is powered If high the ADC module goes into low power mode The HALT mode stops the clock to the CPU which stops the HSPCLK Therefore the ADC register logic is turned off indirectly Copyright 2009 2010 Texas Instruments Incorporated Peripherals 61 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Figure 4 5 shows the ADC pin biasing for internal reference and Figure 4 6 shows the ADC pin biasing for external reference ADC 16 Channel Analog Inputs ADCINA 7 0 Analog input 0 3 V with respect to ADCLO ADCINB 7 0 ADCLO Test Pin ADCBGREFINt Connect to Analog Ground 24 9 kQ 20 See Note C ADC External Current Bias Resistor ADCRESEXT ADC Reference Positive Output ADCREFP ADC Reference Medium Output ADCREFM ADCREFP and ADCREFM should not be loaded by external circuitry VDDA1 Analog 3 3 V VDDA2 Analog 3 3 V Vssa1 Vssa2 ADC Analog Power AVDDREFBG t Analog 3 3 V ADC Reference Power AVSSREFBG Analog 3 3 V Analog Ground VDDAIO ADC Analog I O Power Vssalo 1 8 V can use the same 1 8 V or 1 9 V supply as the Digital Ground digital core but separate the two with a ferrite bea
204. s of the peripheral bus are supported on the F2812 One version only supports 16 bit accesses called peripheral frame 2 and this retains compatibility with C240x compatible peripherals The other version supports both 16 and 32 bit accesses called peripheral frame 1 3 2 4 Heal Time JTAG and Analysis The F2812 implement the standard IEEE 1149 1 JTAG interface Additionally the F2812 supports real time mode of operation whereby the contents of memory peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts The user can also 1 Simultaneous Data and Program writes cannot occur on the Memory Bus 2 Simultaneous Program Reads and Fetches cannot occur on the Memory Bus Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 31 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com single step through non time critical code while enabling time critical interrupts to be serviced without interference The F2812 implements the real time mode in hardware within the CPU This is a unique feature to the F2812 no software monitor is required Additionally special analysis hardware is provided which allows the user to set hardware breakpoint or data address watch points and generate various user selectable break events when a match occurs 3 2 5 Exte
205. specified by that device s data sheet No internal device hardware is included to detect illegal settings f the XREADY signal is ignored USEREADY 0 then 1 Lead LR gt te XTIM LW gt taxTiM These requirements result in the following XTIMING register configuration restrictions Table 6 26 XTIMING Register Configuration Restrictions 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 21 20 20 21 20 20 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when not sampling XREADY Table 6 27 Valid and Invalid Timing 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0 1 Valid 1 0 0 1 0 0 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations f the XREADY signal is sampled in the Synchronous mode USEREADY 1 READYMODE 0 then 1 Lead LR gt taxtim LW gt taxtim 2 Active AR 2 2 x AW22x tecxTIM Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 117 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com NOTE Restriction does not include external hardware wait states These requirements result in the following
206. t be adjusted such that the peripheral speed is less than the I O buffer speed limit 20 MHz maximum Data word length one to sixteen data bits Four clocking schemes controlled by clock polarity and clock phase bits include Falling edge without phase delay SPICLK active high SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Falling edge with phase delay SPICLK active high SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal Rising edge without phase delay SPICLK inactive low SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal Rising edge with phase delay SPICLK inactive low SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Simultaneous receive and transmit operation transmit function can be disabled in software Transmitter and receiver operations are accomplished through either interrupt driven or polled algorithms Nine SPI module control registers Located in control register frame beginning at address 7040h NOTE All registers in this module are 16 bit registers that are connected to Peripheral Frame 2 When a register is accessed the register data is in the lower byte 7 0 and the upper byte
207. t device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to
208. t production tested Table 6 55 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 10b CLKXP 0 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M24 tnickxtoFxL Hold time FSX low after CLKX low 2P ns M25 td FXLOCKXH Delay time FSX low to CLKX high P ns Disable time DX high impedance following last data bit from M28 tdis FXHODXHZ FSX high gn imp 9 6 6P 6 ns M29 twexLopxv Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all SPI slave modes CLKX has to be minimum eight CLKG cycles Also CLKG should be LSPCLK 2 by setting CLKSM CLKGDV 1 With maximum LSPCLK speed of 75 MHz CLKX maximum frequency is LSPCLK 16 that is 4 5 MHz and P 13 3 ns LSB CLKX MSB M32 gt gt M33 WF FSX DX Bin X na X X na X M3 7M CM wat DR oa X 9 X na X Figure 6 43 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT Electrical Specifications 145 SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Table 6 56 McBSP as SPI Master or Slave Timing Requirements CLKSTP 11b CLKXP 0 MASTER SLAVE NO UNIT MIN MAX MIN MAX M39 tsu DRV C
209. ted to 3 3 V in ROM parts as well 22 Introduction Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Signal Descriptions Continued PIN NO GPIO 172 PIN DIE PAD NO Y cenTER 022 PUIPD DESCRIPTION GPIO OR PERIPHERAL SIGNALS GPIOA OR EVA SIGNALS GPIOAO PWM1 O 90 104 4908 6 5057 5 0 2 PU GPIOA1 PWM2 O 91 106 4690 0 5057 5 0 2 PU UU no GPIOA2 PWM3 O 92 107 4566 0 5057 5 0 2 PU OU ln a GPIOA3 PWM4 O 93 108 4442 1 5057 5 0 2 PU 51 GPIOA4 PWM5 O 96 111 4070 1 5057 5 Volz PU 4 GPIOAS 6 O 99 114 3766 6 5057 5 0 2 PU 2 bs GPIOA6 HPWM I 100 115 3642 7 5057 5 10 2 PU me GPIOA7 T2PWM T2CMP I 102 117 3394 7 5057 5 0 2 PU ingre GPIOA8 CAP1 QEP I 104 119 3185 9 5057 5 Volz PU ees GPIOA9 2 2 I 105 120 3061 9 5057 5 l O Z PU na D Capture GPIOA10 QEPI I 107 122 2814 0 5057 5 0 2 PU GPIOA11 TDIRA 114 129 2073 2 5057 5 Volz eee GPIOA12 TCLKINA I 115 130 1949 2 5057 5 0 2 PU rei or mimer Glock GPIOA13 CTTRIP 1 119 135 1368 4 5057 5 0 2 PU e1 GPIOA14 C2TRIP 1 120 136 1244 5 5057 5 Volz PU ae ee G
210. teristics 2 2 6 11 STANDBY Mode Switching Characteristics 6 12 HALT Mode Switching Characteristics Lesser 6 13 PWM Switching Characteristics 1 1212 6 14 Timer and Capture Unit Timing Requirements 2 2 2 6 15 External ADC Start of Conversion EVA Switching Characteristics Copyright 2009 2010 Texas Instruments Incorporated SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 IS IS las IN Io IA ie Co 101 103 MONROE RM 105 105 ME 106 List of Tables 7 SM320F2812 HT 13 TEXAS INSTRUMENTS SGUSO62A JUNE 2009 REVISED APRIL 2010 www ti com 6 16 External ADC Start of Conversion Switching Characteristics 222 106 6 17 Interrupt Switching Characteristics 1 lt lt enne he nn nnne enne nnne nennen 106 6 18 Interrupt Timing n nen hme nn n nnne ne nnn nnn nnne nen nn 107 6 19 General Purpose Output Switching Characteristics 107 6 20 General Purpose Input Timing Requirements cceeceeeeeee ence eeeeeeeeeeeeeeeeeneeeeeeaeeeeeeeeeeeeeaeeeeneeenanes 108 6 21 SPI Master Mode External Timing Clock Phase 0
211. the vectors are fetched from Boot ROM This allows the user to either boot from on chip memory or from off chip memory The state of the XMP MC signal on reset is stored in an MP MC mode bit in the XINTCNF2 register The user can change this mode in software and hence control the mapping of Boot ROM and XINTF Zone 7 No other memory blocks are affected by XMP MC I O space is not supported on the 2812 XINTF The wait states for the various spaces in the memory map area are listed in Table 3 2 Table 3 2 Wait States AREA WAIT STATES COMMENTS MO and M1 SARAMs 0 Fixed Peripheral Frame 0 0 wait Fixed Peripheral Frame 1 2 Fixed Peripheral Frame 2 21 Fixed LO and L1 SARAMs 0 wait OTP or ROM Programmable Programmed via the Flash registers 1 wait state operation is possible at a reduced 1 wait minimum CPU frequency See Section 3 2 6 Flash F281x Only for more information Programmable Programmed via the Flash registers 0 wait state operation is possible at reduced Flash or ROM 5 minimum CPU frequency The CSM password locations are hardwired for 16 wait states See Section 3 2 6 Flash F281x Only for more information HO SARAM 0 Fixed Boot ROM 1 wait Fixed Programmed via the XINTF registers XINTF Cycles be extended by external memory or peripheral wait minimum 0 wait operation is not possible 30 Functional Overview Copyright 200
212. ther signals not listed in this group remain in their default or functional operational modes during these signal events Detailed timing diagram is released in a future revision of this data sheet Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 131 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUSO62A JUNE 2009 REVISED APRIL 2010 www ti com 6 28 XHOLD XHOLDA Timing Table 6 44 XHOLD XHOLDA Timing Requirements XCLKOUT XTIMCLK 9 9 MIN MAX UNIT la HL Hiz Delay time XHOLD low to Hi Z on all Address Data and Control Atc xTIM ns ld HL HAL Delay time XHOLD low to XHOLDA low 5 ns la HH HAH Delay time XHOLD high to XHOLDA high Stixri NS la HH BV Delay time XHOLD high to Bus valid Atc xTiM ns 1 When low signal is detected on XHOLD all pending XINTF accesses are completed before the bus is placed in a high impedance state 2 The state of XHOLD is latched on the rising edge of XTIMCLK 3 Not production tested XCLKOUT 1 Mode K N K taHH HAH XHOLDA la HL HAL ta HH BV 95 XR W NEP XZCSOAND1 4 7 52 gt High Impedance BERK XZCS6AND7 XA 18 0 Valid High Impedance lt SeeNoteA See Note 4
213. this requirement During alignment cycles all signals transitions to their inactive state For USEREADY 0 the external XREADY input signal is ignored Figure 6 30 Example Write Access Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT SOE OES OOO OSI All XINTF accesses lead period begin on the rising edge of XCLKOUT When necessary the device inserts an alignment cycle XA 0 18 holds the last address put on the bus during inactive cycles including alignment cycles Electrical Specifications 123 SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 XTIMING register parameters used for this example 1 INSTRUMENTS www ti com XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE N A N A N A 0 0 21 20 20 N A 1 N A care for this example 124 Electrical Specifications Submit Documentation Feedback Product Folder Link s SM320F2812 HT Copyright 2009 2010 Texas Instruments Incorporated 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 25 External Interface Ready on Read Timing With One External Wait State Table 6 37 External Memory Interface Read Switching Characteristics
214. ti com space avionics defense Defense and ZigBee Solutions www ti com Iprf Video and Imaging www ti com video Wireless www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2010 Texas Instruments Incorporated
215. ting to reading from peripheral registers is possible only after the peripheral clocks are turned on 2 Not production tested 3 This number represents the current drawn by the digital portion of the ADC module Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC as well 6 7 Power Sequencing Requirements SM320F2812 silicon requires dual voltages 1 8 V or 1 9 V and 3 3 V to power up the CPU Flash ROM ADC and the I Os To ensure the correct reset state for all modules during power up there are some requirements to be met while powering up powering down the device The current F2812 silicon reference schematics Spectrum Digital Incorporated eZdsp board suggests two options for the power sequencing circuit Option 1 In this approach an external power sequencing circuit enables Vppjo first then Vpp and Vpp 1 8 V or 1 9 V After 1 8 V or 1 9 V ramps the 3 3 V for Flash and ADC VppA1 Vppaz AVppnerao modules are ramped up While option 1 is still valid has simplified the requirement Option 2 is the recommended approach Option 2 Enable power to all 3 3 V supply pins Vppio Vopavet 1 and thenramp 1 8 V or 1 9 V Vpp Vpp4 supply pins 1 8 V or 1 9 V Vpp Vppi should not reach 0 3 V until Vppjo has reached 2 5 V This ensures the reset signal from the pin has propagated t
216. to high All GPIOs 10 ns 7 Fall time GPIO switching high to low All GPIOs 10 ns 7 Toggling frequency GPO pins 20 MHz 1 Not production tested Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 107 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 TEXAS INSTRUMENTS www ti com XCLKOUT YS K GPlo N M Figure 6 21 General Purpose Output Timing 6 18 General Purpose Input Output GPIO Input Timing See Note A GPIO MEE 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 Sampling gt lt QUALPRD SYSCLKOUT QUALPRD 1 2 x SYSCLKOUT cycles x 5 Output From Qualifier NOTES This glitch is ignored by the input qualifier The QUALPRD bit field specifies the qualification sampling period It can vary from 00 to OxFF Input qualification is not applicable when QUALPRD 00 For any other value n the qualification sampling period in 2n SYSCLKOUT cycles i e at every 2n SYSCLKOUT cycle the GPIO pin is sampled Six consecutive samples must be of the same value for a given input to be recognized B For the qualifier to detect the change the input should be stable for 10 SYSCLKOUT cycles or greater
217. tosco IQT Cycles 1 Not production tested 2 Input Qualification Time IQT 5 x QUALPRD x 2 x tesco 3 This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction Execution of an ISR triggered by the wake up signal involves additional latency A0 A15 X X XCLKOUT see Note A WAKE INT 3 5 see Note B ta WAKE IDLE 990900 FPA N N OT FFF X Ne A XCLKOUT SYSCLKOUT B WAKE INT can be any enabled interrupt WDINT XNMI or XRS Figure 6 13 IDLE Entry and Exit Timing 100 Electrical Specifications 45 tw WAKE INT 4 SN Submit Documentation Feedback mmm Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s SM320F2812 HT TEXAS INSTRUMENTS SM320F2812 HT www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Table 6 11 is also the STANDBY Mode Wake Up Timing Requirements table Table 6 11 STANDBY Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time IDLE instruction executed to XCLKOUT high 32 x tesco 12 tecn Cycles Without input t Pulse duration external qualifier P 12 x teci Cycles W WAKE INT wake up signal gt With input qualifier 2 QUALSTDBY teci Cycles Delay time external wake signal to program execution
218. urrent per pin is 2 mA 134 Electrical Specifications Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 6 29 2 ADC Electrical Characteristics Over Recommended Operating Conditions Table 6 46 DC Specifications 2 55 to 220 C PARAMETER UNIT MIN TYP MAX Resolution 12 Bits ADC clock 1 kHz 25 MHz ACCURACY INL Integral nonlinearity 4 1 18 75 MHz ADC clock 1 5 LSB DNL Differential nonlinearity 1 18 75 MHz ADC clock 1 LSB Offset error 9 80 80 LSB ea error with internal 200 200 LSB ee If ADCREFP ADCREFM 1 V 40 1 50 55 LSB Channel to channel offset variation 8 LSB Channel to channel Gain variation 8 LSB ANALOG INPUT ADCS voltage ADCINx to 0 3 V ADCLO 5 0 5 Input capacitance 10 pF Input leakage current 3 5 INTERNAL VOLTAGE REFERENCE Accuracy ADCVnerp 1 9 2 2 1 V Accuracy 0 95 1 1 05 V Voltage difference ADCREFP 1 V ADCREFM Temperature coefficient 50 PPM C Reference noise 100 V EXTERNAL VOLTAGE REFERENCE Accuracy 1 9 2 2 1 V Accuracy ADCVrerm 0 95 1 1 05 V difference ADCREFP 0 99 1 1 01 V 1 Not production tested 2 Tested at 12 5 MHz ADCCLK 3 If SYSCLKOU
219. wait states setup and hold timing and is supported by zone chip selects XZCSOAND1 XZCS2 XZCS6AND7 which toggle when an access to a particular zone is performed These features enable glueless connection to many external memories and peripherals C The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select XZCSOAND1 Any external memory that is connected to XZCSOAND1 is dually mapped to both Zones 0 and Zone 1 D chip selects for Zone 6 and 7 are ANDed internally together to form one chip select KZCS6AND7 Any external memory that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7 This means that if Zone 7 is disabled via the MP MC mode then any external memory is still accessible via Zone 6 address space 40 Functional Overview Figure 3 3 External Interface Block Diagram Submit Documentation Feedback Product Folder Link s SM320F2812 HT Copyright 2009 2010 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com SM320F2812 HT SGUS062A JUNE 2009 REVISED APRIL 2010 The operation and timing of the external interface can be controlled by the registers listed in Table 3 8 Table 3 8 XINTF Configuration and Control Register Mappings NAME ADDRESS SIZE x16 DESCRIPTION XTIMINGO 0x00 0B20 2 ae Register Zone 0 can access as two 16 bit registers or one 32 bit XTIMING1 0x00 0B22 2 XINTF Timing Registe
220. wer mode 2 The IDLE mode on the C28x behaves differently than on the 24x 240x On the C28x the clock output from the core SYSCLKOUT is still functional while on the 24x 240x the clock is turned off 3 On the C28x the JTAG port can still function even if the core clock CLKIN is turned off On the C28x the JTAG port can still function even if the core clock CLKIN is turned off The various low power modes operate as follows IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor The LPM block performs no tasks during this mode as long as the LPMCRO LPM bits are set to 0 0 STANDBY Mode All other signals including XNMI wake the device from STANDBY mode if selected by the LPMCR1 register The user needs to select which signal s wakes the device The selected signal s are also qualified by the OSCCLK before waking the device The number of OSCCLKs is specified in the LPMCRO register HALT Mode Only the XRS and XNMI external signals can wake the device from HALT mode The XNMI input to the core has an enable disable bit Hence it is safe to use the XNMI signal for this function NOTE The low power modes do not affect the state of the output pins PWM pins included They are in whatever state the code left them in when the IDLE instruction was executed Copyright 2009 2010 Texas Instruments Incorporated Functional Overview 51 Submit Documentation Feedback Produ
221. within the Code Composer Studio for TMS320C2000 IDE that simulates the instruction set of the C28x core TMS320C28x DSP BIOS Application Programming Interface API Reference Guide literature number SPRU625 describes development using DSP BIOS TMS320C28x Assembly Language Tools User s Guide literature number SPRU513 describes the assembly language tools assembler and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS320C28x device TMS320C28x Optimizing C Compiler User s Guide literature number SPRU514 describes the TMS320C28x C C compiler This compiler accepts ANSI standard C C source code and produces TMS320 DSP assembly language source code for the TMS320C28x device A series of DSP textbooks is published by Prentice Hall and John Wiley amp Sons to support digital signal processing research and education The TMS320 DSP newsletter Details on Signal Processing is published quarterly and distributed to update TMS320 DSP customers on product information Development Support Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT 1 TEXAS SM320F2812 HT INSTRUMENTS www ti com SGUS062A JUNE 2009 REVISED APRIL 2010 Updated information on the TMS320 DSP controllers can be found on the worldwide web at http www ti com To send c
222. x 16 Ox3E 0000 Ox3E 3FFF Sector G 16K x 16 Ox3E 4000 Ox3E 7FFF Sector F 16K x 16 Ox3E 8000 Ox3E BFFF Sector E 16K x 16 Ox3E C000 Ox3E FFFF Sector D 16K x 16 Ox3F 0000 Ox3F 3FFF Sector C 16K x 16 Ox3F 4000 Ox3F Sector B 8K x 16 Ox3F 6000 Sector A 8K x 16 Ox3F 7F80 Program to 0x0000 when using the Ox3F 7FF5 Code Security Module OxSF 7FF6 Boot to Flash or ROM Entry Point OxSF 7FF7 program branch instruction here Ox3F 7FF8 Security Password 128 Bit Ox3F 7FFF Do not program to all zeros The Low 64K of the memory address range maps into the data space of the 240x The High 64K of the memory address range maps into the program space of the 24x 240x 24x 240x compatible code only executes from the High 64K memory area Hence the top 32K of Flash ROM and HO SARAM block can be used to run 24x 240x compatible code if MP MC mode is low or on the F2812 code can be executed from XINTF Zone 7 if MP MC mode is high The XINTF consists of five independent zones One zone has its own chip select and the remaining four zones share two chip selects Each zone can be programmed with its own timing wait states and to either sample or ignore external ready signal This makes interfacing to external peripherals easy and glueless NOTE The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select XZCSOAND1 and the chip selects of XINTF Zone 6 and Zone 7 are merged together into a single chip se
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224. ynch is found to be high then the access completes If XREADY Asynch is found to be low it wis sampled again each until it is found to be high For each sample setup time from the beginning of the access can be calculated as D XRDLEAD XRDACTIVE 3 n tecxtimy tsu xRDYasynchL XCOHL where n is the sample number n 1 2 3 and so forth Copyright 2009 2010 Texas Instruments Incorporated Electrical Specifications 125 Submit Documentation Feedback Product Folder Link s SM320F2812 HT SM320F2812 HT 1 TEXAS INSTRUMENTS SGUS062A JUNE 2009 REVISED APRIL 2010 www ti com Table 6 40 Asynchronous XREADY Timing Requirements Ready on Read 1 Wait State continued MIN UNIT tsu xRDYAsynchH XCOHL Setup time XREADY Asynch high before XCLKOUT high low 11 ns th xRDYasynchH XZCSH Hold time XREADY Asynch held high after zone chip select high 0 ns See Notes A and B ws Synch Active 4 Lead Trail gt See Note C xcLkour xriMCLK Vf VS LF LSS VLA VLA XCLKOUT 1 2 XTIMCLK A A ta XxCOH XZCSL j ta XCOHL xZzCSH gt 4 XZCSOAND1 2 52 XZCS6AND7 1 gt lt ta xcoH xA i ta XCOHL XRDH gt le ta XCOHL XRDL is XRD ET REL i lsu XD XRD 14 XWE i tg

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