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SIS3302 14xx Firmware - Gamma User Manual

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1. 2 0x00000010 4 RW Acquisition control status register J K register __ INI PS PN 0x00000030 4 RW Broadcast Setup register 0x00000034 4 Memory Page register 0x00000050 4 DAC Control Status register 0x00000054 4 RW DAC Dataregister 0x00000060 RW XILINX JTAG_TEST JTAG_DATA_IN 0 00000064 W XILINXJTAG CONTROL 0x00000080 R W Scan Nof Histograms preset register 0 00000084 _ Scan Histogram counter register 0 00000088 Scan LNE Setup and Prescaler Factor register 0x0000008C Scan Control register 0x00000090 R W Multiscan Nof Scans preset register 0x00000094 Multiscan Scan counter register 0x00000098 Multiscan last Scan Histogram count register 0x00000400 4 KAW address Reset 0x00000404 4 Key address Sample Logic Reset MCA mode 5 0 ps 0 00000410 4 KAW Key address Sample Logic Reset 0 00000414 4 KAW Key address Disarm Sample Logic 0x00000418 4 Keyaddress Trigger 0 0000041 4 KAW Key address Timestamp Clear 0x00000420 4 KAW Key address Disarm Sample Logic and Arm sampling on Bank 1 0x00000424 4 KAW Key address Disarm Sample Logic and Arm sampling on Bank 2 0x00000428 4 KAW Key address Reset DDR2 Me
2. 83 88 CBET 40 ternal TOOMHZ o 37 clock Iaterrupter su 34 COU DIINO aaa eret eta scie oed 37 ipiius abat d dul 34 37 OCOC ON la 7 SIS UI METEO 37 a aaa erie here 22 COCK SOULC SS 36 37 89 35 Aaa aa a ata a it teeny 85 94 REG ta sa E 35 CONN SUr ON cala 85 MISE TAINO a a 35 COMMECLOP TYPES 92 IRO MO alta oa n af ea aa ata i a a 34 control ROAK li a ad dd dea lat a e 34 ON 83 RORA ot H 34 ee aaa ana la oala e ashes 63 ig 36 E aupra tea da ai noa la ada tie 32 88 COOLITI data oala aaa nat lada ata 9 eae er in 85 86 87 at liantul sta 32 TETO 85 CVT dal 25 PU 20 E NE 88 acte ao lao PI 84 IP 49 e da aula bara 88 e deal tare 43 2
3. 76 MCA Histogram 74 MCA histogram counter 46 MCA IMI OGG ik 36 MCA LNE Setup and Prescaler Factor 46 MCA 23 MCA Multiscan Last Scan Histogram counter 48 MCA Multiscan Arm Scan 24 MCA Multiscan Nof Scans preset 48 MCA Multiscan Arm Scan Enable 24 MCA Multiscan Scan 48 IM AUS CIE NELU o dest oats 23 counter iie 75 MCA Scan erba ute 23 MCA COLO n c oana 47 MEMO ene bebes 31 77 MCA Scan nof histograms 46 modes of AC UL 80 MCA Trigger Start counter 75 AV CCA CC 14 25 THO Ule E aa 33 Next Neigbor gate 22 next sample adufessose dese 57 Next Neighbor trigger enable 53 pretrigger delay and trigger gate length 25 Next Neighbor Trigger Gate logic 19 previous bank sample 57 tesa 91 raw data buffer conf
4. bodies asta hoan 32 TT 32 84 end address threshold 54 LEDs enerey Cale Iengthis oie tote ty tutes 68 84 Salle 68 IrOnt ANC a ata ate i 94 energy sample length 69 LEMO dog dies n 92 energy sample start index 1 69 MO IN MOJE a dai 39 energy sample start index 2 69 MO INN 36 energy sample start index 3 69 LEMO OUT bud 37 enere y botul 67 LEMO OUT MOGG 36 enero y AU TACLOE d ate de 70 live ANS CL LOB uo 91 93 event 52 59 60 67 event extended configuration 53 eH 14 25 firmware revision 00 22 33 MA decor 26 interrupt configuration eee eee eee 34 MEA INI i bo 13 27 interrupt control 35 MCA ENERGY to Histogram Calculation MCA ENERGY to High counter 76 72 MCA ENERGY to Low counter
5. 0 2 0 Page 40 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME i Broadcast functionality is implemented for all Key address cycles Modules which are supposed to participate in a broadcast have to get the same broadcast address The broadcast address is defined by the upper 5 bits of the broadcast setup register One module has to be configured as broadcast master the enable broadcast bit has to be set for all modules as illustrated below 0 jud O Broadcast enable Broadcast enable Broadcast enable VME Crate Broadcast setup example broadcast address 0x38000000 Broadcast Setup Register 0x38000030 0x38000010 Broadcast enable 0x38000010 Broadcast enable 0x38000010 Broadcast enable All 4 modules will participate in a key reset A32 D32 write to address 0x38000400 Note Do not use a broadcast address that 15 an existing VME address of a VME card in the crate Page 41 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 7 ADC Memory Page register define SIS3302 ADC MEMORY PAGE REGISTER 0x34 read write D32 The 5153302 default memory size per channel 15 64 MByte 1 32 MSample The VME address space window per ADC is limited to 8 MByte 4 MSample however The read write ADC memory page register is used to select one of the 8 memory subdivisions pages _ 2 Pager
6. des ta atei cot 42 do O DACCONPROL REGISTER 5 256 li Baia to tea Da cae ala 43 4 8 1 DAC COntrol Status Te 43 4 6 2 DAC DO eer itat bi Ca 44 4 8 3 DA SCQUCHCE C _ n 44 4 9 HISTOGRAMS PRESET REGISTER si oa sa sama ste e aaa nato ap la ala a nd Baa al tale da aaa 46 A10 SCAN HISTOGRAM COUNTER REGISTER ga saltea nad aa ate tata coala Dat ala 46 4 11 MCASCAN LNE SETUP AND PRESCALER FACTOR REGISTER eene enne 46 AIE ONTROLAREGIS TER 47 413 NOF SCANS PRESEI REGISTER 48 AVA MULTISCAN SCAN COUNTER REGIS ER atata ceata dis Data dala 48 4 15 MULTISCAN LAST SCAN HISTOGRAM COUNTER REGISTER 48 4 16 KEY ADDRESS GENERAL RESET 0 400 0 000000001 49 Page 4 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 4 17 KEY ADDRESS SAMPLE LOGIC RESET O0X4404 esses e mee n ne enne enne rennen nun 49 4 6 KEYADDRESSES WOH MC ACMODE S
7. ste po adera anal e da ala data 88 IDAC lodd SEquefi6e r a nd 44 28 85 CEA Sociol deisel bales odaie dae isl os bs 22 detto tie smiles 85 94 22 fee 86 CECONV ONION aid ba ea 14 JIA aa td el al lite band 87 PES acidic siones apio sa nd 92 jumper disarm and arm bank 1 50 ISO emt aa 95 34 double buffer 1 222 80 disarm sample 49 Enero yV eE os d ie lat dida 27 GENELE SE bataia a 49 FAST FIR 10 MCA Multiscan Arm with Scan operation Arm 51 AU 85 MCA Multiscan Arm with Scan operation firmware ee rtv vaii aie 94 od aee ar 51 92 MCA Multiscan Disable 51 FPGA MCA Multiscan Start Reset pulse 51 84 MCA Scan 51 front panel aaa baia 82 MCA Scan Enable esses 51 G 49 MCA Scan LNE 50 28
8. 92 Ws 64 99 Io PCTS CHELAN ON eda 10 Status TELISTO age de 32 Pm 11 SM Bata ta 28 88 PIS Set Gate TOPIC 17 SW seta ea la nai Al ia 28 88 user 26 27 32 85 85 85 NIV IQ 91 85 CORITIGC DOE 92 termination VME ACI E nau aa 28 92 candi aaa lea edeme 91 93 EM P 85 MIE OA X P 93 trapezoidal energy filter 12 oda bt d us alt dd 92 trapezoidal trigger 10 Page 97 of 97
9. cc TI 4 42 1 Event Buffer Data Format With MCA Mode 0 77 5 MODES OF ACQUISITION OF CURRENT 80 5 1 SINE EBEN ta ati tan i at dE 90 2 2 MULTI EVENT DOUBLE BUFFER 1 00000000000000000000000000 80 81 2 odaie COD obezi e 82 7 1 CONTROL IN 4 E _ __ 63 SERIES ee t M ecd 84 7 3 CHANNEL EE D S __ _ _ _ _____ 84 Page 5 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 7 4 de 3D 44 6 JUMPERS CONEBIGURA TION 55225 85 8 1 CONDOTTA tc eet she ta a la gt 85 8 2 VME ADDRESSING MODE RESET BEHAVIOUR 85 8 3 ul tt CAE i lt 86 8 4 PO SOURCE a aur A a wr Stat
10. 49 4 18 1 Key address Sample Logic reset 0 410 02 2 02 2 2 2 2 2 2000000000000000000000000000000 49 4 18 2 Key address VME Disarm Sample logic esses 49 4 18 3 Key address VME Trigger 0 418 49 4 18 4 Key address Timestamp Clear 0 41 eee eee 49 4 18 5 Key address Disarm Sample Logic and Arm sampling on Bank 1 0 420 50 4 18 6 Key address Disarm Sample Logic and Arm sampling on Bank 2 0 424 50 419 KEY ADDRESSES WITH MCA MODE mI ie sete ce coo e Rn oa ia ERAN oe tu ea ca 50 4 19 1 Key address MCA Scan LNE pulse 0 410 0000000000000000000000000000000000 50 4 19 2 Key address MCA Scan Operation Arm 0 414 22202 22 2200000000000000000000000 50 4 19 3 Key address MCA Scan Enable 0 418 51 4 19 4 Key address MCA Scan Disable 0 41 51 4 19 5 address MCA Multiscan Start Reset pulse 420 51 4 19 6 Key address MCA Multiscan Arm with Scan operation Arm 424 51 4 19 7 Key address MCA Multiscan Arm with Scan operation Enable 0 428 51 4 19 8 Key address MCA Multiscan Disable 0x42C esses 51 420 EVENT CONFIGURATION REGI
11. ALL 0x01000054 define 5153302 ENERGY SAMPLE START ADC12 0x02000054 define 5153302 ENERGY SAMPLE START INDEX3 4 0x02800054 define 5153302 ENERGY SAMPLE START INDEX3 ADC56 0x03000054 define 5153302 ENERGY SAMPLE START ADC78 0x03800054 Function 0 Energy Sample Start Index3 Energy Sample Start Index3 0 disable Start Page 69 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 4 35 Energy Tau Factor registers define SIS3302_ENERGY_TAU_FACTOR_ADC1357 0x01000058 fdefine 5153302 ENERGY TAU FACTOR ADC2468 00 90 0056 define SIS3302_ENERGY_TAU_FACTOR_ADC1 0x02000058 define 5153302 ENERGY TAU FACTOR ADC2 002000056 define SIS3302_ENERGY_TAU_FACTOR_ADC3 0x02800058 define 5153302 ENERGY TAU FACTOR 4 0x0280005C define 5153302 ENERGY TAU FACTOR ADC5 0x03000058 define 5153302 ENERGY FACTOR ADCO 0x0300005C define 5153302 ENERGY TAU FACTOR ADC7 0x03800058 define 5153302 ENERGY TAU FACTOR ADCS8 0x0380005C Those registers hold the 6 bit wide Tau factor for the corresponding ADC They are implemented on the FPGA group level also what allows you to run all 8 channels on the board with individual Tau settings 4 5 Bit 5 of Tau factor 0 Bit O of Tau factor The decay time depends on the Tau factor on the decimation mode and on the sample clock Switch gl urst S193230Z2ClockModeConr case Qr 74 intern 100
12. ENERGY2LOW COUNTER ADC2 0x0200009C define 5153302 ENERGY2LOW COUNTER ADC3 0x0290009C define SIS3302_MCA_ENERGY2LOW_COUNTER_ADC4 0 0280009 define SIS3302_MCA_ENERGY2LOW_COUNTER_ADC5 0x0300008C define 5153302 MCA ENERGY2LOW COUNTER ADCO 0xUSDODOSC define 5153302 MCA ENERGY2LOW COUNTER ADC7 0x0380008C define 5153302 MCA ENERGY2LOW COUNTER ADCS8 0x0390009C This 32 bit counter is cleared with a Multiscan or Scan operation start command During the Multiscan or Scan operation is active this counter will be incremented if the calculated Histogram Index is negative Page 76 of 97 SIS Documentation 5153302 14xx SIS GmbH A Firmware Gamma VME 4 42 ADC memory define 5153302 1 OFFSET 0x04000000 define 5153302 ADC2 OFFSET 0x04800000 define 5153302 ADC3 OFFSET 0x05000000 define 5153302 4 OFFSET 0x05800000 define 5153302 ADC5 OFFSET 0x06000000 define 5153302 ADC6 OFFSET 0x06800000 define 5153302 ADC7 OFFSET 0x07000000 define 5153302 ADC8 OFFSET 0x07800000 The 64 MByte ADC memory per channel can be address in pages of 8 MByte The page is selected with the ADC Memory page register One 32 bit word holds 2 ADC samples as shown in the table below 4 42 1 Event Buffer Data Format with MCA Mode 0 31 16 15 0 Timestamp 47 32 Event Header ID Timestamp 31 16 Timestamp 15 0 sample 2 sample 1 ADC raw data buffer Za pie ame programable length 0 to 65532 s
13. Multiscan operation The register content 15 updated with the start signal pulse 4 15 MCA Multiscan Last Scan Histogram counter register define 5153302 MCA MULTISCAN LAST SCAN HISTOGRAM COUNTER 0x98 This 32 bit deep register holds the number of histograms of the last earlier scan in MCA Multiscan operation It is updated with the start in MCA Multiscan operation Page 48 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 4 16 Key address general reset 0 400 define 5153302 KEY RESET 0 400 p Gris D32 Ww A write with arbitrary data to this register key address resets the SIS3302 to it s power up state 4 17 Key address Sample Logic reset 0x404 define 5153302 KEY 0x404 SAMPLE LOGIC RESET 024 04 write only D32 A write with arbitrary data to this register key address resets the sampling logic The moving average sums are cleared at the same time This key write has to be used after the P and G parameters are updated and before a key arm is issued Undefined behavior negative sign e g may result otherwise 4 18 Key addresses with MCA mode z 0 4 18 1 Key address Sample Logic reset 0x410 define 5153302 KEY SAMPLE LOGIC RESET 0x410 PE Wee 20320 A write with arbitrary data to this register key address resets the sampling logic The moving average sums are cleared at the same time This key write has to be used after the P and G parameters are updated and
14. 2 Suchen gt gt Ordner Adresse C sis3302_gamma_system cvi work_version_1012007 Header Wechseln zu Mame Grobe Ge ndert am ic pc T5 communication address map h 11KB 5 29 04 2005 10 32 sis3150 h SKB Source File 27 05 2005 09 51 sis3150_global h 32KB Source File 10 12 2007 12 33 sis3150usb h Source File 28 11 2005 12 36 ic 5153302 v1201 h 13KB Source File 10 12 2007 18 00 sis 3920_clock h 8kKB Source File 25 04 2005 14 26 ic 5159300 24 Source File 14 03 2005 09 02 ic sis9300_gamma h 8KB Source File 15 12 2007 18 18 Page 89 of 97 SIS Documentation 5153302 14xx Firmware Gamma 9 2 Ccode Following C files are part of the software PE Datei Bearbeiten Ansicht Favoriten Extras 7 o zur ck gt T 7 Suchen Ordner Hae Adresse suchergebnisse Wechseln ic pc ko routines c 5153150 display routines c ie 5153150 energy speckrum 5153150 gamma_diagnastic c 5153150 gamma_offline c 5153150 _ gamma running ie 5153150 main c 23150 utils c Following files are most important to get started with your own project 5153302 holds the configuration for the digitizer sis3 150_gamma_running c holds the readout code Page 90 of 97 SIS GmbH VME SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Ga
15. 22979 m L Ww 7 0D e T Ld E QNI 525 11 m d 0 a ___ LL S ENERGY MAX 4000 E _ __ 4 55 FECA i ves is acad PERS 1 Ps Peer 5 B show all Reset T X Position Page 26 of 97 SIS Documentation 5153302 14xx 2 2 9 5 Energy Filter data with Tau correction MAWD screenshot Firmware Gamma Energy Filter Values Panel Plot Style Line Style Plot Background Color Grid Color 24498 99393 cm 1 2 confi Wo poet ci a ete a Laie E ui Uy STORES vene in AY Reset i 3 saca a Vise a Ji poe i c Do ao 5 hy SIS GmbH VME 0 Y Max Scale ENERGY a ENERGY_MIN Y Min Scale 3 show O XPostion Module 1l b d ala Page 27 of 97 SIS Documentation SIS3302 14xx SIS GmbH Firmware Gamma VME 3 Addressing As the SIS3302 FADC features memory options with up to 8 times 32 MSamples A32 addressing was implemented as the only option The module occupies an address space of 7 Bytes 1 e 128 MBytes are used by the module The base address is defined by the selected addressi
16. Scan Operation Arm 50 gamma logic implementation 9 sample logic 49 Page 95 of 97 SIS Documentation 5153302 14xx SIS GmbH A Firmware Gamma VME timestamp 49 parameter 15 daci obama 49 S o ioris siot raat 16 eee rere 93 disarm and arm bank 1 50 80 power consumption ca be abe 9 disarm and arm bank 2 50 80 PROM 85 94 CIEL Al LOSE salua 49 raw pre sample length 56 CSS er 41 raw sample length 56 rtr T 84 PAW SUS 26 IB utin er 45 register LED acquisition control 36 A 84 actual Sample oer ertet 58 84 actual sample value 45 P 84 ADC memory 42 77 R 84 Droadcast QN eot 40 41 AN 84 cita 33 vid se Ara P 84 DAC CONTO E al 43 nm 84 dac Al 44 TR 94 DAC Slats dati 43 U 84 descri
17. p D eT TT NEA IN RE IONA er i RAR 95 Page 6 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 2 Introduction This firmware manual addendum describes the functionality and implementation of the 5153302 firmware major revision 0x14 Besides finite response filter FIR based triggering this version supports asynchronous readout of a programmable set of features of raw Le digitized wave form and or computed like signal height energy e g digitizer information No hardware modification to the 5153302 is required for installation of this firmware This firmware implementation should be of particular interest for detector studies with Gamma ray tracking and strip detectors Page 7 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 2 1 Functionality The main functions of the firmware listed below and illustrated in the Gamma logic block diagram 8 channel asynchronous and synchronous operation Decimation Trapezoidal Energy filter Trigger FIR filter Trigger or output 48 bit Timestamp e Flexible event storage e MCA Histogramming in the ADC Memory Page 8 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 2 2 Gamma Logic Implementation 2 2 1 General block diagram of one ADC channel and the full module SIS3302 Gamma V_ 1406 External Gate Veto depends on Lemo Input Mode and Enable front panel In
18. 0 17 Load shift register of selected DAC 1 Load selected DAC 01 1 Clear all DACs A Clear DAC command sets the value of all DACs to analog ground Page 43 of 97 SIS Documentation SIS3302 14xx SIS GmbH Firmware Gamma VME 4 8 2 DAC Data register derine 5153302 DAC DATA 0x54 read write D32 DAC Input Register Bit 15 from DAC DAC Input Register Bit 0 DAC Output Register Bit 15 DAC Output Register Bit 15 0 DAC Output Register Bit 0 DAC Output Register Bit 0 4 8 3 DAC load sequence The sequence to load the DAC of a single channel is shown below The example routine sis3302_write_dac_offset loads the 8 DACs of a SIS3302 module at base address module_ offset in a loop Sequence to load offset of channel N 0 7 dacdata dacdatum N daccontrol 1 shift N lt lt 4 read dacstatus until busy 0 daccontrol 2 load lt lt 4 read dacstatus until busy 0 Page 44 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME Find below a DAC scan that was acquired with the DAC test function of the SIS3302 ADC Labwindows application The SIS3302 under test was configured for an input span of some 2 It can be seen that a DAC offset of some 37000 counts is required to accomplish input range of 1 1 on this particular channel RAW SIGNALS Locati
19. 0x05800000 8MBye X ADC4memoypage 0x06000000 8MBye X ADCSmemoypae 0x06800000 8MBye X R ADC 6 memory page 0x07000000 8 MByte X _ 7 memory page 0x07800000 8 MByte X ADC S8 memory page Page 31 of 97 SIS Documentation SIS3302 14xx SIS GmbH Firmware Gamma VME 4 Register Resource Description The Ox12xx firmware related registers are described in this section The define statements were taken from 5153302 1201 header file Examples refer to C code which 15 underlying the sis3150_3302_gamma CVI project 4 1 Control Status register rdetine 5Ir93302 CONTROL STATUS 0 0 read write 032 The control register 15 implemented as a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time The only function at this point time is user LED on off On read access the same register represents the status register 31 Clear reserved 156 0 2 30 Clear reserved 146 0 29 ____ Clear reserved 136 0 2 28 jClerreerved 12 0 27 Clear reserved 11 6 26 ____ Clear reserved 106 0 25 JjGherrserved9 o 0 24 Clear reserved 8 6 O 23 Clea
20. External Gate External Gate mode aa NR VME Key Trigger External Trigger In depends on Input and Enable front panel In x External Trigger Enable ored Internal Trigger to External Trigger Acquisition Reg bit 6 Feedback ADCx external gate enable Trigger Out Event conf Reg bit 5 13 ADCx internal gate enable Event conf Reg bit 4 12 ADCx external trigger enable ADC 8 ADC 8 Event conf Reg bit 3 11 ADCx internal trigger enable Event conf Reg bit 2 10 Int Trigger ADC N 1 ADC 2 L 77 Next Neighbor Int Trigger ADC Trigger Logic Int Trigger ADC N A AND E 24 Tri i Disable Trigger Out Gate Logie INV Start Pulse Energy Window Fast Trapezoidal FIR Filter Trigger Sampling Logic ADC 1 Decimation 1 2 4 or 8 Internal Trigger P lt 1023 P lt 1023 Trigger Counter Pretrigger Es Delay max 1023 65932 x 16 Clocks min max Values M u E X nergy Energy Filter Decimation lt 1023 Value 1 2 4 8 G lt 255 Buffer 510 x 32 Timestamp Clear In_ 48 bit Timestamp 48 bit Timestamp gt counter latch Page 9 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME 2 2 2 Trap
21. NOTE avoid a power up deadlock situation by not setting Pos 5 and 7 at the same time Page 85 of 97 SIS Documentation SIS3302 14xx SIS GmbH 8 3 JP101 JTAG chain The JTAG chain on the SIS3302 can be configured to comprise the serial PROM only short JTAG chain or to comprise the serial PROM and the 5 Spartan III FPGAs long chain The configuration is selected with the 6 pin array JP101 as sketched below Long Chain 1 3 and 2 4 closed JP101 Short Chain 3 5 and 4 6 closed factory default JP101 Page 86 of 97 SIS Documentation 5153302 14xx 515 GmbH Firmware Gamma VME 8 4 JP102 JTAG source The JTAG chain can be connected to VME or to the JTAG connector CON via the 4 pin jumper array JP102 as sketched below JTAG connected to VME 1 2 closed JP102 JTAG connected to connector CON100 3 4 closed factory default JP102 Page 87 of 97 SIS Documentation 5153302 14 SIS GmbH 4 Firmware Gamma VME i 8 5 JP120A JP120D control input termination The contact pair 1 2 of these 4 jumper arrays is used to connect the termination resistor to the 4 control inputs as illustrated with the schematic for JP120A below Control Input Factory Default JP120A Clock In JP120B JP120C JP120D JP120A 8 0 SW and SW2 VME base address These 2 rotary switches are used to define 2 nibbles of the VME base address in non geographical addressing refer to section base address also Page 88 of
22. Peaking Time Subtract compensates 1 2 4 8 16 5227 Decimation left aligned 29 logic 25 9 delay Delayed MA gic SumGap Time max 511 ADC clock domain Decimated clock domain depending Shift Logic Add p Trigger Pulse 0 10000 ie se to 16 bit g Threshold value Trigger Pulse MUX d Extented Add e ls a Trigger Pulse 0x20 0000 gger 25 Logic Extended Threshold value Extended Threshold Trigger Enable Bit 26 Page 11 of 97 SIS Documentation 5153302 14xx SIS GmbH 2 2 2 2 Signal diagram of the Trigger MAW unit ADC signal MA Peaking Time lt gt Delayed DE MAW 2 2 3 Trapezoidal Energy Filter Slow FIR Filter A trapezoidal FIR filter is implemented for each ADC Channel to generate a moving window average stream MWA A decimation logic average integration is also implemented Features of the Slow FIR Filter Programmable decimation 1 2 4 8 Clocks e Programmable Peaking Time max 1023 Clocks e Programmable Gap Time max 255 Clocks 2 2 3 1 Slow FIR Filter Energy sample logic Five registers are implemented to control the sampling of the MWD e Energy Gate Length Energy Sample Length register Energy Sample Start Index register Energy Sample Start Index2 register Energy Sample Start Index3 register The Slow FIR Filter Energy sample logic starts with the Energy Gate and executes following steps 1 Clears
23. This implies that the module can not be operated VME slot with a special A C backplane like VSB e g The pin assignments of P2 rows A C of the SIS3302 is shown below 6 6 8 DGND ___ 8 DGND 9 25 9 2 START L fe Note The 2 ECL signals are bussed and terminated on the backplane of 1002 crates The user has to insure proper termination if a cable backplane or add on backplane is used Page 92 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 10 5 How d and z Pin Assignments The SIS3302 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing PCB revisions V2 and higher and live insertion hot swap The prepared pins on the d and 7 rows of the and P2 connectors are listed below GND GA y GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND D _ GND vcw VPC D Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Page 93 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME 10 6 Firmware upgrade The firmware of the SIS3302 can be upgraded over JTAG The upgrade options are VME o
24. 0 bank 2 is armed else addr gl uint ModAddrRun 0 SIS3302_KEY DISARM AND ARM BANKI bankl_armed_flag 1 bank 2 is armed if error sub A32D32 write addr 0x0 0 1 SiSVME_ErrorHandling error addr sub vme A32D32 write 4 19 Key addresses with MCA mode 1 4 19 1 Key address MCA Scan LNE pulse 0x410 define SIS3302_KEY_MCA_SCAN_LNE_PULSE 0 410 Do2 7 A write with arbitrary data to this address issues LNE load next event advance to next histogram in MCA mode 4 19 2 Key address MCA Scan Operation Arm 0x414 define 5153302 KEY SCAN ARM 0 414 write only D32 A write with arbitrary data to this address arms the module in MCA mode The MCA Scan operation will start with next LNE signal or Key MCA Scan LNE pulse the MCA Scan Page 50 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 4 19 3 Key address MCA Scan Enable 0x418 define SIS3302 KEY SCAN START 0x418 write only D32 A write with arbitrary data to this address enables starts the MCA Scan operation 4 19 4 Key address MCA Scan Disable 0x41C fdefine SIS3302 KEY MCA SCAN DISABLE Ox41C Wee only p 23 A write with arbitrary data to this address disables the MCA Scan operation 4 19 5 Key address MCA Multiscan Start Reset pulse 0x420 define 5153302 KEY MCA MULTISCAN START RESET PULSE 0x420 Wee D32 A write
25. 00229 37060 1 192 36493 358c1 34cf6 34124 33555 32991 31dc8 31207 i 200 3063f 2fa70 2eeaa 2e2ea 2 723 2cb52 2bf8a 2b3c6 i 208 2a7f9 29c2e 29065 284a6 278e2 26 20 2615a 25595 1 216 249 0 23 0 2324 22687 2labf 20f01 20343 1f78c i 224 lebd3 1 016 10459 1 8 0 1bce8 1012 la56b 199a2 i 232 18de8 1822f 1766f 16ab0 15ef4 1533f 1477f 1 240 1300 1244 11896 10 10125 E545 e9ba de06 1 248 d24f c693 8 26 362 97ac 8bf6 8037 1 256 7472 68bd 5d0f 5154 4594 3935 2e14 2269 i 264 16ab afd 116 f fffffda32 f fffffccf fffffcce fffffcbd fffffcbb i 272 fffffcc5 fffffcce fffffcdd fffffce3 fffffcfa fffffdqd04 fffffdid fffffd2c max Energy 4976e min Energy 11 Flags 1000001 trailer deadbeef Page 78 of 97 SIS Documentation 5153302 14xx Firmware Gamma 5153302 Gamma 27 03 2009 Panel View System Configuration Run Control Offline Diagnostic Test Menues Panel File Windows Test Trigger Energy Filter Values Panel PlotStyle Line Style Plot Background Color Grid Color SPC Single Event only Module 1 1 a c sis3302_gamma_system sis3302_gamma_system D03 27 2009T 11 43 31 M LL LLL Page 79 of 97 SIS Documentation SIS3302 14xx SIS GmbH Firmware Gamma VME 5 Modes of acquisition of current software The current software illustrates two data acquisition modes Single event and multi event double buffer acquisition They can be found in sis3150_ga
26. 0x02800010 define 5153302 ACTUAL NEXT SAMPLE ADDRESS 4 0x02800014 define 5153302 ACTUAL NEXT SAMPLE ADDRESS ADC5 0x03000010 fdefine 5153302 ACTUAL NEXT SAMPLE ADDRESS ADCO 0x03000014 define 5153302 ACTUAL NEXT SAMPLE ADDRESS ADC7 0x03800010 define 5153302 ACTUAL NEXT SAMPLE ADDRESS ADCO 0x03800014 These 8 read only registers hold the current next sampling address for the given channel Note the Next Sample Address points to 16 bit words samples EN DI __ ___ ____________ ______ Next Sample Address Bit 24 Bank flag Next Sample Address Bit 2 Next Sample Address Bit 1 0 Next Sample Address Bit 0 Sample address bits 1 and O are always 0 Data are stored to memory in packets of 4 consecutive samples by the sample logic 4 26 ADC1 8 Previous Bank Sample address register define SIS3302_PREVIOUS_BANK_SAMPLE_ADDRESS_ADC1 0 02000018 fdefine SIS3302 PREVIOUS BANK SAMPLE ADDRESS ADC2 0x0200001C define 5153302 PREVIOUS BANK SAMPLE ADDRESS ADC3 0x02800018 define 5153302 PREVIOUS BANK SAMPLE ADDRESS 4 0x0290001C define 5153302 PREVIOUS BANK SAMPLE ADDRESS ADC5 0x03000018 define 5153302 PREVIOUS BANK SAMPLE ADDRESS 6 0x0300001C define 5153302 PREVIOUS BANK SAMPLE ADDRESS 0x03800018 fdefine 5153302 PREVIOUS BANK SAMPLE ADDRESS 0x039000l1cC These 8 read only registers hold the stored next sampling address of the previous bank It 1s the stop address 1 Note the Next Sample Addres
27. 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME 9 Software getting started The original Gamma implementation was developed for a setup consisting of several SIS3150 CMC carrier boards with SIS9300 digitizer CMCs a SIS3820 clock distributor and a SIS PCI or USB to VME interface It was adopted for SIS3302 boards in combination with a SIS1100 3100 PCI to VME or SIS3150 USB to VME interface later on The graphical user interface GUI is based on National Instruments CVI As CVI applications are based on underlying C code you can use the code as basis or examples for adaptations to your environment and application The required files are kept in three directories as shown below sis3302_gamma_system ug E Datei Bearbeiten Ansicht Favoriten Extras 7 P zuriick Q 27 Suchen 2 Ordner Hak Adresse C sis3302_gamma_system Wechseln zu Name Grobe Typ Geandert am communication header Dateiordner 10 12 2007 10 29 Dateiordner 10 12 2007 10 23 ts Dateiordner 10 12 2007 10 29 91 Header files The registers of the SIS3302 gamma firmware can be found in 5153302 v1201 h If you want to use the routines unchanged you may have to include header files for the SIS3820 clock distributor for the sis3150 card and for the SIS9300 ADC board An overview of all header files of the project can be seen in the screen dump below Datei Bearbeiten Ansicht Favoriten Extras 7
28. Clock In Clock Out Trigger In ADC sample logic armed Timestamp Clear ADC event sampling busy 777 1 Vee Triggerout The external clock must be a symmetric The width of Trigger In Timestamp Clear pulse must be greater or equal two sampling clock periods Page 83 of 97 SIS Documentation SIS3302 14xx SIS GmbH 1 Firmware Gamma VME 7 2 LED s The SIS3302 has 8 front panel LEDs to visualise part of the modules status The user and access LED are a good way to check first time communication addressing with the module Yelow 2002 Green board logic configured Sampling busy on Bank 1 Sampling busy on Bank 2 Green STP Lit if the lower Timestamp counter bits 27 to 0 are equal or of all four timestamp counters 100MHz gt lit every 2 6 sec Trigger lit if one or more channels are triggered The on duration of the access sampling start stop and trigger LEDs 15 stretched to guarantee visibility even under low rate conditions 7 3 Channel LED s The 8 card edge surface mounted LEDs LI 18 can be seen through the corresponding holes in the front panel They visualize the trigger status of the corresponding channel The on duration is stretched for better visibility of short pulses 7 4 PCBLEDs The 8 surface mounted red LEDs D141A to D141G on the top left corner of the component side of the SIS3302 are routed to the control FPGA their use
29. Length 5 Waveform DEV 5 5 XC3S 1000 UNIT 0 ILA Bus Signal X o fir trigger out pulse 0 1 fi extern adc trigger pulse 0 0 internal gate_length_out 1 0 start_pulse_for_Trigger_Energy_Gate 1 nternal Delay Internal Gate Length Legend fir trigger out pulse generated from the internal Fast Fir Filter internal Trigger with the programmed Trigger Pulse Length Internal Delay 4 clocks External Delay 8 clocks external Logic Cable external user logic Page 18 of 97 SIS Documentation 5153302 14xx SIS GmbH J 2 2 6 Next Neighbor Trigger Gate logic Next Neighbor Trigger logic illustration SIS3302 Gamma V 1406 Next Neighbor Trigger External Trigger ADC N 1 Enable NB Trigger ADC N 1 Event Extended Configuration Reg bit 15 ADC 8 NB Trigger signal Enable NB Trigger ADC N 1 Event Extended Configuration Reg bit 14 AND Internal Trigger ADC 7 Internal Trigger ADC 8 Enable NB Trigger ADC N 1 AND Event Extended Configuration Reg bit 7 ADC 7 NB Trigger signal Enable NB Trigger ADC N 1 Event Extended Configuration Reg bit 6 AND Internal Trigger ADC 6 Event Extended Configuration Register ADC1 ADC2 Internal Trigger ADC 3 Enable NB Trigger ADC N 1 AND Event Extended Configuration Reg bit 15 ADC 2 Trigger signal Enable NB Trigger ADC
30. MHz sample clock 100000 12 7 intern 50 MHz sample clock 50000 Pi break y JJ end switch ol uine Sis3302Cl6ckModecons Switch gl_uint_FirDecimationMode case 0 no decimation float_sampling_time_us break Case EUR float sampling time us 2000 0 sample clock break j Case float sampling time us 4000 0 sample clock break Gase 3 77 float sampling time us 8000 0 sample clock break end switch gl_uint_FirDecimationMode 1000 0 sample_clock float_decay_factor Tau factor 32768 0 float decay time us float sampling time us log 1 0 float decay factor Page 70 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME Example 100 MHz Decimation 4 Tau Factor 1 decay time us 1310 69999990 us Tau Factor 2 decay time us 655 33999980 us Tau Factor 3 decay time us 436 88666636 us Tau Factor 4 decay_time_us 327 65999959 us Tau Factor 5 decay time us 262 12399949 us Tau Factor 6 decay time us 218 43333272 us Tau Factor 7 decay time us 187 22571357 us Tau Factor 8 decay time us 163 81999919 us Tau Factor 9 decay time us 145 61555464 us Tau Factor 10 decay time us 131 05199898 us Tau Factor 11 decay time us 119 13636252 us Tau Factor 12 decay time us 109 20666545 us Tau Factor 13 decay time us 100 80461406 us Tau Factor 14 decay time us 93 60285572 us Tau Factor
31. an internal Energy Index counter and starts this Index counter The logic is busy until the Index counter reaches the value of the Energy Gate Length register busy with the Energy Gate 2 Compares the Index counter with the Energy Sample Start Index x registers If the result is equal the logic writes N Energy Sample Length register values into the Energy Buffer 3 The logic saves the Energy at the beginning of the Energy Gate 4 The logic saves the maximum Energy inside the Energy Gate Page 12 of 97 SIS Documentation 5153302 14xx Gmbh 4 Firmware Gamma VME 2 2 3 2 Block diagram of the MAWD unit Explanation e MAWD moving average window deconvolution Tau correction e MAW moving average window e MA moving average e Decimation decreasing the clock rate Peaking Time the length of the MA for moving average unit e Gap Time the differentiation time of the mowing window average unit plus the Peaking time Flat Moving Average Window ADC signal Moving Average 1 MAWD Peaking Time Decimation Subtract Deconvolution delayed ADC signal delay Moving Average 2 Gap Time Peaking Time ADC clock domain Decimated clock domain Tau Factor 2 2 3 3 Signal diagram of the MAWD unit ADC signal 1 4 yum 2A Gap Time dee Det ad e Hee Peaking Time gt MA2 MAW MA
32. d f aaa 87 8 5 JP120A JP120D CONTROL INPUT TERMINATION cscsccscocscccececsccecececscvcscacavaecesscecseveesavavaecesecscseves 88 8 6 SWIZONDSW2 VMBBASE ADDRESS rios cola aa si cute 88 9 SOGETWARE GE SPAR TED el 89 9 1 PADET ee LAE Mau eae eR RTE SO UE 89 9 2 CODE cats 90 10 APPEINDIX e coca 91 91 10 2 OPER ATING CONDEPIONS S 91 122 2 ae ado 91 TOD statie a la ai 9 10 3 CONNECTOR TYPES daia da a i ta a dt aaa ar la 92 10 4 P2ROW A C PIN ASSIGNMENTS eee e e eee aa a aaa a a aaa aa a 92 10 5 ROW D AND Z PIN ASSIGNMENTS ce e e eee e aa e ae a a a aaa 93 10 6 FIRMWARE ee eee a a a aaa a a aaa 94 106 EE 62 MOD AIT Pr 94 y ___ __ ____________ m 94 11
33. gt gt 20 amp Oxff subtract gl uint McaEnergy2HistogramParameter amp multiplier_factorl 1 0 if div 0 1 multiplier_factorl multiplier factor pow 2 div multiplier_factorl 0 0 for i 0 i lt 8 i d temp multi gt gt 8 i amp Oxl if temp 1 multiplier_factor2 1 0 pow 2 i multiplier_factorl multiplier_factorl T multiplixer Pactorz Multiplier factori multiplier factor 2 SetCtrlVal Panels RUN MCA MENUE RUN MCA RUN MCA FACTOR multiplier factorl return 0 Page 73 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 4 37 MCA Histogram Parameter register define SIS3302_MCA_HISTOGRAM_PARAM_ALL_ ADC 0 01000068 define SIS3302_MCA_HISTOGRAM_PARAM_ADC12 0 02000068 define SIS3302_MCA_HISTOGRAM_PARAM_ADC34 0 02800068 define SIS3302_MCA_HISTOGRAM_PARAM_AD56 0 03000068 define SIS3302_MCA_HISTOGRAM_PARAM_ADC78 0 03800068 ________0 7 Write Test Mode Write Test Mode 6 Nope None P Enable bit Enable bit MN Enable bit Enable bit Pileup Enable bit Pileup Enable bit None Histogam Size bit Histogam Size bit 0 Histogam Size bit 0 Histogam Size bit 0 The power up default value is 0 Histogam Size bit BE 305 1024 Pileup Enable bit 0 don t increment histogram in case of
34. or external LNE 2 internal 10 MHz or external LNE 3 internal 10 MHz or external LNE 4 Page 46 of 97 SIS Documentation 5153302 14xx Gmbh 4 Firmware Gamma VME 4 12 MCA Scan Control register define SIS3302_MCA_SCAN_CONTROL RU 77 8 Nons J 0 000000 6 None 0 5 Histogram Autoclear disable bit O ooo Scan Histogram Autoclear disable bit 0 Scan Mode Autoclear is enabled Multiscan Mode Autoclear is enabled for 1 Scan and disabled for the following Scans Scan Histogram Autoclear disable bit 1 Scan Mode Autoclear is disabled Multiscan Mode Autoclear is disabled Start Scan on Bank 2 bit start address of 1 histogram is first page Start Scan on Bank 2 bit 1 start address of 1 histogram 15 0 0040 0000 4 Mbyte offset Write to this register only if MCA Multiscan or Scan is not Busy Page 47 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME i 4 13 MCA Multiscan Nof Scans preset register define SIS3302_MCA_MULTISCAN_NOF_SCANS_PRESET 0x90 The number of scans in a MCA Multiscan operation can be preset limited with this 32 bit deep register The entry of 0 0 power up default results in disabling the preset limited function 4 14 MCA Multiscan Scan counter register define 5153302 MULTISCAN SCAN COUNTER 0 94 This 32 bit deep register holds the actual number of scans in
35. stoped by NOF_Histogram_Preset Register SIS Documentation 5153302 14xx Firmware Gamma 2 2 9 CVI plots 2 2 9 1 Sampling and Energy Filter Parameter screenshot Panel Define DSP T5 Loader File 4 3 Full Energy Trapezoidal 512 values min max 2 2 9 2 Raw signal screenshot Panel Plot Style Line Style Plot Background Color Grid Color Page 25 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME 2 2 9 3 Raw signal with Pileup screenshot RAW SIGNALS Panel Plot Style Line Style Flot Background Color Grid Color 39742 ae 39500 Ri J T Header ID Trigger Fileup FLAG IMFO LL Ie ADC 8 78 PS 0 wx 0 JT PE JT PS ol _ LLLLLLLLLLLIILLLEL MC4 Ta 37000 LL I ADC 3 0 12 0 EN Jm Je x i ADC 1 0 71 82 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 999 Lm Lo gt show Loren Y Zeon Zooming b bem Timestamp Upper Timestamp Lower X Posiion 0 X Reset Module 2 1 em Be NEN 3609BB92 Y Position 10 2 2 9 4 Energy Filter data without Tau correction MAW screenshot energy Values Panel Plot Style Line Style Plot Background Color Grid Color
36. 02 MCA ENERGY2HISTOGRAM PARAM ADC6 0x02000064 define 5153302 MCA ENERGY2HISTOGRAM PARAM 0x03800064 D31 28 D27 20 D19 0 N Energy Multiplier Enable bits Energy Subract Offset Energy 2 Divider Calculation of the Histogram Index Multiplied Energy bit 27 bnergy L bit 26 gt gt 2 Die 225 gt 29 bit 24 Energy gt gt 4 t pIE 23 cw 22 XIEnerqyee P pit 21L 3 20 Energy gt gt 8 Histogram_index Multiplied_Energy gt gt N 1 Subract Offset Note N 0 gt not allowed Example Signal 100mV gt 3000 counts with Peaktime 100 gt Energy Value 300 000 0 493 0 MCA ENERGY2HISTOGRAM PARAM Ox 9 A4 00100 Energy bit 27 Energy gt gt 1 Zoo Popit 24 Cinergy 249 0 927 0 124 Ox2EEBB OxX2EEBB gt gt 8 0x100 4 494 Histogram_index Calculation of the Energy to Histogram Index Factor Page 72 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME int MCA Energy to Histogram factor calculation void unsigned int 1 int temp unsigned int value div multi subtract double multiplier_factorl multiplier_factor2 Energy to Histogram calculation parameters div gl uint McaEnergy2HistogramParameter gt gt 28 amp Oxf gl uint McaEnergy2HistogramParameter
37. 02 TRIGGER THRESHOLD ADC7 0x038000A0 define 5153302 TRIGGER THRESHOLD ADCS8 0x038000A4 These read write registers hold the extended threshold values for the ADC channels i none Trapezoidal Extended threshold value default after Reset 0 0 Page 66 of 97 SIS Documentation 5153302 14xx Firmware Gamma 4 32 Energy Setup GP registers define define define define define 5153302 ENERGY SETUP GP ALL ADC 5153302 ENERGY SETUP ADCI2 5153302 ENERGY SETUP ADC34 5153302 ENERGY SETUP 56 5193302 ENERGY SETUP ADCTOS SIS GmbH A 0 01000040 0 02000040 0 02800040 0 03000040 0 03800040 This read write register holds the Decimation Peaking max 1023 and Gap max 255 Time values of the trapezoidal FIR Energy filter _ 17 Peaking time P bits 9 to 8 Peaking Time bit 9 Peaking Time bit 8 Gap Time bit 7 Gap time time between both sums Gap Time bit 0 Peaking Time bit 0 The power up default value reads 00000000 Decimation Mode bit setting table Decimation in clocks 0 1 decimation 11 2 3 9 9 10 j4cdoks 0 0 0 0 0 000 0 0 do 5 Page 67 of 97 SIS Documentation 5163302 14xx SIS GmbH Firmware Gamma VME 4 33 Energy Gate Length registers fdefine SIS3302_ENERGY_GATE_LENGTH_ALL_ ADC 0 01000044 define SIS3302_ENERGY_GATE_LENGTH_ADC1
38. 0x0 1xSize Page N 1 N 1 xSize Histogramming in Memory Page 23 of 97 SIS Documentation 5153302 14xx Firmware Gamma 2 2 8 3 MCA Multiscan Arm Scan Enable internal Multiscan BUSY Multiscan Start Reset 1 2 Key or external internal Scan Enable Scan Enable flowdiagram 1 Scan with Clear Pages Scan ist stoped by NOF_Histogram_Preset Register 2 2 8 4 MCA Multiscan Arm Scan Arm Key MCA Multiscan Arm Multiscan Disable Disable with SIS GmbH 4 VME Key MCA Multiscan Disable or with Number of Scans NofScansPresetRegister N Key MCA Multiscan Arm with Scan operation Enable Scan Enable flowdiagram 2 Scan without Clear Pages Scan is stoped by Multiscan Reset Start Scan Enable flowdiagram 3 Scan without Clear Pages Scan ist stoped by NOF_Histogram_Preset Register Multiscan Disable Disable with Key MCA Multiscan Disable or with Number of Scans NofScansPresetRegister N with Scan operation Enable internal Multiscan BUSY MD 3 Multiscan Start Reset Key or external internal Scan Enable Scan Arm flowdiagram 1 Scan with Clear Pages Scan ist stoped by NOF_Histogram_Preset Register Page 24 of 97 Scan Arm flowdiagram 2 Scan without Clear Pages Scan is stoped by Muliscan Reset Start Scan Arm flowdiagram 3 Scan without Clear Pages Scan ist
39. 15 decay time us 87 36133181 us Tau Factor 16 decay_time_us 81 89999837 us Tau Factor 17 decay_time_us 77 08117474 us Tau Factor 18 decay_time_us 72 79777595 us Tau Factor 19 decay_time_us 68 96526122 us Tau Factor 20 decay_time_us 65 51599796 us Tau Factor 21 decay_time_us 62 39523596 us Tau Factor 22 decay_time_us 59 55817958 us Tau Factor 23 decay_time_us 56 96782375 us Tau Factor 24 decay_time_us 54 59333089 us Tau Factor 25 decay_time_us 52 40879746 us Tau Factor 26 decay_time_us 50 39230505 us Tau Factor 27 decay_time_us 48 52518244 us Tau Factor 28 decay_time_us 46 79142572 us Tau Factor 29 decay_time_us 45 17723843 us Tau Factor 30 decay_time_us 43 67066361 us Tau Factor 31 decay_time_us 42 26128717 us Tau Factor 32 decay_time_us 40 93999674 us Tau Factor 33 decay_time_us 39 69878452 us Tau Factor 34 decay_time_us 38 53058477 us Tau Factor 35 decay_time_us 37 42913929 us Tau Factor 36 decay_time_us 36 38888522 us Tau Factor 37 decay_time_us 35 40486110 us Tau Factor 38 decay_time_us 34 47262771 us Tau Factor 39 decay_time_us 33 58820116 us Tau Factor 40 decay_time_us 32 74799593 us Tau Factor 41 decay_time_us 31 94877631 us Tau Factor 42 decay_time_us 31 18761477 us Tau Factor 43 decay_time_us 30 46185609 us Tau Factor 44 decay_time_us 29 76908643 us Tau Factor 45 decay_time_us 29 10710653 us Tau Factor 46 decay_tim
40. 2 0 02000044 define 5153302 ENERGY GATE LENGTH ADC34 0x02800044 define 5153302 ENERGY LENGTH ADC56 0x03000044 define 5153302 ENERGY GATE LENGTH ADC78 0x03800044 This 17 bit register bits 16 0 defines the length of the energy gate and defines test modes bits 29 28 of the Energy Data The Energy Gate starts with begin of sampling and stops after decimation factor clocks Function 0 Test Mode bits 1 0 Energy Gate Length Test Mode bit setting table meaning of ADC Energy Data 0 0 Energy MWD MA Trapez 0 l MW MA Trapez test mode 1 0 Trigger Trapez test mode reserved Test Mode Trigger Trapez The Trigger Trapez is delayed by 32 clocks and it is stored with the Energy Decimation factor 4 34 Energy Sample registers This register set ENERGY SAMPLE LENGTH ENERGY SAMPLE START INDEXI ENERGY SAMPLE START INDEX2 and ENERGY SAMPLE START INDEX3 controls the storage of the energy filter values While the Energy Gate 15 active the logic compares the value of the Energy Gate Index an internal counter which is cleared at the beginning of the event and incremented by each decimated clock with the values of the ENERGY SAMPLE START INDEX registers If the result of the compare is equal then the logic writes N values ENERGY SAMPLE LENGTH into the Energy Buffer The number of values is limited to 510 values in total Page 68 of 97 SIS Docum
41. 272 926b 926b 926f 926a 926f i 40 926c 9269 926d 9269 9265 926b 926b 9268 i 48 9266 926b 9266 9264 926a 9263 9268 9262 i 56 9263 9262 9262 9264 9264 9263 9260 9261 i 0 11 19 18 23 20 1f 25 29 1 8 28 34 34 45 4 52 4 1 16 4 44 44 44 46 47 1 24 47 227 153b 20ec 2 90 3842 4409 1 32 4fc8 5b8b 6752 731 9 9680 a24a 1 40 1 8 b9ec c5b9 d182 dd60 e929 4 6 100 6 1 48 10 98 11865 12428 12ff8 13bc9 14791 T5359 15fle 1 56 16 4 17665 18271 18e2b 199fa labbd 15180 lbd4e 1 64 1d4db 1 09 1 60 1f82a 203ed 20 21b64 1 72 22728 232ed 23ea0 24a5f 2561e 261 26d9d 21951 1 80 20515 290 5 29 2 852 25409 2bfc6 2cb82 2 740 1 88 2 2 2eeb6 2fa78 30631 311 31db0 32966 3351c i 96 340 3 34 92 35851 36408 36fc1 38733 392e5 i 104 39ea2 5 3b61le 3 1 9 3cd94 301952 509 Sieg 1 112 SECTS 40832 41 41 8 42566 43721 44248 44293 1 120 45a55 4660e 471bc 47 4891 49302 496ea 49752 i 128 49758 49768 4976e 49768 49761 49751 49742 4972 1 136 4971 49704 49700 496f0 496e3 496ce 496bd 496a8 1 144 49683 4966 49660 49647 4962 4961 49602 495ef 1 152 495d7 495c8 495b0 49599 4958f 49578 49567 4955f i 160 49554 49547 4953e 49524 49519 4950d 49338 48559 1 168 47ffd 4743c 4688b 45ccd 450fa 4452e 43951 42494 1 176 421bf 415eb 40a10 3fe3d 31260 98 3dacl oce i 184 LE 3b74e 3ab73 39fa3 393d4 387fc S
42. 3 0 02800084 define SIS3302_MCA_PILEUP_COUNTER_ADC4 0 02800094 define SIS3302_MCA_PILEUP_COUNTER_ADC5 0x03000084 define SIS3302_MCA_PILEUP_COUNTER_ADC6 0x03000094 define 153302 MCA PILEUP COUNTER ADC7 0x03800084 define 5153302 COUNTER ADCB8 0x03800094 This 32 bit counter is cleared with a Multiscan or Scan operation start command During the Multiscan or Scan operation is active a detected Pileup Pileup or Retrigger Pileup increments this counter Page 75 of 97 SIS Documentation SIS3302 14xx SIS GmbH A Firmware Gamma VME 4 40 MCA ENERGY_to_High counter register define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC1 0 02000088 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC2 0 02000098 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC3 0 02800088 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC4 0 02800098 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC5 0 03000088 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC6 0 03000098 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC7 0 03800088 define SIS3302_MCA_ENERGY2HIGH_COUNTER_ADC8 0 03800098 define SIS3302_MCA_ENERGY2LOW_COUNTER_ADC1 0 0200008 This 32 bit counter is cleared with a Multiscan or Scan operation start command During the Multiscan or Scan operation is active this counter will be incremented if the calculated Histogram Index is higher than the histogram size 4 41 MCA ENERGY_to_Low counter register define SIS3302_MCA_ENERGY2LOW_COUNTER_ADC1 0x0200008C define 5153302
43. 8 to 255 25 bit running sum 15 shifted to the right by 8 if P 256 to S11 25 bit running sum is shifted to the right by 9 See int calculateFirTriggerAdcCounts void in sis3302_configuraton c and Trigger Example Trapezoidal value calculation Trapezoidal value SUM2 SUM1 0 10000 Where X P SUMI shiftrightbyN gt Si x P sumG SUM2 shiftrightbyN 2 Sj x sumG The FIR Filter logic adds 10000 to the result of the subtraction of the two running sums This implies that the internal value of the trapezoid 15 on average 0 10000 A Trigger Output pulse is generated if the Trapezoidal value exceeds the trigger threshold value 4 30 2 Extended Threshold Mode 1 The FIR Filter logic adds 0x200 0000 to the result of the subtraction of the two running 25 bit sums This implies that the internal value of the trapezoid 15 on average 0 200 0000 Trapezoidal value SUM2 SUM1 0x200 0000 A Trigger Output pulse is generated if the 26 bit Trapezoidal value exceeds the trigger extended threshold value Page 63 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME 4 30 3 Trigger example Screen shot 1 below shows a triggered signal on ADC channel 1 and the resulting FIR The Peaking Time is set to 10 and sumG Time 15 set to 16 Flat Time 6 The trigger condition is set to GT the trapezoidal trigger threshold is set to 100 trigger threshold reg 0x 10000 100 what r
44. ADCS E 8 16 disable it GT Trigger Out enable 100 4 200 10 0 2 ADC 8 24 15 disable if GT Trigger Out enable a 100 4 200 4 10 84 0 4 2 8 4 16 disable Trigger enable 4 100 4 200 4 10 0 2 ADCS 54 8 10 disable Sif GT Trigger Out enable E 100 d 200 EE 10 4 0 2 a 8 24 16 disable ii GT Trigger Out enable 10 4 200 28 10 2 ADC3 4 8 4 16 disable if GT Trigger Out enable a 10 4 200 28 10 4 2 ADC2 8 16 disable Trigger enable p 100 d 200 10 0 2 ADC 10 4 16 9 disable it GT Trigger Out enable 3 10 4 150 4 10 2 Screen shot 1 Page 64 of 97 5153302 14xx Firmware Gamma SIS Documentation Peaking Time 10 SumG Time 16 Gap Time 6 bb435 400 o 2 66000 65800 EI 65700 A 65600 B5532 gt 1210 20 30 40 Screen shot 2 SIS GmbH Page 65 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 4 31 Trigger Extended Threshold registers define SIS3302_TRIGGER_THRESHOLD_ADC1 0x020000A0 define 5153302 TRIGGER THRESHOLD ADC2 0x020000A4 define 5153302 TRIGGER THRESHOLD ADC3 0x028000A0 define SIS3302_TRIGGER_THRESHOLD_ADC4 0x028000A4 define 5153302 TRIGGER THRESHOLD ADC5 0x030000A0 define SIS3302_TRIGGER_THRESHOLD_ADC6 0x030000A4 define 51533
45. DC8 ADC 8 NB Gate signal ADC 7 NB Gate signal ADC 2 NB Gate signal ADC 1 NB Gate signal Attention Next Neighbor Gate logic is not implemented on the SIS3302 4 channel version Page 20 of 97 SIS Documentation 5153302 14xx Firmware Gamma 2 2 Sample Logic with MCA Mode 0 SIS GmbH A The sample logic starts with a trigger signal Start Pulse for Trigger and Energy Gate and executes following steps 1 starts the Trigger and Energy Gate and stores the 48 bit timestamp writes the 16 bit programmable ADC Header and the stored 48 bit Timestamp into the Event Memory 3 writes a programmable number of ADC Raw Values into the Event Memory 4 writes at the end of the Energy Gate a programmable number of Slow FIR Values MAWD into the Event Memory 5 writes the maximum and minimum first value of Energy Gate MAWD value into the Event Memory 6 writes the Fast Filter Information register into the Event Memory 7 writes a Trailer into the Event Memory 31 16 15 0 Timestamp 47 32 Event Header 10 Timestamp 31 16 Timestamp 15 0 sample 2 sample 1 ADC raw data buffer programable length 0 to 65532 samples all sempe sample N sample N 1 Energy data buffer MAWD signed int programable length 0 to 510 Energy max value Energy value from first value of Energy Gate Pileup Flag Retrigger Flag and Trigger counter Trailer OXD
46. EADBEEF Page 21 of 97 SIS Documentation 5153302 14xx 2 2 1 Deadtime Firmware Gamma Event storage induces Deadtime Arm sampling on Bankx Internal Sample Gate Internal Trigger Trigger Gate Energy Gate Write to Event Memory Deadtime table Raw Data Sample Length lt _ Deadtime AL Timestamp ADC Raw Energy data Header data MAWD ah SIS GmbH A Timestamp Header Energy Sample Deadtime approximate Length 1 Page 22 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME 2 2 8 MCA Mode e 1 2 4 8K Histogram Bins histogram page size Page Clear Time table Page Clear Time approximate _ ius 0 02 2 2 8 1 MCA Scan Enable Scan Disable Stop with Key MCA Disable or with Key MCA Scan Enable Number of Histograms NofHistogramPresetRegister Internal Scan Enable LNE Key MCA LNE Pulse or external LNE Page 1 0 0 1xSize Page 2 0 0 2xSize Page N 1 0 0 N 1 xSize Histogramming in Memory I clear 2 2 8 2 MCA Scan Arm Scan Disable Stop with Kev MCA S A Key MCA Disable or with eee internal Scan Arm Internal Scan Enable LINE Key MCA LNE Pulse or external LNE Page 1
47. I CON 100 i 1 E 2 nn 22111 120 M i dnt m 9 eem JP101 O3 ae Sia wi millia a SWI p 5 Hi mi MER im d uon d li 36088800 SW2 2220 z WANN 03000000 SHEMA U LETETT gl 2 z IL g ala E mate 111 pi anc 0000000 20309800 KT UE 5 LILI 003300 Page 81 of 97 SIS Documentation 5153302 14xx 515 GmbH Firmware Gamma VME 7 Front panel The SIS3302 is a single width 4TE 6U VME module A sketch of the SIS3302 front panel single ended LEMOOO version without handles is shown below The IN OUT breakouts hold 4 LEMO connectors each 1 5153302 ADC bH WUW struck de 8 3 O Page 82 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME 7 1 Control In Outputs The control I O section features 8 LEMOOO connectors with NIM levels The assignment of the functions of the LEMO Inputs 1 3 and of the LEMO Outputs 1 3 depends on the programmed LEMO IN Mode and LEMO OUT Mode Example for LEMO IN Mode 0 and LEMO OUT Mode 0
48. N 1 Event Extended Configuration Reg bit 14 AND Internal Trigger ADC 1 Internal Trigger ADC 2 Enable NB Trigger ADC N 1 Event Extended Configuration Reg bit 7 ADC 1 Trigger signal Enable NB Trigger ADC N 1 Event Extended Configuration Reg bit 6 AND External Trigger ADC N 1 Event Extended Configuration Register ADC ADC8 Attention Next Neighbor Trigger logic is not implemented on the SIS3302 4 channel version Page 19 of 97 SIS Documentation 5153302 14xx Firmware Gamma Next Neighbor Gate logic illustration 5153302 V 1406 Next Neighbor Gate Logic External Trigger ADC N 1 Internal Trigger ADC 7 Internal Trigger ADC 8 Internal Trigger ADC 6 Internal Trigger ADC 3 Internal Trigger ADC 1 Internal Trigger ADC 2 External Trigger ADC N 1 Enable NB Trigger ADC N 1 ANG Event Configuration Reg bit 15 Enable NB Trigger ADC N 1 Event Configuration Reg bit 14 AND Enable NB Trigger ADC N 1 Event Configuration Reg bit 7 Enable NB Trigger ADC N 1 Event Configuration Reg bit 6 AND Event Configuration Register ADC1 ADC2 Enable NB Trigger ADC N 1 oe Event Configuration Reg bit 15 Enable NB Trigger ADC N 1 Event Configuration Reg bit 14 AND Enable NB Trigger ADC N 1 Event Configuration Reg bit 7 Enable NB Trigger ADC N 1 Event Configuration Reg bit 6 AND Event Configuration Register ADC7 A
49. R SETUP ADC8 0x03800038 These read write registers hold the lower Peaking and Gap Time values of the trapezoidal FIR filter Trigger Pulse Length value and Internal Gate Length value Flat Time SumG time Peaking Time pang Internal Trigger Pulse Length max 255 clocks SumG time time between both sums Note definition of SumG bit 8 can be found in 90 SumGbitl Trigger Extended Setup registers 8 SumG bit P Peaking time 6 Pbit6 D o P bit 0 definition of P bit 8 can be found in The power up default value reads 0 0 51 Sum of ADC input sample stream from x to x P P Peaking time number of values to sum SumG SumGap time distance in clock ticks of the two running sums Page 59 of 97 SIS Documentation 5163302 14xx SIS GmbH Firmware Gamma VME 4 29 Trigger Extended Setup registers define SIS3302_TRIGGER_EXTENTED_SETUP_ADC1 0 02000078 1 SIS3302_TRIGGER_EXTENTED_SETUP_ADC2 0 0200007 define SIS3302_TRIGGER_EXTENTED_SETUP_ADC3 0x02800078 define 5153302 TRIGGER EXTENTED SETUP ADC4 0x0280007C define 5153302 TRIGGER EXTENTED SETUP ADC5 0x03000078 define 5153302 TRIGGER EXTENTED SETUP 6 0x0300007C fdefine 5153302 TRIGGER EXTENTED SETUP ADC7 0x03800078 define 5153302 TRIGGER EXTENTED SETUP ADCS8 0x0380007C These read write registers hold the upper Peaking and Gap Time values of the trapezoid
50. SB usb hs Load the mcs file to the serial PROM shown as xcf16p 10 6 2 Upgrade over VME not tested with 5153302 firmware 12 02 yet Page 94 of 97 SIS Documentation 5153302 14xx SIS GmbH A Firmware Gamma VME 11 Index 92 gate Seat P ands d a 92 ses 52 Ox TAOX ce dal atu oala 29 Internal ue o 52 EDEN 82 geographical addressing 93 rur FER 82 SOLUTIO Started gt 89 UAI CT 28 Spem T 85 Cres 43 92 Address Map 29 US eann nena EARE 92 address SPACE oeste au i AA 28 Header 89 at CAD ACILY 91 HOES Wap 91 93 EA 49 7 srp taiat 91 E 94 81 input broadcast COG Craii d eee 83 88 i c IA SASI ARE 41 COMO 63 DE aa 40 83 88 to cit atent Car atu abea li 40 83 88 90
51. SIS Documentation 5153302 14xx 515 GmbH Firmware Gamma VME 5153302 14xx Firmware Gamma User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version sis3302 M 1408 1 V132 gamma doc as of 04 12 2009 Page 1 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME Revision Table 1 02 29 07 08 Design Version iod oe 05 E 03 09 Design Version 1205 add Next Neighbor Trigger feature add external Veto Gate add internal Trigger or Gate mode Acquisition control register add new bits 18 05 09 Design Version 1405 Add MCA Mode Fir Filter maximum Peaking time and Gap time values expanded from 16 x clock to 64 x clock 29 05 09 Change in documentation 10 07 09 Bug fix in broadcast setup 20 02 09 09 Design Version 1406 Fir Filter maximum Peaking time and Gap time values expanded from 64 x clock to 1023 x clock and add Decimation of 2 4 or 8 Energy Filter maximum Peaking time value expanded from 255 x clock to 1023 x clock maximum Raw Data sample length expanded from 1024 samples to 65532 samples maximum Pretrigger Delay expanded from 511 clocks to 1023 clocks maximum Trigger Gate length expanded from 1024 clocks to 65536 clocks maximum Energy Gate length expanded from 1024 clocks to 131072 clocks maximum Energy Sample Start Index X value
52. STERS Desa Deest iat al ul tei 52 4 21 EVENT EXTENDED CONFIGURATION REGISTERS 2000000 53 422 END ADDRESS THRESHOLD REGISTERS dt i 54 4 23 DELAY AND TRIGGER GATE LENGTH 5 6 0 0 55 4 24 RAW DATA BUFFER CONFIGURATION REGISTERS 56 4 23 NEXT SAMPLE ADDRESS REGISTER bad abate de 0d 57 4 26 ADCI 8 PREVIOUS BANK SAMPLE ADDRESS 8 57 ACTUAL SAMPLE REGISTERS alt ra uae d 58 29 TRIGGER SETUP REGISTER S dap ne dat eo bl a ol bt 0d 59 429 TRIGGER EXIENDED SETUP REGISTERS EA dea oala bu 60 TRIGGER THRESHOLD PEGISTERS vel Gne 62 4 30 1 Extended Threshold Mode te do ele aci Dac ala at le 63 4 30 2 Extended Threshold Mode I tp Rei eden oe a eine 63 4303 ai 64 4 3 TRIGGER EXTENDED THRESHOLD REGISTERS cccccccscceecescenccseceucescceeceucesceeeeeecesceeeseuceeceeesancesceeeees 66 4 32 ENERGY SETUP 65 eee u
53. Sampling and Energy Filter Parameter screenshot 1 10 0000000000000000000 E Ea aaa 25 2292 seen NOU 5 a la A 25 229 RAW stenal with PHeup Cree nshoL oaia ou bates ai aia a 26 2 2 9 4 Energy Filter data without Tau correction MAW 26 2 2 9 5 Energy Filter data with Tau correction MAWD screenshot 27 355 ADDRESSING E 28 3 1 ADDRESS ABS secs ons mU M a ata 29 4 REGISTER RESOURCE DESCRIP TION cass 32 4 1 STATUS REGIS FER dit suta __________________ Due D 32 42 MODULE ID AND FIRMWARE REVISION REGISTER 33 4 2 1 Malor FEV ON WIDE alt ua tes 33 45 INTERRUPT CONFIGURATION REGISTER oa az petu ta Einar orale a 34 4 3 1 IKO node cce oa ____________ 34 Z4 INTERRUPT CONTROL REGISTER otel af urat ba an e Bara ate Da alea vaca cu oa a Bea arate a 35 a JACOUISEHION CONTBOE RE GIG WER n lea a __________ 36 AO 3BBOADCASPESEDUPRBEGISTER 62 Li aa bu ana lies aia idea e aa 40 ADC MEMORY PAGE REGISTER
54. To get a better resolution use the Second internal 100 MHz instead of internal 100 MHz U212 must be assembled with a 100 MHz 3 3 V oscillator LEMO OUT Mode bit setting table Lemo Output Mode Lemo Output assignment with MCA Mode 0 Mode 0 output 3 gt ADC sample logic armed 1 0 bit0 0 output 2 gt ADCx event sampling busy output 1 gt Trigger output Mode 1 output 3 gt ADC sample logic armed bit 1 0 bit0 1 output 2 gt ADCx event sampling busy or ADC sample logic not armed Veto output 1 gt Trigger output Mode 2 output 3 gt ADC N 1 Neighbor Trigger Gate Out bitl 1 bit0 0 output 2 gt Trigger output output 1 gt ADC N 1 Neighbor Trigger Gate Out Mode 3 output 3 gt ADC N 1 Neighbor Trigger Gate Out bitl 1 bit0 1 output 2 gt ADC sampling busy or ADC sample logic not armed Veto output 1 gt ADC N 1 Neighbor Trigger Gate Out Page 37 of 97 SIS Documentation 5153302 14 SIS GmbH 4 Firmware Gamma VME Lemo Output Mode Lemo Output assignment with MCA Mode 1 Mode 0 output 3 gt ADC sample logic armed 1 0 bit0 0 output 2 gt ADCx event sampling busy output 1 gt Trigger output Mode 1 output 3 gt Multiscan first scan signal bit1 0 bitO 1 output 2 gt LNE output 1 gt Scan enable Mode 2 output 3 gt Scan enable bitl 1 bit0 0 output 2 gt LNE output 1 gt Trigger output Mode 3 output 3 gt reserved bitl 1 bitO 1 output 2 gt reser
55. WD Page 13 of 97 SIS Documentation 5153302 14xx SIS GmbH J Firmware Gamma VME 2 2 3 4 Block diagram of the moving average MA unit Mowing Average Accumulator Subtract MA input delay Peaking Time delayed input Peaking Time 2 2 3 5 Block diagram of the Deconvolution Tau correction unit Deconvolution Tau Factor Multiply gt Accumulator MAW MAWD Accumulator Page 14 of 97 SIS Documentation 5153302 14xx 515 GmbH 4 Firmware Gamma VME 2 2 4 Gamma Logic Parameter illustration ADC signal Peaking and Gap Time P1 Trigger Threshold 2 Trapezoidal ja Internal Trigger 4 Trigger Gate Length P3 gt Trigger Gate oe i 01112 T1 N 4 Trigger Gate index Stop Trigger Gate index Energy Gate E3 E4 M o 112 E1 E2 Energy Gate index Stop Energy Gate index Saved raw data example 1 Delayed ADC signal Energy Gate Length P7 gt Delayed Internal Trigger Pretrigger Delay P4 Saved Energy data example 2 MAW moving average window without Tau correction Saved Energy data example 3 Saved Energy data example 3 MAW moving average window
56. a tar art ar aa er ENE 67 4 33 ENERGY GATE LENGTH REGISTERS 0 66 6 68 4 34 JBNERGY DAMPEEREGISTER RENI RO ar ar o atu a e til 68 em 69 4 3422 Energy Sample Start Indext registers ice eA HE RAE NE VE AR Vd Eat 69 4 34 3 Energy Sample Start Index2 registers 4 esce er TREE coasa dada 69 4 34 4 Enerey Sample Start Index3 registers c eae ata ony YR ave 69 JENERG VL AUP ACTOR REGIS DES n aaa at 70 4 36 MCAENERGY_TO_HISTOGRAM CALCULATION PARAMETER 2 2222 72 457 NMCATHSTOGRAM PARAMETER REGISTER 25 25 aa 74 4 46 MCAIRICCEROSIARTCOUNIEE REGISTER 2 0 Deos ausa uu ima ata ei 75 4 39 A PIEBOP COUNTER REGISTER talpa 75 440 TO HIGH COUNTER 5 4 6 76 441 MCAENERGY_TO_LOW COUNTER REGISTER 0 0 000000000000004000000000 76 ka NIE MOR
57. al FIR filter the decimation value and Internal Trigger Delay value Internal Trigger Delay E Reserved III 6 Reserved II Pots SSCS The power up default value reads 0 0 Page 60 of 97 SIS Documentation 5153302 14xx Firmware Gamma Note The maximum SumG time 511 clocks The minimun SumG time 1 clocks Value will be set to 1 The maximum Peaking time 511 clocks The minimun Peaking time 1 clocks Value will be set to 1 Trigger Decimation Mode bit setting table 0 10 0 nodecimation __ 0 07 1 g2cdoks 0 11 0 4 0 1 2 1 10 0 Ji6doks 0 0 d 0 reserved 00 d 1 JO reserved 00 Only the Peaking and Gap Time dependent on the Trigger Decimation Mode SIS GmbH 4 Page 61 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME i 4 30 Trigger Threshold registers define SIS3302_TRIGGER_THRESHOLD_ADC1 0x02000034 define SIS3302_TRIGGER_THRESHOLD_ADC2 0x0200003C define 5153302 TRIGGER THRESHOLD ADC3 0x02800034 define SIS3302_TRIGGER_THRESHOLD_ADC4 0x0280003C define 5153302 TRIGGER THRESHOLD ADC5 0 03000034 define SIS3302_TRIGGER_THRESHOLD_ADC6 0x0300003C define 5153302 TRIGGER THRESHOLD ADC7 0x03800034 define 5153302 TRIGGER THRESHOLD ADCS8 0x0380003C These read write registers hold the threshold values for the ADC channels Function none Disable Trigger Tr
58. amples P P sample N sample N 1 Energy data buffer signed int programable length 010 510 Energy max value Energy value from first value of Energy Gate Pileup Flag Retrigger Flag and Trigger counter Trailer OXDEADBEEF Event Header see Event configuration registers Pileup Flag and Trigger Counter Bis 31 30 29 28 2724 231 0 function Pileup Retrigger ADC N 1 ADC N I Fast Trigger Flag Flag Neighbor Neighbor Trigger Flag Trigger Trigger Counter Flag Flag While the Trigger Gate is active the Trigger Counter is incremented with each delayed Trigger up to Oxf Pileup Flag is set if Fast Trigger Counter gt 1 Retrigger Flag is set if an earlier Fast Trigger was P G Decimation Clocks before the actual Fast Trigger In this case the Energy Filter contains also the Energy of the earlier Fast Trigger Page 77 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME Example Raw Data Sample Length 64 Energy Sample Length 280 Start Index 1 Start Index2 0 Start Index3 0 Energy Peaking Time 100 Gap 40 Decimation 0 ADC_ID 4000 upper Timestamp lower Timestamp 251045 1 0 869c 86al 86a2 86a3 869 869e 86 0 86 7 1 8 86a4 86a6 8869 8e75 91 1 9254 9247 925a 1 16 0209 9267 926a 9267 926b 9269 9270 926a i 24 926c 926a 926c 9267 926e 9276 926d 9260 i 32 926d 926c 9
59. before a key arm is issued Undefined behavior negative sign e g may result otherwise 4 18 2 Key address VME Disarm Sample logic 0x414 define 5153302 KEY DISARM 0 414 Weare only D32 A write with arbitrary data to this register key address will disarm the sampling logic 4 18 3 Key address VME Trigger 0x418 define 5153302 Trigger 0 418 IT Wee dni 2022 2557 A write with arbitrary data to this register key address will trigger the sampling logic if external trigger is enabled see Event configuration registers 4 18 4 Key address Timestamp Clear 0x41C define SIS3302_KEY_TIMESTAMP_CLEAR Ox41C write only 032 A write with arbitrary data to this register key address clears the 48 bit Timestamp counter Page 49 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME 4 18 5 Key address Disarm Sample Logic and Arm sampling on Bank 1 0x420 define 5153302 KEY DISARM AND ARM BANK1 0x420 write only Do2 Disarms sampling on current bank and arms bank 1 4 18 6 Key address Disarm Sample Logic and Arm sampling on Bank 2 0x424 define 5153302 KEY DISARM AND ARM BANK2 0x424 7 write only 032 Disarms sampling on current bank and arms bank 2 Used in dual bank acquisition as illustrated in the example below Example from sis3 150_gamma_running c if bankl_armed_flag 1 addr gl_uint_ModAddrRun 0 SIS3302 KEY DISARM AND ARM BANK2 bankl_armed_flag
60. c compares the value of the Trigger Gate Index an internal counter which is cleared at the beginning of the event and incremented by each clock with the value of the Raw Data Sample Start Index register If the result of the compare is equal then the logic writes N values Raw Data Sample Length into the Raw Data Buffer Both values are 16 bit deep The number of samples has to be quad sample aligned and the number of pre trigger samples has to be even The number of Raw Data Sample Length 16 limited to 65532 samples Note The register is implemented on the FPGA group level also Bit 15 of Raw Data Sample Length Bit 2 of Raw Data Sample Length quad sample aligned values only quad sample aligned values only Bit 15 of Raw Data Sample Start Index Bit of Raw Data Sample Start Index O even values only Example data addr module SIS3302_RAW_DATA_BUFFER_CONFIG_ALL_ADC if error sub A32D32 write addr data 0 gl uint RawPreSampleStart index amp Oxfffe gl uint RawSampleLength amp Oxfffc 515 ErrorHandling error addr sub vme A32D32 write Page 56 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 4 25 ADC1 8 Next Sample address register define SIS3302_ACTUAL_NEXT_SAMPLE_ADDRESS_ADC1 0 02000010 define SIS3302_ACTUAL_NEXT_SAMPLE_ADDRESS_ADC2 0x02000014 define 5153302 ACTUAL NEXT SAMPLE ADDRESS ADC3
61. controls the VME interrupt behaviour of the SIS3302 ADC Four interrupt sources are foreseen for the time being two of them are associated with an interrupt condition two condition are reserved for future use The interrupter type is DOS 4 3 1 IRQ mode In release on register access mode interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ source disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again D 12 Mode 0 LI VME IRQ Enable 0 IRQ disabled 1 2 0 VMElQlewlBt oo S LT Vector Bit 7 placed on D7 during VME IRQ ACK cycle p 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK Do i IRQ Vector Bit 4 placed on D4 during VMEIRQ ACK cyce 0 3 Vector Bit 3 placed on D3 during VME ACK cycle 2 Vector Bit 2 placed on D2 during VME IRQ ACK cycle 1 IRQ Vect
62. e_us 28 47390836 us Tau Factor 47 decay_time_us 27 86765479 us Tau Factor 48 decay_time_us 27 28666178 us Tau Factor 49 decay_time_us 26 72938277 us Tau Factor 50 decay_time_us 26 19439491 us Tau Factor 51 decay_time_us 25 68038696 us Tau Factor 52 decay_time_us 25 18614855 us Tau Factor 53 decay_time_us 24 71056064 us Tau Factor 54 decay_time_us 24 25258709 us Tau Factor 55 decay_time_us 23 81126713 us Tau Factor 56 decay_time_us 23 38570858 us Tau Factor 57 decay_time_us 22 97508192 us Tau Factor 58 decay_time_us 22 57861478 us Tau Factor 59 decay_time_us 22 19558721 us Tau Factor 60 decay_time_us 21 82532722 us Tau Factor 61 decay_time_us 21 46720690 us Tau Factor 62 decay_time_us 21 12063885 us Tau Factor 63 decay_time_us 20 78507295 us Page 71 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 4 36 MCA ENERGY_to_Histogram Calculation Parameter register define SIS3302_MCA_ENERGY2HISTOGRAM_PARAM_ADC1357 0 01000060 define 5153302 MCA ENERGY2HISTOGRAM PARAM ADC2468 0x01000064 define 5153302 ENERGY2HISTOGRAM PARAM ADCI 0x02000060 define 5153302 MCA ENERGY2HISTOGRAM PARAM ADC3 0x02800060 define 5153302 MCA ENERGY2HISTOGRAM PARAM ADC5 0x02000060 define 5153302 ENERGY2HISTOGRAM PARAM ADC7 0x03800060 define 5153302 MCA ENERGY2HISTOGRAM PARAM ADC2 0x02000064 define 5153302 MCA ENERGY2HISTOGRAM PARAM 4 0x02800064 define 51533
63. egister bio Example dual 1 2 memory buffer acquisition scheme see sis3 150_gamma_running c data 0x0 Bank2 is armed and Bankl page 0 has to be readout if bankl_armed_flag 1 Bankl is armed and Bank2 page 4 has to be readout data 0 4 addr gl uint ModAddrRun module index SIS3302_ADC_MEMORY_PAGE REGISTER if error sub_vme_A32D32_write addr data 0 S1sVME ErrorHandling error gl uint ModAddrRun module index sub write return cp Page 42 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 48 DAC Control Registers define 5153302 DAC CONTROL STATUS 0x50 vead write D32 This set of registers is used to program the 16 bit offset DACs for the 8 ADC channels Refer to the documentation of the AD5570 DAC chip for details also and have a look to the configuration example in 5163302 adc testl c CVI directory Example routine int 5153302 write dac unsigned int module addr unsigned int offset value array 4 8 1 DAC Control Status register read write idefine 5193302 DAC CONTROL STATUS 0x50 read write D32 Write Function Read Function 16 None DAC Read Write Clear Cycle BUSY 14 7 _____________ 6 selection Bit 2 status of DAC selection 2 3 4424 2 mme 3 0044509 0 Command Bit0 Command Bit 0 Status _ DAC Command Bit _0 0 JjNofuction ___
64. entation amp s od define define define define define SIS3302 14xx Firmware Gamma Energy Sample Length registers 5153302 ENERGY SAMPLE LENGTH ALL ADC 5193302 ENERGY SAMPLE LENGTH 0 12 5153302 ENERGY SAMPLE LENGTH ADC34 5153302 ENERGY SAMPLE LENGTH ADC56 5153302 ENERGY SAMPLE LENGIH ADC78 SIS GmbH A VME 0x01000048 0x02000048 0x02800048 0x03000048 0x03800048 Energy Sample Length valid values 0 2 4 508 510 Ed 1 34 70 Energy Sample Start Index1 registers define 5153302 ENERGY SAMPLE START INDEX1 ALL ADC 0x0100004C define 5153302 ENERGY SAMPLE START INDEX1 ADC12 0x0200004C define 5153302 ENERGY SAMPLE START INDEX1 ADC34 0x0280004C define 5153302 ENERGY SAMPLE START ADC56 0x0300004C define 5153302 ENERGY SAMPLE START INDEXI1 ADC78 0x0380004C 31 16 Function 0 Energy Sample Start Index1 Energy Sample Start Index 0 disable Start 4 34 3 Energy Sample Start Index2 registers define 5153302 ENERGY SAMPLE START 2 ALL 002000050 define 5153302 ENERGY SAMPLE START INDEX2 ADC12 0x02000050 define 5153302 ENERGY SAMPLE START INDEX2 ADC34 0x02800050 define 5153302 ENERGY SAMPLE START INDEX2 ADC56 0x03000050 define 5153302 ENERGY SAMPLE START INDEX2 ADC78 00530000909 31 16 Function 0 Energy Sample Start Index2 Energy Sample Start Index2 0 disable Start 4 34 4 Energy Sample Start Index3 registers define 5153302 ENERGY SAMPLE START
65. er and Energy Gate Page 17 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME Example Internal Trigger External Gate Lemo Input Mode and Lemo Output Mode 0 In 1 connected with Out 1 and Enable front panel In 1 1 ADCx internal trigger enable 1 and ADCx external gate enable 1 Internal Trigger Pulse Length 30 Internal Trigger Delay Internal Gate Length 20 lt Internal Trigger Pulse Length gt External Delay gt Waveform DEV 5 MyDevice 351000 UNIT 0 ILA Bus Signal 22 212 T 3 8 a za fir trigger out pulse 1 1 extern adc trigger pulse 0 0 gare or 1 1 intern adc trigger pulse delayed 0 0 start pulse for Trigger Energy 0 0 Delay 4 nternal Trigger Delay Example 2 External Trigger Internal Gate Lemo Input Mode 0 Lemo Output Mode 0 In connected with Out and Enable front panel In 3 1 or Enable ored Internal Trigger to External Trigger In 1 Feedback ADCx external trigger enable 1 and ADCx internal gate enable 1 Internal Trigger Pulse Length 6 Internal Trigger Delay Internal Gate Length 20 External Delay Internal Trigger Pulse
66. esults in a decimal threshold of 160 ADC counts Trigger Threshold 100 gt 100 16 10 160 adc counts corresponds to approx 5mV 16 because data are shifted right by 4 10 because P 10 sum over 10 counts ADC Raw data 36481 34936 1545 corresponds to 50mV 1 5153302 Gamma 02 09 2009 Firmware Version 1406 or 1446 Panel View System Configuration Run Control Offline Diagnostic RUN CONTROL Energy Filter Values Panel Fle Windows Test Trigger Panel Plot Style Line Style Plot Background Color Grid Color Stop Condition al Stop after Events 3 66495 a eem 521 Ll RaW SIGNALS 66300 Panel Plot Style Line Style Plot Background Color Grid Color 66200 NA _ __ _ LIgN EM an E j sed E ae 35400 65532 1 1 1 T 1 1 1 1 1 MCN EEE J 35200 lt 34936 ADC1 4000 J 1 0 15 20 25 30 3 40 4 50 5 60 63 dibus Locati i ocation i 222 Zoomi i Vidi Timestamp Upper Timestamp Lower d Poston 10 9 326FD368 a ogule d A Y Posiion 000 Filter Parameter Trigger Parameter Peaking Time Gap Sum Diff P G Decimation Condition Threshold inADC counts Trigger Out Pulse Length Internal Trigger Delay Internal Gate Length
67. ezoidal Trigger Filter Fast FIR Filter A trapezoidal FIR filter is implemented for each ADC Channel to generate a trigger signal This Trigger Signal can be used to trigger the sample logic immediately or it can be routed to SIS3302 Lemo Output This Trigger Signal will be also used to store the Fast Filter trigger information Features for each ADC channel Programmable decimation 1 2 4 8 16 Clocks Programmable Peaking Time max 511 Clocks Programmable SumGap Time max 511 Clocks Programmable Trigger pulse out length max 255 Clocks Programmable Trigger Threshold Programmable Trigger Extended Threshold finer granularity Programmable Trigger Mode GT Disable Programmable Trigger OUT Enable Disable see Trigger Setup ADCx registers Trigger Extended Setup ADCx registers Trigger Threshold ADCx registers and Trigger Extended Threshold ADCx registers Page 10 of 97 16 SIS Documentation SIS3302 14xx Firmware Gamma 2 2 2 1 Block diagram of the Trigger MAW unit SIS GmbH 4 VME Explanation e MAW moving average window e MA moving average e Decimation decreasing the clock rate Peaking Time the length of the MA for moving average unit SumGap Time the differentiation time of the mowing window average unit Moving Average Window MAW Shift 4bit right ERE sign sign ADC signal SC Imanen Moving Average MAW Logic MAW Integration
68. g I in ACQUISITION in older header files The acquisition control register 15 in charge of most of the settings related to the actual configuration of the digitization process Like the control register it is implemented 1 a J K fashion 31 Clear reserved 156 __ 0 00 30 Clear Clock Source bit 0 y O 29 Clock Source bit 28__ Clear Clock Source 27 Clear reserved 116 26 Disable front panel LEMO n1 JSTO O 25 Disable front panel LEMO n2 STO o 24 Disable front panel LEMO n3 23__ Clear reserved 70 22 Disableored Internal Trigger to External Trigger 0 __ o O S y 9 Enable front panel LEMO In2 Status front panel LEMO In 2 Enable bit ______ 8 Enable front panel LEMO In 3 Status front panel LEMO In 3 Enable bit ______ Enable ored Internal Trigger to External Trigger In Status ored Internal Trigger to External Trigger In Feedback Feedback 0 SetLEMOIN Mode bit0 Mode bitO 0 The power up default value reads 0x0 Page 36 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME i Clock source bit setting table Clock Source Clock Source Clock Source Clock Source Bit2 Bitl oO O I internal 50 MHz Of internal 25 MHz 9211 SY internal Me SS J clock EMO front panel min Note The internal 100 MHz is generated with a DLL in the FPGA from the internal 50 MHz
69. ig all ADC 56 output trigger extended 60 Dank NENNT n UNDC DONNE 93 UTE DOT e cs cutu al 59 N ID NR NEI NI RE ut 63 threshold atol t 62 66 E 63 gt HMM DAN IS 49 85 iri alei dania n 83 34 49 59 60 67 N 0 SS 34 udata ata 93 Sample 21 RARI as le NI NR nara 93 Second internal 00 37 pin 1 6 92 single event acquisition 2222 22 80 CST PINT S set ate na dt baie te bac bat a 92 Ale title a tali tuens 89 Pace Clear Time table 4er eerte 23 eer eT t asa a cul sts 89 Page 96 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 153150_3302_ 32 trigger Din 32 CHS ADI OG 62 test 89 SAIS UP due 22 ST59200 o och 89 inte TaN E 32
70. igger Mode Extended Trapezoidal Threshold threshold value Mode default after Reset 0 0 The value of the Sum trapezoidal value depends on the peaking time P Therefore the selection of the value of the Trapezoidal threshold depends on P also The running sum is build with full accuracy Trigger Extended Mode is cleared shifted 16 bit running sum 0000 is compared with the threshold value of the Trigger Threshold register Trigger Extended Mode is set the full 25 bit running sum 0x200 0000 is compared with the value of the Trigger Extended Threshold register to generate the Trigger e GT isset the Trigger Out Pulse will be issued if the actual trapezoidal value goes above the programmable trapezoidal threshold value Note 1 The trigger is disabled if GT is cleared Note 2 use ADCx input invert bit for negative signals see Event configuration registers Page 62 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME i 4 30 1 Extended Threshold Mode 0 The running sum is build with full accuracy before the result 15 shifted to a 16 bit wide sum value SUM1 SUM2 is SUMI delayed by clocks ifP 1 to 15 25 bit running sum 15 shifted to the right by 4 if P 16 to 31 25 bit running sum is shifted to the right by 5 if P 32 to 63 25 bit running sum is shifted to the right by 6 if P 64 to 127 25 bit running sum is shifted to the right by 7 if P 12
71. it if set then triggers are generated with 50KHz with ADC clock 100 This feature is useful for ADC value histogramming in MCA mode Page 53 of 97 SIS Documentation 5163302 14xx SIS GmbH Firmware Gamma VME 4 22 End Address Threshold registers define SIS3302_END_ADDRESS_THRESHOLD_ALL ADC 0 01000004 define SIS3302_END_ADDRESS_THRESHOLD_ADC12 0 02000004 define SIS3302_END_ADDRESS_THRESHOLD_ADC34 0 02800004 1 SIS3302_END_ADDRESS_THRESHOLD_ADC56 0 03000004 define SIS3302_END_ADDRESS_THRESHOLD_ADC78 0 03800004 These registers define the End Address Threshold values for the ADC channel groups The value of the Actual Next Sample address counter will be compared with value of the End Address Threshold register The value is given in samples 1 number of 16 bit words Er End Address Threshold Bit 23 End Address Threshold Bit 2 junsed readas0 The power up default value is 0 Page 54 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 4 23 Pretrigger Delay and Trigger Gate Length registers define SIS3302 PRETRIGGER DELAY TRIGGERGATE LENGTH ALL ADC 0x01000008 define 5153302 PRETRIGGER DELAY TRIGGERGATE LENGTH ADC12 0x02000008 define SIS3302 PRETRIGGER DELAY TRIGGERGATE LENGTH ADC34 0x02800008 define SIS3302 PRETRIGGER DELAY TRIGGERGATE LENGTH ADC56 0x03000008 define 5153302 PRETRIGGER DELAY TRIGGERGATE LENGTH ADC78 0x03800008 This
72. lation Parameter ADC2 MCA Histogram Parameters ADC1 ADC2 4 4 4 4 4 4 tn pe Fe SIS Documentation SIS3302 14xx SIS GmbH Firmware Gamma VME 0 02000070 2000078 Ox0Z 000 07C o 1 0x020000A0 0x020000A4 Event Extended configuration ADC1 ADC2 Trigger Extended Setup ADC1 Trigger Extended Setup ADC2 MCA Trigger Start Counter ADC1 MCA Pileup Counter ADCI NES gt MCA Energy to high counter ADCI 4 R MCA Energy to low counter _ __ _______ 4 R MCA Trigger Start Counter ADC2 4 R Counter ADC 4 R MCA Energy to high counter ADC2 NE M NN MCA Energy to low counter ADC2 R W Trigger Extended Threshold ADC1 Trigger Extended Threshold ADC2 Event information ADC group 2 0x02800000 4 RW Event configuration ADC3 And so on as for ADC group 1 Event information ADC group 3 0x03000000 4 RAW Event configuration ADCO 5 And so on as for ADC group 1 Event information ADC group 4 0x03500000 4 RW Event configuration ADC7 ADCS And so on as for ADC group 1 ADC memory pages 0x04000000 8MBye X ADCImemoypage 0x04800000 8MBye X ADC2memoypag 0x05000000 8MBye X ADC3memoypae
73. may depend on the firmware design Page 84 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME 8 Jumpers Configuration 8 1 100 JTAG The 5153302 on board logic can load its firmware from a serial PROMs via the JTAG port on connector 100 or over VME A list of firmware designs can be found under http www struck de sis3302firm htm Hardware like the XILINX HW JTAG PC in connection with the appropriate software will be required for in field JTAG firmware upgrades The JTAG chain configuration is selected with jumper JP101 jumper JP102 is used to chose VME or CON100 as JTAG source The JTAG connector is a 9 pin single row 1 10 inch header the pin assignment on the connector can be found in the table below fi 2 GND ______ 3 n not connected cut to avoid polarity mismatch ___ 5 6 notconnected 6 7 testata in _ 9 __ 5 testmodus 8 2 JP80 VME addressing mode reset behaviour This 8 position jumper array is used to select the addressing mode and the reset behaviour of the SIS3302 T open CE S 5 watchdog to VMESYSRESETOUT open JP80 8 SYSRESET to board reset __ closed _ The enable watchdog jumper has to be removed during initial JTAG firmware load
74. mma VME i 10 Appendix 10 1 Power consumption The SIS3302 uses standard VME voltages only 10 2 Operating conditions 10 2 1 Cooling Although the SIS3302 is mainly 2 5 and 3 3 V design substantial power 15 consumed by the Analog to Digital converter chips and linear regulators however Hence forced air flow is required for the operation of the board An air capacity in excess of 160 m p is required Unoccupied adjacent slots of the VME crate have to be equipped with filler modules to ensure proper air flow The board may be operated in a non condensing environment at an ambient temperature between 10 and 25 Celsius A power up warm up time of some 10 minutes 15 recommended to ensure equilibrium on board temperature conditions 10 2 2 Hot swap live insertion Please note that the VME standard does not support hot swap by default The SIS3302 is configured for hot swap in conjunction with a VME64x backplane In non VME64x backplane environments the crate has to be powered down for module insertion and removal Page 91 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME 10 3 Connector types The VME connectors and the different types of front panel connectors used on the SIS3302 are SMA option 3302 differential input version 10 4 P2 row A C pin assignments The P2 connector of the 5153302 has several connections on rows and for the 1002 compatible use at the DESY 1 FNC subdetector
75. mma_running c as routines RunPC_SingleEventAquisition RunPC SIS3302Gamma MultiEvent DoubleBuffer Aquisition 5 1 Single event acquisition Events are read out one by one in single event acquisition This mode is most straightforward to implement but not suited for throughput 5 2 Multi Event Double Buffer acquisition Dual bank acquisition with two memory sections of 8 MBytes each is implemented as illustrated below Typically events are acquired into one buffer until the end address threshold is reached At this point in time acquisition is passed to the alternate bank buffer with the key disarm and arm bank N command and data are readout from the inactive bank The key disarm and arm bank N registers position the memory pointer to the beginning of the corresponding buffer Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Buffer 1 unused Buffer 2 unused KEY disarm and KEY disarm and arm bank 1 arm bank 2 Page 80 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 6 Board layout A printout of the silk screen of the component side of the PCB is shown below piu OL41F L REDE Lal Lg Lg Lg Led Lg Lg bq Lad ted tad uml Bons i l imn 102 LI CADIC 1100 us aa TT 1 120 ram ape ei JP120B Fer in Hilt JP120C ETNII MINTI
76. mory Logic 0 00000410 4 Scan LNE Pulse 0x00000414 4 KAW Scan operation Arm start with next LNE 0x00000418 4 MCA Scan Enable start immediately 0x0000041c 4 KAW Scan Disable 0x00000420 4 KeyMCA Multiscan Start Reset pulse 0x00000424 4 KAW MCA Multiscan Arm with Scan operation Arm start scan with next LNE 0x00000428 4 MCA Multiscan Arm with Scan operation Enable 0x0000042C 4 Multiscan disable Page 29 of 97 SIS Documentation SIS3302 14xx SIS GmbH A Firmware Gamma VME 4 __ 22277 A Actual Sample address ADC1 Actual Next Sample address ADC2 Previous Bank Sample address ADC1 Previous Bank Sample address ADC2 Actual Sample Value ADCI ADC2 internal Test 0x02000020 0x02000028 DDR2 Memory Logic Verification ADCI ADC2 0x02000030 E p 1 4 E Page 30 of 97 Trigger Setup ADCI Trigger Threshold ADCI Trigger Setup ADC2 Trigger Threshold ADC2 Energy Setup GP ADC1 ADC2 Energy Gate Length ADC1 ADC2 Energy Sample Length ADC1 ADC2 Energy Sample Start Index ADC1 ADC2 Energy Sample Start Index2 ADC1 ADC2 Energy Sample Start Index3 ADCI ADC2 Energy Tau Factor ADCI Energy Tau Factor ADC2 W MCA Energy to Histogram Calculation Parameter ADCI W MCA Energy to Histogram Calcu
77. mple Start Index registers Energy Sample Start Index2 see Energy Sample Start Index2 registers Energy Sample Start Index3 see Energy Sample Start Index3 registers Energy Tau correction Factor see Tau Factor registers Energy Filter Peaking Time see Energy Setup GP registers Energy Filter GapTime see Energy Setup GP registers SIS Documentation 2 2 5 Trigger Gate logic Trigger Gate logic illustration 5153302 14xx Firmware Gamma 153302 V 1406 Trigger Gate Logic SIS GmbH 4 VME ADCx internal trigger enable Event conf Reg bit 2 10 ADC x NB Trigger signal rising edge to programmable Trigger Pulse Delay rising edge to programmable Trigger Pulse Delay External Gate AND ADCx external gate enable Event conf Reg bit 5 13 Internal Trigger Gate AND ADCx internal gate enable rising edge to programmable Gate Length Event conf Reg bit 4 12 Gate 1 if internal gate enable and external gate enable 0 and NB Gate signal NB gate 1 enable 0 rising amp dge to programmable Gate Leno s te ADC N 0 _gate_ _N 1_enable Trigger Setup register bits 29 24 max 63 clocks External Trigger AND cT T ADCx external trigger enable nevi edge Event conf Reg bit 3 11 Internal Trigger Trigger Pulse AND Trigger Extended Setup register bits 28 24 max 31 clocks Gate Triager Pulse Start Pulse for Trigg
78. n units that have intact firmware and the JTAG connector CON100 The VME upgrade option is not tested for the current 01 02 firmware release yet 10 6 1 Upgrade over CON100 The firmware can be upgraded with the Xilinx Impact software which is part of the Webpack that can be downloaded from the Xilinx web page for free A version of the Webpack software which may not be up to date and not compatible with your JTAG hardware can be found in the xilinx_webpack directory of the Struck Innovative Systeme CDROM also A Xilinx JTAG parallel cable or USB Xilinx part number HW USB cable can be used to roll in the firmware Configure the SIS3302 for short JTAG chain refer to section 8 3 JP101 and set the unit to JTAG over CON100 refer to section 8 4 JP102 JTAG source With your hard and software properly set up you should see a screen as illustrated below after executing the initialize chain command Untitled Configuration Mode iMPACT EE aa gx Boundary Scan Slave Serial SelectMAP Desktop Configuration Assign New Configuration File Suchen in v_031005_v0102 EJ ro n_file ncs rom File 0102 Dateiname prom file 01 02 Dateityp MCS Files mcs Abbrechen 1 Manufacturer s ID xc INFO3MPACTA777 Reading C fXilinzdscfp dataxcfl 6p 501 1 Added DEEE ETTO TIT Configuration Mode Boundary Scan Platform Cable U
79. ng mode which is selected by jumper array JP80 and SW1 and SW2 in non geographical mode The table below summarises the possible base address settings DN GEO 27 __ X SWI SW220 7 7 SWI SW2 8 F are gt X X Not implemented in this design o dx Not implemented in this design Shorthand SWI SW2 Setting of rotary switch SW1 or SW2 respective Notes This concept allows the use of the 5153302 in standard VME as well as in VME64x environments i e the user does not need to use VME64x backplane e The factory default setting 15 EN_A32 closed SW1 3 SW2 0 1 the module will react to A32 addressing under address 0 30000000 With more than one unit shipped in one batch a set of addresses like 0 10000000 0x20000000 0x30000000 may be used also Page 28 of 97 SIS Documentation SIS3302 14xx SIS GmbH A Firmware Gamma VME 3 1 Address The 0x120x firmware specific 5153302 resources and their locations are listed with function in the table below The header file sis3302_v1405 h or equivalent provides the define statements Offset Size in BLT Access Function Bytes 0x00000000 4 W R__ Control Status Register J Kregister __ 0 00000044 4 Module Id and Firmware Revision register 0x00000008 4 RW Intemuptconfipurationregister 0x0000000C 4 RW ntemuptcontrolregiter
80. on Xs Zooming Fitting A Zoomin X Position 0 n ing Y Position 0 Note The actual sample value registers can be used to monitor the influence of the DAC settings on the ADC values Page 45 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 49 MCA Scan Nof Histograms preset register define SIS3302_MCA_SCAN_NOF_HISTOGRAMS_PRESET 0x80 The number of histograms in a MCA Scan operation can be preset limited with this 32 bit deep register The entry of 0 0 power up default results in disabling the preset limited function Histogram filing wraps at the 64 MByte Page Boundary while the Histogram counter continues incrementing 4 10 MCA Scan Histogram counter register define 5153302 MCA SCAN HISTOGRAM COUNTER 0x84 This 32 bit deep register holds the actual number of histograms in MCA Scan operation Histogram numbering starts with 0 4 11 MCA Scan LNE Setup and Prescaler Factor register define SIS3302_MCA_SCAN_SETUP_PRESCALE_FACTOR 0x88 D31 29 D27 0 LNE source bit LNE prescale factor LNE source bit O external next pulse see Input Mode 1 J internal 10 MHz The LNE prescale factor register allows you to prescale the LNE pulse external next pulse or internal 10M Hz The prescale factor is a 28 bit value in MCA Scan operation LNE prescale factor LNE pulse O 10 MHz or external internal 10 MHz
81. or Bit 1 placed on DI during VME IRQ ACK eyele 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle The power up default value reads 0x 00000000 Page 34 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 4 44 Interrupt control register define 5153302 CONTROL OxC read write D32 This register controls the VME interrupt behaviour of the 5153302 ADC Four interrupt sources are foreseen for the time being two of them are associated with an interrupt condition two condition are reserved for future use 131 UpdateIRQPulse _______ Status source 7 reserved 0 30 Unused Status IRQ source 6 reserved 0 29 Unued Status source 5 reserved 28 Unued Status source 4 reserved 2 0 27 Unused ______ Status IRQ source 3 reserved 0 26 Unued StausIRQsource2 rserved Status IRQ source 1 End Address Threshold Flag level sensitive 0 24 Unued Status IRQ source 0 End Address Threshold Flag edge sensitive 0 23 __ Disable Clear source 7 flag source 4 0 22_ Disable Clear IRQ source6 0 21 Disable Clear sourceS Status flag source5 0 20 _ Disable Clear IRQ source 4 Status flag source 4 19 Disable Cler source 3 Statusflagsouce3 18 Disable Clear IRQ source 2 _____ flagsouree 20 17 Disable Clear source Status flagsou
82. pileup Pileup Enable bit 1 increment histogram in case of pileup Memory Write Test Mode 1 Test Write to the Memory with BLT32 is possible start must on 8 byte boundary address and the length must be Nx byte MCA ADCx histogramming Enable bit If this bit 1 set then the ADC value will be histogramed in MCA mode To map the full 16 bit ADC range to the histogram page you will want to use the value listed in the table below 0 58000000 4K 048000000 038000000 Page 74 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 4 38 MCA Trigger Start counter register define SIS3302_MCA_TRIGGER_START_COUNTER_ADC1 0 02000080 define SIS3302_MCA_TRIGGER_START_COUNTER_ADC2 0 02000090 define SIS3302_MCA_TRIGGER_START_COUNTER_ADC3 0 02800080 define SIS3302_MCA_TRIGGER_START_COUNTER_ADC4 0 02800090 define SIS3302_MCA_TRIGGER_START_COUNTER_ADC5 0 03000080 define SIS3302_MCA_TRIGGER_START_COUNTER_ADC6 0 03000090 define SIS3302_MCA_TRIGGER_START_COUNTER_ADC7 0x03800080 define 5153302 MCA TRIGGER START COUNTER ADCS8 0x03800090 This 32 bit counter is cleared with a Multiscan or Scan operation start command During the Multiscan or Scan operation is active each Trigger Start Start of the Energy Window increments this counter 4 39 MCA Pileup counter register define SIS3302_MCA_PILEUP_COUNTER_ADC1 0 02000084 define SIS3302_MCA_PILEUP_COUNTER_ADC2 0 02000094 define SIS3302_MCA_PILEUP_COUNTER_ADC
83. r reserved 22 Clear reserved 6069 21 JGlarrsevedS 0 20 Clear reserved 4 69 O 2 2 19 3 0 18 Clearreserved2 0 17 Clear reserved 16 O 16 JjSwichoffusrLED 0 00 2 9 Setreserved9 sd Statusreserved 9 8 jSetrserved8 7 Statusreserved 8 0 02 6 jSetrseved7 __ Statusreserved 6 Status reserved O Switch on user LED Status User LED I LED 0 LED off denotes power up default setting Page 32 of 97 SIS Documentation 5153302 14 SIS GmbH Firmware Gamma VME 4 2 Module Id and Firmware Revision register define SIS3302 MODID 0x4 ead som sz Ww This register reflects the module identification of the 5153302 and its minor and major firmware revision levels The major revision level will be used to distinguish between substantial design differences and experiment specific designs while the minor revision level will be used to mark user specific adaptations 3 2 9 Major Revision Bit 0 8 Major Revision 6 Minor Revision Bit6 0 Minor Revision BitO 4 2 1 Major revision numbers Find below a table with major revision numbers used to date Application user Gamma add MCA Mode Page 33 of 97 SIS Documentation 5153302 14xx Gmbh 1 Firmware Gamma VME 4 3 Interrupt configuration register define 5153302 CONFIG 0 8 read write D32 This read write register
84. read write D32 This register is implemented for each channel group The 5153302 EVENT CONFIG ALI ADC register can be used to write the same setting to the registers of all channel groups simultaneously oue o RE 2 21 ___ 12 11 ADC 2 external trigger enable 10 ADC 2 internal trigger enable 12 HN 10 9 reserved 8 ADC 2inputinvert bit 6 ADC 1 ADC N 1 Next Neighbor gate enable O 0 ADC 1 input invert bit ADCx input invert bit 0 use for positive signals ADCx input invert bit 1 use for negative signals Page 52 of 97 SIS Documentation SIS3302 14xx SIS GmbH Firmware Gamma VME 4 21 Event Extended configuration registers define 5153302 EVENT EXTENDED CONFIG ALL ADC 0x01000070 Wwilters D32 7 define 5153302 EVENT EXTENDED CONFIG ADC12 0 02000070 read write define SIS3302 EVENT EXTENDED CONFIG ADC34 0x02800070 read write define SIS3302 EVENT EXTENDED CONFIG ADC56 0 03000070 read write define 5153302 EVENT EXTENDED CONFIG ADC78 0x03800070 read write This register is implemented for each channel group The 5153302 EVENT EXTENDED CONFIG ALL ADC register can be used to write the same setting to the registers of all channel groups simultaneously wa UN l 9 reserved 8 Trigger 50KHz Enable 6 ADC1 ADC N 1 Next Neighbor trigger enable 0 ADCI Trigger 50KHz Enable bit ______ ADCx Trigger 50KHz Enable b
85. ree 4 0 16 Disable Clear source 0 StatusflagsoureO 0 15 Unsed 14 jUnsed ______ Statusintermal 0 12 Unsed 11 Unsd S o OO IE E RI NEM 7 __ Enable IRQ source 7 7 Status enable source 7 read as 1 if enabled 0 if disabled 0 5 _ Enable IRQ source 6 __________ Status enable source 6 read as 1 if enabled 0 if disabled 0 5 __ Enable IRQ source 5 Status enable source 5 read as 1 if enabled 0 if disabled 0 4 __ Enable IRQ source 4 enable source 4 read as 1 if enabled 0 if disabled JO 3 __ Enable IRQ source 3 ___________ Status enable source 3 read as 1 if enabled 0 if disabled 0 2 __ Enable IRQ source 2 Status enable source 2 read as 1 if enabled 0 if disabled 0 ___ 1 Enable IRQ source Status enable source read as 1 if enabled 0 if disabled JO 0 Enable IRQ source 0 enable source 0 read as 1 if enabled 0 if disabled ____ 0 The power up default value reads 00000000 IRQ source 3 reserved IRQ source 2 reserved IRQ source 1 reached Address Threshold level sensitive IRQ source 0 reached Address Threshold edge sensitive Page 35 of 97 SIS Documentation 5153302 14xx Gmbh 1 Firmware Gamma VME 4 5 Acquisition control register define 5153302 ACQUISTION CONTROL 0 10 read write D32 define 5153302 ACQUISITION CONTROL 9510 read write 032 Note missin
86. register defines the length of the Trigger Gate 1 to 65536 and the Pretrigger Delay 0 to 1023 The used value for the Pretrigger Delay is the set value 2 with a wrap behaviour as illustrated in the table below Written value Trigger Gate Length 0 1 2 2 3 3 4 4 2 69559 05990 Written value Pretrigger Delay 0 1022 T0235 2 0 gt al 4 2 SLO 508 odd 3092 1022 1020 1025 Register bit assignments D31 25 D24 16 D15 0 O Pretrigger Delay 2 Trigger Gate Length 1 The power up default value is 0 Example Desired Trigger Gate Length of 1024 clocks and a Pretrigger Delay of 256 clocks samples gt set the register to Ox 0102 O3FF Note The Trigger Gate Length is independent from the Trigger Decimation Mode Page 55 of 97 SIS Documentation SIS3302 14xx Firmware Gamma 4 24 Raw Data Buffer Configuration registers define define define define define S193302 RAW DATA BUFFER CONFIG ALL 5153302 RAW DATA BUFFER CONFIG ADCI2 5153302 RAW DATA BUFFER CONFIG ADC34 5153302 RAW DATA BUFFER CONFIG ADC56 5153302 RAW DATA BUFFER CONFIG ADC78 0x0100000C 0x0200000C 0x0280000C 0x0300000C 0x0590000C SIS GmbH VME This register is used to configure the number of samples of raw data to be acquired and to define the number of pre trigger samples combination of Data Sample Start Index and Pretrigger Delay While the Trigger Gate is active the logi
87. s expanded from 1023 to 65535 maximum Trigger Output Pulse length expanded from 63 clocks to 255 clocks changed Trigger Gate logic add Event Extended Configuration registers e add Trigger Extended Setup registers Page 20 97 SIS Documentation 5153302 14xx SIS GmbH 4 000000 Gamma 1 30 11 09 09 Design Version F407 add adc value histogramming in MCA Mode e add ADCx Trigger 50KHz Enable bits in Event Extended configuration registers add MCA ADCXx histogramming Enable bits in MCA Histogram Parameter registers 1 31 28 09 09 Design Version 1407 Timestamp freeze logic modified 1 32 04 12 09 Design Version 1408 change Fir Trigger Filter reduced maximum Peaking time and Gap time values to 511 clocks expanded decimation 1 2 4 8 16 add Trigger Extended Threshold registers Page 3 of 97 SIS Documentation SIS3302 14xx SIS GmbH 4 Firmware Gamma VME 1 Table of contents L CON ea eaae och Cone dp i dee citeai oce e nea loa lili dea ae deal d nea 4 2 INTRODUCTION scai a clau l utari ala asta 7 2 1 FUNCTIONALE ____ 8 2 2 GAMMA LOGIC IMPLEMENTATION s0sccccsssscccnsscccesscccssscccansscccaassceseasscensesesesensssensesscesaasscensesssens 9 2 21 General block diagram one ADC channel and the full 9 2 2 2 Ir pe
88. s points to 16 bit words samples Next Sample Address Bit 24 Bank flag Next Sample Address Bit 2 Next Sample Address Bit 1 0 Sample Address Bit 0 Page 57 of 97 SIS Documentation 5153302 14xx Firmware Gamma 4 27 Actual Sample registers define SIS3302 ACTUAL SAMPLE VALUE ADC12 define 5153302 ACTUAL SAMPLE VALUE ADC34 define 5153302 ACTUAL SAMPLE VALUE ADC56 define 5153302 ACTUAL SAMPLE VALUE ADC56 Read the fly of the actual converted ADC values 0 02000020 0 02800020 0 03000020 0 03000020 SIS GmbH VME The read only registers are updated with every ADC clock unless a concurrent VME read access 15 pending The register contents is refreshed and can be read any time 1 they are updated independent of the unarmed armed sampling state as long as a sampling clock is distributed on the ADC board internal clock or active clocking external clock ADC 1 3 5 7 ADC 2 4 6 8 D31 16 D15 0 16 bit data 16 bit data Page 58 of 97 SIS Documentation 5153302 14xx SIS GmbH Firmware Gamma VME 4 28 Trigger Setup registers define 5153302 TRIGGER SETUP ADC1 0x02000030 define SIS3302 TRIGGER SETUP ADC2 0x02000038 define SIS3302 TRIGGER SETUP ADC3 0x02800030 define SIS3302 TRIGGER SETUP _ADC4 0x02800038 define 5153302 TRIGGER SETUP 5 0x03000030 define 5153302 TRIGGER SETUP ADC6 0x03000038 define SIS3302 TRIGGER SETUP ADC7 0x03800030 define SIS3302 TRIGGE
89. ut 3 gt ADC N 1 Neighbor Trigger Gate In input 2 gt Gate input 1 gt ADC N 1 Neighbor Trigger Gate In Lemo Input assignment input 3 gt reserved SIS GmbH 4 input 2 gt external Start histogram ptr reset start pulse input 1 gt external next pulse LNE input 3 gt Trigger input 2 gt external Start histogram ptr reset start pulse input 1 gt external next pulse LNE input 3 gt Veto input 2 gt external Start histogram ptr reset start pulse input 1 gt external next pulse LNE input 3 gt Gate input 2 gt external Start histogram ptr reset start pulse input 1 gt external next pulse LNE reserved Page 39 of 97 SIS Documentation 5153302 14xx SIS GmbH 1 Firmware Gamma VME 4 6 Broadcast setup register define 5153302 CBLT BROADCAST SETUP 0x30 read write D32 7 This read write register defines whether the 5153302 will participate a Broadcast The configuration of this register and the registers of other participating modules is essential for proper Broadcast behaviour _ _ _ 4 reserved 22 _ O 10 grseved 18 reserved 0 0 0 00 7 reserved 0 5 16 reserved 0 00000000 59 OSO 9 __ 0 00 0 o _ 80 O 7 90 6 90 OSO 34 2 reserved 0 O reserved 0
90. ved output 1 gt reserved MCA Mode bit 0 MCA Mode 1s disabled MCA Mode bit 1 Mode is enabled The Energy Histograms are build in the ADCx memories Page 38 of 97 SIS Documentation 5153302 14xx Firmware Gamma LEMO IN Mode bit setting table Lemo Input Mode with MCA Mode 0 Mode 0 bit2 0 bit 1 0 bit0 0 Mode 1 bit2 0 bit 1 0 bit0 1 Mode 2 bit2 0 bitl 1 bit0 0 Mode 3 bit2 0 bitl 1 bit0 1 Mode 4 bit2 0 bitl 1 bit0 0 Mode 5 bit2 1 bitl 0 bit0 1 Mode 6 bit2 1 bitl 1 bit0 0 Mode 7 bit2 1 bitl 1 bit0 1 Lemo Input Mode with MCA Mode 1 Mode 0 bit2 0 bit 1 0 bit0 0 Mode 1 bit2 0 bit 1 0 bit0 1 Mode 2 bit2 0 bitl 1 bit0 0 Mode 3 bit2 0 bitl 1 bit0 1 Mode 4 to 7 Lemo Input assignment input 3 gt Trigger input 2 gt Timestamp Clear input gt Veto input 3 gt Trigger input 2 gt Timestamp Clear input gt Gate input 3 gt reserved input 2 gt reserved input gt reserved input 3 gt reserved input 2 gt reserved input gt reserved input 3 gt ADC N 1 Neighbor Trigger Gate In input 2 gt Trigger input 1 gt ADC N 1 Neighbor Trigger Gate In input 3 gt ADC N 1 Neighbor Trigger Gate In input 2 gt Timestamp Clear input 1 gt ADC N 1 Neighbor Trigger Gate In input 3 gt ADC N 1 Neighbor Trigger Gate In input 2 gt Veto input 1 gt ADC N 1 Neighbor Trigger Gate In inp
91. with Tau correction P12 4 Peaking Time P13 gt Gap Time lt 14 gt save raw data gate A Raw Data S mple Start Index P6 Possible example 2 lt MAW MAWD Data Sample Length 8 save energy data MAW MAWD gate 4 Energy Sample Start Index1 P9 Possible example 3 save energy data MAW MAWD Data Sample Length P8 MAW MAWD gate E2 E3 E4 A Energy Sample Start Index1 P9 A Energy Sample Start Index2 P10 4 Energy Sample Start Index3 11 Page 15 of 97 SIS Documentation 5153302 14xx SIS GmbH 4 Firmware Gamma VME The Gamma Logic parameters are 2 P3 5 P6 7 P8 e 2 P 3 4 Page 16 of 97 Fast FIR Filter Trigger parameters see Trigger Setup ADCx registers Fast FIR Filter Trigger Threshold see Trigger Threshold ADCx registers Trigger Gate Length see Pretrigger Delay and Trigger Gate Length registers Pretrigger Delay see Pretrigger Delay and Trigger Gate Length registers Raw Data Sample Length see Raw Data Buffer Configuration registers Raw Data Sample Start Index see Raw Data Buffer Configuration registers Energy Gate Length see Energy Gate Length registers Energy Sample Length see Energy Sample Length registers Energy Sample Start Index1 see Energy Sa
92. with arbitrary data to this address issues a start pulse in MCA Multiscan mode 4 19 6 Key address MCA Multiscan Arm with Scan operation Arm 0x424 define 5153302 KEY MCA MULTISCAN ARM SCAN ARM 0x424 LE WES D32 A write with arbitrary data to this address arms the MCA Muliscan operation it starts with Start Reset pulse After the MCA Multiscan operation is started the logic arms the MCA Scan operation the Scan operation starts with next LNE 4 19 7 Key address MCA Multiscan Arm with Scan operation Enable 0x428 define 5153302 KEY MCA MULTISCAN ARM SCAN ENABLE 0x428 Wee D32 A write with arbitrary data to this address arms the MCA Muliscan operation it starts with Start Reset pulse After the MCA Multiscan operation is started the logic enables starts the MCA Scan operation 4 19 8 Key address MCA Multiscan Disable 0x42C fdefine 5153302 KEY MCA MULTISCAN DISABLE 0x42C Le wir DAZ A write with arbitrary data to this address disables MCA Multiscan operation Page 51 of 97 SIS Documentation SIS3302 14xx Gmbh 1 Firmware Gamma VME 4 20 Event configuration registers define SIS3302 EVENT CONFIG ALL ADC 001000000 Jw write only D32 define 5153302 EVENT ADC12 0x02000000 read write D32 define 5153302 EVENT CONFIG ADC34 0x02800000 read write D32 define 5153302 EVENT CONFIG ADC56 0x03000000 read write D32 define SIS3302 EVENT ADC78 0x03800000
93. zoidal Trigger Filter Fast FIR Per se __ ___ 10 22 21 Block diagramot the rigser MAW Ull 4 cie cesa eie eoa aeneae aa a denis eu PU ETUR d 11 2220 Sismal diacrain onthe Treger MAW la 12 2 29 Trapezoidal Energy Filter Slow FIR 12 223 Slow FIR Falter Bnerey sample la dna ae i tuia i di Aia a d ji ala dia 12 225 2 Block diasram MEA WE omae uoa uud ot ee 13 2222522 Seal diger or the MAW D UMT iu tun eu up ui ul ut iu ale 13 2234 Block diasram orthe movine average MA UTIL aa da 14 2222 Block diagram of the Deconvolution Tau correction 14 2 2 4 Gamma Farameter INUSITOM ON 15 2 2 V EAT OL CHO od RP PRO vano 17 226 Next Nero nDOF Trisoet GOtedOUIO esos aceti 19 Zu d Sample Logic with MCA Mode 24 2211 PCAC Wie 22 2 2 8 IVC AsV adera Uinta iale 23 2 2 8 1 MCAS Cat Enable 25 2202 67 ee 0 a er e ener Dai a 23 2 259 24 2 2 8 4 Multiscan Arm Scan ATM 24 2 29 23 2 2 9

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