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1. 149 CHAPTER 6 ORDERING INFORMATION cccccsssssscssscssscsosssssssosssosssosssosees 151 1 SCONTA 84 pn DIE E 151 2 151 21 IT 151 22 CBS PARTS Ot ITT t oe i E 151 2 2 1 Hardware Errata Details i cccccccccsssccccsssscececsscceceessecececsscceceesscceseessaceceessces 151 253 eerte EB 151 24 SPEBD GIBADES ecce teen tiet ee E ie o Eee te 153 2 52 153 3 OPTIONAL EQUIPMENT catene 153 3 1 COMPATIBLE DINI GROUP PRODUCTS 0 02000000020 00 0 00 00000000000 00 153 S l iuda asd tende osea caus 153 312 S E oet PDA D ada pd buts 155 3 2 COMPATIBLE THIRD PARTY PRODUCTS 22 2 8 8000000000 156 4 COMPLIANCE DATA 156 156 156 42 0 60 00 157 dd Tempel acusada at tene 157 TABLE OF CONTENTS 49 EXPORT CONTROL e tte ete ec tite e eet reb e dix rates 157 4 3 1 Lead Free 432 The USA Schedule B number based on the HTS 433 Export
2. 139 1 PURPOSE USE 139 1 1 INTERFACES USED BY REFERENCE DESIGN eene entente entes 139 2 HARDWARE TESTS vsceciccccsicdscccsecccctsscevccessdssccsbbccosssesevuscsvecdocsoesdsoocssdscesscedsieedoa 140 2 1 1 Testing FPGA to FPGA interconnect eese 140 2 1 2 Testing DDR2 TACT ACCS nest ot e De ee iret 140 2 3 USB cte au 140 2 1 4 Testing Daughtercard Connectors and External Clocks 140 REFERENCE DESIGN 141 Bilt MANTES e Dee E EN rere ees 141 32 EV DS sec E 141 2235 INE D donwctsueaeeuses san vesedbeasanessenvetvsonessberten 141 wo MEADER eee bte 141 4 USING THE REFERENCE DESIGN e eeeeeeee esee ee seen s ens ens es eene aee as 142 4 REFERENCE DESIGN MEMORY 8 142 5 INTERCONNECT SINGLE eere ee enero aora tne tne etna eaa 144 5 1 USING THE ceccccecscccssccssssccsssecssssccssssssssecesssscessscessssecssecessescessesessess 144 5 2 RUNNING THE TEST ee cette tere toto teet o eee ee te e e e esee deerat 145 6 DDR2INTERREAQCE eec eo oe eoe praese n
3. E A 58 3 4 3 External Compact Flasche atc dui eie a 58 3 5 CONFIGURATION REGISTERS ccccescsccsssccsssecesseecsssccsssscsssescesssccsssscsssscessescessesnes 58 3 5 1 Undocumented controls eee eee eee enses 59 26 sacs hi ccce eee 59 EE 60 4 CLOCK NEIWONRNK 60 4 1 DISAMBIGUATION 60 TABLE OF CONTENTS AD GEOBAL CLOCKS sock notti eto occult 60 2d AGO AGT 62 CIOCKS o ineat tha Rt Mira eet a te 62 422 Clock VERIZON S a uita P Rea od Nobb itae diss 62 4 2 3 Feeding a Global Clock from an External Clock Source 65 dou JONES 67 20 Step Clock asa sucked C PO A satan echt 67 EPA sco t m estf tenet 67 423 E A ec ue 68 AA JDOOCLRNEDIWOBRS 68 45 NON GLOBAL CLOCKS tip endet cette 71 dog Daughter Card Local Clocks 71 ous AE A 71 SMA EMO 73 du DDR eie 74 5
4. Quae e uae 75 Jd POWER DHRU HOLE Seed a etd 75 5 2 ACLOCK TESTPOINIS i Id eoe toro udi tete e aditus 78 9 9 DIMM CK SIGNALS 79 25 4 BATTERY TESTPOINT enabled 79 6 79 6 1 CONNECTING TO THE DN9000K TD 80 OCT A dre ieu 80 80 CON Po SEMIN 5 80 e toa ites ted taka Sate 80 6 2 VENDORREQUESTS rosei se aiiis 81 O2 AIG CTIA 82 6 2 2 VRZSETUP CONFIG ee eor nte kas eus 82 6 23 escrita ro e oai dua RS 82 624 VR_SET_EP6TC Read buffer size aie mi dedic 82 6 2 5 Configuration Registers essere 82 0 207 Other Vendor 82 6 31 BUS ACCESSES Olbia tete 83 6 3 1 Important Note about Endpoihis uu 83 0 9 2 gt PCI OVINGICE i iti diete ui qc adu a nde Hu d und 83 EPGA CONFIGU
5. BUS XX Name A unique name of the bus schematic OxOxxxxxxx REG DEFAULT OxDEAD5566 any undefined register 5 Interconnect Single The single ended interconnect test tests the DC connectivity of FPGA to FPGA interconnect and the MB signals Presented on the MainBus are registers allowing the interface to control the output value output enable and input value of each FPGA to FPGA interconnect pin Each pin on the FPGAs is pulled high This allows a test program to find single stuck at faults open faults and stuck together faults 5 1 Using the Design The design can be controller over the MainBus The register banks connected to the IO are arranged into busses Each bus has an ID code an OE register bank an ENABLE register bank and an IN register bank The addresses of the IO registers are as follows FpgaNum 4 bit MB_SEL_INTERCON 4 bit busnum 20 bit reg offset 4 bit FPGA NUM is 0x0 for FPGA F0 0 1 for FPGA F1 0x2 for FPGA F2 MB_SEL_INTERCON is 0xC busnum is any number but only low values less than LAST_ADDR will constrain valid busses reg offset is 0 0 for REG OUT 0x4 for REG OE 0x8 for REG IN and OxC for REG ENABLED To determine which bits if any in bus are valid read the REG ENABLED register The 32 bits returned 1 are a mask for which of the bits in the REG OUT REG OE and REG IN registets are meaningful To get the bus ID of a bus write value 0x1
6. DN9000K10 User Guide www dinigroup com 79 THE REFERENCE DESIGN USB on the DN9000K10 also allows control of the configuration circuitry from a host PC This includes configuring FPGAs setting clock frequencies and others This section will describe the software interface required to communicate to the DN9000K10 In addition to reading this section you may choose to modify the provided software USB Controller and AETEST_usb The source code for these programs is on the user CD These programs collectively implement all of the available controls on the DN9000K10 6 1 Connecting to the DN9000K10 Depending on the operating system there are different methods of obtaining a software handle to the DN9000K10 in order to access it from softwate 6 1 1 Windows XP What driver is this It s the EzUSB driver HANDLE handle CreateFile Ezusb 0 GENERIC WRITE FILE SHARE WRITE NULL OPEN EXISTING 0 NULL The EzUsb 0 device name is registered with Windows when installing the EzUSB device driver The ini file provided with the driver causes the driver to be assigned to any USB device with VendorID 0x1234 and ProductID 0x1234 The HANDLE object returned by CreateFile is suitable for use with DeviceloControl 6 1 2 Windows Vista Testing was not complete at print time Contact support dinigroup com for the latest information on this 6 1 3 Linux To use USB in Linux use the provided usbdrvlinux c f
7. PROM File Formatter prom_fip mes bypass Available Operations are Program Succeeded gt Program mp Verify Operations Boundary Scan done 1 Putting device in ISP mode done done 1 Putting device in ISP mode done 1 Verifying device done 1 Verification completed 1 Putting device in ISP mode done 1 Programming completed successfully 1 Programming completed successfully PROGRESS END End Operation Elapsed time 122 sec utput Eror 1 Waming Configuration Platform Cable USB 6 MHz usb hs Figure 13 iMPACT window on succeeded Warning Performing this procedure incorrectly may result in a non functioning board Contact support first to confirm that updated firmware is available and will correct your problem support dinigroup com 4 3 2 Using USBController If you do not have a JTAG cable you will need to use the following instructions to update your Spartan PROM firmware This update is dependent on USBController and Flash firmware version Please double check with us support dinigroup com to make sure that your current version MCU version USBController supports this option and request xsvf file from us 1 Open USBController ini and add the line service _mode 1 You save and close the file DN9000K10 User Guide www dinigroup com 42 CONTROLLER SOFTWARE Launch USBController go to
8. COUNTER COUNTER COUNTER This range of addresses is reserved for manufacturing tests Daughtercards This does nothing on the DN9000K10 Ox1 if the FPGA is an LX330 0 0 is it is not Data read from the SODIMM IIC interface Contains contents of GO counter Contains contents of G1 counter Contains contents of G2 counter Contains contents of MBCLK counter LVDS source synchronous clock counters LVDS design only Clock counters for DCLK0 DCLK3 NONE NONE REFCLK 200MHz NONE NONE DDR_FB_CLK TESTPOINT NONE DDR2TESTTAPCNT Reserved for manufacturing tests DDR2 DDR2SIZE SODIMM2 HIADDRSIZE SODIMM2 SODIMM2 RANK SODIMM2 COL SODIMM2 ROW SODIMM2 BANK SODIMM2 CAS VRP ALL VRN ALL RS232 BUS SPI BLOCKRAM DN9000K10 User Guide Controls address mapping order on second DIMM interface FGPA C only Number of unique addresses in HIADDR for second DIMM interface FPGA C only data retrieved from the SODIMM in socket 2 FPGA C only Contains input signals on the pins Contains input values on the pins Mapped to the RS232 signals Mapped to SPI Flash signals the contents of an internal FPGA block RAM www dinigroup com 143 THE REFERENCE DESIGN 0x0CO00XXO BUS XX OUT XX can be 0 21 hex Output status of IOs on bus XX 0x0CO00XX4 BUS XX OE XX can be 0 21 hex OE status of IOs 0 0 000 8 BUS XX IN XX can be 0 21 hex The input values
9. MEG Array Expansion Connector 400 pin 5 1 5V to 3 3V 1 5V to 3 3V I O TAI 7 96 1196 A O AS L uid oop 101290009 uoisuedx3 93W MEG Array Expansion Connector 400 pin LX330 FF1760 120 128Mb DIMMs 15V1043 3V 10 Diagram indicating what features and pins ate lost when downgrading to LX220 LX110 parts Note that red cross bars indicate number of pins LOST For example when using LX110 parts for F4 and F8 you lose 100 pairs leaving 20 pairs connecting the two chips DN9000K10 User Guide www dinigroup com 152 1 5V to 3 3V I O 1X330 160x54 160 108 240 108 110 592 221184 331 776 69 120 138 240 207 360 4 608 6912 10 368 2 4 Speed Grades The interface performance characterizations included in this manual and in advertisements are valid for all shipped FPGAs regardless of speed grade These numbers are characterizations and not guaranteed under all operational conditions Every shipped board has passed this characterization test under some operational conditions If there are any interfaces where performance is only characterized for specific speed grade parts this is noted in the advertisement and in this document 2 5 Upgrade Policy Upgrading adding FPGAs to a DN9000K10 Call for a quote 3 Optional Equipment The following tools are suggested for use with the Dini Group DN9000K10
10. 100 ohm resistor connects the P and side of these clock signals This is excellent for probing with a high impedance probe but not so good for connecting wires You can remove this tesistor if needed Clock Test Points p n PHO Test TP34 TP33 PH1 Test TP41 TP42 PH2 Test TP48 TP49 MBCLK Test TP37 TP38 5 3 DIMM CK Signals These test points are described in section 14 5 DIMM Clock Testpoints 5 4 Battery Testpoint TP16 is a test point for attaching a temporary power source while swapping out the FPGA encryption backup battery BT1 Nominal voltage for this test point is 3 0V maximum applied voltage is 3 0V The recommended procedure is to apply a 3 0V signal to this net square pad is power circular is for ground reference swap out 1 install a new battery into and then disconnect the external power supply It is not recommended to leave an external power supply on TP16 for long periods of time 6 USB interface The DN9000K10 allows the user FPGA to communicate to a host PC over USB The configuration circuitry allows this by bridging USB to the Main Bus interface For most users implementing USB communication will be as simple as making a Main Bus controller inside each FPGA difficulty 9 9 9 9 92 5 gates In the reference design there is an example Main Bus controller See the Main Bus section of this chapter for more information on the Main Bus USB Connector
11. DN9000K10 User Guide www dinigroup com 123 THE REFERENCE DESIGN Mounting holes are all over the place represented by the grey circles These are grounded Metal runners are installed parallel to all four edges of the board These are for ground oscilloscope probe ground clips You should also handle the DN9000K10 by its ground bars to help prevent ESD damage to the FPGAs 22Daughtercard Headers The daughter card expansion capability of the DN9000K10 is provided by several FCI MEG Array family connectors Even though it uses the same FCI connector it is NOT compatible with the 300 pin MSA standard Daughter card headers are named DC2 through DC10 These are somewhat arbitrary naming numbering schemes based on where the header is on the board DN9000K10 User Guide www dinigroup com 124 THE REFERENCE DESIGN Each daughtercard connector provides 186 signals plus 4 clocks to its associated FPGA The signals can be used with just about any setting of IOSTANDARD and can be used differentially The following is a list of headers and their associated FPGAs Header FPGA DC2 P102 F8 DC3 P103 F12 DC4 P104 F3 DC5 P105 F3 DC6 P106 F7 DC7 P107 F11 DC8 P108 F15 DC9 P109 F15 DC10 P210 F16 Note 1 DC4 and do not follow the standard bank splits as the other headers do This limitation is described later in this section Note 2 DC10 is connected
12. a n 117 19 5 eae tet teet OE 117 19 6 OTHER POWER 8 0 00 117 19775 aieo etre ese terere ERU desee EE 117 19 8 POWER CONNECTIONS ccccccccccccsscccsssscssscecssscccssccssssscsssescesscccssssssssscessescessssseaees 118 19 9 POWER MONITORS E E EEE 119 19 AOS HEA 119 om 120 19 10 2 Removing Heat 120 49 103 Tachom el ers ii e e i eee dete eris 120 2 OLD OLOR 122 20 1 FPGA USER INTERFACE 8 0 4 00000000 122 20 L1 Comments iss ee eee e ERO Ned 122 21 MECHANICAL 000464 0 nenas tibt 123 22 DAUGHTERCARD 5 eene tenens tns ens ens ens esee aseo 124 22 1 DAUGHTER CARD 2 0 0 0 2 1 1 6006 eite seen neon 126 22 1 1 Daughter Card Locations and Mounting 126 22 1 2 Insertion and removal eese 127 22 2 DAUGHTER CARD 1 00000 00 00 128 22 2 1 PH GSSIBRIBEHINS ee aan eben 129 TABLE OF CONTENTS 22 22 LO Bank Splits sicat alan boe duet Mer Med oe aids 131 22 2 3 CE
13. 3 1 Compatible Dini Group products The Dini Group supplies standard daughtercards and memory modules that you can use with the DN9000K10 3 1 1 Memories DNSODM200 SRAM Memory module for use in the 200 pin SODIMM sockets Standard memory configuration Two GS8320V32 memories 1M x 32 each DN9000K10 User Guide www dinigroup com 153 ORDERING INFORMATION Performance up to 175MHz SDR Small EPROM Contact us about zero bus latency type parts DNSODM200_RLDRAM Reduced latency DRAM Micron 64 bit wide compatible with the 200 pin SODIMM sockets Small EPROM DNSODM200 MICTOR Provides 2 Mictor 38 connectots Compatible with the DDR2 SODIMM sockets User LEDs Small EPROM DNSODM200 QUADMIC Provides 4 Mictor 38 connectots Compatible with the DDR2 SODIMM sockets DNSODM200 DDR1 DDR1 memory module compatible with the 200 pin SODIMM sockets Comes with 512MB standard Allows use of standard PC2700 modules up to 1GB 175MHz performance DNSODM200 DDR3 DDR3 memory module compatible with the 200 pin SODIMM sockets Comes with 512MB standard 200MHz performance DNSODM200 SDR SDR memory module compatible with 200 pin SODIMM sockets Accepts PC133 modules up to 512MB User is required to install a Jumper Comes with 256MB standard 75MHz performance DNSODM200_ FLASH Spansion S29WS064 memory x2 Each is 4Mx16 bit flash 16Mb SRAM memory 612k x 32 Compatible with DDR2 SODIMM sockets 66MHz performan
14. 433V Power LEDs 40 pin Header 0 1 pin spacing Samtec 3 Rocket channels Vohage Control 40 pin 4 Header 3 2 Compatible third party products The following products have been shown to work with the DN9000K10 Standard DDR2 modules 256 MB 19 512 MB 15 1GB 25 2GB 79 4GB eventually http www ctucial com stote listmodule DDRII list html Xilinx Platform USB Cable required for JTAG FPGA programming firmware update ChipScope Pro Synplicity Identify HW USB G http nuhorizons com Mictot bteakout MIC 38 BREAKOUT http www emulation com catalog off the shelf solutions mictor 4 Compliance Data 4 1 Compliance 4 1 1 EMI Since the DN9000K10 is not intended for production systems it has not passed EMI testing Compliance is only done by special request DN9000K10 User Guide www dinigroup com 156 ORDERING INFORMATION 4 2 Environmental 4 2 1 Temperature The DN9000K10 is designed to operate within an ambient temperature range of 0 50 degrees C All components used on the DN9000K10 are guaranteed to operate within a temperature range of 0 80 degrees C measured on the device die 4 3 Export Control 4 3 1 Lead Free The DN9000K10 meets the requirements of EU Directive 2002 95 EC RoHS Specifically the DN9000K10 contains no homogeneous materials that a contains lead Pb in excess of 0 1 weight o 1000 ppm b contains mercury Hg in excess
15. One Shot Test This menu option tests various functions on the board automatically configuring the FPGAs and setting up the clocks as required Note that some options like the header test require an external test fixture that is not provided with the board 1 3 INI File Some command considered debugging commands save persistence information in an ini file that gets created in the same directory as the USB Controller executable This file should not be generated for most users Some of the settings that can be stored in this file are the Text Editor Selection settings the location of path to the reference design programming files for one shot test and enabling the debug menu Deleting the file will clear those settings but will not cause any fatal problems 2 AETEST USB 2 1 Compiling AETEST usb AETEST usb can be compiled using Microsoft Visual Studio 6 or later or on any version of Linux that supports the usbdevfs library DN9000K10 User Guide www dinigroup com 37 CONTROLLER SOFTWARE A make file is provided but you must un comment one of the following lines to define which operating system you are running In Windows you should run nmake ZDESTOS WIN ZDESTOS LINUX ZDESTOS SOLARIS 2 1 1 Cygwin Nope VS6 only AETEST utility program can test and verify the functionality of the DN9000K10 Logic Emulation board and provide data transfer to and from the User design 3 Rolling Your Own Software
16. 1 6 Ordering Information Contains a list of the available options and available optional equipment some suggested parts and equipment available from third party vendors Compatibility lists also 2 Conventions This document uses the following conventions An example illustrates each convention 2 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Prefix Indicates hexadecimal notation Read from addtess 0x00110373 returned Suffix H Signal is active low INTF is active low RSTn is active low 2 2 Manual Content 2 2 1 File names Paths to documents included on the User CD prefixed with D V This refers to your CD drive s root directory when the User CD is inserted in your Windows computer Alternately copy the entire contents of the User CD to your hard drive and allow D to refer to this path Due to limitations of the Xilinx ISE software we recommend a path without space characters in it Bad places include C Documents and Settings username Desketop DN9000K10 User Guide www dinigroup com INTRODUCTION 2 2 2 Physical Dimensions By convention the board is oriented as shown in the above board photo with the north of the board being the edge near DDR2 SODIMM number 0 The east edge is near the front panel connections The west side is the side with fewer connectors Compon
17. 1125 B2L22P 2124 BOL25N BOL27N 1124 1126 2125 B2L26N BOL25P 0127 1124 1126 2125 2126 BOL26N 0129 1128 1127 2127 2128 BOL26P BOL29P 1128 1127 B2L27P B2L28P BOL28N 1 B1L2N B1L29N B2L29N B2L30N BOL28P BOL31P B1L2P B1L29P B2L29P B2L30P BOL2N BOL3N B1L30N B1L31N B2L2N B2L3N BOL2P BOL3P B1L30P B1L31P B2L2P B2L3P BOLS3ON BOLAN B1L3N B1L5N B2L31N B2LAN DN9000K10 User Guide www dinigroup com 131 THE REFERENCE DESIGN BOL3OP BOL4P B1L3P B1L5P B2L31P B2L4P BOL5N BOL7N B1LAN B1L6N B2L5N B2L7N BOL5P BOL7P B1iL4P B1L6P B2L5P B2L7P BOL6N BOL8N B1L7N B1L9N B2L6N B2L8N BOL6P BOL8P B1L7P B1L9P B2L6P B2L8P BOL9N B1L8N B2L9N BOL9P B1L8P B2L9P Bank OA OB etc correspond to individual banks on FPGAs Here is the mapping FPGA Bank0A BankOB Bank1A Bank1B Bank2A Bank 2B Header F8 2 16 20 12 14 18 22 F12 DC3 16 20 12 14 18 22 5 17 21 11 13 19 15 F7 DC6 17 21 11 13 19 15 F11 17 Al 11 13 19 15 F15 DC8 17 21 11 13 19 15 VCCO is shared between banks on the FPGA i e Bank 0 on the daughter card shares VCCO with Bank and Bank OB on the FPGA CC pins are split evenly between both banks same with VREF Positions DC4 and DC9 have their bank splits defined differently as they use five FPGA banks for the three daughter card banks See the schematic for details on these
18. All of these connectors should be fully described in the manual section indicated below Reference Manuf Part Number Connector description J89 J90 J94 J95 J99 J106 J12 J7 J39 J40 JA J65 J6 J11 Lighthorse LTI SASF546 P26 X1 SMA Jacks differential J203 AMP 2 767004 2 Mictor logic analyzer connector P102 P103 P104 P105 P106 P107 P108 P109 P210 FCI 84520102LF MEG Array 400 pin plug J100 J101 J102 J103 1104 1105 JAE MM50 200B2 1E DDR2 200 pin SODIMM socket Shrouded Right Angle Header P204 P206 P207 P208 Tyco 5103310 1 0 1 P209 Molex 71349 1003 Shrouded Vertical Header 0 1 J42 Molex 67068 1000 USB Header Right Angle Type B 20 1 1 Comments If you have a board with fewer than two FPGAs installed connectors associated with the missing FPGA will be not being installed This is typically the daughter card connectors and the SODIMMs DN9000K10 User Guide www dinigroup com 122 THE REFERENCE DESIGN 21Mechanical The following diagram outlines the basic dimensions and mounting hole positions on the DN9000K10 525 6 35 525 374 75 O e 153 398 259 121 321 202 6 35 5 5 3 gt 542 5 0 0 co ordinate is in south west corner of PCB 237 374 75 237 259 237 121 237 6 33 143 374 75 153 202 143 635 85 374 75 24 315 25 24 190 5 24 66 25
19. Compact Flash card The procedure in USB Controller is outlined below By default the DN9000K10 accepts an LVDS clock input on the external clock SMAs This can be changed to LVPECL or CML by changing the resistor stuffing options for the clock mux See schematic pages 98 100 for details on this option There are no explicit limits on the input frequency of the external clocks Warning Do not attempt to make changes to your PCB without proper training in SMD soldering techniques The potential for causing irreversible damage to the product is very high when performing rework procedures 4 2 3 1 How to set up a Global Clock to feed from SMA input In USB Controller this operation is simple Step one is to select the GCLK Mux dialog DN9000K10 User Guide www dinigroup com 65 THE REFERENCE DESIGN DiNi Products USB Controller aus Settings Info Service 6000 10 Series RocketiO Frequency Change Text Editor FPGA Stuffing Information 2 Turn FPGA Fans On Off BOARD SPARTAN MCU Version Read FPGA Temperatures a UU X Force Memory Menu Display Toggle Sanity Check 258 Read Write Benchmark Update Spartan were Setup Clock Frequencies p DNB000K10P5 Glock Mux Setup DNSOO0KIOPEI Clock Source Selection N8 9000k10 GCLK Mux Dialog m DN8000k10 MB Switches Clock Synth Setup DN8000k10 Read Synth Settings DN8000k10 DC Clock Setup DN8000k10 Rocket IO Mux Setup Su Test DDR
20. should update in the following order DN9000K10 User Guide www dinigroup com 39 CONTROLLER SOFTWARE 1 USB Controller exe http www dinigroup com product common USBController zip 2 Configuration FPGA PROM firmware 3 EEPROM option 4 MCU Flash 5 Clock Frequency Tables 4 3 Updating the Spartan PROM firmware 4 3 1 Using JTAG cable Xilinx products This process assumes that you have install iMPACT program and are using Xilinx JTAG Cable USB 1 2 Connect the cable to the Firmware header 19 on top 201 on bottom Power on the DN9000K10 When the Platform USB cable is connected to a header the status light turns green Run iMPACT program iMPACT Project Dialog will appear please hit Cancel At the main iMPACT window please double click on Boundary Scan on the upper left corner Move mouse to Boundary Scan tab right click and select Initialize Chain The chain should recognize 2 devices xcf32p and xc4vlx80 Assign New Configuration File Dialog is opened please select prom flp mcs for the first device and Bypass the second device DN9000K10 User Guide www dinigroup com 40 CONTROLLER SOFTWARE 5 Boundary Scan File Edit View Operations Output Debug Window Help PE x 2220 ight click device to select operations SalBoundary Scan Rig x alSlaveSerial alselectMAP alDesktop Configuration alDirect
21. 0 1377 H 1 843199 MHz 4 15791 624 3 375 H 2 457600 MHz 4 15791 624 3 281 H 3 276800 MHz 4 47487 1874 3 211 H 3 579545 MHz 5 7900 31 2 225 H 3 686399 MHz 4 15791 624 3 187 H 4 006000 MHz 7 2303 124 7 107 4 194304 MHz 6 36307 1790 6 115 4 433617 MHz 6 49867 2462 0 273 4 915200 MHz 7 2303 124 7 89 H 6 144000 MHz 4 631 24 1 157 7 372799 4 15791 624 3 93 8 192000 MHz 7 2303 124 7 53 8 867238 MHz 1 2153 52 7 49 H 9 216000 MHz 7 2303 124 7 47 H 9 830400 MHz 4 15871 624 4 61 10 160000 MHz 2 507 14 6 47 H 10 245000 MHz 3 23221 79 3 67 11 059200 MHz 7 2303 124 7 39 www dinigroup com THE REFERENCE DESIGN dk XE XE XE XE XE XE XE GE db Xt db XE XE XE XE Xt db Xt db Xdb Xt db db XE db Xt Xt db dE db XE XE Xt dk Xt db db dt db XE dt xb xtodt 11 228000 MHz 5 11 289600 MHz 3 12 288000 MHz 7 14 318181 MHz 3 14 745599 MHz 7 16 384000 MHz 4 16 934400 MHz 5 17 734475 MHz 0 17 900000 MHz 0 18 432000 MHz 7 19 200000 MHz 4 19 440000 MHz 5 19 531250 MHz 1 19 660800 MHz 4 22 118400 MHz 7 24 576000 MHz 7 26 562500 MHz 1 32 768000 MHz 4 33 330000 MHz 7 38 880000 MHz 5 66 660000 MHz 7 74 175824 MHz 7 76 800000 MHz 4 77 760000 MHz 5 98 304000 MHz 4 122 880000 MHz 4 124 416000 MHz 5 133 330000 MHz 0 155 520000 MHz 5 156 256000 MHz 4 159 375000 MHz 1 160 380000 MHz 7 161 130000 MHz 0 161 132800 MHz 4 164 360000 MHz 3 166 630000 MHz 0 166 667000 MHz 0 167 331600 MHz 5 172 640000 MHz 0 173 37
22. 17 Note that on the netlist these signals connect to the FPGA twice once on DDR2 interface bank 1 8V and once on the global clock input bank 2 5V The 2 5V clock bank connections should be used as inputs and the 1 8V bank signals should be configured as outputs For input signals use the LVDSEXT standard with the DIFF_TERM attribute set to TRUE NOTE Be careful when running DIMM PWR at 3 3V to avoid loading the DIMM _CK2 lines with a 3 3V signal 5 Test points This section lists all of the test points on the DN9000K10 A more detailed description may be found in the section about the system that the test point is part of but all test points are listed here for reference 5 1 Power Thru hole Each power rail on DN9000K10 has a dedicated test point associated with it This test point is a through hole two pin location where pin one is the power rail and pin two is a ground connection These test point locations are physically suitable for supplying at least 2A disregarding the power requirements or capabilities of the power net DN9000K10 User Guide www dinigroup com 75 THE REFERENCE DESIGN FPGA F11 XILINX VIRTEX XC5VLX330 FFG 1 T60FGL 74 lt 2 00 1478549 Aiwa Pin one power is a square Pin two is circular GND Test Point Net Name Nominal Voltage TP1 DIMM VTTO 0 9V TP2 DIMM PWRO 1 8V TPS DIMM VT
23. 32 bit to REG ENABLED then read REG ENABLED then write 0x0 32 bit to ENABLED The value returned will be a coded name for the bus Bits 0 15 are ASCII characters representing FPGA names Bits 16 31 are an arbitrary unique integer distinguishing the bus Connecting busses from two different FPGAs have the same bus ID To cause an FPGA to output signals on a bus write Ox FFFFFFFF on REG OE To set the outputs all to high write to REG OUT To read the current received value from the bus inputs read from REG IN DN9000K10 User Guide www dinigroup com 144 THE REFERENCE DESIGN 5 2 Running the Test In the USB Controller program select Settings gt One Shot Test From the dialog box check the Interconnect Test box The program will automatically load the bit files set the clocks and run the test 6 DDR2 Interface The DDR2 interface design is an example DDR2 controller running at 250MHz You can use this controller as an example especially for the purpose of required IO logic timing and clocking The controller bandwidth is most of the DDR2 bandwidth possible on the DN9000K10 6 1 Provided Files The DDR2 reference design is part of the reference design and the Main Test files should be used 6 2 Using the Design The DDR2 memory interfaces are mapped to the address range OxNXX00000 OXNXXFFFFF Where the 4 bit N represents an FPGA ID as described in th
24. 98 DONC AG BH Syn Ep M Clock inputs to 215226 14 FCS _ PH2 SYN CK2p 100 Global Clock L4N_VREF_FOE_B_ 0 PH2 SYN CK2n 100 Synthesizer L5P FWE REF SYN CK2p 102 REF SYN CK2n 102 XCSVDG3OFF1760 1 Clock pins on FPGA F15 The design loaded in FPGA F15 must output a clock First check the CK2 GOOD LED on each synthesizer to make sure the synthesizer recognized your clock output as a valid signal This LED is DS139 on PHO DS143 on PH1 DS159 on PH2 and DS135 on REFCLK To use the clock input from FPGA F15 enter USB Controller From the Settings Info menu select DN8 9000k10 GCLK Mux Dialog Select the clock you want to use and in the GCLK Configuration dialog select FPGA15 Clk output Note This option is not available in software for To use this feature for REFCLK setup must be accomplished over Compact FLASH see section 3 4 1 of this chapter for how to do this DN9000K10 User Guide www dinigroup com 67 THE REFERENCE DESIGN 4 3 REFCLK REFCLK is a clock distributed in the same way as G0 G2 However it does not feature the same 4 1 bus So there is no mux selection for it only a programmable synthesizer Otherwise the clock is length PLL matched the same way as G0 G2 and connects to the same type on input at the FPGA The naming convention for REFCLK is REFCLK F P where is the FPGA number you are referencing REFCLK is fixed to 200MHz It may be changed by specifying an alternate frequenc
25. CLEAR FPGA This vendor request clears an FPGA Direction is OUT Size is 0 Value represents which FPGA should be cleared 0 is FPGA FO 1 is FPGA F1 and so on 6 2 2 VR_SETUP_CONFIG This vendor request must be called before sending configuration data to an FPGA It tells the DN9000K10 which FPGA should receive the next configuration stream sent over USB It also clears that FPGA of its current configuration Direction is OUT Size is 1 In the buffer is a number representing which FPGA should be selected 0 is FPGA F0 1 is FPGA F1 2 is FPGA F2 and so on 6 2 3 VR END CONFIG This vendor request de selects and FPGA so that configuration data sent will go to no FPGA and checks the configuration status of an FPGA 6 2 4 VR SET 6 Read buffer size The SetReadBufferSize vendor request must be used before any bulk read bulk transfer This sets the size in bytes of the data that will be requested by the bulk transfer If this vendor request is not sent before the bulk read the behavior is undefined The direction is OUT The size is 0 The value is the number of bytes required for the next bulk transfer 6 2 5 VR MEM MAPPED Configuration Registers Some of the controls on the DN9000K10 do not have their own Vendor Request These functions include setting the clock frequencies In order to accomplish these tasks you must use the Configuration Registers The full list of registers is in the Configuration Secti
26. Dini Group DN9000K10 DN9000K10 reference design Also board description Programming_Files files and simulation models apencore Schematics Rev_01 Contains a PDF version of the board schematic Search the PDF using control F Also contains an ASCII netlist of the board USB_Software_Applications Contains source and binaries for the provided driver USB hosted controller applications aetest_usb USBController The schematic is probably the single most useful resource available even more so than this manual All functionality is drawn out correctly in the schematic When it doubt or when an inconsistency between two resources is found the schematic should be treated as the controlling document 3 2 Dinigroup com The most recent versions of the following documents are found on the product web page http dinigroup com DN9000k10 php User s Manual this document e Errata none at the time of printing e USB Controller executable 3 3 Errata and Customer Notifications The Errata sheet available at www dinigroup com lists all cases where the DN9000K10 is found to have failed to meet advertised specifications ot where an error in schematics ot documentation is likely to cause a difficult to debug error by the user Customets are not notified when changes are made to other documents including the reference design USB Controller and User Manual These documents change on a weekly basis or more often You the customer may a
27. FIRMWARE ecce nnne en nnne ente et ense 44 4 4 1 5 ated beet ca obtu 44 DS 45 4 5 UPDATING THE MCU FLASH 2 2 72 002 2 0001000 ennt enne 45 AOI DUsmnplSBGonirollers usate etis e stets 45 qun ut ren duties 46 4 6 UPDATE CLOCK FREQUENCY 8 2 0 8 46 CHAPTER 4 HARDWARE 522005 47 1 GENERAL OVERVIEW eeeeeeeesee essen seen s ens ens ens eene eese e ese ene ens ens ens ense 47 11 iaai 49 LII 49 2 5 50 3 CONFIGURATION SECTION cccccsccssscssscsssccssssssssosssssssosssssssssssscscsssssossees 50 3 1 CONFIGURATION SECTION 00 044000000 00 51 3 2 FPGA CONFIGURATION ccccccessscesscccsssccsssscsssescesssccssscsssescesssscsssscsssscessescessecsees 53 3 3 200 eerta cet periret vere ea Eae 54 3 4 COMPACT FLASH 00 00 10 54 2 41 nonien nO 54 ER WAE E
28. FPGAs is given It is accessible through 20 on the component side and J202 on the solder side The FPGAs are in order on the JTAG chain This is not a preferred method of configuring FPGAs and is usually only used as a debugging interface for FPGA debug tools and as a fail safe backup to the configuration methods listed above 4 Clock Network 4 1 Disambiguation GC Pins When this manual refers to a clock input of an FPGA it means the GC pin described in the Virtex 5 user manual These pins have the capability of driving a DCM PLL or BUFG input with a known accounted for delay within the FPGA 4 2 Global Clocks All of the global clock networks on the DN9000K10 are LVDS point to point signals The arrival times of the clock edges at each FPGA are phase aligned length matched on the PCB and aligned using PLL buffers within about 100ps These clocks are all suitable for synchronous communication among FPGAs Since LVDS is a very low voltage swing differential signal you cannot receive these signals without using a differential input buffer Single ended inputs will not work An example Verilog implementation of a differential clock input is gtven below Wire aclk_ibufds IBUFGDS GOCLK_IBUFG O g0clk_ibufg I GCLKOp IB GCLK0n always g0clk_ibufg begin Registers end Either in the UCF or using a synthesis directive you should turn the DIFF_TERM attribute of the IBUFGDS to TRUE This is highly recommended
29. Interface Most important settings on the DN9000K10 can be controlled through the Compact Flash interface This interface can also be used to configure FPGAs The Compact Flash interface is not under the direct control of the user but is accessed only by the configuration logic If you have a chassis it is preferable and easier to use the front panel Compact Flash slot Without a chassis you should use J22 the on board Compact Flash socket 3 4 1 Main txt The main txt interface is the primary method you will use to control settings on the DN9000K10 From this interface you can DN9000K10 User Guide www dinigroup com 54 THE REFERENCE DESIGN Configure FPGAs Set clock frequencies and mux settings write to MainBus Other settings on the DN9000K10 can also be controlled via the main txt file by accessing the configuration registers using the MEMORY MAPPED command To use the main txt interface create a file called main txt on the root directory of the Compact Flash card Plug the card into the DN9000K10 either to the on board socket or the front panel socket depending on chassis options The DN9000K10 will execute commands contained within this file when the board powers on when the Hard Reset button is pressed or when instructed to do so by the USB interface vendor request A main txt file contains a list of commands separated by newline characters A list of valid main txt commands is given below comment FPG
30. Itt fee 11 101 9999 Signal Name LEDs associated Meaning LOL_LED DS141 GO 515326 LED ON indicates loss of input frequency DS145 G1 515326 lock on the associated 515326 105158 G2 15326 105137 REFCLK 15326 1 INT 05140 GO 15326 LED ON indicates that CK1 input is not DS144 G1 515326 acceptable This generally indicates a DS157 G2 515326 hardware failure with the on board oscillator DS136 REFCLK 15326 C2B_INT DS139 GO Si5326 LED ON indicates that CK2 input is valid DS143 G1 515326 DS159 G2 515326 DS135 REFCLK 515326 This indicates that a valid clock is being sourced from FPGA F15 DN9000K10 User Guide www dinigroup com 98 THE REFERENCE DESIGN 13 6 Unused LEDs These LEDs ate controlled by the configuration circuitry At print time the meaning of these LEDs was undefined These LEDs often blink just when you least expect them to LED Reference LED Signal Name the LED indicates the following Designator Color DS1 18 ex 16 GREEN Config FPGA No meaning DS16 RED ERR_TEMP FPGA over temperature DS85 DS88 GREEN MCU LEDs No Meaning 15216 08219 GREEN MCU LEDs No Meaning 14DDR2 SODIMMs There are several SODIMM sockets on the DN9000K10 They are numbered DIMMO DIMM5 In general DIMM signals are named DIMM lt n gt _ where lt n gt refers to the DIMM number the signal is connected to So the signal DIMM2 DQO would b
31. One Shot Test Step 1 Select DN8 9000k10 GCLK Mux Dialog The next step is to select the SMA source in the dialog PF C 515326 Synthesizer e ConfigFPGA Divide Clock C ConfigFPGA Single Step Clock C C FPGA15 output Phase 0 Divide Clock divider 2 2 NOTE All divide Step 2 Select SMA Source as the input for your global clock PHO setting is shown here DN9000K10 User Guide www dinigroup com 66 THE REFERENCE DESIGN Hit refresh The clock status labels on the right side of USB Controller should reflect the new setting 4 2 4 Divide Clock The divide clock takes your 515326 output and divides it down by a set value To use the divide clock first set your 515326 to the frequency that you want to divide down Then select ConfigFPGA Divide Clock as the source for G0 G1 G2 and input the desired divide factor 4 2 5 Step Clock You can do a step clock from the Configuration FPGA The register for this is You can toggle the step clock by writing to bit 0 for GO bit 1 for G1 and bit 2 for G2 least significant bits To toggle this clock select the menu option Toggle Step Clock from the Settings Info menu in USB Controller Select the clock you are toggling and then how many times to cycle it 4 2 6 FPGA F15 All global clocks can be fed from FPGA F15 s clock output pins LOP_CC_RS1_2 PHO SYN CK2p 98 PHO S N_CK2n
32. SODIMMs 250MHZ o 64 bit data width 250MHz operation PC2 5300 Addtessing power to support 4GB in each socket DDR2 Verilog VHDL reference design provided no charge DDR2 SODIMM data transfer rate 32GB s Alternate pin compatible memory cards available QDR 55 Mictor RLDRAM SSRAM DDR3 interconnect SDRAM DRAM FLASH and others board level global clock networks GCLK0 GCLK1 GCLK2 o Separate programmable synthesizers for each network o User configurable via Compact Flash or USB o Global clocks networks distributed differentially and balanced o Single step clocking available on each global clock network 3 external differential clock inputs can be multiplexed in to global clock networks via SMA s e Eight 400 pin MEG Array connectors o 96LVDS pairs clocks or 192 single ended 450 2 on all signals with LVDS o Reset o Supplied power rails fused 12 24W max 0 DN9000K10 User Guide www dinigroup com 49 THE REFERENCE DESIGN 5V 10W max 3 3 LOW max o Pin multiplexing to from daughter cards using ISERDES OSERDES and LVDS up to 10x e Fast and Painless FPGA configuration Compact Hash JTAG and or USB o Integrated sanity checks on configuration files o Accelerated configuration readback 4 separate parallel readback busses e Custom base plate standard and optional rackmount chassis o Protection from those drooling engineers Four RS232 ports for embedd
33. USB Cable plugged into the board Note that if you have a chassis plug it into the hole that says USB 3 4 3 Connect Power cable Plug in ATX AC power cable into the back of the chassis Turn on the switch on the front of the chassis Tf you do not have a chassis with your DN9000K10 connect an ATX power supply to P200 P202 Make sure all three headers are connected Turn on the ATX supply A jumper must also be installed across pins 34 of P203 this should be done from the factory If the jumper is not installed the ATX supply will not turn on When the DN9000K10 powers on it automatically loads Xilinx FPGA design files ending with a bit extension found on the Compact Flash card in the Compact Flash slot into the FPGAs using the main txt file as a guide DN9000K10 User Guide www dinigroup com 14 QUICK START GUIDE 3 5 View configuration feedback over RS232 As the DN9000K10 powers on your RS232 terminal will display information about the Configuration process If FPGAs ever fail to configure using the Compact Flash card this is the best place to look for an explanation and for help A typical RS232 power on session is given below Rebooting from FLASH please wait Setting 60 N 01 M 000001000 DONE Setting Gl 01 M 000001000 DONE Setting G2 01 M 000001000 DONE DN9000K10 MCU FLASH BOOT FPGAS STUFFED FO F1 COMPACTFLASH INFO MAKER ID EC DEVICE
34. Using the Design The design s MainBus interface is undocumented The IOs in the LVDS reference design are clocked using the GO clock A clock setting of 300MHz on GO results in data transmission from FPGA to FPGA of 600Mbs per signal pair 13 3 Running the Test In the USB Controller program select Settings gt OneShot Test From the dialog box check the Interconnect Test box The program will automatically load the bit files set the clocks and run the test DN9000K10 User Guide www dinigroup com 149 Chapter 6 Ordering Information 1 Contact Us Request quotes by emailing sales dinigroup com For technical questions email support dinigroup com 2 FPGA Options Any subset of FPGAs can be installed on the DN9000K10 Any unneeded FPGA positions can ship empty to reduce the total price 2 1 FPGAs Select an FPGA part to be supplied in each position 15 Possible selections are NONE LX110 1 2 3 LX220 1 23 LX330 1 2 RECOMMENDED 2 2 CES Parts The DN9000K10 may ship with CES engineering sample parts This is often the case early in the Xilinx product release cycle If your board will ship with CES parts the quote will state the Xilinx part number of each FPGA on your board indicating a CES revision It is important that the user knows that CES parts may have limitations that are not listed in the Virtex 5 datasheet To read about these limitations see the Xilinx website and search for Virtex 5 errata In ge
35. VREF tu abet E 132 22 24 2 eee teet tibi ett 132 22 2 5 Timing and Clocking a IRR s 133 22 2 6 Power and 134 252 7 VECO i QNA RD te 134 22 28 gOhnerallOnu cnc ii tud cata baa ce nes 135 22 2 9 Changing On Board VCCO Bias Voltage essere 135 22 3 ROLLING YOUR OWN 0 0 8 40000 0 000 0 0 136 22 4 FURTHER REFERENCE cccccccccccsssscsssscssssecssssccsssscsssscesssscessscessssesssscessescessesesaess 136 23 5 seen s ens esee eee se eee ene ene ens ens ens ense 136 23 1 THEBOARD IS 000600020 136 23 2 THE FPGAS 0 400000 136 23 3 MY DESIGN DOESN T DO 0 0 04 0000000 137 23 4 THEDCMS 0 00004000 00000000 0000000 3 137 23 5 THE BOARD RESETS RIGHT AFTER I T HIT THE RESET 138 23 6 THE SIGNAL ON MY BOARD IS GOING CRAZY ON MY 138 CHAPTER 5 REFERENCE DESIGN
36. because there are no external termination resistors on the DN9000K10 at the FPGA for most of the clock inputs All global clock networks have a differential test point The positive side of the differential signal is connected to pin 1 square copper pad and the negative side is connected to pin 2 circular copper pad These test points are described in section 5 2 Clock Testpoints DN9000K10 User Guide www dinigroup com 60 THE REFERENCE DESIGN Phase matched output to all 16 FPGAs feedback Phase matched output to all 16 FPGAs Bedback Phase matched output to all 16 FPGAs feedback A diagram of the global clock network is shown above Each of the clock outputs of the clock network is distributed to all FPGAs through a phase matched network DN9000K10 User Guide www dinigroup com 61 THE REFERENCE DESIGN 4 2 1 GO G1 G2 Clocks The GO G1 and G2 clocks are the primary global clock resources for your FPGA design Each of these clocks can be set to a combination of sources including a wide range synthesizer a step clock and an external clock input On the schematic these signals are named PH F P N where is 0 1 or 2 and is the name of the FPGA connected to that signal There are five possible sources for each clock G0 G2 The first is the 515326 programmable synthesizers which generates a constant frequency bounded by 0 125MHz and 550MHz The second is an external SMA input which allows
37. chapter 4 5 1 Daughter Card Local Clocks All FPGAs with adjacent daughter card headers have two bi directional clock pairs attached from the header to the FPGA These may be used for clocking FPGA circuitry or for feeding a clock to the daughter card FPGA Daughter Card Clock Signals F3 DC4_GCAP DC4_GCAN DC5_GCAP DC5_GCAN F7 DC6_GCAP DC6_GCAN F8 DC2_GCAP DC2_GCAN F11 DC7 GCAP 7 GCAN F12 DC3 GCAP GCAN F15 DC8 GCAP DC8 GCAN DC9 GCAP DC9 GCAN These clock inputs have no filtering circuitry and therefore no phase relationship to anything else on the board is guaranteed without using the FPGA s DCM Note that these clocks ate on a 2 5V bank Make sure that any clock you feed the FPGA does not exceed 2 5V Feeding the FPGA a higher voltage signal level will damage the Virtex 5 part 4 5 2 Clock TP Each FPGA is connected to a two pinned test point This test point can be used to input a differential clock from off board Each of these test points has a 100 Ohm resistor installed shorting across the negative and positive signals DN9000K10 User Guide www dinigroup com 71 THE REFERENCE DESIGN TESTPOINT FOR EXTERNAL CLOCK INPUT OUTPUT J30 F2_CLK_TESTPOINT_INOUTp 1 7 3 3 Silkscreen F2 CLKIN gt 90120 0123 U102 3 XCSVLG3OFFI760_1 5 533999 933 FPGA F2 Clock Testpoint The schematic clipping above shows FPGA F2 s test po
38. computer over USB From the settings info menu select One Shot Test Enter in one of the text boxes the path to your user CD where the bit files are kept Unselect DDR and the other test options leaving only Main One Shot Test so that only interconnect is tested 2 1 2 Testing DDR2 Interfaces Tutn on the board and connect it to a windows machine To test the DDR2 interface s configure an FPGA which has a DDR2 interface with the Main reference design Install a DDR2 SODIMM into the socket of the FPGA In USB Controller click the enable USB communication button Then set the global clock networks to the following frequencies G0 100 MHz G1 250 MHz G2 200 MHz The frequency of network G1 determines the DDR2 frequency of operation From the settings info menu select Test DDR In the dialog box select the FPGA which is configured The test will report PASS or FAIL 2 1 3 Testing USB USB can be tested by running the DDR2 test or by configuring FPGAs over USB 2 1 4 Testing Daughtercard Connectors and External Clocks This test requires a test fixture and cannot be performed by the user DN9000K10 User Guide www dinigroup com 140 THE REFERENCE DESIGN 3 Reference Design Types The Reference Design in this chapter refers to the FPGA designs located on the user CD at DA FPGA_Reference_Designs DN9000K10 MainRef DA FPGA_Reference_Designs Programming_Files DN9000K10 Th
39. connections 22 2 3 CC VREF DCI Some of the signals connected to the daughter card expansion headers are clock capable the inputs on the Virtex 5 FPGA can be used for source synchronous clocking In the schematic and customer netlist on the user CD these pins contain in the pin name Pins declared in the above diagram that are underlined are connected to pins on the Virtex 5 FPGA These FPGA pins are used to supply a voltage reference used as the threshold voltage for the signals on that bank The use of these pins is only necessary when using threshold standatds such as SSTL DCI is used on all FPGA IO banks connected to a daughter card header The reference tesistance is 50 Ohms Each Virtex 5 bank that is connected to a header DCI in enabled 22 2 4 Global clocks The daughter card pin out defines 6 clock output pins These clock outputs are intended to be used a three differential signal pairs LVDS Two clock signals GCA and GCB connect to the DN9000K10 User Guide www dinigroup com 132 THE REFERENCE DESIGN clock inputs on the FPGA These clocks be used only by the FPGA that is associated with the header The GCC signal driven from each FPGA connects to a global clock buffer and can be used by all of the FPGAs on the DN9000K10 See section 4 4 of this chapter for details on GCC implementation and distribution Note that the GCC pin for DC10 FPGA F16 does not go to a global cloc
40. cover flange bottoms on the front face of the plug Like mating a connector pair can be unmated by pulling them straight apart However it requires less effort to un mate if the force is originated from one of the slot key ends of the assembly Reverse procedure from mating Mating or un mating of the connector by rolling in a direction perpendicular to alignment slots keys may cause damage to the terminal contacts and is not recommended 22 2 Daughter Card Electrical The daughter card pins out and routing were designed to allow use of the Virtex 5 s 1 Gbps general purpose IO All signals on the DN9000K10 are all routed as differential 50 Ohm DN9000K10 User Guide www dinigroup com 128 THE REFERENCE DESIGN signal to ground transmission lines Signals can be used as single ended also Proper electrical levels are explained in the VCCO section No length matching is done on the PCB for daughter card signals except between two ends of a differential pair However the Virtex 5 is capable of variable delay input or output using the built in IDELAY or ODELAY modules A signal delay report is available A signal delay table in ps and taps assuming calibration at 200 2 is available on request Contact support dinigroup com 22 2 1 Pin assignments The pin out of the DN9000K10 expansion system was designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 5 The ground to signal ratio of the conn
41. expansion board This selection was made to give a greater height selection to the daughter card designer 22 1 1 Daughter Card Locations and Mounting The 400 pin daughtercard headers are located on the bottom solder side of the board Each MEG Array header on a Dini Group product has at least four standard position mountain holes See dn9k10_daughtercard_dimensions vsd ot dn9 amp 10 daughtercard dimensions bdfit you do not have Microsoft Visio for a description of the daughter card mounting locations on the DN9000K10 The mounting holes are designed to be used with 14mm M3 standoffs Dini Group has available appropriate mounting hardware on request Standoffs Male to Female Dini Part 1789 Harwin R30 3001402 Mouser 855 R30 3001402 M3 x 14mm HEX 5mmA F Harwin Metric Spacers RoHS Compliant Box 100 Big Round Nuts Part 1787 LMI HN4600300 M3 x 0 5mm Screws Dini Part 1788 MPMS 003 0005 PH Digi key H742 ND SCREW MACHINE METRIC PH M3x5MM DN9000K10 User Guide www dinigroup com 126 THE REFERENCE DESIGN With this host plate daughter card arrangement there is a limited Z dimension clearance for backside components on the daughter card This dimension is determined by the daughter card designer s part selection for the MEG Array receptacle Note that the components on the topside of the daughter card and DN9000K10 face in opposite directions 22 1 2 Insertion and removal Due to the small dimensions
42. find an incompatible card we will attempt to add software support for it 3 4 3 External Compact Flash The external compact flash reader mounted inside the chassis should work identically to the internal one The options for main txt are identical 3 5 Configuration Registers The configuration control on the DN9000K10 is controlled by setting configuration registers Basically these are just locations in the memory space of the on board micro controller that controls the board s function A full description of the function of this micro controller is omitted but some of the registers in this space are required to be accessed over USB to control the board For information on how to access this address space over USB see the corresponding section in this chapter REGISTER IADDRESS FUNCTION FPGA_RESET IDF 22 Write 0x2 to hold reset 0 0 to release G0 INTEGER IDFCO 1 Sets the integer value of the frequency 2 bytes G0 FRACTIONAL IDFC2 3 Sets the fractional value of the frequency 2 bytes G1 INTEGER DFC4 5 Sets the integer value of the frequency 2 bytes G1 FRACTIONAL IDFC6 7 Sets the fractional value of the frequency 2 bytes G2 INTEGER IDFC8 9 Sets the integer value of the frequency 2 bytes G2 FRACTIONAL DFCA B Sets the fractional value of the frequency 2 bytes PENDING_CLOCKS IDF 40 When high each bit causes the configuration circuit to update the represented clock frequency with the cu
43. is controlled by the LED value register 9 RS232 Signals In the RS232 register Bits 2 0 ate mapped to RS232 C A TX Outputs Bits 10 8 are mapped to RS232 C A TX Outputs Enables Bits 18 16 are mapped to RS232 C A RX Inputs 10 SPI Flash In the SPI Flash Register Bit 0 is mapped to FLASH CLK Bit 1 is mapped to FLASH_CSn Bit 2 is mapped to FLASH_DIN Bit 3 is mapped to FLASH_DOUT Bit 4 is mapped to FLASH_WPn See the SPI Flash section of Chapter 4 section 17 for more details on the SPI flash interface 11Simulating the Reference Design The simulation environment the Dini Group uses is ModelSim A ModelSim project file is provided but it may not be compatible with your version of ModelSim When you create a ModelSim project add only the top level design file sim single v Soutce can be found on the user CD DA FPGA_Reference_Designs DN9000K10 MainTest source Also you must add to the project a simulation library Simulation models of all of the primitives used in the reference design are found in the Xilinx ISE install directory in the unisims directory Simulation models are also provided of the DN9000K10 as a whole board along with DDR2 modules headers and the MainBus interface DN9000K10 User Guide www dinigroup com 146 THE REFERENCE DESIGN 12Compiling the Reference Design The MainTest reference design for which bit files are included on the user CD and the provided Compact Flash card can be found
44. lis GND R 232 2 SHONN 24 C855 0 tuF CPUMP54 1 23 1 4 e 5 856 0 tuF 6 NPUMP24 2 e MAX3388E TSOP24 zer RS232 shown at transceiver side 6 Scan the JTAG chain Silkscreen RS232 3 FPGA C3621 C3620 per User l RS232 P208 CONIDA 103310 10 Silkscreen RS232 4 1 2 3 4 5 5 8 9 10 gt P209 CONIDA C3188 C3187 MOLEX 71348 1003 F JOA Silkscreen RS232_5 If you wish you can program the FPGAs using their JTAG interface Connect a Xilinx Platform USB cable into one of the FPGA JTAG port J20 or J202 and open the IMPACT program that is installed with Xilinx ISE 9 2 DN9000K10 User Guide www dinigroup com 24 QUICK START GUIDE Pow Gale v ies nurg i 8 iiu f T 5 FETI 94 Y9d4 913000 Figure 9 FPGA Jtag header is in Red circled 25 inigroup com www d DN9000K10 User Guide QUICK START GUIDE When you connect the Platform USB cable for the first time Windows will automatically install a driver three times in a row like a retarded parrot The program scans the chain to auto detect the type and number of FPGAs installed on your board and displays them on the screen The order of these FPGAs is by increasing number that is the first FPGA in the chain is FO the next will be F1 etc FPGAs not stuffed will not be shown Righ
45. lt filename hex gt aeusb linux cmd exe FLASH lt filename hex gt 4 6 Update Clock frequency tables You should not have to update Clock Frequency Tables unless you erase the entire flash or we provide the new clock frequency tables For now only USBController is able to do the update The two files si5326divider output and si5326init output should be in the same folder as USBController exe Enable service menu please contact us if you don t know how Run USBController exe Put the board under Firmware mode Select Update i5326 Registers value in Flash under Service menu The process should take about 1 2 minutes DN9000K10 User Guide www dinigroup com 46 Chapter 4 Hardware 1 General Overview The DN9000K10 ASIC emulation platform is optimized for providing the maximum amount of interconnect between the Virtex 5 FPGAs It is the highest density off the shelf development board using the Xilinx Virtex 5 FPGA Below is a block diagram of the DN9000K10 DDR2 4GB DDR2 4GB DDR2 46 SODIMM max SODIMM max SODIMM max FPGA FPGA 0 1 Virtex LX 4 96 1196 Oll A O AS L t lt 8 2 o FF1760 FF1760 SODIMM SODIMM max DN9000K10 User Guide www dinigroup com THE REFERENCE DESIGN 1 5V to 43 3V 1 0 1 5V to 3 3V I O CY7C68013 P Configuration controller Virtex 5 LX330 FF1760 1 5V to 43
46. maximum DDR2 interface for the Virtex 5 of 333MHz The DDR2 memory interface can also be used with SRAM Flash and other types of memory modules See the Chapter 6 Ordering Options for a list of compatible memory modules DN9000K10 User Guide www dinigroup com 104 THE REFERENCE DESIGN THE DINI GROUP 1 8V 200 PIN SODIMM gt 2 a MICTOR MODI The interface implementation on these modules is not provided The customer must design the memory interface including timing and clocking 14 5 Test Points Each DDR2 interface has a clock test point This test point is driven from the FPGA thus must be driven manually However it is length matched to the clocks actually going to the DIMM and therefore may be used for checking the phase as well as the frequency of the clocking as it enters your DIMM The test points are listed in the following table DIMM Test Point DIMMO TP11 DIMM1 TP12 DIMM2 TP13 DIMM3 TP74 DIMMA TP75 DIMM5 TP76 DN9000K10 User Guide www dinigroup com 105 THE REFERENCE DESIGN VIRTEX 4 oe JIRTEX S XC5VLX330 XC5VLX330 FFG1TOSFGUDTAS io Frorropredares 15FPGA Interconnect The point to point interconnect on the DN9000K10 is designed to operate at the maximum switching frequency possible on the DN9000K10 The fastest switching standard available on the Virtex 5 FPGA is LVDS Using this standard on the interconnect of a DN900
47. may be disconnected isolating a set of FPGAs from the rest of the board s main bus and decreasing latency MBUS40A and MBUSAOB also connect to the configuration FPGA DN9000K10 User Guide www dinigroup com 108 THE REFERENCE DESIGN MBUS40A 39 0 MBUS40B 39 0 MBUS40A 39 0 MBUSAOB 39 0 TH MBUS40A 39 0 MBUS40A MBUS40B topology DN9000K10 Mainbus Architecture MBUS40C and MBUS40D connect to the two east most columns of FPGAs They do not have any switches and are not connected to the configuration FPGA The implementation of these busses is left completely up to the user DN9000K10 User Guide www dinigroup com 109 THE REFERENCE DESIGN MBUS40D MBUS40C ele dell 16 1 1 Disambiguation The term Main Bus has two meanings In this document it usually refers to the interface connecting the FPGAs to USB via the configuration circuitry It can also mean the group of 36 signals on the DN9000K10 that connects all of the Virtex 5 FPGAs It just so happens that the MainBus interface is implemented using 36 of the MBUS signals In this document MBUS will be used when referring to the signals themselves and Main Bus when referring to the Dini Group defined 36 signal interface description 16 1 2 Electrical The MB signals fixed at a 2 5V signaling level LVCMOS265 is an appropriate singling standard Due to very heavy capacitive loads on the MBUS signals you must use dr
48. o o Builder 7 3 6 2 Using Partitioning and a party synthesis 1OOIS ciuis cesa Road cratis 7 4 EMAIL AND PHONE SUPPORT cccccsccssscssscssscsssssssssssssssssosssossssssssssssossosee 7 CHAPTER 2 QUICK START GUIDE eene reto e nean epe poene 9 1 PROVIDED MATERIALS eese eee eren eene erase ene ens ena ens ens eos eos eas eaa n 9 11 SYSTEM REQUIREMENTS cccccccsssccsssccssssccssscssseecssssscssssscsescesssscssssscssssessascesesenaess 9 EMD P H ec r 10 DN9000K10 User Guide www dinigroup com TABLE OF CONTENTS 2 AES take or enit e demie eet pati lakes 10 2 2 OTHER 10 2 3 OTHER WARNINGS ou 11 3 PRE POWER ON INSTRUCTIONS esoossesoossessossossossoosossoossesoossossossosssssossse 11 21 INSTALL eee ecce eee ee eve eda reed e venena tides 12 3 2 PREPARE CONFIGURATION FILES cccccccssccsssscesssscssssccssscsssescesssccsssscsssscessescesseesnas 13 3 3 INSERT THE COMPACT FLASH CARD INTO THE DN9000K10 S COMPACT FLASH SLOT 13 224 eter dme E eet deca trea tele POTNIT DIEN 13 3 4 1 Connect RS232 Cab l iccecccccccccccccccsscccsssscssscccsssccsssscssssccssscccsscsssssscesseccsssecsesece 13 3 4 2 Connect USB Cable viccccccccccccccccsccccsssccsssscssscccsssccsssccssssscssscccsscs
49. of the very high speed Meg Array connector system the pins on the plug and receptacle of the Meg Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the Meg Array line up BEFORE applying pressure to mate the connectors 7 nM ita Place it down flat then press down gently DN9000K10 User Guide www dinigroup com 127 THE REFERENCE DESIGN The following two excerpts are taken from the FCI application guide for the Meg Array series of connectors A part can be started from either end Locate and match the triangle connector s A1 position marking for both the Plug and Receptacle Markings are located on the long side of the housing Rough alignment is required prior to connector mating as misalignment of gt 0 8mm could damage connector contacts Rough alignment of the connector is achieved through matching the Small alignment slot of the plug housing with the Small alignment key of the receptacle housing and the large alignment slot with the large alignment key Both connector housings have generous lead in around the perimeter and will allow the user to blind mate assemble the connectors Align the two connectors by feel and when the receptacle keys start into the plug slots push down on one end and then move force forward until the receptacle
50. prevent shorting the 1 8V supply to a different voltage These jumpers are located in the corner of each SODIMM socket Example Board comes with jumper installed in positions 24 from the factory This connects 1 8V_0 to You wants to use 1 5V_0 on your SODIMM First remove the factory jumper from positions 24 leaving connector empty Then install a jumper in 1 3 shorting 1 5V_0 to DIMM_PWRO Note There is an over voltage and an under voltage LEED on each DIMM Make sure it is not lit if you are using a standard DDR2 SODIMM For the reference designators of these LEDs see section 13 4 Warning Be careful when performing this procedure An incorrectly placed jumper or a stray piece of solder could short two power rails together and damage all sorts of things on your board including the FPGAs This procedure should only be done by users qualified for soldering through hole parts Warning When connecting the DN9000K10 to any external device make sure the device does not impress a signal level greater than VCCO on your FPGA banks Failure to do so may result in permanent damage to your board For example if you are running your SODIMM interface at 1 8 V you may not connect it to any device signaling at a level greater than 1 8V 15 Place DIMM PUR selection jumper and bulk capacitor near DIMM Silkscreen DIMM PWRO SEL 1 3 1 5 2 4 1 8V 3 5 2 5V 4 6 3 3V Tllustration of a voltage sele
51. the selected FPGA This resets the FPGA and clears any configuration data it may already have This Vendor request also selects the FPGA so that SelectMap bus activity only affects the selected FPGA Bulk transfers initiated after this command to endpoint 2 are interpreted as SelectMap transfers rather than Main Bus transfers See Main Bus access above This will be so until vendor request SETUP END 0xBD is called 4 USB host software sends a bulk write USB request to EP2 Each byte of data in the bulk write is sent to the selected FPGA over the SelectMap bus and the FPGA signal CCLK is pulsed once for each byte of data sent Note that the LSBit in the USB transaction is sent to the LSBit in the SelectMap interface so bit swapping as described in the Virtex 5 Configuration Guide is not required A standard bit file from Xilinx bitgen can be transferred in binary over this USB interface to correctly configure an FPGA on the DN9000K10 Make sure CCLK is selected as the startup clock in the bitgen settings This is the default setting 5 After an FPGA configures the DONE signal will go high lighting the blue LED next to the FPGA labeled DONE 6 The USB Controller sends a vendor request out VR SETUP END This request deselects the FPGA so that further bulk requests are interpreted as Main Bus transactions 6 4 1 Readback Readback is performed in the same way that configuration except that the direction of the bulk t
52. to the configuration FPGA Its function is defined by the Dini Group and is not user definable If you need access to this header contact Support DN9000K10 User Guide www dinigroup com 125 THE REFERENCE DESIGN The daughter card interface includes a 400 pin MEG Array connector made by FCI The daughter card header is arranged into three Banks correlating to the banks of IO on the Virtex 5 FPGA Each of these banks connects to one or more IO Banks on the Virtex 5 FPGA This allows three different sets of voltage or timing requirements to be met on a single daughter card simultaneously Each Bank on the daughter card is 62 signals Other connections on the daughter card connector system include three dedicated differential clock connections for inputting global clocks from an external source power connections bank VCCO powet a buffered powet on reset signal 22 1 Daughter Card Physical The connectors used in the expansion system ate FCI MEG Array 400 pin plug 6mm part number 84520 102 This connector is capable of as much as 10Gbs transmission rates using differential signaling All daughter card expansion headers on the DN9000K10 are located on the bottom side of the PWB This is done to eliminate the need for resolving board to board clearance issues assuming the daughter card uses no large components on the backside The Plug of the system is located on the DN9000K10 and the receptacle is located on the
53. want to use reference design features MCU FLASH VERSION 0x23 35 9000k10 Board Serial Number 0712083 Figure 6 USB Controller Window This window will appear showing the current state of the DN9000K10 Ifa FPGA configured next to each FPGA a blue light will appear 4 2 1 Configure an FPGA Even though the reference design should already be loaded because you had a Compact Flash card installed when the board powered on let s configure an FPGA over USB Clear an FPGA of its configuration right click on an FPGA and selecting from the popup menu Clear FPGA The blue light above the FPGA on the GUI and on the board should turn off To re configure that FPGA using the USB Controller program right click on the FPGA and select Configure FPGA via USB from the popup menu The program will open a dialog box for you to select the configuration file to use for configuration Browse to the provided user s CD D FPGA_Reference_Designs Programming_Files DN9I000K10 Main Test LX330 fpea_f0 bit If you ate configuring an LX220 or LX110 device you should select a bit file from the LX220 or LX110 directories instead Failing to select the correct type of bit file will result in the USB DN9000K10 User Guide www dinigroup com 20 QUICK START GUIDE Controller program warning you and the FPGA fail to configure The program will report the status of the configuration when it finishes When a bitfile for a different size type of F
54. 0 FPGA fan F1 0 000RPM 0x00000000 0x00000000 FPGA fan F2 0 000RPM 0x00000000 0x00000000 FPGA fan F3 0 000RPM 0x00000000 0x00000000 FPGA fan F4 0 000RPM 0x00000000 0x00000000 FPGA fan F5 0 000RPM 0x00000000 0x00000000 FPGA fan F6 0 000RPM 0x00000000 0x00000000 FPGA fan F7 0 000RPM 0x00000000 0x00000000 FPGA fan F8 0 000RPM 0x00000000 0x00000000 FPGA fan F9 5815 230RPM 0x0000095c 0x00000971 FPGA fan F10 0 000RPM 0x00000000 0x00000000 FPGA fan 11 0 000RPM 0x00000000 0x00000000 FPGA fan F12 0 000RPM 0x00000000 0x00000000 FPGA fan F13 0 000RPM 0x00000000 0x00000000 FPGA fan F14 0 000RPM 0x00000000 0x00000000 FPGA fan 15 5815 230RPM 0x00000428 0 0000043 DN9000K10 User Guide www dinigroup com THE REFERENCE DESIGN FPGA fan 16 0 000RPM 0x00000000 0x00000000 Chassis fanl 0 000RPM 0x00000000 0x00000000 Chassis fan2 0 000RPM 0x00000000 0x00000000 Where fan speed is given in RPMs Fans that are not installed will have 0 displayed for speed as in this case only F9 and F15 have fans on this board 20Connectors This section provides a list of all connectors on the DN9000K10 Items considered test points including the clock TP points are listed in the test point section 20 1 FPGA User Interface Connectors The following connectors are directly connected to the FPGA and the user needs to know the interface requirements in detail
55. 0 are shared A monolithic ground design strategy was used The nets GND_SHIELD and GND_ANALOG ate directly connected to the ground plane DN9000K10 User Guide www dinigroup com 117 THE REFERENCE DESIGN 19 8 Power Connections The primary source of power for the DN9000K10 are the ATX power connector From is source the DN9000K10 draws current at 3 3V 5 0V and most of all at 12 0V All other voltages on the board are generated VIRTEX 5 XC5VLX330 T1117 This connector will work with a standard ATX power supply Any supply rated above 500W is likely to be suitable for use with the DN9000K10 Some budget power supplies do not regulate 5 0V and 12 0V to within the margin required by the DN9000K10 If the 5 0V power rail drops below 4 0V or the 12V drops below 10 64V then the DN9000K10 will automatically reset Ifyou DN9000K10 User Guide www dinigroup com 118 THE REFERENCE DESIGN experience intermittent resets and are operating with the board outside of a chassis check that your power supply is regulating the output voltages effectively An auxiliary power connector is provided and is highly recommended for use on fully populated boards It connects to the standard 12V auxiliary power connector of an ATX power supply 19 9 Power Monitors The DN9000K10 monitors the voltage levels on the board to ensure they ate within tolerance If they fall out of tolerance below voltage the boar
56. 0000 MHz 3 176 100000 MHz 3 176 840000 MHz 3 184 320000 MHz 4 195 312500 MHz 3 311 010000 MHz 3 DN9000K10 User Guide 5613 3611 2303 2549 2303 383 14111 190485 3735 6085 2303 383 269 31249 15871 2303 2303 3909 383 605 1133 403 6749 383 575 383 383 575 26665 575 9765 509 485 10741 50353 1173 33325 333333 6399 92961 2157 11557 1173 8841 671 6249 2961 249 124 124 87 124 14 624 09 OO 4 OO 119 124 14 11 767 624 124 124 95 14 31 49 19 363 14 24 14 14 24 479 24 374 11 24 199 1874 39 639 2 2 frre as gt UO U OO 4 590 FR OO DH 3999 39 399 39 299 24 191 99 4 gt gt gt gt gt gt gt 09 amp 9 UW 02 09 09 amp WH 59 W C9 SO AI www dinigroup com 64 THE REFERENCE DESIGN 4 2 3 Feeding a Global Clock from an External Clock Source It is possible to source a global clock from an external source This can be accomplished via the SMAs connected to the global clock muxes J89 J90 for GO J94 J95 for G1 and J99 J106 for G2 The SMA clock must then be selected as the source for the global clock mux an operation that may be done through the USB interface or via the main txt configuration file on the
57. 0K10 we have demonstrated switching frequencies as high as 950Mbs A block diagram of the point to point interconnect is given in supporting document DN9000K1 Oblock png The diagram is only valid when the board is installed with LX330 FPGAs the largest available size When any LX220 or LX110 FPGAs are installed the amount of interconnect available between FPGAs drops See the diagram in Chapter 6 Section 2 3 for details on what is lost Each FPGA to FPGA interconnect signal is tested at 900Mbs prior to shipping no matter which speed grade is installed on your board Higher speeds are possible given appropriate IO timing methodology and speed grade parts The theoretical limitation imposed by the DN9000K10 is 1 1Gbs the limit of the Virtex 5 s internal clock network Dini group has demonstrated speeds up to 0 90Gbs on each pair of interconnect signals Information on how to achieve this interconnect switching speed can be obtained by examining the Xilinx application note XAPP855 Other methods of implanting high bandwidth interconnect are described in 860 The Dini Group reference design uses an older method designed for Virtex 4 In a synchronous system between two FPGAs and a DCM in zero delay mode the following timing is possible DN9000K10 User Guide www dinigroup com 106 THE REFERENCE DESIGN Clock to Out 3 37 ns Trace Delay 1 70 ns Rise time adjustment 0 30 ns Clock skew 0 20 ns duty cycle 0 05 ns jitter 0 05 n
58. 1 Added Device xc5vlx330 successfully PROGRESS END End Operation Elapsed time sec BATCH CMD identifyMPM Configuration Platform Cable USB 6 MHz 1 usb hs Z What you will see when you look at the FPGA JTAG This is on a fully stuffed board partial stuffs will have some FPGAs missing DN9000K10 User Guide www dinigroup com 27 QUICK START GUIDE 6 1 Moving On Congratulations You have just programmed the DN9000K10 and learned all of the features that you have to know to start your emulation project If you are new to Xilinx FPGA you might want start by compiling the reference design and adding code to the reference design until you are comfortable with the design flow You should also use the provided UCF constraint file as a starting point for your UCF file DN9000K10 User Guide www dinigroup com 28 Chapter 3 Controller Software The DN9000K10 can be hosted from USB As an example to hosting using this interface the Dini Group provides some controller software that allows configuring FPGAs and changing the board settings For more complex host behavior such as interactively transferring data to and from the board from the host computer you may have to develop your own host software At the end of this chapter there is a programmer s guide to help you interface to the DN9000K10 This along with the source code of the example software should be able to get you communicating with the DN9000K10 T
59. 2 6 Power and Reset The 3 3V 5 0V and 12V power rails are supplied to the Daughter card headers Each pin on the MEG Array connector is rated to tolerate of current without thermal overload Most of the power available to daughter cards through the connector comes from the two 12V pins for a total of 24W Each power rail supplied to the Daughter card is fused with a reset able switch Daughter catds are required to provide their own power supply bypassing and onrush current limiting L1 acap HE GCAP 104 2 GCAN DCO_GCAN 104 GCBP DCO_GCBP 104 GCBN DC0 GCBN 104 GCCP DCO_GCCP 85 7 GCCN DC0 GCCN 85 RSTn Section 1 of 5 Clock Power Reset 1A PER PIN DCO RSTn 74LVC1G07 MEG Array 300 P in SOT95P280 5N iz The RSTn signal to the daughter card is an open drain buffered copy of the SYS_RST signal It is also asserted when the User Reset is active When RSTn is de asserted the 3 3V 5 0V and 12V power rails are guaranteed to be within the DN9000K10 tolerance If there are additional power requirements the daughter card is required to ensure these 22 2 7 VCCO Voltage The daughter card is required to provide a voltage on the VCCO pin on the connector This voltage is used on the DN9000K10 to power the FPGA IOs that are connected with that daughter catd In this way the daughter card can control what voltage the interface will use Each bank of the connector BO B1 or B2 uses a sep
60. 27P600 8N R467 10 380mA MAX AT 1 22V The output voltage of this regulator can be adjusted if needed This will require changing the resistors on the ADJ pin of the regulators The bias regulators can provide up to 1 5A of current Some low speed designs may not need more than this Dini Group recommends placing the IO voltage regulators on the daughtercards because this does not require modification of the DN9000K10 22 2 9 Changing On Board VCCO Bias Voltage It is possible to change the VCCO bias voltage to a different setting This involves changing the trim resistors Alternately you can short the VCCO bias voltage to 2 5V or 3 3V directly Note Most applications do not require this as the daughter card provides the VCCO voltage for both itself and the FPGA DN9000K10 User Guide www dinigroup com 135 THE REFERENCE DESIGN We do not recommend doing this without assistance Contact suppor dinigroup com for instructions on doing this 22 3 Rolling your own daughtercard Small quantities of the connectors required for building a daughtercard can be obtained at cost from the Dini Group If you need help designing a daughtercard we will be happy to review your schematic for errors as well as reviewing your desired footprint for compatibility Contact Support to arrange this We also do design custom daughter cards for user specific applications The pricing and lead time is per case and depends on the complexity of t
61. 3V 1 0 1 5V to 3 3V I O 780 TT LN SRAM 128Kb x 8 Flash 1 8 Config FPGA LX80 FF1148 1 5V to 3 3V I O PLL Clock nthesizers 1 5V to 3 3V I O DN9000K10 User Guide 1 5V to 3 3V I O lt GCLKO K1 GCLK2 He Ext Clock SMA s 1 Reference Clock 7 58442 1 www dinigroup com 48 THE REFERENCE DESIGN 1 1 Marketing The following is the advertised feature list of this board This manual is responsible for providing the information necessary to use these features 1 1 1 Features e USB2 0 hosted logic prototyping system with Two to Sixteen Xilinx Virtex 5 FPGA s o 16 LX330 s FF1760 e 100 FPGA resources available for user application e 32M ASIC gates LSI measure with 16 LX330 s FPGA to FPGA interconnect is single ended or LVDS o 450MHz differential chip to chip DDR 900Mb s o Reference designs for integrated I O pad ISERDES OSERDES o 10x pin multiplexing per LVDS pair o Greatly simplified logic partitioning o Source synchronous clocking for LVDS e Main Busses for global connectivity o Main Bus Horizontal MBH all FPGAs 80 single ended signals o Bus Vertical MBV right two columns of FPGAs 80 single ended signals Auspy AES models for partitioning assistance o And hooks for other third party partitioning solutions e 6 separate DDR2
62. 7 RS232 2 RX to FPGA AK30 RS232 3 TX from FPGA AJ30 RS232 3 RX to FPGA AK14 RS232_4 TX from FPGA AK15 RS232_4 RX to FPGA RS232_5 is connected and muxed through the configuration FPGA The TX and RX signals use the RS232 data protocol so the FPGA will have to implement a UART in its logic All FPGA share the same RX and TX signals so only one FPGA should use the interface at a time RS232 requires 12V to 12V signaling level which is not available on VirtexS FPGAs so an external RS232 transceiver is used See page 56 of the schematic for details DN9000K10 User Guide www dinigroup com 91 THE REFERENCE DESIGN RS232 ports outlined in red One the board pin 1 is marked with a arrow molded into the side of the connector On the provided cable pin one is marked with a red stripe on the cable Hot plugging this connector is acceptable and encouraged The port settings required on the serial port of your computer are dependent on the UART in the FPGA Since the flow control signals on the serial cable are not connected to the FPGA you cannot use hardware handshaking The other port settings parity stop bits speed and data bits are user design dependent 10 1 1 Configuration RS232 RS232 header P204 is for the configuration circuitry to give feedback to the user It is described in the section Configuration Section DN9000K10 User Guide www dinigroup com 92 THE REFERENCE DESIGN 11Temperat
63. 8 9000K10 DC Clock Setup from the Settings Info menu You will see the following dialog DN3000K10 GCLK Configuration DCGCLKO Header 4 F3 C Header 2 F8 DCGCLKO Input Frequency Mhz Header 9 15 DCGCLK1 Header 3 12 DCGCLK1 Input Frequency Mhz Header 5 DCGCLK2 Header 6 DCGCLK2 Input Frequency Mhz DCGCLK3 C Header 7 F11 C Header 8 15 DCGCLK3 Input Frequency Mhz Cancel Select for each item the header you want to source DC GCLK from see diagram above for clarification Also input the frequency you are running so that the PLLs in the network may be set to wotk at that frequency If you don t care about the phase of the clocks going to the FPGAs you can put 0 which will disable the PLLs in the distribution network Note that putting down a frequency will NOT cause the networks to output that frequency It only calibrates the PLLs to accept that frequency an external clock source still must be provided DN9000K10 User Guide www dinigroup com 70 THE REFERENCE DESIGN 4 5 Non Global Clocks The following sections describe clocks that are not considered global because they do not distribute to both FPGAs on the board These clocks may be used for specific interfaces and details on the clocking required for those interfaces are found in a different section in the hardware
64. 9 daughter ard 191 Mri 22 2 mE L3 2 MBUS SM 32 49 8 MBUS 31 49 DATA bus is used to either MBUS SM 30 49 3 1 Configure the slave board from MBUS SM 29 49 the host also uses control signals nA MBUS SM 28 49 4 on pins ft 4 10 12 14 nz MBUS SM 27 48 S MBUS SM 26 40 8 2 Configure the host board from the DATA M ae slave daughtercard also uses CON DATAO MBUS SM24 49 bus MICTOR_CLK_E T 44 40 42 41 2 767004 2 CONN MICTOR38 Schematic clipping of Select MAP Mictor interface If you want to use this Mictor interface for logic debugging or any other non specified purpose and need access to the signals connected to it contact Support 19Power The power used on the DN9000K10 is provided through the ATX connector 12V 5 0V and 3 3V are all used by this board Other power supplies are generated on board with either switching or linear regulators DN9000K10 User Guide www dinigroup com 116 THE REFERENCE DESIGN The DN9000K10 standard chassis comes with a built in 600W server grade power supply While theoretically the DN9000K10 can draw more than this amount of power the included power supply has proven sufficient for meeting the needs of our customets 19 1 Power 12 0V The 12 0V rail is used to generate most other voltages on the board The maximum possible draw on 12 0V is 100A 1200W This rate of dissipation would overload almost any
65. A O filename FPGA 1 filename FPGA 2 filename FPGA 3 filename 5326 PHO CLOCK FREQUENCY number MHz 5326 PH1 CLOCK FREQUENCY number MHz 5326 PH2 CLOCK FREQUENCY number MHz GCLKO SELECT 5326 GCLK1 SELECT 5326 GCLK2 SELECT DIV SANITY CHECK lt y n gt VERBOSE LEVEL lt level gt MEMORY MAPPED 0x lt SHORTADDR gt 0x lt BYTE gt SOURCE GO 2 DCGCLKO SELECT DC2 100MHZ MAIN BUS 0x lt WORDADDR gt 0x lt WORDDATA gt lt comment gt can be any string of characters except for newline lt filename gt can be the name of a file on the root directory of the Compact Flash Card lt number gt can be any positive number in decimal Decimal points are allowed lt y n gt can be the letter y or the letter n lt level gt can be 0 1 2 or 3 recommended 2 lt SHORTADDR gt is 2 digit number in hexadecimal 16 bits lt BYTE gt is a 1 digit number in hexadecimal 8 bits lt WORDADDR gt 4 digit 32 bit number in hexadecimal representing a main bus address DN9000K10 User Guide www dinigroup com 55 THE REFERENCE DESIGN WORDDATA 4 digit 32 bit number in hexadecimal containing data for a main bus transaction The following table describes the function of each of the available main txt commands Instruction Function comment The configuration circuitry performs no operation and moves to the next command VERBOSE LEVEL This command will set the amount of o
66. ATX power supply and will probably never be seen except in a pathological case However a fully populated board could reasonably draw 300 500W depending on logic and IO utilization Note It is recommended to use a server grade 500W ATX power supply for the DN9000K10 This is especially important for fully stuffed boards running power intensive designs 19 2 Power 5 0V The only place that 5 0V power is used is for driving fans some LEDs and driving main bus switches So it would be unlikely to see more than a few amps of power draw on 5 0V 19 3 Power 3 3V 3 3V is used by the DN9000K10 to supply the clock distribution network the configuration logic Micro controller and Virtex 4 Configuration FPGA and daughter card power 3 3V is taken directly from the power supply The amount of current required should be within the range of most regular ATX power supplies 19 4 Power 2 5V 2 5V power is generated from the 12 0V using a 30A power supply Every four FPGAs by quadrant have their own 2 5V power supply 19 5 Power 1 0V 1 0V power is generated from the 12 0V using a 30A power supply Every FPGA has its own 1 0V power supply 19 6 Other Power Supplies 1 8V and 1 5V power is generated with a 30A power supply 2 power supplies per rail Most other power supplies are generated with linear regulators These typically have low current draw requirements 19 7 Ground All ground OV voltages on the DN9000K1
67. Dm _ Group LOGIC Emulation 000000 User Manual DN9OOOK10 DN9000K10 User Manual Major Revision 1 Last Update April 13 2009 7469 Draper Ave La Jolla CA92037 USA Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com DN9000K10 User Guide www dinigroup com O Table of Contents 0 TABLE OF en s ens ens enses e eee eee eee ene ens ens ense 3 CHAPTER 1 INTRODUCTION eeeeeee eee een seen sens ens ens eae e eee eee ene ene ens ens eaae 1 1 MANUAL CONTEN IS so cE e ce poa eoa ep aea nae aor n 1 11 040 00000 0000 1 I QUCKSTART GUIDBE sae a ngo pA 1 13 CONTROLLER SOFTWARE Q cccccccsseccsssscssscccsssccsscecessssessssscseecesssscessssessssessascessevenaase 2 14 HARDWARE eee eee eo Eee Ede eel 2 15 THE REFERENCE DESIGN eene 2 1 6 ORDERING INFORMATION 000040000 00 2 2 GL OVPADMMN LOC 2 2 1 2 000000 2 2 2 MANUAL CONTENT cccccccccccsscccssccssscscssssccssscsssescesssccsssssesascessescssssccssscesssscessesensese 2 227 UE Imesca v
68. ERENCE DESIGN TPT3 1 0 14 1 0V TP77 140V 15 1 0V TP78 2 5V_2 2 5V TP79 DC9 B1 VCCO 1 22V TP80 DC9 B0 VCCO 1 22V 1 8V_1 1 8V TP82 DIMM_PWR3 1 8V TP83 DIMM_VTT3 0 9V TP84 DIMM PWR4 1 8V TP85 DIMM_VTT4 0 9V TP86 DIMM_PWR5 1 8V TP87 DIMM_VTT5 0 9V TP88 12 0 12 Note 1 Daughter card power supplies 1 221 nominal are bias only When you attach a daughter card to any of these connectors the VCCO power supplies will register a higher voltage matching that of what is generated on the daughter card Note 2 In general nominal voltages are given on a naked board with only power connections plugged in These test points are suitable for wiring to if power is needed off board for some reason Or maybe if you need to bring power in from an external source 5 2 Clock Test points Each of the Global clock networks has a test point These points are not length matched with the global clock network so there may be some phase offset between this point and the FPGA input gt gt i C5VLX330 XC5VLX330 4 XC5 61760FGU0745 212502510245 seem 21478549A TAIWAN Test Point FPGA F5 uai rte e chil mh ni sith FFL FPGA All of test points output LVDS signaling P N polarity is given in the table below DN9000K10 User Guide www dinigroup com 78 THE REFERENCE DESIGN
69. F2 U13 F12 U91 F13 U117 F14 U99 If you wish to use your own design and access the SPI lines directly use the following pins same on all FPGAs Signal Pin Signal Desciption FLASH HOLDn R28 Pause serial communication without de selection of device active low FLASH_CSn R27 Chip select active low FLASH WPn M13 Write protect active low FLASH DIN N13 Flash Serial Data In output from FPGA input to Flash FLASH CLK P27 Flash Serial Clock FLASH DOUT P26 Flash Serial Data Out output from Flash input to FPGA Note For complete pin descriptions see the datasheet for the ST Microelectronics M25P128 Flash Chip The flash chip used on the board is the ST Microelectronics M25P128 This SPI flash can operate from 0 to 20MHz and up to 50MHz for some instructions notably FAST_READ There are only a few user controlled signals so writing a controller for this chip is easy A reference design capable of accessing the flash chip is provided This design does not include a controller it simply gives register access to the control lines Implementation of controller functionality is left up to the software The following is a memory map of the flash control lines as accessed through the main bus Signal Register FLASH CLK 0x 800007B bit 0 FLASH CSN 0x 800007B bit 1 FLASH DIN 0x 800007B bit 2 FLASH DOUT 0x 800007B bit 3 DN9000K10 User Guide www dinigrou
70. Flashs Read SPI Flashs Clear Log Scroll Log BOARD TYPE DN9000k10 USB to FPG communication is disabled Enable if you want to use reference design features USB to fpga communication enabled DN9000K10 User Guide www dinigroup com 115 THE REFERENCE DESIGN You will be given the option to erase the flash before programming Afterwards select the binary file must have extension bit to program into your flash chip and the offset at which to start programming in DWORDs You will also be given the option to verify afterwards To read the SPI flash chips select Read SPI Flashs You can select the starting offset measured DWORDs and the number of DWORDs to read The program will then inconveniently print the output to the log window instead of to a file like you wanted 18 SelectMAP Mictor Connector There is one Mictor connector on the DN9000K10 While it could in theory be used for logic analysis it is connected to the Virtex 4 Configuration FPGA only and is intended for use in configuring a daughter board or having a daughter board configure on board FPGAs SelectMAP Mictor Interface 53 lt lt Silkscreen SelectMAP Mictor J203 1 Do Not ME FPGA F17 15 50 3 PA 18 MICTOR CLK E 4o M 48 53 a DON CON bus provides control FPGA F1 CCLK 53 signals when configuring the FPGA F17 PROGn 53 host board from the slave MBUS SM 35 4
71. Group design exercises and provides examples for are e Access to the DDR2 SDRAM Modules at 250MHz e FPGA Configuration interfaces over USB JTAG and Compact Flash RS232 Communication e FPGA Interconnect at high speed techniques e MainBus interface for USB communication Blink LEDs in cool patterns e Reset Button e New internal Virtex 5 features PLL ODELAY 550MHz clocking 900Mbs IO Set global clocks All source code for the reference design is included on the CD and may be used freely in customer development Precompiled bit files for the FPGA types that are installed on your DN9000K10 User Guide www dinigroup com 139 THE REFERENCE DESIGN board are provided and can be used to verify board functionality before beginning development A build utility described in the section Compiling The Reference Design can be used to generate new bit files or to generate bit files for less common configurations of the DN9000K10 2 Hardware Tests The provided bit files and software is suitable for testing most of the hardware interfaces on your board Some hardware tests require test fixtures these are not provided They can be soutced from Dini Group contact support dinigroup com with your request 2 1 1 Testing FPGA to FPGA interconnect To test the FPGA interconnect you will need to run the One Shot Test This is a feature of the Windows program USBController exe Turn on the board and connect it to a windows
72. H Oed emat ve tabe e rte deseaba tac seduta 103 1433 LOISIR UR 103 14 4 COMPATIBLE MODULES cccccesscccsssccsssecesssccsscccsssscesseecessscessssecssscesssscessssessese 104 TABLE OF CONTENTS 1455 etie eee teeth 105 15 FPGA INTERCONNECT eiiscccccccccssecccscesececesasiccatecsoceascetdcovecesscesscescssdeessceessssecoes 106 16 MAIN BUS 25202220059 108 MIB SIGNAES emt ad 108 7041 Disambiguation stus tow ere cod eese 110 LOD RSS 110 o ek ED MEME ae NODE NEUEN 110 16 2 SWITCHING 111 16 39 JBRROR CODES reete a eae ME co Boek a a 111 164 112 16 4 1 Conventional Memory BID ducks 113 17 114 17 1 SPIFLASH ACCESS THROUGH USB CONTROLLER eene 115 18 SELECTMAP CONNECTOR e eeeeeeeee eene eene een s ens ens ens eos n 116 19 POWER 116 19 1 POWER aane ten rtt erre tette 117 19 2 POWER SOV unnar tete tele dte et e eet ede 117 19 3 POWER 3 3 V iced ete ta rede e tee tra ide tete ee ets 117 192 POWER 2
73. IC RST LEDn Logic Reset has been triggered DS23 RED SYS_RSTn Hard Reset has been triggered DS39 BLUE FPGA_FO_DONE FPGA is configured DS44 BLUE FPGA F1 DONE FPGA F1 is configured DS49 BLUE FPGA F2 DONE FPGA F2 is configured DS54 BLUE F DONE FPGA F3 is configured DS60 BLUE FA DONE FPGA F4 is configured DS65 BLUE FPGA F5 DONE FPGA F5 is configured DS70 BLUE F6 DONE FPGA F6 is configured DS75 BLUE FPGA F7 DONE FPGA F7 is configured DS99 BLUE FPGA F8 DONE FPGA F8 is configured DS104 BLUE FPGA F9 DONE FPGA F9 is configured DS109 BLUE FPGA F10 DONE FPGA F10 is configured DS114 BLUE FPGA F11 DONE FPGA F11 is configured DS119 BLUE 12 DONE FPGA 12 is configured DS124 BLUE F13 DONE FPGA F13 is configured DS129 BLUE F14 DONE FPGA F14 is configured 05134 BLUE FPGA_F15_DONE FPGA F15 is configured 13 2 User LEDs These LEDs are connected to an FPGA and are controller by the user There are four LEDs per FPGA The meaning of the LED is defined by the design loaded Below is the general DN9000K10 User Guide 95 www dinigroup com THE REFERENCE DESIGN circuit used to connect user LEDs To turn the LED on drive the signal low To turn off tri state or drive high See sheets 2 17 of the schematic for an illustration of these LED sub circuits Do not use DCI on LED signals You can control the brightness of LEDs by either using a low drive setting DRIVE 2ma in the ucf file or by ra
74. ID 75 SIZE 32 MB FILES FOUND ON COMPACTFLASH CARD FPGA F1 BIT FPGA 0 MAIN TXT CONFIGURATION FILES FPGA FPGA 0 FPGA Fl FPGA 1 5 Message level set to default 2 Sanity check is set to default ON N 00 M 000001010 DONE Setting GO N 01 M 000001100 DONE Setting Gl 01 000001000 DONE CONFIGURING FPGA FO okckckckckckckck kk Performing Sanity Check on Bit File This line has to do with the firmware update mode The board is setting the global clock frequencies according to the main txt file on the Compact Flash card The messages here ate mostly only useful to whoever programmed the firmware Prints the FPGAs the configuration circuit thinks you have on your boatd Compact Flash card debugging information This lists the files found on the compact flash card If this list is wrong there is something wrong with Compact Flash The MCU reads the contents of the file MAIN TXT and executes each instruction line Here the MCU is setting the clocks according to instructions in MAIN TXT The MCU is configuring FPGA FO according to instructions in DN9000K10 User Guide www dinigroup com 15 QUICK START GUIDE BIT FILE ATTRIBUTES MAIN TXT FILE NAME FPGA 0 FILE SIZE 003A943B bytes PART 5v1x330ff1760 09 38 DATA 2007 07 25 TIME 17 09 38 Sanity check passed Debugging info
75. MCU RS232 provides a great debug interface to the board s configuration section It is also extremely reliable if this interface is not working then it is likely that nothing else is either 3 2 FPGA Configuration Normally configuration of the Virtex 5 FPGA occurs over the Virtex 5 SelectMap interface The only configuration method possible on the DN9000K10 that does not use this interface is JTAG For a description of the SelectMap interface see the Virtex 5 configuration guide Typically the user will supply a bitfile generated by ISE and either put it on a CF card or supply it to software over USB Thus the user does not have to understand the SelectMap interface USB and Compact Flash configuration occur over the SelectMap bus The configuration section makes no modification of the bitstream sent to it over USB It only copies the data to the SelectMap interface The bitstream must contain all of the SelectMap commands necessary to configure and startup the FPGA These SelectMap commands are created automatically by Xilinx tool bitgen part of ISE Not all of the bitstream generation options available in bitgen are compatible with the DN9000K10 Currently before configuring the FPGA using any method except JTAG the configuration section asserts the PROG signal of the FPGA to clear it For this reason the disable SelectMap option in bitgen has no effect On each FPGA the DONE signal is connected to a blue LED located n
76. Most customers who need to use USB as a data interface to their FPGA designs write their own USB controller programs if the USBController and AETEST programs do not meet their requirements 3 1 USB The behavior of the DN9000K10 with regard to the USB interface is given in the Hardware chapter 4 Updating the Firmware Dini Group may release firmware bug fixes or added features for the DN9000K10 If a firmware update is released you will need into download this new code to the firmware of the DN9000K10 There are three firmware files that Dini Group may release EEPROM_FLP tic for EEPROM firmware hex for FLASH and prom flp mcs for Spartan PROM The first firmware update is for EEPROM which stands for Electrically Erasable Programmable Read Only Memory The Firmware Mode is booted from here This firmware is rarely changed Please consult with us before updating this device The second firmware update is Micro Controller MCU software that is stored in a flash memory The User Mode is booted from here This update can be accomplished easily from the USBController or AEtest_USB application The third update that may be required is a Spartan FPGA core update The configuration data for the Spartan FPGA is contained in a Xilinx configuration PROM This update can be accomplished with the Xilinx JTAG programming or iMPACT programs Either the Xilinx Platform cable USB 199 or the Xilinx Parallel cable IV 125 helps updating firmware much faste
77. N9000K10 to enable a configuration register must be written This behavior is intended to protect users who do not want to implement the Main Bus interface as outlined in the Main Bus Specification but who wish to use the MBUS40A 35 0 signals for their own purposes DN9000K10 User Guide www dinigroup com 111 THE REFERENCE DESIGN Note The Main Bus Specification describing the Main Bus interface for generic Dini Group applications can be found at http dinigroup com product common mainbus_spec pdf 16 4 FPGA Interface All memory mapped transactions in the reference design occur over the main bus a 36 bit wide section of MBUS40A This 36 signal bus connects to all Virtex 5 FPGAs and to the Virtex 4 LX80 configuration FPGA The Configuration circuit is the master of the bus All access to the main bus reads and writes is initiated by the LX80 FPGA when the reference design is in use and the main bus is enabled MBCLK 1 MBUS4OA 34 ooo cada dle eiii aigu erai cta erac MBUSAOA SS 2L MBUS40A 31 0 MBUS40A 32 0 to 200 Cycles All transfers a synchronous to the MBCLK clock This clock is fixed at 40M Hz and cannot be changed by the user This clock is LVDS When the configuration circuit asserts the ALE signal the slave device on the bus the FPGA is required to register the data on the AD bus This is the main bus address The next transfer
78. PGA is selected the program will not attempt to configure and will fail the sanity check If you ate configuring FPGA F1 or any other FPGA you should use the respective bitfile Should you configure the wrong FPGA with the wrong bitfile the FPGA will succeed to configure if the FPGA type is the same but probably won t function properly This is not recommended because it could lead to bus contention and excessive heat generation Done FPGA FO cleared successfully FPGA Fl cleared successfully Doing a sanity check Sanity Check passed Configuring FPGA F1 via USB please wait File D dn_BitFiles DN9000K10 MainTest LX330 fpga_fl bit transferred Configured FPGA B via USB Figure 7 USB Controller Log Output The message box below the DN9000K10 graphic should display some information about the configuration process When the configuration is successful the green LED should re appear next to the FPGA 4 2 2 Set Clock Frequencies To change the clock frequencies of GO G1 or G2 select the Clock settings option from the Settings menu A dialog box appears asking to which frequency you would like to set each clock Enter 200 100 100 MHz for GO G1 and G2 respectively 4 2 3 Run Hardware Test DDR2 First hit the USB gt FPGA communication button This must be done before the program can interact with the reference design You must also have the reference design
79. RATION a deest deckt ecce E decuit 84 OP 64 6 5 USB HARDWARE 85 6 5 1 Cypress CY COSOISA iouis uno RI ipae Alaa adden 85 0 02 Activity LED 86 6 5 3 Configuration 86 034 NAE EU A Bi 86 TABLE OF CONTENTS 0 6 TROUBLESHOOTING eet e edd ed feta 86 6 011 USB Controller Freezes UT ced e 86 6 6 2 Main Bus always returns Error Codes esses 87 70 UNUSABLE PINS c 87 Surat 87 7 1 2 Bank 0 Configuration 87 A on Eri ieu EU en TQ P 87 D POWER REESE Me sitio 87 RIES coetus delatae ate d Dm fant ud 88 9 eon TR c rm cr 89 9 gate oS 89 9 1 1 Compatible Configuration Devices ineat ota tutos tpa Dh 90 D TA eos oborta aote 91 ODS amp aa Biss Saas aan aan sate 91 92 FIRMWARE UPDATE HEADER iiec n tee aene veru verse que
80. SB program to update MCU Flash firmware 4 5 1 Using USBController 1 Put the board into Firmware Mode instruction 4 1 2 Run USBController exe Flash Update dialog will appear please select Yes 3 Please select firmware hex we provide you this file DN9000K10 User Guide www dinigroup com 45 CONTROLLER SOFTWARE 4 When finish please recycle power the board or hit Hard Reset S3 on the board to boot from User Mode 4 5 2 Using AETest_USB 1 Put the board into Firmware Mode See 4 1 2 Run aeusb_wdm Select option 3 Firmware Menu 3 Please select option 2 Update Flash from lt firmware gt hex 4 Enter the full path filename It should be firmware hex that we provide you 5 The process will take about 2 minutes When it finishes please hit Hard Reset S3 on the board or recycle power the board so that DN9000k10 can boot from User Mode ASIC Emulator EEPROM Boot Menu v5 Display Flash Version Update EEPROM from lt filename gt iic file Update Flash from lt firmware gt hex file Update 15326 Register values Boot From Flash Main Menu 9 Quit Please select option 2 Please enter filename C DiniWlork dn_conf ig MCU DN 666k16 f irmware hex Transfered 133766 byte Transfered 178648 byte Set serial number to 6712686 Updated Flash Press any key to continue m Figure 16 aeusb_wdm window You can also run this on the commend line aeusb_wdm_cmd exe FLASH
81. SODIMM see the SODIMM datasheet HTFA4C16 32 64x64H paf For general information on using the interface see the specification user manual UM Specpaf 14 3 3 Timing The length matching of the DDR2 interface signals includes all signals except for DIMM_SCL and SDA DN9000K10 User Guide www dinigroup com 103 THE REFERENCE DESIGN The trace impedance to each of the connectors is controlled to 50 ohms All signals in the interface are ground referenced Note that this is contradictory to the recommendations of the DDR2 SODIMM specification To increase the setup time available for control signals modules may be set into T2 mode In the reference design the modules in T1 mode Address Control signals FPGA Assume a DCM in system synchronous mode Worst clock to out time of Virtex 5 3 37 with DCM No phase shift Worst setup time 0 097 Worst hold time 0 21 DIMM setup 600ps hold 600ps DQ signals DIMM DQS must be within 350ps of DQ DM setup 400ps Hold 400ps FPGA IDELAY setup 1 23 hold 2 14 clock to out 5 34 14 4 Compatible Modules The DDR2 interfaces are compatible with standard PC2 2700 or faster memory modules up to a capacity of 4GB The greatest capacity modules available at print time are 2GB The interface has been tested with modules with a CAS latency of 3 The interface is characterized to 250MHz although faster designs may be possible Xilinx is advertising a
82. SPI Configuration SystemA amp CE xcf32p 4 80 fa PROM File Formatter prom_fip mes bypass Available Operations are Operations oundary Scan INFO 1 501 1 Added Device xcf32p successfully PROGRESS END End Operation Elapsed time 1 sec BATCH CMD identifyMPM BATCH CMD assignFile p 1 file C DiniWVork dn config ConfigFPGA DN9000k1 1 Loading file C DiniWVork dn config ConfigFPGA DN9O0D0O0k10 prom flp rmcs done INFO iMPACT 1835 Loading CFI file C DiniWork dn config ConfigFPGA DN9000k10 pron CFI file not found proceed with device default setting BATCH CMD set ttribute position 1 attr packageName value null Configuration Platform Cable USB 6 MHz usb hs Figure 12 Impact Window 7 Move mouse to the first device right click and select Program 8 Check only two boxes Verify and Erase Before Programming Hit 9 It takes about 3 minutes to complete Please recycle power the board after the blue box Program Succeeded appears on the main screen DN9000K10 User Guide www dinigroup com 41 CONTROLLER SOFTWARE GMPAGI Boundary Scan File Edit View Operations Output Debug Window Help Pe SRI 1 280 wiv Scan 319 29 3 Configuration SPI Configuration SystemACE xcf32p
83. Service menu and select Program Update Spartan warning message will appear to ensure that you want to update Spartan If you do hit Yes button Open file Dialog will appear Please select the xsvf file that we provide you After selecting file there will be debug level dialog Please select debug level 0 The process takes about 10 15 minutes please leave the board and USBController alone The process bar is on the bottom of USBController window When the execution is finished power cycle the board 4 3 3 Using AEtest_USB If you do not have a JTAG cable you will need to use the following instructions to update your Spartan PROM firmware This update is depending on AEtest_USB and Flash firmware version Please double check with us support dinigroup com to make sure that your current version MCU version AEtest_USB supports this option and request xsvf file from us 1 2 Run aeusb_wdm exe or aeusb_linux At the main menu please select option 3 FPGA Configuration Menu In Flash Boot Menu please select option 9 Note the option menu is not displayed for security purpose Please enter the full path filename for the xsvf file Verbose level is 0 The higher verbose level the slower the program runs DN9000K10 User Guide www dinigroup com 43 CONTROLLER SOFTWARE C WDiniWork Aetest_USB aetest_usb ae Display Flash Version Check FPGA configuration status Con
84. Silkscreen F12 SMA IN p n 264 2 F12 CLK SMA INOUTnr F12 CLK SMA NOUTA ur 3 R1275 OR 4 Illustration of SMA clock inputs to FPGA F12 DN9000K10 User Guide www dinigroup com 73 THE REFERENCE DESIGN DIMMO FPGA FO VIRTEX 4 XC5VLX330 F3 F15 SMAs F8 and F12 SMAs are along the west edge of the board in pairs An identical setup exists F3 F8 and F15 FPGA SMAs positive negative F3 112 7 F8 J39 J40 F12 165 164 15 11 J6 Note that these SMAs are by default DC coupled so the user must make sure to feed them appropriate signaling levels We recommend LVDS signaling or a 2 5V signaling level Feeding the FPGA a higher voltage signal level without putting in AC coupling capacitors will damage the Virtex 5 part 4 5 4 DDR2 Clocks The function of the CK signals in the DDR2 interface are described in the DDR2 interface section FPGA Net Name Output Pins Input Pins first first F0 DIMMO CK2 D21 AL16 DN9000K10 User Guide www dinigroup com 74 THE REFERENCE DESIGN DIMMO CKn2 D20 AK17 F1 DIMM1 CK2 D21 AL16 DIMM1_CKn2 D20 AK17 F2 DIMM2 CK2 D21 AL16 DIMM2 CKn2 D20 AK17 F12 DIMM3 CK2 AW26 AL16 DIMM3 CKn2 AW25 AK17 F13 DIMM4 CK2 AW26 AL16 DIMM4_CKn2 AW25 AK17 F14 DIMM5_CK2 AW26 AL16 DIMM5 CKn2 AW25
85. T1 0 9V TP4 DIMM VTI2 0 9V TP5 PWR1 1 8V TP6 DIMM PWR2 1 8V TP7 DC4 B2 VCCO 1 22V TP8 DC4 B1 VCCO 1 22V TP9 2 5V_1 2 5V TP10 DC5_B2_VCCO 1 22V TP14 1 5V_0 1 5V TP15 4 VCCO 1 227 TP17 1 0V TP18 TLUV 3 1 0V TP19 1 0 2 1 0V TP20 1 0V_0 10V TP21 DC5 B1 VCCO 1 22V DN9000K10 User Guide www dinigroup com 76 THE REFERENCE DESIGN TP22 DC5 B0 VCCO 1 22V TP25 1 8 0 1 8V TP24 GND OV TP25 DC6 B2 VCCO 1 22V TP26 GND OV TP27 1 0V_6 1 0V TP28 1 0V_5 1 0V TP29 1 0 7 1 0V TP30 1 0 4 1 0V DC6 B1 VCCO 1 22V TP32 DC6 B0 VCCO 1 22V TP35 2 5V_0 2 5V TP36 1 2V_16 1 2V TP39 DC2 B0 VCCO 1 22V TP40 1 0V_8 1 0V TP43 DC7_B2_VCCO 1 22V TP44 LV 9 1 0V TP45 T 10V 11 1 0V TP46 DC2_B1_VCCO 1 22V TP47 1 0V 10 1 0V TP50 DC7_B1_VCCO 1 22V TP51 2 5V_3 2 5V 52 DC2_B2_VCCO 1 22V TP53 DC7 B0 VCCO 1 22V TP54 DC10 VCCO 1 22V TP55 DC10 B1 VCCO 1 22V TP56 DC10 B2 VCCO 1 22V TP57 GND OV TP58 DC3 B0 VCCO 1 22V TP39 3 3V 3 3V TP60 DC8 B2 VCCO 1 22V TP61 DC3 B1 VCCO 1 22V TP62 T15V 1 15V TP63 12 0 12V TP64 DC8 B1 VCCO 1 22V TP65 5 0V 5V TP66 5 0V 5V TP67 DC35 B2 VCCO 1 22V TP68 5 0VSB 5V TP69 DC9_B2_VCCO 1 22V TP70 DC8 B0 VCCO 1 22V TLV 15 1 0V TP72 1 0 12 1 0V DN9000K10 User Guide www dinigroup com THE REF
86. V_1 FAULT 1 5 1 power supply failed DS146 RED 1 0 13 FAULT 1 0 13 power supply failed DS147 RED 1 0V_12FAULT 1 0 12 power supply failed DS150 RED 1 0V_14FAULT 1 0 14 power supply failed DS155 RED 1 0V_15FAULT 1 0 15 power supply failed DS156 RED 2 5V_2FAULT 2 5 2 power supply failed 13 4 SODIMM Over Under Voltage LEDs These LEDs indicate that a SODIMM power supply is either above or below the standard 1 8V voltage DN9000K10 User Guide www dinigroup com 96 THE REFERENCE DESIGN DIMMO FPGA FO VIRTEX 4 VIRTEX 4 1 VIRTEX 4 XC5VLX330 f XC5VLX330 XCS5VLX330 FFGITOOFGUOTES j A FFG TBDFGUDTAS FFGI760FBU0T4 DIMM4 LED Meaning 1525 DIMM_PWRO rail exceeds 2 2V DS24 DIMM_PWRO rail is less than 1 6V DS27 DIMM_PWR1 rail exceeds 2 2V DS26 DIMM_PWRI rail is less than 1 6V 0529 DIMM_PWR2 rail exceeds 2 2V DS28 DIMM_PWR2 rail is less than 1 6V DS154 DIMM_PWR3 rail exceeds 2 2V DS153 DIMM_PWR3 rail is less than 1 6V DS152 DIMM PWARA rail exceeds 2 2V DS151 PWARA rail is less than 1 6V DS149 DIMM PWARS5 rail exceeds 2 2V DS148 DIMM_PWRS5 rail is less than 1 6V 13 5 Global Clock Si5326 LEDs These LEDs give status on the global 515326 frequency synthesizers DN9000K10 User Guide www dinigroup com 97 THE REFERENCE DESIGN LL PES cC gt gt
87. ally adjusted 3 3 Insert the Compact Flash card into the DN9000K10 s Compact Flash slot This step involves inserting the Compact Flash card into the DN9000K10 s Compact Flash slot Install it into the on board CF slot if you are using the board without a chassis If your board is inside a chassis install it into the slot on the front panel 3 4 Cables 3 4 1 Connect RS232 Cable The configuration circuit displays status messages to the MCU RS232 terminal If something goes wrong with configuration this terminal will output error messages Normally you would only connect this cable when something is not working and you want to debug the problem Use the provided cable to connect the MCU RS232 port to a computer serial port to view feedback from the configuration circuitry during FPGA configuration Run a serial terminal program on your PC On Windows you can use HyperTerminal Start gt Programs gt Accessories gt Communications gt HyperTerminal and make sure the computer serial port is configured with the following options DN9000K10 User Guide www dinigroup com 13 QUICK START GUIDE Bits per second 19200 Data bits 8 Parity None Stop Bits 1 Flow control None Terminal Emulation VT100 or None if available No chassis Use a DB9 t0 IDC10 adapter to connect your serial port to P204 3 4 2 Connect USB Cable Use the provided USB cable to connect the DN9000K10 to a Windows computer Windows XP is recommended
88. ally written 1 2 6 Settings Info Menu The Settings Info Menu has the following options Change Text Editor This option changes the behavior or Open in the file menu and is otherwise undocumented FPGA stuffing information displays a list of the FPGAs on the board and their type and speed grade This information is stored in the firmware flash and is not detected on the fly Board Spartan MCU version this option is used to read the version number of the current board s firmware There are two types of firmware the Flash and the Prom The two types of firmware the reference design and the USB Controller application are only guaranteed to work when using corresponding versions of each If you update one you should update the others Read FPGA temperatures Displays the current temperature of the on die FPGA temperature sensors Force Memory Menu display When the Dini Group reference design is not loaded in at least one FPGA the FPGA Reference Design menu is disabled This menu command causes that menu to be displayed in this situation The USB Controller determines if the Dini Group reference design 1s loaded by reading a memory location on Main Bus and comparing the result to a predetermined value This menu may also be disabled because the USB gt FPGA Communication is disabled Toggle Sanity Check This menu command changes the behavior of configuration where it reads the header in the binaty bit file and
89. als should use the SSTL18 II T DCI drive standard The required VREF VRP and VRN connections required for this standard are provided on all DIMM interface banks DN9000K10 User Guide www dinigroup com 102 THE REFERENCE DESIGN DQS signals should use the DIFF_SSTL18_II drive standard External differential termination is provided on these signals at the FPGA DDR2 clock signals should be driven by the DIFF SSTL18 II standard DDR2 Control signals BA SH RASH WEZ should be driven by the SSTL18 I standard The following signals are exceptions to this requirement On the DIMM interfaces external termination resistors are provided The signals with external termination are listed below 1 DIMM A00 2 DIMM 01 3 DIMM A02 4 DIMM A03 5 DIMM A04 6 DIMM A05 7 DIMM A06 8 DIMM A07 9 DIMM A08 10 DIMM A09 11 DIMM A10 12 DIMM A11 13 DIMM A12 14 DIMM A13 15 DIMM A14 16 DIMM A15 17 DIMM _CAS 18 DIMM _CS 0 19 DIMM ODTO For signals in this list use the SSTL18 drive standard 14 3 2 Serial Interface The SDA and SCL interfaces are 2 5V I C signals and should use the 2 5V LVCMOS signaling standard External pull ups are provided on these signals The address of all DIMMs on the DN9000K10 is set to zero The reference design provides a basic interface to the lines For a detailed description on the information available via the interface on the
90. ank of 40 interconnects pins 3 4 Header This reference design is a hardware test of the Header interface It requires a test fixture to work properly It may not be provided DN9000K10 User Guide www dinigroup com 141 THE REFERENCE DESIGN 4 Using the Reference Design 4 1 Reference Design Memory Map Each reference design uses the MainBus interface to supply status and controls The following memory map is used These registers are accessible using the windows USB Controller program using the MainBus menu or from AETEST for PCI Express access All addresses on main bus are 32 bits Each address contains one 32 bit word By convention each FPGA has a fixed memory range FPGA FO will respond to all MB accesses in the range 0 00000000 FPGA F1 will respond to accesses from 0x10000000 Ox1FFFFFTF Et cetera The addresses given below are offsets from the base address of any given FPGA Some registers are not valid for all FPGAs Some addresses are not valid for all of the Dini Group s reference designs Main Test does not have LVDS registers and LVDS test does not have DDR2 registers Some of the address bits are decoded as don t care bits Therefore accesses to undefined addresses may cause undefined and unexpected behavior Address Register Register Range Name Contents 0x00000000 DDR2 the data contained in the DDR2 SODIMM memory 0x07FFFFFF 0 08000001 DDR2HIADDR the upper bi
91. arate VCCO pin and can have a different voltage applied to it When designing a daughter card you must determine the current requirements for the DN9000K10 and supply enough current capacity on these pins Warning Do not impress any signal voltage greater than VCCO to a daughter card bank Doing so may cause permanent damage to your DN9000K10 User Guide www dinigroup com 134 THE REFERENCE DESIGN For example if you are running VCCO at 2 5V do not impress a 3 3V signal on your daughter card pins 1 8V signals are safe but may not work correctly because they may fail to hit switching threshold Warning Do not impress a VCCO voltage greater than 3 3V on the DN9000K10 s VCCO pins Virtex 5 parts can only signal at maximum 3 3V levels The VCCO voltage impressed by the daughter card should be less than 3 75 to prevent damage to the Virtex 5 IOs connected to that daughter card See section 22 2 2 for more information on how VCCOS ate shared on FPGA banks 22 2 8 VCCO bias generation Since a daughter card will not always be present on a daughter catd connector a VCCO bias generator is used on the motherboatd for each daughter card bank to keep the VCCO pin on the FPGA within its recommended operating range The VCCO bias generators supply 1 2V to the VCCO pins on the FPGAs and are back biased by the daughter card when it drives the VCCO rails VCCO 380mA MAX AT 1 22V Vadj 1 22 LT1763C S8 SOIC1
92. are DC2 DC5 DC6 DC8 or DC9 Then enter a number for lt n gt to set the PLL options Omitting the last bracketed part will cause the PLLs to go into bypass mode For valid combinations please see the diagram in Section 4 4 of this chapter Source lt clock gt lt n gt Sets lt clock gt to run from source lt n gt where n 1 corresponds to normal operation and n 2 corresponds to bypass mode running from F15 clock output Clock can be G0 G1 G2 Figure 17 Main txt Commands An example main txt file is given below This will prevent the MCU output over RS232 to speed configuration VERBOSE LEVEL 2 this will load the configuration a bit into FPGA FPGA 0 fpga fO bit 5326 PHO CLOCK FREQUENCY 300MHz Writes to a register in FPGA FO DN9000K10 User Guide www dinigroup com 57 THE REFERENCE DESIGN MAIN BUS 0x08000000 0x00000001 Even if you are not planning to configure your Virtex 5 FPGAs using a Compact Flash card you may want to leave a Compact Flash card in the socket to automatically program your global clock Clocks may also be programmed using the provided USB application 3 4 2 Hardware The Compact Flash interface is hot swappable Due to inconsistency in Compact Flash cards some Compact Flash cards may not completely meet the Compact Flash specification and thus may be incompatible with the DN9000K10 Please contact support dinigroup com if you
93. are Update For information about the MCU boot up sequence see Hardware Configuration Circuit MCU DN9000K10 User Guide www dinigroup com 85 THE REFERENCE DESIGN The source code for the MCU firmware Flash is provided Source Code MCU FLASH as a Keil Studios MicroVision 2 11 project file 6 5 2 Activity LED A yellow LED located next to the USB connector flickers when there is USB activity 6 5 3 Configuration FPGA The MCU unit controls all of the configuration circuits on the DN9000K10 but it does not have sufficient IO to access all of the configuration signals For IO expansion the MCU s external memory bus is connected to a Virtex 4 LX80 FPGA This FPGA provides a memory mapped interface to all of its IO This bus is called the Configuration Bus The configuration FPGA is connected to all of the configuration signals of the Virtex 5 FPGAs the temperature sensors status LEDs SmartMedia card Compact Flash card reset buttons Main Bus switches RS232 ports clock synthesizer control signals global clock multiplexer control signals FPGA clock inputs the Main Bus and an 300 pin expansion header The source code for the Configuration FPGA is provided in Source Code ConfigFPGA This project can be compiled using Xilinx ISE version 7 11 SP4 or later Your board may have been build using LX80 FF1148 or an LX40 FF 1148 for the configuration FPGA Note Modifications to the Configuration FPGA bitfile
94. board has already been fully tested at the factory 1 Provided Materials Examine the contents of your DN9000K10 kit It should contain DN9000K10 board mounted in a chassis with integrated power supply if chassis option is ordered Otherwise board comes on a base plate Compact Flash card containing the FPGA configuration bit files required to run the hardware test e USB Compact Flash card reader e Cable for RS232 10 pin header female to female e USB cable e Plenty of daughtercard mounting hardware e CD ROM containing Virtex 5 Reference Designs User manual PDF Board Schematic PDF USB program usbcontroller exe Source code for USB program DN9000K10 firmware Board netlist and simulation model 1 1 System Requirements To compile Verilog designs for Virtex 5 ISE 9 21 or 9 11 with all service packs may be required To use the provided controller software you need any Windows XP computer with USB 2 0 Using the product with USB 1 1 will work but is not recommended DN9000K10 User Guide www dinigroup com QUICK START GUIDE Although firmware updates can be completed without a Jtag cable board recovering after failed update required a Jtag cable for ISP If you don t have a Jtag cable you can ship the board back for recovery 2 Warnings 2 1 ESD The DN9000K10 is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar w
95. by the AETEST_usb and USB Controller programs are not documented in the table above This is because we do not anticipate a need for customer use If there are board features that are accessible through USB Controller or AETEST programs that you feel you need access to in your own USB application contact support dinigroup com and we will provide details on using the interface you require A list of these features is provided below G0 G1 G2 frequencies below 31 MHz Single step clocking on GO G1 G2 clock networks Zeto Delay Daughtercard clock network External clock source selection Readback of GO G1 G2 frequency measurements MainBus counter 3 6 Firmware A Virtex 4 LX80 FPGA and a Cypress micro controller control the configuration circuitry The programming data for the FPGA is stored on a flash device and the code for the micro controller is stored on a separate flash device The instructions for updating the firmware are given in the software section The flash that stores the Spartan FPGA programming information DN9000K10 User Guide www dinigroup com 59 THE REFERENCE DESIGN is made available via a JTAG header J19 J201 which can be used with the Xilinx program impact The Dini Group does not recommend doing any sort of development on this FPGA because if you add custom code you will not be able to use firmware updates from Dini Group without merging it with your custom code 3 7 JTAG JTAG interface to the
96. ce read burst Other SODIMM s include access to the following interfaces USB 3 3V IO FPGA interconnect Contact Sales and or Support for details on Compatible Modules Also see website for modules not listed here DN9000K10 User Guide www dinigroup com 154 ORDERING INFORMATION 3 1 2 Daughtercards Dini Group daughtercards connect to the MEG Array connector 400 pin using the standard Dini Group interface description DNMEG CPCIe 8 lane PCIe express PHY card Host or downstream mode DDR2 memory module Virtex 5 FPGA LX110 DNMEG ADC High speed Analog Digital daughtercard Virtex 4 FPGA DDR2 memory module 250Msps 12 bit ADC 60dB SNR 10 bits 200 kHz 75MHz DNMEG V5T two versions Xilinx Virtex 5 LXT FPGA with high speed serial interfaces SMA SATA SFP PCI Express PCI Express cable connectors some SMAs also Display Port Highly recommended for PCIe interface applications DNMEG INTERCON Connects headers for two FPGAs together Contact sales for details on which positions are compatible DNMEG OBS Our most popular MEG Array daughter card Adjustable voltage tenth inch pitch headers User LEDs Two Mictor 38 connectors SMA global clock inputs for host board DNMEG Diff Nine mictor 38 connectors with differential pinout Not standard AMP pinout DN9000K10 User Guide www dinigroup com 155 ORDERING INFORMATION an DNMEG Obs UO Voltage Control 1 2 0 3 37 412V 45V
97. cess will take about 1 minute Please hit OK 5 Select file EEPROM_FLP tic When USBController completes the update please power cycle power the board DN9000K10 User Guide www dinigroup com 44 CONTROLLER SOFTWARE 4 4 2 Using AETest_USB 1 Put the board into Firmware Mode See 4 1 2 Run aeusb_wdm aeusb_linux Select option 3 Firmware Menu 3 In EEPROM Boot Menu please select option 1 Update EEPROM from lt filename gt iic file 4 Enter filename full path The process should take about 2 minutes ASIC Emulator EEPROM Boot Menu v5 Display Flash Version Update EEPROM from lt filename gt iic file Update Flash from lt firmware gt hex file Update 15326 Register values Boot From Flash Main Menu 9 Quit Please select option 1 Please enter filename C Dinillork dn_conf ig MCU EEPROM EEPROM_FLP iic This process take about 2 minutes please patient is updated Please POWER CYCLE the board or functionality doesn t work property AETest Quitting Press any key to continue Figure 15 aeusb_wdm window 5 Please power cycle the board You can also run this on the commend line aeusb_wdm_cmd exe EEPROM lt filename iic gt 4 5 Updating the MCU Flash firmware To protect against accidental erasure the MCU Flash firmware cannot be updated unless the board is put in Firmware Mode during power on Instruction is 4 1 You can either use USBController or AEtest_U
98. control classification number 157 44 MISSION CRITICAL Chapter 1 Introduction Congratulations on your purchase of the DN9000K10 logic emulation board If you are unfamiliar with Dini Group products you should read this chapter and Chapter 2 Quick Start Guide to familiarize yourself with the user interfaces the DN9000K10 provides Figure 1 DN9000K10 Heat sinks recklessly left uninstalled 4 Manual Contents This manual contains the following chapters 1 1 Introduction Reader s Guide to this manual List of available documentation and resources 1 2 Quick Start Guide Step by step instructions for poweting on the DN9000K10 loading and communicating with a simple provided FPGA design and using the board s common control features DN9000K10 User Guide www dinigroup com INTRODUCTION 1 3 Controller Software summary of the functionality of the provided software Implementation details for the remote USB board control functions and instructions for developing your own USB host software 1 4 Hardware Detailed description and operating instructions of each individual circuit on the DN9000K10 A description of each uset accessible interface and user features Also includes a troubleshooting guide posted at the end 1 5 The Reference Design Detailed description of the provided DN9000K10 reference design Implementation details of the reference design interaction with DN9000K10 hardware features
99. controller in it Note that the default voltage on the DN9000K10 User Guide www dinigroup com 12 QUICK START GUIDE SODIMMs precludes the use of these standards modification to the board jumper position change is necessary to set the SODIMM voltage for memory standards other than DDR2 3 2 Prepare configuration files The DN9000K10 reads FPGA configuration data from a Compact Flash card To program the FPGAs on the DN9000K10 FPGA design files with a bit file extension put on the root directory of the Compact Flash card file using the provided USB card reader The DN9000K10 ships with a 256MB Compact Flash card preloaded with the Dini Group reference design These bitfiles can also be found on the User CD You can also compile the reference design source provided on the CD and place the generated bit files on the Compact Flash card Insert the provided Compact Flash card labeled Reference Design into your USB card reader Make sure the card contains a set of files similar to the following adjusted to match the FPGAs you have installed FPGA_FO bit i FPGA FO installed FPGA_F1 bit i FPGA F1 installed main txt The files FPGA_F 15 0 bit are files created by the Xilinx program bitgen part of the ISE 9 2 tools The file main txt contains instructions for the DN9000K10 configuration circuitry to configure the board including which FPGAs to configure and to which frequency the global clock networks should be automatic
100. csssscsssescsssessssese 14 3 4 3 Connect Power cable eee enint entera testet seen nen 14 3 5 VIEW CONFIGURATION FEEDBACK OVER RS S232 eee 15 3 6 CHECK LED STATUS 16 4 RUN USB CONTROLLER esee ee seen seen enne eines see eee ene ene ena ens ens ens ena n 19 4 1 DRIVER INSTALLATION aeterne 19 4 2 OPERATING THE USB CONTROLLER 19 424 Configure PGA uei edited reti ed et rete ME 20 ADD Set Clock FregueHcles tiet od ence eo eni Pn teach aede as 21 4 2 3 Hardware Test DDR2 e Ste i eis 21 4 3 GETTING DATA TO AND FROM THE FPGA 22 0 0808 0 22 5 COMMUNICATING OVER THE SERIAL 1 1 23 6 SCAN THE JI AG CHAIN ean e in abeo tocca 24 61 MOVING ON iiia ta ete iet esi ee te bete led edes 28 CHAPTER 3 CONTROLLER SOFTWARE e eeee sees seen seen netus ens ens tenes ease seas 29 1 USBCONIROLLER 222eicoeto prensa eo rae caeso eae tane eene tice ane eoe aac aaa aide 29 1 1 MAIN WINDOW tei eiecti eb eee tee reed eut 30 JP eas etsi e n 31 1 1 2 Disable Enable USB essent eren tneeene tenent 31 Eoo WindOW scien ix 31 dod OBodnbOFGDhie usas e
101. ctor this one is for DIMMO DN9000K10 User Guide www dinigroup com 100 THE REFERENCE DESIGN n DIMM PWR2 SEL e DIMM_PWR2 1457 14 2 Clocking The data signals in the DDR2 interface are clocked source synchronously In order to clock in and out the DQ data signals the DOS signal are used as a clock using the Virtex 5 BUFIO clock driver Details on how to implement a DDR2 controller are in the Xilinx application note XAPP858 You can also see the provided DDR2 reference design for example code A basic block diagram of the clocking is given below DN9000K10 User Guide www dinigroup com 101 THE REFERENCE DESIGN DDR2 SODIMM Module REFCLK CLKOUTO CLKFB Note that the DIMM CKO2 signal is driven by the FPGA from a 1 8V bank The output should be a DIFF_SSTL18 It is received by a global clock pin on the Virtex 4 device To receive the signal use an LVDS EXT input with DIFF TERM attribute set to TRUE The CKO CK1 and CK2 signals are length matched so this input should be synchronous to the clock input of the DIMM module The DQ and DM signals are synchronous to the DOS signals in each bank See the DDR2 SODIMM module specification for information on the timing of this interface 14 2 1 005 timing In order to clock the DQ and DM inputs using the DQS signal you must use a BUFIO clock buffer on the DQS signal 14 3 Signaling 14 3 1 Standards DQ and DM sign
102. d and only updates the status when there is some user command Items that may be updated when the refresh button is hit ate Type of board connected DN9000K10 in this case Number of FPGAs installed Whether or not the FPGAs are configured blue DONE LED on off Whether the Dini Group reference design is loaded in one or more FPGAs disable enable the FPGA Reference Design menu Check whether USB is enabled 1 1 2 Disable Enable USB ij Copitrollay Jration FPGA Reference Design Mainbu Disable USB gt FPGA To communicate to the FPGA design using USB the Main Bus interface is used See the hardware chapter for more information on this interface Some users elect not to use the Main Bus for USB communication To allow these users to make use of the signals in the Main Bus for their own purposes the USB Controller is careful not to use the Main Bus unless explicitly given permission by the user The user can give permission to use Main Bus by pressing the Enable USB gt FPGA communication button It can revoke that permission by pressing the Disable USB gt FPGA communication button causing the LX80 to tristate the Main Bus signals When the DN9000K10 powers on it begins in the disabled state The state is stored on the boatd so that multiple programs accessing the DN9000K10 may prevent each other from using the Main Bus 1 1 3 Log Window This text box prints the result of each user c
103. d will enter a reset state These tolerance ranges are listed below Nom Voltage Min 1 0V 0 86V 1 5V 1 33V 1 8V 1 60V 3 3 2 9V 5 0V 4 0V 12V 10 64V 2 5V 2 20V The voltage monitors filter the voltage at a frequency of about 1 KHz When a power supply voltage falls out of tolerance the board is put in hard reset the SYS_RST signal is asserted and SYS_RSTn LED glows and an LED along the right hand side of the board will light to indicate which power rail has failed The voltage levels are measured with a RC filter time constant of around 100Hz This means transient voltage spikes may not trigger a board reset 19 10 Heat The maximum power dissipation supported for each FPGA is 25W Using the provided heat sink and fan assemblies FPGAs will remain under the maximum recommended junction temperature 85 degrees C If your design exceeds this limit you can assume the temperature of the device rises 2 degrees for each watt above this amount your design uses Put this number in the settings of the timing analyzer Power requirements of a design can be estimated using the power estimator tool in ISE 9 1 For this calculation the board is assumed to be in an ambient temperature of 35 degrees In a closed computer case the ambient temperature will increase DN9000K10 User Guide www dinigroup com 119 THE REFERENCE DESIGN 19 10 1 Fans The fan units attached above the heat sinks are powered by 5V Each fan has it
104. determines if the file is compatible with the installed FPGA This may be necessaty if using bitstream encryption or using a custom bitfile not created by ISE 8 2 bitgen Setup clock frequencies this menu option displays a dialog box allowing the main global clock networks to be configured DN9000K10 User Guide www dinigroup com 36 CONTROLLER SOFTWARE DN9000 series clock multiplexer setup Set up the multiplexers for the global clocks see clock section for the meaning of the options given Also allows you to set the configuration FPGA divide clock factors DN8 9000K10 GCLK Mux Dialog Allows the user to set up muxes on the GCLK clock networks G0 G2 Also allows you to select FPGA F15 as a clock soutce instead of the on board oscillators and allows you to select the divide value for the Divide Clock option DN8 9000K10 MB Switches Allows you to set the MB switches This does not allow fine control only opening closing each set of main bus switches We do support switching bytes individually contact support dinigroup com for instructions on how to do this DN8 9000K10 DC Clock Setup Allows user to set the DC global clock distribution network See section 4 4 of chapter 4 for details on this 1 2 7 Production Tests Test DDR2 this menu option displays a dialog box allowing testing of the DDR2 sockets on the DN9000K10 If the Dini Group reference design is not loaded the command will automatically load them into the FPGAs
105. du apice aussi ha ee for iita 32 1 2 MENU OPTIONS Dee e ne 33 db RAMS E CE 33 122 Menit uites ime 33 1 23 FPGA Configuration as 34 424 Reference sso s a bit 35 42 5 AMI BUS da se esce 35 1520 Settings aceon e tives sca teeta 36 127 PLOGUCTION 37 L3 JINEBIEEU ente tete te ete ee etate 37 TABLE OF CONTENTS 2 AETEST USB 37 2 1 COMPILING AETEST USB 37 38 3 ROLLING YOUR OWN SOFTWARE cccccsscssssssssssssssssoscssssssssssesssesssossees 38 Sek 38 4 UPDATING THE FIRMWARE cccccsccsssssssscssscccssosssssssssssssscscsssesscsssscsssoesees 38 41 BOOTING THE 0 39 42 OBTAINING THE UPDATES ceccscecssscessccssscccsseecesscccsssssessecessescessevessscessascesssvensseees 39 4 3 UPDATING THE SPARTAN PROM FIRMWARE eese enne 40 4 3 1 Using JTAG cable Xilinx products eerte 40 43 2 USD COMMON CR och Dena ee bc 42 4 33 Using AEtest USB aaa eire rui Fe etel diu 43 4 4 UPDATING EEPROM
106. e MainBus interface description X are don t care Since the remaining 19 bits are insufficient to address an entire 4GB DRAM there is a register DDR2ZHIADDR that selects the highest address bits of the DRAM Each address refers to a 32 bit location in the DRAM The lowest bit is not mapped to DRAM address but instead selects between the upper and lower 32 bits of the DRAM data This is necessary because MainBus is a 32 bit interface and DN9000K10 DRAM interfaces 64 bits wide The bank and side controls are also mapped to the DDR2HIADDR register The location of the DDR2HIADDR register is given in the Reference Design Memory Map section The clock that this design uses G1 must be set to between 180 and 250MHz 6 3 Running the Test To run the hardware test in the USB Controller application select Settings gt OneShotTest and check the DDR2 box The program will automatically load the bit files set the clocks and run the test reporting any errors 7 Clock Counters Each clock available to the FPGA is connected to a counter register and the value of this register is available on MainBus In this way the user can determine if each clock input is working properly DN9000K10 User Guide www dinigroup com 145 THE REFERENCE DESIGN 8 LEDs All of the LEDs connected to an output enable register When the LEDs are not enabled the blink a pattern representing which FPGA the design is for When enabled each LED
107. e remaining sections of this chapter describe this design MainTest the reference design and Dini Group reference design are the same thing Most features of the board such as memory sockets and daughtercard headers are tested using the Main Test LVDS Reference Design Aside from MainTest there is one other self contained design on the CD This design characterizes the FPGA interconnect using differential signaling and a source synchronous clocking scheme It is described in its own section later in this chapter section 13 3 1 Main Test This reference design is also referred to as SINGLE because it is used to test the FPGA to FPGA interconnect This reference design provides access to the following All FPGA clocks DDR2 memory MainBus for USB RS232 SPI Flash Chip pin access only 3 2 LVDS This reference design is an implementation of Xilinx App Note 705 It achieves 900 Mbs sec per LVDS pair between FPGAs the maximum speed possible using this method Other methods may improve bandwidth beyond this limit see Xilinx Application Note 860 The design provides Main Bus registers to allow counting the bit error rate of each bank of 40 interconnect pins 3 3 Single Fast This reference design allows the characterization of FPGA to FPGA interconnect using standard synchronous IO methods between FPGAs Main Bus registers are provided to allow the monitoring of the BER of each b
108. e required Note that for speeds above 550MHz you must use the ISERDES and OSERDES modules adding latency to your interconnect At speeds greater than 500MHz there is more than one clock cycle of latency in board trace delay alone For the maximum bandwidth use single ended signaling at 00MHz For single ended signaling an IOSTANDARD of LVCMOS25 is appropriate Use drive strength of 6mA or 8mA DN9000K10 User Guide www dinigroup com 107 THE REFERENCE DESIGN 16 Main bus Main Bus is the interface that the DN9000K10 uses to bring USB access to all of the Virtex 5 FPGAs If you want to use USB to communicate with your design then you must implement Main Bus slave module in your FPGAs The reference designs include such a controller and you are free to use it Also the MBUS signals can be used as a general purpose shared bus as they connect to a number of FPGAs on the board 16 1 MB Signals The DN9000K10 in addition to the dense interconnect available between FPGAs in a point to point topology provides a MBUS bus that is connected to all Virtex 5 FPGAs There are four MBUS subgroups on the DN9000K10 MBUS40A and MBUS40B are both 40 signals wide and connect to all 16 FPGAs MBUS40A has three sets of switches and three branches and MBUS40B has two sets and two branches The following diagrams shows the topology of this bus Note that each square with label 40 and 40 represents a block of switches Switches
109. e the DQO signal on DIMMO 14 1 Power Each DDR2 SODIMM is capable of drawing 5A of current when in auto precharge mode The DN9000K10 is capable of providing this amount of current 14 1 1 Interface Voltages The standard DDR2 interface voltage is 1 8V The banks that connect to the DIMM interface are powered by 1 8V and the power pins on the socket is connected to this same power net In a DDR2 interface these signals are driven using the SSTL18 DCI drive standard There are some exceptions listed below DIMM SDA DIMM SCL DIMM CK2 These signals are connected to a 2 5V clock bank on the FPGA DIMM_SDA and DIMM_SCL should be driven using the LVCMOS25 standard For details on the DIMM n signal see the clocking section below Note The DIMM interfaces are not designed for hot plug 14 1 2 Changing the DIMM voltage If you need to change the voltage of the DIMM interface there is a set of jumper points provided for each interface allowing power to be redirected from a source other than the on board 1 8V power supply When the DN9000K10 is shipped a jumper is installed connecting the DIMM FPGA Bank power to the 1 8V power rail Next to each of these is a connection to DN9000K10 User Guide www dinigroup com 99 THE REFERENCE DESIGN 2 5V 3 3V or 1 5V Some Dini Group products DNSODM_SDR DNSODM_DDR1 and DNSODM_DDR3 require a different voltage on DIMM_PWR When installing this jumper removing the original jumper to
110. ector is 1 1 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use On the DN9000K10 host these signals are routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used single ended ly do not interfere with each other excessively DN9000K10 User Guide www dinigroup com 129 THE REFERENCE DESIGN A BCD EF GH JK BO Lip L2P LIN LSP LSN LEN 3 L10P 2 2 Special Signal LON 13 14 L14N E Power z 17 18 2 29 9 FPGA I O 12 T o 2 5 m 2 b 2 25 o 0 3 x 72 5 0 bg 2 NO z 1 4 LOIN 15 B1 L N L7N 1 LUN 23 25 N 38 B2 26 27 28 29 30 31 32 F 33 DE 35 36 37 40 2 L22N W All high speed signals the DN9000K10 including daughter card signals are routed against ground potential reference plane When creating a daughter card it is highly recommended that these signals remain against a ground plane to maintain trace impedance DN9000K10 User Guide www dinigroup com 130 THE REFERENCE DESIGN The central columns of the connector pin out use a closely coupled differential pair pin arrangement which
111. ed uP debug o Accessible from all FPGA s via Configuration FPGA Full support for embedded logic analyzers via JTAG interface o ChipScope ChipScope Pro and other third party tools e Convert a pair of MEG Array expansion connectors to interconnect with the DNMEG Intercon Add 186 single ended OR 93 pairs LVDS o 8 12 FPGA 3 to 7 AND OR FPGA 11 to 15 e Enough status LED s to perform a cosmic peel on the face of a walrus 2 Virtex 5 The DN9000K10 allows use of each of the new features of the Virtex 5 FPGA As well as exercises all of the external interfaces on the DN9000K10 the included reference design also exetcises all of the new Compared to Virtex 4 Virtex 5 features listed below Greater speed logic and internal routing speed Built in PLLs Example PLL usage found in the DDR2 reference design 1 25 Gbs maximum IO speed LVDS design uses high speed IO 900Mbs characterized and tested ODELAY output signal delay elements LVDS design dynamically adjusts IDELAY to account for interfaces on the DN9000K10 where signals are not externally length matched FPGA interconnect 6 input lookup tables Larger total density parts in terms of total LUT gates More flexible IO 3 Configuration Section Many functions on the DN9000K10 are done by circuitry on the DN9000K10 external to the FPGA Collectively these circuits are referred to in this document as the Configuration Section The configuration section take
112. en the board is reset the Hard Reset LED DS85 is lit red It is located about an inch above the USB connector DN9000K10 User Guide www dinigroup com 87 THE REFERENCE DESIGN When the board is in reset FPGAs cannot be configured USB does not function the host computer will not be able to communicate with the device When in reset the Spartan configuration FPGA remains configured but all of the logic in the device is cleared Pressing the HARD RESET button S1 located near the ATX power connector can trigger the Power reset This reset cannot be triggered over USB or other remote interface It is also triggered with one or more voltages on the board fall below or above a certain threshold These thresholds are given below Voltage Min 1 0V 0 86V 1 5V 1 33V 1 8V 1 60V 3 3V 2 9V 5 0V 4 0V 12V 10 64V 2 5V 2 20V When the board comes out of reset the micro controller goes through an initialization process that will cause all current settings to be lost including clock settings Also the configuration circuit will act as if the board has just powered on and read from the main txt file to configure FPGAs When reset is triggered it remains triggered until 55us after all trigger conditions are removed This behavior prevents USB from behaving in such a way to permanently disable USB on the host machine Under some conditions the DN9000K10 can fail to be responsive after rapidly asserting and de assertin
113. ent side refers to the side of the PCB with FPGAs and fans the solder side is the side with the daughter card connectors The reference origin of the board is 1 2mm west of the north west corner 2 2 3 Part Pin Names References to individual part s pin are given in the form lt X gt lt Y gt lt Z gt The lt X gt is one of U for ICs R for resistors C for capacitors P or J for connectors FB or L for inductors TP for test points MH for mounting structures FD for fiducials BT for sockets DS for displays light emitting diodes F for fuses PSU for power supply modules Q for discrete semiconductors RN for resistor networks X for oscillators Y for crystals lt Y gt is a number uniquely identifying each part from other parts of the same class lt Z gt is the pin or terminal number or name as defined in the datasheet of the part Datasheets for all standard and optional parts used on the DN9000K10 are included in the Document library on the user CD 2 2 4 Schematic Clippings Partial schematic drawings are included in this document to aid quick understanding of the features of the DN9000K10 These clippings have been modified for clarity and brevity and may be missing signals parts net names and connections Unmodified Schematics are included in the User CD as a PDF Phase refer to this document when designing an interface in the FPGA It is the controlling document for all other resources and therefore should be used to re
114. ext to each FPGA This signal gives a quick indication of whether each FPGA is configured or not The data signals CFG 3 0 DATA 7 0 are dual purpose signals and can be used as additional interconnect pins after all FPGAs have been configured Care must be taken that the FPGA design does not drive these signals until all of the FPGAs have been configured The configuration section will assert the FPGA_RESET signal until this occurs Compact Flash configuration only If you do use the SelectMap data signals as interconnect the provided software USB Controller is not guaranteed to function properly may interfere with your design When using these signals as interconnect the appropriate drive standard is LVCMOS25 The IO voltage is 2 5V SelectMap readback is possible on the DN9000K10 This can be accomplished over USB The user interface for obtaining this data is not defined If you need this feature contact Dini Group support support a dinigroup com DN9000K10 User Guide www dinigroup com 53 THE REFERENCE DESIGN The JTAG configuration method does not go through the configuration circuit See the JTAG interface section for details about this 3 3 USB Interface The USB interface can be used for both configuration FPGA configuration and clock settings etc ot for direct communication with the user design in the FPGA These interfaces are described individually in their own sections in the hardware chapter 3 4 Compact Flash
115. f the selected FPGA is configured FLASH VERSION ADDR 0x08 Value to go into upper address register MCU XADDR VR SET 6 OxBB Sets the size of the bulk transfer Read buffer You must set this to a value equal to the SIZE field of the USB Bulk transfer VR SETUP CONFIG OxB7 This vendor request must be called to select an FPGA for configuration prior to a bulk transfer containing the configuration stream for that FPGA VR_END_CONFIG OxBD This vendor request de selects an FPGA after configuration and returns the configuration status of that FPGA DONE signal VR_MEM MAPPED OxBE This vendor request reads or writes to the address Config Read space of the MCU This vendor request can be Config Write used with the configuration register map above to accomplish any configuration task VR_CLEAR_FPGA Ox90 Clears the selected FPGA of configuration data VR BOARD VERSION OxB9 Returns a byte representing the type of board Each vendor request has a direction request type request and value size and buffer pointer fields The request type is always TYPE VENDOR The request field is the ID listed in the table above The value and data in the buffer pointer fields are vendor request specific The size DN9000K10 User Guide www dinigroup com 81 THE REFERENCE DESIGN field is the number of bytes in the buffer The details of how to implement a vendor request are outside the scope of this manual 6 2 1 VR
116. fer to Each one is labeled with the voltage that it represents Normally all of these LEDs are off If any of these LEDs light there is a power problem with the board and you should contact us First make sure that the output of the power supply is acceptable If the 5Vor 3 3V power fail LED is lit you most likely have a problem with the power supply you ate connected to and less likely with the DN9000K10 board itself If possible probe the 12V 5V and 3 3V test points on the DN9000K10 located near the ATX header with a multimeter to verify that the voltages are out of spec See section 8 1 for specifications on minimum required voltages on monitored power nets When the board is in reset for any reason including power failure or user pressing the reset button the Reset LED 0523 will light RED The LED is located near the reset button S3 north east corner A secondary reset LED is located on the solder side opposite FPGA DS220 Check the Configuration FPGA status LED located near the LX80 FPGA blue LED 0593 This LED should remain BLUE as long as the board is powered on except for a moment just as the board is powering on This LED indicates the Configuration FPGA comes up correctly If this LED is not on it indicates a problem with the board or firmware Check the DONE LEDs of each FPGA When an FPGA is configured a blue LED labeled DONE will glow next to the FPGA it refers to Check the FPGA user LEDs loca
117. figure FPGA via smartmedia Configure FPGA individually via USB Configure FPGA from configuration file Set PowerPC RS232 Multiplexing Clear All FPGAs Read PowerPC RS232 Multiplexing Load UST Prom with filename hex Toggle Sanity Check Main Menu Q gt Quit Please select option You are about to run command that change Spartan s prom Do you want to continue Cy n gt Please enter filename C DiniWork dn_conf ig Conf igFPGA DN 666k16 prom_f lp xsvuf Please enter verbose level 0 4 Om Figure 14 aetest_usb window 6 The progress will start from 0 to 100 This will take long time to complete 10 minutes Please do not disturb the process 7 Power cycle the board when finish You can also use commend line aeusb_wdm_cmd exe XSVF lt filename xsvf gt or aeusb_linux_cmd exe XSVF lt filename xsvf gt 4 4 Updating EEPROM firmware To protect against accidental erasure the EEPROM firmware cannot be updated unless the board is put in Firmware Mode during power on See 4 1 You can either use USBController AEtest_USB program to update EEPROM firmware 4 4 1 Using USBController 1 Putthe boatd into Firmware Mode See 4 1 2 Open USBController ini and add this line service mode 1 save and close the file 3 Run USBController Update Flash dialog will appear please select NO because we are doing update EEPROM 4 Goto Service menu select Program EEPROM This Pro
118. frequency In this manual as well as other supporting documentation the terms G0 and PHO are used interchangeably They refer to the same clock networks On the provided compact flash card there is a table giving the command to set a clock to any of a large number of intermediate frequencies The main txt syntax is Source G1 1 a b c d e DN9000K10 User Guide www dinigroup com 62 THE REFERENCE DESIGN Where lt a gt lt b gt lt c gt lt d gt and lt e gt are arbitrary parameters given in the table The correct value of the five parameters for select frequencies are given below DN9000K10 User Guide H 0 003000 MHz 7 29395 1599 7 146969 0 005000 MHz 1 969 23 6 96999 H 0 010000 MHz 1 969 23 6 48499 H 0 015734 MHz 6 44035 2178 3 44035 0 024000 MHz 5 22453 999 5 22453 H 0 032000 MHz 3 10825 374 3 21651 0 032768 MHz 7 63915 3478 7 13455 H 0 038400 MHz 4 15787 624 4 15787 H 0 044100 MHz 7 139971 7618 7 9997 0 048000 MHz 7 9185 499 7 9185 0 050000 MHz 1 969 23 6 9699 H 0 060000 MHz 3 5773 199 3 11547 0 075000 MHz 2 10777 319 2 10777 0 076810 MHz 5 168383 7498 5 7015 0 096000 MHz 5 5613 249 5 5613 H 0 100000 MHz 1 969 23 6 4849 0 150000 MHz 0 4041 79 4 4041 0 176400 MHz 3 72667 2516 3 3927 0 192000 MHz 4 3157 124 4 3157 H 0 220000 MHz 7 1377 74 4 2755 0 325000 MHz 3 13857 479 3 2131 H 0 440000 MHz 7 1377 74 4 1377 H 0 455000 MHz 3 13857 479 6 1065 H 0 880000 MHz 7 1377 74
119. g prohibitions apply Don t smoke around the DN9000K10 Or let interns play with it 3 Pre Power on Instructions The image below represents your DN9000K10 You will need to know the location of the following parts referenced in this chapter DN9000K10 User Guide www dinigroup com 11 QUICK START GUIDE Figure 3 DN9000K10 stuff you need to know about to get started The FPGAs on the board are named FPGA FPGA F1 etc as shown in the above photo To begin working with the DN9000K10 follow the steps below 3 1 Install Memory The DN9000K10 comes packaged without memory installed If you want the Dini Group reference design to test your memory interfaces you must install memory modules in the SODIMM slot on the board The reference design supports DDR2 SODIMM modules in any densities up to 4 GB more than 4 GB is not tested Although the DN9000K10 is compatible with any DDR2 SODIMM module support for certain addressing configurations may not have been implemented so if you find your module doesn t work email us the model number and timing numbers and we will see if we can add support for this module to our reference design There are SODIMM sockets on FPGA FO F1 F2 F12 F13 and F14 These sockets are DDR2 only we offer custom SODIMM modules with DDR3 DDR1 or SDRAM memory installed on them These may be used if you are interested in prototyping a product and have a specific need for a DDR1 DDR3 SDRAM
120. g reset several times in succession or if the board is powered off and back on very quickly This behavior is caused due to a flaw in the micro controller used for the DN9000K10 configuration circuit This flaw is believed to be mitigated by the reset circuitry on the DN9000K10 If you experience the behavior please report it to support dinigroup com 8 2 User Reset The USER RESET circuit is intended for use by the user When this reset is asserted the RESET_ signal from the schematic is asserted to each FPGA After at least 200ns this signal is de asserted simultaneously to each FPGA This signal is connected to a regular user IO on the FPGA so it is up to the FPGA designer to implement reset correctly within his design The User Reset is asserted whenever the User Reset button is pressed This button S2 is located just above the USB connector There is no LED indicating the state of user reset User reset is also asserted when the reset vendor request is sent over USB When User reset is asserted the RSTn signal to each daughtercard is also asserted DN9000K10 User Guide www dinigroup com 88 THE REFERENCE DESIGN The rise time of the reset signal is fairly slow 10s of nanoseconds and the delay within the FPGA of the reset signal causes the actual de assertion time of the logic within the FPGA to be uncertain by as many as 20ns the timing of a synchronous reset within a single FPGA is guaranteed This means that if th
121. he chapter Reference Design for a description of the Main bus interface Test DDRs FLASH Registers FPGA Interconnect 1 1 Main Window The main USB Controller window has the following components a menu bar a refresh button a Disable USB button and board graphic and a message log Each item in the menu bar is described later in this section DiNi Products USB Controller File Edit FPGA Configuration FPGA Reference Desion Mainbus Settings Info Service Refresh Enable USB gt FPGA GCLK Settings GCLK Phase 0 5326 100 00Mhz GCLK Phase 1 5326 100 00Mhz GCLK Phase 2 5326 100 00Mhz Selected Clock Frequency Mhz SPARTAN CONFIG FPGA VERSION Oxee Board Serial Number 0712083 Sanity Check passed Configuring FPGA F via USB please wait File C mydocs PROJ_MKS dn bitfiles DN9000K10 MainTest LX330 fpga FO bit transferred Configured FPGA F0 via USB Sanity Check passed Configuring FPGA F1 via USB please wait File C mydocs PROJ_MKS dn bitfiles DN900D0K10MMainTestNLX330 fpga Fl bit transferred Configured FPG F1 via USB Figure 10 Main USBController window DN9000K10 User Guide www dinigroup com 30 CONTROLLER SOFTWARE 1 1 1 Refresh Button 258 0077 File Edit FPGA Configuration Refresh Di The Refresh button updates the board graphic by querying the DN9000K10 and reading back its status The USB Controller program does not poll the boar
122. he design Contact sales dinigroup com to request a custom daughter card 22 4 Further Reference See the Dini Group MEG Array Daughter Card specification for generic specification information applicable to all Dini Group boards and daughter cards http dinigroup com product common manual megarray pdf 23Troubleshooting 23 1 The board is dead If the board is not responding at all when connected to a Windows XP computer there is no Dini Emulation Engine in the hardware manager the board may be stuck in reset Check the power failure LEDs If any of them are red then the board is stuck in reset due to a power problem If the failing voltage is 3 3V 5V or 12V then the problem is probably caused by your power supply Check the voltages of these power rails and make sure they are within at least 5 of their nominal voltages If the board is not in reset the RS232 terminal will be active Connect a computer serial port to the MCU RS232 header and open a terminal program on the computer Start gt Programs gt Accessories gt Communication gt Hyper Terminal is a suitable program Hopefully the RS232 configuration status dump will tell you exactly what the problem is In any case the Dini Group will need this capture to diagnose the problem 23 2 The FPGAs won t program First connect the RS232 terminal and follow the instructions in the preceding paragraph Usually when an FPGA fails to program the configuration sectio
123. he software included with the DN9000K10 is USB Controller A Windows XP only GUI application capable of configuring FPGAs sending data to the user FPGA core via USB changing board settings and running hardware tests AETEST usb A cross platform Windows DOS Linux and Solaris command line application capable of configuring FPGAs sending data via USB and changing board settings These programs and the source code for them can be found on the user CD DA USB_Softvare_Applications AETEST_USB DX USB_Software_Applications US BController Precompiled Windows XP binaries for USB Controller and AETEST_usb are provided on the user CD as a Microsoft Visual Studio 6 project Visual Studio 6 or later is required to compile these programs All programs use a driver provided by the Dini Group The USB driver can be found at DX USB_Software_Applications driver 1 USB Controller The USB Controller program is intended to Verify Configuration Status Configure FPGAs over USB Configure FPGAs via Compact Flash card Clear FPGAs Reset FPGAs Set up clock muxes and various other board level features Set Global clocks frequency DN9000K10 User Guide www dinigroup com CONTROLLER SOFTWARE Update firmware for MCU and Spartan Communicate with your reference design over Main Bus described in detail in Chapter 4 The following function interface with the Dini Group reference design Read Write to FPGAs see t
124. hot as 120 degrees but timing is not guaranteed You can use the temperature setting in the ISE place and route tool to make timing allowances for operating the FPGA out of range If you want to disable the temperature limit on the DN9000K10 you can do that using a menu option in the MCU RS232 interface 12Encryption Battery The Virtex5 FPGA supports bit stream encryption When using encryption the FPGA must decode the bitstream using a secret key that is stored in a persistent memory in the FPGA When the DN9000K10 is powered off a voltage is supplied to the FPGA by a battery installed in socket BT1 15 designed to house a CR1220 type lithium coin cell battery Typically these batteries produce just over 3 0V The socket may also work with battery types 13 104 PA These howevet have not been tested Insert the battery positive side up DN9000K10 User Guide www dinigroup com 93 THE REFERENCE DESIGN nnnm The same battery is used for all FPGAs Removing the battery will cause the FPGAs to lose their encryption memories and will have to be re programmed before they can work with encrypted bitfiles again To create encrypted bitfiles turn on the encryption option in bitgen The program will produce an additional output file with an nky extension Use the program impact with a Platform USB JTAG cable plugged into the FPGA JTAG connector on the DN9000K10 to load this nky file into each FPGA When
125. how the user how to implement source synchronous communication between FPGAs Using this method the advertised 900Mbs system speed can be achieved If you do not wish to use source synchronous interconnect ignore this reference design with prejudice All FPGA to FPGA interconnect in this design is constantly being driven by one FPGA sending uni directionally a test pattern The receiving FPGA checks the test pattern for correctness against a known pattern The design is intended to characterize the bandwidth of the interconnect between FPGAs Access to test status is provided over the MainBus interface Note that there are two designs ADC and In the design the directions of LVDS connections between FPGAs are uni directional In the all of the signals are in a direction opposite to the ABC design signals 13 1 Provided Files The source is located at DAFPGA Reference DesigusNIDN9000K10NMainRef DN9000K10 User Guide www dinigroup com 148 THE REFERENCE DESIGN Note that this is the same source as the Main Reference Design compile the design for LVDS some define statements in the Verilog code must be added or removed The make bat utility described in the compiling the reference design section automatically adds and removes these directives The pre compiled bitfiles for this design are located at DA FPGA_Reference_Designs Programming_Files DN9000K10 LV DS Intercon 13 2
126. ile provided on the user CD in AETEST_usb driver Connecting to the device occurs using the driver s usb_open function int handle usb_open 0x1234 0x1234 0 6 1 4 Communication The USB interfaces that the DN9000K10 presents are separated into two types The Vendor requests and the Bulk Transfers All other types of USB transactions are not supported The vendor requests low bandwidth control signals used for controlling the board settings The Bulk Transfers are used for configuring and reading back FPGAs and reading and writing to the main Bus interface DN9000K10 User Guide www dinigroup com 80 THE REFERENCE DESIGN 6 2 Vendor Requests Most of the control functions available over USB are accomplished using a vendor request Programming a USB vendor request is out of the scope of this document but you can copy the code provided in the USB Controller program The following table describes the USB interface presented to the host by the MCU micro controller Vendor Request Name ID Description VR GET FLASH REV OxAG Returns a revision code of the firmware VR GET FPGA INFO OxA7 VR REBOOT OxAD VR CONFIG OxAF Causes MCU to go through configuration sequence Media Card VR FLASH VERSION OxB2 Reads version of flash code VR DISPLAY FPGA INFO OxB3 VR CHECK FPGA INFO 0 4 VR CHECK FPGA OxB5 Returns a string representing i
127. in bus is LSB first The address 0x12345678 should be sent as a bulk transfer of 5 bytes 0x00 0x78 0x56 0x34 0x12 To send a datum send the code 0x01 followed by 4 bytes LSB first When the DN9000K10 receives a data word it sends it onto the main bus interface to the address in the address register It then increments the address register Therefore to send two words over main bus 0x00000001 to address 0x0000001 and 0x00000002 to address 0x00000002 the USB Controller would send the following 15 bytes to USB EP2 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x02 0x00 0x00 0x00 Note that the number of bytes sent to EP2 must be divisible by 5 To request a main bus read operation the USB Controller sends a USB bulk write to EP2 to set the address register as described in the above paragraph Then the USB Controller sends a bulk read to EP6 endpoint 6 with the USB bulk request SIZE field set to the number of bytes requested The number requested must be divisible by 4 After the bulk read is complete the address register is incremented by SIZE 4 Read and write transactions use the same Before starting a USB read using a bulk transfer you must tell the DN9000K10 how many bytes are going to be read by using the VR_SET_EPOTC vendor request described in the Vendor Requests section 6 3 1 Important Note about Endpoints There is only one endpoint that the user should use endpoint 2 Note that an endpoint is bi d
128. in the Hardware manager then the DN9000K10 may be stuck in reset See the Troubleshooting section in the Hardware chapter Also check the red Reset LED described in the LEDs section of the hardware chapter As well as providing visual feedback the board graphic can be used to control configuration of the FPGAs To do this right click on an FPGA in the graphic to show a contextual menu with the options Configure Clear and reconfigure DN9000K10 User Guide www dinigroup com 32 CONTROLLER SOFTWARE EP Configure FPGA FO via LISB Clear FPGA FO Reconfigure FPGA FO Configure will show an Open dialog for you to select the bit file you wish to use with the FPGA Clear FPGA will clear and reset the FPGA Reconfigure FPGA will configure the FPGA with whatever bit file that 2 instantiation of USB Controller last used to configure that FPGA 1 2 Menu Options The following sections describe each menu option and its function 1 2 1 File Menu The File Menu has the following options Open Opens a file with the selected text editor notepad by default To change the text editor see Settings Info Menu section About Displays USB Controller version number along with other things Switch device Displays a list of all Dini Group USB devices detects and allows the user to switch the current device The USB Controller will behave as if the current device is the only attached Dini Group USB product Under
129. inBus read MainBus wtite Vendor requests can contain short 512Byte messages in either direction and cause the MCU to execute code In response to most vendor requests the MCU will modify or read values in the Configuration memory space see next section Since vendor requests can contain only a limited amount of data USB Bulk transfers are used to send configuration data to the DN9000K10 The MCU is too slow to process USB 2 0 data at full speed and so the bulk transfer data is sent to external pins on the Cypress MCU see Cypress datasheet and to the configuration FPGA next section Currently this data is only used to configure FPGAs and so the data is sent to the SelectMap pins of the Virtex 5 FPGAs To begin communication with the DN9000K10 the USB Controller program creates a USB connection object in the host operating system by opening Vendor ID 0x1234 product ID 0x1234 For the purposes of updating the firmware the DN9000K10 can come up in EPROM mode where it loads a program capable of connecting over USB to a host downloading firmware and writing it to the MCU flash memory 1201 The check the MCU makes on reset to determine which mode it should start in is the firmware update switch S1 4 This EPROM code is stored in the EPROM DIP installed in U203 When the MCU is in this mode it registers itself to the operating system as Vendor ID 0x1234 product ID 0x1233 For firmware update instructions see USB Software Firmw
130. ing high currents even though they are within their limits the voltage regulation gets sloppy Power supplies advertised as rated 500W or greater are generally acceptable 23 6 The signal on my board is going crazy on my oscilloscope Make sure the ground clip is attached to the probe If there is an oscillation on the signal near 60 Hz there is a problem with the oscilloscope setup But you probably aren t running the signal that slowly anyway Capture the oscilloscope view and email it to support dinigroup com DN9000K10 User Guide www dinigroup com 138 THE REFERENCE DESIGN Chapter 5 Reference Design This chapter introduces the DN9000K10 Reference Design including information on what the reference design does how to build it from the source files and how to modify it for another application 1 Purpose The purpose of the reference design includes the following e Provide a means to test board hardware for failure e Give users an understanding of the code necessary to use each interface provided in hardware e Provide a starting point for using a tool design flow 1 1 Interfaces used by reference design The reference design helps users by showing them how using each interface is possible Code is provided as is and is intended as proof of concept on each interface advertised for the DN9000K10 product The Dini Group warrants only that the DN9000K10 hardwate is functional and usable The interfaces that the Dini
131. int but all FPGAs use the same pinout A list of all test points on the board can be found in the test points section section 5 of this chapter FPGA FO FPGA F1 SZ XILINX 3 VIRFRTEX 4 3 VIRTEX S XC5VLX330 Ze XC5VLX330 FFG1760FGU0745 1 FFG1760FGU0745 DD1478549A 001478549 TAIWAN TAIWAN Clock Testpoint Photo DN9000K10 User Guide www dinigroup com 72 THE REFERENCE DESIGN This signal can also be used as an external feedback path for a DCM When connecting the output of a DCM to K30 the DCM FB input can be connected to J30 Using this configuration output flip flops connected to of the DCM will have an effective clock to out time of less than zero However for this to function well at high frequencies the bridging resistor R113 in the case of FPGA F2 should be replaced with a 33 Ohm resistor or a 0 Ohm resistor if you enable DCI on the input As these testpoints are DC coupled to the FPGA the user must make sure not to exceed maximum safe voltage levels 2 5V on the test point Feeding the FPGA a higher voltage signal level will damage the Virtex 5 part 4 5 3 SMA Clocks FPGAs F3 F8 F12 and F15 have differential SMA clock inputs on GC pins These are wired with a 0 Ohm inline resistor to allow you to install series termination The following schematic clipping shows the SMA clock on FPGA F12 5 2 F12 CLK SMA INOUTPr ur 3 R1276 DR 4
132. irectional Using the driver that Dini group provides the endpoint and direction fields are stuffed within the same byte write to endpoint 2 this byte should be 0x02 To read it should be 0x08 Some people refer to these as uni directional endpoints 2 and 8 6 3 2 Performance Main Bus over USB runs at a maximum speed of 80Mbs for reads and 32Mbs for writes These numbers assume that the FPGA operates the Main Bus interface with zero wait cycles If the FPGA design has more wait cycles this speeds decreases The approximate speed of Main Bus over USB is given below as a function of Main Bus wait states DN9000K10 User Guide www dinigroup com 83 THE REFERENCE DESIGN 0 cycles 80Mbs read 32 write 1 cycle 76Mbs read 31Mbs write 5 cycles 64Mbs read 29 5 write 30 cycles 32Mbsread 16Mbs write 100 cycles 13Mbsread 11 write 250 cycles 6Mbs read 5Mbs write 6 4 FPGA Configuration The following procedure is used by software on the host computer to configure an FPGA over USB This procedure is followed by the USBController program and AETEST_usb program on the user CD 1 USB Software gets a handle to a USB device with VID 0x1234 PID 0x1234 2 USB host software sends vendor request VR SETUP CONFIG 0xB7 see Vendor Requests with 1 byte in the data buffer representing which FPGA to configure A is 0x01 B is 0x02 C is 0x03 3 The configuration circuit on receiving this vendor request asserts the PROG signal of
133. is not supported by the Dini Group Programming the Configuration FPGA with an incorrect bitfile is a good way to render your board non functional If you need a feature that is not available contact support dinigroup com and we will add it to our standard features 6 5 4 Power The DN9000K10 does not draw any power from the USB connector Hot plugging the DN9000K10 is acceptable 6 6 Troubleshooting If you cannot get USB to communicate with your design over Main Bus please try using the USB Controller software with your design and using the Dini Group reference design with your software This will help determine whether the software or the hardware is causing the error 6 6 1 USB Controller Freezes The Vendor requests on the DN9000K10 are blocking Only one can be completed at a time This includes vendor requests that take a very long time like Configure from Compact Flash 10 seconds During this time USB Controller a single threaded application freezes when any Vendor Request is issued The only way to work around this issue is to create a separate board interaction thread DN9000K10 User Guide www dinigroup com 86 THE REFERENCE DESIGN 6 6 2 Main Bus always returns 0x Error Codes 0xDEADDEAD Main Bus timeout The VALID signal on Main Bus was never asserted See the Main Bus section for details Your FPGA may not be configured 0x12345678 This error code may mean the Enable USB gt FPGA Communication button in USB C
134. is signal is used to reset circuitry used for inter FPGA communication needs to be taken that a synchronous reset is not required for the multiple FPGA system to operate correctly Alternately you design can re generate a synchronous reset and distribute this signal using a MB signal 9 JTAG There are several JTAG headers on the DN9000K10 J19 J201 and J17 J200 are used only to update the boatd s firmware J20 J202 however is connected to the JTAG port of the Virtex 5 FPGAs This interface can be used for configuring the FPGAs or using debugging tools like ChipScope or Identify 9 1 FPGA JTAG The connector for FPGA is shown below 42 5 2 Q JTAG TMS A TICA FPGA JTAG Silkscreen 87332 1420 DUPLICATE JTAG HEADER BACK SIDE DN9000K10 User Guide www dinigroup com 89 THE REFERENCE DESIGN nnnm ym Location of the FPGA JTAG port The order of the FPGA JTAG chain is FPGA F0 2FPGA F1 in order up to FPGA F15 There are no other components in the chain Unstuffed devices will not be shown The voltage of the JTAG chain is fixed at 2 5V and cannot change Hot plug on this header is allowed 9 1 1 Compatible Configuration Devices The JTAG header is designed to work with the Xilinx Parallel IV or Platform USB cable The JT AG chain is tested using a Platform USB cable at 6 MHz The driver installation process for the Platform USB cable is relatively difficult fo
135. is uniformly surrounded by ground pins Above is a graphic representation of the pin assignments for the 400 pin connectors Note that this is a view from the backside of the connector The green boxes represent ground connections Special purpose pins are described below in section 22 2 3 22 2 2 10 Bank Splits One cannot help but notice that each bank on the daughter card has 30 pairs of IO signals yet each bank on the Virtex 5 device only has 20 pairs How is this The trick is that each Daughter Card bank is split between two FPGA banks These bank splits are the same between DC2 DC3 DC5 DC6 DC7 and DC8 The following table illustrates which pairs go to which FPGA bank group BankOA BankOB Bank1A Bank 1B Bank 2A Bank 2B BOL10N BOL11N B1L11N B1L10N B2L10N B2L11N BOL10P 0111 1111 1110 2110 2111 0113 BOL12N 1112 1113 2113 2112 BOL13P 0112 B1L12P 1113 B2L13P 2112 BOL14N BOL15N B1L15N B1L14N B2L14N B2L15N BOL14P BOL15P B1L15P 1114 B2L14P 2115 BOL17N BOL16N B1L16N B1L17N B2L17N B2L16N BOL17P BOL16P B1L16P 1117 B2L17P 2116 BOL18N BOL19N B1L19N B1L18N B2L18N B2L19N BOL18P 0119 B1L19P 1118 B2L18P 2119 BOL1N BOL20N B1L1N B1L21N B2L1N B2L20N BOL1P BOL20P B1L1P B1L21P B2L1P B2L20P BOL21N BOL23N 1120 B1L22N B2L21N B2L23N BOL21P BOL23P 1120 1122 B2L21P B2L23P BOL22N 0124 1123 1125 2122 2124 BOL22P 0124 1123
136. ith FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda ore esd fundamentals html Figure 2 Tens of thousands of dollars in damage may result There are four large grounded metal rails on the DN9000K10 The user should handle the board using these rails as they are much less ESD sensitive than any other point on the board It is recommended to only handle the board when grounded with an ESD strap otherwise it should be carried in an anti static bag The chassis replaces the benefit of the anti static bag inside a sealed chassis danger from ESD is minimal The 400 pin connectors are not 5V tolerant Very few exposed surfaces on the board are tolerant of voltages greater than 4V referenced to GND According to the Virtex 5 datasheets the maximum applied voltage to any IO signals on the FPGA is VCCO This means you should not try to over drive IOs in an FPGA interface above the interface voltage specified in this manual 2 2 Other Some parts of the board are physically fragile Take extra care when handling the board to avoid touching the daughter card connectors Leave the covers on the daughter card connectors whenever they are not in use Use mounting hardware to secure daughter cards DN9000K10 User Guide www dinigroup com 10 QUICK START GUIDE 2 3 Other warnings The followin
137. ive strength of 24mA to use main bus DCI should not be used because the signals are not impedance controlled Although not required by convention data on the MBUS signals is synchronous to the MBCLK clock In order to use the Main Bus interface to communicate with USB you must use the MBCLK clock This clock runs at a fixed 40 MHz 16 1 3 Timing As described above the MBUS signals are typically run synchronous to the 40 MHz MBCLK clock This is the highest speed that the MBUS signals ate guaranteed to run using a system DN9000K10 User Guide www dinigroup com 110 THE REFERENCE DESIGN synchronous clocking method You may be able to achieve performance from FPGA to FPGA on this bus as high as 75 MHz if you adjust input and output clocks and perform a timing analysis Using LVCMOS25 with a drive strength of 24mA you can assume there is 10ns rise time flight time for signals on this bus The MBCLK clock distribution is described in Chapter 4 Section 4 3 3 No length matching is done on the MBUS signals The MBUS signals are tested at 40 MHz Although this is probably the maximum theoretical speed for MBUS40A and MBUS4OB faster speeds may likely be achieved on MBUS40C and MBUSAOD Also it is possible that you may see a speed increase by opening main bus switches and running one branch isolated from the rest of the bus 16 2 Switching Topology The MBUS signals on the DN9000K10 aside from being broken up into busses of 40 pi
138. k network 22 2 5 Timing and Clocking Signal from the FPGAs to the daughtercard connector are not length matched The maximum trace length on the DN9000K10 board for these signals is 800ps Each daughtercatd has a global clock output pair DC GCCP DC _GCCN This LVDS output is distributed on the DN9000K10 to all Virtex 5 FPGAs The clock buffers on the host board is designed to deliver the clock edge to all FPGA synchronized with the CCLK pin on the daughtercard header The daughtercard is expected to distribute clocks on it so that ICs on the daughtercard receive the clock signal synchronized with the pin on the daughtercard header In this way the host and daughter boards should be able to communicate synchronously with equal large IO periods in each direction There are three methods of communicating FPGA to FPGA across the daughtercard interface Local Synchronous The daughtercard generates a clock and drives it over the GCAp n or GCBp n clock pins to the host board FPGA The daughtercard drives a synchronized clock to the logic on the daughtercard adding 0 5ns delay to account for the trace delay on the DN9000K10 The host FPGA will use a DCM in zero delay mode and the logic on the daughtercard should have a low clock to out and setup times or use a DCM This method has the disadvantage of only allowing the one FPGA attached to the daughtercatd to use this frequency To communicate globally across the DN9000K10 the user would have to
139. les there After the script completes you will find files for each FPGA that was built fpga_ bit is the file to be downloaded to the FPGA When using the provided VHDL the generic definitions are not complete in the Dini Group code Some of the signals that are governed by generics must be defined externally or defined in the first place DN9000K10 User Guide www dinigroup com 147 THE REFERENCE DESIGN 12 2 Bitgen Options The Make bat script correctly sets all bitgen options that are compatible with the DN9000k10PCI The following options should be used with the DN9000K10PCI Options that ate not listed here can be selected by the user or left to their default settings Compress OFF Or you can disable sanity check option on board UnusedPin Pullnone Persist Yes Only require is Readback is used Encrypt No Or you can disable sanity check option on board DonePipe No Yes Can cause configuration errors DriveDone Yes No can cause configuration Errors Don t ever disable CRC Check This is the easiest and most certain way to turn your FPGAs into little piles of carbon ash I am pretty sure this option exists to increase sales of replacement FPGAs 12 3 VHDL No VHDL design exists at the time of print However one is planned for the very near future Contact support dinigroup com for the availability and schedule of this design 13LVDS Reference Design The LVDS Interconnect design is to s
140. lly end with electrical connectivity Especially read the Virtex 5 user guide The copy provided on the user CD is only recent as of the DN9000K10 product announcement Mote recently copies of the datasheets can often be found online In general it is recommended that you use the latest datasheet especially for complicated parts like the Virtex 5 FPGAs Often manufacturers make corrections or add vital details into their datasheets long after the parts are put into production 3 6 Xilinx Virtex 5 is a state of the art programmable logic device and technical questions about getting the FPGA and ISE software to behave like you expect should be directed to a Xilinx FAE Also use WebCase http www xilinx com Supa clearexpress websupport htm AnswetrBrowser x ISE Manual Virtex 5 Manual s DN9000K10 User Guide www dinigroup com INTRODUCTION 3 7 Dini Group Reference Designs The source code to the reference designs are on the User CD Please copy and use any code you would like The reference designs themselves are not deliverables and as such receive limited support 3 8 Board Models Simulation models for the DN9000K10 are provided on the user CD DAFPGA Reference DesignsN DN9000K10 source 3 8 1 Base System Builder Files are not provided with the standard user CD at the time of print Contact support dinigroup com to obtain files and support for this option 3 8 2 Using Partitioning and 3 party synthe
141. loaded and a DDR2 module installed in a memory socket connected to the FPGA using that reference design Also the clock settings must be correct Follow the procedure in the previous section to accomplish this From the FPGA Memory menu select Test DDR A box will appear and ask which FPGA should be tested Select an FPGA with the MainRef design loaded on a DDR2 SODIMM inserted The log window will report whether the test passed If it fails it will print a list of addresses and data that failed If you would like to simulate a failure you can repeat this guide with the DDR2 module removed Other tests that could be performed from the USB Controller but aren t part of this DN9000K10 User Guide www dinigroup com 21 QUICK START GUIDE quick start are interconnect tests and others For more detailed information on running these tests see the Software chapter 4 3 Getting data to and from the FPGA The USB Controller program also allows you to easily configure and transfer data to and from the user design on the emulation board This data transfer occurs over the board s MainBus This interface is described in the Hardware chapter section 16 Some users may choose not to implement the MainBus interface and use these signals for general purpose FPGA interconnect To allow this by default the main bus is disabled and the Host interface USB in this case is prevented from operating it This is necessary in this application because
142. lways request a duplicate User CD with the latest documentation and other provided files We will also be happy to provide the latest version of documents via email to customers Contact support dinigroup com for either of these options 3 3 1 Existing Errata At the time of print no errata exist DN9000K10 User Guide www dinigroup com INTRODUCTION 3 4 Schematics and Netlist Unmodified Schematics are included in the User CD as a PDF Use the PDF search feature to search for nets and parts 3 4 1 Netlist In lieu of providing a machine readable version of the schematic the Dini Group provides a text netlist of the board This netlist contains all nets on the board that connect to user IO on any FPGA When interfacing with any device or connector the DN9000K10 you should use either the provided ucf or the netlist to generate the pin out The netlist is located on the user CD at DNSebematicNRev 01NDIN9000K10 customer bt 3 4 2 Net name conventions Two sides of a differential signal differ by one character or n This character is near the end of the net name Active low signals end in or n In the provided UCF files a is replaced by an N 3 5 Datasheet Library Datasheets for all parts used or interfaced to on the DN9000K10 are provided on the user CD In order to successfully use the DN9000K10 you will have to reference these datasheets The interface descriptions given in this user manual typica
143. n shes in ge neo 91 935 SLROUBLESHOOTINO 91 10 55555 DE D EU 91 TODD Configuration eo tec quen 92 11 5 5 93 12 ENCRYPTION BATTERY 93 13 95 13 1 CONFIGURATION SECTION LEDS eer 95 13 27 USER LEEDS P MS 95 13 3 POWER FAULT ra EI E 96 13 4 SODIMM OVER UNDER VOLTAGE 96 13 5 GLOBAL CLOCK 815326 LEDS 1er ceess tetra ve e Neh bes e Pee e Pe Ue Pee Ye 97 13 6 UNUSED LEDS 99 14 56 99 POWER ute uk usi 99 Interface Voltas d ante bec dete a 99 14 1 2 Changing the DIMM voltage eese eene enne 99 14 2 CLOCKING R E EER 101 JL b DOS TMG a a is Slag ae a 102 14 3 SIGNALING eaten seco a Pn pare p ados E Pen pte 102 eei dla cce aunt ints 102 143 2 e
144. n will detect the problem and print an error message to this terminal Common problems the configuration section might report The syntax in the main txt file is incorrect The bitfile on the Compact Flash card is for the wrong type of FPGA The Compact Flash card 1s not formatted with a file system that the DN9000K10 can read DN9000K10 User Guide www dinigroup com 136 THE REFERENCE DESIGN If the DN9000K10 reports about one or more FPGAs that DONE did not go high then there is a problem with the bit file The bit file may have been generated using bitgen options that are not compatible with the DN9000K10 See if the FPGAs will configure using USB or JTAG When you contact Dini Group for support we will need a capture of the RS232 terminal output 23 3 My design doesn t do anything Make sure that the clock your design uses is running Output the clock to an LED and probe it with an oscilloscope Check the pinout in your constraint file Check the PAR report file to make sure that 100 of your IOBs used have LOC constraints There is never a reason not to constrain an IO That is all IOs should be constrained Use the PAD report to make sure your constraints were all applied Some situations may cause constraints to be ignored Double check that the connections match between your FPGA pins and the daughtercard pins using the schematic If Main Bus interface is not working makes sure that none of the othe
145. neral it is the responsibility of the user to determine if the board is suitable for his application prior to ordering a board Details about the interfaces on the board that are not in this manual and characterizations of interfaces if available can be requested 2 2 1 Hardware Errata Details There are no errata for Virtex 5 production non CES parts 2 3 Small FPGAs The DN9000K10 is optimized for Xilinx Virtex 5 LX330 FPGAs Optionally it be ordered with LX110 or LX220 FPGAs instead When installed with one or more LX110 or LX220 FPGAs the amount of available interconnect is reduced due to some IOs in those devices being no connected DN9000K10 User Guide www dinigroup com ORDERING INFORMATION When installing LX110 LX220 instead of LX330 parts the SODIMM connectors some daughter cards and a good deal of chip to chip interconnect is lost In the following diagram lost features are crossed out in red When a bus is partially lost the bus has a red cross bar on it with a red label indicating the number of pins LOST 1 5V to 3 3V DDR2 um Serial 120 Serial 120 Serial FLASH 128Mb 20 2 140 Zit 140 2072 MBV MEG Array Expansion Connector 400 pin 8 1 5V to 3 3V 8 MEG Array Expansion Connector 400 pin Virtex 5 Virtex 5 LX330 LX330 FF1760 FF1760 OF AS L 1012euuo uoisuedx3
146. ns can also be separated into branches by opening switch groups There are a few reasons why this may be desirable The first is that you can effectively break one bus into several smaller ones that can run independently from one another The second is that it decreases latency by decreasing the number of loads on the bus In the above diagram MBUS40A and MBUS40B topology the switches are represented by the squares on the MBUS40A and MBUS4OB busses They may be toggled connected disconnected through USB Controller via the Setup MB Switches function under the Settings Info menu By default all switches are closed connected 16 3 Error Codes The Main Bus interface has no way of signaling an error condition on read requests but some errors will result in the same sentinel values being returned Following is a list of these values OxDEADDEAD The Main Bus read times out USB only When this condition occurs register accessible as part of the configuration register space gets incremented In this way it is possible for a Main Bus access program to verify that a MainBus transaction has succeeded OxDEAD5566 This value is returned by the Dini Group reference design as a default value when a read request is to an address that has no registers associated with it OxBABABABA unknown Contact support 0 12345678 The Main Bus is disabled This is the default state of the DN9000K10 when it powers on To set the D
147. ns information on which FPGA s should be configured and what bitfiles should be used for each FPGA The syntax of this file is similar or identical to the syntax of the Compact Flash main txt interface Details are found in the USB Controller manual on the user CD at DX USB_Software_Applications US BController doc US BController_Manual pdf Configure via Compact Flash this command causes the FPGAs to configure based on the instructions in the main txt file on the Compact Flash card It will also cause the commands and settings on the main txt file to be re issued Configure Daughter card over SM Mictor This menu command let you configure FPGA on the daughter card via select map Mictor Clear All FPGAs this command resets all FPGAs causing them to lose their configuration Reconfigure All FPGAs this menu command is equivalent to selecting reconfigure FPGA in the context menu of each of the FPGAs Each FPGA is cleared before being configured The last bit file that was loaded via USB for each FPGA is loaded again into the FPGA If an FPGA has not been loaded with a bit file using instance of USB controller it has no effect Reset this command asserts the signal to all FPGAs simultaneously This is the same signal that is asserted when the user hits the Soft Reset User Reset button Its function in the user design is left for the user to define In our reference design it causes a global asynchronous
148. nt to communicate with your design over a user serial port RS232_2 3 4 or 5 The MainTest reference design that you already loaded has an asynchronous loop back on port 5 Ports 2 4 are connected directly to the FPGAs on bank 1 of each FPGA Using this interface requires you to implement a UART inside the FPGA for parsing the interface This feature is not demonstrated in the reference design but is fairly trivial to do There is no hardware methodology for dealing with bus contention on the RS232 lines This function is left up to the user 91 2 5072 425 2 LIN CC A24 SN ZO L4P L4N FOE B L8N_D2_FS 2_2 LOP_D1_FS1_2 LON_DO_FSO_2 XCSVDXG3D0FF1760 1 RS232 connections at FPGA FPGA FO shown as example Pins and bank are same for all FPGAs DN9000K10 User Guide www dinigroup com 23 QUICK START GUIDE RS232_TA amp all FPGAs bank i RS232 DX B 42 510 VECO 5232 206 CONIDA 103310 10 Silkscreen P207 103310 10 RS232_2 D iuF CPUMP4 1 1 5 2 R110 R1115 1 00K 1 00K TT C TO ALL FPGAs f 2 50 85232 TLC RS232 7 21 85232 TxD4 D TO FPGA BANK 6 49 RS232 XD lt 9 18 42 50 Vero RS232 uci IE 8522 49 R 232 RXD 10 325V2 R1093 1 00K 11
149. of 0 1 weight 1000 ppm contains hexavalent chromium Cr in excess of 0 1 weight 1000 ppm d contains polybrominated biphenyls PBB or polybrominated dimethyl ethers PBDE in excess of 0 1 weight o 1000 ppm contains cadmium in excess of 0 01 weight 100 ppm No exemptions are claimed for this product 4 3 2 The USA Schedule B number based on the HTS 8471 60 7080 4 3 3 Export control classification number ECCN EAR99 4 4 Mission Critical DN9000K10 and supporting hardware and software are not intended for use on human subjects that you like in life support mission critical systems or aviation DN9000K10 User Guide www dinigroup com 157
150. ommand in USB Controller There is a clear log button to clear the contents of this text box DN9000K10 User Guide www dinigroup com 31 CONTROLLER SOFTWARE 1 1 4 Board Graphic USB Controller s main window shows a graphic representing your DN9000K10 The number of FPGAs that are installed on your board should appear in this graphic If one or more FPGAs are configured on the board a blue LED will glow next to the FPGA in this graphic window just like on the actual board hardware itself If the USB Controller could not find a DN9000K10 connected to any USB port this window will appear The DiNi product was not found Please check the Following 1 Your USB cable is firmly plugged into the computer and the board 2 Your board is powered on 3 The device driver for the board is loaded 4 The device is not presently configuring itself from the media card If the board is turned on and plugged in the USB Controller should be able to detect it If it does not try opening the Device manager You can right click on the My computer icon and select Hardware tab and click the Device Manager button This will display a list of the devices connected to your computer If a DiniGroup Product FLASH Boot appears in the USB section then USB is working properly on the boatd but the program is unable to connect to it Select Switch Device from the File menu If the board does not appear
151. on section To write to a configuration register use the VR MEMORY vendor request The direction is OUT The value field is the address you wish to write to example 0xDF39 the disable Main Bus register The size field should be 1 The buffer should contain a single byte containing the byte to be written to the Configuration Register All configuration registers are one byte 6 2 6 Other Vendor Requests Many of the Vendor requests used by the USB Controller program are not documented Dini Group does not support these requests for users If you need a function that you feel is not described here contact support dinigroup com DN9000K10 User Guide www dinigroup com 82 THE REFERENCE DESIGN 6 3 Main Bus accesses The USB Controller control the DN9000K10 reference design using USB vendor requests and bulk transfers that access the configuration FPGAs registers These registers cause Main Bus transactions with the user FPGAs The host computer initiates all Main Bus transactions To see a specification of the Main Bus interface see Reference Design To request a Main Bus interface write transaction the USB Controller program sends a USB bulk write to EP2 endpoint 2 The first byte contains a code either 0x00 or 0x01 determining whether the next 4 bytes contain an address or a datum If this byte is a 0x00 the next 4 bytes in the bulk transfer are stored into an address register All data transferred to and from the ma
152. on the user CD here DA FPGA_Reference_Designs common DDR2 controller_ver ddr2_to_mb DN9I000K10 source The top module is DA FPGA_Reference_Designs DN9I000K10 MainTest source fpga v This module includes all of the other required sources and expects the directory structure found on the CD 12 1 4 Xilinx Embedded Development Kit EDK The DN9000K10 does not use the EDK because it has no embedded processor 12 1 2 Xilinx ISE Xilinx ISE version 9 1 service pack 1 or later is required to use the reference designs Earlier versions may work but are not supported Create a new ISE project file and add the edf as a source For part type select the type of FPGA installed on your board Make sure to add the provided ucf file to the project Run the map implement and generate steps 12 1 3 The Build Utility Make bat The Build Utility is found at DN9000K10 buildxst make bat This batch file can be used to run ISE and bitgen If you do not have cygwin installed you need sed Stream Editor command to tun make bat sed can be download from http gnuwin32 sourceforge net packages sed htm please download the setup program and set your PATH environment to executable file under lt SED gt bin folder You may also need to add the Xilinx bin directory to your path so the command calls the correct program The build script creates a directory called out and places its output fi
153. ontroller has not be pressed the Main Bus disable register is set 0xDEAD5566 this error code is returned by the Dini Group reference design when there is a Main Bus read to a register that is not defined Default Main Bus output This code is specific to the reference design 0xDEAD1234 Contact support 0xABCDABCD this error code is returned when a MainBus register corresponding to a memory is read but the memory is not implemented in the Reference Design 7 Unusable pins 7 1 1 Configuration The following pins All FPGAs are the SelectMap data pins used to configure the FPGAs These pins are connected to both Virtex 5 FPGAs Using these signals for FPGA interconnect is possible but may interfere with the configuration circuitry on the DN9000K10 Pins AJ13 AK13 AJ28 AK29 AL14 AL15 AJ26 AJ27 7 1 2 Bank 0 Configuration Bank These pins may not be used nor mapped to for any purpose 8 Reset There are two reset circuits on the DN9000K10 One is the power on reset or Hard Reset that holds the boatd including the configuration circuitry in reset until all power supplies on the board ate within their tolerances The second reset circuit is the user reset or Soft reset 8 1 Power Reset The power reset signal holds the configuration circuit including a micro controller and Spartan 3 FPGA in reset It also causes the FPGAs to become un configured and causes the RSTn signal on the daughtercards to be asserted Wh
154. or is inserted on line This effectively filters out frequencies below a certain range Also it eliminates any DC bias on the line eliminating common mode issues The term DC coupling implies an absence of a series capacitor FPGA Numbering A B C vs F0 F1 F2 The official FPGA numbering on the DN9000K10 is FO through F16 Some resources refer to FPGAs as FPGA A instead of FPGA F0 FPGA A and FPGA FO is the same thing same with B and F1 and so on 3 Resources The following electronic resources will help you during development with your board 3 1 User CD The User CD contains all the electronic documents required for you to operate the DN9000K10 These include schematics the user manual FPGA reference designs and datasheets The directory structure of the CD is as follows Config_Section_Code The DN9000K10 firmware source code these sources are not intended to be used for MCUN development Datasheets A datasheet for every part used on the board You will need these to interface successfully with resources on the DN9000K10 Documentation Contains this document and USB specification Manual Dini_USB_Spec DNMEG _InterconDaughtercard Documentation on the Test Daughter Card DNMEG_Observation_Daughtercard Documentation on the Test Daughter Card DN9000K10 User Guide www dinigroup com INTRODUCTION FPGA_Reference_Designs Contains the source and compiled program common ming files for the
155. over the main bus are said to be at this address and subsequent transactions will increment address by 1 each until a new address is latched On a later clock cycle the master may assert the signal Sometime after this within 256 clock cycles the FPGA should assert DONE for one clock cycle On this cycle the master Spartan will register the data on the AD bus and that will be the read data If DONE is not asserted then a timeout will be recorded and the transaction cancelled is a wtite transaction DN9000K10 User Guide www dinigroup com 112 THE REFERENCE DESIGN MBAS USB CLK SYS RD Aaeeei o m enemies MB WR Spartan 2 MB 33 DONE FPGA ccce ee ee ee erue eere emen nnne ne ee lt lt lt 5 0 to 200 Cycles When the Spartan asserts the WR signal the FPGA should register the data on the AD bus Sometime after this the FPGA should assert the DONE signal This will allow the Spartan to begin more transactions The FPGA may delay this for up to 256 clock cycles before a timeout is recorded and the transaction is cancelled Main bus can be controlled from the USB Controller program Read and write single addresses ot to from files It can also be written from the main txt configuration method The main txt syntax is MAIN BUS Ox lt address gt Ox lt data gt Where lt address gt and lt data g
156. p com 114 THE REFERENCE DESIGN FLASH_WPn 0x 800007B bit 4 Note is the hexadecimal number of the FPGA you are accessing Provisions for accessing the SPI flash through USB controller have been made see section 17 1 below For timing diagrams and instructions on how to communicate with an SPI Flash please see the datasheet for the M25P128 You can find this in your datasheets folder file name is st_flash_m25p 128 pdf 17 1 SPI Flash Access through USB Controller Provisions for accessing the SPI flash through USB Controller have been made You can program a binary file into the flash modules up to 128Mb for standard boards at the time of print larger SPI flash options may be available and read back the flash memory space To program a file into the flash program the FPGA connected to the flash chip with the MainRef design and select Program SPI Flashs from the FPGA Reference Design menu DiNi Prod troller Edit FPGA Configuration FPGA Reference Design Mainbus Settings Info Production Tests Service Refresh pi Test FLASH through PRES DN 7 8 000K10 PCI Interconnect Test T 5 GCLK Settings DN 7 8 000K10PCI Interconnect Menu gt r GCLK Phase 0 0 8000 10 Interconnect Menu 5326 100 00Mhz GCLK Phase 1 5326 100 00Mhz Read DDR 12C Data GCLK Phase 2 Read FPGA Clock Frequencies E 5326 100 00Mhz Selected Clock Frequency Mhz Program SPI
157. pass the data across clock domains Global Synchronous The daughter catd generates a clock and dtives it over the GCCp n pins to the DN9000K10 host board The user will select the daughtercard source for the daughter card network as appropriate Set the network in zero delay mode done by default disadvantage of this method is that the DC GCLK network must be used The advantage is that the entire system can be operated on a single clock domain Zero delay on the DN9000K10 is allowed by enabling PLL devices zero delay buffers connected to the GCC pins of each daughtercard header To allow for a very wide range of clock frequencies sourced from the daughtercatd the PLL bandwidth of these buffers must be manually set This can be done via USB ot Compact Flash The PLL can also be bypassed allowing a global system synchronous clock to be used without configuring this PLL To use this method the user will have to experimentally find the proper clock phase to use on the IO of the daughter catd DN9000K10 User Guide www dinigroup com 133 THE REFERENCE DESIGN Source Synchronous The daughtercard drives a clock into the CC pins of the daughtercard connector This clock is used to latch IOs This method should be used for frequencies exceeding 150 MHz because the phase tolerance of the Virtex 5 FPGA and the clock buffer devices on the DN9000K10 DC GCLK signals will prevent a reliable system synchronous design at very high speeds 22
158. pe nene aepo tna eaa tune arenas 145 6 1 PROVIDED PIEES Site eet dale RE Reve 145 TABLE OF CONTENTS 6 2 USING THE DESIOA cccccccccssccsssccessecsessecesssccssssccssecesssscessscesssecssecessescessevessess 145 6 3 RUNNING THE 5 145 CLOCK COUNTERS 145 146 RS232 SIGNALS iicicciciccccatecisbecccscussscssdedetsescasssnselesascusceevsceselestebssdaadeedsbeccescesetasees 146 10 d BO Ped o eem 146 11 SIMULATING THE REFERENCE DESIGN eeeeeee eee seen seen 146 12 COMPILING THE REFERENCE ense en s ens enn enne n 147 12 1 1 The Xilinx Embedded Development Kit 147 12 22 147 12 1 3 The Build Utility Make RED 147 12 3 BITGEN OPTIONS eot ec teet ete RIS 148 12 3 there tette ot tees tee 148 13 LVDS REFERENCE 148 13 1 PROVIDED cece a 148 13 2 USING THE 149 13 3 RUNNING THE TEST ccc
159. perature sensor FPGA overheat Compact Flash card reading USB configuration Main Bus teads writes Global clock settings Mainbus Switch Settings Daughter Card Clock Mux Settings DN9000K10 User Guide www dinigroup com 51 THE REFERENCE DESIGN HOV 50 x6 EU 50 52 LCD TX FPGA BANK 3 42 29 VECO 80 50 52 MCU i P204 terminal ia 103310 10 2 isk ESD PROTECTED R1OUT RIIN R20UT 2 3 16 ND SOURCED MAXIM MAX3i22E gt Silkscreen RS232 TI MAX3232 DO NOT USE MAXIM 222 81 CPUMP1 32 20 46 0 CPUMP2 The configuration section RS232 terminal header labeled MCU terminal above can be connected to a computer serial port using the settings 19200 Baud No flow control One stop bit No parity DN9000K10 User Guide www dinigroup com 52 THE REFERENCE DESIGN The output will give you the status of the board start up and configuration processes and serves as a log of any errors that occur on board boot up Any settings you have programmed into your main txt file on the Compact Flash card should be reflected in this output The MCU RS232 interface is not at all fun to use and is intended mostly for Dini Group to debug hardware or software failures However if you are having problems configuring your board or setting things like clocks
160. pidly toggling the LED signal high and low with different duty cycles 50 duty cycle 50 brightness 13 3 Power FAULT LEDs These RED LEDs indicate is one or more power supplies fail The voltage and power supply that the LED refers to is marked in silkscreen near the LED LED LED Signal Name The LED indicates the following when ON Designator Color DS21 RED 2 5V_1 FAULT 2 5 1 power supply failed DS30 RED 1 0V_3FAULT 1 0 3 power supply failed DS31 RED 1 0V_2 FAULT 1 0 2 power supply failed DS32 RED 1 5V_0 FAULT 1 5 0 power supply failed DS33 RED 1 0V_1 FAULT 1 0 1 power supply failed DS34 RED 1 0 OFAULT 1 0 0 power supply failed DS55 RED 1 8V_0 FAULT 1 8V_0 power supply failed DS76 RED 1 0V_6FAULT 1 0 power supply failed DS77 RED 1 0V_4FAULT 1 0 4 power supply failed DS78 RED 1 0V_5 FAULT 1 0 5 power supply failed DS79 RED 5 0V FAULT 5 0V power supply out of spec ATX supply DS80 RED 3 3V FAULT 3 3V power supply out of spec ATX supply DS81 RED 1 0V_7FAULT 1 0 7 power supply failed DS83 RED 2 5V_0 FAULT 2 5V_0 power supply failed DS84 RED 12 16 FAULT 1 2 16 power supply failed DS89 RED 1 0V_8FAULT 1 0 8 power supply failed DS90 RED 1 0V_9 FAULT 1 0 9 power supply failed DS91 RED 1 0 11 FAULT 1 0 11 power supply failed DS92 RED 1 0 10 FAULT 1 0 10 power supply failed DS94 RED 2 5V_3 FAULT 2 5V_3 power supply failed DS138 RED 1 5
161. r DN9000K10 User Guide www dinigroup com 38 CONTROLLER SOFTWARE If you don t have Xilinx cable and wish to update Spartan prom you can use USBController AEtest_USB to program it through USB You have to contact us for xsvf file When updating the firmware the Flash PROM and USBController exe should all is updated simultaneously since Dini Group only verifies this code using corresponding versions of each 4 1 Booting the board There are 2 modes Firmware mode The board is booted from EEPROM and User Mode The board is booted from FLASH User Mode is default run when the board is powered on To boot the board in the Firmware Mode find Switch 52 User Reset on the DN9000K10 Figure 11 Switch S2 Hold down the User reset button for 5 seconds while the DN9000K10 powers on Alternately while holding down the User reset switch press the Hard reset button and then release User reset switch after 5 seconds The DN9000K10 samples the user reset button on power on to enter into firmware update mode If your board is hooked up serial port RS232 you will see this message MCU FLASH can be updated now 4 2 Obtaining the updates The firmware update files are not posted on the web site In order to obtain them you must request them from support dinigroup com You may be required to perform a firmware update to your boatd to receive support and some features When updating firmware you
162. r FPGAs are driving those MB pins Make sure that the Unused IOBs option in bitgen is set to Float Check for Timing errors in the timing report Route the clock signal to a pin and observe it with an oscilloscope 23 4 The DCMs won t lock 1 The DCMs ate required to be set in a frequency mode compatible with the frequency of the reference clock input Check the following attributes of the DCMs DFS FREQUENCY MODE DFS FREQUENCY MODE 2 All clock inputs of the DCM are required to be stable for a certain number of microseconds before releasing the DCMs reset signal If you are generating the reference clock from an FPGA or another DCM you will need to build a delayed reset circuit to reset the second DCM 3 Make sure the global clock you are using is being received with an LVDS receiver not a single ended one Make sure the DIFF TERM attribute is turned on Especially is the problem is with high frequency clocks DN9000K10 User Guide www dinigroup com 137 THE REFERENCE DESIGN 23 5 The board resets right after 1 didn t hit the reset button Make sure you ate meeting the minimum load requirements of the power supply Also check that the 12V 5V and 3 3V voltages on the DN9000K10 are close to their nominal voltages If they droop too low the DN9000K10 will detect this and reset These two voltages are generated by the external power supply Dini Group has found that while some cheaper ATX power supplies are outputt
163. r a USB device Follow the instructions carefully In order to achieve high speed configuration using a Parallel IV cable you need to enable ECP mode on yout parallel port This is probably a BIOS setting on your computer DN9000K10 User Guide www dinigroup com 90 THE REFERENCE DESIGN 9 1 2 Identify You do not need to configure via JTAG in order to use JTAG debugging tools on the DN9000K10 9 1 3 ChipScope In order to use debugging tools on the DN9000K10 you do not need to configure via JTAG 9 2 Firmware Update Header The firmware update JTAG header J16 should not be used unless you are updating the DN9000K10 firmware This header is used with a Xilinx Platform USB or Parallel IV cable The instructions for updating the firmware are in the Controller software chapter 9 3 Troubleshooting If you ate having problems getting JTAG to work try connecting the Xilinx Platform USB cable to the JTAG header and running the Xilinx program Impact Impact will generate a failure log that you can email to support dinigroup com 10RS232 Interface RS232 access is available to all FPGAs through the four headers P206 P209 RS232 5 2 P206 corresponds to RS232 2 P207 to RS232 3 etc Three of the four ports are bused to all FPGAs The other port is connected to the configuration FPGA and multiplexed through its internal logic The RS232 transmit and receive signals connected to each FPGA s pins AJ16 RS232 2 TX from FPGA AJ1
164. ransfer is BULK READ instead of WRITE The commands required by the SelectMap interface to start a Readback must be sent using the configuration interface For this reason it is the programmer s responsibility to understand and implement the SelectMap protocol DN9000K10 User Guide www dinigroup com 84 THE REFERENCE DESIGN 6 5 USB Hardware The actual hardware associated with performing USB communication with the DN9000K10 is briefly described here Since the user is not required to understand how to operate the hardware from the FPGA much detail is omitted 6 5 1 Cypress CY7C68013A A Cypress Micro controller MCU with a built in USB controller provides the USB interface of the DN9000K10 For a low level understanding of the way the DN9000K10 communicates over USB you should see the Cypress CY7C68013A datasheet The driver that Dini Group provides is the free Cypress EzUSB driver with customizations to the corresponding file to identify the board as a Dini Group Emulator product As with all USB devices communication with the DN9000K10 is initiated by the host PC and can be either a USB vendor request or Bulk transfer All other types of USB transactions are not supported or documented with the DN9000K10 In general Bulk transfers are used for high bandwidth data and vendor requests are used for all other control functions Bulk Transfer Functions Configure FPGA SelectMap Readback FPGA SelectMap Ma
165. re ar EIE 2 Zug Physical Dimensions du Pacto 3 2 2 3 Part Pin NQMOS iiccccesssccccesssccesssnsececssnsccecssnsccecssnsccecssaccesssnaccesssnaceessenaceeceeaceess 3 224 Schemat CIOS MM 3 2 3 TERMINOLOGY uoe ceecccccceccccsccssscccssecsssescssssccssscsssescesssecssssscsascessescssssscsassesssscessesenaess 3 3 RESOURCES Pc oadacssscnssestesducs 4 USER CD 4 3 2 ccccsecesccccssscccssecssscscssssccssscessescessccsssscssascessescessescssscessascessesensece 5 3 3 ERRATA AND CUSTOMER 8 0 440 400000 5 DI NSE fina 5 3 4 SCHEMATICS AND NETLIST cccccccsssscssssccssecssscecesssecssscsssescesssscssssscssssesssscessevensese 6 E A aoa sta Goes ee ee 6 3 4 2 CONVENTIONS ssccecesnsccecesnsececssnsccecssnsccecssnsccecessccessenaccesssnaceeceensccess 6 3 5 DATASHEET LIBRARY cccccccsscccssecssscecssssccsscssseecssssecsssccsescesssscssssccssssesssscesesensase 6 O D i D 6 27 DINI GROUP REFERENCE DESIGNS 0 2 0 4 0800 7 3 8 8 0 04 40 0 6 1 7 38 1
166. reset This option also causes the SYS_RSTn signal on the daughtercards to be asserted DN9000K10 User Guide www dinigroup com 34 CONTROLLER SOFTWARE 1 2 4 FPGA Reference Design Note There are many options under this menu Only ones applicable to the DIN9000K10 are described DDR Type Size when running the DDR2 test in the reference design a register must be set to identify the type of memory installed in the DDR2 slot This menu option allows you to set that register Read FPGA Clock Frequencies This menu option measures and reads back the frequencies of the clocks connected to a particular FPGA Requires the reference design to be loaded on the FPGAs you are reading from Single Ended Interconnect Test slow this menu option will run test single ended test on which FPGAs is selected 1 2 5 Main Bus The way that user FPGA designs can communicate over USB is the Bus interface The Reference design menu uses the main bus to read and write registers in the reference design to control the board tests These tests can be done by the using these menu options without the user having to understand the Main Bus interface or the main bus memory space and it s mapping to the reference design The Main Bus menu allows direct control of the Main Bus This can be useful if you are using your own FPGA core that implements the main bus Write and Read DWORD this displays a dialog box for writing and reading to the Main Bus address
167. rmation about the bit file CONFIGURATION OF FPGA FO CONFIGURING FPGA Fl x x Performing Sanity Check on Bit File The MCU is configuring FPGA F1 according to instructions in BIT FILE ATTRIBUTES MAIN TXT FILE NAME FPGA 1 FILE SIZE 003A943B bytes PART 5v1x330ff176017 05 01 DATA 2007 07 19 TIME 17 05 01 Sanity check passed Sx dU ee M ed n DONE WITH CONFIGURATION OF FPGA F1 TEMPERATURE SENSORS AES The MCU is setting the temperature threshold Causes the FPGAs B YES to automatically disable when overheating FPGA Temperature Alarm Threshold 80 degrees C Figure 4 RS232 Output Note that this text is not board specific and may vary depending on your board configuration and configuration settings 3 6 Check LED status lights The DN9000K10 has many status LEDs to help the user confirm the status of the configuration process In general red LEDs mean BAD or FAILURE and green LEDs mean GOOD or WORKING The board should have no red LEDs lit during normal operation Check the power Failure LEDs to confirm that all voltage rails of the DN9000K10 are within tolerance If the voltage of any critical power net on the DN9000K10 is too low the board will be held in reset and at least one of the red LEDs will light The LEDs are located near the DN9000K10 User Guide www dinigroup com 16 QUICK START GUIDE power supplies that they re
168. rrent M and N values 0x01 is GO 0x02 is G1 0x04 is G2 PENDING SOURCE DF16 When high each bit sets the source of the each clock source Bit 0 sets the source of GO between oscillator and F15 0 oscillator bit 1 sets source of G1 etc DN9000K10 User Guide www dinigroup com 58 THE REFERENCE DESIGN FPGA COMMUNICATIO DF39 Disables Main Bus interface N TEMP SENSOR A CF50 Temperature of FPGA FO F1 is at CF51 etc SERIAL NUMBER DFFA Board Serial Number ASCII String BOARD_TYPE DFFE Board type identifier IMBUS40A B1 DF36 Controls the switch for MB40A B1 Writing opens the switch disconnected 0x00 closes the switch connected IMBUS40A B2 DF38 Controls the switch for MB40A B2 Writing opens the switch disconnected 0x00 closes the switch connected MBUSA40A DFA43 Controls the switch for MB40A B3 Writing OxFF opens the switch disconnected 0x00 closes the switch connected 540 B1 DF41 Controls the switch for MB40B B1 Writing OxFF opens the switch disconnected 0x00 closes the switch connected MBUS40B B2 DF42 Controls the switch for MB40B_B2 Writing OxFF opens the switch disconnected 0x00 closes the switch connected Note 1 See USBController function ClkF req_int_frac in CUSBCW indow pp for example of this logic 3 5 1 Undocumented controls Most of the accessible registers to control board function used
169. s setup time 1 00 ns Min Period 6 67 ns Max Frequency 0 15 GHz If LVDS is used make sure to assign the DIFF TERM attribute to the IBUFDS the receiver FPGA As the frequency of synchronous communication between FPGAs increases the user must implement more difficult techniques As a general guide these techniques are described below 0 MHz 20 MHz The user should use the Pack the IOBs by using synthesis attributes The output delay for each output and setup time for each input is a known value 100 MHz Use DCMs in each FPGA to eliminate the variation of clock network skew internal to each FPGA The clock must be free running 250 MHz Use DDR clocking and DDR IO buffers 300 Use source synchronous clocking between FPGAs The clock is driven with the data for each bus The receiving FPGA uses the clock signal received on a CC pin to clock the IOs in the bus An IDELAY element on the CC pin input delays the clock with respect to the data by a fixed amount to allow some setup time 550 Use the Virtex 5 build in ISERDES and OSERDES modules 600 MHz Use Virtex 5 PLL devices to reduce cycle to cycle jitter on the clocks 700 MHz individually de skew each bit using IDELAY elements Use a training pattern or hatd code the correct delay values for each input 800 MHz Use LVDS signal standard 900 MHz Dynamically de skew each bit to account for temperature and voltage variation 1 GHz Highest speed grade parts ar
170. s care of DN9000K10 User Guide www dinigroup com 50 THE REFERENCE DESIGN Compact Flash interface USB interface Main Bus interfaces master Temperature sensing Over under voltage sensing Clock frequency and source configuration SelectMap configuration interface Blinking red and green LEDs The Configuration Section is built around a Virtex 4 LX80 FPGA and Cypress microprocessor These ICs are used by the configuration circuit and are not intended for user design The code running these controlling ICs is collectively referred to as the firmware The code for this firmware is provided for reasons I don t know Customer development efforts on these platforms are not supported If you need special configuration circuit behavior please contact Dini Group and request that we implement it and support it as a standard feature The technical details of the configuration circuit are omitted from this manual since the user should not require it The configuration code is not user serviceable modify at your own risk There is a good chance of disabling either temporarily or irreversibly the configuration section when modifying the firmware 3 1 Configuration Section Feedback Duting normal operation and in error situations the configuration section prints messages to the RS232 terminal header P204 on the PCB and labeled on the front panel The configuration section processes that can be monitored using this header are Tem
171. s own power connector 19 10 2 Removing Heat sinks The heat sink fan assemblies are attached using a plastic clip There is a thermal interface material between the FPGA and heat sink that is slightly adhesive Removing the heat sink should only be done using a special tool Contact us for help 19 10 3 Tachometers Fan Tachometers are sent to the Configuration FPGA These registers may be read back and interpreted via USB Controller menu option Read Frequencies under Settings Info DN9000K10 User Guide www dinigroup com 120 THE REFERENCE DESIGN DiNi Products USB Controller c Mainbus Settings Info Service figuration FPGS Reference Design 6000K10 Series RocketTO Frequency Change Text Editor m USB Read ri FPGA Stuffing Information FPGA Fans On Off BOARD SPARTAN MCU Version Read FPGA Temperatures Force Memory Menu Display Toggle Sanity Check Update Spartan Setup Clock Frequencies DIYBGGOKTOPSX Glock Mux Setup DNSGOOKTOPCI Glock Source Selection DN8 9000k10 GCLK Mux Dialog DN8000k10 MB Switches DN8 9000k10 Clock Synth Setup DN8000k10 Read Synth Settings DN8 9000k10 DC Clock Setup DN8000k10 Rocket IO Mux Setup Test DDR One Shot Test You should see the following output in the USB Controller log Name Value Raw Value in Hex FPGA fan FO 0 000RPM 0x00000000 0x0000000
172. sis tools We cannot support directly third party synthesis tools that we do not have Therefore support for these tools must be obtained from the software vendor 4 Email and Phone Support Dini Group technical support for products can be reached via email at support dinigroup com Our phone number is USA 858 454 3419 Please do not send exe files vb files or zip files containing other zip files as attachments without contacting us first as we will not receive these attachments nor the email itself Please include the board s serial number in your email This will allow us to reference our records regarding your board Before contacting support you should complete the following 1 Follow the debugging steps in the troubleshooting sections at the end of the hardware chapter and in any applicable interface sections 2 Test the applicable interface s using the provided software and bit files to help rule out hardware failures DN9000K10 User Guide www dinigroup com Chapter 2 Quick Start Guide The Dini Group DN9000K10 can be used and controlled using many interfaces In order to learn the use of the most fundamental interfaces of the board FPGA Configuration USB data movement etc please follow the instructions in this quick start guide The guide will also show you how to tun the boatd s hardware test to verify board functionality Note These diagnostic tests are provided only for board interface familiarization The
173. solve any inconsistencies Use the PDF search feature to search for nets and parts 2 3 Terminology Abbreviations and pronouns are used for some commonly used phrases The user is assumed to know the meaning of the following CONFIGURATION FPGA Configuration FPGA refers to the Virtex 4 LX80 FPGA device used by the DN9000K10 to perform configuration circuit functions It is used interchangeably with configuration circuit DCM DLL PLL Digital Clock Manager or Digitally locked loop This is a clock synthesis module in a Virtex 5 FPGA PLL is Phase locked loop See Xilinx documentation LVDS Low Voltage differential signaling a signaling standard with a 1 2V DC and 300mV AC level in this manual and in advertisements LVDS is often used where Differential Signal should be used instead DN9000K10 User Guide www dinigroup com INTRODUCTION Net Signal Plane Rail a net is an electrically continuous piece of conductor on the PCB before assembly Signal can refer to an electrically continuous conductor on the PCB or to the logical meaning of that net Plane is a net for voltage sources Rail is also used to mean a power net GND Ground Grounded GND is a net on the DN9000K10 to which all voltages are referenced Ground is equivalent Grounded means connected to GND There is a single ground net on the DN9000K10 DC AC Coupled AC coupling is a type of routing where a series capacit
174. some situations the USB Controller may automatically switch device when the current device is not valid 2 Exit Closes the USBController application 1 2 2 Edit Menu The Edit Menu performs the basic textual editing commands on the command log in the bottom half of the USBController window These are mostly self explanitory Copy delete and select all DN9000K10 User Guide www dinigroup com 33 CONTROLLER SOFTWARE 1 2 3 FPGA Configuration Menu The FPGA Configuration Menu has the following options Refresh Window this menu option is equivalent to hitting the Refresh button in the main window It queries the board and updates the graphic for visual feedback Configure Via USB individual this menu option allows you to configure an FPGA It is equivalent to selecting an FPGA by clicking on it and selecting Configure except that this menu option will display a dialog asking which FPGA to configure Before any FPGA is configured in USB Controller a sanity check is performed This reads the header out of the binary bit file and determines whether the bit file is compatible with the FPGA installed on the DN9000K10 It will prevent configuration if the sanity check is not passed This check can be disabled from the Settings Info menu Configure via USB using file this command allows the user to configure more than one FPGA over USB at a time To use this option you must create a setup file that contai
175. sources settings the EXTO or EXT1 clock buffers to zero delay mode or setting the clocks to frequencies lower than 31MHz DN9000K10 User Guide www dinigroup com 56 THE REFERENCE DESIGN GCLKO0 SELECT 5326 GCLK1 SELECT 5326 GCLK2 SELECT DIV The GCLK lt n gt SELECT instructions cause the global clock networks to output a clock from an alternate source When source of GCLKO is set to 5326 then the global clock is clocked from the 515326 synthesizer When source of GCLKO is set to STEP GCLKO becomes a step clock which can be accessed through MCU configuration register OxDF8F see Chapter 4 Section 4 2 5 for details DIV sets source to the Configuration FPGA Divide clock and SMA selects the external SMA source 5326 lt CLOCKNAME gt CLOCK FREQUENCY lt number gt MHz The MCU will adjust the clock synthesizer producing clock lt clockname gt to the frequency lt number gt Valid clock names are PHO PH1 PH2 and REF PH lt phase number gt Divide By 2A lt N gt The divider for the PH lt phase number gt global clock will be set to 2 lt gt MCU Register write Ox lt short addr gt Ox lt byte gt Writes to configuration register lt short addr gt with the value lt byte gt hexadecimal DCGCLK dc clock number gt Select lt dc source gt lt n gt MHz Sets the DCGCLK Clock Network DCLK dc clock number gt to feed off of lt source gt values
176. space It includes some debugging features All main bus transactions are of length 4 bytes DWORD Test Address Space This writes and reads random data to the address range specified in a dialog box and prints and error message when the read and write do not match Read Address Space to File this reads data from the main bus at the address specified and writes the data to a binary file specified Data on the main bus is in little endian order The address after each DWORD is implicitly incremented This behavior can be turned off contact support Write Address space from file this reads data from a file and writes the data to the address on main bus specified The data is written in little endian order The address is implicitly incremented after each DWORD of data This behavior can be changed contact suppott Send Command File allows you to run a file consisting of set address read data and write data commands to the mainbus Example syntax AD 0x00000001 WR 0x00000001 DN9000K10 User Guide www dinigroup com 35 CONTROLLER SOFTWARE WR 0x00000002 WR 0x00000003 WR 0x00000004 AD 0x00000001 RD 0x00000004 This file will set the initial address to 0x00000001 Then it will write 0 00000001 to address 0x00000001 0x00000002 to address 0 00000002 etc address automatically increments by 1 every time a write read is performed Then address is reset to 0x00000001 and four reads are done returning the four values origin
177. t are 8 digit 32 bit hexadecimal numbers 16 4 1 Conventional Memory map By convention FPGAs on the main bus interface are assigned address ranges Assigning address ranges is required because the FPGA sourced signals DONE need to be driven by only one FPGA at a time The convention that Dini Group uses is to reserve the upper four bits in the address as an FPGA select address The address range hex 0x00000000 OxOFFFFFFF is reserved for FPGA 0x10000000 Ox1FFFFFFF is reserved for FPGA F1 and so on The user need not follow this convention but unless you really need 32 bit addresses we recommend using it Only one FPGA has control of the DONE signal If the last address latched by ALE was not for a given FPGA it should tri state the output Before tri stating any DN9000K10 User Guide www dinigroup com 113 THE REFERENCE DESIGN signal with a pull up or pull down resistor it is good practice to drive the signal to the DC value before tri stating So that simulation will match emulation result 17 SPI FLASH Several FPGAs on the DN9000K10 have a SPI Flash chip attached to them This chip allows you to store a sizable amount of microcode for running a built in processor 128Mb is the capacity at the time of writing although in the future larger capacities will become available The following tables are a list of flash chips and associated FPGAs FPGA Flash Chip FO U2 F1 U3
178. t click on an FPGA and select choose configuration file Browse to the bit files provided on the user CD For example DA FPGA_Reference_Designs Programming_Files DN9000K10 L X330 fpea_f0 bit Configuration via JTAG is not recommended for standard use USB and Compact Flash configuration is much faster as it goes through SelectMAP an inherently faster bus JTAG configuration is provided mainly for debugging purposes This JTAG port should also be used for visibility products like Xilinx ChipScope DN9000K10 User Guide www dinigroup com 26 QUICK START GUIDE 22 Boundary Scan Ba SlaveSerial 220 Configuration 22 SPI Configuration xc5vix330 xc5vix330 xc5vix330 xc5vix330 e PROM File Formatter file file file 5 330 5 330 xc5vlx330 5 330 file file file xc5vlx330 xc5vlx330 xc5vlx330 5 330 file file file file 5 330 xc5vlx330 xc5vlx330 5 330 file file file Operati Boundary Scan 15 Manufacturer s ID Xilinx xc5v1x330 Version 2 INFO iMPACT 501 1 Added Device xc5v1x330 successfully 116 Manufacturer s ID Xilinx xc5v1x330 Version 2 INFO iMPACT 501
179. t do you want the wizard to do Don t search will choose the driver to install Choose this option to select the device driver from a list Windows does not guarantee that the driver you choose will be the best match for your hardware tical Recommended ion Advanced In the window that appears select Install from a list or specific location Select Next Click Include this location in the search and browse to DA USB_Software_Applications driver windows_wdm Select Next In the next window select the item in the list Dini Group ASIC Emulator Click FINISH After Windows installs the driver you will be able to see the following device in the ASIC Emulators group in the Windows device manager DiniGroup Product FLASH Boot 4 2 Operating the USB Controller program Run the USB controller application found on the product CD in DX USB_Software_Applications US BController US BController exe DN9000K10 User Guide www dinigroup com 19 QUICK START GUIDE DiNi Products USB Controller File Edit FPGA Configuration FPGA Reference Design Mainbus Settings Info Service Refresh Enable USB gt FPGA Com Sa GCLK Settings my s Sand GCLK Phase 0 5326 99 99Mhz GCLK Phase 1 5326 100 00Mhz GCLK Phase 2 5326 100 00Mhz Selected Clock Frequency Mhz BOARD TYPE DN9000k10 USB to FPGA communication is disabled Enable if you
180. ted just next to the FPGA they refer to on the component side of the PCB These LEDs should be active blinking if the Dini Group reference design is correctly loaded in the FPGAs These green LEDs are lined up below the FPGAs DN9000K10 User Guide www dinigroup com 17 QUICK START GUIDE Config FPGA LEDs Logic Reset LED LED JTAG E Connectots MCU LED VIRTExX 4 XC4VLXB0 SPARTAN DONE LED Figure 5 Configuration Section LEDs DN9000K10 User Guide www dinigroup com 18 QUICK START GUIDE 4 Run USB Controller This section will get you started with USB and show you how to operate the provided software 4 1 Driver Installation When the DN9000K10 powers on or you connect it to a USB port for the first time the computer will ask you to install a driver Welcome to the Found New Please choose your search and installation options om E Hardware Wizard RSS This wizard helps you install software for DiniGroup DN6000K10 FLASH Boot Search for the best driver in these locations Use the check boxes below to limit or expand the default search which includes local paths and removable media The best driver found will be installed Search removable media floppy CD ROM If your hardware came with an installation CD floppy disk insert it now Wha
181. ts of DDR2 address MainBus memory space is smaller than most DDR2 SODIMM s 0 08000002 IDCODE 0x05000162 0x08000003 DDR2HIADDRSIZE The number of valid addresses in DDR2HIADDR 0 08000004 INTERCONTYPE An ID code used to identify which design is loaded 0x34561111 Interconnect Single 0x34562222 Interconnect LVDS 0x34563333 Interconnect LVDS reversed 0x34560000 Any Other Design 0x08000005 DDR2SIZE code to control how DDR2 memory is coded into MainBus memory 0 08000006 Read Write Scratch Register for testing 0x08000007 DDR2TAPCNTO The current tap settings of the IODELAY elements in the DQ IO buffers on the DDR2 interface ower bytes 0x08000008 DDR2TAPCNT1 The current tap settings of the IODELAY elements in the DQ IO buffers on the DDR2 interface upper bytes DN9000K10 User Guide www dinigroup com 142 THE REFERENCE DESIGN 0 0800000 0x080000011 0x080000012 0x08000001 4 0x08000001B 0x08000001C 0x08000001D 0x08000001E 0x08000001F 0x08000021 0x08000022 0x08000023 0x08000024 0x08000025 0x08000032 0x08000033 0x0800003F 0x08000040 0x08000043 0x08000046 0x08000047 0x0800004B 0x0800004C 0x0800004D 0x0800004E 0 0800004 0 0800007 0x0800007F 0 0800007 0x0800007B 0 0 000000 SODIMM_SEL IS LX 330 SODIMM RANK SODIMM COL SODIMM ROW SODIMM BANK SODIMM CAS COUNTER COUNTER COUNTER
182. ure Sensors Each FPGA is connected to a temperature monitor This monitor can internally measure the temperature of the FPGA silicon die The maximum recommended operating temperature of the FPGA is 85 degrees The accuracy of the temperature sensor is about 0 to 5 degrees When the configuration circuitry measures the temperature of any FPGA rise above 80 degrees it will immediately un configure the hot FPGA and prevent it from re configuring When the temperature drops below 80 the configuration circuitry will again allow the FPGA to configure When this occurs a message will appear on the CONFIG RS232 port P204 An example test output is given below DRA AAA AAC AAA AA AAA AB eek ee AA EEE kkk AACA AAA ACR RA TEMPERATURE ALERT FPGA F0 CURRENT TEMPERATURE 81 DEGREES C THRESHOLD TEMPERATURE 80 DEGREES C THE FPGA IS BEING CLEARED IN AN ATTEMPT TO PREVENT HEAT DAMAGE SOFTWARE WILL PREVENT RECONFIGURATION UNTIL THE TEMPERATURE DROPS A FULL DEGREE BELOW THE THRESHOLD TEMPERATURE DRA A AAA AA one RA eoe ee ACA AACA AAA ACR ete DRA A AAA se RA AA eek A AACA AACA AAA A RA TEMPERATURE ALERT FPGA F0 CURRENT TEMPERATURE 79 DEGREES C THRESHOLD TEMPERATURE 80 DEGREES C THE FPGA HAS DROPPED BELOW THE ALARM THRESHOLD AND MAY NOW BE RECONFIGURED DRA AA AAA AAC AA A A AA AAC EAA AACA AACA AACA AAA ACR ete The FPGA can safely operate as
183. using a bitfile with encryption enabled the DN9000K10 will not be able to read the FPGA type out of the bitstream The sanity check will fail and it will therefore prevent your FPGA design from loading into the FPGA To disable this behavior you must disable sanity check Adding the following line to your main txt file can do this Sanity check n Also when using encryption you must be careful to correctly set the startup clock option correctly in bitgen or the FPGA will fail to configure DN9000K10 User Guide www dinigroup com 94 THE REFERENCE DESIGN If you need to replace your battery without clearing the FPGA encryption keys see section 5 4 of this chapter Whatever you do if you love your FPGAs do not disable the CRC Check option in bitgen They should have called this option Do you want your FPGAs to not catch on fire 13LED Interface This section lists all of the LEDs More detailed explanations of the LED functions may be in the sections describing the board system that contains the LED 13 1 Configuration Section LEDs These LEDs are controlled by the configuration section These all have a specific function and give the status of the board LED LED Signal Name The LED indicates the following when ON Designator Color 1059 GREEN ON 3 3V The board is powered on DS93 BLUE SPARTAN_DONE Configuration circuit is on Firmware loaded DS82 YELLOW USBACT LEDn There is USB activity DS22 RED LOG
184. utput that will be produced level ovet the RS232 port during configuration When level is set to 0 the port will produce only error output FPGA 0 lt filename gt The 5 FPGA F0 will be configured with the file named by lt filename gt FPGA 1 lt filename gt The Virtex 5 FPGA F1 will be configured with the file named by lt filename gt SANITY CHECK If lt y n gt is set to y then the MCU will examine the headers in the lt y n gt bit files on the Compact Flash card before using them to configure each FPGA If the target FPGA annotated in the bit file header is not the same type as the FPGA the MCU detects on the board it will reject the file and flash the error LED Before this command is executed lt y n gt is set to the default value y If you want to encrypt of compress your bit files you will need to set lt y n gt to n MAIN BUS Writes data in lt WORDDATA gt to the address on the main bus Ox WORDADDR interface at lt WORDADDR gt This command only makes sense 0 lt gt in the context of Dini Group reference design unless your design implements a compatible controller on the main bus pins The Specification for this interface is in MainBus section MEMORY MAPPED Writes to a configuration Register This command can be used to lt 5 gt access features that do not have main txt command Example Ox lt BYTE gt applications include setting clock
185. y in the main txt configuration file on the Compact Flash card Setting REFCLK over USB is not currently supported contact support dinigroup com if this is necessary in your application 4 4 DC GCLK Networks There are four daughter card global clock networks on the DN9000K10 These are PLL and length matched networks that allow you to drive a clock in from a daughter card s GCC pins and distribute it to all FPGAs to use as synchronous clocking mechanism Each network has a 2 1 mux on it allowing it to source from one of two daughter card positions DN9000K10 User Guide www dinigroup com 68 THE REFERENCE DESIGN Dc2Gcc De ALLFPGAs TO ALLFPGAS 222 Dz ALL FPGAS DN9000K10 DC GCLK Network Diagram DC GCLK Clock Network 1 Daughter Card Source Daughter Card Source DC GCLKO DC2 DC4 DC GCLK1 DC9 DC3 DC GCLK2 DC5 DC6 DC GCLK3 DC7 DC8 Possible sources for each DC Global Clock network Please note that whatever clock you input it must be a LVDS signal It must also be between 31 25MHz and 700MHz If you want to input a clock below this frequency range you must disable the internal PLL on the clock network This can be done by setting the frequency to something below 31 25 MHz in the dialogs mentioned below DN9000K10 User Guide www dinigroup com 69 THE REFERENCE DESIGN Setting the source and PLL bypass options is done through USB Controller Run the option DN
186. you do not want the configuration FPGA to try to drive the MainBus lines while you are using them for another purpose If you do decide you want to use the MainBus interface for communication between the FPGAs and the Configuration Circuit hit the Enable USB gt FPGA communication button near the top of the window This will allow the Configuration FPGA to drive the MainBus lines To read data from the FPGA design the Dini Group reference design select from the menu MainBus gt Read and Write In the resulting dialog box enter 080000007 in the Start Address box and 10 in the Size box Press OK and then DONE The result of the read is printed to the USB Controller log window FPGA READ ADDRESS DATA 0x08000000 Oxdead5566 0x08000001 0x00000000 0x08000002 0x050001 62 0x08000003 Oxffffffee 0x08000004 0x34561111 0x08000005 0x00000001 0x08000006 0x00000000 0x08000007 0x00000000 Figure 8 USB Controller Log Output The address 0x080000000 is by convention assigned as part of the space available for implementation by FPGA F0 on DN9000K10 If FPGA is not loaded with the Dini Group reference design or a design that does not implement the MainBus slave then all address reads will return OxDEADDEAD the error code indicating a timeout for the main bus read DN9000K10 User Guide www dinigroup com 22 QUICK START GUIDE 5 Communicating over the Serial Port You may wa
187. you to connect any external clock source through a coaxial cable The third is a divide clock from the configuration FPGA which allows you to divide the 515326 synthesizer frequency down by any value from 2 1 to 2 15 32768 The last source is a step clock from the configuration FPGA which is controlled by writing to register 0xDF8F bit lt n gt lt n gt being the clock number GO G2 you are stepping Finally it is possible to use the output of dedicated pins on FPGA F15 and feed this output into the clock network The default source for the DN9000K10 is from the 515326 synthesizer The configuration register that sets the source of the clocks is at location OxDF16 bit 0 corresponds to GO bit 1 corresponds to G1 and bit 2 corresponds to G2 To change the source to the stop clock write a 1 to the bit location corresponding to the clock network Then write a 1 to the bit corresponding to the clock network in the update register OxDF40 Writing to this register will cause a glitch in the clock 4 2 2 Clock Synthesizers The GO G1 and G2 clock synthesis source is driven by an 515326 clock synthesizer chip This chip is capable of driving a wide range of output frequencies The configuration register that allows selecting the output frequency supports each multiple of 0 125MHz up to 550MHz If the desired frequency is between one of these steps or in the Khz range then you will have to use a compact flash card to set the

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