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Errata Sheet

1. technologies Microcontrollers Errata Sheet V0 4 2004 08 19 Device XC161CJ 16F20F 16F40F Stepping Code Marking ES AD AD Package P TQFP 144 19 This Errata Sheet describes the deviations from the current user documentation The module oriented classification and numbering system uses an ascending sequence over several derivatives including already solved deviations So gaps inside this enumeration can occur This Errata Sheet applies to all temperature SAB SAF SAK and frequency versions 20 40 unless explicitly noted otherwise Current Documentation e XC161 User s Manual V2 2 Volume 1 System Units 2004 01 e XC161 User s Manual V2 2 Volume 2 Peripheral Units 2004 01 e XC161CJ Data Sheet V2 2 2003 06 e C166S V2 User s Manual Core Instruction Set V1 7 2001 01 Note Devices additionally marked with EES or ES or E followed by a 3 digit date code are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet Contents section History List Change Summary Functional Problems Deviations from Electrical and Timing Specification Application Hints Documentation Update re T Errata Sheet XC161CJ 16F20F 40F ES AD 1of31 Mh Es UK V0 4 2004 08 19 1 History List Change Summary from Errata Sheet Rev 0 3
2. 7 of 31 Mh Es UK V0 4 2004 08 19 assign the highest priority to the PEC channel or interrupt service routine and use local register banks and the interrupt jump table cache fast interrupt check for long ATOMIC or EXTEND sequences or phases where the interrupt system is temporarily disabled e g by an operating system extend the ADC conversion time bit fields ADCTC ADSTC Workaround 2 1 for standard conversions if no injected conversions are used Use an interrupt service routine to read the results of standard conversions from register DAT In the interrupt service routine read the result register DAT twice In case a lock situation had occurred the second dummy read access will terminate the lock situation the next conversion result n 1 will be transferred to DAT and interrupt request flag ADCIR will be set such that the result n 1 will be read correctly in the associated interrupt service routine In contrast to Workaround 1 this workaround has less strict timing requirements because it allows wait for read situations and handles the result management within the interrupt service routine The interrupt request flag ADCIR is analyzed to identify and store new results The sequence in the interrupt service routine for standard conversions Is e g MOV Rx Ry read and store conversion result n Rx points to table for results Ryl porints to DAT NOP wait 3 clock cycles before reading ADCIR NO
3. Instead of starting injected conversions by events of CAPCOM channel CC31 or by a period match of timer T13 XC164 XC167 only injected conversions may be started via software in the CC31 or T13 interrupt routine by setting bit ADCRQ 1 In order to avoid that CC31 or T13 events directly trigger injected conversions while the enable bit ADCIN 1 the enhanced mode should be used with bit ADCTS 0 in register ADC_CTRO Since the injected conversion is started by software in an interrupt service routine no coincidence with an instruction that would read register DAT can occur ADC X 004 ADC Overrun Error Generation when result is read during last cycle of conversion When the A D Converter operates without wait for read mode bit ADWR 0 in register ADC_CON or ADC_CTRO respectively and the result of a previous conversion n is read from the result register ADC_DAT one clock cycle before the ADC completes the next standard conversion n 1 the overrun error interrupt request flag ADEIR is already set to 1 This means that ADEIR is set one clock cycle too early and the result has not been overwritten Flag ADCIR is set to 1 to indicate that a new result has been written to ADC_DAT Workaround In the auto scan conversion modes if an interrupt service routine is used to read the result from register ADC_DAT the channel number included in the 4 msbs ADC_DAT 15 12 may be compared to the channel number of the previous conversio
4. This problem occurs for debugging with OCDS as well as with OCE Note The Tasking and Keil compilers including libraries do not generate this type of critical instruction sequence Workarounds choices For assembler programmers one of the following workarounds may be used 1 disable zero cycle operation for jumps when debugging code set CPUCON1 ZCu to 0 or 2 include a NOP after any MUL DIV instruction followed by a conditional jump JMPR JMPA or 3 do not set any break before make type breakpoints on the instruction following the jump or break now type breakpoints shortly before or on the MUL DIV instructions iC X H1 Maximum IIC Bus Data Rate at low f p The extended IIC bus data rate of 400 Kbit s can not be used for clock frequencies fep lt 8 MHz When a lower CPU frequency is used system limitations frequency accuracy and duty cycle of serial clock SCL have to be considered iC X H2 Timing of Bit IRQD The Data Transfer Event Interrupt Request Flag IRQD in register IIC_ST is set to 1 after the acknowledge bit of the last byte has been received or transmitted If bit IC_CON INT 0 IRQD is automatically cleared to 0 by HW with a delay of 1 module clock cycle upon a complete read or write accesses to the buffers RTBO 3 according to the buffer size defined via bit field Cl in register IIC_CON Therefore after reading writing RTBO 3 either add 5 NOPS or read status register IIC_ST
5. auto scan single conversion mode If the wait for DAT read mode is selected bit ADWR 1 the ADC does not acknowledge the request if the conversion result from register DAT has not been read Therefore before the SRST instruction is executed it is recommended e g in the continuous fixed or auto scan conversion modes to switch to fixed channel single conversion mode ADM 00 and perform one last conversion in order to stop the ADC in a defined way In the auto scan conversion modes this switch is performed after conversion of channel 0 If a 0 to 1 transition is forced in the start bit ADST by software a new conversion is immediately started If the wait for DAT read mode is selected register DAT must be read after the last conversion is finished The external bus controller e g may not acknowledge a shutdown request if bus arbitration is enabled and the HOLD input is asserted low Errata Sheet XC161CJ 16F20F 40F ES AD 26 of 31 Mh Es UK V0 4 2004 08 19 SCU X H2 1 Preservation of internal RAM contents after reset After a power up hardware reset the RAM contents are undefined The contents of the on chip RAM modules are preserved during a software reset or a watchdog timer reset Because a hardware reset can occur asynchronously to internal operation it may interrupt a current write operation and so inadvertently corrupt the contents of on chip RAM RAM contents are preserved if the hardware reset occurs du
6. 0 RUN 0 3 disable the RTC module by setting bit SYSCON3 14 RTCDIS 1 Errata Sheet XC161CJ 16F20F 40F ES AD 28 of 31 Mh Es UK V0 4 2004 08 19 5 Documentation Update e XC161 User s Manual V2 2 Volume System Units 2004 01 RSTLEN 1 t p 6 4 6 25 duration of internal reset sequence te 2 typ instead of 2 fos p 6 5 the reset value for register SYSCONS is 9FDOh as stated in the manual i e not all modules are enabled after reset p 6 56 WDTCON X D1 Write access to register WDTCON A write access to register WOTCON in unprotected or secured mode e g before execution of EINIT or by using a special command sequence directly copies bit field WOTREL of register WDTCON to the high byte of the watchdog timer register WDT Clears the low byte of register WDT and selects the WDT clock prescaler factor according to bit field WDTIN This means that an effective write to WDTCON has the same effect as execution of instruction SRVWDT Modifications in step AC and following The following modifications have been performed on devices with stepping code marking AC and higher PORTS X D1 Port Output Control Registers POCONz The encoding of the port driver modes in bit field PDMyN of the Port Output Control Registers POCONz y 0 3 Z OL OH 1L 1H 2 4 6 7 9 has been modified for weak and medium driver mode as listed below The settings for strong driver mode remain unchanged Bit fie
7. 16 This results in an operating frequency range of 3 75 11 25 MHz Systems designed for lower target frequencies should consider the increased power consumption due to the potential frequency increase during these phases of operation Exception in bypass mode with VCO off in case 2 if the RTC is not running on the main oscillator and case in 3 the device stops until it again receives a clock from the oscillator RSTOUT X H1 RSTOUT driven by weak driver during HW Reset A weak driver see specification in Data Sheet has been implemented on pin RSTOUT which is driven low while RSTIN is asserted low After the end of the internal reset sequence RSTOUT operates in default mode strong driver sharp edge mode i e POCON20 PDM3N 15 12 0000b The software setting POCON20 PDM3N 15 12 xx11b is not supported and should not be selected by software otherwise pin RSTOUT floats SDLM_X H1 Writing the Transmit Buffer and reading the Receive Buffer in FIFO Mode The PD bus on the XC166 architecture accessing the FIFO of the SDLM module works word wise Writing reading of transmit or receive buffers runs halfword wise To get a closer look on the functionality of accessing the FIFO buffers the following two paragraphs shall help Writing to the transmit buffer In case the information which shall be transmitted is stored word wise the information has to be stored twice In the other case the user has the information as bytes
8. Interrupt Level EES AA INT X 004 Spike Filter on ExnIN Interrupt Inputs EES AA INT X 005 Unexpected NMI Trap after reset if NMI is permanently tied low EES AA SCU_X 001 Oscillator XTAL1 XTAL2 not disabled in Power Down Mode EES AA SCU_X 002 Watchdog Timer Reset during Bootstrap Mode EES AA SCU_X 003 Modifications of bits ROCON ROCOFF and ROC are not taken into EES AA account SCU_X 004 Wake up from Sleep Mode by RTC Interrupt EES AA SCU_X 005 Reset Indication Flags in Register SYSSTAT EES AA EBC _X 001 Booting from external memories in Multiplexed Bus Mode EES AA IPD_X 001 Power Down Mode Supply Current too high ES AA Cerberus does not follow Event Sequences during Triggered Data EES AA Transfers Break on MUL DIV followed by zero cycle jump gt replaced by Application Hint ES AB ES AB ES AB ES AB SCU_X 006 RSTOUT Characteristics can not be selected via POL O during ES AB Reset PORTS_X 009 1 Pins associated with External Bus Controller are driven after ES AC Software Reset in Single Chip Mode specific description for step ES AB after correction of problem PORTS_X 007 PORTS _X 010 Sleep and Power Down Mode Supply Current influenced by P3 5 ES AC SCU_X 007 Reset value of register FOCON after Software Watchdog Timer ES AC reset DC_X_IPDO 60 Sleep and power down mode supply current with RTC disabled ES AC Note problems listed above may still have to be considered when using an emulation device with marking T
9. be forbidden otherwise an uncontrolled TxRQ will be set Set Message Object Transmit Requests TxRQs in order from 0 to 31 rather than at random This could be done by implementing a software array for transmit requests TxRQs 32 When a TxRQ bit for a Message Object has to be set the software should write to the corresponding location within the software array On a regular basis all transmit requests then have to be reset and set according to the settings within the software array to enable all message objects with TxRQs to be updated in the correct order Between reset and set the application has to wait for the length of two CAN frames In order to use the gateway mode do not set the GDFS bit in MSGFGCR Under the same software control as in workaround a TxRQs can be set as long as CPUUPD is set and only reset in the natural order In this case Remote Frames are allowed Sample for workaround a In a for loop the following takes place for I 0 1 lt 32 i if TxRQ i Message _Object i MSGCTR 0xe7ff Send this message TxRaq Reaquest to Send Errata Sheet XC161CJ 16F20F 40F ES AD 12 of 31 Mh Es UK V0 4 2004 08 19 Simplified sample code interrupt CC1_TOINT void CCl_viTmr0 void Interrupt which takes place on a regular base int ubObjNr Message Object Number for ubObjNr 0 ubObj JNr lt 32 ubOb jNr for all message objects do if CAN_HWOBJ ubObjNr uwMSGCTR amp 0x2000 V ifTxRQ is st
10. flash module is read e g for test purposes with bit field margin 0001b low level margin in register MAR an additional wait state must be used i e bit field WSFLASH in register IMBCTR must be set to 10b for fcpu gt 20 MHz bit field WSFLASH in register IMBCTR must be 01b default after HW reset for fcpu lt 20 MHz 2 When writing to the Margin Control Register MAR with the Write Margin command bit MAR 7 must be written as 1 FLASH X H4 Minimum active time after wake up from sleep or idle mode If the flash module is automatically disabled upon entry into sleep or idle mode bit field PFCFG 01b in register SYSCON1 sleep or idle mode should not be re entered before a minimum active awake Errata Sheet XC161CJ 16F20F 40F ES AD 20 of 31 Mh Es UK V0 4 2004 08 19 time has elapsed Otherwise the current consumption during this sleep idle phase will be 1 mA above the specified limits of the Data Sheet Therefore If code is executed from the internal flash after wake up at least 16 instructions should be executed from the internal flash before re entering sleep idle mode f code is executed from external memory or PRAM wait until the flash BUSY bit returns to 0 before re entering sleep idle mode If PEC transfers with automatic return to sleep idle mode shall be triggered by the wake up event use e g the following procedure use an auxiliary routine in internal flash that waits un
11. mode with this PLLCTRL setting It is therefore recommended to switch to bypass mode PLLCTRL 00b before entry into sleep mode check PLLCON for its target value before executing the IDLE instruction to enter sleep mode e In PLL mode with input clock from XTAL1 connected to the VCO PLLCTRL 11b if the RTC was not running on the main oscillator the device will wake up in emergency mode and run using the internal PLL base frequency from the VCO f 16 until the oscillator input XTAL1 is locked Then the PLL resynchronizes to the target frequency determined by the settings in register PLLCON If the RTC is running on the main oscillator the device will wake up and stay in emergency mode using the internal PLL frequency from the VCO f 16 It is therefore recommended to switch to bypass mode PLLCTRL 00b before entry into sleep mode check PLLCON for its target value before executing the IDLE instruction to enter sleep mode IDLE X H1 Entering Idle Mode after Flash Program Erase After a program erase operation idle mode should not be entered before the BUSY bit in register FSR has returned to 0 status not busy ADC X H1 Polling of Bit ADBSY After an A D conversion is started standard conversion by setting bit ADST 1 injected conversion by setting ADCRQ 1 flag ADBSY is set 5 clock cycles later When polling for the end of a conversion it is therefore recommended to check e g the interrupt request flags ADC_C
12. the application software has to shift every second byte Note Odd byte is written to odd position even byte to even position Every piece of information has to be stored in Register TxDO Errata Sheet XC161CJ 16F20F 40F ES AD 24 of 31 Mh Es UK V0 4 2004 08 19 high byte low byte Write Access 2 Ox high byte 00 TxData 1 TxData0 TxData3 TxData2 TxData5 TxData4 TxData7 TxData6 TxData9 TxData8 0x0 TxData10 Write Access 1 0x 00 low byte Figure 1 Scheme of writing to TxDO Application code Word Write for 1 0 i lt number of words 1 4 SDLM TxDO SDLM TxDO write wordwise i write _wordwise i Byte Write if TxCPU amp Ox1 for 1 0 i1 lt number_of_bytes l 1 2 SDLM_TxDO write_bytewise itl SDLM_TxDO write _bytewise i x Bye if number_of_bytes amp Oxl1 SDLM_TxDO write_bytewise number_of_bytes 1 else for 1 0 i1 lt number_of_bytes l 1 2 SDLM TRDO write_bytewise i SDLM_TxDO write_bytewise itl lt lt 8 if number_of_bytes amp Oxl1 SDLM_TxDO write_bytewise number_of_bytes 1 Reading the receive buffer Storing the information out of the receive buffers somewhere else or directly using the received information can be done byte wise or word wise RxDATA01 RxDATAOO RxDO Figure 2 Readable part of the receiv
13. 000b or 011b and ALE low and RD high b2 00b VCO bypass without oscillator watchdog if pin EA is sampled low and POH 7 5 000b or 011b and both ALE and RD are low b3 11b PLL mode for all other combinations of POH 7 5 if pin EA is sampled low Note that register SYSCON1 is only cleared after a hardware reset therefore bit CPSYS remains at 1 after a software or watchdog timer reset once it had been set by software If CPSYS 1 and any of the above mentioned PLLCTRL transitions 1 3 are executed due to an explicit or implicit write to PLLCON the following effect will occur the clock system is reconfigured according to the value written to register PLLCON but flag PLLWRI remains set at 1 no further reconfigurations or modifications of the clock system are possible neither by writing to PLLCON by software nor by a watchdog timer or software reset The locked state of PLLCON can only be resolved by a hardware reset Workaround 1 Leave SYSCON1 CPSYS 0 default after hardware reset Workaround 2 If CPSYS 1 before performing modifications of PLLCTRL that result in state transitions other than 1Xb lt 1Xb set CPSYS 0 Note that a watchdog timer overflow that causes state transitions of PLLCTRL from 1X lt OX or from 00 lt 01 and which occurs while CPSYS 1 still leads to a locked state of PLLCON Workaround 3 If CPSYS 1 in order to avoid a locked state of PLLCON after a
14. 08 19 3 Deviations from Electrical and Timing Specification Reference XC161CJ Data Sheet V2 2 2003 06 see also Status Sheet The following restrictions should be considered TAP_X 85 Maximum ambient temperature T lt 85 C SAK version only during flash programming FCPUR X 162832 Frequency Limits for Flash Read Accesses For instruction and data read accesses to the internal flash module including programming and erase sequences the frequency limits listed below must be considered otherwise instructions and operands read from the internal flash may become incorrect The problem depends primarily on the internal frequency fcpy and the number of wait states selected for the flash module bit field WSFLASH in register IMBCTR It is statistically more likely to occur when the ambient temperature T is in the upper region of the specified range and when the internal supply voltage Vpp is in the lower region of the specified range When the problem occurs this typically results in a class B trap program access error indicated by flag PACER 1 in register TFR while the flash status register FSR signals single or double bit errors For applications that exceed a specific frequency limit at a given maximum ambient temperature T4 an additional wait state for the flash module will avoid the problem as listed in the tables below No problem will occur in applications that use the following settings and limits a Ambient Tem
15. 16F20F 40F ES AD 6 of 31 Mh Es UK V0 4 2004 08 19 Effect on tools In the Altium Tasking compiler v7 0 and above the problem is not present The result of a MUL DIV instruction is available through the MDL MDH SFRs These SFRs are not allocatable by the register allocator Therefore the compiler always needs a MOV instruction to transfer MDL H to a GPR This avoids the problem In the RT and FP libraries v7 0 and above the problem was not found Versions lower than v7 0 do not explicitly support the C166S V2 core In case optimizations are implemented in future versions which could cause this problem to occur also a workaround will be included All Keil C166 tool Versions compiler and libraries since V3 xx do not generate a MUL U or a DIV L U LU followed by either of the jump instructions JMPR JMPS JMPA JMPI Basically the support of the C166S V2 core requires anyway V4 21 or higher Workarounds e g for program parts written in assembly language generally disable overrun of pipeline bubbles by clearing bit CPUCON2 OVRUN CPUCON2 4 0 This will result only in a negligible performance decrease and will prohibit corruption of the target IP of the JMPI or provide a NOP or any other suitable instruction between the MUL DIV instructions and the succeeding jump in the above cases To simplify place a NOP between any MUL DIV and a JMPR JMPS JMPA JMPI that might follow it Other branches CALLs jump on bi
16. Ah WH A O Under the following conditions the problem described below will occur Message Object X MOx lower priority is in the process of actually being MOY transmitted and then the transmit request bit for Message Object Y MOy higher priority is set via the user software Other message objects MQ MO may be pending for transmission where the priorities are MOQpo gt gt MOy gt gt MOx gt MO gt MO x There is no message object MO which has a valid transmit request and a lower message number than MOy priority of MOx lt priority of MOy Symptom MOK MO is sent twice MO is not sent Aod Detailed Description MO is sent but neither the transmit request is cleared nor bit INTPND is set Also no transmit interrupt is requested for MO Instead TXRQ of MOy is cleared INTPND of MOy is set and a transmit interrupt is requested for MOy if enabled although MOy has actually not been transmitted If NEWDAT has been set for message object MOy then MOy is setup for transmission by the TwinCAN additionally to the INTPND otherwise MOx MOX will be transmitted If NEWDAT has not been set for message object MOy then MOy will not be transmitted at all but the INTPND is set As TxRQ has not been cleared for MOy MOx will be transmitted a second op time The gateway mode is affected as well In case the STT bit is used the error will occur in any case Workarounds a b Remote frames have to
17. C1 Errata Sheet XC161CJ 16F20F 40F ES AD 3 of 31 Mh Es UK V0 4 2004 08 19 1 2 Summary of Open Problems Problem Name _ Short Description Fixed in Step EBC_X 003 TwinCAN access with EBC enabled SDLM_X 001 Reset TXRQ TXCPU CPU_X 002 Branch to wrong target after mispredicted JMPI a reo a e Injected Conversion in Wait for Read Mode ADC Overrun Error Generation when result is read during last cycle of conversion SLEEP_X 001 Wake up trigger during last clock cycle before entry into sleep mode Ls Ls Le Le Double Send TwinCAN2 006 CPUUPDfastset reset o2 222 o y o TwinCAN2 007 ___ Transmit after error o o y o TwinCAN2 008 __ Double remote request sd y o ASC _X 001 ASC Autobaud Detection in 8 bit Modes with Parity LG Le Lo Ss PSW ILVL 2 CMCTR LEVEL FCPUR_X 162832 Frequency Limits for Flash Read Accesses SCU X 009 1 Software or Watchdog Timer Reset while Oscillator is not locked SCU_X 008 1 Modification of register PLLCON while CPSYS 1 OCDS_X 001 BRKOUT pulsing after Instruction Pointer Debug Event Errata Sheet XC161CJ 16F20F 40F ES AD 4 of 31 Mh Es UK V0 4 2004 08 19 1 3 Summary of Application Hints Problem Name ShortDescription Remarks CPU X H1 Configuration of Registers CPUCON1 and CPUCON2 CPU X H2 Special Characteristics of VO Areas FLASH X H2 1 Access to Flash Module after Wake Up from Sleep Idle Mode or steps gt AC Shut Down Flash 28 1 Read Acc
18. DAT In the interrupt service routine read the result register DAT twice In case a lock situation had occurred the second dummy read access will terminate the lock situation the next conversion result n 1 will be transferred to DAT and interrupt request flag ADCIR will be set such that the result n 1 will be read correctly in the associated interrupt service routine Interference with injected conversions is avoided by disabling them temporarily The sequence in the interrupt service routine for standard conversions is e g BCLR IEN disable interrupts to shorten time where injected conversions are disabled BCLR ADCIN temporarily disable injected conversions to avoid conflict between read of DAT and start of injected conversion for 2 and 3 read OL DAT 1 read covered by workaround MOV Rx Ry gt read and store conversion result n Rx points to table for results gt Ry p oints to DAT NOP wait 3 clock cycles before reading ADCIR NOP NOP JB ADCIR Label Done gt if ADCIR 1 result of next conversion will be read in next invocation of this interrupt service routine wait for read protection is effective MOV dummy DAT second read of result n workaround NOP wait 3 clock cycles before reading ADCIR NOP NOP JNB ADCIR Label Done tf ADCIR Ly a Conversion Nas Just 1 unushed BCLR lt ADCLE Clear interrupt request flag MOV Rx Ry gt read and store conversion r
19. DS X 001 BRKOUT pulsing after Instruction Pointer Debug Event When the ACTIVATE_PIN bit of any DxxEVT register is set and a debug event occurs the BRKOUT pin is Supposed to be asserted as long as the debug event condition is met However when software debug mode is specified as event action in addition to asserting BRKOUT and the jump into the monitor program takes place BRKOUT will toggle once for each instruction of the monitor program that is executed This problem does not occur when software debug mode is not specified as event action e g when halt debug mode is used Workaround set DxxEVT ACTIVATE_PIN 0O at the beginning of the monitor program and set DxxEVT ACTIVATE PIN 1 at the end Note that not all toggles first last instruction of monitor program can be avoided by this method Errata Sheet XC161CJ 16F20F 40F ES AD 16 of 31 Mh Es UK V0 4 2004 08 19 OCDS X 002 OCDS indicates incorrect status after break_now requests if PSW ILVL gt CMCTR LEVEL When the OCDS processes a break_now request while the CPU priority level in PSW ILVL is not lower than the OCDS break level in CMCTR LEVEL the actual break is delayed until either PSW ILVL or CMCTR LEVEL is reprogrammed such that CMCTR LEVEL gt PSW ILVL If in the meantime further debug events have occurred register DBGSR will still indicate the status of the first break_now request If e g a software break is executed the OCDS will accept this but registe
20. IC_IR for standard conversions or ADC_EIC_IR for injected conversions instead of ADBSY BSL X H1 1 Using the Bootstrap Loader over a Single Wire Connection Beginning with step ES AB the bootstrap loader has been improved such that the transmission of the acknowledge byte is not started before the stop bit time slot of the last character received has been Errata Sheet XC161CJ 16F20F 40F ES AD 22 of 31 Mh Es UK V0 4 2004 08 19 completed This avoids a collision of the start bit of the acknowledge byte with the stop bit of the last received character sync byte when a single wire connection is used BREAK X H1 Break on MUL DIV followed by zero cycle jump When a MUL or DIV instruction is immediately followed by a falsely predicted conditional zero cycle jump JMPR or JMPA on any condition other than cc_UC and either a break now request is set at the time the MUL DIV instruction is being executed i e a break request on operand address data task ID BRKIN pin etc is generated by one of the instructions may be up to four preceding MUL DIV ora break before make request break on IP address is derived from the instruction immediately following the jump jump target or linear following address depending whether the jump is taken or not then the internal program counter will be corrupted equal to last value before jump which will lead to a false update of the IP with the next instruction modifying the IP
21. O area 00 E000h 00 EFFFh including IIC and SDLM module on XC 161 the 2 Mbyte external I O area 20 0000h 3F FFFFh including the TwinCAN module default from 20 0000h 20 07F Fh lt is therefore recommended to map devices which do not tolerate speculative reads into the 2 Mbyte external I O area 20 0000h 3F FFFFh Errata Sheet XC161CJ 16F20F 40F ES AD 19 of 31 Mh Es UK V0 4 2004 08 19 For further special properties of the I O areas see p 3 13 in the XC161 User s Manual V2 0 Volume System Units 2003 03 FLASH X H1 1 Access to Flash Module after Program Erase After the last instruction of a program or erase command the BUSY bit in register FSR is set to 1 status busy after a delay of one instruction cycle When polling the BUSY flag one NOP or other instruction which is not evaluating the BUSY flag must be inserted after the last instruction of a program or erase command No additional delay is required when performing the first operand read or instruction fetch access from the flash module after the BUSY bit has returned to 0 status not busy FLASH X H2 1 Access to Flash Module after Wake Up from Sleep Idle Mode or Shut Down In order to reduce power consumption the devices of the XC166 family allow to selectively disable individual modules The flash module may be disabled upon entry into Idle or Sleep mode selection in register SYSCON1 and it will be automatically re enabled after wake up from idl
22. P NOP JB ADCIR Label Done gt TE ADCIR ty result of next conversion will be read in next invocation of this interrupt service routine wait for read protection is effective ATOMIC 4 MOV dummy DAT second read of result n workaround NOP wait 3 clock cycles before reading ADCIR NOP ATOMIC 3 JNB ADCIR Label_Done if ADCIR 1 a conversion has just finished BCLR ADCIR gt clear interrupt request flag MOV Rx Ry read and store conversion result n 1 Rx points to table for results hy pPornts co DAT if required emulation of PEC COUNT function SUB s_count 1 decrement counter for standard conversions Label Done SUB S Ccount 1 decrement counter for standard conversions JMPR cc_NZ Label_End ad S Coun 0 y pe lLude code for Nandiling Of S COUnE assumes that no further conversion is Started after s_count 0 and same interrupt as for reading the results is 7 used Label End RET I This routine has only the timing requirement that the 7 instructions in the ATOMIC 4 ATOMIC 3 sequence from the dummy read until the result is stored in case a new conversion Is finished are executed within tc ADC conversion time Errata Sheet XC161CJ 16F20F 40F ES AD 8 of 31 Mh Es UK V0 4 2004 08 19 Workaround 2 2 for standard conversions if injected conversions are used in parallel Use an interrupt service routine to read the results of standard conversions from register
23. SRST or WDT reset will not change the settings of the clock system Also if an oscillator fail condition or PLL unlock event occurs in this mode the clock system will remain unchanged However a PLL OWD interrupt flag PLLIR will be generated The failure mode can only be resolved by a hardware reset rising edge at pin RSTIN Workaround 1 Before executing a SRST instruction wait until the clock system is stable Ifthe PLL is used in locked mode wait until OSCLOCK 1 PLLLOCK 1 and PLLWRI 0 For other clock configurations wait until OSCLOCK 1 and PLLWRI 0 Make sure that the remaining watchdog time interval will cover the oscillator start up and lock time after wake up from sleep mode This is typically about 6 ms for a 4 MHz crystal and about 1 ms for a 16 MHz crystal Workaround 2 Use an external clock source with permanent oscillation In this case only 2048 clock cycles need to be considered for the remaining watchdog time interval Workaround 3 1 step gt AD only Use the clock from XTAL1 as clock source for the real time clock RTC and do not switch off the RTC during sleep mode i e set RTC_CON 0 RUN 1 and RTC_CON 4 REFCLK 1 ltems in OCDS and OCE Modules The following issues have been found in the OCDS and OCE modules Please see the debugger or emulator manufacturer s documentation whether or not these issues actually cause a problem or restriction when the respective tool is used OC
24. WDAT is set AS a consequence the remote request is transmitted once again Workaround Clear NEWDAT after the reception of a data frame ASC X 001 ASC Autobaud Detection in 8 bit Modes with Parity The Autobaud Detection feature of the Asynchronous Synchronous Serial Interface ASC does not work correctly for 8 bit modes with even or odd parity The Autobaud Detection feature works correctly for 7 bit modes with even or odd parity and for 8 bit modes without parity Workaround None SCU_X 008 1 Modification of register PLLCON while CPSYS 1 After a hardware reset if bit SYSCON1 CPSYS has been set to 1 by software certain modifications of the clock generation mode in bit field PLLCON PLLCTRL will result in incorrect clock control behavior The following PLLCTRL transitions will result in incorrect behavior and must be avoided by the user 1 1xb Oxb x don t care 2 00b any value other than 00b 3 01b any value other than 01b These transitions include not only explicit modifications of PLLCON by software but also implicit modifications of PLLCON by a watchdog timer reset A watchdog timer reset will implicitly set PLLCON PLLCTRL to a 01b VCO bypass with oscillator watchdog if pin EA is sampled high start from internal flash Errata Sheet XC161CJ 16F20F 40F ES AD 14 of 31 Mh Es UK V0 4 2004 08 19 b1 01b VCO bypass with oscillator watchdog if pin EA is sampled low and POH 7 5
25. afe start up The gain may be reduced when the oscillations have reached their full amplitude For standard crystals or ceramic resonators this is typically 2 32768 cycles of f after bit OSCLOCK 1 and if the PLL is used PLLLOCK 1 in register SYSSTAT After reset the internal reset sequence ensures that OSCLOCK 1 and PLLLOCK 1 before the first instruction of the application software is executed unless a problem with the oscillator circuit is detected in this case flag PLLIR 1 Errata Sheet XC161CJ 16F20F 40F ES AD 30 of 31 Mh Es UK V0 4 2004 08 19 If the RTC is not running on the main oscillator during sleep mode i e the main oscillator is off during sleep mode bit SYSCON 12 OSCGRED should be set to 0 high gain before entry into sleep mode to guarantee safe oscillator start up after wake up from sleep SCU_ X D2 Functionality of register OPSEN When a breakpoint is hit the on chip peripherals selected in register OPSEN are stopped and placed in power down mode the same way as if disabled via register SYSCONS3 Registers of peripherals which are stopped this way can be read but not written A read access will not trigger any actions within a disabled peripheral Application hint BREAK_X H2 Behavior of on chip peripherals after Break which was valid for step AC and earlier steps is therefore removed for the Errata Sheet of step AD and newer steps Note also the following documentation update
26. ccur during the last clock cycles before sleep mode is entered In case the CLKOUT signal is used for synchronization please note the following o the internal spike filter on the external interrupt input pins may have a maximum delay of 100 ns o ifthe output pins are switched off during sleep mode SYSCON1 PDCFG 01b the last internal clock cycle is no longer visible on pin CLKOUT i e the output drivers are turned off one cycle before the internal clock is turned off Workaround 2 Before entering sleep mode set the PLL to a configuration where it can not lock theoretical output frequency lower than VCO base frequency After wake up from sleep mode reconfigure register PLLCON to the desired clock mode e g device is running in desired clock mode on desired target frequency BCLR IEN disable interrupts Label_enter_sleep EXTR 1 MOV PLLCON 618Eh this configuration is expected not to allow 2 Che PEL CO LOCK IDLE enter sleep mode Label_reconfigure_clock EXTR 1 Tirst AUNSeCruct1 on alter wake up MOV PLLCON target_val reconfigure target clock mode and frequency Label_wait_for_target_clk if defined frequency is required wait until MOV Rx PLLCON y target clock has stabilized PLLODIV OFh CMP Rx target_val JMPR cc_NE Label_wait_for_target_clk BSE TEN enable interrupts Errata Sheet XC161CJ 16F20F 40F ES AD 11 of 31 Mh Es UK V0 4 2004 08 19 TwinCAN2 005 Double Send ON On
27. e buffer in FIFO mode Accessing RxD0 leads to the following readout Errata Sheet XC161CJ 16F20F 40F ES AD 25 of 31 Mh Es UK V0 4 2004 08 19 0x0 RxDATAOO first read RxDATAO1 0x0 m second read Figure 3 Reading RxDO in FIFO mode Here again the software application can handle the FIFO in two different ways Application code Read Words number of words RxCNT number of words number_of words gt gt 1 number _of words amp 0x1 for 1 0 i lt number_of words i read_wordwise i SDLM_RxDOO SDLM _RxDOO Read Bytes received_bytes RxCNT for 1 0 i lt received_bytes 1l TF2 read_bytewise i SDLM_RxDOO read_bytewise itl SDLM_RxDOO gt gt 8 if received_bytes amp amp 0x1 read_bytewise received_bytes 1 SDLM_RxDOO By using these techniques a simple access of the Transmit as well as the Receive FIFO can be guaranteed SCU_X H1 Shutdown handshake by software reset SRST instruction In the pre reset phase of the software reset instruction the SCU requests a shutdown from the active modules equipped with shutdown handshake see Section 8 3 4 in User s Manual volume System Units The pre reset phase is complete as soon as all modules acknowledge the shutdown state As a consequence e g the A D converter will only acknowledge the request after the current conversion is finished fixed channel single conversion mode or after conversion of channel 0
28. e sleep Like other on chip peripheral modules the flash module may also be shut down turned on by software flexible peripheral management via register SYSCONS while not required during specific operating periods of an application Since the transition from active to inactive state and vice versa requires several clock cycles some special situations have to be considered when access to the flash is required directly after wake up If during entry into sleep or idle mode where the flash module shall be disabled bit field PFCFG 01b in register SYSCON1 awake up event PEC interrupt NMI occurs before the flash deactivation process is complete andthe corresponding PEC transfer or interrupt trap routine wants to access operands or instructions in the internal flash then the flash access is automatically delayed until the flash is ready again When the flash is disabled by software shut down by writing bit PFMDIS 1 in register SYSCONS and itis at some later time enabled again by writing PFMDIS 0 and the instruction immediately following the instruction which sets PFMDIS 0 Is fetched or reads operands from internal flash then the PACER flag in register TFR is set and the BIRAP routine is entered Therefore it is recommended to insert 4 NOPs before the internal flash is accessed again after PFMDIS has been set to 0 FLASH X H3 1 Read Access to internal Flash Module with modified Margin Level 1 When the internal
29. ess to internal Flash Module with modified Margin Level a a oo IDLE_X H1 Entering Idle Mode after Flash Program Erase ADC_X H1_ PollingofBitADBSY SS S o BREAK_X H1 Break on MUL DIV followed by zero cycle jump dIC_X H1 Maximum IIC Bus Data Rate atlowf o o o o So o y o diC_X H2 Timingof BtIRQD _ _ SSS S o POWER_X H1 Initialization of SYSCONS for Power Saving Modes POWER_X H2 1 _ Power Consumption during Clock System Configuration SDLM_X H1 Writing the Transmit Buffer and reading the Receive Buffer in FIFO Mode SCU_X H1 Shutdown handshake by software reset SRST instruction Ea SCU X H3 Effect of PLLODIV on Duty Cycle of CLKOUT SCU X H4 Changing PLLCON in Emergency Mode RTC_X H1 1 Resetting and Disabling of the Real Time Clock lt TwinCAN_X H1 Minimum f for TwinCAN module V2 2 p 21 46 ADC_X H2 Handling of Results of Injected Conversions by the A D Converter V2 2 p 16 15 Errata Sheet XC161CJ 16F20F 40F ES AD 5 of 31 Mh Es UK V0 4 2004 08 19 2 Functional Problems EBC X 003 TwinCAN Access with EBC enabled lf the External Bus Controller EBC is enabled a read or write access to the TwinCAN module fails when an external bus access with TCONCSx PHA 00b precedes the TwinCAN access Workaround Since it is hard to predict the order of external bus and TwinCAN accesses in particular when PEC transfers are involved it is recommended to set bitfield PHA to 00 in al
30. esult n 1 Rx points to table for results oy ERY HOt Ss tOo DAT 7 if required emulation of PEC COUNT function SUB lt 6 count FI decrement counter for standard conversions Label_Done BSET LEN enable interrupt system again BSET ADCIN enable injected conversions again SUB s count Fil decrement counter for standard Conversions JMPR cc_NZ Label_End 5 GE S Count U include code for handling of s_count 0 assumes that no further conversion is Started after s_count 0 and same interrupt as for reading the results is used Label End RETI This routine has only timing requirement that the 7 instructions from the dummy read MOV dummy DAT until the result is stored in case a new conversion is finished are executed within tc ADC conversion time Note that this instruction sequence can not be interrupted because interrupts have been disabled to avoid interference with injected conversions Errata Sheet XC161CJ 16F20F 40F ES AD 9 of 31 Mh Es UK V0 4 2004 08 19 Workaround 3 In order to avoid the problem make sure that only one conversion is started at a time a For standard conversions Instead of continuous and auto scan conversion modes use a sequence of fixed channel single conversions which are started in the ADC conversion complete interrupt service routine triggered by ADCIR after the result of the previous conversion has been read from register DAT b For injected conversions
31. for XC161CJ 16F devices with marking ES AD AD to this Errata Sheet Rev 0 4 for XC161CJ 16F devices with marking ES AD AD Documentation Reference updated XC161 User s Manual V2 2 Volume 1 2 System Peripheral Units 2004 01 printed version Description of the following problems added Frequency Limits for Flash Read Accesses FCPUR_X 162832 see section Deviations from DC AC Specification Modification of register PLLCON while CPSYS 1 SCU_X 008 1 Software or Watchdog Timer Reset while Oscillator is not locked SCU_X 009 1 ASC Autobaud Detection in 8 bit Modes with Parity ASC_X 001 The following Application Hint has been added Timing of Bit IRQD IIC_X H2 The following text has been added in section Documentation Update duration of internal reset sequence ta 20 t instead of 2 t Errata Sheet XC161CJ 16F20F 40F ES AD 2 of 31 Mh Es UK V0 4 2004 08 19 1 1 Summary of Fixed Problems Problem Name _ Short Description Fixed in Step Power Loss Operation S Power Loss Operation EES AA EES AA EES AA EES AA EES AA EES AA EES AA EES AA FLASH_X 001 Flash Access Error Trap gt replaced by Application Hint PMI EES AA Access Error in TC1 EES devices EES AA EES AA EES AA EES AA EES AA EES AA EES AA Acknowledge of PEC Transfers gt fixed by new default value in CPUCON2 gt fixed by new default value in CPUCON2 INT X 003 Dynamic change of
32. g restrictions a Remote frames will not be received by the message object during the time where the message object is tagged invalid b You may lose the transmit interrupt for the already set transmit request c In case no remote frames exist in the system reset TxRQ and set CPUUPD change the message object and set TxRQ and reset CPUUPD again Errata Sheet XC161CJ 16F20F 40F ES AD 13 of 31 Mh Es UK V0 4 2004 08 19 TwinCAN2 007 Transmit after Error During a CAN error transmission may stop after EOF or an error frame until a successful reception or a write access to the TwinCAN module Detailed Description In case of a CAN error and there is no other activity on the CAN module e g frame reception frame transmission on the other CAN node write access to any CAN register the transmission of messages may stop even if some transmit requests are still set The CAN module will start transmitting immediately after a reception or a write access to the module Workarounds a Write periodically OxFFFF to one of the MSGCTRx registers as this value is having no effect on the register b Incase writing to a CAN register shall be the exception use the last error code LEC interrupt This shall start writing to one of the MSGCTRx register OxFFFF in case the LEC value is unequal to 0 TwinCAN2 008 Double remote request After the transmission of the remote request TXRQ is not cleared in the receive object if NE
33. h Es UK V0 4 2004 08 19 If the RTC was not running on the main oscillator the system will not be clocked until the amplitude on the external oscillator input XTAL1 exceeds the input hysteresis This requires typ a few ms depending on external crystal oscillator circuit With this mode there is no oscillator watchdog function and the system will not be clocked until the external oscillator input XTAL1 receives a clock that exceeds the input hysteresis e In bypass mode with VCO on PLLCTRL 01b the device will directly continue to run on the frequency derived from the external oscillator input after wake up from sleep if the RTC is running on the main oscillator If the RTC was not running on the main oscillator the device will wake up and run using the internal PLL base frequency from the VCO f 16 until the oscillator input XTAL1 is locked and then switch to the frequency derived from the external oscillator input e In PLL mode with input clock from XTAL1 disconnected PLLCTRL 10b the device will only wake up from sleep if the RTC was not running on the main oscillator i e when the main oscillator is off during sleep mode In this case the device will run using the internal PLL base frequency from the VCO f 16 until the oscillator input XTAL1 is locked and then switch to f k with the output divider selected by PLLODIV base If the RTC is running on the main oscillator the device will not wake up from sleep
34. ill set for MOX CAN_HWOBJ ubObjNr uwMSGCTR 0xDFFF reset TxRO if CAN_HWOBJ ubObjNr uwMSGCTR amp 0x2 Incase the message has been transmitted before resetting the TxRQ here the INTPND is detected TXRQs ubObjNr 1 Set TxRQ in Softwaretable Wait the length of two CAN frames for ubObjNr 0 ubObj JNr lt 32 ubOb jNr for all message objects do if TXRQs ubObjNr if TxRQ is set in Softwaretable for MOX if CAN_HWOBJ ubObjNr uwMSGCTR amp 0x2 In case the message has been transmitted before resetting the TxR here the INTPND is detected TXRQs ubObjNr 0 Reset TxRQ in Softwaretable else CAN_HWOBJ ubObjNr uwMSGCTR 0xe ff Set TxRO TXRQs ubObjNr 0 reset TxRQ in Softwaretable End of function CC1_viTmr0 TwinCAN2 006 CPUUPD fast set reset In case TxRQ is set and CPUUPD in MSGCTR is set and reset within forty CAN cycles the message data might be corrupted Detailed Description If a transmit request is set for a message object and this object is currently transmitted while at the same time the user application set CPUUPD to change the information then a mixture of the former information and new information may be sent This is only the case if CPUUPD Is set and reset within 40 CAN cycles Workarounds a Between setting and resetting CPUUPD there has to be a time distance of 40 CAN cycles b Use MSGVAL The application will have the followin
35. in register CON1 and no conversion is in progress indicated by bit ADBSY 0 in register CON This is possible in enhanced mode bit MD 1 in register CTRO as well as in standard mode MD 0 Note 2 The accuracy of the ADC depends to a great extent on the stability of the reference voltage V in particular during the reset calibration phase 3 The ADC is currently tested with post calibration enabled The accuracy with post calibration disabled is guaranteed by design RTC X D2 Real Time Clock Source Selection The clock source for the RTC can be selected by software via bit REFCLK bit position RTC_CON 4 REFCLK 0 RTC count clock signal is fscax input XTAL3 REFCLK 1 RTC count clock signal iS fscman 32 input XTAL1 Register RTC_CON is not affected by a hardware software watchdog reset After power up it is undefined A reset of the RTC module is achieved by setting bit SYSCONO 15 RITCRST 1 This way register RTC_CON is set to 8003h RTC runs prescaler by 8 enabled synchronous mode bit REFCLK 0 As a general recommendation bit REFCLK should be set to the desired value after any start up hardware software watchdog reset and whenever the RTC module is reset by setting bit SYSCONO 15 RTCRST 1 SCU_X D1 Oscillator gain reduction The gain of the main oscillator pins XTAL1 2 may be reduced via software by setting bit SYSCON 12 OSCGRED 1 After reset high gain is selected by default to guarantee s
36. is still derived from the VCO and if a relatively small value k is written to PLLODIV this results in the system running on an internal frequency of fvco k that may exceed the specified frequency limit for the device In general it is recommended to wait until PLLODIV lt OFh before PLLCON is written Use a timeout limit in case a permanent clock failure is present FOCON X H1 Read access to register FOCON Bit FOTL and bit field FOCNT in register FOCON are marked as rh in the User s Manual i e they can not be modified by software If register FOCON is read directly after it was written the value read back from the positions of FOTL and FOCNT represents the value that was written by the preceding instruction but not the actual contents of FOTL and FOCNT In order to obtain correct values for FOTL and FOCNT either insert one NOP or other instruction that does not write to FOCON or read FOCON twice and discard the first result Errata Sheet XC161CJ 16F20F 40F ES AD 27 of 31 Mh Es UK V0 4 2004 08 19 RTC X H1 1 Resetting and Disabling of the Real Time Clock The clock source for the RTC can be selected by software via bit REFCLK bit position RTC_CON 4 REFCLK 0 RTC count clock signal is foscaux input XTALS REFCLK 1 RTC count clock signal is foscmain 32 input XTAL1 Register RTC_CON is not affected by a hardware software watchdog reset After power up it is undefined A reset of the RTC module is achieved by set
37. l TCONCSx registers which are used for external bus accesses SDLM_X 001 Reset TXRQ TXCPU A reset on bit TXRQ in register BUFFCON by software should reset the register TXCPU This is the case If blockmode bit BMEN register GLOBCON is enabled Failure In all other cases TXCPU is not reset if TXRQ is reset by software Note This problem is referred to as SDLM 11 in C161JC JI devices Workaround Reset TXCPU by software CPU_X 002 Branch to wrong target after mispredicted JMPI After a JMPI is initially mispredicted according to the static branch prediction scheme of the C1668 V2 code execution may continue at a wrong target address in the following situations Situation I a memory write operation is processed by the DMU followed by a MUL U followed by the mispredicted JMPI Example_1 MOV mem Rwn MUL R13 R14 JMPI cc_NV R6 Situation II MUL U or DIV L U LU followed by not mispredicted zero cycle jump e g JMPA JMPR JMPS bit CPUCON1 ZCJ 1 followed by the mispredicted JMPI Example_2a MULU R13 R14 JMPA cc_V _some_target predicated not taken gt correct JMPI ce NV R6 taken but predicted not taken It could be possible that the JMPI is at the jump target of the JMPA if it is taken Example_2b MULU R13 R14 JMPA CGONA lt ompa adar predicted taken gt correct oe eee GEREH COOC esri oadd WIMP ice INV RG taken but predicted not taken Errata Sheet XC161CJ
38. ld POCONz PDMyN 0011 0100 0101 0110 0111 Notes 1 There is no difference in the port output characteristics driver strength edge shape between the 3 selections for medium driver mode PDMyN 010Xb 0110b The electrical characteristics are comparable to medium driver sharp edge mode of the XC16x 16F step AB devices 2 Currently weak driver mode is selected for setting 0111b However there will be approximately 30 UA low level to 80 uA high level additional current on Vddp per pin which is configured as output in weak driver mode To avoid this use only setting 0011b for weak driver mode Errata Sheet XC161CJ 16F20F 40F ES AD 29 of 31 Mh Es UK V0 4 2004 08 19 Modifications in step AD and future devices The following modifications have been performed on devices with stepping code marking AD and higher ADC X D2 A D Converter Characteristics Conversion Time In order to increase accuracy the conversion time with post calibration default after reset is extended by 4t as follows with post calibration without post calibration 8 bit b 44t b 6b t 32t b 6h 2 75us f 20MHz 2 15us f 20MHz 10 bit bio 921 b 6hy bio 408 b 6hy 3 15us f 20MHz 2 55us f 20MHz 1 For time critical applications post calibration may be disabled by software set bit CALOFF 1 in register CTRO after the reset calibration is finished indicated by bit CAL 0
39. n to identify an overrun situation SLEEP X 001 Wake up trigger during last clock cycle before entry into sleep mode When the wake up trigger from the RTC or from the NMI or external interrupt input pin occurs in a specific time window the device will not wake up from sleep mode until a hardware reset is asserted on pin RSTIN In general this problem occurs when all of the following conditions are true 1 the wake up trigger occurs during the last clock cycle before the device enters sleep mode 2 the VCO is involved in the clock generation i e PLLCTRL 11b 10b 01b The same effect may occur if due to software malfunction the device is about to enter sleep mode and a watchdog timer reset occurs during the last clock cycle before the device enters sleep mode This problem does not occur in direct drive mode where the VCO is off PLLCTRL 00b Errata Sheet XC161CJ 16F20F 40F ES AD 10 of 31 Mh Es UK V0 4 2004 08 19 Workaround 1 In order to avoid the problem when PLLCTRL 00b make sure that the wake up trigger only occurs after the device has already entered sleep mode check the RTC before entering sleep mode If the wake up trigger will occur soon either skip entry into sleep mode or extend the time for the next wake up If the RTC time interval is reprogrammed make sure that no interrupt occurs between reprogramming and entry into sleep mode synchronize external wake up events such that they do not o
40. perature 40 C lt Ta lt 85 C fcpu Number of wait states for flash module fopy lt 16 MHz OWS WSFLASH 00b 16 MHz lt fopy lt 32 MHz 1WS WSFLASH 01b default after reset fopy gt 32 MHz 2WS WSFLASH 10b b Ambient Temperature T gt 85 C fcpu Number of wait states for flash module fopy lt 16 MHz OWS WSFLASH 00b 16 MHz lt fopy lt 28 MHz 1WS default after reset WSFLASH 10b Note fepy max 40 MHz for devices marked 40F and fcpy max 20 MHz for devices marked 20F Errata Sheet XC161CJ 16F20F 40F ES AD 18 of 31 Mh Es UK V0 4 2004 08 19 The performance decrease due to an additional wait state depends on the individual characteristics of the software Due to the internal instruction prefetch queue the average performance decrease when using 1 wait state instead of 0 wait states is expected to be approximately 5 and approximately 15 when using 2 wait states instead of 1 wait state 4 Application Hints CPU X H1 Configuration of Registers CPUCON1 and CPUCON2 The default values of registers CPUCON1 and CPUCON2 have been chosen to provide optimized performance directly after reset It is recommended notto modify the performance related parts 3 LSBs of register CPUCON1 not to modify register CPUCON2 except for test purposes or for enabling specific workarounds under special conditions see e g problem CPU_X 002 or application hint BREAK_X H1 CPUCON2
41. r DBGSR will indicate the wrong cause of break Workarounds 1 If the application uses tasks with different levels and debugging is to take place using the OCDS break level feature e g only tasks up to a maximum level are halted higher level tasks aren t halted and the OCDS level is programmed in between there is no problem if only classic hardware breakpoints IP address or software breakpoints are used i e no trigger on address data TASKID no external pin assertions are used to trigger breaks no direct writes to DBGSR DEBUG_ STATE are used to force breaks 2 If break_now request sources are to be used the maximum level of the application PSW ILVL should always be lower than the programmed OCDS break level e g PSW ILVL lt 14d CMCTR LEVEL 15d This means that all generated break_now requests by the OCDS will always be accepted independent of the CPU interrupt priority OCE X 001 Wrong MAC Flags are declared valid at Core OCE interface In case a MAC instruction Co is directly followed by a MOV MSW data16 instruction the upper byte of data16 is output instead of the flags corresponding to the MAC instruction The bug was found with code coshr 00001h mov MSW 00100h other variations of datal6 Workaround Add a NOP between the two instructions cosnr 00001 nop mov MSW 00100h other variations of datal6 Errata Sheet XC161CJ 16F20F 40F ES AD 17 of 31 Mh Es UK V0 4 2004
42. reset recommended value 8FBBh enables several performance features CPUCONT1 reset recommended value 0 0 OXXX X111 only the 3 Isbs are performance related Name CPUCON1 15 7 0 0 reseved O o S O CPUCON1 6 5 VECSC ka scaling factor for vector table value depends on application 00 is compatible to C166 systems CPUCON1 4 WDTCTL configuration for scope and function of DISWDT ENWDT instructions value depends on application 0 is compatible to C166 systems CPUCON1 3 SGTDIS gt e enable disable control value depends on application CPUCON1 2 INTSCXT enable interruptibility of switch context CPUCON1 1 BP 1 enable branch prediction unit CPUCON1 0 enable zero cycle jump function CPU_X H2 Special Characteristics of I O Areas As an element of performance optimization the pipeline of the C166S V2 core may perform speculative read accesses under specific conditions In case the prediction for the speculative read was wrong the read to the actually required location is restarted While this method Is uncritical e g for accesses to non volatile memories or SRAMs it may cause problems on devices which do not tolerate speculative reads e g FIFOs which are advanced on every read access No speculative reads are performed in memory areas which are marked as I O area This memory area includes the SFR and ESFR space e g with buffers for received data from serial interfaces or A D results the 4 Kbyte internal I
43. ring Power Down mode during Sleep mode or during Idle mode with no PEC transfers enabled After any reset RAM locations in the following area are used by the internal start up code and will therefore be overwritten OFBAOh OFC1Fh Programs that e g perform RAM checksum calculations after reset should exclude this memory area SCU_X H3 Effect of PLLODIV on Duty Cycle of CLKOUT When using even values 0 14 for the output divider PLLODIV in register PLLCON the duty cycle for signal CLKOUT may be below its nominal value of 50 This should only be a problem for applications that use both the rising and the falling edge of signal CLKOUT When using odd values 1 15 for PLLODIV where PLLODIV 15 OFh is selected by hardware only during clock system emergency mode or reconfiguration the duty cycle for signal CLKOUT is on its nominal value of 50 PPLLODIV 0 2 ol T 33 oa 42 86 A 44 45 45 46 13 46 67 Cycle SCU_X H4 Changing PLLCON in emergency mode While the clock system is in emergency mode e g after wake up from sleep or due to an external clock failure the clock output divider is set to 16 i e PLLODIV OFh in register PLLCON Emergency mode is terminated if the internal oscillator lock counter has received 2048 clock ticks from XTAL1 lf PLLCON is written in emergency mode all settings except bypass modes PLLCTRL 0Xb become effective immediately within a few clock cycles As long as the system clock
44. s for some versions of the User s Manual volume System Units SYSCONS 10 ASC1DIS all XC16x SYSCONS 8 CC6DIS XC164 XC167 OPSEN 13 CANSEN all XC16x It is recommended to leave bit OPSEN 5 PFLSEN at its default value 0 Otherwise the program flash is deactivated when a breakpoint is hit i e it can not be read and it has to ramp up when program execution is resumed i e synchronization between software and peripherals is lost SCU_X D3 Register PLLCON after software reset Register PLLCON is not affected by a software reset i e the current clock configuration remains unchanged PLLCON may be reconfigured by software or an endless loop terminated by a watchdog timer reset may be used to force PLLCON to its hardware reset value SCU_ X D4 VCO band after hardware watchdog reset in single chip mode From the falling edge of RSTIN until 2048 stable oscillator clocks after the rising edge of RSTIN always the highest VCO band is selected see POWER_X H2 1 After that for a hardware or watchdog timer reset in single chip mode PLL bypass mode with the lowest VCO band is selected during the internal reset phase PLLCON 2710h Product and Test Engineering Group Munich Errata Sheet XC161CJ 16F20F 40F ES AD 31 of 31 Mh Es UK V0 4 2004 08 19
45. t instructions do not need to be taken into account ADC X 003 Coincidence of Result Read and End of next Conversion or Start of Injected Conversion in Wait for Read Mode When the A D Converter operates in wait for read mode bit ADWR 1 in register ADC_CON or ADC_CTRO respectively and the result of a previous standard non injected conversion n is read from the result register ADC_DAT in the same clock cycle as the ADC a completes the next standard conversion n 1 or b starts an injected conversion after conversion n 1 has been completed at some earlier time the following problem will occur the interrupt request flag ADCIR for standard conversions is not set the result of conversion n 1 is not transferred to the result register ADC_DAT This leads to a lock situation where the ADC will not perform further standard conversions since there is no trigger interrupt request for the PEC or interrupt service routines to read the results Further injected conversions are performed correctly Workaround 1 for standard conversions with or without injected conversions In order to avoid the problem make sure that the method interrupt routine or PEC transfer that is used to read the results of standard conversions can keep track with the conversion rate of the ADC i e make sure that no wait for result read situation occurs In this context the following points may be considered Errata Sheet XC161CJ 16F20F 40F ES AD
46. ted in bit field PLLODIV in register PLLCON which returns the value Fh when read during this reconfiguration phase When the reconfiguration is complete PLLLOCK 1 and PLLODIV returns the value which was written to PLLCON When the PLL is about to be reconfigured i e an instruction which writes to PLLCON has been executed and no bypass mode has been selected and sleep mode is entered instruction IDLE is executed before the PLL has locked on the new frequency then after wake up from sleep mode the device will stay in clock system emergency mode flagged by SYSSTAT PLLEM 1 with f f 16 even after the oscillator has locked again Therefore it is recommended not to enter sleep mode before the PLL has locked i e wait until bit OSCLOCK 1 PLLLOCK 1 and bit field PLLODIV lt OFh SLEEP X H3 Clock system after wake up from Sleep Mode There are different wake up behaviors depending on the PLL control setting used in register PLLCON during entry into sleep mode and depending on whether the RTC is running on the main oscillator Note that in either case the VCO is turned off during sleep mode and does not contribute to any additional power consumption e In bypass mode with VCO off PLLCTRL 00b the device will directly continue to run on the frequency derived from the external oscillator input after wake up from sleep if the RTC is running on the main oscillator Errata Sheet XC161CJ 16F20F 40F ES AD 21 of 31 M
47. til the flash is ready after wake up from sleep or idle mode e g define a semaphore bit that is set to 1 before the IDLE instruction is executed All trap and interrupt service routines invoked after wake up from idle sleep should clear this bit to 0 disable interrupts execute the IDLE instruction if idle or sleep mode is terminated by an interrupt request the instructions following the IDLE instruction will be executed the interrupt request flags remain set if idle or sleep mode was terminated by an NMI the trap handler will be invoked enable interrupts to allow prioritization of requests for interrupt or PEC service the instructions following the IDLE instruction should test the flash BUSY bit in register FSR when the flash is ready and at least 12 instructions have been executed after the interrupt system has been enabled and if the semaphore bit is still at 1 i e no interrupts traps have occurred disable interrupts and return to the IDLE instruction SLEEP X H1 Sleep Mode during PLL Reconfiguration The PLL may be reconfigured by software by modifying the settings in register PLLCON When PLLCON is written to and the PLL was locked at that time flag PLLLOCK in register SYSSTAT is cleared to 0 to indicate that a reconfiguration of the clock system is in progress In addition in order not to exceed the internal frequency limits the clock divider K is set to 16 such that f f 16 This is indica
48. ting bit SYSCONO 15 RITCRST 1 This way register RTC_CON is set to 8003h RTC runs prescaler by 8 enabled bit REFCLK 0 The RTC clocking mode synchronous asynchronous is determined by bit SYSCONO 14 RTCCM Note that register SYSCONQO is not affected by a software or watchdog reset This means that when a software or watchdog reset occurred while the RTC module was in asynchronous mode selected by bit SYSCONO 14 RTCCM 1 it will return to asynchronous mode after a RTC reset triggered by setting bit SYSCONO 15 RTCRST 1 with a bit instruction For a software or watchdog reset that is followed by an initialization of the RTC module it is recommended to select synchronous RTC clocking mode i e clear bit SYSCON0 14 RTCCM 0 reset the RTC module i e set bit SYSCONO 15 RTCRST 1 This may be achieved with one word or bit field instruction e g EXTR 1 BFUDH SYSCONO 0COhy 4 80h F RICRSI 15 RTCCM 10 wait_accpos EXTR 1 JNB ACCPOS wait_accpos gt Walt until bit ACCPOS 1 As a general recommendation bit REFCLK should be set to the desired value after any start up hardware software watchdog reset and in particular whenever the RTC module is reset by setting bit SYSCONO 15 RTCRST 1 When the RTC module is not used and shall be disabled after a power on hardware reset the following steps are recommended 1 reset the RTC by setting bit SYSCONO 15 RTCRST 1 2 clear the RTC run bit by setting RTC_CON
49. twice before evaluating the status of flag IRQD POWER X H1 Initialization of SYSCON3 for Power Saving Modes For minimum power consumption during power saving modes all modules which are not required should be disabled in register SYSCONS i e the corresponding disable bits should be set to 1 Errata Sheet XC161CJ 16F20F 40F ES AD 23 of 31 Mh Es UK V0 4 2004 08 19 including bits which are marked as reserved this provides compatibility with future devices since all SYSCONS bits are disable bits In test chip devices marked as TC SYSCONS bits 14 9 and 4 will always be read as 0 while in the final production version reading these bits will return the written value This e g allows to check the shut down status of peripherals equipped with peripheral shut down handshake Beginning with the AA step of the XC161CJ XC164CS bit SYSCON 14 RTCDIS is implemented for control of the Real Time Clock RTC module Its default value after reset is RTCDIS 0 i e RTC on POWER _X H2 1 Power Consumption during Clock System Configuration In the following situations 1 during and after a hardware reset from falling edge on RSTIN until oscillator lock 2 after wake up from sleep mode until oscillator lock 3 after a clock failure PLL unlock or oscillator fail until clock reconfiguration by software the device is internally clocked by the VCO running on the base frequency of the currently selected VCO band divided by
50. watchdog timer reset select the clocking mode in PLLCTRL such that it is either identical to the status after reset See a b3 above or such that only state transitions from 1Xb lt 1Xb will occur Example for single chip mode EA high e g the following sequence is recommended 1 clear CPSYS 0 2 program PLLCON with setting which selects PLLCTRL 01b same setting as default setting after reset 3 set CPSYS 1 If a reset occurs at this point the internal initialization phase will write the same PLLCTRL value that is already in effect and therefore no problem will occur SCU_X 009 1 Software or Watchdog Timer Reset while Oscillator is not locked If a software reset instruction SRST is executed or a watchdog timer overflow occurs while the oscillator has not yet locked i e 2048 clock cycles that exceed the XTAL1 input hysteresis have been counted the clock system will remain in the state it had before entry into sleep mode This problem occurs after wake up from sleep mode if the clock at XTAL1 was switched off during sleep mode i e the RTC is not running on the clock derived from XTAL1 and SRST is executed or a watchdog overflow occurs before the oscillator has locked flag OSCLOCK 1 Errata Sheet XC161CJ 16F20F 40F ES AD 15 of 31 Mh Es UK V0 4 2004 08 19 If this failure mode has been entered write accesses to register PLLCON have no effect Entry into sleep mode or further internal resets

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