TPA3125D2N - Electrocomponents
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1. TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY 10 10 se Voc 12 V z Vcc 18V 40 SE R 26 Q SE 8 Gain 20 dB 8 Gain 20 dB 2 2 1 1 5 2 5 5 2 2 2 D Po 1W y 5 2 0 1 8 0 1 o o E E I I g S 0 01 Po 0 5W E 0 01 a d 0 5 I I 0 001 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz G001 Go02 Figure 1 Figure 2 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY 10 10 18V Voc 24 V 28 Q SE 28 Q SE Gain 20 dB Gain 20 dB 2 2 1 1 8 8 Po 5W t 2 5 8 9 Po 2 5 B OA g 0 1 X E E G G T T g P 00 t 001 2 1W gt Po 1W a a I I H 0 001 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz G003 G004 Figure 3 Figure 4 6 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D22. TERMINAL NAME Vo DESCRIPTION PVCCL 1 Power supply for left channel H bridge SD 2 Shutdown signal for IC low outputs disabled high operational TTL logic levels with compliance to AVCC MUTE 3 Mute signal for quick disable enable of outputs high outputs switch at 5096 duty cycle low outputs enabled TTL logic levels with compliance to AVCC LIN 4 Audio input for left channel RIN 5 Audio input for right channel BYPASS 6 o 2 inputs Nominally equal to AVCC 8 Also controls start up time via AGND 7 Analog ground for digital analog cells in core AGND 8 Analog ground for digital analog cells in core VCLAMP 9 Internally generated voltage supply for bootstrap capacitors PVCCR 10 Power supply for right channel H bridge PGNDR 11 Power ground for right channel H bridge ROUT 12 Class D H bridge negative output for right channel BSR 13 Bootstrap input for right channel GAIN1 14 Gain select most significant bit TTL logic levels with compliance to AVCC GAINO 15 Gain select least significant bit TTL logic levels with compliance to AVCC AVCC 16 17 High voltage analog power supply Not internally connected to PVCCR or PVCCL BSL 18 Bootstrap input for left channel LOUT 19 Class D H bridge positive output for left channel PGNDL 20 Power ground for left channel H bridge 2 Submit Documentation Feedback Copyright O 2008 Texas Instruments I
3. TEXAS INSTRUMENTS www ti com TPA3125D2 SLOS611 DECEMBER 2008 TYPICAL CHARACTERISTICS continued All tests are conducted at frequency 1 kHz unless otherwise noted TOTAL HARMONIC DISTORTION NOISE vs OUTPUT POWER 10 Ri 24 Q SE 20 dB 2 D 2 1 z c c t t 2 2 2 a a 8 0 1 Veco 2 12V 8 o o E E I T 5 5 001 2 2 a a T T E E 0 001 0 01 0 1 1 10 40 Po Output Power W 9005 Figure 5 TOTAL HARMONIC DISTORTION NOISE vs OUTPUT POWER 10 2 8 9 SE Gain 20 dB 0 1 0 01 THD N Total Harmonic Distortion Noise 0 001 0 01 0 1 1 10 Po Output Power W Figure 7 Copyright O 2008 Texas Instruments Incorporated 40 G007 Crosstalk dB TOTAL HARMONIC DISTORTION NOISE VS OUTPUT POWER 10 6 Q SE Gain 20 dB 0 1 0 01 0 001 0 01 0 1 1 10 40 Po Output Power W 6006 Figure 6 CROSSTALK vs FREQUENCY 20 Voc 12V E 24 Q SE 30 0 25 W Gain 20 dB 50 60 Right to Left 70 Left to Right 80 90 100 20 100 1k 10k 20k f Frequency Hz G008 Figure 8
4. resistance GAINO 0 8 V 18 20 22 GAIN1 0 8 V GAINO 2 V 24 26 28 G Gain dB GAINO 0 8 V 30 32 34 GAIN 2V GAINO 2 V 34 36 38 Mute attenuation Vi 1 Vrms 80 dB AC CHARACTERISTICS 25 Voc 24 V 80 unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voc 24 Viipple 0 2 Vpp Gain 20 dB m ksvR Supply ripple rejection freq 1 kHz 52 dB Output power at 1 THD N Voc 24 V f 1 kHz single ended output 8 Output power at 10 THD N Vcc 24 V 1 kHz single ended output 10 Output power at 1 THD N Voc 12 V f 1 kHz bridge tied output 7 Output power at 10 THD N Voc 12 V f 1 kHz bridge tied output 9 Po Voc 24 V f 1 kHz bridge tied output W Output power at 1 THD N output thermally limited to 20W unless 30 heatsink is used Voc 24 V f 1 kHz bridge tied output Output power at 10 THD N output thermally limited to 20W unless 36 heatsink is used THD N Total harmonic distortion f 1 kHz Po 5 W single ended output 0 04 noise THD N 19191 harmonic distortion t 1kHz Po 10 W bridge tied output 0 04 20 Hz to 22 kHz A weighted filter 125 RMS Vn Output integrated noise floor Gain 20 dB 78 dBV Crosstalk Po 1 W f 1 kHz gain 20 dB 0 dB Max output at THD N 1 f 1 kHz SNR Signal to noise ratio gain 20 dB 92 dB Thermal trip point 150 Thermal hysteresis 30 C fosc Oscillator frequency 250 300 350 kH
5. TEXAS INSTRUMENTS www ti com TPA3125D2 SLOS611 DECEMBER 2008 10 W STEREO CLASS D AUDIO POWER AMPLIFIER FEATURES 10 W Ch stereo SE into an 8 O Load From a 24 V Supply 20 W Ch mono BTL into an 8 O Load from a 24 V Supply Operates From 10 V to 26 V Operates From 24 V LCD Backlight Supply Efficient Class D Operation Eliminates Need for Heat Sinks Four Selectable Fixed Gain Settings Single Ended Analog Inputs Thermal and Short Circuit Protection With Auto Recovery 20 Pin DIP Package Advanced Power Off Pop Reduction APPLICATIONS e Flat Panel Televisions DLP TVs e CRT TVs Powered Speakers DESCRIPTION The TPA3125D2 is a 10 W per channel efficient class D audio power amplifier for driving stereo speakers in a single ended configuration or a mono speaker in bridge tied load configuration The TPA3125D2 can drive stereo speakers as low as 4 The efficiency of the TPA3125D2 eliminates the need for an external heat sink when playing music The gain of the amplifier is controlled by two gain select pins The gain selections are 20 26 32 and 36 dB The patented start up and shutdown sequences minimize pop noise in the speakers without additional circuitry The thru hole package allows single sided printed circuit boards placement on SIMPLIFIED APPLICATION CIRCUIT TPA3125D2 1 uF 0 22 uF Left Channel _ gt j di 33 uH 4
6. This is not true of the class D amplifier system shown in Figure 31 b which requires low pass filters in most cases in order to measure the audio output waveforms This is because it takes an analog input signal and converts it into a pulse width modulated PWM output signal that is not accurately processed by some analyzers 20 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 Ij TEXAS TPA3125D2 INSTRUMENTS www ti com SLOS611 DECEMBER 2008 Power Supply Signal R Analyzer Generator 20 Hz 20 kHz 5 a Basic Class AB Power Supply Signal Cz Analyzer Class D APA filt R 20 Hz 20 kHz b Traditional Class D Figure 31 Audio Measurement Systems Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s TPA3125D2 TPA3125D2 J TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com SE Input and SE Output TPA3125D2 Stereo Configuration The SE input and output configuration is used with class D amplifiers A block diagram of a fully SE measurement circuit is shown in Figure 32 SE inputs normally have one input pin per channel In some cases two pins are present one is the signal and the other is ground SE outputs have one pin driving a load through an output ac coupling capacitor and the other end of the load is tied to gro
7. 10 0 1 0 01 0 001 0 01 100 90 TOTAL HARMONIC DISTORTION NOISE VS OUTPUT POWER 80 BTL Gain 20 dB Voc 12 Voc 18 V 0 1 1 10 40 Po Output Power W 9021 Figure 22 EFFICIENCY VS OUTPUT POWER RL 8Q BTL Gain 20 dB 4 6 8 10 12 Po Output Power W 9024 Figure 24 Submit Documentation Feedback 11 TPA3125D2 Ij TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com TYPICAL CHARACTERISTICS continued All tests are conducted at frequency 1 kHz unless otherwise noted POWER SUPPLY REJECTION RATIO VS FREQUENCY BTL Voc 24V Vovripp p 0 2 Vpp R 8 Q BTL Gain 20 dB Power Supply Rejection Ratio dB 20 100 1k 10k 20k f Frequency Hz 9026 Figure 25 12 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 I TEXAS TPA3125D2 INSTRUMENTS www ti com SLOS611 DECEMBER 2008 APPLICATION INFORMATION CLASS D OPERATION This section focuses on the class D operation of the TPA3125D2 Traditional Class D Modulation Scheme The TPA3125D2 operates in AD mode There are two main configurations that may be used For stereo operation the TPA3125D2 should be configured in a single ended SE half bridge amplifier For mono a
8. The external capacitor for this reference Cayp is a critical component and serves several important functions During start up or recovery from shutdown mode determines the rate at which the amplifier starts The start up time is proportional to 0 5 s per microfarad Thus the recommended 1 uF capacitor results in a start up time of approximately 500 ms The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal This noise could result in degraded power supply rejection and THD N 16 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 TEXAS TPA3125D2 INSTRUMENTS www ti com SLOS611 DECEMBER 2008 The circuit is designed for a Cgyp value of 1 uF for best pop performance The input capacitors should have the same value A ceramic or tantalum low ESR capacitor is recommended SHUTDOWN OPERATION The TPA3125D2 employs a shutdown mode of operation designed to reduce supply current Icc to the absolute minimum level during periods of nonuse for power conservation The SHUTDOWN input terminal should be held high see specification table for threshold during normal operation when the amplifier is in use Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low current state Never leave SHUTDOWN unconnected because amplifier operation would be unpredictable For the best power up pop perfo
9. Submit Documentation Feedback 7 Product Folder Link s TPA3125D2 TPA3125D2 SLOS611 DECEMBER 2008 Crosstalk dB Gain dB 8 TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued All tests are conducted at frequency 1 kHz unless otherwise noted CROSSTALK vs FREQUENCY 20 Vcc 18V Vo 1 Vrms 30 8 Q SE 0 125 W 40 Gain 20 dB 50 60 Right to Left 70 80 Left to Right 90 100 20 100 1k 10k 20k f Frequency Hz 9009 Figure 9 GAIN PHASE vs FREQUENCY 40 600 Voc 24 RL 40 SE 99 Gain 20 dB ae Liit 22 uH 30 Cu 0 68 uF 400 1000 uF 25 300 Gain 20 200 9 oO Phase a 15 100 10 0 5 100 0 200 20 100 1k 10k 100k f Frequency Hz Peaking of frequencies above 10 kHz is due to reconstruction filter not the device Figure 11 Submit Documentation Feedback 9011 Crosstalk dB Gain dB CROSSTALK vs FREQUENCY 20 24 1 Vrms 30 8
10. close to the device as possible Large 220 or greater bulk power supply decoupling capacitors should be placed near the TPA3125D2 on the PVCCL and PVCCR terminals Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s TPA3125D2 TPA3125D2 Ij TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com Grounding The AVCC pins 16 and 17 decoupling capacitor and BYPASS pin 6 capacitor should each be grounded to analog ground AGND pins 7 and 8 The PVCOx decoupling capacitors and VCLAMP capacitors should each be grounded to power ground PGND pins 11 and 20 Analog ground and power ground should be connected at the thermal pad which should be used as a central ground connection or star ground for the TPA3125D2 Output filter The reconstruction filter 22uH and 0 68uF network in the output circuit should be placed as close to the output terminals as possible for the best EMI performance The capacitors should be grounded to power ground Thermal pad The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability The dimensions of the thermal pad and thermal land are described in the mechanical section at the back of the data sheet See TI Technical Briefs SLMA002 and SLOA120 for more information about using the thermal pad For recommended PCB footprints see figures at the end of this data sheet For an example layout see the TPA3125D2 Evalua
11. 38 MAX 00 5 08 Cau x ge Plane l Seating Plane 125 3 18 MIN gt 4 0 010 0 25 NOM d 0 430 10 92 MAX D 7 0 51 0 2 t 0 015 0 38 10 010 0 25 14 18 Pin Only 20 Pin vendor option A 4040049 E 12 2002 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Falls within JEDEC 5 001 except 18 and 20 pin minimum body length Dim A The 20 pin end lead shoulder width is a vendor option either half or full width bp o gt 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirement
12. 70 uF Right Channel gt 3 1uF 0 22 uF e e 1 uF 0 22 uF SE BYPASS mis AGND H L 0 22 uF 10 V to 26 V 10Vto26V gt OoOo VCLAMP ts Shutdown Control gt 1 WF NT Mute Control gt DLP is a registered trademark of Texas Instruments System Two Audio Precision are trademarks of Audio Precision Inc All other trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters lt 4 Step Gain Control lt 50267 02 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Copyright 2008 Texas Instruments Incorporated TPA3125D2 SLOS611 DECEMBER 2008 TEXAS INSTRUMENTS www ti com A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam NG a during storage or handling to prevent electrostatic damage to the MOS gates DUAL INLINE PACKAGE TOP VIEW PVCCL 20 PGNDL SD 19 LOUT MUTE BSL LIN AVCC RIN AVCC BYPASS GAINO AGND GAIN1 AGND BSR VCLAMP ROUT PVCCR PGNDR Table 1 TERMINAL FUNCTIONS
13. 80 1000 2200 6 470 680 1500 8 330 470 1000 Bleeder Resistor for Single Ended Output Capacitor The single ended application schematic shows a 4 7 resistor from the IC side of the single ended output capacitor to ground This resistor is used to bleed the charge off of the capacitor when the amp is powered down preventing pop if the amp is power back up quickly The value of the resistor can be adjusted to control the time required to discharge the capacitor The discharge time is proportional to the RC time constant of the resistor and capacitor Output Filter and Frequency Response For the best frequency response a flat passband output filter second order Butterworth may be used The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins There are several possible configurations depending on the speaker impedance and whether the output configuration is single ended SE or bridge tied load BTL Table 4 lists the recommended values for the filter components It is important to use a high quality capacitor in this application A rating of at least X7R and voltage rating of 50V is suggested Table 4 Recommended Filter Output Components Output Configuration Speaker Impedance Filter Inductor uH Filter Capacitor nF 4 22 680 Single Ended SE 8 33 220 Bridge Tied Load BTL 8 22 680 Copyright 2008 Texas Instruments Incorpo
14. E GAIN1 GAINO kO TYPICAL 0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 INPUT RESISTANCE Changing the gain setting can vary the input resistance of the amplifier from its smallest value 9 20 to the largest value 60 20 As a result if a single capacitor is used in the input high pass filter the 3 dB cutoff frequency will change when changing gain steps IN Input Signal The 3 dB frequency be calculated using Equation 1 Use the Z values given in Table 2 ie 1 INPUT CAPACITOR C In the typical application input capacitor C is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation In this case C and the input impedance of the amplifier Zi form a high pass filter with the corner frequency determined in Equation 2 3 dB fe 2 The value of C is important as it directly affects the bass low frequency performance of the circuit Consider the example where 4 is 60 and the specification calls for a flat bass response down to 20 Hz Equation 2 is reconfigured as Equation 3 1 2 2 f 3 In this example C is 0 4 uF so one would likely choose a value of 0 47 uF as this value is commonly used If the gain is known and is constant use 4 from Table 2 to calculate A further consideration for this capacitor is the leakage path from the input source through t
15. POWER PER CHANNEL 8 Q SE Gain 20 dB 0 5 10 15 20 25 Po Output Power Per Channel W G018 A dashed line represents thermally limited region Figure 18 POWER SUPPLY REJECTION RATIO VS FREQUENCY SE Voc 224 V Vo ripp e 0 2 Vpp 8Q SE Gain 20 dB 20 100 1k f Frequency Hz 10k 20k 9025 Figure 20 Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 1 INSTRUMENTS www ti com THD N Total Harmonic Distortion Noise Po Output Power W 10 0 1 0 01 0 001 TPA3125D2 SLOS611 DECEMBER 2008 TYPICAL CHARACTERISTICS continued All tests are conducted at frequency 1 kHz unless otherwise noted TOTAL HARMONIC DISTORTION NOISE vs FREQUENCY Voc 24 V 8 Q BTL Gain 20 dB 20 100 1k f Frequency Hz Figure 21 OUTPUT POWER vs SUPPLY VOLTAGE RL 8 Q BTL THD N Total Harmonic Distortion Noise 96 10k 20k 9020 Gain 20 dB THD N 10 Efficiency 10 12 14 16 18 20 22 24 Voc Supply Voltage V A dashed line represents thermally limited region Figure 23 Copyright O 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 26 9023
16. PUT POWER vs SUPPLY VOLTAGE Ri 8 Q SE Gain 20 dB 10 12 14 16 18 20 22 Voc Supply Voltage V 24 26 G014 A dashed line represents thermally limited region Figure 14 EFFICIENCY vs OUTPUT POWER 100 90 80 70 60 50 40 30 20 10 Ri 8 Q SE Gain 20 dB 0 0 2 4 6 8 10 12 Po Output Power W G016 Figure 16 Submit Documentation Feedback 9 Product Folder Link s TPA3125D2 TPA3125D2 SLOS611 DECEMBER 2008 All tests are conducted at frequency 1 kHz unless otherwise noted Supply Current Power Supply Rejection Ratio dB 10 TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued SUPPLY CURRENT vs OUTPUT POWER PER CHANNEL 4 SE Gain 20 dB 0 3 6 9 12 15 Po Output Power Per Channel W A dashed line represents thermally limited 9017 Figure 17 POWER SUPPLY REJECTION RATIO vs FREQUENCY 0 Voc 24V 10 Vovripp 0 2 Vpp RL 4 Q SE 20 Gain 20 dB 30 40 50 60 70 80 90 100 20 100 1k 10k 20k f Frequency Hz Figure 19 Submit Documentation Feedback G019 Icc Supply Current Power Supply Rejection Ratio dB SUPPLY CURRENT VS OUTPUT
17. Q SE Po 0 125 W 40 Gain 20 dB 50 60 Right to Left 70 80 Left to Right 90 100 20 100 1k 10k 20k f Frequency Hz 9010 Figure 10 GAIN PHASE vs FREQUENCY 40 600 Voc 24V RL 80 SE 89 Gain 20 dB 309 Li ilt 33 uH 30 Cit 0 22 uF 400 470 uF 25 300 Gain 20 200 9 1 amp 15 Phase 100 10 0 5 100 0 200 20 100 1k 10k 100k f Frequency Hz 9012 Peaking of frequencies above 10 kHz is due to reconstruction filter not the device Figure 12 Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 TEXAS INSTRUMENTS www ti com TPA3125D2 SLOS611 DECEMBER 2008 TYPICAL CHARACTERISTICS continued All tests are conducted at frequency 1 kHz unless otherwise noted OUTPUT POWER vs SUPPLY VOLTAGE 22 4 Q SE Gain 20 dB 20 18 16 14 12 10 Po Output Power W m 10 12 14 16 18 20 22 24 Voc Supply Voltage V 26 A dashed line represents thermally limited region Figure 13 EFFICIENCY vs OUTPUT POWER 100 90 80 70 60 50 Efficiency 40 30 20 4 in 20 dB 10 0 1 2 3 4 5 6 7 Po Output Power W Figure 15 Copyright O 2008 Texas Instruments Incorporated 9013 6015 Po Output Power W Efficiency 96 OUT
18. ee RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA N R PDIP T PLASTIC DUAL IN LINE PACKAGE 16 PINS SHOWN PINS DIM A MAX A MIN MS 001 VARIATION 0 020 MIN 0 015 0
19. ended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Fr
20. ference in voltage between the pins Differential inputs reduce the common mode noise and distortion of the input circuit BTL is a term commonly used in audio to describe differential outputs BTL outputs have two output pins providing audio signals that are 180 out of phase The load is connected between these pins This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor A block diagram of the measurement circuit is shown in Figure 33 The differential input is a balanced input meaning the positive and negative pins have the same impedance to ground Similarly the BTL output equates to a balanced output Evaluation Module G t Audio Power enerator Amplifier Analyzer Lr rY YS i 1 Twisted Pair Wire Twisted Pair Wire Figure 33 Differential Input BTL Output Measurement Circuit The generator should have balanced outputs and the signal should be balanced for best results An unbalanced output can be used but it may create a ground loop that affects the measurement accuracy The analyzer must also have balanced inputs for the system to be fully balanced thereby cancelling out any common mode noise in the circuit and providing the most accurate measurement The following general rules should be f
21. he input network Ci and the feedback network to the load This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom especially 14 Submit Documentation Feedback Copyright O 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 I TEXAS TPA3125D2 INSTRUMENTS www ti com SLOS611 DECEMBER 2008 in high gain applications For this reason a low leakage tantalum or ceramic capacitor is the best choice When polarized capacitors are used the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 8 volts which is likely higher than the source dc level Note that it is important to confirm the capacitor polarity in the application Additionally lead free solder can create dc offset voltages due to leakage so it is important to ensure that boards are cleaned properly Single Ended Output Capacitor In single ended SE applications the dc blocking capacitor forms a high pass filter with the speaker impedance The frequency response rolls off with decreasing frequency at a rate of 20 dB decade The cutoff frequency is determined by _ 1 2n 4 Table shows some common component values and the associated cutoff frequencies Table 3 Common Filter Responses C DC Blocking Capacitor uF Speaker Impedance f 60 Hz 3 dB f 40 Hz 3 dB f 20 Hz 3 dB 4 6
22. iling Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2009 Texas Instruments Incorporated
23. ncorporated Product Folder Link s TPA3125D2 TEXAS INSTRUMENTS www ti com ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted TPA3125D2 SLOS611 DECEMBER 2008 VALUE UNIT Voc Supply voltage AVCC PVCC 0 3 to 30 V Logic input voltage SD MUTE GAINO GAIN1 0 3 to Voc 0 3 V Analog input voltage RIN LIN 0 3 to 7 V Continuous total power dissipation See Dissipation Rating Table TA Operating free air temperature range 40 to 85 Ty Operating junction temperature range 40 to 150 Tstg Storage temperature range 65 to 150 SE Output Configuration 3 2 Z Load impedance minimum value Q BTL Output Configuration 6 Human body model all pins 2 kV ESD Electrostatic Discharge model all 4500 V 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability DISSIPATION RATINGS PACKAGE Ta lt 25 DERATING FACTOR Ta 70 C Ta 85 C 20 pin DIP 1 87 W 15 mW C 1 20 W 0 97 W 1 For the most current package and ordering inf
24. nect to each PVCC terminal A 10 uF capacitor on the AVCC terminal is adequate These capacitors must be properly derated for voltage and ripple current rating to ensure reliability BSN and BSP Capacitors The half H bridge output stages use only NMOS transistors Therefore they require bootstrap capacitors for the high side of each output to turn on correctly A 220 nF ceramic capacitor rated for at least 25 V must be connected from each output to its corresponding bootstrap input Specifically one 220 nF capacitor must be connected from LOUT to BSL and one 220 nF capacitor must be connected from ROUT to BSR The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating power supply for the high side N channel power MOSFET gate drive circuitry During each high side switching cycle the bootstrap capacitors hold the gate to source voltage high enough to keep the high side MOSFETs turned on VCLAMP Capacitor To ensure that the maximum gate to source voltage for the NMOS output transistors is not exceeded one internal regulator clamps the gate voltage One 1 uF capacitor must be connected from VCLAMP pin 11 to ground and must be rated for at least 16 V The voltages at the VCLAMP terminal may vary with Vcc and may not be used for powering any other circuitry BYPASS Capacitor Selection The scaled supply reference VBYP nominally provides an AVCC 8 internal bias for the preamplifier stages
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26. ollowed when connecting to APAs with differential inputs and BTL outputs e Use a balanced source to supply the input signal Use an analyzer with balanced inputs Use twisted pair wire for all connections e Use shielding when the system environment is noisy Ensure that the cables from the power supply to the APA and from the APA to the load can handle the large currents see Table 5 Table 5 shows the recommended wire size for the power supply and load cables of the APA system The real concern is the dc or ac power loss that occurs as the current flows through the cable These recommendations are based on 12 inch 30 5 cm long wire with a 20 kHz sine wave signal at 25 Table 5 Recommended Minimum Wire Size for Power Cables DC POWER LOSS AC POWER LOSS Pour W AWG Size mW mW 10 4 18 22 16 40 18 42 2 4 18 22 3 2 8 3 7 8 5 1 8 22 28 2 8 2 1 8 1 0 75 8 22 28 1 5 6 1 1 6 6 2 Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s TPA3125D2 K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 19 Jan 2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty TPA3125D2N ACTIVE PDIP N 20 20 Pb Free CU NIPDAU for Pkg Type RoHS The marketing status values are defined as follows ACTIVE Product device recomm
27. ons Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specificatio
28. ormation see the Package Option Addendum at the end of this document or see the TI website at www ti com RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Voc Supply voltage PVCC AVCC 10 26 V Vin High level input voltage SD MUTE GAINO GAIN1 2 V Vit Low level input voltage SD MUTE GAINO GAIN1 0 8 V High level input current SD MUTE GAINO Vin Voc 26 V 125 Low level input current 1 MUTE GAINO GAIN1 Vin 0 Vcc 26 1 uA Ta Operating free air temperature 40 85 Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 Submit Documentation Feedback TPA3125D2 SLOS611 DECEMBER 2008 DC CHARACTERISTICS 25 Voc 24 V 80 unless otherwise noted TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class D output offset voltage Vos measured differentially in BTL Vj 0 V Ay 36 dB 7 5 50 mV mode as shown in Figure 33 V BvPASS Bypass output voltage No load AVCC 8 V lcc a Quiescent supply current SD 2 V MUTE 0 V no load 16 30 mA Icco Quiescent supply current in _ imuta mode MUTE 0 8 V no load 16 mA Icc a Quiescent supply current in cen sh tdown mod D 0 8 V no load 0 39 1 mA DS on Drain source on state 210 450
29. pplications TPA3125D2 may be used as a bridge tied load BTL amplifier The traditional class D modulation scheme which is used in the TPA3125D2 BTL configuration has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage Vcc Therefore the differential prefiltered output varies between positive negative Voc where filtered 50 duty cycle yields 0 V across the load The class D modulation scheme with voltage and current waveforms is shown in Figure 26 0v Output Current 52 Figure 26 Class D Modulation for TPA3125D2 SE Configuration Supply Pumping One issue encountered in single ended SE class D amplifier designs is supply pumping Power supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class D amplifier This phenomenon is most evident at low audio frequencies and when both channels are operating at the same frequency and phase At low levels power supply pumping results in distortion in the audio output due to fluctuations in supply voltage At higher levels pumping can cause the overvoltage protection to operate which temporarily shuts down the audio output Several things can be done to relieve power supply pumping The lowest impact is to operate the two inputs out of phase 180 and reverse the speaker connections Because most audio is highly correlated this causes the supply p
30. rated Submit Documentation Feedback 15 Product Folder Link s TPA3125D2 TPA3125D2 I TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com LOUT e LOUT ROUT Litter Liter T Critter ROUT _ 5 Litter Citer T Figure 27 BTL Filter Configuration Figure 28 SE Filter Configuration Power Supply Decoupling Cs The TPA3125D2 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion THD is as low as possible Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads For higher frequency transients spikes or digital hash on the line a good low equivalent series resistance ESR ceramic capacitor typically 0 1 uF to 1 uF placed as close as possible to the device PVcc pin works best For filtering lower frequency noise signals a larger aluminum electrolytic capacitor of 470 uF or greater placed near the audio power amplifier is recommended The 470 uF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs The PVCC terminals provide the power to the output transistors so a 470 uF or larger capacitor should be con
31. rmance place the amplifier in the shutdown or mute mode prior to applying the power supply voltage MUTE Operation The MUTE pin is an input for controlling the output state of the TPA3125D2 A logic high on this terminal causes the outputs to switch at a constant 5096 duty cycle A logic low on this pin enables the outputs This terminal may be used as a quick disable enable of outputs when changing channels on a television or transitioning between different audio sources The MUTE terminal should never be left floating For power conservation the SHUTDOWN terminal should be used when the amp will be off for a significant amount of time to reduce the quiescent current to the absolute minimum level USING LOW ESR CAPACITORS Low ESR capacitors are recommended throughout this application section A real as opposed to ideal capacitor can be modeled simply as a resistor in series with an ideal capacitor The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor SHORT CIRCUIT PROTECTION The TPA3125D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output to output shorts and output to GND shorts after the filter and output capacitor at the speaker terminal Directly at the device terminals the protection circuitry prevents damage to device d
32. s e Linear regulated power supply e Filter components EVM or other complete audio circuit Figure 31 shows the block diagrams of basic measurement systems for class AB and class D amplifiers A sine wave is normally used as the input signal because it consists of the fundamental frequency only no other harmonics are present An analyzer is then connected to the audio power amplifier APA output to measure the voltage output The analyzer must be capable of measuring the entire audio bandwidth A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins A System Two audio measurement system by Audio Precision includes the signal generator and analyzer in one package The generator output and amplifier input must be ac coupled However the EVMs already have the ac coupling capacitors so no additional coupling is required The generator output impedance should be low to avoid attenuating the test signal and is important because the input resistance of APAs is not high Conversely the analyzer input impedance should be high The output resistance Rour of the APA is normally in the hundreds of milliohms and can be ignored for all but the power related calculations Figure 31 a shows a class AB amplifier system It takes an analog signal input and produces an analog signal output This amplifier circuit can be directly connected to the or other analyzer input
33. s testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restricti
34. tion Module TPA3125D2 EVM User Manual SLOU250 Both the EVM user manual and the thermal pad application note are available on the TI Web site at http www ti com 18 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 TEXAS INSTRUMENTS www ti com Shutdown Control Mute Control TPA3125D2 SLOS611 DECEMBER 2008 VCC 22uH 470uF 4 0uF PGNDL 71571 LEFT OUT 0 68uF Letinput Mure TF Poa i AVCC L H 0 220 Right Input Cg RIN S 1 0uF BSR IL 4 RIGHT OUT ROUT 41 PGNDR 0 68uF 9 470uF 0 1uF 10uF Figure 29 Schematic for Single Ended SE Configuration 8 O Speaker vcc 22uH Shutdown Control ren Mute Control T 1 0uF PVCCL PGNDL LEFT OUT 0 68uF Plus Input Minus Input K 1 0uF 1 0uF RIGHT OUT PVCCR PGNDR TPA3125D2 PDIP 0 1uF 22uH TT 1 0uF 470uF 470uF 0 1uF 10uF Figure 30 Schematic for Bridge Tied Load BTL Configuration 8 O Speaker Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link s TPA3125D2 TPA3125D2 Ij TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com BASIC MEASUREMENT SYSTEM This section focuses on methods that use the basic equipment listed below e Audio analyzer or spectrum analyzer Digital multi meter DMM e Oscilloscope e Twisted pair wires e Signal generator e Power resistor
35. umping to be out of phase and not as severe If this is not enough the amount of bulk capacitance on the supply must be increased Also improvement is realized by hooking other supplies to this node thereby sinking some of the excess current Power supply pumping should be tested by operating the amplifier at low frequencies and high output levels Gain Setting via GAINO and GAIN1 Inputs The gain of the TPA3125D2 is set by two input terminals GAINO and GAIN1 The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier This causes the input impedance Zi to be dependent on the gain setting The actual gain settings are controlled by ratios of resistors so the gain variation from part to part is small However the input impedance from part to part at the same gain may shift by 20 due to shifts in the actual resistance of the input resistors For design purposes the input network discussed in the next section should be designed assuming an input impedance of 8 which is the absolute minimum input impedance of the TPA3125D2 At the higher gain settings the input impedance could increase as high as 72 Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TPA3125D2 TPA3125D2 I TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com Table 2 Gain Setting AMPLIFIER GAIN dB NPUT IMPEDANC
36. und SE inputs and outputs are considered to be unbalanced meaning one end is tied to ground and the other to an amplifier input output The generator should have unbalanced outputs and the signal should be referenced to the generator ground for best results Unbalanced or balanced outputs can be used when floating but they may create a ground loop that affects the measurement accuracy The analyzer should have balanced inputs to cancel out any common mode noise in the measurement Twisted Pair Wire Twisted Pair Wire Figure 32 SE Input SE Output Measurement Circuit The following general rules should be followed when connecting to APAs with SE inputs and outputs Use an unbalanced source to supply the input signal e Use an analyzer with balanced inputs e Use twisted pair wire for all connections e Use shielding when the system environment is noisy e Ensure the cables from the power supply to the APA and from the APA to the load can handle the large currents see Table 5 22 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 I TEXAS TPA3125D2 INSTRUMENTS www ti com SLOS611 DECEMBER 2008 DIFFERENTIAL INPUT AND BTL OUTPUT TPA3125D2 Mono Configuration Many of the class D APAs and many class AB APAs have differential inputs and bridge tied load BTL outputs Differential inputs have two input pins per channel and amplify the dif
37. uring output to output output to ground and output to supply When a short circuit is detected on the outputs the part immediately disables the output drive This is an unlatched fault Normal operation is restored when the fault is removed The device will try to restart after a 250 ms delay so in a true fault condition the 250 msec period of the restart attempts can be used to confirm the fault is an over current type THERMAL PROTECTION Thermal protection on the TPA3125D2 prevents damage to the device when the internal die temperature exceeds 150 C There is a 15 tolerance on this trip point from device to device Once the die temperature exceeds the thermal set point the device enters into the shutdown state and the outputs are disabled This is not a latched fault The thermal fault is cleared once the temperature of the die is reduced by 30 The device begins normal operation at this point with no external system interaction PRINTED CIRCUIT BOARD PCB LAYOUT Because the TPA3125D2 is a class D amplifier that switches at a high frequency the layout of the printed circuit board PCB should be optimized according to the following guidelines for the best possible performance e Decoupling capacitors The high frequency 0 1 uF decoupling capacitors should be placed as close to the PVCC pins 1 and 10 and AVCC pins 16 and 17 terminals as possible The BYPASS pin 6 capacitor and VCLAMP pin 9 capacitor should also be placed as
38. z Mute delay Time from mute input switches high until 30 us outputs muted Unmute delay Time from mute input switches low until 120 ms outputs unmuted Start up time Bypass capacitor on pin 6 1uF 500 ms 4 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3125D2 lj TEXAS TPA3125D2 INSTRUMENTS www ti com SLOS611 DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM lt gt BSL AVCC AVDD lt gt PVCCL REGULATOR lt gt LOUT lt gt PGNDL LIN AVDD 2 AGND lt gt SD CONTROL BIAS THERMAL MUTE MUTE lt gt CONTROL BYPASS lt gt BYPASS GAIN1 lt gt li AV GAINO lt gt CONTROL lt gt BSR lt gt PVCCR lt gt ROUT lt gt PGNDR RIN lt gt Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link s TPA3125D2 TPA3125D2 Ij TEXAS INSTRUMENTS SLOS611 DECEMBER 2008 www ti com TYPICAL CHARACTERISTICS All tests are conducted at frequency 1 kHz unless otherwise noted
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