TB-FMCL-HDMI Hardware User Manual
Contents
1. GIKCM2C P Vio 10 uewen FPGAt FMC Cock FMESCL Vi 10 uewen 12Cserialciock FMCSDA YN 10 uewen 120 senialdata peu Riz LVCMOS2S Generatpurpose DIP SW input0 pa m2 LVCMOS2S Generakpurpose DIP SW input1 Gem mg 1 LVCMOS2S Generakpurpose DIP SW input2 pas wis 1 LVCMOS2S Generakpurpose DIP SW input3 Deo Tis O LVCMOS2S Generakpurpose LED output0 7 bieDi urs O LVCMOS2S Generatpurpose LED outputt Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi Pm ame 4 i0 Se Dem OO DEZ wie O LVCMOS25 Generatpurpose LED output2 plena vie O LVCMOS25 Generakpurpose LED output3 DECP2O Ai amp LVCMOSGS DEC Video data input29 DEC R28 Bi amp LVCMOSGS DEC Video data input28 DEC Par c17 LVCMOSGS l DEC Video data input 27 DECP26 b17 LVCMOSGS DEC Video data input26 DECP25 Eis LVCMOSGS l DEC Video data input25 DEC PM p16 LVCMOSGS l DEC Video data input24 DEC pza AT LVCMOSGS l DEC Video data input23 pecpzz B17 LVCMOSGS DEC Video data input22 DEC EXT CLK me O LVCMOSGS DEC extemal cock output DEC PA 016 LVCMOSGS l DEC Videodatainputzi DECP20 cts LVCMOSGS DEC Video data input20 DEC PIS DIS LVCMOSGS DEC Video data input 19 pec Pie AM LVCMOSGS DEC Video data inputs DEC Pi CM2. LVCMOSGS DEC Video data input 17 DECPi6 s LVCMOSGS DEC Video data inpute DEC Pre 815 LVCMOSGS DEC Video data input 16 DECPM Fi LVCMOSSS l DEC Video data input 14 DEC pis Ei LVCMOSGS DEC Video data impu DEC piz 613 LVCMOSGS DEC Video data input12 DECPN D14 LVOMOSSS DEC Video data inui DEC Pro Ciz LVCMOSGS DEC Video data inui Dec Po B13 LVCMOSSS DEC Video data imu DECP8 F12 LVCMOSGS DEC Video data inputs DECP p12 LVCMOSGS DEC Video data input DECP6 Ai LVCMOSGS DEC Video data inpute DECP5 B12 LVCMOSGS DEC Video data inputs pec pa CH LVCMOSGS DEC Video data inputa DECP3 BH LVCMOSSS DEC Video data inputs DEcuic on LVOMOSSS DEClCsgna SYSiK P MO LVCMOS33_ System clock input fon DECSOLK DIO LVCMOSGS DEC Audio serial cock DEC MCLKOUT A9 LVCMOS33 DECAudomastercok DECP2 C9 LVCMOSSS DEC Video data imput2 DECPi B0 LVCMOSGS DEC Video data inputi DECPO ce LVCMOSSS DEC Video data imputO DECRESETX B8 O LVOMOS33 DECresetoutput U DECINT2 D LVCMOSGS l DEC interuptinput2 DECINTI CT LVCMOSGS DECiemupipu DEC VSYNG F9 LVCMOSGS DECVSYNC input DEC SYNC Eo LVCMOSGS DECHSYNCipu Rev 3 00
3. 9 FPGA Pin Assignment ull kaaa 23 10 Carrier Card FPGA ING ace siri SS 28 11 Default Switch Settings e eerereea arena na menn nnnm nennen nnns 29 12 EEN 30 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun E List of Figures Figure 3 1 FMC Connector Pinout aaa kaaa aaa aaa akan 11 Figure 4 1 Block Diagram ME 12 Figure 5 1 Component Side cccceecccssccceseecseeceececeucecueecseeccueecsueecsueesaeeesueeeeueessueesseeesseessaeessneess 13 mle Ol gama a Melo lt ED OR DR d A ER ag a aaa RR anga e ho 13 Figure 6 1 Board Dimensions inclusive of wasteable substrate teem 14 Figure 7 1 Power Supply Gtruchure errar aka nsn nns 15 Flgure 7 2 PIS LP TA e Le e NEE 18 Figure 8 1 S1 2 OFF S1 3 OFF Cable connection ss kaaa kaaa kaaa kaaa kana 22 Figure 8 2 S1 2 ON 81 3 OFF Cable connection aaa kakaa kakaa kaaa 22 Figure 8 3 S1 2 OFF S1 3 ON CGableconnechon enne 22 Figure 8 4 S1 2 ON S1 3 ON Cable connection ener 22 Figure 10 1 Timing of input and output signals kakaa kakaa kakaa aaa 28 Figure 11 1 Default Switch Settings Component Side erre 29 FIGURE 1241 lena e 30 List of Tables Table 7 1 JP4 VCCIO SEL Jumper Gettng errar en rer aa rrenanea 15 Table 7 2 HDMI Connector Transmit Side AA 16 Table 7 3 HDMI Connector Receiver Gdel nennen menn nnns 17 Table 7 4 JP5 SCL JP6 SDA Jumper Setting nennen 17 Table 7 5 JP7 JP8 Jumper
4. LVCMOSSS ENC Video data ouput14 ENCDIS Kie O LVCMOSSS ENC Video data ouput15 enc pi s17 O LVCMOSSS ENC Video data ouput16 ENCDGLK H18 O LVCMOSSS ENG Video data dock ENG Di me O LVCMOSSS ENCVeodstaoupui ENCDIS 620 O LVCMOSSS ENC Video data ouput18 enc Dia H20 O LVCMOSSS ENC Video data output 9 enc D20 Hir O LVCMOSSS ENC Video data output20 op 618 O LVCMOSSS ENC Video data output21 enc D22 Fi9 O LVCMOSSS ENC Video data ouput22 op F20 O LVCMOSSS ENC Video data output 23 ENCDM Fi O LVCMOSSS ENC Video data ouput24 op 617 O LVCMOSSS ENC Video data output25 ENCDZ E19 O LVCMOSSS ENC Video data output26 op Ex O LVCMOSSS ENC Video data output27 enc D28 FW O LVCMOSSS ENC Video data output28 ENcpz E18 O LVCMOSSS ENC Video data ouput29 enc D30 p18 O LVCMOSSS ENC Video data ouput30 ENCDS D20 O LVCMOSSS ENC Video data output31 enc Daz Fi O LVCMOSSS ENC Video data output32 op 616 O LVCMOSSS ENCVeodetaoupu3 ENCDM CI9 O LVCMOSSS ENC Video data ouput34 Enc pas c20 O LVCMOSSS ENC Video data ouiput35 ENCSDA B19 10 LVCMOSSS ENG 12C senal data ENCSCL Bx O LVCMOSSS ENC 12C serialclock ENCCEC NM O Deen ENG CEC signa ENG INT Pas Deen ENCinterap
5. LA30 N D2 IO LVCMOS25 FMC to FPGA VSYNC LA30 P C1 IO LVCMOS25 FPGAto FMC VSYNC LA31N E1 IO LVCMOS25 FMC to FPGA HSYNC LA31P D1 IO LVCMOS25 FPGAto FMC HSYNC LA29N G5 IO LVCMOS25 FMC to FPGA DATA29 R9 LA29 P F4 IO LVCMOS25 FPGA to FMC DATA29 R9 LA22N J5 IO LVCMOS25 FMC to FPGA DATA22 R2 LA22 P J6 IO LVCMOS25 FPGA to FMC DATA22 R2 LA27 N H4 IO LVCMOS25 FMC to FPGA DATA27 R7 LA27 P H6 IO LVCMOS25 FPGA to FMC DATA27 R7 LA26 N G4 IO LVCMOS25 FMC to FPGA DATA26 R6 LA26 P F3 IO LVCMOS25 FPGA to FMC DATA26 R6 LA28N F2 IO LVCMOS25 FMC to FPGA DATA28 R8 LA28P E3 IO LVCMOS25 FPGA to FMC DATA28 R8 LA24 N H2 IO LVCMOS25 FMC to FPGA DATA24 R4 LA24 P G3 IO LVCMOS25 FPGA to FMC DATA24 R4 LA23N G1 IO LVCMOS25 FMC to FPGA DATA23 R3 LA23 P F4 IO LVCMOS25 FPGA to FMC DATA23 R3 LA25 N H3 IO LVCMOS25 FMC to FPGA DATA25 R5 LA25 P J4 IO LVCMOS25 FPGA to FMC DATA25 R5 LA21N J2 IO LVCMOS25 FMC to FPGA DATA21 R1 LA21P J3 IO LVCMOS25 FPGA to FMC DATA21 R1 LA20 N K2 IO LVCMOS25 FMC to FPGA DATA20 R0 LA20P J1 IO LVCMOS25 FPGA to FMC DATA20 R0 LATO N L3 IO LVCMOS25 FMC to FPGA DATA19 G9 LA19 P K3 IO LVCMOS25 FPGA to FMC DATA19 G9 LA18 N CC L5 IO LVCMOS25 FMC to FPGA DATA18 G8 LAT8 PCC K4 IO LVCMOS25
6. ON DVI OFF HDMI Input setting ON DVI OFF HDMI S1 4 Loopback connection select from receiver to transmitter ul ON Receiver to Transmitter OFF Receiver to FMC FMC to Transmitter o4 Reconfiguration pushbutton Depress for greater then 3 seconds to initiate Ld FPGA reconfiguration Notice Supported resolution TV format HDMI 480p 60frame 720p 50 60frame 1080i 30frame 1080p 60frame PC format DVI UXGA 1600x1200 162MHz WUXGA 1920x1200 2 154 MHz Rev 3 00 TOKYO ELECTRON DEVICE LIMITED TB FMCL HDMI Hardware User Manual ag HDMI Cable commaercial SE Monitor side HDMI Cable commercial SE AT le DVI D to HDMI Cable commercial Monitor DVI D o Bibl Jo DVI D to HDMI Cable Source side commercial DLDLDLDLDLDLDLD eebe Je BDDODDUD GOOOOGNO ole SE 7 Je i Figure 8 4 81 2 ON S1 3 ON Cable connection Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 22 inreviun Bi 9 FPGA Pin Assignment Table 9 1 shows the FPGA pin assignment The pin assignments between the FMC and FPGA signals are related by video signal format When the HDMI input format is 8bits the FPGA output signals are assigned to the most significant 8 bits and the least significant two bits of each color will be 0 Table 9 1 FPGA Pin Assignment amame 10 ose ben LA32N C2 IO LVCMOS25 FMC to FPGA DATA ENABLE LA32P B1 IO LVCMOS25 FPGA to FMC DATA ENABLE
7. Setting nennen nennen nnne nnns 18 Table 7 6 FMC Connector Pin Assignment eee nane nnne nenne kaaa nnns 19 Table 7 7 JTAG AAA 20 A ak b mmm mrem o a EAA 21 Table 9 1 FPGA Pin Assignment aaa dosao t peel ol ita 23 Table 11 1 Default Jumper Gettngs nennen nennen nnne nnne nnn nnns 29 Table 11 2 Default DIP Switch Settings A 29 Table 12 1 Jumper Settings in the Exvampnie cess eeseeeeseeeeseeeeseeeseeeeseneesaees 30 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi Introduction Thank you for purchasing the TB FMCL HDMI board Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual and then always keep it handy Observe the precautions listed below to prevent injuries to you other personnel or damage to property e Before using the product read these safety precautions carefully to assure safe use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Ae Indicates the high possibility of serious injury or death if the product is handled Danger incorrectly Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indi
8. Uz O uwen ENG 125 Audio signalo ENCMCIK 019 O uwen ENC Audio master clock ENC spor PIT O uwen ENC SPDIF digital Audio output ENC DSD CLK Pre O uwen ENCDSDdok enc_osps el O uwen ENG DSD AudiodataS eme Ri O uwen ENG DSD Audio datad ENcOSOS R20 O uwen ENG DSD Audio datad ENcpsD2 R19 O uwen ENCDSDAWiodHa2 ENcpsbi P20 O uwen ENG DSD Audiodatat ENcpsbo pis O uwen ENG DSD Audio dataO ENCVSWNC NIT O uwen ENCVSYNCoupu ENCHSYNC NS O uwen ENCHSYNC output ENCDE NS O uwen ENG data enabe mem me O uwen ENC Video data outputO ENcO2 mi O uwen ENC Video data output Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 26 inreviun E mame a 0 se BDesHpion OOO enc ps Lis O LVCMOSSS ENC Video data outputs ENCDA Lis O LVCMOSSS ENC Video data output ENCDs M20 O LVCMOSSS ENG Video data output5 ENCD6 mio O LVCMOSSS ENC Video data output6 ENCD Li O LVCMOSSS ENC Video data output ENCD8 Lie O LVCMOSSS ENCVdeodstaoupu8 ENCDS Liz O LVCMOSSS ENC Video data output9 ENCDIO Ki amp O LVCMOSSS ENC Video data output i0 EncON 420 O LVCMOSSS ENC Video data ouput enc Diz k20 O LVCMOSSS ENC Video data output i2 enc Dia 6 O LVCMOSSS ENC Video data ouput13 ENCDM vio O
9. 192 E mi 6 O2 7TH Figure 6 1 Board Dimensions inclusive of wasteable substrate Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi 7 Description of Components 7 1 Power Supply Structure for the TB FMCL HDMI Board Following figure shows the power supply structure for the board VCC 12V IN LT3503bEDCB VCC 5V ADG702 0 001mA 24LCS22A 3mA TA i sp A 97mA O 485W LT1963AES VCC_3 3V_2 5V FPGA VCCIO 94mA 234mA a LT3503EDCB VCC 3 3V e BE Tr FPGA VCAUX 31mA ADV7510 0 3mA I FPGA VCCIO 244mA ADV7441 251mA SHDN TEC MAX3223 AMA KC3225A 6mA on NC7SZ125 0 02mA LTC1326 0 04mA VCC 3 3V IN LT3568EDD VCC 2 5V 982mA 1235mA LTC3026EMSE VCC 1 8V 3 08W _ ADV7510 325mA si ADV7441 562mA oo LTC3026EMSE VCC 1 2V r Figure 7 1 Power Supply Structure VCC 3 3V 2 5V is used as the I O voltage for FPGA BANK2 BANKS The BANK supports both 3 3V and 2 5V interfaces The interface selection can be performed using JP4 VCCIO_SEL Caution Initial setting by jumper JP4 sets the FPGA IO standard at 2 5V LVDS25 JP4 can provide 3 3V for FPGA lO power but the FPGA configuration ROM is 2 5V device Please contact us if your application requires 3 3V IO Table 7 1 JP4 VCCIO SEL Jumper Setting IO Standard Jumper Setting VCCIO SEL 2 3 Shorted default as shipped Recommended setting Rev 3 00 TOKYO ELECTRON DE
10. FPGAto FMC DATA18 G8 LA7 N CC M1 IO LVCMOS25 FMC to FPGA DATA17 G7 LA17 PCC LA IO LVCMOS25 FPGAto FMC DATA17 G7 LATGN M3 IO LVCMOS25 FMC to FPGA DATA16 G6 LAG P M2 IO LVCMOS25 FPGA to FMC DATA16 G6 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 23 inreviun E Panem 0 Se Dem wen MS 10 WCMOSZS Joere DATAIS GS tap M4 10 uewen FPGAISFMC DATMINGS UM N N 10 LCMOS2S FNC to FPGA DATATA imap N 10 uewen FPGAISFMC DATMINGS iman Ri 10 luewen FNC to FPGA pennen ann Pa IO luewen FMG to FPGA DATATI tame PS 10 LVOMOS25 FPGAISFMC DATAM G wan T2 IO neuen FMC to FPGA DATAS B9 LP T 10 luewen FPGAISFMC DATAWES LP TS 10 LVOMOS25 FPGAISFMC DATANBS Taon US 10 luewen FMC to FPGA DATATE L6 P Rs 10 LVOMOS25 FPGAto FMC DATAS kaos N V2 IO uewen FMC to FPGA DATAS BS iman Wz 10 uewen FMC to FPGA DATAA LP wi 10 uewen FPGAISFMC DATAWBA Lamp YS 10 uewen FPGAISFMC DATANES wen R7 IO VCMOS2S FMC to FPGA DATAZ B2 A0 N CC US 10 LVCMOS2S FMC to FPGA DATAE LAN PCC vs IO LVOMOS25 FPGAto FMG DATATE LA0 N CC us 10 LVCMOS2S FMG to FPGA DATA ciko Mic N va 10 LVOMOS2S Nouse CLKo Mac Pp WS 10 LVOMOS25 FMCtOFPGA Clock eiki macn wio 10 uewen Notused
11. MC The a dia a a FMC connector is mounted on the solder side of the board FMCLPC AA E EN D35 0 31 TX2 TX2 HDMI ENC DE DCLK HSYNC VSYNC TDMS TKAHTKI ENC DSD5 0 ENC DSD CLK ADV7510 TDMS TXOH TXO CLKO M2C P N CLK1 M2C P N ENC 12S3 0 SCLK LRCLK EE cM TDMS TXC TXC ENC DDCA SCL SDA SCL SDA ENC CEC ENC PD ENC INT ENC HPD HDMI Transmitter block FMC Inerface block EEPROM EEPROM SCL Not Mounted EEPROM_ SDA DEC SDA SCL DEC HPD IO HDMI EL Ru Y Eo a RX2 RX2 HDMI so DSW3 0 DEC DE LLC HSYNC VSYNC mjes RX1 RX1 DEC 1283 0 LRCLK SCLK ADV7441 A vous RXosRXO EM L meme M ETE c DLED3 0 DEC_SPDIF DEC_MCLKOUT L suem RXC RXC DEC INT1 INT2 DEC RESETX EXT CLAMP DEC DDCA SCLISDA DDCA SCL SDA DEC DET1 Receiver RS232C UART TXD RXD Block Not Mounted JP Figure 4 1 Block Diagram Primary Interfaces 1 o UL dg Ce Pe HDMI Receive Function FMC Connector to ADV 441A HDMI Transmit Function ADV 7510 to FMC Connector FMC Connector Interface FMC Connector and FPGA JTAG Interface General Purpose Clock Interface General Purpose Switch General Purpose LED Rev 3 00 TOKYO ELECTRON DEVICE LIMITED TB FMCL HDMI Hardware User Manual 5 External View of the Board The following figures show the top and bottom views of the board FPGA HDMI ne ESTE co dere HDMI Transmitter HDMI connector Figure 5 1 Component Side F E arara je
12. TOKYO ELECTRON DEVICE LIMITED 25 inreviun Bi mame o se Da DECDE F uwen DEC aata enaos Dec sa E amp O Wemosas_ DEGloGsealaok_ o DECSDA ar 10 uwen DECI2C serial data DEC EXT CLAMP B7 O LVCMOS33 DEC external CLAMP signal DECIROK ce uwen DECLROlKspml DEC tasa As uwen DECUSAuiosgna3 DEC gs es uwen DECUSAuiosgna2 pec ast as uwen DECUSAuiosgna vec ps0 Fr uwen DECUSAuiosgnaO Dec spor Er uwen DEC SPDIF digtal Audio input DEC DDCA SDAF D6 10 LVCMOS33 DEC slave senal data DEC DOCA SCLF cs uewen DEG slave serial cock DECCEC ca 10 uwen DEC CEC signal DECHPDIO M O uwen DEG hot plug contol DEC DEM B3 uwen DEC Detect siga UARLTXD A3 O uwen UART transmit data Not used UART RxD Fe uewen UART receive data Not used EEPROM SOL E6 O LVCMOS33 EEPROM serial ock Not used EEPROM SDA A2 iO LVCMOS33 EEPROM serial data Not used ENCHPDIO v20 O uwen ENG hot plug convo ENCPD w2 O uwen ENC power down signal ENCIROK ute O uwen ENCLROLKspna ENcsQK via O uwen ENC Audio serial clock ECM T O uwen ENG 125 Audio signats enc i282 10 O uwen ENCUSAuiosgna2 C encsi tis O uwen ENG 125 Audio signait enc aso
13. VICE LIMITED inreviun Bi HDMI Transmitter block The HDMI connector is the 5002541927 Molex The HDMI transmitter device is the ADV7510BSTZ Analog Devices The following EMI ESD devices are used ESD ESD Suppressor RCLAMP0524P SEMTEC ESD ESD Suppressor RCLAMP0504P SEMTEC Following table shows the HDMI transmitter connector pin assignments Table 7 2 HDMI Connector Transmit Side 2 TMDSSH D2 TMDS Transmit Data 2 Shad 3 TMDSDATAZ TDS Transmit Da2 4 MOS DATM TMDSTransmitData1 o 5 TMDSSHDi TMDSTensmiDataiGNed 6 TMDSDATAH TMDSTenmiDaai 8 TMDSSH DO TMDS Transmit Data Shield 9 TMDSDATAD TMDSTanmiDaa Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi HDMI Receiver block The HDMI connector is the 5002541927 Molex The HDMI Transmitter device is the ADV 7441ABSTZ Analog Devices The following EMI ESD devices are used ESD ESD Suppressor RCLAMP0524P SEMTEC ESD ESD Suppressor RCLAMP0504P SEMTEC Following table shows the HDMI receiver connector pin assignments Table 7 3 HDMI Connector Receiver Side 2 TMDSSHLD2 TMDS Receiver Data 2 Shed a TMDSDATA2 TMDS Receive Data Shield 4 TMDSDATAI TMDS Receive Data t o 5 TWDSSHLD1 TMDS Receive Data Sed 6 MDSDATM TMDS Receive Datat flo 8 TMDSSHLDO l TMDSReceive Data 0 Shield 9 MDSDATA TMDSReeveDaa0 The receiver circuit ha
14. any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi 1 Related Documents and Accessories Related documents All documents relating to this board can be downloaded from the TED website https www teldevice co jp ppg cgi bin HotLine swTopEng cgi indexEng htm Please see attached paper on the producis Board accessories FMC spacer set Spacer 4 Large 2 small 2 Screws 6 Jumper socket set Jumper socket 5 FPGA Bitstream Version 2 0 goes with board revision 3 0 2 Overview This board provides HDMI receive and transmit functions It uses the Samtec FMC connector Low Pin Count and Molex HDMI connectors The board is designed for connection with the platform board for example the TB 6S LX150T IMG with a Low Pin Count connector Notice 1 This board uses Analog Devices Inc ADV7441A Encoder and ADV7510 Decoder These devices do not support High bandwidth Digital Content Protection HDCP functions 2 The ADV7441A Encoder is capable of accepting 8 or 12 bits per pixe
15. cates the possibility of injury or physical damage in connection with property if Caution the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch Do not disassemble the product Do not attempt this Rev 3 00 TOKYO ELECTRON DEVICE LIMITED TB FMCL HDMI Hardware User Manual inrevium 8 Rev 3 00 N Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact technical support If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates at high speed do not put your hand close to it or touch it Otherwise it may cause injury Do not place the product in an unstable position Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or
16. dified Figure 12 1 Example of Use Rev 2 00 2011 3 3 Not available Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun E Rev 3 00 2011 3 3 PCB version3 xx Yoshioka FPGA version 3 xx Modified 2 Overview Figure 4 1 Block Diagrams 7 2 HDMI Encoder block gt HDMI Transmitter Block Table 7 2 HDMI connector Transmitter side 7 3 HDMI Decoder block gt HDMI Receiver Block Table 7 3 HDMI connector Receiver side 7 5 Other Interfaces Table 8 1 LEDs Table 8 2 Switches Figure 8 1 2 3 4 TB FMCL HDMI connections Table 11 1 Initial setting JP Table 11 2 Initial setting DIPSW 12 Example of Use 13 Others Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun E Table of Contents 1 Related Documents and Accessories aaa aka kakaa aaa kakaa nnne nnns 10 EEG UU EE 10 gt emm 11 Bx BIOO dB em 12 5 External View of the Board 13 b Board PECINA E 14 7 Description of Components LL aaa aaa aaa aaa aka kaaa kaaa kakaa kaaa kakaa kaaa 15 7 1 Power Supply Structure for the TB FMCL HDMI Board 15 7 2 FMC CONNECCION iam raia ip 18 1 3 Other Interfaces eaaaa nakana aka aaa kaaa aaa aaa kaaa aaa anna 20 7 3 1 JTAG Interface ar Ra 20 1 9 2 General Purpose Clock Interface eee nns 20 8 Status Display and Operation Functions ccccoccncccccncccccnnccncnononcncnnnnnnnonnnononnnnnnnnnnnnnnnnnnnnnnnnnnos 21 8 1 1 DISPIEV Et ee aasre e RAR l ES E me NE e akas a 21 8 1 2 Operation FUNCION erratas 21
17. electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash on it Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may be damaged and break down or it may cause a fire or electric shock Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity TOKYO ELECTRON DEVICE LIMITED inreviun E N Caution Do not use or place the product in the following locations Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Static locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the product may be damaged Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi B Disclaimer This product is intended for use simultaneously as a High Definition Mu
18. eviun Bi Table 7 6 shows the FMC connector pin assignment Table 7 6 FMC Connector Pin Assignment 6 per op mpe GND 8 op Ire og aen o Ls ee wwe wr o exo wen web Lx p mx wr ee uun 39 MAN op en ur Le cw Tee oe UN Ta op tined or GND 3 sb T0 on or 9 eo SAX me on en ms wee oo ae Go me UN UMP Ls p cw LS e mW 36 op an or o en er a an om en 39 an ep mp op 40 om Lon om VAM Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi 7 3 Other Interfaces The board has the following interfaces 1 3 1 JTAG Interface The board has a JTAG connector to permit FPGA configuration by the user JTAG connector 87832 1420 Molex Table 7 7 JTAG Connector 7 3 2 General Purpose Clock Interface The board has a general purpose clock oscillator Kyocera KC5032C027 0000C30E00 which supplies a 2 MHz clock to the FPGA Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 20 inreviun Bi 8 Status Display and Operation Functions The board provides a variety of status display and operation functions using various LEDs and switches 8 1 1 Display Function The following table shows the onboard LEDs and their functions Table 8 1 LEDs 8 1 2 Operation Function Following table shows the onboard switches and their functions Table 8 2 Switches Color depth select ON 10bit OFF 8bit Output setting
19. inreviun Bi TB FMCL HDMI Hardware User Manual Rev 3 00 For hardware revision 3 0 TOKYO ELECTRON DEVICE LIMITED inreviun Bi Revision History Rev 1 01 2010 05 27 2 Overview Add notice of ADV 7441A Yoshioka Table 8 1 LED function modified Table 8 2 Switch function modified Table 9 1 FPGA Ping assign modified Table 11 2 Default setting of DIP SW modified 12 Example of use Add comment Rev1 02 2010 05 28 Table 9 1 Changed Ping assign Rev 1 03 2010 05 31 Changed document format Rev 1 04 2010 06 16 Table 9 1 Changed Ping assign Rev 1 05 2010 06 24 Modified disclaimer Yoshioka Modified Table 8 1 LEDs Modified Table 8 2 Switches Added Figure 8 1 S1 3 is ON of connection Added Figure 8 2 S1 3 is OFF of connection Modified Table 11 2 Default settings Rev 1 06 2010 07 01 Modified disclaimer Yoshioka Modified related document and accessories Modified Figure 5 1 5 2 Overview Modified Table 7 4 SCL SDA settings Modified Table 8 2 SW Operation Added Figure 8 1 2 Cable connections Modified Figure 11 1 Default switch settings Modified Table 11 1 Default Jumper settings Modified Table 11 2 Default DIP switch settings Modified Figure 12 1 Example of use Rev 1 07 2010 07 24 Added Figure 8 1 S1 3 is ON of connection Yoshioka TTT e Rev 1 08 2010 10 19 Modified Table 7 1 VCCIO SEL Jumper Setting Yoshioka Modified Table 9 1 FPGA Pin Assignment Modified Table 11 1 Default Jumper Settings Mo
20. l input videobut the output format is 8 or 10 bits per pixel due to the FPGA to ADV7441A interface width limitation of 10 bits color When receiving a 12 bit input signal the output is reduced to 10bits LSB 2 bits dropped Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi 3 Features FMC Connector Samtec FMC Low Pin Count connector HDMI Connector Molex 5002541927 Power Selection Supply voltage is selectable using an onboard jumper switch K G F E D C GND E mb Mel ME JAP LA0BN Mp NC Me LAN GM 15 e Ne Ne E TC TAIL sw E KP KC e EE LA16 m AI LAIS NC c AA ImTOO GND GND 281 EL EE TD SER SM uer ll uzr j 27 Ei e tes mM do ano en 28 te tod ae ERES Lo No 1 NI GO GO es NC NC LAN GND To NE 30 NC an Le nn ME NO Mo LAG Leen TOME ae ALAN E RT MARA 33 NC E mW sr lel i e Mime Hu Laso E ASIN NG E 3 NO TOM Lean MN cGND MO 1 mM 1 36 NC L NC lo Y lassp NwG HG 37 rr IBI CT 3p NO To MO LAN f GND NC NG Mo tomo 4 NC NO LPC Connector zlalajslalslalg slalalslalg a a a PE app EE 2 S S S S SSS m il E LPC Connector LPC Connector LPC Connector Figure 3 1 FMC Connector Pinout Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 11 inreviun Bi 4 Block Diagram Figure 4 1 shows the block diagram of the TB FMCL HDMI FPGA Mezzanine Card F
21. ltimedia Interface HDMI receiver and as an HDMI transmitter Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 3 Damage of this product not due to our responsibility or failure due to modification 4 Any consequences or other abnormalities arising from use of this product or Damage by connections which do not meet the following conditions Do not input video source when this product is not powered on Do not connect disconnect when this product is powered on Do not misconnect Input to output or output to input This product has been developed for research testing or evaluation It is not authorized for use in
22. mple of use when the loop back path is enabled by jumper selection Please be careful with onboard jumper settings If video is not see at the HDMI TX output press pushbutton S4 longer than 3 seconds to force a re configuration of the TB FMCL HDMI FPGA P Ca All setting of TB FMCL HDMI are default p b ES uninaju O ET 8 TB FMCL HDMI is connected to ME da Ze i Ed up SES m mE CN6 of TB 6S LX150T IMG2 CENE ae ieli SCH JP2 1 2 Short 2 5V 4 JP6 7 A Wns yaa Open KE pa dea TRA Figure 12 1 Example of Use Table 12 1 Jumper Settings in the Example Bank2 IO voltage setting 2 5V 3 3V FMC3 VADJ voltage setting 2 5V 3 3V 5V None 2 JP6 7 Open The two jumper settings must always be in the same relative positions The values indicated by boldface are used in the example above Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 30 inreviun Bi m TOKYO ELECTRON DEVICE PLD Solution Division URL http www inrevium jp eng x fpga board E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED
23. r SS E q i paged E EBBB BB F Er a o j E EJE i ja Y dme cut dan mom d ika NE tu res E aa fa d jif TTITIT E V uen KIB am EN ps a A E ARET SE EN A KEELT A ide edddd dB t 22142 FIM PRRI Eur es 3333833333338 1351 oe do KE uy m mom m m ETA M m s A N m M m ou M FEMEA A del Ski Hr Figure 5 2 Solder Side Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 13 inreviun Bi 6 Board Specifications The board specifications are as follows External Dimensions Number of Layers Board Thickness Material FPGA FMC Connector HDMI Connector 135 9 mm W x 69 mm H 8 layers 1 6 mm FR 4 Xilinx XC3S400AN 5FGG400 Samtec ASP 134604 01 Molex 5002541927 Following figure shows the board specifications Unit mm 10 135 9 10 2 D4 ONTH 2 05 0X4 ONTH A R2 g ET f ER v mom 0000 em U17 C12 15 3 56 g9 Ve 14 20 i 4 gt U25 U24 7 10 13 16 19 O MADE IN JAPAN o o o o e e 2020 mu or Ba uw Hu Hi gg o a w c o c o SOUI2 ox Cage ze HIM c ollalo bd 73 9 10 Y 5 UB e 51 l e o OOo 50 B D ba cz U22 U21 _ BIH o o 195 A VCCIO SEL 1 JP4 3 TB FMCL HDMI me m TOKYO ELECTRON DEVICE LIMITED http ppg teldevice co jp 8 75 1 E173 iu R
24. s an EEPROM Micro Chip 24LCS22A SN containing the Extended Display Information Data EDID for the HDMI input channel The HDMI input sink receive connectors DDC SCL and DDC SDA are connected to jumper JP5 SCL JP6 SDA to permit alternate sources of EDID data Table 7 4 describes the jumper JP5 JP6 settings which permit connection to either the EDID EEPROM or to the Transmit Device Caution The EDID EEPROM contents are for evaluation purposes only and should not be shipped in a product to your end customer Table 7 4 JP5 SCL JP6 SDA Jumper Setting To Transmitter JP5 SCL 2 3 Short JP6 SDA 2 3 Short To EEPROM JP5 SCL 1 2 Short JP6 SDA 1 2 Short Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 17 inreviun Bi 7 2 FMC Connector The FMC connector Low Pin Count which is connected to the main board or carrier card uses a SAMTEC ASP 134604 01 The TB FMCL HDMI board uses both the 12V and 3 3V rails supplied by the main board across the FMC connector An external power supply source can also be used when necessary for loop back testing Jumpers JP7 and JP8 select between FMC and external power sources Table 7 5 JP7 JP8 Jumper Setting Power Supply Jumper Setting FMC Connector JP7 1 2 Short JP8 1 2 Short External Power Supply JP7 2 3 Short JP8 2 3 Short Ze JO EM gina RE al St Soa nn ba fo ieee ii ik SE 12VIN Figure 7 2 TP13 TP14 Location Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inr
25. timput Rev 3 00 TOKYO ELECTRON DEVICE LIMITED inreviun Bi 10 Carrier Card FPGA Interface The following figure shows timing waveforms of the signaling interface between the carrier board FPGA and the TB 6S FMCL HDMI mezzanine FPGA Both interfaces are source synchronous and rising edge clocked FPGA to FMC CLK1 M2C P VSYNC HSYNC DEDATAL A A A A A A A A A A A X e It output these data by falling edge of HDMIRX_CLK FMC to FPGA CLKO M2C P VSYNC HSYNC DEDATALLL A A A A A A A A A X 2 X gt It latch these data by rising edge of HDMIRX CLK Figure 10 1 Timing of input and output signals Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 28 inreviun Bi 11 Default Switch Settings Following figure shows default switch settings see yellow dotted circles uka 8 Qu M E il Mg p ei ur HL Ce K imi Gab Lei TTT R FEE j Lin 2 Y ai ade ll RR E m 4 oi Mar e i he LS Ta jil a lis A i L E g JP8 JP4 Figure 11 1 Default Switch Settings Component Side Table 11 1 Default Jumper Settings Table 11 2 Default DIP Switch Settings External loopback connection select from Receiver to Transmitter ON Receiver to Transmitter loopback SW 1 4 OFF OFF Receiver to FMC FMC to Transmitter no loopback normal operation Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 29 inreviun Bi 12 Example of Use Figure 12 1 show an exa
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