MC56F8013 Gang Programming
Contents
1. semiconductor2. Freescale Semiconductor Application Note Document Number AN3337 Rev 0 11 2007 MC56F8013 Gang Programming by Paulo Knirsch RTAC Americas 1 Introduction This application note describes how to implement a simple gang programming technique for Freescale s MC56F8013 devices using the JTAG interface The proposed programming method does not verify programming success in all devices consequently it is necessary to include a mechanism for verification For this purpose a flash checksum routine was developed in the application s start up code It verifies whether the flash content is equal to the expected code The main objective of gang programming is to reduce the programming time Freescale Semiconductor Inc 2007 All rights reserved NOOR WN Contents KANO ION as Zaden ce tobe ee oho ek eee eee ders 1 Production Flash Programming 2 Tape See oss 6tc0 sens SENE te Nei De wees ax 2 Multiple Target Connection in Series 5 Multiple Target Connection in Parallel 6 Flash Firmware Integrity Check 6 CONCISO eer ee oo e GaSe debe Th het eee CFTR SS 8 I PSA 2 fre escale emiconductor Production Flash Programming 2 Production Flash Programming There are four ways to program the flash blocks in a factory environment This is described in AN3118 Production Flash Programming for the 56F8000 Family e Using the serial bootloader present in the int
3. ble hardware for the JTAG EOnce interface is the CodeWarrior USB TAP This tool is connected to the USB port The gang programming method works with any of these tools They connect with Freescale DSCs via the JTAG EOnce interface The JTAG EOnCE interface connector is illustrated in Figure 3 and described in Table 1 This table briefly describes each pin of the JTAG EOnCE interface Figure 4 describes the JTAG connections in the S6F8013 TDI TDO TCK RESET 3 3V O DE JTAG Connector Figure 3 JTAG EOnCE Connector MC56F8013 Gang Programming Rev 0 Freescale Semiconductor 3 JTAG EOnCE Table 1 JTAG Pins Description PinName Pin Description Test Clock Input This input pin provides the clock to synchronize the test logic It shifts serial data to and from all TAP controllers and the TLM If the EOnCE module is not accessed using the master or 56800E core TAP controllers the maximum TCK frequency is 1 4 the maximum frequency for the 56800E core When accessing the EOnCE module through the 56800E core TAP controller the maximum frequency for TCK is 1 8 the maximum frequency for the 56800E core The TCK pin has a pull down non disabled resistor Test Data Input This input pin provides a serial input data stream to the TAP and the TLM It is sampled on the rising edge of the TCK The TDI has an on chip pullup resistor that can be disabled through PUPEN register in the GPIO module Test Mode Select Input T
4. do 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number AN3337 Rev 0 11 2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in sy
5. ernal flash e Using a commercially available device programmer e Using the J TAG OnCE port e Using GPIO pins with a custom bootloader The programming data speeds are estimated below e SCI serial bootloader 2 5 k words per second e I n circuit JTAG OnCE port 3 k words per second These two programming methods are mainly suitable for low mid volume production lines and generally are too slow for high volume lines Listed at the Freescale website www freescale com under the Freescale Alliance Member Portal are several third parties that offer a variety of production line flash programming solutions The solution described in this application note 1s for a flash gang programming that is easily implemented 3 JTAG EOnCE The flash gang programming method uses a command converter interface This interface is described in Suite56 Parallel Port Command Converter User s Manual This interface allows the connection of digital signal controllers DSC with a PC host to debug and program Freescale DSCs via JTAG EOnce Figure and Figure 2 Parallel Extention i Cable Parallel Target zZ Command System PC Compatible Converter Computer 1 Power Figure 1 Connection via Parallel Command Converter MC56F8013 Gang Programming Rev 0 2 Freescale Semiconductor JTAG EOnCE _ _ Fy i USB Cable Target H System PC Compatible USB TAP i Computer i Figure 2 Connection via USB TAP Another possi
6. his input pin is used to sequence the TAP controllers TLM state machine It is sampled on the rising edge of the TCK The TMS has an on chip pull up resistor that can be disabled through PUPEN register in the GPIO module Test Data Output This three state output pin provides a serial output data stream from the Master TAP or the 56800E core TAP controller It operates in the Shift IR and Shift DR controller states of the TAP controller state machines Output data changes on the falling edge of TCK U1 ANA_O PAO 2 PAO PWMO ANAO PCO ANA 1 PA dl PA1 PWM1 ANA1 PC1 ANA gt PA2 PA2 PWM2 ANA2 VREFHIPC2 HE PA3 PA3 PWM3 ANB 0 PA4 PA4 PWM4 FAULT 1 T2 ANBO PC4 ANB 1 PA5 PA5 PWM5 FAULT2 T3 ANB1 PC5 ANB 2 PAG dl PAG FAULTO ANB2 VREFL PC6 PBO SCLK SCL VDDA ADC HH O 3 3VA PB1 SS SDA VSSA ADC F PB2 MISO T2 PB3 MOSI T3 VY PB4 TO CLKO PB5 T1 FAULT3 VDD IO F O 3 3V PB6 RXD SDA CLKIN PB7 TXD SCL TDI PDO 64 TDO PD1 en TCK PD2 zes TMS PD3 VSS 100 RESET PA VPP VSS 101 JTAG Interface Pins MC56F8013VFAE Figure 4 JTAG Pins Connections to the 56F8013 The command converter and the CodeWarrior USB TAP are not stand alone tools They need to be controlled via a PC to program the DSC In a development environment they can both work with CodeWarrior IDE MC56F8013 Gang Programming Rev 0 4 Freescale Semiconductor Multiple Target Connection in Series Freescale also provides a PC application ca
7. is is located by the DSC hardware in the address range from Ox 1 FF7 to Ox1 FFF For more information regarding the flash configuration field please refer to the 56F8000 Peripheral Manual in the flash memory section MC56F8013 Gang Programming Rev 0 8 Freescale Semiconductor Conclusion MC56F8013 Gang Programming Rev 0 Freescale Semiconductor 9 How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colora
8. ker file The following code is added to the linker file This code forces the programming of the expected checksum in the specified section address SECTIONS Elashchecksec WRITEW Ox1f6adicc t gt flashcheck MC56F8013 Gang Programming Rev 0 Freescale Semiconductor 7 Conclusion Bean Inspector Cpu 56F8013VFAE mn x Bean Items Visibility Help lt gt Peripheral Initialization gt Properties Methods Events Build options Used Comment Compiler Metrowerks DSPCQ a Unhandled interupts 0 E User initialization _ string list string list User code after PE ini string list E Generate linker file ve pROM xFAM mode ve T En m z a T g cu k IE wa zink i o 200 MemorAreal MemorAreal El MemoArea2 E MemorgArea3 O Oo Z O ROM7RAM AreEnabled BANEN JF BASIC ADVANCED EXPERT Bean Level High Level Bean 4 Figure 7 Extra Section Creation via Processor Expert 7 Conclusion This application note proposes a very simple and low cost solution for the MC56F8013 gang programming via JTAG interface and reduces the production line flash programming time This method requires a flash firmware integrity check that verifies correct programming of all parts As an important improvement the flash expected checksum is located in another flash address other then Ox 1 FFE and does not overlap with the flash configuration field Th
9. lled 56800E Flash Programmer It is suitable for a low volume production environment as well as in field firmware upgrades The 56800E Flash Programmer is provided in two forms The first is command line oriented This allows easy integration with scripts The second is a graphical user interface GUI This runs in windows to allow easy rapid flash loading onto the target device The command line version is backwards compatible with the old flash over the JTAG tool The 56800E Flash Programmer can be downloaded at www freescale com Flash programming tool for 5 6F83xx 1xx and 56F801x DSCs Requires installation of CodeWarrior 7 2 or higher 4 Multiple Target Connection in Series Multiple target devices may be connected in series This allows a single command converter JTAG OnCE connector to control multiple devices as in Figure 5 Data flows from the JTAG host to each JTAG implementation through TDI out through TDO and back into TDI in the next chip eventually returning to the JTAG host RESET TRST EEE HE BEE ee ee m TDO TRST RESET TDI TDO D TDI TDO TDI TDO F A TDI TDO TMS TCK TMS i CK TMS TCK TMS TCK TMS TCK TMS TDI a a HE i TCK es ee GE eee ee _ u TMS el __ Maximum of 4 Loads on TCK Circuits Buffer 74HCT244 or Similar Figure 5 Multiple Target Connection in Series In a series programming method the devices are programmed sequentially this means one by one Consequently this sol
10. s and sweeps all flash addresses excluding the addresses 0x 1 FFE and Ox1 FFF These last two specific addresses store the expected checksum and are not included in the checksum calculations UWord16 YerityFlashIntegrity void UWWord3 CheckSum 0 UWord1l6 ptr for ptr 00000 ptr lt OslFFE ptr CheckSum ReadProgramMemoryviptr 1f CheckSum FlashSignature return 1 else return 0 The read program memory is an optimized routine for accessing data in the program flash It has an input pointer for specifying the reading address and as output it returns a word with the data asm UWord16 ReadProgranMenory UWord16 Address moveu w WO RU mowe w P ROj3 0 rts Finally the flash signature routine reads the expected checksum already programmed in flash and returns it as a double word Below is the routine code asm UWord3 FlashSignature void i move w OxLFFE Y moveu w O RO move w P R01 W 0 move YO A0 move w P RO3 Al rts The last important point is how to program the expected checksum in specified addresses This is done via a linker file edition For using processor EXPERT an extra memory section is created as shown in the Figure 7 The address is where the expected checksum is programmed After creating this memory section the generate linker file option in EXPERT processor is turned off This procedure prevents overwriting the changes that are done in the lin
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12. uccessful the firmware signals it to the external world via an Led or any other user interface This signal must be verified in the production line together with other tests Figure 6 Multiple Target Connection in Parallel 6 Flash Firmware Integrity Check The firmware integrity check routine calculates a 32 bit checksum over the whole flash program area The firmware verifies 1f it is equal with the predefined expected value If the verification succeeds the code executes normally the applications code If the check fails the application execution is blocked The code lines below illustrate a simple use of the flash firmware integrity check void main vold ifi VeriftyFlashIntegrity j bor 2 4 arr Processor Expert internal initialization DON T REMOVE THIS CODE sa PE low level initi End of Processor Expert internal initialization ER Write your code here 7 Table D fort Jor The verify flash integrity routine verifies the flash content after executing the start up code If it succeeds the application initialization code executes normally as well as the application code If it fails the MC56F8013 Gang Programming Rev 0 6 Freescale Semiconductor Flash Firmware Integrity Check application code is blocked and the program execution is trapped in an infinite loop If the COP watchdog is enabled the DSC resets The verify flash integrity routine code is shown below A pointer ptr appear
13. ution reduces the connecting time Multiple devices can be connected at the same time in the programmer This programming topology also requires the development of a JTAG controller capable of addressing multiple devices 5 Multiple Target Connection in Parallel A system is developed to make the gang programming simple This system connects four MC56F8013 with the same JTAG connector according with the schematics in Figure 6 Connected in parallel are the pins RESET TCK TMS VDD and GND MC56F8013 Gang Programming Rev 0 Freescale Semiconductor 5 Flash Firmware Integrity Check The TDI is also connected parallel with the four DSCs supplying them with the programming data command stream The TDO is connected to a DSC to avoid a short circuit with multiple devices The DSC must always be connected to the programming circuits It acts as the feedback supplier to the JTAG programmer This makes it possible to gang program four DSCs with the same JTAG interface The programming time is around 4 5 s The main drawback of this implementation is that only one DSC has its programming success guaranteed the DSC with the TDO signal connected to the JTAG interface All the other DSCs go through a blind programming process and the correct programming can not be verified via the JTAG host The proposed solution for this drawback is to include in the DSC a flash firmware integrity check at the beginning of the application If the check 1s s
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