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LPC3141/3143

1. 1 8 V and 3 3 V 5 8 Symbol Parameter Conditions Min Typ Max Unit tsua address set up time 1xLCDCLK ns thia address hold time 2xLCDCLK ns access cycle time 5xLCDOLK ns tw en W write enable pulse width 2xLCDCLK ns lw en R read enable pulse width 2xLCDCLK ns tr rise time 2 5 ns tr fall time 2 5 ns tsu D data input set up time ibd ns th D data input hold time lt tbd gt ns taav data output valid delay time 1xLCDCLK ns ldis Q data output disable time 2xLCDCLK ns Timing is determined by the LCD Interface Control Register fields INVERT_CS 1 MI 0 PS 0 INVERT E RD 0 See the LPC314x user manual th A mLCD_CSB tw en R and twien W _ mLCD_RW_WR mLCD_E_RD mLCD DB 15 0 16 bit mode mLCD DB 15 8 8 bit mode mLCD DB 15 12 4 bit mode mLCD DB 15 0 16 bit mode mLCD DB 15 8 8 bit mode mLCD DB 15 12 4 bit mode write access 002aae207 Fig 12 LCD timing Intel 8080 mode LPC3141 3143 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 48 of 74 NXP Semiconductors LPC3141 3143 9 1 2 Motorola 6800 mode Table 16 Dynamic characteristics LCD controller in Motorola 6800 mode 25 pF Tamb 40 C t
2. 3 Typical x x TRP TWH x TWP x TCLS x TCLH x TALS x TALH x TCS TCH Unit ns ns ns ns ns ns ns ns ns ns 1 NANDFLASH see LPC314x user manual 2 See registers NandTiming1 and NandTiming2 in the LPC314x user manual 3 Each timing parameter can be set from 7 clock cycles to 1 clock cycle A programmed zero value is treated as a one mNAND NCS EBI NWE EBI A 1 CLE tcLs A 0 ALE tALS DOM 0 NOE lALH tap 002aae353 Fig 19 NAND flash controller write and read timing All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 57 of 74 NXP Semiconductors LPC3141 3143 9 5 Crystal oscillator Table 21 Dynamic characteristics crystal oscillator Symbol Parameter Conditions Min Typ Max Unit fosc oscillator frequency 10 12 25 MHz clock duty cycle 45 50 55 96 oscillator capacitance input on pin 2 pF FFAST IN output on pin 0 74 pF FFAST OUT tstartup start up time 500 us Parive drive power 100 500 uW 9 6 SPI Table 22 Dynamic characteristics
3. LPC3141 3143 s BUS Low cost low power ARM926EJ microcontrollers with USB High speed OTG SD MMC and NAND flash controller Rev 0 16 27 May 2010 Preliminary data sheet 1 General description The NXP LPC3141 3143 combine a 270 MHz ARM926EJ S CPU core High speed USB 2 0 OTG 192 KB SRAM NAND flash controller flexible external bus interface four channel 10 bit A D and a myriad of serial and parallel interfaces in a single chip targeted at consumer industrial medical and communication markets To optimize system power consumption the LPC3141 3143 have multiple power domains and a very flexible Clock Generation Unit CGU that provides dynamic clock gating and scaling 2 Features and benefits 2 1 Key features W CPU platform 270 MHz 32 bit ARM926EJ S 16 D cache and 16 Memory Management Unit MMU E Internal memory 192 kB embedded SRAM B External memory interface NAND flash controller with 8 bit ECC and AES decryption support LPC3143 only 8 16 bit Multi Port Memory Controller MPMC SDRAM and SRAM Security AES decryption engine LPC3143 only Secure one time programmable memory for AES key storage and customer use 128 bit unique ID per device for DRM schemes Communication and connectivity High speed USB 2 0 OTG Host Device with on chip Two 125 interfaces Integrated master slave SPI
4. E E RIA 19 DMA 20 Interrupt controller 21 Multi layer AHB 21 APB bridge 22 24 Clock Generation Unit CGU 25 Watchdog Timer WDT 26 Input Output Configuration module 27 10 bit Analog to Digital Converter ADC10B 27 Event router 28 Random number generator 29 AES decryption LPC3143 29 Secure One Time Programmable memory OUP ii ii Depp 29 Serial Peripheral Interface 29 Universal Asynchronous Receiver Transmitter UART Reim 30 Pulse Code Modulation PCM interface 30 LCD interface 31 12 master slave interface 31 LCD NAND flash SDRAM multiplexing 32 Pin connections 32 Multiplexing between LCD and MPMC 34 Supply domains 35 Timer module 36 Pulse Width Modulation PWM module 36 System control 36 6 32 e 36 6 32 1 125 AHB 37 7 Limiting values 38 8 Static characteristics 38 8 1 Power consumption 45 9 Dynamic characteristics 48 9 1 L
5. AHB to APB bridge 1 AHB to APB bridge 2 AHB to APB bridge 3 AHB to APB bridge 4 Interrupt controller NAND flash controller MCI SD SDIO USB2 0HS OTG 96 kB ISRAM 96 kB ISRAM 128 kB ROM MPMC Multi Purpose Memory Controller 6 14 bridge bridge is bus bridge between Advanced High performance Bus AHB and the ARM Peripheral Bus APB interface The module supports two different architectures LPC3141 3143 Single clock architecture synchronous bridge The same clock is used at the AHB side and at the APB side of the bridge The AHB to APBA bridge uses this architecture Dual clock architecture asynchronous bridge Different clocks are used at the AHB side and at the APB side of the bridge The AHB to APBO AHB to APB1 AHB to APB2 and bridges use this architecture All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 24 of 74 NXP Semiconductors LPC31 41 31 43 LPC3141 3143 6 15 Clock Generation Unit CGU The clock generation unit generates all clock signals in the system and controls the reset signals for all modules The structure of the CGU is shown in Figure 6 Each output clock generated by the CGU belongs to one of the domains Each clock domain is fed by a single base clock that originates
6. supply domains SUP1 SUP3 SUP4 SUP8 LPC3141_3143 All information provided in this document is subject to legal disclaimers 60 8 2 1 2 25 0 0 79 0 0002 0 89 1 75 90 86 mA mA mA mA mA mA mA mA mW NXP B V 2010 rights reserved Preliminary data sheet Rev 0 16 27 May 2010 46 of 74 NXP Semiconductors LPC31 41 31 43 Table 14 Power consumption continued Symbol Parameter Conditions Min Typ Max Unit Internal SRAM based system operating frequency 270 MHz core 90 MHz bus normal mode power without dynamic clock scaling MMU offl l Ipp Supply current core VDDI 1 2 V 37 95 all other SUP1 supplies VDDA12 1 2 V 2 1 mA USB VDDA12 PL 1 2 V VDDE IOA 1 8 V 2 25 mA VDDE 1 8 V 0 mA VDDE IOC 2 3 3 V 0 79 mA ADC10B_VDDA33 3 3 V 0 0002 mA USB_VDDA33 3 3 V 0 89 mA USB VDDA DRV 3 3 V 1 75 mA P Power dissipation Total for supply domains SUP1 SUP3 SUP4 63 44 mW SUP8 Internal SRAM based system operating frequency 270 MHz core 90 MHz bus normal mode power with dynamic clock scaling MMU 3161 Ipp Supply current core VDDI 1 2 V 17 8 mA all other SUP1 supplies VDDA12 1 2 V 2 1 mA USB VDDA12 PL 1 2 V VDDE IOA 1 8 V 2 25 mA VDDE IOB 1 8 V 0 mA VDDE IOC 2 3 3 V 0 79 mA ADC10B VDDAS33 3 3 V 0 0002 mA USB_VDDA33 3 3 V 0 89 mA USB VDDA DRV 3 3 V 1 75 mA
7. LPC3141 3143 12 Package outline TFBGA180 thin fine pitch ball grid array package 180 balls ball A1 index area SOT570 3 gt WEGE detail X ball A1 index area DIMENSIONS mm are the original dimensions UNIT AY b 1 20 nom 1 06 0 35 0 71 0 45 12 0 min 0 95 12 1 12 0 11 9 OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA PROJECTION ISSUE DATE SOT570 3 98 05 30 08 07 09 Fig 29 LPC3141 3143 TFBGA180 package outline LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 68 of 74 NXP Semiconductors LPC3141 3143 13 Abbreviations LPC3141_3143 Table 30 Abbreviations Acronym A D ADC AES AHB AMBA APB ATA BIU CBC CE CGU CRC DFU DMA DRM DSP EBI ECC EOP ESD FIFO FPGA GF IOCONFIG IOM IrDA ISRAM ISROM JTAG LSB MCI MCU MMC MPMC OTG PCM PHY PLL PWM Description Analog to Digital Analog to Digital Converter Advanced Encryption Standard Advanced H
8. Supports polling the busy flag from LCD controller to off load the CPU from polling Contains a 16 byte FIFO for sending control and data information to the LCD controller Supports maskable interrupts Supports DMA transfers 2 master slave interface The LPC3141 3143 contains two 12C master slave interfaces This module has the following features e 12 0 interface The 12 0 interface is a standard I C compliant bus interface with open drain pins This interface supports functions described in the I2C bus specification for speeds up to 400 kHz This includes multi master operation and allows powering off this device in a working system while leaving the I2C bus functional 12C1 interface The 12 1 interface uses standard I O pins and is intended for use with a single master I2C bus and does not support powering off this device Standard I Os also do not support multi master 2 implementations Supports normal mode 100 kHz SCL All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 31 of 74 NXP Semiconductors LPC31 41 31 43 Fast mode 400 kHz SCLwith 24 MHz APB clock 325 kHz with12 MHz APB clock 175 kHz with 6 MHz APB clock Interrupt support Supports DMA transfers single Four modes of operation Master transmitter Master receiver Slave
9. 0 1 x CB gt 300 ns tr fall time Standard mode lt tbd gt lt tbd gt 300 ns Fast mode 20 0 1x gt 300 ns tBur bus free time between a STOP lt tbd gt lt tbd gt lt tbd gt START condition tLow LOW period of the SCL clock Standard mode 4 7 lt tbd gt lt tbd gt us Fast mode 1 3 lt tbd gt lt tbd gt us tHD STA hold time repeated START lt tbd gt lt tbd gt lt tbd gt condition THIGH HIGH period of the SCL clock Standard mode 4 0 lt tbd gt lt tbd gt us Fast mode 0 6 lt tbd gt lt tbd gt us tsu DAT data set up time Standard mode 250 lt tbd gt lt tbd gt ns Fast mode 100 lt tbd gt lt tbd gt ns tsu sTA set up time for a repeated START lt tbd gt lt tbd gt lt tbd gt condition tsu sTo set up time for STOP condition Standard mode 4 0 lt tbd gt lt tbd gt us Fast mode 0 6 lt tbd gt lt tbd gt us 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed at room temperature 25 nominal supply voltages 3 Bus capacitance Cy in pF from 10 pF to 400 pF LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 63 of 74 NXP Semiconductors LPC31 41 31 43 gt lt m lt tHD STA tHD STA tHIGH ts
10. 1 tsPICLK tsPICLKH tSPICLKL lt lt gt lt gt SCK CPOL 0 SCK CPOL 1 tsPISEDV tsPIOH MOSI DATA VALID DATA VALID tsPIDSU tsPIDH 248 gt MISO DATA VALID DATA VALID 002aad987 Fig 21 SPI master timing CPHA 0 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 59 of 74 NXP Semiconductors LPC3141 3143 SCK CPOL 0 SCK CPOL 1 MOSI MISO tsPICLK tSPICLKH tSPICLKL DATA VALID isPISEDV gt SPIOH DATA VALID DATA VALID Fig 22 SPI slave timing 1 tsPIDSU tsPIDH DATA VALID 002aad988 SCK CPOL 0 MOSI tsPICLK tsPICLKH tSPICLKL SCK CPOL 1 tsPIDSU lt DATA VALID tsPISEDV gt gt tsPIOH MISO DATA VALID DATA VALID lt lt tsPIDH gt DATA VALID 002aad989 Fig 23 SPI slave timing CPHA 0 9 6 1 Texas Instruments synchronous serial mode SSI mode Table 23 Dynamic characteristic SPI interface SSI mode Tamb 40 C to 85 C SUP3 over specified ranges Symbol Parameter Conditions Min Typ 2 Max Unit tsu SPI_MISO SPI_MISO set up time Tamb 25 11 ns measured in S
11. 1 75 mW SUP8 External SDRAM based system operating frequency 270 MHz core 90 MHz bus heavy SDRAM load power without dynamic clock scaling Ipp Supply current core VDDI 1 2 V 86 mA all other SUP1 supplies VDDA12 1 2 V 1 61 mA USB VDDA12 PL 1 2 V VDDE IOA 1 8 V 10 5 mA VDDE IOB 1 8 V 5 8 mA VDDE IOC 3 3 V 0 52 mA ADC10B_VDDA33 3 3 V 0 0002 mA USB VDDAS33 3 3 V 1 66 mA USB_VDDA_DRV 3 3 V 0 895 mA P Power dissipation Total for supply domains SUP1 SUP3 SUP4 144 6 mW SUP8 External SDRAM based system operating frequency 270 MHz core 90 MHz bus heavy SDRAM load power with dynamic clock 213 Ipp Supply current core VDDI 1 2 V 67 mA all other SUP1 supplies VDDA12 1 2 V s 1 61 mA USB VDDA12 PL 1 2V VDDE_IOA 1 8 V 10 5 mA VDDE_IOB 1 8 V 5 8 mA VDDE_IOC 3 3V 0 52 mA ADC10B_VDDA33 3 3 V 0 0002 mA USB VDDA33 3 3 V 1 66 mA USB_VDDA_DRV 3 3 V 0 895 mA P Power dissipation Total for supply domains SUP1 SUP3 SUP4 121 8 mW SUP8 LPC3141_3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 45 of 74 NXP Semiconductors LPC31 41 31 43 Table 14 Power consumption continued Symbol Parameter Conditions Min Typ Max Unit External SDRAM based system operating frequency
12. 102 12 MHz oscillator clock output VDDA12 D11 SUP1 Supply PS3 12 MHz oscillator PLLs analog supply E10 VSSA12 E9 Ground CG1 12 MHz oscillator PLLs analog ground RSTIN N H14 SUP3 DI 0102 System Reset Input active LOW CLK 256FS O H12 SUP3 DO DIO1 Programmable clock output fractionally derived from CLK1024FS BASE clock domain Generally used for external audio codec master clock CLOCK OUT J4 SUP4 DO 0104 Programmable clock output fractionally derived from SYS BASE clock domain SYSCLK G13 SUPS DO DIO1 Programmable clock output Output one of seven base reference input clocks No fractional divider 10 bit ADC ADC10B VDDAS33 A13 SUP3 Supply PS3 10 bit ADC analog supply ADC10B_GNDA A12 Ground CG1 10 bit ADC analog ground ADC10B GPAO 814 SUP3 AIO1 10 bit ADC analog input ADC10B GPA1 A14 SUP3 AIO1 10 bit ADC analog input ADC10B GPA2 813 SUP3 AIO1 10 bit ADC analog input ADC10B_GPA3 C14 SUP3 AIO1 10 bit ADC analog input USB HS 2 0 OTG USB VBUS L2 SUP5 AlO3 USB supply detection line USB ID M1 SUP3 AIO1 Indicates to the USB transceiver whether in device USB ID HIGH or host USB ID LOW mode contains internal pull up resistor USB RREF J5 SUP3 AIO AIO1 USB connection for external reference resistor 12 1 to analog ground supply USB DP P2 SUP3 AIO AIO1 USB D connection with integrated 45 LPC3141 3143 All information provided in
13. charged device model 1 The following applies to the limiting values Typ Max Unit 43 6 V 43 6 V 4 mA 25 4125 150 25 85 500 V 4100 V 500 V a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Dependent on package type 3 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 series resistor 8 Static characteristics Table 12 Static characteristics 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Supply pins VpD O input output supply NAND flash controller 1 65 voltage pads SUP4 and LCD interface SUP8 1 8 V mode NAND flash controller 2 5 pads SUP4 and LCD interface SUP8 3 3 V mode other peripherals 2 7 SUP 3 VDD CORE core supply voltage SUP1 13 Vpp osc oscillator and PLL on pin VDDA12 for 1 0 supply voltage 12 MHz oscillator SUP1 LPC3141_3143 All information provided in this document is subject to legal disclaimers Typ Max Unit 1 8 1 95 V 3 3 3 6 V 3 3 3 6 V 1 2 1 3 V 1 2 1 3 V NXP B
14. lt tbd gt lt tbd gt ns tw pulse width LOW tbd tbd lt tbd gt ns twa data output valid time I2STX_DATAx lt tbd gt tbd tbd ns on pin 125 WSxll lt tbd gt lt tbd gt lt tbd gt ns input tsu d data input set up time on pin IISRX lt tbd gt lt tbd gt lt tbd gt ns on pin l2SRX_WSx lt tbd gt lt tbd gt lt tbd gt ns tha data output hold time on pin I2SRX_DATAx lt tbd gt lt tbd gt lt tbd gt ns on l2SRX_WSx lt tbd gt lt tbd gt lt tbd gt ns 1 0 1 125 SCK 125 SDA X X I2STX WS 002aad992 Fig 25 125 timing output LPC3141 3143 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 62 of 74 NXP Semiconductors LPC3141 3143 I2SRX 5 IPSRX SDA tho IPSRX WS tsu D the 002aad993 Fig 26 125 timing input 9 8 2 Table 25 Dynamic characteristic I2C bus pins 40 to 85 Symbol Parameter Conditions Min Unit SCL clock frequency Standard mode 0 lt tbd gt 100 kHz Fast mode 0 lt tbd gt 400 kHz output fall time Vin to Vi 20 01 ns tr rise time Standard mode lt tbd gt lt tbd gt 1000 ns Fast mode 20
15. 85 unless otherwise specified 1 8 V and 3 3 V SUP8 Symbol Parameter Conditions Min Typ Max Unit clock cycle time 5xLCDCLK ns tw clk H HIGH clock pulse width 3xLCDCLK ns tw clk L LOW clock pulse width 2xLCDCLK ns tr rise time 2 5 ns ti fall time 2 5 ns tsu A address set up time 3xLCDCLK ns tha address hold time 2xLCDCLK ns tsu D data input set up time lt tbd gt ns 150 data input hold time tbd ns tsu S chip select set up time 3xLCDCLK ns ins chip select hold time 1xLCDCLK ns ta av data output valid delay time 1xLCDCLK ns Timing is determined by the LCD Interface Control Register fields PS 1 SERIAL SHIFT 3 SERIAL READ POS 3 See the LPC314x user manual mLCD CSB mLCD RS mLCD DB13 serial clock mLCD DB14 serial data in mLCD DB15 serial data out 002aae209 Fig 14 LCD timing serial mode LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 rights reserved Preliminary data sheet Rev 0 16 27 May 2010 50 of 74 NXP Semiconductors LPC31 41 31 43 9 2 SRAM controller Table 18 Dynamic characteristics static external memory interface C 25 pF Tamb 40 to 85 unless otherwise specified 1 8 V and 3 3 V SUP8 Symbol Parameter Conditions Min Max Un
16. P Power dissipation Total for supply domains SUP1 SUP3 SUP4 39 26 mW SUP8 1 12 Mhz oscillator running PLLs off SYS BASE and AHB APBO BASE Base domain clocks are enabled driven by 12 Mhz oscillator all peripherals off SUP4 buffers set to input w PD SUP8 and SUP3 buffers set to input w repeater Shutting off the 12 Mhz osc will reduce power to 1 4 mW requires a RSTIN N to run again 2 Running Linux with 100 load all peripherals on instruction and data caches on MMU 3 Dynamic clock scaling active hardware will automatically switch the SYSBASE clocks to a slow clock 180 64 2 81 MHz during times of bus inactivity ARM926 and NAND flash clocks are not scaled for this test 4 Running Linux idle at prompt all peripherals on instruction and data caches on MMU on 5 Running Dhrystone test 600 k sec UART and timers enabled instruction and data caches on MMU on 6 Running Dhrystone test 121 83 k sec UART and timers enabled instruction and data caches off MMU off LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 47 of 74 NXP Semiconductors LPC31 41 31 43 9 Dynamic characteristics 91 LCD controller 9 1 1 Intel 8080 mode Table 15 Dynamic characteristics LCD controller in Intel 8080 mode 25 pF Tamb 40 C to 85 unless otherwise specified
17. Two master slave 12 interfaces Fast UART Memory Card Interface MCI MMC SD SDIO CE ATA Four channel 10 bit ADC Integrated 4 8 16 bit 6800 8080 compatible LCD interface System functions Dynamic clock gating and scaling Multiple power domains NXP Semiconductors LPC31 41 131 43 Selectable boot up SPI flash NAND flash SD MMC cards UART USB On the LPC3143 only secure booting using an AES decryption engine from SPI flash NAND flash SD MMC cards UART or USB DMA controller Four 32 bit timers Watchdog timer PWM module Master slave PCM interface Random Number Generator RNG General Purpose I O pins GPIO Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access B Operating voltage and temperature Core voltage 1 2 V voltages 1 8 V 3 3 V Temperature 40 C to 85 TFBGA180 package 12 x 12 mm 0 8 mm pitch 3 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC3141FET180 TFBGA180 Plastic thin fine pitch ball grid array package 180 balls body 12 x 12 x 0 8 mm SOT570 3 LPC3143FET180 TFBGA180 Plastic thin fine pitch ball grid array package 180 balls body 12 x 12 x 0 8 mm SOT570 3 3 1 Ordering options Table 2 Ordering options for LPC3141 3143 Type number Core bus Total Security High speed US
18. accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Con
19. giving a minimum Hamming distance of 11 Up to 8 symbol errors can be corrected per codeword Error correction can be turned on and off to match the demands of the application Parity generator for error correction encoding Wear leveling information can be integrated into protected data Interrupts generated after completion of error correction task with three interrupt registers Error correction statistics distributed to ARM using interrupt scheme Interface is compatible with the ARM External Bus Interface EBI 6 5 Multi Port Memory Controller MPMC The multi port memory controller supports the interface to different memory types for example LPC3141 3143 SDRAM Low power SDRAM Static memory interface This module has the following features Dynamic memory interface support including SDRAM JEDEC low power SDRAM Address line supporting up to 128 MB two 64 8 devices connected to a single chip select of dynamic memory The MPMC has two AHB interfaces a an interface for accessing external memory b a separate control interface to program the MPMC This enables the MPMC registers to be situated in memory with other system peripheral registers Low transaction latency Read and write buffers to reduce latency and to improve performance particularly for un cached processors Static memory features include asynchronous page mode read programmable wait states bu
20. 15 0 lt 5 4 tcsLDv 4 EBI D 15 0 tWELWEH 4 CSLWEL e 4 EBI NWE i 4 4 BLSHDNV tBLSLBLSH t SLBLSL EBI NCAS BLOUT 0 EBI NRAS BLOUT 1 002aae162 Fig 16 External memory write access to static memory LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 53 of 74 NXP Semiconductors LPC31 41 31 43 9 3 SDRAM controller Table 19 Dynamic characteristics of SDR SDRAM memory interface Tamb 40 C to 85 C unless otherwise specified 1 8 V and 3 3 V 5 8 11213 Symbol Parameter Conditions Min Typical Max Unit foper operating frequency 80 90 MHz clock cycle time 11 1 lt tbd gt ns tcLox clock LOW time 5 55 ns tcHcx clock HIGH time 5 55 ns lato output delay time on pin CKE 3 6 ns on pins 3 6 ns EBI NRAS BLOUT EBI NCAS BLOUT EBI NWE EBI NDYCS on pins EBI DOM 1 5 ns EBI DOM 0 NOE thio output hold time on pin 0 13 3 6 ns on pins 0 1 3 6 ns EBI NRAS BLOUT EBI NCAS BLOUT EBI NWE EBI NDYCS on pins EBI DOM 1 1 7 5 ns EBI DOM 0 NOE ta av address valid delay 5 ns time tha address hold time 5 0 1 5 ns taav data output valid 9 ns delay time t
21. 270 MHz core 90 MHz bus normal mode power without dynamic clock scaling Ipp Supply current core VDDI 1 2 V all other SUP1 supplies VDDA12 1 2 V USB VDDA12 PL 1 2 V VDDE IOA 1 8 V VDDE IOB 1 8 V VDDE_IOC 3 3 V ADC10B VDDA33 3 3 V USB VDDA33 3 3 V USB VDDA DRV 3 3 V Power dissipation Total for supply domains SUP1 SUP3 SUP4 SUP8 36 1 1 61 3 79 3 75 0 67 0 0002 1 66 0 895 69 46 mA mA mA mA mA mA mA mA mW External SDRAM based system operating frequency 270 MHz core 90 MHz bus normal mode power with dynamic clock Ipp Supply current core VDDI 1 2 V all other SUP1 supplies VDDA12 1 2 V USB VDDA12 PL 1 2 V VDDE_IOA 1 8 V VDDE 1 8 V VDDE 3 3 V ADC10B VDDA33 3 3 V USB VDDA33 3 3 V USB VDDA DRV 3 3 V P Power dissipation Total for supply domains SUP1 SUP3 SUP4 SUP8 17 8 1 61 3 79 3 75 0 67 0 0002 1 66 0 895 47 5 mA mA mA mA mA mA mA mA mW Internal SRAM based system operating frequency 270 MHz core 90 MHz bus normal mode power without dynamic clock scaling MMU 51 Ipp Supply current core VDDI 1 2 V all other SUP1 supplies VDDA12 1 2 V USB VDDA12 PL 1 2 V VDDE 1 8 V VDDE IOB 1 8 V VDDE IOC 3 3 V ADC10B VDDA33 3 3 V USB VDDA33 3 3 V USB VDDA 3 3 V Power dissipation Total
22. 43 6 32 1 25 AHB interface 125 AHB interface has the following features Supports DMA transfers Transmit FIFO 125 transmit or receive FIFO 125 receive of 4 stereo samples Supports single 16 bit transfers to from the left or right FIFO Supports single 24 bit transfers to from the left or right FIFO Supports 32 bit interleaved transfers with the lower 16 bits representing the left audio sample and the higher 16 bits representing the right audio sample Supports two 16 bit audio samples combined in a 32 bit word 2 left or 2 right samples to reduce busload Provides maskable interrupts for audio status FIFO underrun overrun full half_full not empty for left and right channel separately LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 37 of 74 NXP Semiconductors LPC3141 3143 7 Limiting values Table 11 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min All digital I O pins Vi input voltage 0 5 Vo output voltage 0 5 lo output current VDDE 3 3 V Temperature values Tj junction temperature 40 storage temperature 2 65 Tamb ambient temperature 40 Electrostatic handling cS 500 machine model 100 Vesp electrostatic human body model discharge voltage
23. Interface SPI SPI CS OUTO SUP3 SPI A8 SUPS SPI MISOHI C8 SUP3 SPI B7 SUP3 SPI CS B8 SUP3 Digital power supply VDDI SUP1 VSSI A11 Peripheral power supply VDDE B2 SUP4 VDDE L4 SUP8 VDDE IOC C13 SUPS VSSE C3 VSSE M3 LPC3141 3143 Application Pin function DO DIO DIO DIO DI Supply Ground Supply Supply Supply Ground Ground state after Celltype Description 0104 0104 0104 0104 0104 CS2 CG2 PS1 PS1 PS1 PG1 PG1 SPI chip select output master SPI clock input slave clock output master SPI data input master data output slave SPI data output master data input slave SPI chip select input slave Digital core supply Digital core ground Peripheral supply for NAND flash interface Peripheral supply for SDRAM LCD Peripheral supply All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 8 of 74 NXP Semiconductors LPC3141 3143 Table 4 Pin description continued Pin names with prefix m are multiplexed pins See Table 10 for pin function selection of multiplexed pins Pin name VSSE_IOC LCD interface mLCD_CSBI4 mLCD E mLCD RS mLCD RW mLCD DB 014 mLCD DB 114 mLCD DB 214 mLC
24. JTAGSEL ARM TDO E11 SUP3 DO DIO1 JTAG TPO signal from ARM926 TAP controller BUF TRST N F11 SUPS3 DO DIO1 Buffered TRST out signal Used for connecting an on board TAP controller FPGA DSP etc BUF_TCK 013 SUP3 DO DIO1 Buffered TCK out signal Used for connecting an on board TAP controller FPGA DSP etc BUF TMS 014 SUPS DO DIO1 Buffered TMS out signal Used for connecting an on board TAP controller FPGA DSP etc UART mUART CTS N IISI N13 lt DI GPIO DIO1 UART clear to send active LOW mUART RTS NHIBI P14 SUPS DO GPIO O DIO1 UART ready to send active LOW UART RXD P12 SUP3 DI GPIO DIO1 UART serial input UART TXD I N12 SUP3 DO GPIO DIO1 UART serial output I C bus master slave interface 2 SDAO C10 SUP3 DIO 12 0 serial data line 2 SCLO 010 SUP3 DIO 12 0 serial clock line 2 5 1 E12 SUP3 DIO DIO1 I2C1 bus serial data line 2 SCL1 4l E13 SUP3 DIO DIO1 I2C1 bus serial clock line LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 7 of 74 NXP Semiconductors LPC3141 3143 Table 4 Pin description continued Pin names with prefix m are multiplexed pins See Table 10 for pin function selection of multiplexed pins Pin name BGA Digital Ball I O level Serial Peripheral
25. LCD data 5 LCD data 6 LCD data 7 LCD data 8 8 bit data 0 LCD data 9 8 bit data 1 LCD data 10 8 bit data 2 LCD data 11 8 bit data 3 LCD data 12 8 bit data 4 4 bit data 0 LCD data 13 8 bit data 5 4 bit data 1 serial clock output LCD data 14 8 bit data 6 4 bit data 2 serial data input LCD data 15 8 bit data 7 4 bit data 3 serial data output 25 serial data receive input 25 serial data receive input 25 bit clock 25 bit clock 25 word select 125 word select NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 9 of 74 NXP Semiconductors LPC31 41 131 43 Table 4 Pin description continued Pin names with prefix m are multiplexed pins See Table 10 for pin function selection of multiplexed pins Pin name Digital Application Pin Celltype Description Ball function state level after 1 125 audio output ml2STX_DATAOI4 M13 SUP3 DO GPIO DIO1 125 serial data transmit output 25 BCKO M12 SUP3 DO GPIO DIO1 25 bit clock ml2STX WSOHI M11 SUP3 DO GPIO DIO1 125 word select ml2STX 0 N14 SUPS DO GPIO DIO1 126 serial clock 125 1141 F12 SUP3 DO GPIO DIO1 126 serial data transmit output l2STX E14 SUP3 DO GPIO DIO1 25 bit clock 125 5111 G10 SUP3 DO GPIO DIO1 125 word select General Purpose IO GPIO GPIOOl1 K10 SUP3 GPIO DIO1 General Purp
26. MCI DAT 1 MCI DAT 2 MCI DAT 3 All information provided in this document is subject to legal disclaimers Description LCD DB 3 LCD bidirectional data line 3 A 3 address line 3 LCD DB 4 LCD bidirectional data line 4 EBI A 4 EBI address line 4 LCD DB 5 LCD bidirectional data line 5 EBI A 5 EBI address line 5 LCD DB 6 LCD bidirectional data line 6 EBI A 6 address line 6 LCD DB 7 LCD bidirectional data line 7 A 7 address line 7 LCD DB 8 LCD bidirectional data line 8 EBI A 8 address line 8 LCD DB 9 LCD bidirectional data line 9 EBI A 9 EBI address line 9 LCD DB 10 LCD bidirectional data line 10 EBI A 10 EBI address line 10 LCD DB 11 LCD bidirectional data line 11 EBI A 11 EBI address line 11 LCD DB 12 LCD bidirectional data line 12 EBI A 12 EBI address line 12 LCD DB 13 LCD bidirectional data line 13 EBI A 13 EBI address line 13 LCD DB 14 LCD bidirectional data line 14 EBI A 14 EBI address line 14 LCD DB 15 LCD bidirectional data line 15 EBI A 15 EBI address line 15 GPIO5 General Purpose pin 5 MCI CLK MCI card clock GPIO 6 General Purpose pin 6 MCI CMD MCI card command input output GPIO7 General Purpose pin 7 MCI DAT 0 MCI card data input output line O GPIO8 General Purpose pin 8 MCI DAT 1 MCI card data
27. USB VSSA TERM VDDE IOB 5 mLCD DB 9 6 VSSI 7 VDDI 8 mLCD E RD 9 VSSE IOC 10 VDDE 11 VSSI 12 VDDI 13 VSSE_IOC 14 GPIO2 Row 1 USB ID 2 USB VDDA33 DRV 3 VSSE 4 VSSE_IOB 5 VDDE 6 VSSE IOB 7 8 VSSE 9 VDDE 10 125 DATAO 11 25 50 12 25 BCKO 13 25 DATAO 14 Row 1 USB GNDA 2 USB DM mLCD DB 15 mLCD DB 11 5 mLCD DB 8 6 mLCD DB2 mLCD DB 4 mLCD DB 0 9 mLCD RW WR 10 125 BCKO 11 JTAGSEL 12 UART TXD 13 mUART CTS N 14 25 CLKO LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 5 of 74 NXP Semiconductors LPC3141 3143 Table 3 Pin allocation table continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row P 1 USB VDDA33 2 USB DP mLCD DB 14 4 mLCD DB 13 5 mLCD DB 7 6 mLCD DB 3 7 mLCD DB 5 8 mLCD RS 9 mLCD DB 1 10 TMS 11 l2SRX WSO 12 UART RXD 13 TRST 14 mUART RTS Table4 description Pin names with prefix m are multiplexed pins See Table 10 for pin function selection of multiplexed pins Pin name Digital Application Pin Celltype Description Ball W O function state 21 level after Clock Generation Unit CGU FFAST A10 SUP1 AIO2 12 MHz oscillator clock input FFAST OUT B10 SUP1 AO
28. V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 38 of 74 NXP Semiconductors LPC3141 3143 Table 12 Static characteristics 40 C to 85 C unless otherwise specified Symbol Parameter VDD ADC ADC supply voltage polyfuse programming voltage VBus bus supply voltage USB analog supply voltage 3 3 V PLL analog supply voltage 1 2 V VpDA PLL 1V2 Conditions on pin ADC10B_VDDA33 for 10 bit ADC SUP 3 on pin VPP write on pin VPP read on pin USB VBUS SUP5 on pin USB VDDAS33 SUP 3 on pin USB VDDA33 DRV SUP 3 driver on pin USB VDDA12 SUP1 Input pins and I O pins configured as input Vi input voltage HIGH level input voltage ViL LOW level input voltage Vhys hysteresis voltage lit LOW level input current HIGH level input current llatch I O latch up current lou pull up current lod pull down current LPC3141 3143 SUP3 SUP4 SUP8 SUP3 SUP4 SUP8 SUP4 SUP8 1 8 V mode 3 3 V mode SUP3 Vi 0 V no pull up Vi Vpp ioy pull down 1 5Vpp oy Vi 1 5 inputs with pull up Vi 0 SUP4 SUP8 1 8 V mode SUP4 SUP8 3 3 V mode SUP3 inputs with pull down Vi SUP4 SUP8 1 8 V mode SUP4 SUP8 3 3 V mode SUP3 gud Min 2 7 3 0 1 1 3 0 2 7 1 1 400 550 0 1VDDE IOC lt tbd gt
29. as production test Guaranteed by design differential data lines tpERIOD 4 crossover point differential data to crossover point extended SEO EOP skew source EOP width n X tPERIOD T receiver EOP width tEOPR1 2 002aab561 Fig 28 Differential data to EOP transition skew and EOP width 9 10 10 bit ADC Table 27 Dynamic characteristics 10 bit ADC Symbol Parameter Conditions Min Typ Max Unit fs sampling frequency 10 bit resolution 400 kSamples s 2 bit resolution 1500 kSamples s conversion time 10 bit resolution 11 clock cycles 2 bit resolution 3 clock cycles LPC3141 3143 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 65 of 74 19995 gep 0102 22 91 0 sjeuurejosip j2efgns 3ueuinoop siy Iv VZ 10 99 5715 171091 pamasa 0102 dXN 10 Application information Table 28 LCD panel connections TFBGA pin Pin name Reset function LCD mode default Parallel Serial LCD panel data mapping Control function 16 bit 8 bit 4 bit 6800 8080 K8 mLCD CSB EBI NSTCS 0 LCD CSB LCD LCD CSB LCD CSB L8 mLCD E RD EBI CKE LCD E RD LCD E L
30. code generated by the ECC module After data is read from the NAND flash the error correction module corrects errors and or the AES decryption module can decrypt data AHB MULTI LAYER MATRIX M CONTROLLER DMA transfer request ECC ENCODER DECODER V NAND INTERFACE 1 AES decoder available on LPC3143 only Fig 4 Block diagram of the NAND flash controller 002 083 This module has the following features Dedicated NAND flash interface with hardware controlled read and write accesses Wear leveling support with 516 byte mode Software controlled command and address transfers to support wide range of flash devices Software control mode where the ARM is directly master of the flash device LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 rights reserved Preliminary data sheet Rev 0 16 27 May 2010 15 of 74 NXP Semiconductors LPC31 41 31 43 Support for 8 bit and 16 bit flash devices Support for any page size from 0 5 kB upwards Programmable NAND flash timing parameters Support for up to 4 NAND devices Hardware AES decryption LPC3143 only Error Correction Module ECC for MLC NAND flash support Reed Solomon error correction encoding and decoding Uses Reed Solomon code words with 9 bit symbols over GF 29 a total codeword length of 469 symbols including 10 parity symbols
31. document is subject to legal disclaimers Rev 0 16 27 May 2010 LPC3141 3143 Preliminary data sheet 19995 0102 22 9L 0 pl 30 99 5715 171091 efqns jueuinoop pepi o4d sjeuurejosip Jeba 12 AJ8S81 0102 dXN wem gt ta o th o EBI CKE EBI NCAS BLOUT EBI NWE EBI CKE EBI NRAS BLOUT EBI NDYCS EBLDOMx ta o thio ANNONA tha il EBI A 15 2 BANK BANK ROW COLUMN EBI D 15 0 Fig 18 SDRAM bank activate and write timing ta Qv th Q 102 002aae123 SJOJONPUODIWIS dXN 1 NXP Semiconductors LPC3141 3143 9 4 NAND flash memory controller LPC3141_3143 Table 20 Dynamic characteristics of the NAND Flash memory controller 40 C to 85 unless otherwise specified Symbol tREH trp twp tcLs taLs taLH tcs Parameter RE HIGH hold time RE pulse width WE HIGH hold time WE pulse width CLE set up time CLE hold time ALS set up time ALE hold time CE set up time CE hold time mi2 3 3 3 3 3 mi2 3 3 3 mi2 3
32. external SRAM bank 0 reserved 71 0x1700 9000 configuration registers 0x1700 8000 4 domain 0x1700 0000 APB3 domain 0x1600 0000 APB2d i 128 ISROM 0 1200 0000 LPC3141 3143 OxFFFF FFFF 2 GB pullo 0x8000 0000 2 reserved 0x7000 0800 NAND flash AES buffer 4 domain _ 0x7000 0000 1 0x6000 1000 interrupt controller 0x6000 0000 posenied 2 0 4000 0000 external SDRAM bank 0 0x3000 0000 0x2004 0000 domain 0 2002 0000 0 2000 0000 0 1900 1000 0 1900 0000 Uu reserved USB OTG E reserved E 0x1800 0900 d d 2 0 1300 B000 APB1 domain 0 1300 8000 1 domain APBO doman 0x1300 0000 reserved 0x1202 0000 reserved ENS 0x1105 8000 96 kB ISRAM1 0x1104 0000 APBO domain 96 kB ISRAMO 0x1102 8000 5 reserved uz 0 0000 0000 0x0000 1000 Fig3 LPC3141 3143 memory map reserved NAND flash controller reserved I2SRX 1 125 0 I2STX 1 125 0 125 system config reserved 4 reserved timer 3 timer 2 IOCONFIG SysCReg ADC10B event router 0x1700 8000 0x1700 1000 0x1700 0800 0x1700 0000 0x1600 0280 0x1600 0200 0x1600 0180 0x1600 0100 0x1600 0080 0x1600 0000 0x1500 3000 0x1500 2000 0x1500 1000 0x1500 0800 0x1500 0400 0x1500 0000 0x1300 B000 0x1300 A400 0x1300 A000 0x1300 9000 0x1300 8C00 0x13
33. from one of the available clock sources Within a clock domain fractional dividers are available to divide the base clock to a lower frequency Within most clock domains the output clocks are again grouped into one or more subdomains All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock Therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock The CGU reference clock is generated by the external crystal Furthermore the CGU has several Phase Locked Loop PLL circuits to generate clock signals that can be used for system clocks and or audio clocks All clock sources except the output of the PLLs can be used as reference input for the PLLs This module has the following features Advanced features to optimize the system for low power All output clocks can be disabled individually for flexible power optimization Some modules have automatic clock gating they are only active when bus access to the module is required Variable clock scaling for automatic power optimization of the AHB bus high clock frequency when the bus is active low clock frequency when the bus is idle Clock wake up feature module clocks can be programmed to be activated automatically on the basis of an event detected by the event ro
34. lois mA 0 298 V voltage lu input leakage current VDDE voltage domain 11 1 7 lt tbd gt 25 VDD voltage domain 0 01 lt gt 25 USB common mode input high speed mode 50 200 500 mV voltage full speed low speed 800 2500 mV mode chirp mode 50 600 mV Vidit differential input 100 400 1100 mV voltage 1 The parameter values specified are simulated values LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 41 of 74 NXP Semiconductors LPC3141 3143 Table 13 ADC static characteristics 2 7 V to 3 6 V Tamb 40 C to 85 unless otherwise specified ADC frequency lt tbd gt Symbol Via Cia Nres ADC Ep EL adj Eo Verr FS Parameter Conditions analog input voltage analog input capacitance ADC resolution differential linearity error 21314 integral non linearity 2 5 offset error 216 gain error 2 7 absolute error 218 offset error voltage full scale offset voltage voltage source interface 9 resistance Min 0 Typ Max VDD ADO lt gt 10 1 1 lt tbd gt lt tbd gt lt tbd gt 20 lt gt lt tbd gt Unit pF bit LSB LSB LSB 96 LSB mV mV 1 On pin ADC10B GNDA 2 Conditio
35. of SPI pins 40 C to 85 C for industrial applications Symbol Parameter Min Typ Max Unit SPI master TsPicvc SPI cycle time 22 2 ns tsPICLKH SPICLK HIGH time 11 09 11 14 ns tsPICLKL SPICLK LOW time 11 09 11 14 ns tsPIDSU SPI data set up time ibd lt tbd gt lt tbd gt ns tsPIDH SPI data hold time lt tbd gt lt tbd gt lt tbd gt ns tsplav SPI data output valid time 14 ns tsPIOH SPI output data hold time 9 9 ns SPI slave Tspicyc SPI cycle time lt tbd gt 40 lt tbd gt ns tsPICLKH SPICLK HIGH time lt tbd gt 20 lt tbd gt ns tsPICLKL SPICLK LOW time lt tbd gt 20 lt tbd gt ns tsPIDSU SPI data set up time ibd lt tbd gt lt tbd gt ns tsPIDH SPI data hold time lt tbd gt lt tbd gt lt tbd gt ns tspiav SPI data output valid time lt tbd gt lt tbd gt 14 ns tsPIOH SPI output data hold time 9 9 ns LPC3141_3143 Remark Note that the signal names SCK MISO and MOSI correspond to signals on pins SPI SCK SPI MOSI and SPI_MISO in the following SPI timing diagrams All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 58 of 74 NXP Semiconductors LPC3141 3143 LPC3141_3143 tSPICLK tSPICLKH tSPICLKL SCK CPOL 0 SCK CPOL 1 tsPISEDV tsPIOH MOSI MISO 002aad986 Fig 20 SPI master timing
36. this document is subject to legal disclaimers termination resistor NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 6 of 74 NXP Semiconductors LPC31 41 31 43 Table 4 Pin description continued Pin names with prefix m are multiplexed pins See Table 10 for pin function selection of multiplexed pins Pin name Digital Application Pin Celltype Description Ball function state level after resetl2 USB_DM N2 SUP3 AIO1 USB D connection with integrated 45 termination resistor USB VDDA12 PLL L1 SUP1 Supply PS3 USB PLL supply USB VDDA33 DRV M2 SUPS Supply PS3 USB analog supply for driver USB VDDA33 P1 SUP3 Supply PS3 USB analog supply for PHY USB VSSA TERM L3 Ground CG1 USB analog ground for clean reference for on chip termination resistors USB GNDA N1 Ground CG1 USB analog ground USB VSSA REF K4 Ground CG1 USB analog ground for clean reference JTAG JTAGSEL N11 SUP3 DI PD DIO1 JTAG selection Controls output function of SCAN TDO and ARM TDO signals Must be LOW during power on reset TDI K9 SUP3 DI DIO1 JTAG data input TRST N P13 SUP3 DI DIO1 JTAG TAP Controller Reset Input Must be LOW during power on reset TCK M14 SUP3 DI DIO1 JTAG clock input TMS P10 SUPS DI 0101 JTAG mode select input SCAN TDO F10 SUP3 DO O Z DIO1 JTAG TDO signal from scan TAP controller Pin state is controlled by
37. to peripheral and peripheral to memory MCI Memory to peripheral and peripheral to memory LCD interface Memory to peripheral UART Memory to peripheral and peripheral to memory 12C0 1 bus interfaces Memory to peripheral and peripheral to memory All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 20 of 74 NXP Semiconductors LPC31 41 131 43 Table 9 Peripherals that support DMA Peripheral name Supported transfer types 250 1 receive Peripheral to Memory 250 1 transmit Memory to peripheral interface Memory to peripheral and peripheral to memory 1 AES decryption engine is available on LPC3143 only 6 12 Interrupt controller The interrupt controller collects interrupt requests from multiple devices masks interrupt requests and forwards the combined requests to the processor The interrupt controller also provides facilities to identify the interrupt requesting devices to be served This module has the following features The interrupt controller decodes all the interrupt requests issued by the on chip peripherals Two interrupt lines Fast Interrupt Request FIQ Interrupt Request IRQ to the ARM core The ARM core supports two distinct levels of priority on all interrupt sources FIQ for high priority interrupts and IRQ for normal priority interrupts Software interrupt request capabilit
38. up output connected to the CGU as shown in Figure 8 The output signals are activated when an event for instance a rising edge is detected on one of the input signals The input signals of the event router are connected to relevant internal control signals in the system or to external signals through pins of the LPC3141 3143 This module has the following features Provides programmable routing of input events to multiple outputs for use as interrupts or wake up signals Input events can come from internal signals or from the pins that can be used as GPIO Inputs can be used either directly or latched edge detected as an event source The active level polarity of the input signal for triggering events is programmable Direct events will disappear when the input becomes inactive Latched events will remain active until they are explicitly cleared Each input can be masked globally for all inputs at once Each input can be masked for each output individually Event detect status can be read for each output separately Event detection is fully asynchronous no active clock required Module can be used to generate a system wake up from suspend mode Remark All pins that can be used as GPIO are connected to the event router see Figure 8 Note that they can be used to trigger events when in normal functional mode or in GPIO mode LPC3141 3143 All information provided this document is subject to legal disclai
39. 0 1021 1022 1023 1024 Via LSB offset error IA LSBideal V 1 DD ADO zi 1024 002 752 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity aq b Center of a step of the actual transfer curve Fig 10 ADC characteristics LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 43 of 74 NXP Semiconductors LPC31 41 131 43 LPC31XX AD10B GPA o 3 Pvsi ADCsAMPLE 1 Vssa 002aae 136 Fig 11 Suggested 10 bit ADC interface LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 44 of 74 NXP Semiconductors LPC31 41 31 43 8 1 Power consumption Table 14 Power consumption Symbol Parameter Conditions Min Typ Max Unit Standby power model Ipp Supply current core VDDI 1 2 V 1 1 mA all other SUP1 supplies VDDA12 1 2 V 0 175 mA USB VDDA12 PL 1 2V VDDE IOA 1 8V 0 001 mA VDDE 1 8 V 0 0008 mA VDDE 3 3v 0 065 mA ADC10B_VDDA33 3 3 V 0 mA USB VDDA33 3 3 V 0 mA USB VDDA DRV 3 3 V 0 mA P Power dissipation Total for supply domains SUP1 SUP3 SUP4
40. 0 bits are used for security and other features which are programmed at the customer production line 184 bits are available for customer use 32 bits are used for USB product ID and vendor ID by bootROM DFU mode 128 bits are used for secure key used by BootROM to load secure images Programmable at the customer production line Random read access via sixteen 32 bit registers Flexible read protection mechanism to hide security related data Flexible write protection mechanism Serial Peripheral Interface SPI The SPI module is used for synchronous serial data communication with other devices which support the SPI SSI protocol Examples of the devices that this SPI module can communicate with are memories camera and WiFi g 1 Onthe LPC3141 secure boot is not supported hence these bits are also available for customer use LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 29 of 74 NXP Semiconductors LPC31 41 31 43 The SPI SSI bus is a 5 wire interface and it is suitable for low medium and high data rate transfers This module has the following features Supports Motorola SPI frame format with a word size of 8 16 bits Texas Instruments SSI Synchronous Serial Interface frame format with a word size of 4 bit to 16 bit Receive FIFO and transmit FIFO of 64 hal
41. 00 8800 0x1300 8400 0x1300 8000 0x1300 6000 0x1300 5000 0x1300 4000 0x1300 3000 0x1300 2800 0x1300 2400 0x1300 2000 0x1300 0000 002aae307 6 3 LPC3141 3143 JTAG The Joint Test Action Group JTAG interface allows the incorporation of the LPC3141 3143 in a JTAG scan chain This module has the following features All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 14 of 74 NXP Semiconductors LPC31 41 31 43 ARM926 debug access Boundary scan The ARM926 debug access can be permanently disabled through JTAG security bits in the One Time Programmable memory OTP block 6 4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices Figure 4 shows a block diagram of the NAND flash controller module The heart of the module is formed by a controller block that controls the flow of data from to the AHB bus through the NAND flash controller block to from the external NAND flash An Error Correction Code ECC module allows for hardware error correction for support of Multi Level Cell MLC NAND flash devices The NAND flash controller is connected to the AES block to support secure encrypted code execution see Section 6 21 Before data is written from the buffer to the NAND flash optionally it is first protected by an error correction
42. 4 chip enable 1 NCS 2 4 K1 SUP4 DO 0104 chip enable 2 NAND NCS 3 4 K2 SUP4 DO O DIO4 NAND chip enable 3 mNAND RYBNOHI DI 0104 NAND ready busy 0 _ 1 7 DI 0104 NAND ready busy 1 mNAND RYBN2HI B4 DI 0104 NAND ready busy 2 mNAND RYBN3 D4 SUP4 DI 0104 NAND ready busy 3 EBI NCAS BLOUT 0 G1 SUP4 DO 0104 EBI lower lane byte select 7 0 NRAS BLOUT 14 H2 SUP4 DO 0104 EBI upper lane byte select 15 8 Secure one time programmable memory VPPI6I A9 SUP1 Supply PS3 Supply for polyfuse programming C9 SUP3 Pulse Width Modulation PWM PWM DATAHI B9 SUP3 DO GPIO DIO1 PWM output 1 Digital IO levels are explained in Table 5 2 1 input input with internal weak pull up input with internal weak pull down output 3 Cell types are explained in Table 6 4 Pin can be configured as GPIO pin in the IOCONFIG block 5 UART flow control lines mUART CTS N and mUART RTS are multiplexed This means that if these balls are not required for UART flow control they can be selected to be used for alternative functions SPI chip select signals SPI 5 OUT1 and SPI CS 0072 6 The polyfuses get unintentionally burned at random if VPP is powered to 2 3 V or greater before the VDDI is powered up to minimum nominal voltage This will destroy the sample because randomly blowing security fuses will lock the sample and
43. 4 DIO 0104 data I O 1 D 2Hl F1 SUP4 DIO 0104 data I O 2 D 3Hl E1 SUP4 DIO 0104 data I O 3 D 4Hl E2 50 4 DIO 0104 data I O 4 LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 10 of 74 NXP Semiconductors LPC31 41 131 43 Table 4 Pin description continued Pin names with prefix m are multiplexed pins See Table 10 for pin function selection of multiplexed pins Pin name Digital Application Pin Celltype Description Ball W O function state level after resetl2 D 514 D1 DIO 0104 data I O 5 EBI D 6 4 D2 SUP4 DIO 0104 EBI data 6 D 714 C1 DIO 0104 EBI data 7 EBI D 8 4 B1 DIO DIO4 data 8 D 9 4 DIO 0104 EBI data 9 EBI D 10 4 A1 DIO 0104 data I O 10 D 111 C2 SUP4 DIO 0104 data I O 11 EBI D 1214 SUP4 0104 data I O 12 D 13 4 03 DIO 0104 data I O 13 EBI D 1411 E3 SUP4 DIO 0104 data I O 14 EBI D 1514 F3 DIO 0104 data I O 15 EBI DOM 0 NOEHI H1 SUP4 DO 0104 NAND read enable active LOW EBL NWE I J2 SUP4 DO 0104 NAND write enable active LOW NAND NCS 0 4 J1 SUP4 DO 0104 NAND chip enable 0 NAND NCS 1 4 J3 SUP4 DO 010
44. AND flash must be the same The dedicated LCD interface is not available in the MPMC mode All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 35 of 74 NXP Semiconductors LPC31 41 31 43 6 29 6 30 6 31 6 32 LPC3141 3143 2 Dedicated LCD interface only This is the LCD mode The NAND flash supply voltage can be different from the LCD supply voltage SUP Timer module The LPC3141 3143 contains four fully independent timer modules which can be used to generate interrupts after a pre set time interval has elapsed This module has the following features Each timer is a 32 bit wide down counter with selectable pre scale The pre scaler allows using either the module clock directly or the clock divided by 16 or 256 Two modes of operation Free running timer The timer generates an interrupt when the counter reaches zero The timer wraps around to OXFFFF FFFF and continues counting down Periodic timer The timer generates an interrupt when the counter reaches zero It reloads the value from a load register and continues counting down from that value An interrupt will be generated every time the counter reaches zero This effectively gives a repeated interrupt at a regular interval Atany time the current timer value can be read Atany time the value in the load register may
45. B Internal Static ROM ISROM The internal static ROM is used to store the boot code of the LPC3141 3143 After a reset the ARM processor will start its code execution from this memory The LPC3143 ROM memory has the following features Supports secure booting from SPI flash NAND flash SD SDHC MMC cards and USB DFU class interfaces Supports SHA1 hash checking on the boot image Supports non secure boot from UART and USB DFU class interfaces during development Once AES key is programmed in OTP only secure boot is allowed through UART and USB Supports secure booting from managed NAND devices such as moviNAND iNAND eMMC NAND and eSD NAND using SD MMC boot mode Contains pre defined MMU table 16 kB for simple systems All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 17 of 74 NXP Semiconductors LPC31 41 31 43 6 8 LPC3141 3143 The LPC3141 ROM memory has the following features Supports booting from SPI flash NAND flash SD SDHC MMC cards UART and USB DFU class interfaces Supports option to perform CRC32 checking on the boot image Contains pre defined MMU table 16 kB for simple systems Supports booting from managed NAND devices such as movi NAND iNAND eMMC NAND and eSD NAND using SD MMC boot mode The boot ROM determines the boot mode based on reset s
46. B 10 bit 125 MCI Temperature frequency SRAM engine ADC SDHC range AES channels SDIO CE ATA LPC3141FET180 270 192kB no Device 4 2each yes 40 C to 85 C 90 MHz Host OTG LPC3143FET180 270 192kB yes Device 4 2each yes 40 C to 85 C 90 MHz Host OTG LPC3141_3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 2 of 74 NXP Semiconductors LPC31 41 31 43 4 Block diagram JTAG interface LPC3141 3143 TEST DEBUG USB 2 0 ARM926EJ S HIGH SPEED OTG master master slave slave master master slave slave slave gt 96kBISRAMO MPMC slave MULTI LAYER AHB MATRIX sete 96 kB ISRAM1 slave slave NAND CONTROLLER AESC SD SDIO C C DMA CONTROLLER DATA CACHE 16 kB INSTRUCTION CACHE 16 kB BUFFER slave slave slave i slave slave AHB TO AHB TO AHB TO AHB TO AHB TO APB APB APB APB APB BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE 4 slave group 0 ASYNC ASYNC ASYNC ASYNC SYNC APB slave group 4 WDT T NAND REGISTERS ow sme s APB slave group 3 Sa gt Ce ___ alive group 2 gt on cw o C APB slave group 1 wes J 7 002aae081 Fig 1 LPC3141 3143 block diagr
47. CD RD P8 mLCD RS EBI NDYCS LCD RS LCD RS LCD RS LCD RS N9 mLCD RW WR EBI 1 LCD RW WR LCD RW LCD WR N8 mLCD DB CLKOUT LCD DB 0 LCD DBO P9 mLCD DB 1 EBI NSTCS 1 LCD DB 1 LCD DB 1 N6 mLCD DB 2 EBI A 2 LCD DB 2 LCD DB2 P6 mLCD DB A 3 LCD DB 3 LCD DB3 N7 mLCD DB 4 EBI A 4 LCD DB 4 LCD DB4 P7 mLCD DB 5 EBI A 5 LCD DB 5 LCD DB5 K6 mLCD DB 6 EBI A 6 LCD DB 6 LCD DB6 P5 mLCD DB 7 EBI A 7 LCD DB 7 LCD DB7 N5 mLCD DB 8 EBI A 8 LCD DB 8 LCD DB8 LCD DBO L5 mLCD DB 9 EBI 9 LCD DB 9 LCD DB9 LCD DB1 K7 mLCD DB 10 EBI A 10 LCD DB 10 LCD DB 10 LCD 2 4 mLCD DB 11 EBI A 11 LCD DB 11 LCD DB 11 LCD DB3 K5 mLCD DB 12 EBI A 12 LCD DB 12 LCD DB 12 LCD DB 4 LCD DB P4 mLCD DB 13 EBI A 13 LCD DB 13 LCD DB 13 LCD DB 5 LCD DB 1 SER CLK P3 mLCD DB 14 EBI A 14 LCD DB 14 LCD DB 14 LCD DB 6 LCD DB 2 SER DAT IN N3 mLCD DB 15 EBI A 15 LCD DB 15 LCD DB 15 LCD DB 7 LCD DB 3 SER DAT OUT 5 dXN EVLE LVLEDd 1 NXP Semiconductors LPC31 41 31 43 11 Marking Table 29 LPC3141 3143 Marking Line Marking Description A LPC3141 3143 BASIC TYPE LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 67 of 74 NXP Semiconductors
48. CD controller 48 9 1 1 Intel 8080 48 9 1 2 Motorola 6800 mode 49 9 1 3 Serial mode 50 9 2 SRAM 51 9 3 SDRAM controller 54 9 4 NAND flash memory controller 57 9 5 Crystal 58 9 6 58 9 6 1 Texas Instruments synchronous serial mode SSI 096 ea ERR 60 9 7 25 62 9 8 IC DUS had 63 9 9 USB 65 9 10 10 bit 65 10 Application information 66 11 Marking 67 12 Package 68 13 Abbreviations rn 69 14 Revision history 71 15 Legal information 72 15 1 Data sheet 72 15 2 Definitions e sir pr REESE 72 15 3 Disclaimers 72 15 4 Trademarks 73 16 Contact information 73 17 Contents mk eden 74 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information 2010 For more information ple
49. CMOS with hysteresis programmable pull up pull down repeater DIO2 bpts5pcph Digital input output Bidirectional 5 V plain input 3 state output CMOS with programmable hysteresis programmable pull up pull down repeater DIO4 mem1 Digital input output Bidirectional 1 8 V or 3 3 V plain input 3 state output programmable bsptz40pchp hysteresis programmable pull up pull down repeater iicam4scl Digital input output 12 clock signal IICD iicamvsda Digital input output 1 2 data signal AlO1 apio3v3 Analog input output Analog input output protection to external 3 3 V supply rail AIO2 apio Analog input output Analog input output AlO3 apiot5v Analog input output Analog input output 5 V tolerant pad based ESD protection CS1 vddco Core supply CS2 vddi Core supply PS1 vdde3v3 Peripheral supply PS2 vdde Peripheral supply PS3 vddco3v3 Analog power supply CG1 VSSCO Core ground CG2 vssis Core ground PG1 vsse Peripheral ground LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 12 of 74 NXP Semiconductors LPC31 41 31 43 6 Functional description 6 1 ARM926EJ S The processor embedded in the chip is the ARM926EJ S It is a member of the ARM9 family of general purpose microprocessors The ARM926EJ S is intended for multi tasking applications where full memory man
50. D DB 3 4 mLCD DB 414 mLCD DB 514 mLCD DB 614 mLCD DB 7141 mLCD DB 814 mLCD DB 9 4 mLCD DB 10 4 mLCD DB 11 4 mLCD DB 12 4 mLCD DB 13 4 mLCD DB 14 4 mLCD DB 15 4 l S digital audio input I2SRX DATAOU I2SRX 1 4 I2SRX BCKOl4 I2SRX BCK1l4 I2SRX 5041 I2SRX 5141 LPC3141 3143 BGA Digital Ball level B12 D6 D8 D9 G11 L9 L13 K8 SUP8 L8 SUP8 P8 SUP8 N9 SUP8 SUP8 P9 SUP8 6 SUP8 P6 SUP8 7 SUP8 P7 SUP8 K6 SUP8 P5 SUP8 SUP8 L5 SUP8 K7 SUP8 SUP8 K5 SUP8 P4 SUP8 P3 SUP8 N3 SUP8 M10 SUP3 G14 SUP3 N10 SUP3 F14 SUP3 P11 SUP3 F13 SUP3 Application Pin function Ground DO DO DO DO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DI GPIO DI GPIO DIO GPIO DIO GPIO DIO GPIO DIO GPIO All information provided in this document is subject to legal disclaimers state after OOO 000000000000 Celltype Description PG1 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 0104 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 LCD chip select active LOW LCD 6800 enable or 8080 read enable active HIGH LCD instruction register LOW data register HIGH select LCD 6800 read write select or 8080 write enable active HIGH LCD data 0 LCD data 1 LCD data 2 LCD data 3 LCD data 4
51. DDE short circuit output x Vou 20V current Vpp VDDE_IOx x 0 V lots LOW level short circuit Vpp VDDE_lOx output current x A B Voi Vpp Vpp VDDE x A B Vpp Zo output impedance Vpp x A B C 1 8 V mode 3 3 V mode 2 0 pins loz OFF state output Vo 0 V Vo Vpp current no pull up down LPC3141 3143 pud Min lt tbd gt lt tbd gt Vpp 0 0 26 Vpp 0 0 26 Vpp 0 0 38 tbd lt tbd gt lt tbd gt lt tbd gt lt tbd gt lt tbd gt lt tbd gt lt tbd gt All information provided in this document is subject to legal disclaimers Typ tbd tbd tbd 0 65 Max Unit tbd pF V tbd V lt tbd gt V V V tbd V lt tbd gt V lt tbd gt V mA mA mA mA 0 064 lt tbd gt mA lt tbd gt mA lt tbd gt mA lt tbd gt mA lt tbd gt Q lt tbd gt Q 7 25 NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 40 of 74 NXP Semiconductors LPC31 41 131 43 Table 12 Static characteristics 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit HIGH level input 0 7VDDE IOC V voltage Vit LOW level input O 3VDDE V voltage Vnys hysteresis voltage 0 1VDDE IOC V VoL LOW level output
52. EJ S 9 MASTER slave 0 BRIDGE 0 0 1 2 3 7 6 5 4 AHB APB BRIDGE 1 0 1 2 3 4 5 6 TIMER 0 TIMER 1 2 TIMER 3 AHB APB BRIDGE 2 0 1 2 3 AHB APB 0 2 BRIDGE 3 50 1 BRIDGE 4 1 NAND REGISTERS INTERRUPT CONTROLLER gg CONTROLLER AES BUFFER MCI SD SDIO USB HIGH SPEED OTG ISRAM 0 ISRAM 1 ISROM MPMC CONFIG MULTI LAYER AHB MATRIX master slave connection supported by matrix 1 1 available for LPC3143 only Fig 5 MPMC CONTROLLER 002aae080 LPC3141 3143 multi layer AHB matrix connections LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 23 of 74 NXP Semiconductors LPC31 41 31 43 This module has the following features Supports all combinations of 32 bit masters and slaves fully connected interconnect matrix Round Robin priority mechanism for bus arbitration all masters have the same priority and get bus access in their natural order Four devices on a master port listed in their natural order for bus arbitration DMA 926 instruction port ARM926 data port USB OTG Devices on a slave port some ports are shared between multiple devices AHB to bridge 0
53. I CKE LCD E RD LCD enable read signal EBI CKE EBI SDRAM clock enable mLCD RS LCD RS EBI NDYCS LCD RS LCD register select signal EBI NDYCS EBI SDRAM chip select mLCD RW WR LCD RW WR DQM 1 LCD RW WR LCD read write write signal EBI DQM 1 EBI SDRAM data mask output 1 mLCD DB 2 LCD DB 2 EBI 2 LCD DB 2 LCD bidirectional data line 2 EBI A 2 address line 2 LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 rights reserved Preliminary data sheet Rev 0 16 27 May 2010 32 of 74 NXP Semiconductors LPC3141 3143 Table 10 Pin descriptions of multiplexed pins Pin Name mLCD_DB 3 mLCD_DB 4 mLCD_DB_5 mLCD_DB_6 mLCD DB 7 mLCD DB 8 mLCD DB 9 mLCD DB 10 mLCD DB 11 mLCD DB 12 mLCD DB 13 mLCD DB 14 mLCD DB 15 Storage related pin multiplexing mGPIO5 mGPIO6 mGPIO7 mGPIO8 mGPIO9 mGPIO10 LPC3141_3143 Default Signal Alternate Signal LCD DB 3 LCD DB 4 LCD DB 5 LCD DB 6 LCD DB 7 LCD DB 8 LCD DB 9 LCD DB 10 LCD DB 11 LCD DB 12 LCD DB 13 LCD DB 14 LCD DB 15 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 A 3 A 4 5 6 A 7 8 9 10 A 11 12 13 14 15 MCI MCI DAT 0
54. OC VDDE 8 VSSE IOC 9 VSSE IOC 10 l2C SCLO 11 VDDA12 12 VSSI 13 BUF 14 BUF 5 LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 4 of 74 NXP Semiconductors LPC3141 3143 Table3 Pin allocation table continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row 1 EBI D 3 2 EBIDA 3 EBI D 14 VSSE 5 VDDE 6 RYBNO 7 mNAND RYBN1 VDDE 9 VSSA12 10 VDDA12 11 ARM TDO 12 12 SDA1 13 12 SCL1 14 125 BCK1 Row 1 D 2 2 EBID 1 3 EBI D 15 4 VSSE IOA 5 VDDE 10 SCAN TDO 11 BUF TRST 12 125 DATA1 13 125 WS1 14 125 BCK1 1 EBI NCAS BLOUTO 2 EBIDO 3 EBI D 12 4 VSSI 5 VDDE 10 125 WS1 11 VSSE 12 13 SYSCLK 14 125 DATA1 Row H 1 DQM 0 NOE 2 NRAS BLOUT 1 3 VDDI 4 VSSE IOA 5 10 GPIO12 11 GPIO19 12 CLK 256FS O 13 GPIO11 14 RSTIN_N Row J 1 NAND NCS 0 2 NWE 3 NCS 1 4 OUT 5 USB RREF 10 GPIO1 11 GPIO16 12 GPIO13 13 GPIO15 14 GPIO14 Row K 1 NAND NCS 2 2 NCS 3 VSSE USB VSSA REF 5 mLCD DB 12 6 mLCD DB 6 7 mLCD DB 10 mLCD CSB 9 TDI 10 GPIOO 11 VDDE IOC 12 GPIO17 13 GPIO20 14 GPIO18 5 Row 1 USB VDDA12 PLL 2 USB VBUS 3
55. PI Master mode see Figure 24 1 2 Parameters are valid over operating temperature range unless otherwise specified Typical ratings are not guaranteed The values listed are at room temperature 25 nominal supply voltages Remark Note that the signal names SCK MISO and MOSI correspond to signals on pins SPI SCK SPI MOSI and SPI MISO in the following SPI timing diagram LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 60 of 74 NXP Semiconductors LPC3141 3143 LPC3141_3143 shifting edges 1 i i SCK sampling edges MOSI MISO lsu SPI MISO Fig 24 MISO line set up time in SSI Master mode 002aad326 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 61 of 74 NXP Semiconductors LPC31 41 31 43 9 7 125 Table 24 Dynamic characteristics I2S interface pins 40 to 85 for industrial applications Symbol Parameter Conditions Min Typ Max Unit common to input and output Toy clk clock cycle time lt tbd gt lt tbd gt lt tbd gt ns lr rise time 3 5 tbd lt tbd gt ns tr fall time 3 5 lt tbd gt tbd ns output twH pulse width HIGH lt tbd gt
56. Semiconductors LPC31 41 31 43 6 26 6 27 LPC3141 3143 MP Multi Protocol PCM Configurable directional per slot OM 2 Extended ISDN Oriented modular Double clocking physical format Twelve 8 bit slots in a frame with enabling control per slot Internal frame clock generation in master mode Receive and transmit DMA handshaking using a request clear protocol Interrupt generation per frame PCM Pulse Code Modulation is a very common method used for transmitting analog data in digital format Most common applications of PCM are Digital audio as in Audio CD and computers digital telephony and digital videos The IOM ISDN Oriented Modular interface is primarily used to interconnect telecommunications ICs providing ISDN compatibility It delivers a symmetrical full duplex communication link containing user data control programming lines and status channels LCD interface The dedicated LCD interface contains logic to interface to a 6800 Motorola or a 8080 Intel compatible LCD controller which support 4 8 16 bit modes This module also supports a serial interface mode The speed of the interface can be adjusted in software to match the speed of the connected LCD display This module has the following features 4 8 16 bit parallel interface mode 6800 series 8080 series Serial interface mode Supports multiple frequencies for the 6800 8080 bus to support high and low speed controllers
57. agement high performance and low power are important This module has the following features LPC3141 3143 ARMS926EJ S processor core which uses a five stage pipeline consisting of fetch decode execute memory and write stages The processor supports both the 32 bit ARM and 16 bit Thumb instruction sets which allows a trade off between high performance and high code density The ARM926EJ S also executes an extended ARMV5TE instruction set which includes support for Java byte code execution Contains an AMBA BIU for both data accesses and instruction fetches Memory Management Unit MMU 16 kB instruction and 16 kB data separate cache memories with an 8 word line length The caches are organized using Harvard architecture Little endian is supported The ARM926EJ S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging Supports dynamic clock gating for power reduction The processor core clock can be set equal to the AHB bus clock or to an integer number times the AHB bus clock The processor can be switched dynamically between these settings ARM stall support All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 13 of 74 NXP Semiconductors LPC3141 3143 6 2 Memory map 4GB 1 LPC3143 only external SRAM bank 1
58. also can corrupt the AES key For this reason it is recommended that VPP be powered by SUP1 at power on 7 To ensure that GPIOO GPIO1 and GPIO2 pins come up as inputs pins TRST_N and JTAGSEL must be LOW at power on reset see UM10362 JTAG chapter for details LPC3141_3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 11 of 74 NXP Semiconductors LPC3141 3143 Table 5 Supply domains Supply Voltage range Related supply pins Description domain SUP1 1 0 V to 1 3 V VDDI VDDA12 USB VDDA12 PLL Digital core supply VPP OTP read SUP3 2 7 V to 3 6 V VDDE_IOC ADC10B VDDA33 Peripheral supply USB VDDAS33 DRV USB VDDA33 VPP during OTP write SUP4 1 65 V to 1 95 V in 1 8 V VDDE Peripheral supply for NAND flash mode interface 2 5 V to 3 6 V in 3 3 V mode SUP5 4 5 V to 5 5 V USB_VBUS USB VBUS voltage SUP8 1 65 V to 1 95 V in 1 8 V VDDE_IOB Peripheral supply for mode 2 5 V to 3 1 V in 3 3 V mode SDRAM SRAM bus based LCD When the SDRAM is used the supply voltage of the NAND flash SDRAM and the LCD interface must be the same i e SUP4 and SUP8 should be connected to the same rail See also Section 6 28 3 Table 6 pads Cell type Pad type Function Description DIO1 bspts3chp Digital input output Bidirectional 3 3 V 3 state output 3 ns slew rate control plain input
59. am LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 3 of 74 NXP Semiconductors LPC3141 3143 5 Pinning information 5 1 Pinning ball A1 index area _ gt LPC3141 3143 123456 7 8 9 1011121314 OOOOOOOOOOO000 OOOOOOOOOOO0000 OOOOOOOOOOO0000 OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO 002aae082 Transparent top view Fig 2 LPC3141 3143 pinning TFBGA180 package Table3 Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 EBI D 10 2 EBI A 1 CLE EBI D 9 mGPIO10 5 mGPIO7 6 mGPIO6 SPI CS OUTO SPI SCK 9 VPP 10 FFAST IN 11 VSSI 12 ADC10B GNDA 13 ADC10B_VDDA33 14 ADC10B_GPA1 Row B 1 EBI D 8 2 VDDE IOA EBI A 0 ALE mNAND RYBN2 5 mGPIO8 6 mGPIO5 SPI MOSI SPI CS IN 9 DATA 10 FFAST OUT 11 12 VSSE_IOC 13 ADC10B GPA2 14 ADC10B GPAO Row 1 EBI D 7 2 EBID 11 VSSE VSSE 5 mGPIO9 6 00 VSSI SPI MISO 9 VPP 10 2 SDAO 11 GPIO4 12 VDDI 13 VDDE_IOC 14 ADC10B_GPA3 Row D 1 EBI D 5 2 EBID6 EBI D 13 mNAND RYBN3 5 VDDE 6 VSSE I
60. as such is not complete exhaustive or legally binding Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 16 Contact information whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 15 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V For more information please v
61. ase visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 27 May 2010 Document identifier LPC3141 3143 rights reserved
62. ata invalid 1x HCLK ns time Refer to the LPC314x user manual for the programming of WAITOEN and HCLK 2 Refer to the LPC314x user manual UM10362 for the programming of WAITRD and HCLK 3 WAITRD WAITOEN 1 3 min at 60 MHz 4 Refer to the LPC314x user manual UM10362 for the programming of WAITWEN and HCLK 5 Refer to the LPC314x user manual UM10362 for the programming of WAITWR and HCLK 6 WAITWD WAITWEN 1 3 min at 60 MHz LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 51 of 74 NXP Semiconductors LPC31 41 31 43 EBI NSTCS X tCSLAV EBI A 15 0 19 loELAV 4 4 0 NOE tOELOEH lcsLOEL lt lt tBLSLAV CSHBLSH EBI NCAS BLOUT 0 EBI NRAS BLOUT 1 tBLSLBLSH CSLBLSL lt IBLSHANV EBI D 15 0 4 ih DQ tsu DQ gt 002aae161 Fig 15 External memory read access to static memory LPC3141_3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 52 of 74 NXP Semiconductors LPC31 41 31 43 EBI NSTCS X 4 tcsLav EBI A
63. ata line A I2STX_BCKO 125 interface 0 transmit bit clock signal PCM FSC frame synchronization signal 125 WSO0 125 interface 0 transmit word select signal PCM DCLK data clock output 125 CLKO 125 interface 0 transmit clock signal PCM DB POM serial data line B UART CTS N UART modem control Clear to send signal SPI CS OUT1 SPI chip select out for slave 1 used in master mode UART RTS N UART modem control Request to Send signal SPI CS OUT2 SPI chip select out for slave 2 used in master mode 6 28 2 Multiplexing between LCD and MPMC The multiplexing between the LCD interface and MPMC allows for the following two modes of operation MPMOC mode SDRAM and bus based LCD SRAM LCD mode Dedicated LCD interface The external NAND flash is accessible in both modes The block diagram Figure 9 gives a high level overview of the modules in the chip that are involved in the pin interface multiplexing between the EBI NAND flash controller MPMC and RAM based LCD interface LPC3141 3143 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 34 of 74 NXP Semiconductors LPC3141 3143 NAND_NCS 0 3 NAND RYBN 0 3 EBI NCAS BLOUT 0 EBI NRAS BLOUT 1 EBI 0 NOE Fig 9 Diagram of LCD and MPMC multiplexing LPC31x
64. be re written causing the timer to restart Pulse Width Modulation PWM module This PWM can be used to generate a pulse width modulated or a pulse density modulated signal With an external low pass filter the module can be used to generate a low frequent analog signal A typical use of the output of the module is to control the backlight of an LCD display This module has the following features Supports Pulse Width Modulation PWM with software controlled duty cycle Supports Pulse Density Modulation PDM with software controlled pulse density System control registers The System Control Registers SysCReg module provides a register interface for some of the high level settings in the system such as multiplexers and mode settings This is an auxiliary module included in this overview for the sake of completeness 125 The 125 125 transmit modules have the following features Audio interface compatible with the 5 standard 125 receive block supports master mode and slave mode 125 transmit block supports master mode Supports LSB justified words of 16 18 20 and 24 bit Supports a configurable number of bit clock periods per word select period up to 128 bit clock periods All information provided in this document is subject to legal disclaimers NXP B V 2010 rights reserved Preliminary data sheet Rev 0 16 27 May 2010 36 of 74 NXP Semiconductors LPC31 41 31
65. document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 26 of 74 NXP Semiconductors LPC31 41 131 43 6 17 6 18 LPC3141 3143 After a reset a register will indicate whether a reset has occurred because of a watchdog generated reset Watchdog timer can also be used as a normal timer in addition to the watchdog functionality output FIQ INTERRUPT mO EVENT ROUTER CONTROLLER IRQ C WDT 002aae086 Fig 7 Block diagram of the Watchdog Timer Input Output Configuration module IOCONFIG The General Purpose Input Output GPIO pins can be controlled through the register interface provided by the IOCONFIG module Next to several dedicated GPIO pins most digital IO pins can also be used as GPIO if they are not required for their normal dedicated function This module has the following features Provides control for the digital pins that can double as GPIO next to their normal function The pinning list in Table 4 indicates which pins can double as GPIO Each controlled pin can be configured for 4 operational modes Normal operation i e controlled by a function block Driven LOW Driven HIGH High impedance input AGPIO pin can be observed read in any mode The register interface provides set and clear access methods for choosing the operational mode 10 bit Analog to Digital Con
66. e a base clock by a fractional number to a lower clock frequency Fractional dividers support clock stretching to obtain a near 50 duty cycle output clock Register interface to reset all modules under software control Basedon the input of the Watchdog timer see also Section 6 16 the CGU can generate a system wide reset in the case of a system stall clock resources subdomain clocks clock outputs EXTERNAL OSCILLATOR CRYSTAL FRACTIONAL DIVIDER m SM CLOCK DOMAIN 0 modules 1 I2S AUDIO CLOCK DOMAIN n I2SRX BCKO I2SRX 50 I28RX BCK1 I2SRX WS1 SWITCHBOX 002aae916 The LPC3141 3143 has 11 clock domains n 11 The number of fractional dividers m depends on the clock domain Fig 6 CGU block diagram 6 16 Watchdog Timer WDT The watchdog timer can be used to generate a system reset if there is a CPU software crash In addition the watchdog timer can be used as an ordinary timer Figure 7 shows how the watchdog timer module is connected in the system This module has the following features n the event of a software or hardware failure generates a chip wide reset request when its programmed time out period has expired output m1 Watchdog counter can be reset by a periodical software trigger LPC3141 3143 All information provided in this
67. f words each Serial clock rate master mode maximum 45 MHz Serial clock rate slave mode maximum 25 MHz Support for single data access DMA Full duplex operation Supports up to three slaves Supports maskable interrupts Supports DMA transfers 6 24 Universal Asynchronous Receiver Transmitter UART The UART module supports the industry standard serial interface This module has the following features Programmable baud rate with a maximum of 1049 kBd Programmable data length 5 bit to 8 bit Implements only asynchronous UART Transmit break character length indication Programmable 1 to 2 stops bits in transmission Odd Even Force parity check generation Frame error overrun error and break detection Automatic hardware flow control Independent control of transmit receive line status data set interrupts and FIFOs SIR IrDA encoder decoder from 2400 to 115 Supports maskable interrupts Supports DMA transfers 6 25 Pulse Code Modulation PCM interface The interface supports the PCM and interfaces This module has the following features LPC3141 3143 Four wire serial interface Can function in both Master and Slave modes Supports PCM Pulse code modulation Single clocking physical format All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 30 of 74 NXP
68. ha data output hold time 4 10 ns tsu D data input set up 6 lt tbd gt ns time thio data input hold time bd ns toz data output 5 lt ns high impedance time 1 Parameters are valid over operating temperature range unless otherwise specified 2 All values valid for pads set to high slew rate IOA VDDE 1 8 0 15 V VDDI 1 2 0 1 V 3 Refer to the LPC3141 3143 user manual for the programming of MPMCDynamicReadConfig and SYSCREG_MPMP_DELAYMODES registers 4 foper 1 5 thio times are dependent MPMCDynamicReadConfig register value and SYSCREG MPMP DELAYMODES register bits 11 6 6 times are dependent SYSCREG_MPMP_DELAYMODES register bits 5 0 LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 54 of 74 LPC3141 3143 NXP Semiconductors CLKOUT EBI NRAS BLOUT EBI NCAS BLOUT EBI NWE EBI CKE EBI NDYCS EBI NR SS LAN tha EBI A 15 2 BANK UR COLUMN uai bord EBI D 15 0 DATA 2 CAS LATENCY 2 DATA n 1 DATA n 3 002aae121 EBI CKE is HIGH Fig 17 SDRAM burst read timing NXP B V 2010 All rights reserved 55 of 74 All information provided in this
69. he ISRAM Internal Static RAM Memory controller module is used as controller between the AHB bus and the internal RAM memory The internal RAM memory can be used as working memory for the ARM processor and as temporary storage to execute the code that is loaded by boot ROM from external devices such as SPI flash NAND flash and SD MNC cards This module has the following features Capacity of 192 kB All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 18 of 74 NXP Semiconductors LPC31 41 31 43 Implemented as two independent 96 memory banks 6 9 Memory Card Interface MCI The MCI controller interface can be used to access memory cards according to the Secure Digital SD and Multi Media Card MMC standards The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well Finally the MCI supports CE ATA 1 1 compliant hard disk drives This module has the following features One 8 bit wide interface Supports high speed SD versions 1 01 1 10 and 2 0 Supports SDIO version 1 10 Supports MMCplus MMCmobile and MMCmicro cards based on MMC 4 1 Supports SDHC memory cards CRC generation and checking Supports 1 4 bit SD cards Card detection and write protection FIFO buffers of 16 byte deep Host pull up control SDIO suspend and res
70. igh performance Bus Advanced Microcontroller Bus Architecture ARM Peripheral Bus Advanced Transport Architecture Bus Interface Unit Cipher Block Chaining Consumer Electronics Clock Generation Unit Cyclic Redundancy Check Device Firmware Upgrade Direct Memory Access Digital Rights Management Digital Signal Processing External Bus Interface Error Correction Code End Of Packet Electrostatic Discharge First In First Out Field Programmable Gate Array Galois Field Input Output Configuration ISDN Oriented Modular Infrared Data Association Internal Static RAM Internal Static ROM Joint Test Action Group Least Significant Bit Memory Card Interface Microcontroller Unit Multi Media Card Multi Port Memory Controller On The Go Pulse Code Modulation Physical Layer Phase Locked Loop Pulse Width Modulation All information provided this document is subject to legal disclaimers NXP B V 2010 rights reserved Preliminary data sheet Rev 0 16 27 May 2010 69 of 74 NXP Semiconductors LPC3141 3143 LPC3141_3143 Table 30 Abbreviations continued Acronym RNG ROM SD SDHC SDIO SDR SDRAM SEO SIR SPI 551 SysCReg TAP TDO UART USB UTMI WDT Description Random Number Generator Read Only Memory Secure Digital Secure Digital High Capacity Secure Digital Input Output Single Data Rate Synchronous Dynamic Random Access Memory Single Ended 0 Serial IrDA Serial Peri
71. input output line 1 GPIO9 General Purpose pin 9 MCI DAT 2 MCI card data input output line 2 GPIO10 General Purpose pin 10 MCI DAT 3 MCI card data input output line 3 NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 33 of 74 NXP Semiconductors LPC3141 3143 Table 10 Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal NAND related pin multiplexing mNAND RYBNO NAND RYBNO MCI DAT 4 mNAND RYBN1 RYBN1 MCI DAT 5 mNAND RYBN2 NAND RYBN2 MCI DAT 6 mNAND RYBN3 NAND RYBN3 MCI DAT 7 Audio related pin multiplexing 25 DATAO 125 DATAO PCM DA ml2STX_BCKO 125 FSC ml2STX WSO0 125 WSO0 DCLK ml2STX CLKO 125 CLKO DB UART related pin multiplexing mUART CTS UART CTS SPI CS OUTI1 mUART RTS N UART RTS N SPI CS OUT2 Description NAND RYBNO NAND flash controller Read Not busy signal 0 MCI DAT 4 MCI card data input output line 4 NAND flash controller Read Not busy signal 1 MCI DAT 5 MCI card data input output line 5 NAND RYBN 2 NAND flash controller Read Not busy signal 2 MCI DAT 6 MCI card data input output line 6 NAND NAND flash controller Read Not busy signal MCI DAT 7 MCI card data input output line 7 I2STX DATAO 125 interface 0 transmit data signal PCM DA serial d
72. isit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 73 of 74 NXP Semiconductors LPC3141 3143 17 Contents 2 1 3 1 5 1 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 6 10 6 11 6 12 6 13 6 14 6 15 6 16 6 17 6 18 6 19 6 20 6 21 6 22 6 23 6 24 6 25 6 26 6 27 6 28 6 28 1 6 28 2 6 28 3 6 29 6 30 6 31 General 1 Features and benefits 1 Key 5 1 Ordering 2 Ordering 2 Block diagram 3 Pinning 4 occ 4 Functional description 13 26 6 13 Memory 14 Ny c 14 flash 15 Multi Port Memory Controller MPMC 16 External Bus Interface 17 Internal Static ROM ISROM 17 Internal RAM memory 18 Memory Card Interface 19 High speed Universal Serial Bus 2 0 On The Go
73. it Common to read and write cycles tcsLav CS LOW to address valid 18 0 4 ns time Read cycle parameters OE LOW to address valid m 0 WAITOEN x HCLK ns time SLAV BLS LOW to address valid n 0 WAITOEN x HCLK ns time tcsLoeL CS LOW to OE LOW time 0 WAITOEN x HCLK ns CS LOW to BLS LOW time p 0 WAITOEN x HCLK ns OE LOW to OE HIGH time WAITRD WAITOEN 1 HCLK ns tBLsLBLSH BLS LOW to BLS HIGH time WAITRD WAITOEN 1 x HCLK ns tsu D data input set up time 9 ns th D data input hold time 0 ns CS HIGH to OE HIGH time 3 0 ns tcsHBLsH CS HIGH to BLS HIGH time 0 ns HIGH to address invalid 10 ns time tgisHanv BLS HIGH to address invalid 1x HCLK ns time Write cycle parameters testov CS LOW to data valid time 9 ns tcs weL CS LOW to WE LOW time a WAITWEN 1 x ns tcsiBLsL CS LOW to BLS LOW time WAITWEN x HCLK ns WE LOW to data valid time 0 WAITWEN 1 x HCLK ns twetweH WE LOW to WE HIGH time 415 16 WAITWR WAITWEN 1 ns BLS LOW to BLS HIGH time 405 WAITWR WAITWEN 3 x ns tweHanv WE HIGH to address invalid 1x HCLK ns time tweHpnv HIGH to data invalid time 1x HCLK ns BLS HIGH to address invalid 1x HCLK ns time BLS HIGH to d
74. lt tbd gt lt tbd gt lt tbd gt lt tbd gt tbd All information provided in this document is subject to legal disclaimers Typ 3 3 3 3 5 0 3 3 3 3 65 50 50 75 50 50 Max Unit 3 6 V 3 6 V 1 3 V V 3 6 V 3 6 V 1 3 V VDDE V V O 3VDDE V x A B C V 600 mV 850 mV V lt tbd gt lt tbd gt 100 mA lt tbd gt uA lt tbd gt uA lt tbd gt uA lt tbd gt uA lt tbd gt uA lt tbd gt uA NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 39 of 74 NXP Semiconductors LPC3141 3143 Table 12 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Ci input capacitance excluding bonding pad capacitance Output pins and pins configured as output Vo output voltage HIGH level output SUP4 SUP8 voltage lou 6 mA 1 8 V mode 3 3 V mode SUP3 6 mA SUP3 30 mA VoL LOW level output SUPS outputs voltage lo 4 mA 1 8 V mode 3 3 V mode SUP3 loi 4 mA HIGH level output Vpp VDDE IOx current x A B Vpp 0 4 V Vpp VDDE 1 A B C Vou Vpp 0 4 V lot LOW level output Vpp current x A B C Vor 0 4 V Vpp VDDE 1 x A B VoL 0 4 V loz OFF state output Vo 0 V Vo Vpp current no pull up down lous HIGH level Vpp V
75. mers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 28 of 74 NXP Semiconductors LPC31 41 31 43 6 20 6 21 6 22 6 23 Random number generator The Random Number Generator RNG generates true random numbers for use in advanced security and Digital Rights Management DRM related schemes These schemes rely upon truly random i e completely unpredictable numbers This module has the following features True random number generator The random number register does not rely on any kind of reset The generators are free running in order to ensure randomness and security AES decryption LPC3143 only This module can be used for data decryption using the AES algorithm The AES module has the following features AES 128 128 bit key 128 bit data CBC mode over blocks of 512 bytes Each block of 512 bytes uses the same initial value AES can be turned on and off Secure One Time Programmable memory OTP The Secure One Time Programmable Memory can be used for storing non volatile information like serial number security bits etc It consists of a polyfuse array embedded data registers and control registers One of the main features of the OTP is storing a security key and a unique ID This module has the following features 512 bit one time programmable memory 128 bits are used for an unique ID which is pre programmed in the wafer fab 4
76. ne 6 11 DMA controller LPC3141 3143 The DMA controller can perform DMA transfers on the AHB without using the CPU This module has the following features Tabl Supported transfer types Memory to memory copy Memory can be copied from the source address to the destination address with a specified length while incrementing the address for both the source and destination Memory to peripheral Datais transferred from incrementing memory to a fixed address of a peripheral The flow is controlled by the peripheral Peripheral to memory Data is transferred from a fixed address of a peripheral to incrementing memory The flow is controlled by the peripheral Supports single data transfers for all transfer types Supports burst transfers for memory to memory transfers A burst always consists of multiples of 4 32 bit words The DMA controller has 12 channels Scatter gather is used to gather data located at different areas of memory Two channels are needed per scatter gather action Supports byte half word and word transfers and correctly aligns them over the AHB bus Compatible with ARM flow control for single requests last single requests terminal count info and DMA clearing Supports swapping endian property of the transported data e9 Peripherals that support DMA Peripheral name Supported transfer types flash controller AES decryption enginel l Memory to memory SPI Memory
77. ns 0 V on pin ADC10B_GNDA 3 3 V 3 The ADC is monotonic there no missing codes 4 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 10 5 The integral non linearity E is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 10 6 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 10 7 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 10 8 The absolute error is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 10 9 SeeFigure 11 LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 42 of 74 NXP Semiconductors LPC31 41 31 43 offset gain error error Eo 1023 1022 1021 1020 1019 1018 7 code out 6 5 4 3 2 1 0 1018 1019 102
78. o 85 unless otherwise specified 1 8 V and 3 3 V SUP8 Symbol tsu A tha tf tsu D thio ldis Q lw en Parameter Conditions address set up time address hold time access cycle time rise time fall time data input set up time data input hold time data output valid delay time data output disable time enable pulse width read cycle write cycle Min pue 2 2 ibd lt tbd gt Typ Max Unit 1xLCDCLK ns 2xLCDCLK ns 5xLCDCLK ns 5 ns 5 ns ns ns 1xLCDCLK ns 2xLCDCLK ns 2xLCDCLK ns 2xLCDCLK ns 1 Timing is derived from the LCD Interface Control Register fields INVERT E RD 0 See the LPC314x user manual INVERT CS 1 1 PS 0 mLCD CSB mLCD E RD mLCD RS mLCD RW WR mLCD DB 15 0 16 bit mode mLCD DB 15 8 8 bit mode mLCD DB 15 12 4 bit mode mLCD_DB 15 0 16 bit mode mLCD_DB 15 8 8 bit mode mLCD_DB 15 12 4 bit mode Fig 13 LCD timing Motorola 6800 mode read access write access 002aae208 LPC3141_3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 49 of 74 NXP Semiconductors LPC31 41 31 43 9 1 3 Serial mode Table 17 Dynamic characteristics LCD controller serial mode 25 pF Tamb 40 C to
79. onditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or LPC3141 3143 All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors
80. ose IO 0 mode pin 0 GPIO1U1 J10 SUPS3 0101 General Purpose IO pin 1 mode pin 1 GPIO2l1 114 SUP3 GPIO DIO1 General Purpose IO pin 2 mode pin 2 GPIOS B11 5 GPIO DIO1 General Purpose 10 3 GPIO4 C11 SUP3 0101 General Purpose input 4 mGPIO5H B6 SUPS GPIO 0104 General Purpose pin 5 mGPIO6 41 A6 SUP3 GPIO 0104 General Purpose pin 6 mGPIO7 4 A5 SUP3 GPIO 0104 General Purpose IO pin 7 8 1 5 SUPS GPIO 0104 General Purpose IO 8 mGPIO9H C5 SUPS GPIO 0104 General Purpose IO 9 mGPIO 1 081 A4 SUPS GPIO 0104 General Purpose pin 10 GPIO11 H13 SUPS3 GPIO DIO1 General Purpose IO pin 11 GPIO12 H10 SUPS3 GPIO DIO1 General Purpose IO pin 12 GPIO13 J12 SUP3 GPIO DIO1 General Purpose IO pin 13 GPIO14 J14 SUP3 GPIO DIO1 General Purpose IO pin 14 GPIO15 J13 SUP3 DIO1 General Purpose IO pin 15 GPIO16 J11 SUPS GPIO DIO1 General Purpose IO pin 16 GPIO17 K12 SUP3 DIO1 General Purpose IO pin 17 GPIO18 K14 SUP3 GPIO DIO1 General Purpose IO pin 18 GPIO19 H11 SUP3 GPIO DIO1 General Purpose IO pin 19 20 K13 SUP3 GPIO DIO1 General Purpose IO pin 20 External Bus Interface EBI NAND flash controller EBI A 0 ALEHI B3 SUP4 DO 0104 EBI address latch enable A 1 A2 SUP4 DO 0104 EBI command latch enable D 0 4 G2 SUP4 DIO 0104 data I O 0 D 19 F2 SUP
81. pecification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 15 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet
82. pheral Interface Serial Synchronous Interface System Control Registers Test Access Port Test Data Out Universal Asynchronous Receiver Transmitter Universal Serial Bus USB 2 0 Transceiver Macrocell Interface WatchDog Timer All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 70 of 74 NXP Semiconductors LPC31 41 31 43 14 Revision history Table 31 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC3141 3143 v 0 16 lt tbd gt Preliminary data sheet LPC3141 3143 0 15 Modifications Reset state of JTAG pins and GPIOO GPIO1 and GPIO2 pins updated in Table 4 Document template updated Digital I O level for pin CLOCK OUT corrected in Table 4 Power consumption data updated in Table 14 LPC3141 3143 0 15 lt tbd gt Preliminary data sheet LPC3141_3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 71 of 74 NXP Semiconductors LPC3141 3143 15 Legal information 15 1 Data sheet status Document status I 2 Product statusi3 Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective s
83. s turnaround delay All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 16 of 74 NXP Semiconductors LPC31 41 31 43 output enable and write enable delays extended wait One chip select for synchronous memory and two chip selects for static memory devices Power saving modes Dynamic memory self refresh mode supported Controller support for 2 k 4 k and 8 k row address synchronous memory parts Support for all AHB burst types Little and big endian support Support for the External Bus Interface EBI that enables the memory controller pads to be shared 6 6 External Bus Interface EBI The EBI module acts as multiplexer with arbitration between the NAND flash and the SDRAM SRAM memory modules connected externally through the MPMC 6 7 LPC3141 3143 The main purpose for using the EBI module is to save external pins However only data and address pins are multiplexed Control signals towards and from the external memory devices are not multiplexed Table 7 Memory map of the external SRAM SDRAM memory modules Module Maximum address space Data width Device size External SRAMO 0 2000 0000 0x2000 FFFF 8 bit 64 kB 0x2000 0000 0x2001 FFFF 16 bit 128 kB External SRAM1 0x2002 0000 0x2002 FFFF 8 bit 64 kB 0x2002 0000 0x2003 FFFF 16 bit 128 kB External SDRAMO 0x3000 0000 Ox37FF FFFF 16 bit 128 M
84. shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 15 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and c
85. stant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 72 of 74 NXP Semiconductors LPC3141 3143 Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document and
86. tate of GPIOO GPIO1 and GPIO2 pins To ensure that GPIOO GPIO1 and GPIO2 pins come up as inputs pins _ and JTAGSEL must LOW during power on reset see UM10362 JTAG chapter for details Table 8 shows the various boot modes supported on the LPC3141 3143 Table8 LPC3141 3143 boot modes Boot mode GPIOO GPIO1 GPIO2 Description NAND 0 0 0 Boots from NAND flash If proper image is not found boot ROM will switch to DFU boot mode SPI 0 0 1 Boot from SPI NOR flash connected to SPI CS OUTO If proper image is not found boot ROM will switch to DFU boot mode DFU 0 1 0 Device boots via USB using DFU class specification SD MMC 0 1 1 Boot ROM searches all the partitions on the SD MMC SDHC MMC eMMC eSD card for boot image If partition table is missing it will start searching from sector 0 A valid image is said to be found if a valid image header is found followed by a valid image If a proper image is not found boot ROM will switch to DFU boot mode ReservedO 1 0 0 Reserved for testing NOR flash 1 0 1 Boot from parallel NOR flash connected to EBI 5 5 1 UART 1 1 0 Boot ROM tries to download boot image from UART 115200 8 n 1 assuming 12 MHz FFAST clock Test 1 1 1 Boot ROM is testing ISRAM using memory pattern test Switches to UART boot mode on receiving three ASCI dots on UART 1 For security reasons this mode is disabled when JTAG security feature is used Internal RAM memory T
87. transmitter Slave receiver 6 28 LCD NAND flash SDRAM multiplexing The LPC3141 3143 contains a rich set of specialized hardware interfaces but the TFBGA package does not contain enough pins to allow the use of all signals of all interfaces simultaneously Therefore a pin multiplexing scheme is created which allows the selection of the right interface for the application Pin multiplexing is enabled between the following interfaces between the dedicated LCD interface and the external bus interface between the NAND flash controller and the memory card interface between UART and SPI e between 125 0 output and the PCM interface The pin interface multiplexing is subdivided into five categories storage video audio NAND flash and UART related pin multiplexing Each category supports several modes which can be selected by programming the corresponding registers in the SysCReg 6 28 1 Pin connections Table 10 Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal Description Video related pin multiplexing mLCD CSB LCD CSB EBI NSTCS 0 LCD CSB LCD chip select for external LCD controller EBI NSTCS 0 static memory chip select 0 mLCD DB 1 LCD DB 1 EBI NSTCS 1 LCD DB 1 LCD bidirectional data line 1 EBI NSTCS 1 EBI static memory chip select 1 mLCD DB 0 LCD DB 0 EBI CLKOUT LCD DB 0 LCD bidirectional data line 0 EBI CLKOUT EBI SDRAM clock signal mLCD E RD LCD E RD EB
88. u DAT tSU STA 002aad985 Remark Signals SDA and SCL correspond to pins 2 SDAx and I2C_SCLx 0 1 Fig 27 1 C bus pins clock timing LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 64 of 74 NXP Semiconductors LPC3141 3143 Table 26 9 9 USB interface Dynamic characteristics USB pins high speed C 50 pF Hy 1 5 on D to Vppao SUPS unless otherwise specified Symbol t tr FRFM Vcns lrEoPT tEoPR2 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SEO interval of EOP source jitter for differential transition to SEO transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver EOP width at receiver Conditions 10 to 90 96 10 to 90 96 t t see Figure 28 see Figure 28 10 to 90 must reject as EOP see Figure 28 must accept as Figure 28 tbd tbd lt tbd gt lt tbd gt lt tbd gt lt tbd gt tbd lt tbd gt lt tbd gt Typ Max lt tbd gt tbd tbd lt tbd gt lt tbd gt lt tbd gt tbd lt tbd gt Unit ns ns ns ns ns ns ns ns 1 Characterized but not implemented
89. ume 1 to 65 535 byte blocks Suspend and resume operations SDIO read wait Individual clock and power ON OFF features to each card Maximum clock speed of 52 MHz MMC 4 1 Supports CE ATA 1 1 Supports 1 bit 4 bit and 8 bit MMC cards and CE ATA devices 6 10 High speed Universal Serial Bus 2 0 On The Go OTG The USB OTG module allows the LPC3141 3143 to connect directly to a USB host such as a PC in device mode or to a USB device in host mode In addition the LPC3141 3143 has a special built in mode in which it enumerates as a Device Firmware Upgrade DFU class and which allows for a factory download of the device firmware through USB LPC3141 3143 This module has the following features Complies with Universal Serial Bus specification 2 0 Complies with USB On The Go supplement Complies with Enhanced Host Controller Interface Specification Supports auto USB 2 0 mode discovery Supports all high speed USB compliant peripherals Supports all full speed USB compliant peripherals All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 19 of 74 NXP Semiconductors LPC31 41 31 43 Supports software Host Negotiation Protocol HNP and Session Request Protocol SRP for OTG peripherals Contains UTMI compliant transceiver PHY Supports interrupts This module has its own integrated DMA engi
90. uter see also Section 6 19 For example all clocks including the core bus clocks are off and activated automatically when a button is pressed Supports five clock sources Reference clock generated by the oscillator with an external crystal Pins 25 BCKO I28RX WSO I2SRX BCK1 and I28RX WS1 are used to input external clock signals used for generating audio frequencies in I2SRX slave mode see also Section 6 4 Supports two PLLs System PLL generates programmable system clock frequency from its reference input 125 PLL generates programmable audio clock frequency typically 256 x fs from its reference input Remark Both the System PLL and the I2S Audio PLL generate their frequencies based on their individual reference clocks The reference clocks can be programmed to the oscillator clock or one of the external clock signals Highly flexible switchbox to distribute the signals from the clock sources to the module clocks Each clock generated by the CGU is derived from one of the base clocks and optionally divided by a fractional divider All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 25 of 74 NXP Semiconductors LPC31 41 31 43 Each base clock can be programmed to have any one of the clock sources as an input clock Fractional dividers can be used to divid
91. verter ADC10B This module is a 10 bit successive approximation ADC with an input multiplexer to allow for multiple analog signals on its input A common use of this module is to read out multiple keys on one input from a resistor network This module has the following features Four analog input channels selected by an analog multiplexer Programmable ADC resolution from 2 bit to 10 bit The maximum conversion rate is 400 kSamples s for 10 bit resolution and 1500 kSamples s for 2 bit resolution Single and continuous analog to digital conversion scan modes Power down mode All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 27 of 74 NXP Semiconductors LPC31 41 131 43 6 19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts Combined with the wake up functionality of the CGU it also offers a way to wake up the system from suspend mode with all clocks deactivated interrupt 0 interrupt 1 INTERRUPT interrupt 2 CONTROLLER EVENT ROUTER interrupt 3 cgu wakeup internal external pins input signals GPIO configurable 002aae087 Fig 8 Event router block diagram The event router has four interrupt outputs connected to the interrupt controller and one wake
92. x control ALE CLE ERU EBI A 0 ALE INTERFACE A 1 0 gt EBI D 15 0 address EBI A 15 2 14 lt y LCD_DB 15 2 LCD mode control EBI A 15 2 MPMC mode gt data SYSCREG MUX LCD EBI SEL register Paces 5 2 VO LCD MPMC mode mode LCD CSB EBI NSTCS 0 LCD DB 1 NSTCS 1 LCD DB O EBI CLKOUT LCD E RD EBI CKE LCD RS EBI NDYCS LCD RW WR EBI DOM 1 data LCD DB 1 0 control 002aae157 6 28 3 LPC3141 3143 Figure 9 only shows the signals that are involved in pad muxing so not all interface signals are visible The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world Both NAND flash and SDRAM SRAM initiate a request to the EBI unit This request is granted using round robin arbitration see Section 6 6 Supply domains As is shown in Figure 9 the EBI NAND flash MPMC control data is connected to a different supply domain than the LCD interface The EBI control and address signals are muxed with the LCD interface signals and are part of supply domain SUP8 The SDRAM SRAM data lines are shared with the NAND flash through the EBI and are part of supply domain SUPA Therefore the following rules apply for connecting memories 1 SDRAM and bus based LCD or SRAM This is the MPMC mode The supply voltage for SDRAM SRAM bus based LCD and N
93. y associated with each request input Visibility of interrupts request state before masking Support for nesting of interrupt service routines Interrupts routed to IRQ and to FIQ are vectored Level interrupt support The following blocks can generate interrupts NAND flash controller USB 2 0 HS OTG Event router 10 bit ADC UART LCD interface MCI SPI 2 0 and I C1 bus controllers Timer 0 timer 1 timer 2 and timer 3 125 transmit I2STX 0 and I2STX 1 125 receive I2SRX 0 and I2SRX 1 DMA 6 13 Multi layer AHB The multi layer AHB is an interconnection scheme based on the AHB protocol that enables parallel access paths between multiple masters and slaves in a system LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 21 of 74 NXP Semiconductors LPC31 41 31 43 Multiple masters can have access to different slaves at the same time Figure 5 gives an overview of the multi layer AHB configuration in the LPC3141 3143 AHB masters and slaves are numbered according to their AHB port number LPC3141 3143 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Preliminary data sheet Rev 0 16 27 May 2010 22 of 74 NXP Semiconductors LPC3141 3143 master 5 ARM Q AHB 5 926

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