PCI-1710/1710HG Multifunction DAS Card for PCI Bus User`s manual
Contents
1. E pros 43 4 13 Digital VO Registers in 44 4 14 Programmable Timer Counter Registers 44 Chapter 5 Calibration 45 Sl AA 46 5 2 VR ASSIM strain 46 5 3 A D Calibration licia gol 47 5 4 DIA Calibration iii 48 5 5 A eee ee eee eee 49 Appendix A 82C54 Counter Chip Functions 51 AN The ml 1 e ele ea 52 A 2 Counter Read Write and Control Registers 53 A 3 Counter Operating Modes sss 56 A 4 Counter Operations iii 58 CHAPTER General Information 1 1 Introduction 2 The PCI 1710 1710HG is a multifunction DAS card for the PCI bus Advanced circuit design brings you higher quality and more func tions including the five most desired measurement and control functions 12 bit A D conversion D A conversion digital input digital output and counter timer PCI bus Plug and Play The PCI 1710 1710HG uses a PCI controller to interface the card with the PCI bus The controller fully implements the PCI bus specifica tion Rev 2 1 All bus relative configurations such as base address and interrupt assignment are automatically controlled by software No jumper or DIP switch setting is required for user configuration Flexible Inputs Types and Ranges Setting The PCI 1710 1710HG features an automatic channel gain scanning circuit The circuit rather than your software controls multiplexer switchin2. PCI 1710 1710HG Multifunction DAS Card for PCI Bus User s manual Copyright This documentation and the software included with this product are copyrighted 1998 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use nor for any infringements of the rights of third parties which may result from its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation MS DOS and Windows are trademarks of Microsoft Corporation Intel and Pentium are trademarks of Intel Corporation CE notification The PCI 1710 1710HG developed by ADVANTECH CO LTD has passed the CE test for environmental specifications when shielded cables are used for external wiring We recommend the use of shielded cables This kind of cable is available from Advantech Please contact your local supplier for ordering information On line Technical Support For technical support and service please visit our support website at http support advantech com Part
3. FIFO COUNTER 1 12 bit A D Edic dd PACER_OUT Convertor A D Trigger Logic EXT_TRG lt Avo lt ai Multiplexer 16 S E o h l Logi DI Channel Scan Logic 8 DIFF gt e e Gain Control RAM fk MIR Figure 1 1 PCI 1710 PCI 1710HG block diagram 8 PCI 1710 1710HG User s Manual CHAPTER Installation 2 1 Initial Inspection 2 2 Before installing the PCI 1710 1710HG check the card for visible damage We have carefully inspected the card both mechanically and electrically before shipment It should be free of marks and in perfect order upon receipt As you unpack the PCI 1710 1710HG check it for signs of shipping damage damaged box scratches dents etc If it is damaged or fails to meet specifications notify our service department or your local sales representative immediately Also call the carrier immediately and retain the shipping carton and packing materials for inspection by the carrier We will then make arrangements to repair or replace the unit Unpacking 10 The PCI 1710 1710HG contains components that are sensitive and vulnerable to static electricity Discharge any static electricity on your body to ground by touching the back of the system unit grounded metal before you touch the board Remove the PCI 1710 1710HG card from its protective packaging by grasping the card s rear panel Handle the card only by its edges to avoid static discharge
4. No 2003171010 2nd Edition Printed in Taiwan Feburary 1999 Contents Chapter 1 General Information 1 1 1 AMP OCUIC HON ex lt i n n cotta lieti bad Wa ask iad 2 1 2 IRR RA 3 1 3 Specifications nin 55 lt ci5 yaya Kayo yade yar da ela ear 4 1 4 Block Diagram erkeke kek k 8 Chapter 2 Installation 9 2 1 InitialInspection EE keke 10 O eroi 10 2 3 Installation Instructions ee 11 Chapter 3 Signal Connections 13 CA A e e ser ber a Sindee 15 ili TO COMME ili RE 15 3 3 Analog Input Connections eee ee eee 19 3 4 Analog Output Connections eee ee eee 23 3 5 Trigger Source Connections i 23 3 6 FieldWiringConsiderations e 29 Chapter 4 Register Structure and Format 27 l OVE cairoli letra ae 28 4 2 UO Port Address MaD eee ke 28 4 3 Channel Number and A D Da a 33 4 4 Software A D Trigger i 33 4 5 A D Channel Range Setting eee EE 34 4 6 MUX Control e de e 37 4 Control Register ii dd 39 45 Stat s Register lana 40 4 9 Clear Interrupt and FIFO eken 41 4 10 D A Channel 0 Dildo 42 4 11 D A Channel 1 Output n 42 4 12 D A Reference Control
5. Please make sure that you have carefully routed signal cables to the card You must separate the cabling from noise sources Try to keep video monitors far away from the analog signal cables because these are a common noise source in a PCI data acquisition system If you want to reduce common mode noise try to use differential analog input connections If you do not want your signals to be affected when travelling through areas with high electromagnetic interference or large magnetic fields try the following routing techniques Use individually shielded twisted pair wires to connect analog input signals to the board i e the signals connected to the High and Low inputs are twisted together and covered with a shield Finally connect the shield only to one point at the signal source ground Make sure that your signal lines do not travel through conduits because these may contain power lines Also keep your signals far from electric motors breakers or welding equipment as these can create magnetic fields Keep a reasonable distance between high voltage or high current lines and signal cables connected to the PCI 1710 1710HG card if the cables run parallel or route signal cables at right angles to high voltage current cables In addition to outside noise the transmitted signals themselves can affect the card s performance We suggest connecting signal sources to the card using the PCL 10168 shielded cable in order to avoid this kin
6. analog input channels in differential mode however In differential mode signals are transmitted by a pair of channels Al lt i 1 1 gt i 0 2 4 14 In each pair of differential channels the even channel is the positive end and the odd one is the negative end For example if channel 0 is set as differential then channel 0 and channel are combined into one channel and refer to the gain code and B U of channel 0 the channel 1 values are unavailable By the same rule if channel 2 is set as differential then channel 2 and channel 3 are combined into one channel and refer to the gain code and B U of channel 2 the channel 3 values are unavailable The following examples show the scan sequences in differential mode Example 3 Suppose that the start scan input channel is AI14 and the stop scan input channel is AI3 If AI14 is differential AIO and All are single ended and Al2 is differential then the scan sequence is AI14 AIO Al AR AI14 AIO ATI AD AI14 Example 4 Suppose that the start scan channel is AI11 and the stop scan channel is AI15 If AI11 is single ended AI12 is PCI 1710 1710HG User s Manual differential and AI14 is differential then the scan sequence is AI11 A112 AI14 AI11 AI12 AI14 AII Warning Only even channels can be set as differential An odd channel will become unavailable if its preceding channel is set as differential 4 7 Control Register BASE 6 The write only regis
7. low MODE 5 Hardware Triggered Strobe The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached The counter is retriggerable Appendix A 8524 Counter Chip Functions 57 A 4 Counter Operations 58 Read Write Operation Before you write the initial count to each counter you must first specify the read write operation type operating mode and counter type in the control byte and write the control byte to the control register BASE 30 Dec Since the control byte register and all three counter read write registers have separate addresses and each control byte specifies the counter it applies to by SC1 and SCO no instructions on the operat ing sequence are required Any programming sequence following the 82C54 convention is acceptable There are three types of counter operation Read load LSB read load MSB and read load LSB followed by MSB It is important that you make your read write operations in pairs and keep track of the byte order Counter Read back Command The 82C54 counter read back command lets you check the count value programmed mode and current states of the OUT pin and Null Count flag of the selected counter s You write this command to the control word register Format is as shown at the beginning of this section The read back command can latch multiple counter output latches Simply set the CNT bit to 0 and
8. which could damage its integrated circuits Keep the antistatic package Whenever you remove the card from the PC protect the card by storing it in this package You should also avoid contact with materials that hold static electricity such as plastic vinyl and styrofoam Check the product contents inside the packing There should be one card one CD ROM and this manual Make sure nothing is missing PCI 1751 1710HG_ User s Manual 2 3 Installation Instructions The PCI 1710 1710HG can be installed in any PCI slot in the computer However refer to the computer user s manual to avoid any mistakes and danger before you follow the installation procedure below 1 Turn off your computer and any accessories connected to the computer Warning TURN OFF your computer power supply whenever you install or remove any card or connect and disconnect cables 2 Disconnect the power cord and any other cables from the back of the computer 3 Remove the cover of the computer 4 Select an empty 5 V PCI slot Remove the screw that secures the expansion slot cover to the system unit Save the screw to secure the interface card retaining bracket 5 Carefully grasp the upper edge of the PCI 1710 1710HG Align the hole in the retaining bracket with the hole on the expansion slot and align the gold striped edge connector with the expansion slot socket Press the card into the socket gently but firmly Make sure the card fits the slot tight
9. you load the count register You can also synchronize the output by software MODE 3 Square Wave Generator This mode is similar to Mode 2 except that the output will remain high until one half of the count has been completed for even num bers and will go low for the other half of the count This is accom plished by decreasing the counter by two on the falling edge of each clock pulse When the counter reaches the terminal count the state of the output is changed the counter is reloaded with the full count and the whole process is repeated If the count is odd and the output is high the first clock pulse after the count is loaded decrements the count by 1 Subsequent clock pulses decrement the count by 2 After time out the output goes low and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decre ment the count by two until time out then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts MODE 4 Software Triggered Strobe After the mode is set the output will be high When the count is loaded the counter will begin counting On terminal count the output will go low for one input clock period then go high again If you reload the count register during counting the new count will be loaded on the next CLK pulse The count will be inhibited while the GATE input is
10. 6 DA11 DAO Digital to Analog data DAO is the LSB and DA11 is the MSB of the D A data 42 PCI 1710 1710HG User s Manual 4 12 D A Reference Control BASE 14 The write only register of BASE 14 allows users to set the D A reference source Table 4 12 Registers for D A reference control D A Reference Control wie Fea BOZ BCI WI B EI HEZER MERI EKEN Pease EC ET E O DA0_5 10 The internal reference voltage for the D A output channel 0 This bit controls the internal reference voltage for the D A output channel 0 0 means that the internal reference voltage is 5 V and 1 means it is 10 V DAO_I E Internal or external reference voltage for the D A output channel 0 This bit indicates that the reference voltage for the D A output channel 0 is internal or external 0 means that the reference voltage comes from the internal source and 1 means it comes from an external source DA1_5 10 The internal reference voltage for the D A output channel 1 This bit controls the internal reference voltage for the D A output channel 1 0 means that the internal reference voltage is 5 V and 1 means it is 10 V DA1 NE Internal or external reference voltage for the D A output channel 1 This bit indicates that the reference voltage for the D A output channel 1 is internal or external 0 means that the reference voltage comes from the internal source and 1 means it comes from an external source Chapter 4 Register S
11. 6 e Input voltage Low 0 4 V max High 2 4 V min s Input load Low 0 2mA 0 4 V High 20 uA 2 7 V Digital Output e Channels 16 Output voltage Low 0 4 V max 8 0 mA sink High 2 4 V min 0 4 mA source PCI 1710 1710HG User s Manual Programmable Timer Counter Counter chip 82C54 or equivalent e Counters 3 channels 16 bits 2 channels are permanently configured as programmable pacers 1 channel is free for user application e Input gate TTL CMOS compatible Time base Channel 1 10 MHz Channel 2 Takes input from output of channel 1 Channel 0 Internal 1 MHz or external clock 10 MHz max selected by software General T O Connector 68 pin SCSI I female connector Power consumption 5 V 850 mA Typical 5 V O 1 0 A Max Dimensions 175 mm x 107 mm 6 9 x 4 2 Operating temperature 0 60 C 32 140 F refer to IEC 68 2 1 2 Storage temperature 20 70 C 4 158 F Operating humidity 5 95 RH non condensing refer to IEC 68 2 3 MTBF over 64 770 hrs 25 C grounded fixed environment Chapter 1 General Information 7 1 4 Block Diagram Address Decoder Digital Output 6 Digital Input D A Output 0 Address Bus PCI Controller A D amp D A Status Control Logic D A Output 1 CNTO CLK COUNTER CNTO_OUT E UNS 10 MHz 10 0 uu CNTO_GATE IRQ Control 1 MHz 4K Samples Logic
12. D three ground references AIGND AOGND and DGND are connected together on the PCI 1710 1710HG card Analog Output Channel 0 External DAO_ REF Input Reference This is the external reference input for the analog output channel 0 circuitry AOGND AOGND AOGND OGND 16 PCI 1710 1710HG User s Manual I O Connector Signal Descriptions part II DI lt 0 15 gt DGND Digital Input signals DO lt 0 15 gt DGND Output Digital Output signals Digital Ground This pin supplies the reference for the digital signals at the VO DGND connector as well as the 5VDc supply The three ground references AIGND AOGND and DGND are connected together on the PCH1710 1710HG card Counter 0 Clock Input This pin is the external clock input of counter 0 The clock CNTO_ CLK DGND Input input of counter 0 can be either external up to 10 MHz or internal 100 kHz as set by software Counter 0 Output This pin is the output of CNTO _OUT DGND Output counter 0 See Appendix A for more detailed information Counter 0 Gate Input This pin is the gate CNTO _GATE DGND Input control for counter 0 See Appendix A for more detailed information Chapter 3 Signal Connections 17 I O Connector Signal Descriptions part III Snai Reterence prooton eos Name Pacer Clock Output This pin pulses once for each pacer clock when turned on If A D conversion is in the pacer trigger mode users POND Output can use this signal as a sy
13. If you set it for BCD Binary Coded Decimal counting the count can be any number from 0 to 9999 If you set both SC1 and SCO bits to 1 the counter control register is in read back command mode The control register data format then 54 PCI 1750 User s Manual becomes BASE 30 Dec 82C54 control read back mode Bit D7 D6 D5 D4 D3 D2 D1 DO Value 1 1 CNT STA C2 C1 CU X CNT 0 Latch count of selected counter s STA 0 Latch status of selected counter s C2 CI amp C0 Select counter for a read back operation C2 1 select Counter 2 C1 1 select Counter 1 CO 1 select Counter 0 If you set both SCI and SCO to 1 and STA to 0 the register selected by C2 to CO contains a byte which shows the status of the counter The data format of the counter read write register then becomes BASE 24 26 28 Dec Status read back mode Bit D7 D6 D5 D4 D3 D2 D1 DO Value OUT NC RW1 RWO M2 M1 MO BCD OUT Current state of counter output NC Null count is 1 when the last count written to the counter register has been loaded into the counting element Appendix A 8524 Counter Chip Functions 55 A 3 Counter Operating Modes MODE 0 Stop on Terminal Count The output will initially be low after you set this mode of operation After you load the count into the selected count register the output will remain low and the counter will count When the counter reaches the terminal count its output will go high and remain high u
14. PCI 1710 1710HG software CD ROM ADCAL EXE assists you in A D calibration and DACAL EXE in D A calibration The ADCAL EXE and DACAL EXE make calibrations easy It leads you through the calibration and setup procedure with a variety of prompts and graphic displays showing you all of the correct settings and adjustments This appendix offers a brief guide to these calibration programs To perform a satisfactory calibration you need a 4 digit digital multimeter and a voltage calibrator or a stable noise free D C voltage source 5 2 VR Assignment There are five variable resistors VRs on the PCL 1710 1710HG card They help you to make accurate adjustments on all A D and D A channels Please refer to the following figure for VR position VR4 VR5 VRI VR2 VR3 UO YUL Figure 5 1 PCL 1710 1710HG VR assignment 46 PCI 1710 1710HG User s Manual The following list shows the function of each VR VR Function VRI A D unipolar offset VR2 A D bipolar offset VR3 A D full scale gain VR4 D A channel 0 full scale VR5 D A channel 1 full scale 5 3 A D Calibration Regular and accurate calibration procedures ensure the maximum possible accuracy The ADCAL EXE calibration program leads you through the whole A D offset and gain adjustment procedure The basic steps are outlined below 1 Set analog input channel AIO as single ended bipolar range 5 V and set All as single ended unipolar range 0
15. al Ald All Al2 Al3 Al4 Al5 Al6 Al7 AIS Al9 Al10 Al11 AI12 Al13 Al14 Al15 AIGND AIGND DAO_REF DA1_REF DAO_OUT DA1_OUT AOGND AOGND DIO Dit DI2 DI3 DI4 DI5 DIG DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 DGND DGND DOO DO DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DGND DGND CNTO_CLK PACER_OUT CNTO_OUT TRG_GATE CNTO_GATE EXT_TRG 12V 5V Figure 3 1 I O connector pin assignments for the PCI 1710 1710 HG card Chapter 3 Signal Connections 15 I O Connector Signal Descriptions Rima lere pwonon pesetpten Name Analog Input Channels 0 through 15 Each channel pair Aki i 1 gt i 0 2 4 14 can be Onl Oe AND Input configured as either two single ended inputs or one differential input Analog Input Ground These pins are the reference points for single ended measurements and the bias current return point AIGND for differential measurement The three ground references AIGND AOGND and DGND are connected together on the PCI 1710 1710HG card Analog Output Channel 1 External DA1_ REF Input Reference This is the external reference input for the analog output channel 1 circuitry Analog Output Channel 0 This pin supplies DA9 OUT Gupit the voltage output of analog output channel 0 Analog Output Channel 1 This pin supplies Gu AL Output the voltage output of analog output channel 1 Analog Output Ground The analog output voltages are referenced to these nodes The AOGN
16. d BASE 5 described in the next section and then write the range code to BASE 2 bit 0 to bit 2 and bit 4 Table 4 3 Register for A D channel range setting A D channel range setting nT TT Tira pease Tse su Tez er o S D Single ended or Differential 0 means the channel is single ended and 1 means it is differential B U Bipolar or Unipolar 0 means the channel is bipolar and 1 means it is unipolar G2 to GO Gain Code PCI 1710 1710HG User s Manual The following table lists the gain codes for the PCI 1710 Table 4 4 Gain codes for the PCI 1710 Chapter 4 Register Structure and Format 35 The following lists the gain codes for the PCI 1710HG Table 4 5 Gain codes for the PCI 1710HG PCI 1710HG Input Range V EE KIRE EI DoT o s01 xak xd k ai k R O 36 PCI 1710 1710HG User s Manual 4 6 MUX Control BASE 4 and BASE 5 Table 4 6 The register for multiplexer control BETIN EZEL EXE REN EZM jaa ses Tore om om cr eases Te az eu l a CL3 CLO Start Scan Channel Number CH3 CHO Stop Scan Channel Number BASE 4 bit 3 to bit 0 CL3 CLO act as a pointer when you program the A D channel setting see previous section When you set the MUX start channel to an analog input channel Aln n 0 1 2 15 the gain code B U and S D written to the register of BASE 2 is for channel n Caution We recommend you set the same start and stop chan
17. d of interference Chapter 3 Signal Connections 25 26 PCI 1710 1710HG User s Manual CHAPTER Register Structure and Format 4 1 Overview 4 2 The PCI 1710 1710HG is delivered with an easy to use 32 bit DLL driver for user programming under the Windows 95 NT operating system We advise users to program the PCI 1710 1710HG using the 32 bit DLL driver provided by Advantech to avoid the complexity of low level programming by register The most important consideration in programming the PCI 1710 1710HG card at a register level is to understand the function of the card s registers The information in the following sections is provided only for users who would like to do their own low level programming 1 0 Port Address Map 28 The PCI 1710 1710HG card requires 32 consecutive addresses in the PC s I O space The address of each register is specified as an offset from the card s base address For example BASE 0 is the card s base address and BASE 7 is the base address plus seven bytes Table 4 1 shows the function of each register or driver and its address relative to the card s base address PCI 1710 1710HG User s Manual Table 4 1 PCI 1710 1710HG register format Part 1 samal 7 6 s a e Channel Number and A D Data C Chane Number and AD Daa o ror roe os aos ao o gt ao a Status Register SW L L __ so f er en EA HUR 8 Chapter 4 Re
18. g during sampling The on board SRAM stores different gain values and configuration for each channel This design lets you perform multi channel high speed sampling up to 100 kHz with different gains for each channel with free combination of single ended and differential inputs On board FIFO First In First Out Memory The PCI 1710 1710HG has an on board FIFO buffer which can store up to 4K A D samples The PCI 1710 1710HG generates an interrupt when the FIFO is half full This feature provides continuous high speed data transfer and more predictable performance on Windows systems PCI 1710 1710HG User s Manual 1 2 On board Programmable Counter The PCI 1710 1710HG provides a programmable counter for generat ing a pacer trigger for the A D conversion The counter chip is an 82C54 or equivalent which includes three 16 bit counters on a 10 MHz clock One counter is used as an event counter for counting events coming from the input channels The other two are cascaded together to make a 32 bit timer for a pacer trigger Features e 16 single ended or 8 differential analog inputs or a combination e 12 bit A D converter with up to 100 kHz sampling rate e Programmable gain for each input channel Automatic channel gain scanning On board 4K samples FIFO buffer Two 12 bit analog output channels 16 digital inputs and 16 digital outputs Programmable pacer counter Chapter 1 General Information 3 1 3 Specificatio
19. gister Structure and Format 29 30 Table 4 1 PCI 1710 1710HG register format Part 2 ae aal 7 Te s e epr 0 TT TA TT TT TI S L m jr jan or os os on pe ve on oo Counter 0 gz cr sii 24 D7 ps ps os ps D2 pi vo sai Counter 1 rendi cr fi Li iui or pe ps os ps 2 ot vo EREBE Counter 2 HETE a or Ts o 0a or oo TT TT TT TT TT PCI 1710 1710HG User s Manual Table 4 1 PCI 1710 1710HG register format Part 3 Add sema 7 e s a e e E no ng ea IE AN MOS DTCC A ee SIN J TRA Te Ta Ten MUX Control O a O eme emagister 7 Sei ji Ce eno evar asan ewa jor pacen ow E Clear Interrupt and FIFO e INN e IES DA pa channel O TT TT TT Teror 0a oe DiAcuiputcnemei TT p pmp Chapter 4 Register Structure and Format 31 32 Table 4 1 PCI 1710 1710HG register format Part 4 Base Address ted THR conti S ERZA RAE K ma HERE HER E AO Ra D Sito a oos pom vos po 2 pon poso bos vos 5 por vos vos vos vos voz por Doe ES Counter 0 Counter 1 ESE a ll 24 oz pe ps 04 os 02 Di vo Rene Counter 2 esili cora cis rice EE KEL or pe ps 04 ps 02 Di vo Punter Counter Control AAA i so oz pe ps o4 pe pa pi po i A EEE el es o pe ps 04 os pe Di po Counter Co
20. ignal ground to the Low input Figure 3 3 shows a differential channel connection between a ground reference signal source and an input channel on the PCI 1710 1710HG 20 PCI 1710 1710HG User s Manual card With this connection the PGIA rejects a common mode voltage Y between the signal source and the PCI 1710 1710HG ground shown as V in Figure 3 3 Internal j External Ground Vs Referenced Signal Source Y Cees oltage 1 0 Connector Figure 3 3 Differential input channel connection ground reference signal source If a floating signal source is connected to the differential input channel the signal source may exceed the common mode signal range of the PGIA and the PGIA will be saturated with erroneous voltage readings You must therefore reference the signal source to the AIGND Figure 3 4 shows a differential channel connection between a floating signal source and an input channel on the PCI 1710 1710HG card In this figure each side of the floating signal source is connected through a resistor to the AIGND This connection can reject the common mode voltage between the signal source and the PCI 1710 1710HG card ground Chapter 3 Signal Connections 21 Measured oltage Internal i External Multiplexer Floating Vs Signal Source 22 Figure 3 4 Differential input channel connection floating signal source However this connection has the disadvantage of loadi
21. le interval timer counter chip The popular 82C54 offers three independent 16 bit counters counter 0 counter 1 and counter 2 Each counter has a clock input control gate and an output You can program each counter for maximum count values from 2 to 65535 The 82C54 has a maximum input clock frequency of 1 MHz The PCI 1710 1710HG provides 1 MHz input frequencies to the counter chip from an on board crystal oscillator Counter O On the PCI 1710 1710HG counter 0 can be a 16 bit timer or an event counter selectable by users When the clock source is set as an internal source counter 0 is a 16 bit timer when set as an external source then counter 0 is an event counter and the clock source comes from CNTO_CLK The counter is controlled by CNTO_GATE When CNTO_GATE input is high counter O will begin to count Counter 1 amp 2 Counter 1 and counter 2 of the counter chip are cascaded to create a 32 bit timer for the pacer trigger A low to high edge of counter 2 output PACER_OUT will trigger an A D conversion At the same time you can use this signal as a synchronous signal for other applications 52 PCI 1750 User s Manual A 2 Counter Read Write and Control Registers The 82C54 programmable interval timer uses four registers at addresses BASE 24 Dec BASE 26 Dec BASE 28 Dec and BASE 30 Dec for read write and control of counter functions Register functions appear below Register Function BASE 24 Dec Cou
22. ly 6 Secure the PCI 1710 1710HG by screwing the mounting bracket to the back panel of the computer 7 Attach any accessories 68 pin cable wiring terminal etc to the card 8 Replace the cover of your computer Connect the cables you removed in step 2 9 Turn the computer power on Chapter 2 Installation 11 12 PCI 1751 1710HG User s Manual CHAPTER Signal Connections 3 1 Overview 3 2 Correct signal connections are one of the most important factors in ensuring that your application system is sending and receiving data correctly A good signal connection can avoid much unnecessary and costly damage to your valuable PC and other hardware devices This chapter will provide some useful information about how to connect input and output signals to the PCI 1710 1710HG card via the I O connector I O Connector 14 The I O connector for the PCI 1710 1710HG card has 68 pins that you can connect to 68 pin accessories with the PCL 10168 shielded cable Note The PCL 10168 shielded cable is specially designed for the PCI 1710 1710HG for reducing noise in the analog signal lines Its wires are all twisted pairs and the analog lines and digital lines are seperately shielded providing minimal cross talk between signals and the best protection against EMI EMC problems Pin Assignment Figure 3 1 shows the pin assignments for the 68 pin I O connector on the PCI 1710 1710HG card PCI 1710 1710HG User s Manu
23. nal Connections 23 3 5 Trigger Source Connections 24 Internal Pacer Trigger Connection The PCI 1710 1710HG card includes one 82C54 compatible programma ble timer counter chip which provides three 16 bit counters connected to a 1 MHz clock designated as Counter 0 Counter 1 and Counter 2 Counter 0 is an event counter for counting events coming from the input channels Counter 1 and Counter 2 are cascaded to create a 32 bit timer for pacer triggering A low to high edge from the Counter 2 output PACER OUT will trigger an A D conversion on the PCI 1710 1710HG card At the same time you can also use this signal as a synchronous signal for other applications External Trigger Source Connection In addition to pacer triggering the PCI 1710 1710HG card also allows external triggering for A D conversions When a 5 V source is connected to TRG_GATE the external trigger function is enabled A low to high edge coming from EXT_TRG will trigger an A D conver sion on the PCI 1710 1710HG card When DGND is connected to TRG_GATE the external trigger function is disabled PCI 1710 1710HG User s Manual 3 6 Field Wiring Considerations When you use the PCI 1710 1710HG card to acquire outside data environmental noise can seriously affect the accuracy of your mea surements if you don t provide any protection The following sugges tions will be helpful when running signal wires between signal sources and the PCI 1710 1710HG card
24. nchronous signal for other applications A low to high edge triggers A D conversion to start A D External Trigger Gate This pin is external trigger signal input gate control When TRG _GATE is connected to 5 V it will enable TRG GATE DONE hput the external trigger signal to input When TRG _GATE is connected to DGND it will disable the external trigger signal to input A D External Trigger This pin is external trigger signal input for the A D conversion A nA RA DGND input low to high edge triggers A D conversion to start DGND Output 12 Voc Source This pin is 12V power supply DGND Output 5 Voc Source This pin is 5 V power supply 18 PCI 1710 1710HG User s Manual 3 3 Analog Input Connections The PCI 1710 1710HG card supports either 16 single ended or 8 differential analog inputs Input channel configuration is selected by software Selection by software is more convenient than selection by a slide switch on the card In the past if you set one single ended or differential input channel by switch the other channels also would be single ended or differential But on the PCI 1710 1710HG card if you set one single ended or differential input channel by software the other channels will maintain their original configurations Single ended Channel Connections The single ended input configuration has only one signal wire for each channel and the measured voltage Vm is the voltage of the wire referred to
25. nel when writing to the register BASE 2 Otherwise if the A D trigger source is on the multiplexer will continuously scan between channels and the range setting may be set to an unexpected channel Make sure the A D trigger source is turned off to avoid this kind of error The write only registers of BASE 4 and BASE 5 control how the multiplexers MUXs scan BASE 4 bit 3 to bit 0 CL3 CLO hold the start scan channel number and BASE 5 bit 3 to bit 0 CH3 CHO hold the stop scan channel number Writing to these two registers automatically initializes the scan range of the MUXs Each A D conversion trigger also sets the MUXs to the next channel With continuous triggering the MUXs will scan from the start channel to Chapter 4 Register Structure and Format 37 38 the stop channel and then repeat The following examples show the scan sequences of the MUXs all channels are set as single ended Example 1 If the start scan input channel is AI3 and the stop scan input channel is AI7 then the scan sequence is AI3 AI4 AIS AI6 AI7 AD AI4 AIS Alp AI7 AB AIA Example 2 If the start scan channel is AI13 and the stop scan channel is AI2 then the scan sequence is AI13 AI14 ANS ATO All AD AI13 AI14 AI15 AIO Al AD AI13 AI14 The scan logic of the PCI 1710 1710HG card is powerful and easily understood You can set the gain code B U and S D for each channel The scan logic will be a little complex if you set the
26. ng the source down with the series combination sum of the two resistors For r and r for example if the input impedance r is 1 kQ and each of the two resistors is 100 kQ then the resistors load down the signal source with 200 KQ 100 KQ 100 kQ resulting in a 0 5 gain error The following gives a simplified representation of the circuit and calculat ing process rs 1 KQ Vs ideal signal source Vi measured signal source Vi ls output impedance of signal source Pa Fb series wound resistors Ta Tb 200 200 Na Vs Ve Tanne 7 44200 Ne 7 201 Sez es Gain error V oa 0 5 PCI 1710 1710HG User s Manual 3 4 Analog Output Connections The PCI 1710 1710HG card provides two D A output channels DAO_OUT and DA1_OUT Users may use the PCI 1710 1710HG internally provided precision 5V 10V reference to generate 0 to 5 V 10 V D A output range Users also may create D A output range through external references DAO_REF and DAI REE The maximum reference input range is 10 V Connecting with an external reference of 7 V will generate 0 to 7 V DA output Figure 3 5 shows how to make analog output and external reference input connections on the PCI 1710 1710HG card Internal External 2 FY NT REF EE External Reference for DA signal 0 DATA BUS External Reference for DA signal 1 Lo 77 NT_REF O Connector Figure 3 5 Analog output connections Chapter 3 Sig
27. ns 4 Analog Input e Channels 16 single ended or 8 differential software programma ble e Resolution 12 bit On board FIFO 4K samples Conversion time 8 us e Input range V software programmable PCI 1710 PCI 1710HG 10 5 2 5 1 25 10 5 1 0 5 0 1 0 05 0 625 0 01 0 005 0 10 0 5 0 2 5 o 2 Unipol 9 19y 0 10 0 1 0 0 1 0 0 01 Maximum Input Overvoltage 30 V Common Mode Rejection Ratio CMRR Bipolar PCI 1710 PCI 1710HG EREN 84dB 1000 106dB PCI 1710 1710HG User s Manual Maximum data throughput PCI 1710 100 kHz PCI 1710HG variable depending on PGIA settling time PCI 1710HG MON 35 kHz 500 1000 770 Hz e Accuracy depending on gain PCI 1710 PCI 1710HG MOE 0 01 of 0 01 of FSR 1 LSB FSR 1 LSB SEP 0 02 of rep 1 Lan SEP sain 0 02 of FSR 1 LSB Cra CE BESE ei S E Single ended D Differential s Linearity error 1 LSB e Input impedance 1 GQ s Trigger mode Software on board programmable pacer or external Chapter 1 General Information 5 Analog Output Channels 2 Resolution 12 bit Relative accuracy 1 2 LSB Gain error 1 LSB Maximum update rate 100 K samples s Slew rate 10 V us Output range software programmable With internal reference 0 5 V 0 10V With external reference 0 x V x V 10 lt x lt 10 Digital Input e Channels 1
28. nter 0 read write BASE 26 Dec Counter 1 read write BASE 28 Dec Counter 2 read write BASE 30 Dec Counter control word we e Je ee Since the 82C54 counter uses a 16 bit structure each section of read write data is split into a least significant byte LSB and most significant byte MSB To avoid errors it is important that you make read write operations in pairs and keep track of the byte order The data format for the control register appears below BASE 30 Dec 82C54 control standard mode Bit D7 D6 D5 D4 D3 D2 D1 DO Value SC1 SCO RW1 RWO M2 M1 MO BCD Description SC1 amp SCO Select counter Counter SCI Sco 0 0 0 1 0 1 2 1 0 Read back command 1 1 Appendix A 8524 Counter Chip Functions 53 RW1 amp RWO Select read write operation Operation RW1 RWO Counter latch 0 0 Read write LSB 0 1 Read write MSB 1 0 Read write LSB first 1 1 then MSB M2 M1 amp MO Select operating mode M2 1 MO Mode Description 0 Stop on terminal count Programmable one shot Rate generator Square wave rate generator Software triggered strobe Hardware triggered strobe 9O S o cl e 0 1 0 1 0 1 Qn 9 J ND k BCD Select binary or BCD counting BCD Type 0 Binary counting 16 bits 1 Binary coded decimal BCD counting If you set the module for binary counting the count can be any number from 0 up to 65535
29. ntil you reload it with the mode or a new count value The counter continues to decrement after it reaches the terminal count Rewriting a counter register during counting has the following results 1 Writing to the first byte stops the current counting 2 Writing to the second byte starts the new count MODE 1 Programmable One shot Pulse The output is initially high The output will go low on the count following the rising edge of the gate input It will then go high on the terminal count If you load a new count value while the output is low the new value will not affect the duration of the one shot pulse until the succeeding trigger You can read the current count at any time without affecting the one shot pulse The one shot is retriggerable thus the output will remain low for the full count after any rising edge at the gate input MODE 2 Rate Generator The output will be low for one period of the input clock The period from one output pulse to the next equals the number of input counts in the counter register If you reload the counter register between output pulses the present period will not be affected but the subsequent period will reflect the value 56 PCI 1750 User s Manual The gate input when low will force the output high When the gate input goes high the counter will start from the initial count You can thus use the gate input to synchronize the counter With this mode the output will remain high until
30. ntrol PCI 1710 1710HG User s Manual 4 3 Channel Number and A D Data BASE 0 and BASE 1 These two bytes BASE 0 and BASE 1 hold the result of A D conversion data The 12 bits of data from the A D conversion are stored in BASE 1 bit 3 to bit 0 and BASE 0 bit 7 to bit 0 BASE 1 bit 7 to bit 4 hold the source A D channel number Table 4 2 Register for channel number and A D data Pee IE CI EC 99 E RS AD11 ADO Result of A D Conversion ADO is the least significant bit LSB of the A D data and AD11 is the most significant bit MSB CH3 CH0 A D Channel Number CH3 CHO hold the number of the A D channel from which the data is received CH3 is the MSB and CHO is the LSB 4 4 Software A D Trigger BASE 0 You can trigger an A D conversion by software the card s on board pacer or an external pulse Bit 2 to bit 0 of register BASE 6 can select the trigger source see page 39 and page 40 for the register layout of BASE 6 and programming information If you select software triggering a write to the register BASE 0 with any value will trigger an A D conversion Chapter 4 Register Structure and Format 33 4 5 A D Channel Range Setting BASE 2 34 Each A D channel has its own input range controlled by a range code stored in the on board RAM If you want to change the range code for a given channel select the channel as the start channel and the stop channel in the registers of BASE 4 an
31. select the desired counter s This single command is functionally equivalent to multiple counter latch commands one for each counter latched The read back command can also latch status information for selected counter s by setting STA bit 0 The status must be latched to be read the status of a counter is accessed by a read from that counter The counter status format appears at the beginning of the chapter PCI 1750 User s Manual Counter Latch Operation Users often want to read the value of a counter without disturbing the count in progress You do this by latching the count value for the specific counter then reading the value The 82C54 supports the counter latch operation in two ways The first way is to set bits RW1 and RWO to 0 This latches the count of the selected counter in a 16 bit hold register The second way is to perform a latch operation under the read back command Set bits SC1 and SCO to 1 and CNT 0 The second method has the advantage of operating several counters at the same time A subsequent read operation on the selected counter will retrieve the latched value Appendix A 8524 Counter Chip Functions 59 60 PCI 1750 User s Manual
32. te sign For example if V_ 1 5 V then V should be 4 9959 V If Vets 10 V V should be 9 9918 V 48 PCI 1710 1710HG User s Manual 5 5 Self A D Calibration Under many conditions it is difficult to find a good enough DC voltage source for A D calibration There is a simple method to solve this problem First you should calibrate D A channel 0 DAO_OUT with internal reference 5 V and D A channel 1 DA1_OUT with reference 10 V Then run the ADCAL EXE program to finish the self A D calibration procedure 1 Set AIQ as differential bipolar range 5 V and AL as differential unipolar range 0 to 10 V Connect DAO_OUT with codes equal to 4095 LSB 4 9959 V to AI 0 Notice that the polarity of AIO should be connected with reverse polarity i e D A to A D D A to A D Adjust VR2 until the output codes from the card s AIO flicker between 0 and 1 Connect DAO_OUT with codes equal to 4095 LSB 4 9959 V to ATO Adjust VR3 until the output codes from the card s AIO flickers between 4094 and 4095 Repeat steps 2 through 5 adjusting VR2 and VR3 Connect DA1_OUT with codes equal to 1 LSB 2 44 mV to AI2 Adjust VR1 until the output codes from the card s AI1 flicker between 0 and 1 Finish ADCAL EXE Chapter 5 Calibration 49 50 PCI 1710 1710HG User s Manual APPENDIX 82C54 Counter Chip Functions A 1 The Intel 82C54 The PCI 1710 1710HG uses one Intel 82C54 compatible programma b
33. ter BASE 6 allows users to set an A D trigger source and an interrupt source Table 4 7 Control register Control Register wre SW Software trigger enable bit Set 1 to enable software trigger and set 0 to disable PACER PACER trigger enable bit Set 1 to enable pacer trigger and set 0 to disable EXT External trigger enable bit Set 1 to enable external trigger and set 0 to disable Note Users cannot enable SW PACER and EXT concurrently Chapter 4 Register Structure and Format 39 GATE External trigger gate function enable bit Set 1 to enable external trigger gate function and set 0 to disable IRQEN Interrupt enable bit Set 1 to enable interrupt and set 0 to disable ONE FH Interrupt source bit Set 0 to interrupt when an A D conversion occurs and set 1 to interrupt when the FIFO is half full CNTO Counter 0 clock source select bit 0 means that the clock source of Counter 0 comes from the internal clock 100 kHz and 1 means that the clock source of Counter 0 comes from the external clock maximum up to 10 MHz 4 8 Status Register BASE 6 and BASE 7 40 The registers of BASE 6 and BASE 7 provide information for the A D configuration and operation Table 4 8 Status register apa TT TT RO Pease no er Ls re eases ento onere maen care ext acen sw The content of the status register of BASE 6 is the same as that of the control register F E FIFO Emp
34. the common ground A signal source without a local ground is also called a floating source It is fairly simple to connect a single ended channel to a floating signal source In this mode the PCI 1710 1710HG card provides a reference ground for external floating signal sources Figure 3 2 shows a single ended channel connection between a floating signal source and an input channel on the PCI 1710 1710HG card Chapter 3 Signal Connections 19 Internal External AIO Lai Multipl ultiplexers Floating Vs Signal Source Al15 Measured Voltage 1 0 Connector Figure 3 2 Single ended input channel connection Differential Channel Connections The differential input configuration has two signal wires for each channel and the differential input responds only to voltage differenc es between High and Low inputs On the PCI 1710 1710HG card when all channels are configured to differential input up to 8 analog channels are available If one side of the signal source is connected to a local ground the signal source is ground referenced The ground of the signal source and the ground of the PCI 1710 1710HG will not be at exactly the same voltage as they are connected through the ground return of the equipment and building wiring The difference between the ground voltages forms a common mode voltage Y 1 To avoid the ground loop noise effect caused by common mode voltages you can connect the s
35. to 10 V Connect a DC voltage source with value equal to 0 5 LSB 4 9959 V to AIO Adjust VR2 until the output codes from the card s AIO flickers between 0 and 1 Connect a DC voltage source with a value of 4094 5 LSB 4 9953 V to AJO Adjust VR3 until the output codes from the card s AIO flickers between 4094 and 4095 Repeat step 2 to step 5 adjusting VR2 and VR3 Connect a DC voltage source with value equal to 0 5 LSB 1 22 mV to All Adjust VRI until the output codes from the card s All flickers between 0 and 1 Chapter 5 Calibration 47 A D code Mapping Voltage Hex Dec Bipolar 5V Unipolar 0 to 10V 7FFh 2047 0 0024V 4 9947V 800h 2048 4 9971V FFFh 4095 4 9947V 9 9918V 5 4 D A Calibration In a way similar to the ADCAL EXE program the DACAL EXE program leads you through the whole D A calibration procedure You can either use the on board 5 V 10 V internal reference voltage or use an external reference If you use an external reference connect a reference voltage within the range 10 V to the reference input of the D A output channel you want to calibrate Adjust the full scale gain of D A channel 0 and 1 with VR4 and VRS respectively Note Using a precision voltmeter to calibrate the D A outputs is recommended Set the D A data register to 4095 and adjust VR3 until the D A output voltage equals the reference voltage minus LSB but with the opposi
36. tructure and Format 43 4 13 Digital I O Registers BASE 16 and BASE 17 The PCI 1710 1710HG card offers 16 digital input channels and 16 digital output channels These I O channels use the input and output ports at addresses BASE 16 and BASE 17 Table 4 13 Register for digital input jaa TL Tu EDI GE D r ono one or pro oe DE EasE18 ov os os ok os pe on oo Table 4 14 Register for digital output Write gta output e IEA f s EA IE IE A f BASE DOT bora DON DOTE bon por Doe nos ense DOT Bo bos vos pos poz vos vos Note The default configuration of the digital output chan nels is a logic 0 This avoids damaging external devices during system start up or reset since the power on status is set to the default value 4 14 Programmable Timer Counter Registers BASE 24 BASE 26 BASE 28 and BASE 30 The four registers of BASE 24 BASE 26 BASE 28 and BASE 30 are used for the 82C54 programmable timer counter Please refer to Appendix A data sheets for detailed application information Note Users have to use a 16 bit word command to read write each register 44 PCI 1710 1710HG User s Manual CHAPTER 9 Calibration 5 1 Introduction Regular calibration checks are important to maintain accuracy in data acquisition and control applications We provide two calibration programs ADCAL EXE and DACAL EXE on the
37. ty flag This bit indicates whether the FIFO is empty 1 means that the FIFO is empty PCI 1710 1710HG User s Manual F H FIFO Half full flag This bit indicates whether the FIFO is half full 1 means that the FIFO is half full F F FIFO Full flag This bit indicates whether the FIFO is full 1 means that the FIFO is full IRQ Interrupt flag This bit indicates the interrupt status 1 means that an interrupt has occurred 4 9 Clear Interrupt and FIFO BASE 8 and BASE 9 Writing data to either of these two bytes clears the interrupt or the FIFO Table 4 9 Registers to clear interrupt and FIFO Write Clear Interrupt and FIFO Care ER RU E RR HEN EI BEN HEEE TA po lear FIFO BASE 9 Clear FIFO BASE 8 Clear Interrupt Chapter 4 Register Structure and Format 41 4 10 D A Output Channel 0 BASE 10 and BASE 11 The write only registers of BASE 10 and BASE 11 accept data for D A Channel 0 output Table 4 10 Registers for D A channel 0 data D A Output Channel Write HET TE A LEN XAN BEZA E E A HETE Pease TT sar pat ono Bas DA11 DAO Digital to Analog data DAO is the LSB and DA11 is the MSB of the D A data 4 11 D A Output Channel 1 BASE 12 and BASE 13 The write only registers of BASE 12 and BASE 13 accept data for the D A channel 1 output Table 5 11 Registers for D A channel 1 data wie IN OTTO OM BEE A EA ETI A HE E mse pan GH ono 0
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