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iCEcube2 User Guide

1. eee 87 Bere aer Miseni disse lo a career ern re ern ee rete ern tere rernes wre emer N err ree reenter 89 Cha ter 6 Ph sical Constraints in 1CEcube2 cec000000000000000000000000000000000000 94 Specifying Physical Constraints after Design Import and Before Placement 94 ao TVA STM orones tend end onusta ovd Nm ede M Iu PRU LAE DU TU 94 ern cia es uahi aoa boa Tem 0 ROS c 94 OHV le aN ct src 95 el icing Mo E a e E E E O ET rr eer eee 95 78 dui a E S M A E EE 100 Global Butter Promotion Detto UOD zs vri net sd arein E AEE ON eer 102 Modifying the Device Floor Plan after Placement eene 104 Chapter 7 Generating Integrating Fixed Placement IP Blocks 107 lle e ul riso MT 107 wohl addo M 110 Appendix A PCF Syntax ecce eee eee eee eee oes ose eessoessseesssessssesssesss DID iCEcube2 User Guide www SiliconBlueTech com 4 Silicon Preface About this Document The iCEcube2 User Guide provides iCE FPGA designers with an overview of the software tools and the design process using iCEcube2 This document covers the iCEcube2 tools for Project Setup Navigation and Physical Implementation on the iCE FGPA device For information on the Synopsys Synplify Pro software pl
2. 68 RV 68 Specifying Constraints Using the Timing Constraints Editor TCE sess 68 BG Os te es 00 c 70 Clock TAS EIN RC nt Stes 70 Generated Clock Qo aici nechishictepeenen rene er tn Ip PUR rarer errr rn DUUM EUNDI NEUE NEU NIME 70 Source Clock Latency X Mela icjed balacuaern renee te tener erent er Trt r eer EORR wee cub en tee rn ety 71 pat Deky Cons Tani e odaniep opo a O e ner rere rhe r terre E UN 71 Quipu Delay Bag cna tba Comme rene ene erence rine eee N E CMU ere eer ener rrr er rer err ereee 72 Max Delay ONS IS sareni nnne erer ae e eaae Mines stupeo iaaa ie 72 Falbe geld gy vcio uen Re 73 Mali Cycle Path Exceptions Mm 74 3 www SiliconBlueTech com iCEcube2 User Guide Silicon Analyzing Reports Generated by the Static Timing Analyzer STA eee 75 CIock oummpdr DOE rea oin i ISP T O pessum ee eee ee re 49 Clock h E te hol PAUA V gerne mn edet v e sr mur ura gene NIMM osque Made UU UE 79 IB chico tle al e E E E E E T E 79 cuna zn Constrained Pale neern n AE E 81 Nee eee E 81 EE e EO 83 EO E a cte 85 S d An Ee h cc en eee eer ene eee
3. The user now has the option to selectively display the nets connected to a cell For example selecting the Display fan in nets menu item displays only the nets that drive the node i e the fan in nets Similarly if the user wishes to display only the nets that are driven by the selected node the Display fan out nets menu item should be selected Both fan in and fan out nets can be displayed simultaneously by selecting the Display fan in amp fan out nets menu item As an example both fan in and fan out nets of a Block RAM cell are shown in Figure 4 8 It should be noted that the fan in nets connect to the left side of the driven cell and are depicted in light yellow Fan out nets connect to the right side of the driver cell and are depicted in dark pink Using fan in and fan out nets the user can traverse the design from cell to cell and make appropriate decisions about modifying the placement manually Figure 4 8 Fan in and Fan out Nets displayed in Floor Plan Note that by default the fan in and fan out nets are displayed whenever a cell is selected This setting can be changed by disabling it in the Tool Tool Options gt Floor Planner tab as displayed in Figure 4 9below 55 www SiliconBlueTech com iCEcube2 User Guide Silicon QD Tool Options X Placer Router Bitmap Floor Planner Show Fan in nets after a cell is selected Show Fan out nets after a cell is selected Figure 4 9 Floor Planner Options Package
4. Using the third option the results can be restricted based on the maximum slack value The Save Summary and Save Detail provide the ability to save the report in a text format for all paths or the details of the selected path respectively Clock Summary Clock Relationship Summary Datasheet Analyze Paths Generate timing report and sdf Exit Full Screen Mode By Slack By Paths Point to Point Limit Report to 100 paths Maximum No of paths display option Advanced Options Fi HE r Clocks Launch Clock CLK 32MHz Z v Phase Rise Capture Clock CLK 32MHz v Phase Rise w Paths per start point Paths per end point No Limit No Limit Limit to limit to Maximum Slack No Limit umeto Filtering based on maximum slack value Paths Summary 100 Save Summary Save Detail_ Save Detail sort _ Customize Columns Customize Columns Start Point Start Edge End Point Slack Delay Skew Launch Clock Capture Clock 1 GROUPO GROUPO1L COUNTE RISE LED 0 18367 5388 7130 CLK 32MHz R CLK 32MHz R P 2 GROUPO GROUPO COUNTE RISE LED 2 18785 4970 7130 CLK 32MHz R CLK 32MHz R 3 GROUPO GROUPO1 COUNTE RISE LED 3 18830 4925 7130 CLK 32MHz R CLK 32MHz R 5 GROUPO GROUPO1 COUNTE RISE GROUPO GROUPO1 COLINTER10 Q 15 LC 7 20 26777 3667 CLK 32MHz R CLK 32MHz R 5 GROUPO GROUPO1 COUNTE RISE GROUPO GROLUPOT COUNTEROS Q 15 LC 7 18 2
5. LED 1 LED obuf 1 LED 2 LED obuf 2 a LED 3 LED obuf 3 Terminal Type E InOuts H A gt gt PRE IOs Terminal List gt gt 1 CLK OUT obuf PACKAGE PIN Port E Logic Cell lt RAM Global PLL v CTW aths Summary ave Summary Save Detail or ustomize Columns Paths 5i 1 Paths Save S Save Detail Sort Customize Col Start Point _ Start Edge End Point Delay CLK_32kHz_ibuf_iopad PACKAGE_PIN CLK_OUT_obuf_iopad PACKAGE_PIN Figure 5 22 Analyzing Point to Point delays iCEcube2 User Guide www SiliconBlueTech com 86 Clock Summary Clock Relationship Summary Datasheet Analyze Paths By Slack By Paths p Path Detail Generate timing report and sdf Exit Full Screen Mode Stat CLK 32kH buf iopadJPACKAGE PIN Delay 7946 End CLK OUT obuf iopad PACKAGE PIN Path Detailed Path Report Save Detail Customize Columns Pin Name E Routing Delay 1_918 0 Routing Delay I 897 I 897 0 I 899 I 1_899 0 Other Features Various other features in Timing Analyzer include CLK_32kH2_ibuf_iopad CLK_32kH2_ibuf_iopad CLK 32kHz ibuf preio CLK 32kHz ibuf preio Clock Output uni ck 0 0 LC Clock Output uni clk 0 0 LC CLK OUT obuf preio D OUT 0 CLK OUT obuf preiojPADOUT LK OUT obuf iopad DIN C IO PAD 0 5593 FALL CLK QUT obuf iopad PACKAGE PIN IO PAD 2353 7946 FALL Model Name PACKAGE_PIN IO
6. Region Constraints can be specified in the GUI Going to Region tab in Floor Planner and right clicking on it gives an option to create a Region as shown in the Figure 6 6 The coordinates of the region can be selected by dragging the mouse on the Floor Planner view A pop up dialog box comes up asking the name of the region By entering the name a Region would be created User can change the co ordinates of a created region by changing the properties of the region which are available by a right click on the region name The properties of the region gives user the options to change region co ordinates type of region inclusive blocked groups assigned to If the Region is of type Inclusive the logic in the Group assigned to the Region is placed inside the boundary of the Region If the Region type is Blocked no logic is placed inside the Region T 5 A i Alh A y Output Region 8x Region Type Location ey hep ge i FERERELEI LEN punus anu es ut x i nimm n dert Monge m de dp rg d rrEFrREPLEE i i i A LM Create Region f f vf barbie te Region name A REEERE IEI 1 F B FPE En FFs Region vL Ses eee 2 Se on Create Inclusive Region Create Blocked Region Logic GPIO Global RAM Net Group Region Figure 6 6 Creating an Inclusive Region Once a region is created user can assign a Group to a Region by going to Group tab and changing its properties Figure 6 7 shows how to set group to
7. Figure 3 8 PLL Module Generator Frequency Specification Fine Delay Adjustment The delay contributed by the FDA block can be Fixed or controlled dynamically during FPGA operation If Fixed it is necessary to provide a number n in the range 41 www SiliconBlueTech com iCEcube2 User Guide Silicon 0 15 to specify the delay contributed to the feedback path The delay for a setting n is calculated as follows FDA delay n 1 0 15 ps where n is the value specified by the user and 0 lt n x 15 Frequency Specification The input and output frequency of the PLL should be specified in MHz as shown in Figure 3 10 Depending on the values provided by the user the PLL is internally configured to generate the specified output frequency Frequency Specification window also checks for the input and output frequencies given by the user If the specified frequencies are at a range that cannot be generated by the PLL then a popup comes out as shown in Figure 3 91 asking the user to enter the frequencies in valid range IW PLL Module Generator PLL Input Output Frequency Others Fi Create a LOCK output port Create a BYPASS port that will bypass the PLL reference clock to the PLL output port f Note khat the PLL requires re lacking when the BYPASS signal is de asserted For all modes other than the No Compensation mode Low Power Made Enable latching of PLL output clock iCEGate Mate that the PLL requiresessslacla
8. ie We We Ee FSM Compiler Resource Sharing 4 4 Pipelining 4 4 Retiming B quick start syn prj Information M M T4 Wr e eee License synplifypro sbt node locked amp TCL Script Messages Log Watch D J v Nos Figure 2 6 Synplify Pro Graphical User Interface Hit the Run Button to synthesis your design Once synthesis is complete you will see a Done message See Figure 2 7 iCEcube2 User Guide www SiliconBlueTech com 14 Synplify Pro D 2009 12S Early Access 2 C SbtTools examples blinky quick start quick start syn prj P Cy Fie Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help M Eod d 4 ABO Ee OD Mox 8 x 6 9 2449 990 4i s po m 0 errors 4 warnings 19 notes quick start Implmnt Silicon Blue iCE65 iCE65L04 CB284 e gt quick start syn C SbtTools examples b gef startiquick start syr dd blinky vhd work WARNINGS 4 NOTES 6 Information SBTiCE65 Mapper Completed with warnings Return Code 1 Completion Time 13 37 50 Implementation Directory C SbtTools examples blinky quick_start quick_start_Implmnt Directory Directory Directory Directory Directory log File Edif Netlist fse File htm File scf File Netlist Netlist RTL 869 bytes quick_start_prepass srd 7 kB Figure 2 7 View Timing Constraints S
9. 11 6755 Right Bank IO Voltage 1 Power Consumption Static PowertmiWh 0 1596 Top Bank IO valtage V Dynamic PowertmW 11 9802 Bottom Bank IO volrage V Total PowertmW 12 1398 Figure 4 13 Power Estimator Summary Tab The IO tab displayed in Figure 4 146 permits the user to specify the toggle rate for the design s input and output ports as well as loading capacitance for output pins Power Estimator Summary IO Clock Domain IO Port Mame Switching Frequency MHz Qutput Pin Load Capacitance pF PMOD B3B J3e 3 4 00 10 00 PMOD B3B Jae 1 4 00 30 01 PMOD B2L Jai 3 33 33 moo PMOD B2R J30 1 33 33 PMOD B3T J3o 2 4 00 PMOD BzL J31 4 4 00 Figure 4 14 Power Estimator IO Tab iCEcube2 User Guide www SiliconBlueTech com 60 TM Silicontdlils O Power Estimator Summary IO Clock Domain Clock Frequency MHz of Seq LEs Seq LCs Switching Frequency MHz of Comb LCs Comb LEs Switching Frequency MHZ 1 00 0 06 COUNTER inferred dodi HD 0 06 clock divider 32MHe COUNTER inferred coci 27 0 06 4 QK 32Mhe 2 2 00 Figure 4 15 Power Estimator Clock Domain Frequency Specification The Clock Domain tab allows the user to specify the clock frequency in MHz Note that changing this frequency adjusts the operating frequency of the individual logic resources like the IO Cells LUTs Flip Flops and Block RAMs BRAM as per the built
10. Close Project Synthesis Tool E Add Synthesis Files B Design Files blinky vhd B Constraint Files blinky syn sdc pot ef Launch Synthesis Tool P amp R Flow GY Select Implementation quick start I quick start edf quick start scf Add P amp R Files Design Files TP Design Files E Constraint Files Add Files he Import P amp R Input Files D Run Placer Run Router Generate Bitmap Simulation Netlist amp Device Operating Condition amp Device Info DeviceFamily iCE65 bs i LD4 Device Package CB284 Power Grade L amp Operating Condition Core Voltage V 1 14 Temperature C 70 Add Files Figure 2 25 Add additional constraint file Navigate to the lt iCEcube2 Installation Directory examples blinky and Add blinky mtcl file See Figure 2 26 Add Files WE d C quick start constraints meel Desktop File name blinky_constraints mtcl Files of type Constraint sde scF pcF clb mech Co Cea Figure 2 26 Add mtcl file Import Place amp Route Input Files 29 www SiliconBlueTech com iCEcube2 User Guide The next step is to import the files for Place and Route Double click on Import P amp R Input Files in the Project Navigator See Figure 2 27 Once completed you will see a green check next to Import P amp R Input Files See Figure 2 28 W SiliconBlue iCEcube2 Output File view Tool Window Help Pro
11. Slack obe No No No Fa Fa Fa Path Path Path se Path se Path ze Path Figure 5 16 Clock Relationship Summary The Data Sheet report summarizes the timing characteristics of the chip interface It reports the minimum setup delay maximum clock to output delay for every port wrt the relevant clock and phase and the pad to pad delay for combinational paths Setup Delay Gives the setup times for clocks in the design for each combination of input data port and clock port Setup time for an Input port wrt a clock is given by Setup delay Maximum Data delay from Input Pad to FF FF setup delay Clock Path Delay Clock to out Delay Gives the clock to out delays for clocks in the design for each combination of output data port and clock port Clock to out delay for an output port wrt a clock is given by 79 www SiliconBlueTech com iCEcube2 User Guide Silicon Qi Clock to out delay Maximum Clock Path Delay FF clock to out delay Data delay from FF to Output Pad Pad to Pad Delay Reports the Pad to Pad delay for a signal traversing from input pad to output pad Pad to Pad delay Combinational Delay from PI to PO A sample Setup to Clock Data Sheet report by the iCEcube2 software is shown in Figure 5 16 Setup to Clock Clockto Out PadtoPad Data Port Clock Port Delay ps Clock Reference Phast 1 LOAD CLK_32MH2 in 0047 CLK 32MHz R LOAD CLK_32k
12. 1 Specify a Device Family 2 Specify a Device using the drop down menu 3 Select a suitable Device Package for the device selected in the previous step 4 Specify a Power Grade for the selected device This option is available only for iCE65 family as shown in Figure 3 6 The iCEcube2 software supports two Power Grades viz the L which signifies the Low Power device and the U which signifies the Ultra Low Power device Specifying the Operating Conditions for the target device involves the following steps 1 Junction Temperature a Select an appropriate Junction Temperature Range from the options available Depending on the Power Grade selected for the target device the software provides built in options such as Commercial and Industrial temperature ranges b If the device s operating conditions do not fall into either the Commercial or the Industrial temperature ranges the software also permits the user to specify a customized junction temperature This is accomplished by selecting the Custom option and manually specifying the Best Typical and Worst Case junction temperatures 2 Core Voltage Select a Voltage Tolerance Range from the provided options 3 TOBank Voltage This option is available only for iCE40 family as shown in Figure 3 5 Select a bank voltage from the provided options for the top bottom left right banks The specified IO Voltage values are used by Power Estimator and Static Timing Analysis t
13. 426 8864 FALL 1 LED obuf 1 iopad DIM IO PAD 0 8864 FALL 1 LED obuf 1 iopad PACKAGE PIN IO PAD 2353 11218 FALL 1 LED 1 counter power 0 11218 FALL 1 Figure 5 19 Detailed Path Summary of the selected path By Paths The By Paths page in Analyze Paths window allows the user to limit the timing report to specific Start Source and End Destination Points Start points are limited to primary design inputs flip flop outputs and RAM outputs End Points are limited to primary outputs flip flop inputs and RAM inputs All the instances of the design are shown in Resources pane User can search for specific set of resources by using the Find Resource option User can select the Start and End points from Resource pane and can move them to From to To options pane as shown in Figure 5 20 The Resources which are used in From or To options can be a Register Register in IO IO or RAM Timing report will be generated for the set of paths beginning with nodes in the From category and ending with nodes in the To category User can customize the number of paths reported by using No Path Limit and Limit Report to 100 Paths options More Options button gives user different filters to limit the timing reports Various filters include filtering the reported paths based on Launch Clock Latch Capture clock and their phases filtering the paths based on number of paths pe
14. Clock Summary 2 Clock Relationship Summary 3 Data Sheet Report 4 Detailed Report of All timing paths Clock Summary Clock Summary gives details about all clocks in the design their target and computed frequencies Also it reports the frequency defining path for each clock Example 1 shows a typical clock summary report generated by the iCEcube2 STA tool Example 1 Number of clocks 2 Clock clocka Frequency 69 90 MHz Target 100 00 MHz Clock clockb Frequency 322 13 MHz Target 100 00 MHz 89 www SiliconBlueTech com iCEcube2 User Guide Silicon Clock Relationship Summary The Clock Relationship Summary gives the details of constraints and slack details for the critical paths which are in the same clock domain as well as cross clock domains Example is a typical clock relationship summary report generated by iCEcube2 tool Clocka R Clocka R 10000 306 5 Example 2 Clocka F Clockb F False Path False Path Clockb R Clockb R 10000 65 64 Note 1 False Path means the path with such pair of clock edges are constrained as false paths Along with reporting the clock relationship table iCEcube2 STA reports the detailed path report for each worst slack reported in clock relationship summary table Data Sheet Report The Data Sheet report summarizes the timing characteristics of the chip interface It reports the minimum setup delay maximum clock to output delay for every port wrt the relevant clock and
15. Core Voltage V Temperature C Figure 3 5 Launching the PLL Module Generator The PLL Module Generator allows the user to create a new PLL configuration or edit an existing one as shown in Figure 3 7 The output of the PLL Module Generator is a PLL module file Verilog that instantiates a PLL as configured by the user A secondary file wrapper that includes an instance of the PLL module is generated in order to help instantiate the PLL module in the user s design Note that the PLL module file should be included in the list of design files Once a PLL module file has been generated it can be edited by selecting the Modify an existing PLL configuration option Figure 3 7 iCEcube2 User Guide www SiliconBlueTech com 38 TM Silicontdlils v PLL Module Generator Device Family iCE40 v Do you want to modify an existing PLL configuration or create a new one Create a new PLL configuration PLL Module Name mypll Modify an existing PLL configuration PLL Module File Figure 3 6 Create Modify a PLL configuration Configuring a iCE65 PLL Module In the PLL Module Generator wizard select Device Family as iCE65 and provide the PLL Module Name Click on the OK button The PLL Module Generator launches a wizard to help the user configure the PLL as per the design requirements This section describes the features of iCE65 family PLL modules PLL Type The connectivity of the PLL
16. Need to Generate Bitmap Output Files Reports Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily Device Device Package Power Grade Operating Condition Core Voltage Temperature C run Figure 2 12 Select Synthesis Implementation Importing Physical Constraints Physical constraints such as pin assignments are stored in a PCF file Physical Constraint File Add the PCF file to your project In the iCEcube2 Project Navigator Right Click on Constraint Files Select Add Files See Figure 2 13 Note For information on importing physical constraints from iCEcube to iCEcube2 please refer to the Importing Physical Constraints from iCEcube to iCEcube2 section at the end of this quick start guide iCEcube2 User Guide www SiliconBlueTech com 20 SiliconBlue iCEcube 2 Output File View Tool Window Help Project New Project Open Project Close Project Synthesis Tool E Add Synthesis Files B Design Files blinky vhd B Constraint Files blinky syn sdc ff Launch Synthesis Tool P amp R Flow GY Select Implementation quick start I quick start edf quick start scf Add P amp R Files Design Files TP Design Files E Constraint Files Add Files pe Import P amp R Input Files D Run Placer Run Router Generate Bitmap Simulation Netlist amp Device Operating Condition amp Device Info DeviceFamily i
17. Output SIX Timing Analyzer Clock Summary Clock Relationship Summary Datasheet Analyze Paths Clock Name 1 Clk 32Mhz highfreq N Clk 32khz lowfreq clock divider 1Hz LED CLK inferred cl clock divider 32MHz UPPER COUNT infe co A Worst Slack ps 20123 993631 996557 996646 FMAX MHZ 89 87 157 02 290 43 298 12 32 Generate timing report and sdf Full Screen Mode Customize Columns Failing Path Target Frequency MHZ 0 0 0 CELW Critical Path 1 Start Point 1 DIVIDE_32MHz COUNTER_O_LC_13_4_1 lcout End Point DIVIDE 32MHz Slack 20123 Save Detail Customize Columns Delay Skew Launch Clock Capture Clock 10337 o Clk 32Mhz highf Clk 32Mhz highf H Reports Bitmap H Simulation Netlist Device Operating Condition amp Device Info DeviceFamily Device L04 Device Package CB284 Power Grade L Operating Condition Core voltage Temperature C iCE6S 1 14 70 lt Figure 2 22 Timing Analysis Summary You can see from the timing analysis that our 1MHz design is running at over 117 MHz and our 32 MHz clock is running at over 79 MHz worst case timing If we were not meeting timing the timing analyzer will allow you to see your failing paths and do a more in depth analysis For this tutorial we won t go into details on timing slack analysis Perform Power Analysis iCEcube2 also comes with power e
18. a cee 4 39 1 bL Ek t 1 E HH tet Be EH Be OQ amp 1 arnat f FEY ok be D J I DL ra a I iT 4 Figure 2 19 Package Viewer Route the Design Double click on Route in the project navigation window Place and Route have been separated into different steps as to allow you to re route the design after making placement modifications in the floorplanner without having to re run the placer 25 www SiliconBlueTech com iCEcube2 User Guide Perform Static Timing Analysis Now that you have routed the design you can perform timing analysis to check to see if the design is meets your timing requirements To launch the timing analyzer go to the menu and select Tool gt Timing Analysis You can also select the Timing Analysis Icon See Figure 2 22 W SiliconBlue iCEcube2 Output Timing Analyzer W File View Tool Window Help Project New Project Open Project Close Project Synthesis Tool Add Synthesis Files Design Files blinky vhd Constraint Files blinky syn sdc e Launch Synthesis Tool P amp R Flow SY Select Implementation quick_sta quick_start edf quick_start scf Add P amp R Files Design Files IP Design Files Constraint Files blinky pcf Run All e Import P amp R Input Files e Run Placer e Run Router gt Generate Bitmap Output Files a BEB es Q4 oe D e BABES Project Name quick start mx Timing Analysis Icon
19. ee kaiamalin ede abel uber EE beck sath is external to the PLL Enable latching of PLL sour PLL Module Generator Input Frequency must between 10 and 133 3333 Mhz Figure 3 9 Frequency Validation by PLL Configurator Other options LOCK A Lock signal is provided to indicate that the PLL has locked on to the incoming signal Lock asserts High to indicate that the PLL has achieved frequency lock with a good phase lock BYPASS A BYPASS signal is provided which both powers down the PLL core and bypasses it such that the PLL output tracks the input reference frequency Low Power Mode A control is provided to dynamically put the PLL into a Lower Power Mode through the iCEGate feature The iCEGate feature latches the PLL Output signal and prevents unnecessary toggling The RESET Active Low port is always generated so that an explicit PLL reset or bypass operation is required to initialize the PLL functionality iCEcube2 User Guide www SiliconBlueTech com 42 Silicon Configuring a iCE40 PLL Module In the PLL Module Generator wizard select Device Family as iCE40 and provide the PLL Module Name Click on the OK button The PLL Module Generator launches a wizard to help the user configure the PLL as per the design requirements This section describes the features of iCE40 family PLL modules PLL Type The connectivity of the PLL to its surrounding logic determines the PLL Type The iCEcube2 software supports the following PLL
20. jlcout RISE GROUPO GROUPOO COUNTER19 Q 6 LC 2 17 6 in3 28146 2298 0 CLK 32MHz R CLK 32MHz R counter power counter power is GROUPO GROUPOD COUNTER19 Q 0 LC 2 17 jlcout RISE GROUPO GROUPOD COUNTER19 Q 6 LC 2 17 6 in3 996896 2298 0 CLK_32kHz R CLK_32kHz R Figure 5 20 Analyzing User Specific Paths Please note that when the user searches from to an IO STA reports the paths as follows 1 From a combinational INPUT INOUT IO STA reports the path originating from that top module port To a combinational INPUT INOUT IO STA reports the path ending to that top module output port From a Registered INPUT INOUT IO STA reports the path originating from the DINO DINI pin of the corresponding IO To a Registered OUTPUT INOUT IO STA reports the path ending onto DOUTO0 DOUTI pin of the corresponding IO To a Registered INPUT INOUT IO STA reports the path from the top module port to the PACKAGE PIN of the IO From a Registered OUTPUT INOUT IO STA reports the path from the package pin of the IO to the top module port of the IO If only the From list is empty then the STA returns all the paths from all possible From source to given T list If only the To list is empty then STA returns all the paths from the given From list to all the possible To destinations If both From and To lists are empty then no paths are returned iCEcube2 User Guide www SiliconBlueTech com 84
21. 6 Power Estimator This utility assists users in estimating device power for a given design via a spreadsheet listing the various utilized resources of the device the estimated maximum operating frequency the core voltage etc 47 www SiliconBlueTech com iCEcube2 User Guide Silicon 7 Bitmap Generator To support device programming the iCEcube2 Physical Implementation Tools include a utility for generating device configuration data referred to as a bitmap 8 Device Programmer The iCEcube2 Physical Implementation Tools also include a utility for programming the iCE FPGA device Placing and Routing the Design Once the synthesized design output of Synplify Pro is loaded into the iCEcube2 Physical Implementation software the next step is to place and route the design The placement and routing process is started by clicking on the Run Placer and Run Router icons respectively Note that if the placer router is yet to be run there is a green arrow next to the appropriate icon Upon successful completion of the operation the green arrow changes into a green check mark Changing the Router Options The router options can be changed by selecting Tool gt Tool Options gt Router Note that all changes to the options require the router to be rerun The options are as follows 1 Timing Driven The router algorithms try to honor the timing constraints specified by the user 2 Pin Permutation This option is ON by default and aids the
22. B COUNTEROS O RMO 10 COUNTEROS O RMO 11 COUNTEROS O RMO 12 COLINTEROB C RMO 13 COLINTEROS C RMO 14 COLINTEROS C RMO 15 COUNTEROS O RNO 1 COUNTEROS O RMO z COUNTEROS O RMO 3 COUNTEROS O RMO 4 COUNTEROS O RMO 5 COLINTEROS C RMO 5 COLINTERDS C RMO 7 COLINTERDS C RNS COUNTEROS O RMO 8 COUNTERO QO COUNTERO O 10 COUNTERO O 11 COUNTERO O 12 COUNTERO O 13 COUNTERO O 14 COUNTERO 15 Instance Type SB CARRY SB CARRY SB CARRY SB LLT4 SB LLIT4 SB LLT4 SB LLT4 SB LLT4 SB LLT4 SB LLIT4 SB LLIT4 SB LLT4 SB LLT4 SB LLIT4 SB LLIT4 SB LLT4 SB LLT4 SB LLT4 SB LLT4 SB DFF SB DFF SB DFF SB DFF SB DFF SB DFF SB DFF Location Floor Planner E cag cag ca cag cg ca cag ca E co cag E E MCI MI SEL NO MOI SOL DISCI MOI SEIL SIDE SD MOL SDE SD MOI SEIL SO AO NO SO SO SDI MD cx Ch CTI R 00 P CO e ON Ch CDL HR 0 P 0 M 8 CT E 00 P9 C e GROUPO GROUPOL COUNTERO O 1 GPIO Global RAM Met Group SB DFF Logic World view Figure 4 6 Sort by Name option Selecting Sort by Cell option sorts the panel display based on logic cell grouping as shown below iCEcube2 User Guide www SiliconBlueTech com 52 Logic Logic Logic Instance E3 i E E E E E E E E E E E E E E E E E E E H Ee Lee LES Lee babe Le GROUPO GROUPO GROUPO GROUPO GROUPO GROUP
23. Clock Summary Clock Relationship Summary Datasheet Analyze Paths Generate timing report and sdf Exit Full Screen Mode By Slack ByPaths Point to Point Path Detail Start GROUP GROUPOD COUNTER19 Q 0 LC 2 17_Ojlcout End GROUPO GROUPOD COUNTER19 Q 6 LC 2 17 6jin3 Reference CLK 32MHz Setup Constraint 31250 p Path Slack 28146 p Capture Clock Arrival Time CLK_32MH2 R 2 31250 Capture Clock Source Latency 0 Capture Clock Path Delay 7130 Setup Time 441 End of path required time ps 37938 Launch Clock Arrival Time CLK 32MHz RXH 0 Launch Clock Source Latency 0 Launch Clock Path Delay 7130 Clock To Q 365 Data Path Delay 2298 End of path arrival time ps 9793 Data path delay consists of logic delay 6 level s 1095 ps and routing delay 1202 ps DataPath Clock Paths Save Detail Customize Columns Pin Name Model Name Delay AT Edge Fanout GROUPO GROUPOD COUNTERI9 Q D LC 2 17 LogicCel40 SEQ MODE 1000 365 7495 RISE 2 E Routing Delay 837 GROUPO GROUPOD COUNTER19 Q D LC 2 17 LogicCell40_SEQ MODE 1000 0 8332 RISE 1 GROUPO GROUPDD COUNTER19 Q 0 LC 2 17 LogicCelld SEQ MODE 1000 411 8743 RISE 2 GROUPO GROUPOD COUNTER19 Q 1 LC 2 17 LogicCell40_SEQ MODE 1000 0 8743 RISE 1 GROUPD GROUPOD COUNTER19 Q 1 LC 2 17 LogicCelld SEQ MODE 1000 137 8880 RISE 2 GROUPO GROUPOD COUNTER19 Q 2 LC 2 17 LogicCell40_SEQ MODE 1000 0 8680 RISE 1 GROUPD GROUPOD C
24. Edi E Release 2011 03 16214 blinky vhd Build Date May 17 2011 11 54 40 Constraint Files blinky_syn sde Parsing edif file C SbtTools examples blinky quick start quick start Implmnt quick start edf f Launch Synthesis Tool Parsing constraint file C SbtTools examples blinky blinky constraints mtcl 3 P amp R Flow Stored edif netlist at C SbtTools examples blinky quick start quick start Implmnt sbt netlist oadb icetest S ef Select Implementation quick sta specia write Timing Constraint to C SbtTools examples blinky quick start quick start Impluntisbt Temp sbt temp sdc S Add P amp R Files EDIF Parser succeeded Design Files Top nodule is icetes IP Design Files Constraint Files blinky_constraints mtel Run All e Import P amp R Input Files Run Placer gt Run Router D Generate Bitmap Output Files Reports Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 Device L04 Device Package CB284 Power Grade L Operating Condition Core voltage v Temperature C edif parser succeed sdc reader OK C SbtTools examples blinky quick start quick start Implunt quick start scf EDF Parser run time 1 se Figure 2 28 Successful Import of P amp R Input Files Saving Physical Constraints into pcf Format Open the Pin Constraints Editor by going to the menu and selecting Tool gt Pin Constraints Editor or you can also select the Pin Constraints Editor Icon See Figure 2 29 Yo
25. Import P amp R Input Files B IP Creation Project syn rs nee gt Run Placer lt Run Router System Desigrer Board file Generate Bitmap l IP Exporter NOTE This version of the softvare is no oe gt included described in the accompanying documentati Ca Dex Synplicity TCL Script Messages Figure 7 9 Run Synthesis 4 After successfully running synthesis close the Synplify Pro Tool This will bring you back to iCEcube2 tool The Synthesis outputs PRJNAME edf and PRJNAME scf would be automatically added to the project Now right click on the IP Design Files in Add P amp R Files select Add Files On the popup window browse to the Vendor provided IP location and add the EDF file W SiliconBlue iCEcube2 Output W File view Tool FA O BBC eS ee Joc M Window Help Project Name System Design Project z Project New Project Open Project Close Project Synthesis Tool Add Synthesis Files H Design Files Constraint Files e Launch Synthesis Tool P amp R Flow Y Select Implementation Syst System_Design_Project edf System_Design_Project scf Add P amp R Files Design Files EE Files Run All D gt Import P amp R Input Files gt Run Placer b gt Run Router D gt Generate Bitmap a m Sy Add Files Files to add Lookin C workspace msridhar DEMO IP_Flow IP_Creath v ee xported IP 48 ird Exported IP edf gt My Computer Add Se
26. PAD IO PAD PRE IO PIN TIPP PRE IO PIN TIPP Odrv4 Odrv4 InMux 5linO LogicCeldO SEQ 15 5ilcout LogicCeldO SEQ LocalMux LocalMux IoInMux IoInMux Delay 0 800 0 365 2343 0 502 0 502 0 502 0 472 0 365 0 we ALS 944 0 472 0 472 PRE IO PIN TYP 0 PRE IO PIN TYP 426 pa pas jat Figure 5 23 Detailed delay report of the selected path Timing Corner The Timing Corner option in the Timing Analyzer allows the user to analyze the timing performance of a routed design under different Power Grade Operating Conditions without having to recompile the design The Timing Corner window Figure 5 24 is used to change the power grade of the device operating conditions like ambient temperature core voltage and IO bank voltage Along with these user can also select the best typical worst cases corners at which timing analysis should be performed Whenever the Operating Conditions Power Grade are different from the settings used for design compilation the changes are highlighted in red For example in Figure 5 24 the timing analysis condition is red since the design was compiled for Worst case timing analysis 87 www SiliconBlueTech com iCEcube2 User Guide Chock Summary Clock Relationship Summary Datasheet Analyze Paths Device Device Family mMeEds0 Device LF ZEK Device Package CMa225 Operating Condition Ambient Te
27. an origin Once creating the constraint is done user can save the created constraints in PCF file by clicking the save button on the top panel Then the created PCF file will be automatically added to the current project The legality check of the created constraints can be performed by running the Import P amp R files The adherence of the constraints can be checked out by invoking the Floor Planner again after running the Placer 99 www SiliconBlueTech com iCEcube2 User Guide Silicon ZB am eje Qf Output Group Bx LogicGroup Region Create Logic Group Delete Logic Group Set Region ES Logic group name En FFs Origin point I3 5 Region name v En FFs Region Logic GPIO Global RAM Net Group Region Figure 6 7 Set group to a region IO FF Merge The device IO pads includes registers which can be used through explicit instantiation of the SB IO primitive or by merging logic registers into the IO Similarly User can separate the IO registers from the IO pads this process is called Unmerging Creating the merging and unmerging constraintsfrom GUI is shown in Error Reference source not found After successful Import P amp R Input Files open the Floor planner and select GPIO tab Right Clicking on any IO shown in Floor Planner gives the option to merge unmerge FF On selecting this option a pop up comes out asking the user to merge unmerge FF from the IO The pop up gives t
28. beginning with terminals in the From category and ending with terminals in the To category In the Path Summary pane the user can select a path and double click on it A detailed delay report of the path is displayed as shown in Figure 5 23 User can customize the number of paths reported by using No Path Limit and Limit Report to 100 Paths options 85 www SiliconBlueTech com iCEcube2 User Guide More Options button gives user different filters to limit the point to point delay reports The reports can be filtered based on number of paths per start point number of paths per end point and minimum delay value settings Full Screen Mode allows the user to view all the paths and customize window lengths in Full Screen Clock Summary Clock Relationship Summary Datasheet Analyze Paths Generate timing report and sdf Exit Full Screen Mode By Slack By Paths Point to Point No Path Limit Limit Report to 100 paths More Options Path Endpoints Find Terminal Terminal Type 4 Terminals Query From To list Terminals Comment je Port gt B Inputs Terminal Type H CLK 32kHz CLK 32kHz ibuF gt gt i i CLK ICEGATE CLK ICEGATE buf gt gt 1 CLK 32kHz ibuf PACKAGE PIN Port H CLK SELECT CLK SELECT ibuf LOAD LOAD ibuf E Outputs CLK OUT CLK OUT obuf LED 0 LED obuf 0 To
29. d 4 GROUPO GROUPOO COU SB_DFF ah ehre fem GROUPO GROUPOO COU SB_CARRY xp ERT Move GROUPO GROUPOO COU SB_LUT4 op tA 4 IN_MUX_bfy_3_9_0_ SB_CARRY_IN 3 9 8 Lock T GROUPO GROUPOO COLI SB DFF 3 10 0 d GROUPO GROUPOO COLI SB CARRY 3 10 0 w Pin Permutation d GROUPO GROUPOO COU SB LUT4 3 10 0 GROUPO GROUPOO COU SB DFF 3 10 1 Sort By Name GROUPO GROUPOO COLI SB CARRY 3 10 1 Sort By Cell GROUPO GROUPOO COU SB LUT4 3 10 1 4 al amp GROUPO GROUPOD COU SB DFF 3 102 5 Logic GPIO Global RAM Net Group World View Bx Figure 4 5 Invoking the Sort and Search functionality in the Logic IO RAM Net pane Selecting the Sort by Name option sorts the Logic instances based on instance names as shown below Logic Logic Instance enoeoa ooooaeona6 GROUPO GROUPO GROUPA GROUPO GROUPO GROUPO GROUPO GROUP GROUPO GROPO GROUPO Output GROUPOL GROUPOL GSROUPOL GSROUPOL SROUPOL GROUPO GROUPO GROUPO GROUPO GROUPOL GROUPOL GROUPOL JSROUPOL GROUPO GROUPO GSROUPOL GSROUPOL GROUPOL GROUPO GSROUPO GROUP SROUPOL GROUPO GROUPOL SGROUPOI GROUPO GROUPO GROUPOL GROUPOL GROUPOL GROUPO GROUPO GROUPO SROUPOL GROUPO GSROUPOL JSROUPOL GROUPO GROUPO GROUPOL GROUPOL COLINTERDOS C cry c 7 COLINTERDOS C cry c 8 COLINTERDS C cry c 9 COUNTEROS O RMO
30. i reg I4 SB DF i data dff 3 EMEN Global Buffer Promation Demotion Logic part m i oOuTi obuf RNO SB LLI E iT data dff 7 SB DF Sort By Name Promotion Demotion W f data dff 2 2 5UM0_0 SB LU Sort By Cell amp iT reg I SB DF Y Global BufFer Promotion Search Global Buffer Demotion Logic GPIG Global RAM Met Group Region Figure 6 10 Global Buffer Promotion Once creating the constraint is done user can save the created constraints in pcf file by clicking the save button on the top panel Then the created pcf file will be automatically added to the current project The legality check of the created constraints can be performed by running the Import P amp R files The adherence of the constraints can be checked out by invoking the floor planner again after running the placer 103 www SiliconBlueTech com iCEcube2 User Guide Silicon y t I amp ses vi Q 4 M Output Global Bx Logic Instance Instance Type Location n a DI dk ibuf SB GB IO Global Buffer Promotion Demotion a Move Logic ul count_inferred_clock_RNILSP7 3 v Add to logic group Logic port IGLOBAL_BUFFER_OUTPUT v Promotion Demotion Sort By Name Global Buffer Promotion Sort By Cell C Global Buffer Demotion Search Logic GPIO Global RAM Net Group Region Figure 6 11 Global Buffer Demotion Modifying the Device Floor Plan after Placement This section explains the steps use
31. in toggle rate estimates In addition the switching frequencies of the Sequential Logic Cells Logic cell in which the flip flop is utilized as well as the Combinational Logic Cells Logic cell in which only the LUT is utilized can be specified on a per domain basis The user can save the current session s input data while closing the Power Estimator Next time when the Power Estimator is open the previous session s input data arepopulated automatically Generating a Bitmap After routing is complete the last step in the flow is to generate the configuration files bitmap for programming the target device Clicking the Bitmap icon in the Flow tab generates the bitmap Changing the Bitmap Options The user can change the Bitmap options by selecting Tool gt Tool Options gt Bitmap 1 SPI Flash Mode Options Checking the option will place the PROM in low power mode after configuration Note This option is applicable only when the iCE FPGA is used as SPI master mode for configuration 2 RAMA4K Initialization Option The device configuration files will not include RAMAK initialization pattern when this option is unchecked 3 Internal Oscillator Frequency Range Depending on the speed of the external PROM this option adjusts the frequency of the internal oscillator used by the iCE FPGA during configuration Note This is only applicable when the iCE FPGA is used in SPI master mode for configuration 61 www SiliconBlueTech com iCE
32. pane as shown in Figure 5 11 This section gives the details of computed frequency summaries and the frequency defining paths for all clocks in the design When a particular clock is selected the paths corresponding to that clock and the path used for frequency computation are displayed in the path summary pane 75 www SiliconBlueTech com iCEcube2 User Guide Silicon Output Timing Analyzer 4 Clock Summary lock Relationship Summary Datasheet Analyze Paths Generate timing report and sdf Ful Screen Mode M Clock Name Worst Slack ps FMAX MH2 TargetFrequency MH2 Failing Path 1 CKA 5620 228 3 100 N A 2 CLKB 9263 51 91 100 1 3 CKC 6722 305 1 100 N A List of Clocks 4 CLKD 6896 322 13 100 N A Save Path Details Sort Results Max Min Pane N E ES ciara Geman stead Start Point EndPoint Slack Delay Skew LaunchClock Capture Clock 1 14 reg I4 LC 5620 7606 4188 CLKA R CLKA R Frequency defining path for CLKA Figure 5 12 Clock Summary Report For every frequency defining path one per clock the following fields are displayed in the Critical Path Summary section Start Point This indicates the pin at which the data path initiates It can be a top level design port input package pin the output of a flip flop or the RDATA output of a RAM block End Point This indicates the pin at which the data path ends It can be a top level design port output package pin the input of a flip flop
33. path internal to the PLL No Compensation mode O Delay Compensation using only the Fine Delay Adjustment Block amp Delay Compensation using the Phase Shifter and the Fine Delay Adjustment Block 7 Using a feedback path external to the PLL The external feedback path will include a divider implemented by the user in logic with a divide by factor of Fine Delay Adjustment Phase Shift Settings Which output of the Phase Shift Block will drive the PLL output Do you want to dynamically control the delay of the Fine Delay Adjustment Block C Yes No Fine delay adjustment setting Enter a value in the range 0 15 6 lt Back Finish Figure 3 7 Selecting the PLL Type and Operation Mode PLL Operation Modes The PLL can be configured to operate in one of multiple modes An Operation Mode determines the feedback path of the PLL and enables phase alignment of the generated clock w r t to the source clock The iCEcube2 software supports the following PLL Operation modes 1 No Compensation mode The PLL can be used for generating the desired output frequency without the ability to control the phase of the generated clock 2 Delay Compensation using only the Fine Delay Adjustment FDA Block In this mode the feedback path is internal to the PLL but traverses through a fine delay adjustment circuit that permits user control of the feedback path delay in 16 steps of 0 15 ns each The delay adjustment can be controlled dyn
34. successfully the iCEcube2 Physical Implementation Software generates Post route Verilog and VHDL models and SDF files in the project dir project name Impl sbt outputs simulation netlist directory Verilog Simulation iCEcube2 User Guide www SiliconBlueTech com 66 Silicon Post Route Verilog netlist top level design name sbt v The post route files used for Verilog timing simulation are as follows Verilog SDF Timing file lt top level design name gt sbt sdf The iCEcube2 software provides Verilog simulation libraries at the following location lt iCEcube2 installation directory gt Verilog Using the above files the design can be simulated in an industry standard Verilog simulator and verified for functionality and timing VHDL Simulation The post route files used for VHDL timing simulation are as follows Post Route VHDL netlist top level design name sbt vhd VHDL SDF Timing file top level design name sbt vital sdf The iCEcube2 software provides VHDL simulation libraries at the following location lt iCEcube2 installation directory gt VHDL Using the above files the design can be simulated in an industry standard VHDL simulator and verified for functionality and timing 67 www SiliconBlueTech com iCEcube2 User Guide Silicon Chapter 5 Timing Constraints and Static Timing Analysis Overview The iCEcube2 Static Timing Analysis STA software is useful for analyzing verifying and debug
35. to its surrounding logic determines the PLL Type The iCEcube2 software supports the following PLL types These PLL type options can be selected on the first page of the wizard as displayed in Figure 3 9 1 General Purpose IO Pad or Core Logic In this scenario the PLL input source clock is driven by a signal from the FPGA fabric This signal can either be generated on the FPGA core or it can be an external signal that was brought onto the FPGA using a General Purpose IO pad The PLL output generated clock is available on the FPGA to drive a global clock network as well as regular routing 2 Clock Pad The PLL input clock source is driven by a dedicated clock pad located in IO Bank 2 a The PLL output generated clock is available to drive a global clock network as well as regular routing The PLL source clock is not available on the FPGA b The PLL output generated clock is available to drive a global clock network as well a regular routing The PLL source clock is also available on the FPGA and can drive a global clock network as well as regular routing 39 www SiliconBlueTech com iCEcube2 User Guide TM Silicon mot en PLL type How will the PLL Source Clock be driven amp General Purpose IO Pad or Core Logic E Clock Pad In addition to the PLL s generated dock will the design use the PLL Source Clock No Yes PLL Operation Modes How will the PLL output be generated Using a feedback
36. types These PLL type options can be selected on the first page of the wizard as displayed in 3 12 1 Select the number of global networks to be driven by the PLL output Setting the value to 1 generates a PLL which drives a single global clock network as well as regular routing Setting the value to 2 generates a PLL which drives two global clock networks as well as two regular routing resources 2 Select one of the following 2 options a General Purpose IO Pad or Core Logic In this scenario the PLL input source clock is driven by a signal from the FPGA fabric This signal can either be generated on the FPGA core or it can be an external signal that was brought onto the FPGA using a General Purpose IO pad b Clock Pad The PLL input clock source is driven by a dedicated clock pad located in IO Bank 2 Bottom bank or IO Bank 0 Top bank If the number of global networks is 2 the source clock of the PLL can be used as is i e without any frequency delay compensation or phase adjustments It is recommended that if the source clock is required on chip this option not be selected 43 www SiliconBlueTech com iCEcube2 User Guide TM Silicon C PLL Module Generator PLL Type Select the number of global networks to be driven by the PLL outputs How will Ehe PLL Source Clock be driven General Purpose IO Pad or Core Logic Clock Pad The PLL source clack will be used on chip without Frequency phasel
37. 2 Searching for objects in the design Selecting this option opens a new window where the user can search pin clock cell pin names as shown in Figure 5 3 Search Design Search Options Search design For type Cell Pin wt Filters in out Using search pattern C1 10 TO Case sensitive inout other Search results Selected to add 1 1D ID Figure 5 3 Searching for object names to constrain 69 www SiliconBlueTech com iCEcube2 User Guide Silicon SDC Constraints in TCE Clock Constraints To enter clock constraints select the Clock tab in the Timing Constraints Editor GUI The following fields are displayed under the Clock tab Enabled Use the Enable tab to enable or disable the constraint Source Enter the pin name or the port name for the clock in the Source field The port or pin name can be selected from the drop down box Alternately the user can search for ports cell pins by using the search option Right clicking in source field gives the option of searching ports cell pins as shown in Figure 5 2 Name Enter the name for the clock in the Name field This is an optional field Period Enter the period in ns for the clock in Period field Waveform Duty cycle for the clock can be specified in the Waveform field with rising and falling time edges of the clock For example when a clock is specified as displayed in Figure 5 4 the following SDC command is generated Timing_Constrai
38. 6777 3667 CLK 32MHz R CLK 32MHz R v Figure 5 188 Analyze Paths using By Slack Select one of the path in Paths summary panel to display the detailed path summary as shown in Figure 5 19 iCEcube2 User Guide www SiliconBlueTech com 82 Clock Summary Clock Relationship Summary Datasheet Analyze Paths Generate timing report and sdf Exit Full Screen Mode By Slack By Paths Point to Point Path Detail b Start GROUPO GROUPOL COUNTER21 Q_13_LC_1_29 5jleout End LED 1 Reference CLK 32MHz Setup Constraint 31250 p Path Slack 20032 p Capture Clock Arrival Time CLK 32MHz R 2 31250 Capture Clock Source Latency 0 Capture Clock Path Delay 0 Output Delay 0 End of path required time ps 31250 Launch Clock Arrival Time CLK 32MHz Rs1 0 Launch Clock Source Latency Launch Clock Path Delay 7130 Clock To Q 365 Data Path Delay 3723 End of path arrival time ps 112 18 Data path delay consists of logic delay 0 level s 2779 ps and routing delay 943 ps Data Path Clock Paths Save Detail Customize Columns Pin Name Model Name Delay AT Edge Fanout GROUPO GROLIPO1 COLINTER21 Q 13 LC 1 2 LogicCell40_SEQ_ 365 7495 RISE 2 Routing Delay 944 I 1001 I LocalMux 0 7495 RISE I 1001 O LocalMux 472 7967 RISE I 1003 I IoInMux 0 7967 RISE I 1003 O IoInMux 472 8438 RISE LED obuf 1 preio D OLIT O PRE IO PIN TYP 0 8438 RISE 1 LED obuf 1 preio PADOUT PRE IO PIN TYP
39. CBR AL O get CLOCKS CLK BJ timingconstraints sde Enabled From Rise From Fall From To Rise To Fall To Through QK A CKB 20 Figure 5 10 False Path Exceptions Multi Cycle Path Exceptions To create Multi Cycle path exceptions select the Multi Cycle tab The following fields are displayed Enabled Use the Enable field to enable or disable the exception Ncycles Enter the number of clock cycles non negative number of the capture clock From Enter the port or pin from which the exception is defined The exception is applied for the data paths launched on both rising and falling transitions Rise From Enter the port or pin from which the exception is defined The const exception rained is applied only for the paths launched on rising transitions Fall From Enter the port or pin from which the exception is defined The exception is applied only for the paths launched on falling transitions To Enter the port or pin up to which the multi cycle exception is defined The exception is applied for the data paths captured on both rising and falling transitions iCEcube2 User Guide www SiliconBlueTech com 74 Silicon Rise To Enter the port or pin up to which the multi cycle exception is defined The exception is applied only for the paths captured on rising transitions Fall To Enter the port or pin up to which the multi cycle exception is defined The exception is applied only for the paths captured on falling t
40. CE65 Device LO4 Device Package CB284 Power Grade L amp Operating Condition Core Voltage V 1 14 Temperature C 70 Add Files Figure 2 13 Specify Additional Files for Place and Route Navigate to the lt iCEcube2 Installation Directory examples blinky and Add blinky pcf file See Figure 2 14 Add Files blinks pef EN Blinky constraints mtl E blinky syn sdc C3 quick start Lis lt se File name blinky pcf Details Files of type Constraint sde scF pcF clb rtcl na Ca Cee Figure 2 14 Add pcf file Import Place amp Route Input Files 21 www SiliconBlueTech com iCEcube2 User Guide The next step is to import the files for Place and Route Double click on Import P amp R Input Files in the Project Navigator See Figure 2 15 Once completed you will see a green check next to Import P amp R Input Files See Figure 2 16 SiliconBlue iCEcube File View Tool Window Help Project New Project Close Project Synthesis Tool amp Add Synthesis Files B Design Files c blinky vhd Constraint Files blinky syn sdc e Launch Synthesis Tool P amp R Flow Gef Select Implementation quick sta Quick start edf quick start scf 5 Add P amp R Files Design Files IP Design Files Constraint Files blinky pcf Run All z Import P amp R Input Files Run Placer Run Router Generate Bitmap Output Files Reports Bitmap Sim
41. CEcube2 Project Navigator Within the Synopsys design environment assign your Logic Synthesis Timing and Pin constraints 3 Perform Placement and Routing using the iCEcube2 place and route tools iCEcube2 also supports physical implementation tools such as floor planning allowing users to manually place logic cells and IOs 4 Perform timing simulation of your design using an industry standard HDL simulation tool The files necessary for simulation are automatically generated by the iCEcube2 Physical Implementation tools after the routing phase 5 Perform Static Timing Analysis using the iCEcube2 static timing analyzer 6 Generate the device programming and configuration files from the iCEcube2 Physical Implementation tools 7 Program your device using the device programming hardware provided by Silicon Blue Technologies 7 www SiliconBlueTech com iCEcube2 User Guide Silicon Chapter 2 Quick Start Guide This chapter provides a brief introduction to the iCEcube2 design flow The goal of this chapter is to familiarize the user with the fundamental steps needed to create a design project synthesize and implement the design generate the necessary device configuration files and program the target device Detailed information on tool features and usage is provided in subsequent chapters Creating a Project Starting the iCEcube2 software for the first time you will see the following interface shown in Figure 2 1 Sil
42. CLK 32MHz 18367 77 62 32 counter power CLK_32kHz 995527 223 54 1 lt gt CELW Critical Path 1 Poin ta og L E l i End Point Sta J I A GROUPO GROUPO1 COUNTE RISE LED 0 Selected Critical path J Customize Columns J v Data Path Report Save Detail Customize Columns Pin Name GROUPD GROUPO1 COUNTER21 Q 12 LC 1 2 4 Routing Delay LED obuf 0 preio D OUT LED obuf 0 preioJPADOUT LED obuf D iopad DIN IO PAD LED obuf 0 iopad PACKAGE PIN IO PAD LED 0 counter power Model Name LogicCelld SEQ PRE IO PIN TWP PRE IO PIN TYP Delay AT Edge Fan 365 7495 RISE 2 1644 _ 0 N 9138 RISE 1 411 9549 RISE 1 0 x 9549 RISE 1 3334 12883 RISE 1 0 N i 12883 RISE 1 Routing delay gt 9 Figure 5 14 Example of Detailed Path Summary for Frequency Computation Detailed Path Report Pane gives the routing delays and delay of each cell involved in the path and the slack values For detailed analysis of Timing Path Reports refer to Detailed Timing Path section The detailed timing path report can be saved in text format by using Save Detail Option C ProjectMavigatorZ Pin Mame Model Mame Delay AT Edge Slack Fanout I S iS S IS kK Strekch HHHHBBH Move Move Down Figure 5 15 Customize Report Options iCEcube2 User Guide www SiliconBlueTech com 78 Silicon Customize Colum
43. Celld SEQ M 0 3508 RISE Clock Output uni clk 0 O0 LC 1 15 5jlcout LogicCelld SEQ M 715 4224 RISE H Routing Delay 2039 Clock Output uni clk 0 cb gb OJUSER SIGNAL TO GL ICE GB 0 6262 RISE Clock Output uni clk 0 cb gb OjGLOBAL BUFFER OUT ICE GB 228 6491 RISE 4 Routing Delay 578 GROUPO GROUPO1 COUNTER16 Q 15 LC 5 26 7 dk LogicCelld SEQ M 0 7069 RISE si EI Figure 5 17 Detailed Path Summary Setup to Clock Path Analyzing Constrained Paths Clicking on the Analyze Paths button allows the user to query paths in the following ways 1 Querying for the paths based on the Slack value 2 Querying for the paths based on the Paths Start End Points 3 Querying for the combinational paths based on the Start End Terminals By Slack The By Slack option in the Analyze Paths window allows the user to list out all the paths in the design with increasing slack values User can customize the number of paths reported by modifying the value in Limit Report to n Paths option as shown in Figure 5 18 The Advanced Options section helps the user to customize the paths reported The first option in this section is useful to limit the paths reports based on Launch Clock Capture Clock and their phases The second option helps in limiting the results reported based on the number of paths per start point and number of paths per end point 81 www SiliconBlueTech com iCEcube2 User Guide
44. Clock Source Latency 0 Launch Clock Path Delay 1880 Clock To Q 365 Data Path Delay 836 End of path arrival time ps 3082 So from the timing report Slack 10000 1880 441 1880 365 836 8357ps Detailed Clock Path and Data Path delays The Launch and Capture clock path delays Data path delays shown in Slack Computation section are reported in detail here The detailed report is shown below The model name indicates the type of cell involved in the path For example the cells with PRE_IO_GBUF are the IO global buffers and the cells with LOGIC_CELL are the LUTs Also the report gives the details of the LUT configuration mode Cells used for routing are defined using I__ The delay column gives the amount of time iCEcube2 User Guide www SiliconBlueTech com 92 Silicon consumed by each cell unit AT gives the incremental time delay for the path upto the mentioned cell Edge column gives the RISE FALL delay edge of the cell The number in Fanout column gives the Fanout for the mentioned cell The path delays reporting order is Launch Clock Delay Data Path Delay and Capture Clock Delay Clock network delay is the delay from the clock port to the registered clock pin In this section first path reported is detailed clock path report for the launch clock Launch Clock Path pin name clk clk_ibuf_iopad PACKAGEPIN in clk ibuf iopad DOUT clk ibuf preiogbut PADSIGNALTOGLOBALBU
45. Condition Device Info NT DeviceFamily iCE40 Device LP8K Device Package CM225 Power Grade Operating Condition Core Voltage V 1 14 Temperature C 70 Figure 3 4 Modifying the Device Selection Operating Conditions The following Figures 3 5 and 3 6 displays the Device Options Wizard based on the selected device family 35 www SiliconBlueTech com iCEcube2 User Guide Device Options Device Device Family Gz v Device LP8K v Device Package CM121 ha Operating Condition Ambient Temperature in degrees Celsius Range Best Typical Commercial 0 25 Core Voltage Voltage Tolerance Range Typical Hi 5 datasheet def aul v 1 2 IOBank Voltage v topBank 1 8 bottomBank leftBank 1 8 rightBank Perform timing analysis based on COBest COTypical Figure 3 5 Device Options Wizard for iCE40 Family Device Options Device Device Family cees v Device L01 Device Package CB81 Power Grade L Operating Condition Ambient Temperature in degrees Celsius Range Best Typical Commercial 0 25 Core Voltage V Voltage Tolerance Range Best Typical S datasheet def aul v 1 26 1 2 Perform timing analysis based on OBest COTypical Figure 3 6 Device Options Wizard for iCE65 Family iCEcube2 User Guide www SiliconBlueTech com 36 Silicon In order to specify a suitable target Device the following steps need to be performed
46. ET B device pins Loading a configuration image during regular operation is known as the Warm Boot configuration process The Warm Boot configuration process is accomplished through the use of the Warm Boot primitive Please refer to the 1CE65 Technology Library document for additional details on instantiation of the Warm Boot primitive Once the Single Image or Multiple Images mode is selected additional information on the configuration files should be provided by selecting the Image File Settings button This brings up the graphical user interface displayed in Figure 4 20 below If Single Image mode was selected only Image 0 data needs to be specified else data for multiple images should be provided The image file data required for each image is as follows Start Address This is the starting address location in the external SPI Flash PROM that the configuration image is loaded into It is a 24 bit Hexadecimal address that is always zero for the Single Image mode and non zero for the Multiple Images mode In addition for the case of multiple images the memory space for all images should be non overlapping Hence the Start Address field is populated by default with recommended Start Address values iCEcube2 User Guide www SiliconBlueTech com 64 Silicon Configuration File This field allows the user to specify the location of the bitmap configuration file the contents of which are written to the memory starting at the memory location sp
47. FA BTN3 ibuf RNI48D LC 1 5 6 in3 LogicCell40 SEQ 0 1 BTN3 ibuf RNI4BD LC 1 5 6jkout LogicCelM0 SEQ 472 T Routing Del l PMOD LEFTROJ icCeld0 SEO Highlight in Floor planner Highlight Path In Floor planner 1 Sul tA Figure 5 25 Pin Cross Probing between Timer and Floor Planner iCEcube2 User Guide www SiliconBlueTech com 88 Path Detail pa Data Path Delay 7054 I Setup Time 346 Capture Clock Path Delay 1628 1 Setup to Clock 5772 2 gt LIA Data Path Clock Paths Save Detail Customize Columns Pin Name Model Name Delay AT Edi BTN3 icetest 0 0 RISE S BTN3_ib IO PAD 0 0 RISE BTN3 ib IO PAD 800 800 RISE T BTN3_ib PRE IO PIN TYP 0 800 RISE E BTN3 ib PRE IO PIN TYP 365 1165 RISE Routing Delay 1932 T BTN3 ib LogkCeld0 SEQ 0 3098 RISE 5 BTN3 ib LogCel40 SEQ 472 3569 FALL Routing Dela 3484 Locate in Floor planner Un highlight in Floor planner Un hight All A a Figure 5 26 Path Cross Probing between Timer and Floor Planner Detailed Timing Report A detailed timing report in text format is generated after running the Timing Analyzer This section explains about the timing report file generated by iCEcube2 STA tool and how to interpret them iCEcube2 STA can report timing paths at three corner cases Best Typical and Worst Various Kinds of Summary Reports generated by iCEcube2 STA tool are 1
48. FFER clk_ibuf_preiogbuf GLOBALBUFFEROUTPUT I 8 1 I 8 O I 9 I I 9 O I 10 I I 10 O reg 0 LC 1 4 0 clk model name delay cumulative edge Fanout delay i2c top 0 0 RISE 1 IO_PAD 0 0 RISE 1 IO_PAD 800 800 RISE 1 PRE_IO_GBUF 0 800 RISE 1 PRE_IO_GBUF 502 1302 RISE 1 gio2CtrlBuf 0 1302 RISE 1 gio2CtrlBuf 0 1302 RISE 1 GlobalMux 0 1302 RISE 1 GlobalMux 335 1637 RISE 1 ClkMux 0 1637 RISE 1 ClkMux 243 1880 RISE 1 LogicCelld0 SEO MODE 1000 O 1880 RISE 1 Here clk is the launch clock The delay from port clk to Launch Flop clock pin reg 0 LC 1 4 0 cIk is shown here The clock starts from clock port traverse through global buffer and reaches Launch Flop Clock Pin at 1880ps Second section is the Data Path Delay Data delay is the delay from Flop output pin reg 0 LC 1 4 0 Icout to Flop input pin reg 1 LC 1 4 1 in3 From the report the data path delay is 3082 2246 836ps Data path in name model name delay cumulative slack edge Fanout delay reg 0 LC 1 4 O Icout LogicCelld0 SEQ MODE 1000 365 2246 8357 RISE 1 I 15 I LocalMux 0 2246 8357 RISE 1 I 15 O LocalMux 472 2717 8357 RISE 1 I 16 I InMux 0 2717 8357 RISE 1 I 16 O InMux 365 3082 8357 RISE 1 reg 1 LC 1 4 1 in3 LogicCelld0 SEO MODE 1000 0 3082 8357 RISE 1 Third section is the Clock path delay of Capture clock The clock delay is the delay from clock port to registered latch flop clock pin From the report this delay is 1880ps Capture Clock Path pin name clk clk
49. H2 3058 counter power CLK 32kHz R Figure 5 17 Data Sheet Report Select the Setup to Clock path to display the detailed path report as shown in Figure 5 17 iCEcube2 User Guide www SiliconBlueTech com 80 Clock Summary Clock Relationship Summary Datasheet Analyze Paths go M Path Detail Save Datasheet Setup to Clock Clockto Out PadtoPad Data Port Clock Port Delay ps Clock Reference Phi 1 LOAD CLK 32kHz 3941 counter power CLK 32kHz 2 LOAD CLK 32MHz in 3880 CLK 32MHz R ja m Generate timing report and sdf Exit Full Screen Mode Data Path Delay 10569 Setup Time 441 Capture Clock Path Delay 7069 Setup to Clock 3941 Setup to Clock path Summary CETE DataPath ClockPaths Capture Clock Path Pin Name Model Name Delay AT Edge CLK 32kHz counter power 0 0 RISE CLK 32kHz ibuf iopad PACKAGE PIN IO PAD 0 0 RISE CLK 32kHz ibuf iopad DOUT IO PAD 800 800 RISE CLK_32kH2_ibuf_preio PADIN PRE_IO_PIN_TYPE_ 0 800 RISE CLK 32kHz ibuf preio D IN D PRE IO PIN TYPE 365 1165 RISE Routing Delay 2343 I 914 I Odrv4 D 1165 RISE I_914 0 Odrv4 502 1667 RISE I 915 I Span4Mux v 0 1667 RISE 1_915 0 Span4Mux v 502 2169 RISE I 916jI SpandMux v 0 2169 RISE 1_916 0 Span4Mux v 502 2672 RISE I 9171 LocalMux 0 2672 RISE I 917 0 LocalMux 472 3143 RISE I 918 I InMux 0 3143 RISE I 918 O InMux 365 3508 RISE Clock Output uni dk 0 0 LC 1 15 5jino Logic
50. I I2054 Placement of design completed successfully Information regarding placement H Add P amp R Files Run All I2076 Placer run time 12 5 sec e g Clock Summary Import P amp R Input Files Run Router C SBTools Mayl72011 Trunk sbt backend bin vin32 optipacker exe C Generate Bitmap SBTools Mayl72011 TrunkXsbt backendYidevicesVICES dev Output Files C SbtTools examples blinky quick_start quick_start_Inpluntisbti netlist oadb icetest package CB284 outdir H Reports Pla ce Com Dlete 1001s examples blinky quick_start quick start Implmnt sbt outputs packer DRC_only translator C Bitmap XSBTools Mayl72011 Trunk sbt_backend bin sdc translator tcl src sdc file Simulation Netlist p E sa T 1 A x mad 1 em 1 rui i qi ck_st E f mi ck_st i omui pod gi 1 Tanp xe ead de UH de_ f le i C SbtTools examples blinky quick start quick start Implmnt sbt outputs packer icetest sbt sdc Device Operating Condition SiliconBlue Tech Packer 7 i i E Device Info Release 2011 03 16214 DeviceFamily iCE65 Build Date Device L04 Device Package CB284 Begin RENE ES Power Grade L ipee vini NASE Operating Condition ee au ra used logic cells 94 e ran aan Design Rule Checking Succeeded emperatre DRC Checker run time 0 sec packer succeed Figure 2 17 Place complete View Floorplanner At this point since placement has been completed you can view the placement of the design by
51. O GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GROUPO GPIO i3RLIPOT i3R COLIPOT SROUPOL mROUPOL mROUPOL mROUPOL mROUPOL IM MUS BbRPy 9 17 O_ mROUPOL mROUPOL mROUPOL GROUPOL SROUPOL GSROUPO1L mROUPOL mROUPOL mROUPOL GREOLIPOT mROUPOL mROUPOL mROUPOL mROUPOL Global Murpuk COUNTEROG RNO S COUNTEROSG O 6 COLINTEROS C cry_c 6 COUNTEROG O RMO S5 COUNTEROG O F COLINTERD6 C cry e 7 COUNTEROG O RMO 7 COLINTERO6 ofa COLINTERO6 CQ cry c 8 COLINTERO6 CQ RNO 8 COLINTERDS 9 COLINTEROS C cry_c 9 COLINTEROS6 C RAO COLINTERO6 O 10 COUNTERO6 O cry c 10 COLINTERD6 CQ RNO 10 COUNTERO6 O 11 COUNTERO6 O cry c 11 COUNTERO6G G RNO 11 COUNTERO6 O 12 COUNTERO6 O cry c 12 RAM Met Group Figure 4 7 Sort by Cell Option Instance Type SB LLIT4 SB DFF SB CARRY SB LLIT4 SB DFF SB CARRY SB LLIT4 SB CARRY IM SB DFF SB CAREY SB LLIT4 5B6_DOFF SB CARRY SB LLIT4 SB DFF SB CAREY SB LLIT4 SB DFF SB CAREY SB LLIT4 SB DFF SB CAREY Location a 17 17 17 17 17 17 17 17 18 18 18 m m Jo D D xD D D D iD n iu b Du ko ko k ROO oC Qd O P3 MuE MTM 0 QD oO OC o a C Cho Ch GO JD o D D ox n n an Select Lock option to fix the instance location in the floor planner view Flo
52. OUNTER19 Q 2 LC 2 17 LogicCelld SEQ MODE 1000 137 9017 RISE 2 GROUPO GROUPOD COUNTER19 Q 3 LC 2 17 LogicCell40_SEQ MODE 1000 0 9017 RISE 1 GROUPO GROUPOO COUNTER19 Q 3 LC 2 17 LogicCelld SEQ MODE 1000 137 9154 RISE 2 GROUPO GROUPOD COUNTER19 Q 4 LC 2 17 LogicCell40_SEQ MODE 1000 0 9154 RISE 1 GROUPO GROUPOO COUNTER19 Q 4 LC 2 17 LogicCelld SEQ MODE 1000 137 9290 RISE 2 GROUPD GROUPDD COUNTER19 Q 5 LC 217 LogicCelld SEQ MODE 1000 0 9290 RISE 1 GROUPO GROUPOD COUNTER19 Q 5 LC 2 17 LogicCell40_SEQ MODE 1000 137 9427 RISE 2 E Routing Delay 365 GROUPO GROUPOD COUNTER19 Q 6 LC 2 17 LogicCeld0 SEQ MODE 1000 0 9793 RISE 1 Figure 5 21 Detailed Path Summary Point to Point The Point to Point in Analyze Paths window allows the user to analyze the routed timing delays of the combinational paths that exists between the specific Start Source and End Destination Terminals No timing constraints are necessary to report these combinational path delays All the terminals of the design are shown in Terminals pane User can search for specific type of terminal by using the Find Terminal option User can select the Start and End points from Terminals pane and can move them to From and To options pane as shown in Figure 5 22 The terminals which are used in From or To options can be a terminal of a Port LogicCell RAM or PLL Point to Point delay report will be generated for the set of paths
53. Select I mplementation quick_ amp Add P amp R Files project Run All D Import P amp R Input Files D Run Placer D Run Router Generate Bitmap Output Files Reports Bitmap Device information and Simulation Netlist p iti operating conditions are Device Info DeviceFamily iCE65 now set Device LO4 Device Package CB284 Power Grade L Operating Condition Core Voltage Temperature C Figure 2 4 iCEcube2 Project Navigator View after Completing Project Set up Synthesizing the design After a successful project setup Double Click on the Launch Synthesis Tool icon in the project navigator window See Figure 2 5 This will bring up the Synopsys Synplify Pro synthesis tool s graphical user interface See Figure 2 6 iCEcube2 User Guide www SiliconBlueTech com 12 W SiliconBlue iCEcube 2 Output Output Project Project Directory is C SbtTools examples blinky quick start New Project Open Project Close Project Synthesis Tool iB Add Synthesis Files Design Files blinky vhd Constraint Files Bila ceed Double click on Launch m er Launch Synthesis Tool n LL Synthesis Tool gt Select Implementation quick_ H Add P amp R Files Run All Import P amp R Input Files Run Placer Run Router Generate Bitmap Output Files Reports Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 Device L04 Device Package CB284 Power Gr
54. U2 pwm SB_DFFER H i nxm pwm 3 US U0 ram SB DFFN i U4 count reg RNO 3 SB LUT4 amp T Ut count_RNO O SB LUT4 W Add Logic To Group H i nxm pwm 2 US U2 pwm SB_DFFER H nxm pwm 3 US U2 un2 SB LUT4 Group Name H i nxm pwm 3 US U2 pwm SB DFFER r 1 CE LE nxm pwm 3 US U2 U M a I nxm pwm 2 us uo Move H nxm pwm 3 US UZ Add to logic group Ok H i nxm pwm 1 US rd H i nxm pwm 1 US U2 r Global Buffer Promotion Demotion i nxm pwm 1 US U1 f i U4 count reg 1 Sort By Name i U3 count_reg 3 Sort By Cell i nxm_pwm_3_US U2 c Search H i nxm_pwm_3_US U2 H i nxm_pwm_1_US U2 ef Pin Permutation qi nxm pwm 1 US U1 pwmn o cor i Ut count 3 SB DFFS H i nxm pwm 2 US U2 pwm SB DFFER H i nxm pwm 3 US U0 ram SB DFFN v Logic GPIO Global RAM Net Group Region Figure 6 4 Adding Logic Elements to a Group User can also delete the elements from logic elements from a group Right clicking on any logic element in the Group tab gives the user the option to delete element from the logic group as shown in Figure 6 5 97 www SiliconBlueTech com iCEcube2 User Guide Silicon iCEcube2 User Guide Gas Create Logic Group Group Remove From Logic Group Figure 6 5 Removing Logic Elements from a Group www SiliconBlueTech com 98 Silicon Region Constraints The Region Constraints enable the user to constrain a Group to a physical region on the device
55. View The Package View tool Figure 4 10 displays a pin map of the implemented design in the targeted package and allows the user to change Pin properties such as Location and IO Standard Note that these properties can also be modified from the Floor Planner and the Pin Constraints Editor A Port pane is available and it permits the user to select a design pin and highlight it in the package view A World View pane provides a view of the entire package and can be used to navigate the package view when the Zoom In factor is high Mousing over a pin in the package view provides information on its usage whether the pin is available the pin number and the pin name The package pins assigned to the user s design ports are depicted in green and in general can be re assigned to different locations iCEcube2 User Guide www SiliconBlueTech com 56 SiliconBlue iCEcube File Edit View Tool Window Help d AR A o A e Project Name dpcm debug Bx 4 Design Flow Port f Route muxsel 1 0 e Bitmap 4 fvdat 3 0 4 Tools B fvdat 0 dV Clock Constraints Editor 35 fvdat 1 di Pin Constraints Editor fvdat 2 iV Floor Planner i vt Package View E Imemout 7 0 I Power Estimator vt7 5 N Programmer u 7 0 di 7 0 y 7 0 ulat 35 irst 35 ylat calcen World View Files 4 Input Files dpcm bfpga edf dpcm bfpga pcf Constraint Files 4 Output Files 4 packer dpcm info log dp
56. _ibuf_iopad PACKAGEPIN in 93 model name www SiliconBlueTech com delay cumulative edge Fanout 0 0 RISE 1 0 0 RISE 1 iCEcube2 User Guide Silicon clk_ibuf_iopad DOUT IO PAD 800 800 RISE1 clk ibuf preiogbut PADSIGNALTOGLOBALBUFFER PRE IO GBUF 0 800 RISE1 clk_ibuf_preiogbuf GLOBALBUFFEROUTPUT PRE_IO_GBUF 502 1302 RISE1 I 8 1 gio2CtrlBuf 0 1302 RISE1 I 8 O gio2CtrlBuf 0 1302 RISE1 I 9 I GlobalMux 0 1302 RISE1 I 9 O GlobalMux 335 1637 RISE1 I 10 I ClkMux 0 1637 RISE1 I 10 O ClkMux 243 1880 RISE1 reg 1 LC 1 4 1 clk LogicCell40_ SEO MODE 1000 0 1880 RISE1 Chapter 6 Physical Constraints in iCEcube2 Physical constraints in iCEcube2 can be provided at 2 different stages of the design flow before Placement and after Placement Details on both approaches are provided below Specifying Physical Constraints after Design Import and Before Placement After importing the design into iCEcube2 the user can constrain the placement of the design to desired locations on the physical device This can be specified through the following physical constraints Absolute Placement Relative Placement IO FF Merge Global Promotion Demotion Absolute Placement After importing the design into iCEcube2 using Import P amp R Files the user can set a placement location for all the instances like LUTs DFFs RAMs IOs and Carry etc These constraints can be applied in Floor Planner which can be invoked through Tools FloorPl
57. ade L Operating Condition Core Voltage Temperature C Figure 2 5 Launch Synthesis Tool 13 www SiliconBlueTech com iCEcube2 User Guide Synplify Pro D 2009 12S Early Access 2 C SbtTools examples blinky quick_start quick_start_syn prj Sel B re File Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help J amp x B sg 355i 5a MV RSKFEO Sw Oe Fs y c A ANA us s amp Ej oo RRS oo amp Synplify Pro Ready quick start Implmnt Silicon Blue iCE65 iCE65L04 CB284 L B Open Project Implementation Directory R Close Project G 4d blinky vhd work du Add File Eg eZ Constraint FEB blinkly_syn sde Gf Change File m quick start Implmnt Directory Directory Directory Directory Directory identify log 152 bytes log File quick start edF 119 kB Edif Netlist 17 45 quick start fse 0 bytes fse File 17 45 quick start htm 348 bytes htm File 17 45 r1 View Log quick start scf 2 kB scf File 17 45 8 quick start srd 14 kB Netlist 17 45 i Pall quick start srl 6kB Netlist RTL 17 45 WW quick start srm 121 kB Netlist Gate 17 45 Auto Constrain quick start srr 47 kB srr File 17 45 8 quick start srs 6 kB Netlist RTL 17 45 quick start szr 17 kB szr File 17 45 quick start tlq 869 bytes tlg File 17 45 quick start prepass srd 7 kB Netlist 17 45 is Add Implementation 19 Implementation Options BR Add P amp R Implementation
58. age C8284 Power Grade L Operating Condition Core Voltage V 1 14 Temperature C 70 Constraint Selector Clock Generated Clock Input Delay Output Delay Max delay False Path Muki cycle Figure 5 1 Timing Constraints Editor iCEcube2 User Guide www SiliconBlueTech com 68 Silicon The user can select the type of constraint in Constraint Selector tab as displayed in Figure 5 1 When invalid constraints are specified the TCE editor displays them in RED color and does not forward annotate the constraints to the Placer Router STA tools Searching for Pins Ports in the design The Timing Constraints Editor provides the ability to search for design objects to which constraints are be applied Right click on the appropriate field in TCE displays the option to Search Design as displayed in Figure 5 2 File View Tool Window Help E MAE EERST B Project Name test_accum a x untitled0 sdc 4 Project Flow E Enabled Source Search Design 4 Specify Synthesis Input Files Design Files EE Add Row Constraint Files Delete Row e Launch Synthesis Tool 4 P amp R Input Files 4 ef Select Implementation test accum edf test accum scf Specify Additional Files e Import P amp R Input Files e Run Placer e Run Router e Generate Bitmap Clock Generated Clock Input Delay Output Delay Max delay False Path Multi cyde Period ns Waveform ns Figure 5
59. ailed path summary report provides the following details as shown in Figure 5 14 Path Detail Gives the Timing Start Point Timing End Point reference clock used for slack computation and the slack value Data Required Time Gives the details of clocks used for computing the required time including the cycle adjust time between the launch clock and the latch clock Data Arrival Time Detailed path report for computing the data arrival time starting from the launch clock edge 77 www SiliconBlueTech com iCEcube2 User Guide Clock Summary Clock Relationship Summary Datasheet Analyze Paths Path Detail Start GROUPD GROUPO1 COUNTER21 Q 12 LC 1 29 4 lcout End LED 0 Reference CLK 32MHz Setup Constraint 31250 p Path Slack 18367 p Capture Clock Arrival Time CLK 32MHz R amp 2 31250 Capture Clock Source Latency Capture Clock Path Delay 0 Output Delay 0 End of path required time ps 31250 Launch Clock Arrival Time CLK 32MHz R amp 1 0 Launch Clock Source Latency Launch Clock Path Delay 7130 Clock To Q 5 Data Path Delay 5388 End of path arrival time ps 1288 Generate timing report and sdf Exit Full Screen Mode y Path Start End Points Required Time Computation Arrival Time Computation 3 Data path delay consists of logic delay 0 level s 3744 ps and routing delay 1643 ps Customize Columns Clock Name Worst Slack ps FMAX MH2 Target F 1
60. amically through signals connected to the PLL or iCEcube2 User Guide www SiliconBlueTech com 40 Silicon it can be fixed i e once configured the delay contributed by the delay block can only be changed upon re programming the FPGA with a different bit configuration 3 Delay Compensation using the Phase Shifter and the Fine Delay Adjustment FDA Block The Phase Shifter provides 4 outputs corresponding to a phase shift of 0 degrees 90 degrees 180 degrees or 270 degrees In addition this feedback path provides additional delay adjustment through the FDA block 4 Delay Compensation using a feedback path external to the PLL The feedback path traverses through FPGA routing external to the PLL followed by the Fine Delay Adjustment FDA Block Hence in effect 2 delay controls are available the external path for coarse adjustment and the FDA block for fine delay adjustment PLL Input Output Frequency Input frequency Mhz Output frequency Mhz Others Create a LOCK output port Create a BYPASS port that will bypass the PLL reference dock to the PLL output port Mate that the PLL requires re4ocking when the BYPASS signal is de asserted for all modes other than the Ho Compensation mode Low Power Mode Enable latching of PLL output dock iCEGate Mate that the PLL requires reJocking after the latch signal is de asserted when the feedback path is external to the PLL Enable latching of PLL source dock
61. and recheck Locked Box PMOD_B2R_J30 1 Output Y20 Bottom K E PMOD_B2R_J30 2 Output Y18 Bottom S PMOD_B2R_J30 3 Output Y19 Bottom S PMOD_B2R_J30 4 Output Y17 Bottom s PMOD BOR 313 1 Output Hi4 Top S PMOD BOR J13 2 Output Top S PMOD BOR 313 3 Output Top s PMOD BOR 313 4 Output Top S PMOD B3B 338 1 Output K PMOD_B3B_J38 2 Output S PMOD B3B J38 3 Output S PMOD B3B 338 4 Output K PMOD_B1T_J20 1 Output S PMOD B1T J20 2 Output S PMOD B1T Je0 3 Output J DAP DAIT 1908 47 Figure 2 29 Pin Constraints Editor Physical constraints sawe as Physical constraints File Tools examples blinky quick_start quick_start_Implmntisbt constraint icetest pef sbt pcr eer Figure 2 30 Pin Constraints Editor Chapter 3 iCEcube2 Project Setup and Navigation Introduction This chapter describes the features of the iCEcube2 Project Manager and how to set up a design Project The primary functions of the Project Manager include project setup launching the Synopsys Synplify Pro tools for synthesis placing and routing the design and launching the software required to Program the target device iCEcube2 User Guide www SiliconBlueTech com 32 Silicon This chapter assumes that the reader is familiar with the New Project creation process as described in Chapter 2 Quick Start Project Manager GUI Figure 3 1 below
62. anner Constraining Logic or RAMs In the Floor Planner the logic or RAM instances can be placed by dragging the instances from the instance menu to Floor Planner The user can also perform the same action by the following steps 1 Select a logic RAM instance from the instance menu and right click on it 2 Select the Move Option 3 Go to the desired location in the Floor Plan right click and select the option PUT iCEcube2 User Guide www SiliconBlueTech com 94 Silicon The above steps are shown in Figure 6 1 Once constraining of all instances is done you can save these constraints in a PCF file by selecting the Save button on the top panel Rerun the placer to get the constraints honored Logic Instance Instance Type Location H iT data_obuf RMO 3 SB LLIT4 H iT data obuf RMO 2 SB LLIT4 dT data obuf RNMO 4 SB LLIT4 H iT data obuf RMO 0 SB LLIT4 iT data 9 0 D RADDR reg 58 DFFE SB_LUT4 data obuf RMO 1 Add to logic group Global Buffer Promotion Demotion Sort By Mame Sort By Cell Search EH af Pin Permutation Logic GPIO Global RAM Met Group Region EH Figure 6 1 Absolute placement of Logic Cells RAMs Constraining lOs IOs can be constrained at desired locations by invoking the pin constraint editor box This can be invoked by a right click on the IO and selecting move option In the pop up Pin Constraint editor box user
63. ate Bitmap IP Exparter Figure 7 4 Run Complete Flow 5 Launch the Floor Planner from Tool Floor Planner and can view the placed IP on the FPGA If the user wants to do any modification to the placement he can do the same by dragging the placed instances into required location Lock the instance using the option showed after a right click on the instance Save the placement using File Save Floor Planner and rerun Run All 109 www SiliconBlueTech com iCEcube2 User Guide Figure 7 5 Placed IP Instances 6 Double click on IP Exporter to save the IP in EDF format Browse to a location on the pop window and save the EDF file By default the EDIF file is saved in PrjName PrjName Implmnt sbt IP location The saved IP EDF file contains the locations of all the instances W SiliconBlue iCEcube2 Output W File view Tool Window Help DA Bases Project Name IP Creation Project 8 x amp Project Save in C3 IP New Project Open Project Close Project Synthesis Tool Add Synthesis Files Design Files Constraint Files e Launch Synthesis Tool P amp R Flow GY Select Implementation IP_ IP_Creation_Project edf IP_Creation_Project scf Add P amp R Files Design Files Constraint Files Run All e Import P amp R Input Files e Run Placer l e Run Router File name Exported IP edi Please enter the file name My Recent Documents e Generate Bitmap M
64. be2 User Guide www SiliconBlueTech com 10 Silicon 8 Click Next to go to the Add Files dialog box shown in Figure 2 3 You will be prompted to create a new project directory Click Yes 9 In the Add Files dialog box navigate to iCEcube2 installation directory examples blinky Highlight the following files blinky vhd blinky syn sdc Select each file and click gt gt to add the selected file or click gt gt gt to add all the files in the open directory files can be removed using lt lt and lt lt lt to your project Click Finish to create the project The SDC file is a Synopsys constraint file which contains timing constraint information Add Files blinks hd blinky svn sdc S blinks pef Li blinky constraints meel My Computer quick start File name blinky syn sdc Files of type All Files Figure 2 3 New Project Wizard Add Files dialog box After successfully setting up your project you will return to the following iCEcube2 Project Navigator screen shown in Figure 2 4 11 www SiliconBlueTech com iCEcube2 User Guide W File view Tool Window Help Project Name quick_start Output E Project Directory is C SbtTools examples blinky quick start New Project Open Project Close Project Synthesis Tool Add Synthesis Files Design Files blinky vhd Constraint Files blinky syn sdc Synthesis input files Launch Synthesis Tool PBR Flow are now added to D
65. can set the Pin location IO standard and pull up type for the IO as shown in the Figure 6 2 Also user can constrain all the IOs in the Pin Constraint Editor or by selecting them and dragging them to IO locations in the Floor Plan View or the Package Viewer Detailed descriptions of the Pin Constraints Editor and Package View can be found in Chapter 4 iaPIO Bx Logic Instance Instance Type Location data 0 data abuf O ON address 1 address ibu data 7 data abuf 7 address 0 address ibu read en read en ibufF data 5 data abuf amp 5 data 5 data abuf 5 datali data abuf 1 address 2 address ibu data 4 data obuf 4 T sort By Mame IO Standard ENIM M address 5 address ibu Sort By Cell data 3 data abuf 3 address 4 address ibu data 2 data abuf 2 address 3 address ibu E g Pin Constraint El EE Edit Pin Constraint E ODnOOBOOBOBOOOSBH Port Mame data 0 Add to logic group IO Mame data obuf Merge Unmerge FF Fin Location A7 Fe Fe Fe E Pull Up Search E E E Logic GPIO Global RAM Met Group Region Figure 6 2 Absolute Placement of IOs Relative Placement Relative Placement Constraints helps the user to group logic and to fix the placement of the grouped logic cells relative to each other 95 www SiliconBlueTech com iCEcube2 User Guide Silicon Group C
66. cm sbt mtcl 4 router dpcm route dpcm rt log dpcm rt usage log 4 bitmap ICE55L04 C8284 dpcm bitmap bin iCE65L04 CB284 dpcm bitmap hex dpcm bitmap int hex Figure 4 10 Package View The Package Pin Legend Figure 4 11 shows the color coding of the various pins available on the selected package identifying the functions of the pins For example power VCC VCCIO GND VPP VDDP VREF user IO and other special purpose pins which provide access to the low skew global network GBIN SPI SI SP SO SPI SCK SPI S53 B GND VCC VCCIO CDONE CRESET B VPP VDDP VREF TCKE TDI TDO TMS TRST B Figure 4 11 Package Pin Legend Editing Pin Properties Moditying a pin s placement is accomplished either by clicking the pin and dragging it to a desired empty location or by invoking the Pin Constraints dialog box Figure 4 12 using the 57 www SiliconBlueTech com iCEcube2 User Guide Silicon Right Mouse Click gt Edit Pin Constraint In addition to its location the pin s IO standard and Pull Up resistor can also be configured from this dialog Port Mame Imemout_7 Pn Location cm cm IO Standard SB_LVCMOS Pull Up Figure 4 12 The Pin Constraints dialog box invoked from the Package View Undesired pin location changes can be reverted back to their initial state using the Edit gt Undo menu Once all changes are complete the new pinout can be saved by clicking File gt Save Package View
67. cube2 User Guide Silicon 4 Other a Enable Warm Boot This option enables the Warm Boot functionality provided the design contains an instance of the SB WARMBOOT primitive and the Multiple Image Files are specified as explained in the section Programming the Device b Set security Selecting this option ensures that the contents of the Non Volatile Configuration Memory NVCM are secure and the configuration data cannot be read out of the device SPI Flash Mode Options In SPI Flash mode place PROM in low power mode after configuration RAMAK Initialization Options Initialize RAM4K blocks with contents specified in the design or to O if unspecified Internal Oscillator Frequency Range Figure 4 16 Bitmap Options Programming the Device After bitmap generation is complete clicking the Programmer icon in the Project Name tab brings up the dialog box Figure 4 179 to invoke the Programmer iCEcube2 User Guide www SiliconBlueTech com 62 TM m E rue Programmer Programming Options Programming Hardware Programming Target Internal Nonvolatile Configuration Memory NV CM External SPI Serial Flash PROM Image Image Type Single Image Image File Settings Multiple Images Advanced Execute Quit Advanced _ Beate Quit Figure 4 17 Programmer Graphical User Interface The iCEman65 Evaluation Kit Board includes an on board USB 2 0 programming solution to program the on board SPI ser
68. d to change an existing floor plan Modifying Placement of Individual Cells Placement of individual Logic Block RAM and IO cells can be changed by clicking on the cell to be moved and dragging it to the desired location Optionally the following 3 step process is recommended 1 Select the cell to be moved by Right Mouse Click gt Move It may be the case that for certain IO cells the Move menu is not available This is intentional since it prevents incorrect placement of special pins like global buffers that can only be placed at certain fixed locations 2 Move the cursor to the desired location 3 Place the cell at the target location by Right Mouse Click gt Put Note A set of logic cells contained in the same carry chain can be moved as a group In order to move the entire set of logic cells select the carry in cell 1 e the square green cell at the bottom left corner of the Logic Tile Drop this cell at the desired carry in cell location Pin locations can also be changed through the Pin Constraint dialog box Figure 6 8 This dialog can be invoked for each pin using Right Click gt Edit Pin Constraint In addition to its location the pin s IO standard and Pull Up resistor can also be configured from this dialog Note Differential IO pins are supported only on Bank 3 iCEcube2 User Guide www SiliconBlueTech com 104 TM Port Mame irst IO Mame irst pad irst pad IO Standard SB LVCMOS nd up Figure 6 82 T
69. delay adjustments PLL Operation Modes How will the PLL output be generated Using a Feedback path internal to the PLL O No Compensation mode C3 Delay Compensation using only the Fine Delay Adjustment Block Delay Compensation using the Phase Shifter and the Fine Delay Adjustment Block Using a Feedback path external to Ehe PLL The external Feedback path will include a divider implemented by the user in logic with default divide by Factor of 1 Fine Delay Adjustment Settings Do you want to dynamically control Ehe delay of the Fine Delay Adjustment Block O Yes O Ma Fine delay adjustment setting Enter a value in the range 15 Figure 3 12 1iCE40 PLL Configuration Selecting PLL type and Operation Modes PLL Operation Modes The PLL can be configured to operate in one of multiple modes An Operation Mode determines the feedback path of the PLL and enables phase alignment of the generated clock w r t to the source clock The iCEcube2 software supports the following PLL Operation modes 1 No Compensation mode The PLL can be used for generating the desired output frequency without the ability to control the phase of the generated clock 2 Delay Compensation using only the Fine Delay Adjustment FDA Block In this mode the feedback path is internal to the PLL but traverses through a fine delay adjustment circuit that permits user control of the feedback path delay in 16 steps of 0 15 ns each The delay adj
70. displays the Project Manager GUI A new project can be opened by clicking on the New Project icon or the File gt New Project menu item as displayed in Figure 3 1 iCEcube2 Project Flow Manager Similarly an existing project can be opened or closed using the Open Project and Close Project icons Open Project Close Prq Double click to New Project 4 Synthesis Input Files Design Files Constraint Files D Launch Synthesis Tool 4 P amp R Flow Select Implementation gt Additional Files 4 Run D Import P amp R Input Files D Run Placer D Run Router gt Generate Bitmap 4 Output Files Reports Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily Device Device Package Power Grade Figure 3 1 iCEcube2 Project Flow Manager Adding Deleting Design and Constraint Files Design and Constraint files can be added removed from the project by selecting Design Files or Constraint Files respectively as displayed in Figure 3 2 33 www SiliconBlueTech com iCEcube2 User Guide A SiliconBlue iCEcube2 Output Sm H 8 x L e da GEE A EE b gt u ESS test_blinky ja x Output 4 Project Project Directory is C SbtTools 2010_06_May04 SBTools examples pblinky test_blinky New Project Open Project Close Project 4 Synthesis Tool 4 Synthesis Input Files 4 Design Files blinky vhd 4 Constraint Fil test sdc D Launch Synthesis Tool 4 P amp R Flow Select I
71. ds are displayed Enabled Use the Enable field to enable or disable the constraint From Enter the port or pin from which the false path is defined The exception is applied for the data paths launched on both rising and falling transitions Rise From Enter the port or pin from which the false path is defined The exception is applied only for the paths launched on rising transitions Fall From Enter the port or pin from which the false path is defined The exception is applied only for the paths launched on falling transitions 73 www SiliconBlueTech com iCEcube2 User Guide Silicon To Enter the Port or pin up to which the false path is defined The exception is applied for the data paths captured on both rising and falling transitions Rise To Enter the Port or pin up to which the false path is defined The exception is applied only for the paths captured on rising transitions Fall To Enter the Port or pin up to which the false path is defined The exception is applied only for the paths captured on falling transitions Through Specify a pin to ensure that the constrained path passes through this pin This field is optional Note The fields From Rise From Fall From are mutually exclusive Similarly the fields To Rise To Fall To are mutually exclusive For example when a False Path exception is specified as displayed in Figure 5 10 the following SDC command is generated Seu false path rise from get clocks
72. ease refer to the Synplify Pro documentation provided in the synpro doc directory in the iCEcube2 software installation lt icecube2_install_dir gt synpro doc and on the SiliconBlue website Software Version This User Guide documents the features of iCEcube2 Software Version 2011 09 For more information about acquiring the iCEcube2 software please visit the SiliconBlue website http www siliconbluetech com Platform Requirements The iCEcube2 software can be installed on a platform satisfying the following minimum requirements A Pentium 4 computer 500 MHz with 256 MB of RAM 256MB of Virtual Memory and running one of the following Operating Systems e Windows 7 OS 32 bit 64 bit e Windows XP Professional e Red Hat Enterprise Linux WS v4 0 Programming Hardware There are three ways to program iCE FPGA devices e A third party programmer using the programming files generated by the iCEcube2 Physical Implementation Tools Consult the third party programmer user manual for instructions e The iCEman Evaluation Board which not only serves as a vehicle to evaluate iCE FPGAs but also includes an integrated device programmer This programmer can be used to program devices on the iCEman board or it can be used to program devices in a target system Please contact SiliconBlue Technologies for additional information on the iCEman Evaluation Board e Digilent USB cables 5 www SiliconBlueTech com iCEcube2 User Guide Si
73. eating the constraint is done user can save the created constraints in PCF file by clicking the save button on the top panel The created PCF file will be automatically added to the current project The legality check of the created constraints can be performed by running the Import P amp R files The adherence of the constraints can be checked out by invoking the floor planner again after running the placer 101 www SiliconBlueTech com iCEcube2 User Guide Output Flo Logic Instance Instance Type Location TF outa gonta aebuft 5B IO t inl inl ibuf LE ind find ibuf GE out outz obu CF in nz ibuf H GE outi fouko_obur ET oF putt kouti obuf V Merge Unmerge FF 10 with FF Merge ON art Merge FF to Io Merge FF Ea input Merge FF to output Merge FF ta out enable Unmerge FF from IO LInmerge FF From input LInmerge FF From output LInmerge FF From out enable Logic GPIO Global RAM Met Gra Figure 6 9 Control the auto FF Merge synthesis directive World view Global Buffer Promotion Demotion This feature allows the designer to specify usage of global routing network for a net The GUI enables this in terms of promotion demotion constraints Global Buffer Promotion For critical signals and high fan out nets such as clock designer would want to have it routed through the global routing network Also if a high routing congestion is observed in a specific area on the device th
74. ecified in Start Address field File Format This field specifies the format for the data contents within the Configuration File Supported formats include Raw hexadecimal ASCII file with raw hexadecimal data values Each hexadecimal number is represented as two equivalent ASCII characters separated by spaces or new line characters Intel MCS 86 hexadecimal ASCII file with hexadecimal values formatted to the Intel Hexadecimal file format Binary Raw binary file The file data is unmodified when writing to the memory device or when reading from the memory device 8 Cold Image 0 Programming File and Address Format Raw Hexadecimal Intel MC5 86 hexadecimal 3 Binary Start Address 000100 Config File Image 1 Programming File and Address Format Raw Hexadecimal Intel MCS 86 hexadecimal Start Address 010b00 Config File Image 2 Programming File and Address Format Start Address 021500 GP Raw Hexadecmal 3 Intel MCS 86 hexadecimal Config File E ah U Binary Image 3 Programming File and Address Format Start Address 031f00 a ac Intel MCS 86 hexadecimal Config File coon Binary Figure 4 18 Setting up the Image Files for Cold Boot Warm Boot Operation 65 www SiliconBlueTech com iCEcube2 User Guide Silicon Advanced Settings In addition to the above settings the Advanced button allows the user to configure the settings shown in Figure 4 191 Byte Lengt
75. ement Through the Floor Plan View the user can trace the connectivity of an implemented design This can be achieved via a combination of the Logic IO RAM Net pane and the Fan in Fan out functionality available for each used resource The Logic IO RAM Net pane displays the used resources on the device Selection of a node within this pane highlights the corresponding cell net in the Floor Plan view The right button of the mouse brings up a context sensitive menu specific to the particular type of resource selected This menu allows the user to Search for specific nodes or to Sort the listed nodes As an example the menu for Logic Cells is displayed inFigure 4 5 51 www SiliconBlueTech com iCEcube2 User Guide Output Floor Planner Logic Bx Logic Instance Instance Type Location A T GROUPO GROUPOO COLI SB DFF 4 9 242 t GROUPO GROUPOO COLI SB CARRY 3 9 2 F GROUPO GROUPOO COU SB LUT4 3 9 2 gt GROUPO GROUPOO COU SB DFF 9 3 GROUPO GROUPOO COLI SB CARRY 3 9 3 di GROUPO GROUPOO COU SB LUT4 3 9 3 T GROUPO GROUPOO COU SB DFF 3 9 4 GROUPO GROUPOO COU SB CARRY 3 9 4 d GROUPO GROUPOO COU SB LUT4 3 9 4 GROUPO GROUPOO COU SB DFF 3 9 5 GROUPO GROUPOO COU SB CARRY 359 9 3f GROUPO GROUPOO COU SB LUT4 3 9 5 GROUPO GROUPOO COU SB_DFF 3 3 6 GROUPO GROUPOO COLI SB CARRY 3 9 6 d GROUPO GROUPOO COU SB LUT4 3 9 6
76. en select this value as the device name Programming Target The iCEman65 Evaluation Kit Board includes an on board USB 2 0 programming solution to program the on board SPI serial Flash or the iCE65 device directly In a future iCEcube2 release the utility will also support direct programming of the iCE65 device although this is not currently supported For now the External SPI Serial Flash PROM option is automatically selected Specify the part number of the SPI Flash memory connected to the iCE65 device and the programmer The programmer currently supports the following memories m25p16 ST Microelectronics 16Mbit part m25p80 ST Microelectronics 8Mbit part This is the default memory device on the iCEman65 board at45db081 Atmel 8Mbit part 264 byte mode Image Options The iCE FPGA devices support 2 types of configuration images Single Image The device is configured with a single image that is loaded in during the initial device boot up sequence This is also known as the single image Cold Boot operation Multiple Images iCE FPGA devices permit the user to load different configuration images at device boot up or during regular operation The user can load one of 4 pre defined configuration images into the iCE FPGA device using the Cold Boot or Warm Boot operation Loading a configuration image during device boot up is called a Cold Boot operation The specific image is selected and loaded by using the CBSELO CBSEL1 and CRES
77. et ports dins 1 Output Delay Constraints To create output delay constraints select the output delay tab of the TCE GUI The following fields are displayed Enabled Use the enable tab to enable or disable the constraint Output List Enter the Output pin name Clock Specify the Reference clock edge w r t to which the output delay is specified Delay Value Enter the Delay value in Delay Value field Clock Fall Enable this field only if the output delay is specified w r t the negative edge of the reference clock Add Delay Enable this field if multiple clocks or edges reach the same port For example when an output delay is specified as displayed in Figure 5 8 the following SDC command is generated timingconstraints sdc Enabled OutputList Clock Delay Value ns Clock Fall Add Delay 1 channel1A o myclk 2 F 20 Figure 5 8 Output Delay Constraints set output delay clock get clocks imyclk add delay 2 00 get ports jchannellA o Max Delay Constraints To create Max Delay constraints select the Max Delay tab The following fields are displayed iCEcube2 User Guide www SiliconBlueTech com 72 Silicon Delay Value Enter the delay value non negative number in the Delay value field Enabled Use the Enabled field to enable or disable the constraint From Enter the source pin or port of the constrained path The constraint is applied for the data paths launched on both rising and falling transiti
78. fields are displayed Enabled Use the enable tab to enable or disable the constraint Latency Enter the source clock latency value Objects Specify the clock source or the clock name For example when source clock latency is specified as displayed in Figure 5 8 the following SDC command is generated timingconstraintks sdc Enabled Latency Objects 1 2 CLE Figure 5 6 Clock Latency Constraints set clock latency source 200 get clocks CLR AJ Input Delay Constraints To enter Input Delay constraints select the Input Delay tab in the Timing Constraints Editor GUI The following fields are displayed Enabled Use the enable tab to enable or disable the constraint Input List Enter the Input pin name in the Input List Clock This is the reference clock w r t to which the input signal is delayed Delay Value Enter the Delay value in Delay Value field 71 www SiliconBlueTech com iCEcube2 User Guide Silicon Clock Fall Enable this field only if the input is delayed w r t the negative edge of the reference clock Add Delay Enable this field if multiple clocks or edges reach the same port For example when an input delay is specified as displayed in Figure 5 7 the following SDC command is generated timingconstraints sdc Enabled InputList Clock Delay Value ns Clock Fall Add Delay 1 din i myclk 1 20 a L Figure 5 7 Input Delay Constraint Set input delay chock get clocks imyclk 1 00 g
79. from the main menu Note Any changes to the package pin assignment will require the router to be rerun Pin Constraints Editor The Pin Constraints Editor Error Reference source not found provides a table of all the pins in the design and their attributes The Editor allows the user to modify the location of the pin assign an IO Standard specify Load Capacitance on output pads and set a Pull Up resistor In order to modify a cell value click on the cell and select a value from the drop down box The drop down selection for each cell presents only the relevant pin properties ie only those destination pins that match the properties of the selected pin Similarly in the IO Standards column only the IO standards that are valid for the pin are available for selection The same is true for the Pull Up resistor column Once all changes are complete the new pin out can be saved by clicking File gt Save Pin Constraints Editor from the main menu Load Capacitance Entry Pin Constraints Editor also allows specifying the output load capacitance for output pads The default value for load capacitance is 10pf not displayed explicitly in the cells and the new desired value can be entered in the corresponding cells The capacitance values are used by Power Estimator and Static Timing Analysis tool to calculate the power consumptions and paths delays based on output loads Note This option is only available for iCE40 family devices Once the ro
80. ging the timing performances of your design Static Timing analysis along with functional verification allows you to verify the overall design operation The STA tool accepts timing constraints in Synopsys Design Constraints SDC format The SDC constraints can be forward annotated by Synplify Pro or can be specified separately by the user through the Timing Constraints Editor TCE This chapter focuses on the following aspects e Specifying Timing Constraints using the Timing Constraints Editor TCE e Analyzing Reports generated by STA Specifying Constraints Using the Timing Constraints Editor TCE The Timing Constraints Editor can be invoked by clicking Tool Timing Constraints Editor This launches a spread sheet type editor for specifying timing constraints in the SDC format V SiliconBlue iCEcube2 viper processor untitled0 sdc B W Fie View Tool Window Help _ 8 0 i d Nap JH O x Project Name prj Bx N untitled sdc N 3 Project Flow A Ehabled Source Name Period ns Waveform ns PER Input Files N V n j c 3 A Select Implementation pr implmnt Save Constraints viper processor bfpga edf NU 3 Specify Additional Files 1 pice NN i Constraint Editor ef Import P amp R Input Files i e Run Place e Run Route gt Generate Bitmap Open New Constraint Output Files File Reports Bitmap Simulation Netlist Device Operating Condition 3 Device Info DeviceFamily iCE6S Device LO4 Device Pack
81. h Specify the number of bytes not bits to write to the selected memory device The byte length can be specified as either a decimal or hexadecimal value If this option is not specified when writing the contents of a file to the memory device then the entire contents of the file will be written to or programmed into the select memory device If this option is specified but is greater than the length of the file only the number of bytes specified in the source data file are written Advanced i EConfiguration Opt Memory Block Byte Length Verify Programmed Memory 4 Erase Memory Before Programming Options SPI Clock Frequency Hz aM emen Figure 4 19 Advanced Configuration Options Verify Programmed Memory Verify the contents of the memory device after programming Erase Memory Before Programming Erase the entire memory device before programming This is the default option Un checking this option will ensure that the memory is not erased before programming This is a seldom used option but is useful when performing overlays or adding data to a previous image For example this could be used to program individual Warm Boot images across multiple programming sessions SPI Clock Frequency The Programming software optionally controls the SPI clock frequency The iCEman65 board supports any of the listed options so set the rate to its maximum value Simulating the Routed Design Once the design is routed
82. h a good phase lock BYPASS A BYPASS signal is provided which both powers down the PLL core and bypasses it such that the PLL output tracks the input reference frequency Low Power Mode A control is provided to dynamically put the PLL into a Lower Power Mode through the iCEGate feature The iCEGate feature latches the PLL Output signal and prevents unnecessary toggling iCEcube2 User Guide www SiliconBlueTech com 46 Silicon The RESET Active Low port is always generated so that an explicit PLL reset or bypass operation is required to initialize the PLL functionality Chapter 4 iCEcube2 Physical Implementation Tools Overview The iCEcube2 Physical Implementation software constitutes the second half of the iCE design flow and is used to implement the design on the iCE FPGA devices The inputs to Physical Implementation Tools are an EDIF netlist and SDC constraint files generated by Synplify Pro In addition the software supports additional Timing Constraints in SDC format as well as Physical Constraints in PCF format that can be passed directly to the Physical Implementation tools The outputs are the device configuration files used to program the device and Verilog VHDL and SDF files for timing simulation in an industry standard simulator In addition the software also provides several powerful and useful back end tools such as a Timing Constraints Editor SDC a Floor Planner a Pin Constraints Editor a device Package V
83. he Edit Pin Constraints dialog box Modifying Placement of a Group of Cells A group of cells RAM IO Logic can be moved as a unit to a new placement location In order to accomplish such an operation the Floor Planner software permits the user to select the cells using a Left mouse click and drag operation This operation is permitted only when the Floor Planner is in the Select Mode i e the arrow button R is clicked The Select Mode can be toggled ON and OFF simply by clicking this arrow icon Once the cells are grouped together it is recommended that the options shown in Figure 4 9 e switched OFF for easier selection and movement the following 3 step process is recommended 1 Invoke the Move operation through Right Mouse Click gt Move 2 Move the cursor to the desired location Make sure that there are sufficient unused resources available at the target location Since the selected group of cells cannot be placed over any cell this is already utilized it is necessary that the unused portion of the device be large enough to accommodate the same relative layout as the selected group of cells 3 Place the group of cells at the target location by Right Mouse Click gt Lock A lock symbol would be shown on the moved cells in the Floor Planner Note A set of logic cells contained in the same carry chain can be moved as a group In order to move the entire set of logic cells select the carry in cell i e the square green cell at t
84. he bottom left corner of the Logic Tile Drop this cell at the desired carry in cell location 105 www SiliconBlueTech com iCEcube2 User Guide Silicon EEGEEREMEEEEE EIE E E i j I EE aui T LE EEE E LLL EE I E a 5 5 5 Hm Pe RN T HH s 000000 a GLE AANRAAI EE Cala Ca CHER Figure 6 93 Moving a group of Logic Cells Floor Plan changes can be reverted back to their initial state using the Edit gt Undo menu Fe ee aoe Once all changes are complete the new floor plan should be saved my clicking File gt Save Floor Planner from the main menu Note Any changes to the device Floor Plan will require the router to be rerun iCEcube2 User Guide www SiliconBlueTech com 106 Silicon Chapter 7 Generating Integrating Fixed Placement IP Blocks This chapter talks about the IP Generation Integration Flow feature in iCEcube2 tools This chapter consists of the following two sections 1 IP Generation Flow This section explains the steps required to create an IP with fixed locations which can later be used in a design as a sub module thereby guaranteeing the performance of this IP sub module 2 System Design Flow This section explains the steps for instantiating the IP as a black box in the synthesis flow and including the placed IP EDIF as a sub module in the iCEcube2 Physical Implementation tools IP Generation Flow The sample design used i
85. he user the options to merge FF into IO and to separate FF from IO The options Merge FF into Input Merge FF into Output Merge FF into Output Enable specifies where the Flip Flop should be merged into Similarly the options Unmerge FF from Input Unmerge FF from Output Unmerge FF from Output Enable specifies from where the Flip Flop should be separated iCEcube2 User Guide www SiliconBlueTech com 100 Lagic Instance ES E3 E3 3 E3 Logic auE3 douta abuft inl inl ibuF ina rina ibur 4 autz fouk _oburF 4 ing inz buf aut foukO _obur ouki fouki_obuF GPIO Global cuEprut Instance Type SB IO SB IO SB IO SB IO SB IO SB IO SB IO RAM Met sro World view TM Silicon Fla Location W Merge Unmerge FF Merge FF Ea Im Merge FF Eo input Merge FF bo output Merge FF to ouk enable Linmerge FF From IO Linmerge FF From input Linmerge FF From output Linmerge FF From aut enable Figure 6 8 IO FF Merge and Unmerge Option Only the options that are feasible to merge separate are displayed in the GUI The options will be grayed out whenever merging unmerging a FF is not possible The synthesis tool by default identifies the flops that can be merged into the IO and generates appropriate directives to the P amp R tool The auto FF merge directive can be controlled by the user by setting the Merge FF option to off This is shown in Figure 6 9 Once cr
86. iCEcube2 User Guide Silicon me Silicon Copyright Information Copyright 2008 2011 SiliconBlue Technologies Corporation All rights reserved SiliconBlue is a trademark of SiliconBlue Technologies Corporation Magma and Blast FPGA are trademarks Magma Design Automation Inc Synopsys and Synplify Pro are trademarks of Synopsys Inc All other trademarks are the property of their prospective owners All specifications are subject to change without notice Notice of Disclaimer This software is provided to you as is without any express or implied warranty Contact Information SiliconBlue Technologies Corporation 3255 7 Scott Blvd Suite 101 Santa Clara CA 95054 Tel 408 727 6101 Fax 408 727 6085 support siliconbluetech com Revision History The following table lists the revision history of this document Version Revision Release iCEcube2 2010 03 Release iCEcube2 2010 09 Release iCEcube2 2010 12 Release iCEcube2 2011 06 Release iCEcube2 2011 09 iCEcube2 User Guide www SiliconBlueTech com 2 Silicon TABLE OF CONTENTS ladd6iWwJqe m TTR o FaN 0 8 Ohta S Berenice 5 PO Va Nps tera ees E es wesw nsec ncaa ese sete 5 DEdtorm Ted uH Pen HS cosas meer nC a Steerer ere eer imet en ere ree eer ee eer re 5 Frogramnine Hardware HP D 5 Chapter 1 OvVerview ccccccssccssscsssccsssccssccssscsssccsscccssccsssccssscsssccssscssscsscce
87. ial Flash or the iCE65 device directly In a future iCEcube2 release the utility will also support direct programming of the iCE65 device although this is not currently supported The Programming software requires that the Digilent Adept software first be installed on the computer The Adept software includes all the relevant USB device drivers This should already be installed if the user elected the default installer options In order to configure the programmer the user needs to specify the following settings in the Programmer GUI Programming Options Programming Hardware This is the name of the programming target device which is either the iCEman695 evaluation board or a JTAG USB cable The possible values include Eval Board iCEman65 evaluation board This is the default value Digilent USB Cable DCabUsb Use the Adept USB Administrator software to determine the name of the JTAG USB cable If the USB Administrator reports the name as DCabUSP then select this value as the device name Digilent USB Cable CCabUsb Use the Adept USB Administrator software to determine the name of the JTAG USB cable If the USB Administrator reports the name as CCabUSP then select this value as the device name 63 www SiliconBlueTech com iCEcube2 User Guide Silicon Digilent USB Cable BCabUsb Use the Adept USB Administrator software to determine the name of the JTAG USB cable If the USB Administrator reports the name as BCabUSP th
88. iconBlue iCEcube2 DX Tool Window Help Z Figure 2 1 Create a New Project The first step is to create a new design project and add the appropriate design files to your project You can create a new project by either selecting File gt New Project from the iCEcube2 menu or by clicking the Create a New Project icon as seen in Figure 2 1 The New Project Wizard GUI is displayed in Figure 2 2 This example is targeted for iCE65 family device Follow the following steps to setup the project properties New Project Project Project Name Project Directory C SbtTools examplestblinky Device Device Family iCE40 Device Device Package CM1z1 Operating Condition Ambient Temperature fin degrees Celsius Range Best Typical Commercial v a Core Voltage v voltage Tolerance Range Best Typical 5 datasheet deFaul IOBank valtaget v FapBank 1 8 bottormBank leFtBank 1 8 righkBank Perform timing analysis based on Best Typical Start From Synthesis 3 Start From BackEnd F IP Generation Figure 2 2 New Project Setup Wizard for iCE40 Family Worst Worst Silicon 1 Project Name Field Specify a project name quick start in the Project Name field 2 Project Directory Field Specity any directory where you want to place the project directory in the Project Directory field 3 Device Family Fields This section allows you to specify the SiliconBlue device family
89. iewer a Power Estimator and a Static Timing Analyzer Tools for Physical Implementation In addition to the Placer and the Router iCEcube2 provides the following tools to appropriately constrain analyze verify the design and program the target device 1 Timing Constraint Editor TCE This tool allows the user to specify timing constraints in the SDC format which can be used to constrain the Placer and Router Additional details on using TCE are provided in a subsequent chapter 2 Timing Analysis The Static Timing Analysis tool provides design performance analysis to help identify critical paths in the design The usage of this tool is explained in subsequent chapters 3 Physical Constraints Editor Floor Plan Viewer This tool has a dual function It allows the user to create physical constraints after importing the design which are honored by the Placer After the Placer has run this tool allows the user to view the logic and pin placement before final bitmap generation At this stage of the design flow it allows the user to modify the placement of logic cells IO cells and RAM cells before final routing 4 Package View This utility allows the user to view the pin assignments before final bitmap generation It also allows the user to modify the pin placement 5 Pin Attributes Editor This tool allows the user to view and configure pin properties such as pin location the IO standard and the optional pin Pull Up resistor
90. is C SbtTools examples blinky quick start ls Mayl72011 Trunk synpro bin mbin synplify exe C SbtTools examples blinky quick start quick start syn prj Open Project Close Project Synthesis Tool Add Synthesis Files Design Files blinky vhd Constraint Files blinky_syn sdc e Launch Synthesis Tool P amp R Flow H ef Select Implementation H Add P amp R Files Run All Import P amp R Input Files Run Placer Current C SbtTo Current Inplementatio ols examples Implementatio C SbtTools examples quick start Implmnt detected Need to run Current Implementatioy C SbtTools examples quick start Implmnt 4 detected Need to run Current Implementatioy C SbtTools examples lH quick start Implmnt 4 detected Need to run Current Implementatioy n quick start Implmnt its sbt path blinky quick_start quick start Implmntisbt n quick start Implmnt its sbt path blinky quick start quick start Implmnt sbt newer file C SbtToolz examples blinky quick start aa Import P amp R Input Files Select Synthesis Implementation Synthesis Implementation Selection Please select the implementation as input to P amp R quick_start_Implmnt C SbtTools examples quick start Implmnt 4 f quick start Implmnt rt quick start Implmnt fquick start Implmnt fquick start _Implmnt f quick start edf fquick start edf quick start edf quick start edf Run Router detected
91. is can be reduced by promoting a high fanout net in this area Global Buffer Promotion feature allows the user to explicitly assign a net to the global routing network on the device as shown in Figure 6 10 Right clicking on the logic instance gives the option Global Buffer Promotion Demotion Selecting the option will gives a pop up with Global Buffer Promotion Option Global Buffer Demotion Non critical signals in a design need not use the global routing network This can be ensured by the designer by specifying Global buffer demotion constraints in GUI If designer finds that delay from source of the net to SB_GB is causing degradation of performance such instance of SB_GB could be demoted Global Buffer Demotion feature allows the user to demote an SB GB SB GB IO In case of SB GB the instance will be removed and for SB GB IO it will be converted into SB IO iCEcube2 User Guide www SiliconBlueTech com 102 Silicon Figure 6 11 shows how to demote a Global Buffer Right clicking on the instance SB_GB gives the option Global Buffer Promotion Demotion Selecting the option will gives a pop up with Global Buffer Demotion Option Logic m x Logic Instance Instance Type Location i data dff 2 RNO SB LLUT4 m LP oure z sum SB LUT4 d data dff 1 SB DFF i data dff D 2 2 5UMO_ SB LLIT4 EE EMI rea 11 SB DFF RD iT data dff 4 SB DF wave Global Buffer Promoti x m i data dff D SB DF
92. ject Name quick stark Project New Project Open Project Close Project Synthesis Tool Add Synthesis Files Design Files blinky vhd Constraint Files blinky_syn sdc e Launch Synthesis Tool P amp R Flow ef Select Implementation quick_sta quick start edf quick start scf Add P amp R Files Design Files IP Design Files Constraint Files blinky_constraints mtel Run All Import P amp R Input Files Run Placer D gt Run Router Double click to Import P amp R Input Files gt Generate Bitmap Output Files Reports Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 Device L04 Device Package CB284 Power Grade L Operating Condition Core Voltage Temperature C Output Figure 2 27 Double click on Import P amp R Input files iCEcube2 User Guide www SiliconBlueTech com 30 W SiliconBlue iCEcube Output T File view Tool Window Help 08 903 2 Project Name quick start Project New Project Open Project C SBTools Mayl 2011 Trunk sbt backend bin win32 optiedifparser exe Close Project C Tools examples blinky quick start quick start Implmnt quick start edf C SBTools Mayl72011 Trunk sbt_backend devices ICES dev Synthesis Tool Tools examples blinky quick start quick start Implmnt sbt netlist pCB284 3 Add Synthesis Files M Tools ex MIplax BLinky BiXREY E onstraints mtcl c Design Files SiliconBlue dio
93. ks 0 I Constraint Elle CINE Inolementation Options Update Compile Point Timing Data E Annotated Properties f st v CD Launch Synthesis Too RR Add PeR Implementation i Resolve Mixed Drivers E P amp R F ow View Log gt Select Implermenta Double click to lau mi F MHz a Add P amp R Files oe a C Run All E 7 Click on an option for description D Import P amp R Input Files B 19 Creation Project syn D Run Placer D Run Router System Designer Board Fie D Generate Bitmap IP Exporter NOTE This version of the software is not ity included in j described in the accompanying documentatio S li PYF DR mu TCL Script Messages Figure 7 3 Run Synthesis 4 After Synthesis close the Synplify Pro tool This will bring you back to iCEcube2 tool The Synthesis output files PRJNAME edf and PRJNAME scf would be automatically added to the project Double Click on Run All to run placement router and bitmap generation W SiliconBlue iCEcube Output 2 File ES Tool Window Help Deis sect Name IP Creation Project EF Project Mew Project Open Project Clase Project E Synthesis Tool E Add Synthesis Files it Design Files Constraint Files f Launch Synthesis Tool E PER Flow E gf Select Implementation IP_Cre IP Creation Praject edf IP Creation Praject scf H Add P amp R Files L Port FR Input Files D Run Placer gt Run Router Gener
94. le IO iCEcube2 User Guide www SiliconBlueTech com 112 Insertion should be switched OFF during the System Integration phase The synthesis would be performed treating the IP as a black box Synplify Pro E 2010 09S Beta C Avorkspace msridhar DEMO IP_Flow IP_Creation_Project IP_Creation_Project_syn prj File Edk View Project Import Run Analysis HOL Analyst Options Window Tech Support Web Help D W SiliconBlue iCEcube2 Output Bbgeusmsiusg JE WE WM CN NC a i x X oc 20d 2 2 2 x Eola Fa Fa Pp W Implementation Options System_Design_Project_syn System Design Project Implmnt f x File view Tool Window Help i E Devke Options Constraints Implementation Resuks TimingReport Werog PlaceandRoute Implementations fe OOC eo D A AJ d lt a Run gt Technology Pat Package Speed ysam peson Frond Project Name IP_Creation_Project Gx Sion Blue ICE6S issos CB284 zj a M4 Project Device Mapping Options New Project roject IP_Cn Open Project m pe Type Close Project Directory ENS ADV O Synthesis Tool Add Synthesis Files 4 4i Design Files adeat 0 ee I Constrain la ait Update Compile Point Timing Data Annotated Properties for Analyst D Launch Synthesis Tog gt i Launch Synthesis Too e Pap eme zi Ow gt Select Irnplernenta Double click to lau H Add P amp R Files Run All D
95. lected Files gt gt gt G Desktop J Home Rename Exported Jred Fies of type EDIF Files edf edf edn vqn v Figure 7 10 Add IP File for performing P amp R 5 Click on Run All This would perform Placement Routing and Bitmap Generation 6 Once the Flow is completely run the placed instances can be viewed again by launching Floor Planner through Tools Floor Planner You can observe that the IP would be placed according to the locations mentioned in IP EDF 113 www SiliconBlueTech com iCEcube2 User Guide IP Instances Figure 7 11 Placed IP Instances iCEcube2 User Guide www SiliconBlueTech com 114 Silicon Appendix A PCF Syntax Relative Placement 1 Group Creation create_group group_name Ex create_group En_FFs begin begin instO x0 y0 z0 EFF A Ins 1 2 3 inst1 x1 y1 z1 EFF B Inst 1 2 4 end end 2 Set Group Origin Point set group origin group name x0 y0 Ex set group origin En_FFs 2 3 3 Region Constraints create region name region name type type x left y bottom x right y top type can be blocked no cells are placed in the region or inclusive holds the cells placed in the region set group to region group name region name Ex create region name EnFFs Region type inclusive 3 3 7 10 set group to region En FFs EnFFs Region IO FF Merge 1 Merge FF to IO set io ff port name in out oe The options specify where the Flip Flops need to be merged Three Op
96. licon Chapter 1 Overview iCEcube 2 Tool Suite The iCEcube2 Tool Suite is comprised of several integrated components running under either the Microsoft Windows or the Red Hat Linux environments Please refer to Platform Requirements for additional information on supported operating systems The figure below depicts the design flow using the iCEcube2 Tool Suite The components in blue signify functionality supported by SiliconBlue Technologies proprietary iCEcube2 software and the components in purple indicate the functionality supported by Synopsys Synplify Pro synthesis tools The iCEcube2 software and Synopsys software together constitute the iCEcube2 Tool Suite Verilog VHDL D Design Files A Post Synthesized VHDL or Verilog Netlists EDIF Netlist Timing Constraints Post P amp R SS Verilog or RE VHDL Netlist SDF 3 Party Simulation Figure 1 1 The iCEcube2 Design Flow iCEcube2 User Guide www SiliconBlueTech com 6 Silicon Design Flow The following steps provide an overview of the design flow using the iCEcube2 Tool Suite Create a new project in the iCEcube2 Project Navigator and specify a target device and its operating conditions Add your HDL Verilog or VHDL design files and your Constraint files to the project 2 Synthesize your design using the Synplify Pro design software This software has been provided as part of the iCEcube2 Tool Suite and can be invoked from the i
97. menu item The iCEman65 Evaluation Kit Board includes an on board USB 2 0 programming solution to program the on board SPI serial Flash or the iCE65 device directly In a future iCEcube2 release the utility will also support direct programming of the iCE65 device although this is not currently supported Additional details on programming a device are provided in a separate section Programming the Device in the chapter on iCEcube2 Physical Implementation Tools 27 www SiliconBlueTech com iCEcube2 User Guide Programmer Programming Options Programming Hardware Eval Board v Eval Board Digilenk USB Cable OCabUsb Digilenk USB Cable CCabUsb Digilent USB Cable BiabLlsb ICE Cable x di ir IET hz rS m 5p20 w Image Image Type Single Image Image File Settings C3 Multiple Images 2 24 Programmer Graphical User Interface Addendum Importing Physical Constraints from iCEcube to iCEcube2 For users who have created physical constraints using iCEcube this section describes how to import and convert those constraints for use in iCEcube2 This section will demonstrate how to import a MTCL file from iCEcube and save it into PCF format used in iCEcube2 In the iCEcube2 project navigator Right click on Specify Additional Files See Figure 2 25 iCEcube2 User Guide www SiliconBlueTech com 28 SiliconBlue iCEcube 2 Output File View Tool Window Help Project New Project Open Project
98. mperature tin degrees Celsius Range Best Typical Norsk Commercial v o 25 7O Core Wwoltadqecw Voltage Tolerance Range Best Typical Worst S datesheet defaul e ICE nk Vvoltacdgedqsv ropBank bottomBenk lefteank rightBank Perform timing analysis based on C Best Typical C Aforst Figure 5 24 Changing the Timing Corner in the Timing Viewer Generate Timing Report and SDF This option allows the user to save the generated timing reports and SDF file for the Timing Corner selected in the Timing Viewer Cross Probing between the Timing Viewer and Floor Planner A right click on a pin name in the detailed timing path report gives options to highlight the pin and the full path in floor planner When Highlight in Floor Planner is selected the selected pin and its connections would be highlighted in the Floor Planner as shown in the Figure 5 25 When Highlight Path in Floor Panner option is selected the entire reported path is highlighted in the Floor Planner as shown in Figure 5 26 This helps the user to analyze the reported paths easily Path Detail Start BTN3 ibuf iopad PACKAGE PIN End PMOD LEFT ROTATE 4 LC 2 20 Sjsr Y Delay 7054 Path TIT xe BTN3_ibuf_iopad PACKAGE_PIN IO PAD 0 A BTN3_ibuf_iopad DOUT IO PAD 800 4 BTN3_ibuf_preio PADIN PRE IO PIN TYP 0 p BTN3 ibuf preio D IN 0 PRE IO PIN TYP 365 A Routing Delay 1932
99. mplementation Additional Files Run D Import P amp R Input Files D Run Placer gt Run Router Generate Bitmap Output Files Reports Bitmap Simulation Netlist Device Operating Condition 4 Device Info DeviceFamily ICE65 Device Figure 3 2 Adding Removing Design Files to the design project Deleting a specific file can be accomplished by selecting the file name and clicking the right button on the mouse Figure 3 3 below displays the state of the GUI upon clicking the mouse button iCEcube2 User Guide www SiliconBlueTech com 34 SiliconBlue iCEcube2 Output 9 File View Tool Window Help B e Fo a ZEZ E sj TT gt RunTo Project Name test_blinky mx Output 4 Project Project Directory is C SbtTools 2010_06_May04 SBTools examples blinky test_blinky New Project Open Project Close Project 4 Synthesis Tool 4 Synthesis Input Files 4 Design Files blinky vhd 4 Constraint Files Itest sdc D Launch Synthesis Te a MOM ras Remove File Figure 3 3 Removing Files from the design project Selecting the Target Device and Operating Conditions The iCEcube2 software provides the ability to specify the operating conditions for the target device In order to change the Target Family Device and or the Operating Conditions click the right button on the mouse in the Device Operating Condition window to display the Edit action This is shown in Figure 3 4 Ss Device Operating
100. n the New Project Window browse to location where project need to be created enter the project name set device and operation conditions Select option Start from Synthesis and click on Next V New Project Project Project Name System_Design_Project Project Directory CWworkspacelmsridharDEMOVP Flow CD Device Device Family ez v Device Lo4 v Device Package CB284 v Power Grade L v Operating Condition Ambient Temperature in degrees Celsius Range Best Typical Worst Commercial v 0 25 70 Core Voltage V Voltage Tolerance Range Best Typical Worst S datasheet defaul v r 26 1 2 v 1 14 Perform timing analysis based on Best Typical 9 Worst t9 Start From Synthes Start From BackEnd IP Generation Closes JD cance Figure 7 7 Create New Project 2 Browse to the RTL location and add the Verilog file system v into the project as shown Click on Finish to get back to iCEcube2 tool W Add Files Files to add Look in C workspace msridhar DEMO IP_Flow RTL v gt a SS System v d j System v emet gt My Computer A22 File name System v Files of type AI Files v cUm Omm Figure 7 8 Add RTL Files to Project 3 In the iCEcube2 tool window click on Launch Synthesis Tool This will invoke Synplify Pro In the Synplify Pro tool click on RUN icon to run synthesis The Disab
101. n this document as an IP is an up counter The RTL for the up counter is presented below The steps involved in exporting this IP into EDF format are 1 Launch the iCEcube2 tool and create a new project from File New Project In the New Project Window enter the project name set device and operation conditions Make sure that the Start from Synthesis and IP Generation options are selected Click Next 107 www SiliconBlueTech com iCEcube2 User Guide C New Project Project Project Mame IP Creation Project Project Directory C workspace msridhar DEMOVIP Flow qm Device BROWSE Device Family iCEB55 Device 4 Device Package CB284 g A E s 4 14 4 Power Grade Operating Condition Ambient Temperature in degrees Celsius Range Best Typical Worst NN Core Valtagerv voltage Tolerance Range Best Typical Worst 5 datasheet defaul Perform timing analysis based on Best Typical 9 Worst Start From Synthesis Start From BackEnd IP Generation ee X eas DIST Figure 7 1 New Project Creation 2 Browse to the RTL location and add the up counter file ip v into the project Add timing constraint files if any Click Finish to go back to the iCEcube2 main window C Add Files ck Giorno fe n v 8 S Files to add File name ip v Files of type All Files Figure 7 2 Add Files to Project 3 Double click on the Launch Synthesis Tool to i
102. ns option enables the user to choose the parameters that need to be used while displaying the timing report A sample customization option menu is shown in Figure 5 14 It also enables the user to adjust the width of each column By using Move Up and Move Down the user can sort out the Columns Clock Relationship Summary The Clock Relationship Summary in the Timing Analyzer Window displays the constraints and slack details for the critical clocked paths which are in the same clock domain as well as cross clock domains Clicking on Clock Relationship Summary in the timing analyzer pane generates a report as shown in Figure 5 15 No Path in the Slack Column indicates that there exists no Clock Path between mentioned Launch Clock and Capture Clock False Path in the Slack Column indicates that the path between the mentioned Launch Clock and Capture Clock was constrained as False Path The Save Summary option saves the clock relationship summary in a text format Clock Summary Clock Relationship Summary Datasheet Analyze Paths Output Timing Analyzer Generate timing report and sdf Full Screen i Launch Clock CLEAR CLEAR m4 CLRAIF E CLRAIF Ea CLEAR on CLEAR CT C1 KAIF I Data Sheet Capture Clock CLEAR CLRAIF CLKBLR CLKB F CK FR Constraint 10000 No No No Fa Fa Fa Path Path Path se Path se Path ze Path
103. ntrol 1 wr fifo exp 1 gt xnm rt topa uart control 1 rd fifo exp 1 Inst uart topb uart rxvr 1 C94 C1 3 SB 4M Inst uart topa uart xmit 1 C95 C18 c2 S gt xnm rt topa uart control 1 wr fifo exp 1 gt xnm art vr 1 rx data reg reg h data 0 4M Inst uart topb uart xmit 1 exp 10 C3 C5 4M Inst uart topb uart rxvr 1 C1256 C10 c2 4b Inst uart topa uart xmit 1 exp 10 C3 CI Inst uart topa uart rxvr 1 C94 N63 THR Inst uart topa uart rxvr 1 C1279 C3 C8 48 uart deta inb reg 3 THRU LUTA 0 SB L gt Inst uart topb uart control 1 wr fifo C1 gt 4M IN MUX bfv 26407 SB CARRY IN MUX P xnm uart topb uart control 1 rd fifo C4 2 ee xnm uart topa uart control 1 rd fifo C4 4b Inst uart topb uart xmit 1 C205 C7 c2 S d Inst uart topa uart rxvr 1 clk cnt reg 8 4l xnm rt topb uart control 1 wr fifo exp F xnm ontrol 1 write fifo data in reg 6 T Inst uart topa uart rxvr 1 sync cnt reg 0 4i IN MUX bfv 26393 SB CARRY IN MUX Inst uart topb uart control 1 wr fifo C1 IO RAM Net World View mx LI om rro hmm mima mima nam mma mi mum mum MEN REI a RAUM MINI immi man mimi mian Figure 4 2 The Floor Planner Viewing the Device Floor Plan The Floor Planner displays the placement of the netlist on the selected device as shown in Figure 4 3with u
104. nts Enabled Source Mame Periodins Waverormins 1 clack my clk 10 D 3 ARPETTI EEE PEPEE ETETETT TEN Figure 5 4 Specifying a Clock Constraint create clock name my clk period 10 00 wavetorzm 0 3j ge t ports clock Generated Clock Constraints To enter generated clock constraints select the Generated Clock tab in the Timing Constraints Editor GUI The following fields are displayed under the Generated Clock tab Enabled Use the Enable tab to enable or disable the constraint Source Specify the port or pin name from which the clock is derived Ref Clock Pin Specify the generated clock pin name Name Enter the name of the generated clock in Name tab which is optional Select the option Divide by or multiply by or invert options and duty cycle according to constraint iCEcube2 User Guide www SiliconBlueTech com 70 Silicon For example when a generated clock is specified as displayed in Figure 5 5 the following SDC command is generated create generated clock get pins divby2clk inst SB DEFSR inst Q name divbyclk source Geb ports jtcolk a edzvade by 2 e timingconstraints sde Enabled Source Ref Clock Pin Name Divide By Multiply By Duty Cyce Invert c divby2ck inst S8 DFFSR instQ c i dvbyck 20 Figure 5 5 Generated Clock Constraint Source Clock Latency Constraints To create source clock latency constraints select the Source Clock latency tab of the TCE GUI The following
105. nvoke Synplify Pro Click on the RUN icon in Synplify Pro tool to synthesize the design The Disable IO insertion should be turned ON during IP Generation By default IO insertion would be disabled in Synplify iCEcube2 User Guide www SiliconBlueTech com 108 during IP Generation flow You can confirm it by going through Implementation JJ Options Synplify Pro E 2010 09S Beta C Avorkspace msridhar DEMO IP_Flow IP_Creation_Project IP_Creation_Project_syn prj D Fie Edk Vw Project Import Run Analysis HOL Analyst Options Window Tech Support Web Help SiliconBlue iCEcube2 Output Bsgeus5iuudg F3es4uw 6000 amp 52m 22022 35 oo33939638939 n4 dD gt File view Tool Window Help 3 Ej ol Se RRP 3 3 Implementation Options IP Creation Project syn IP_Creation_Project_Impimnt PR e RO i EE Jan d Devke Options Constraints Implementation Results TimingReport Verilog PlaceandRoute anplementations 4 ate gt IP Creation Ready Technology Pat Package Speed Project m Project Name IP_Creation_Project 8 xX Sal promt fies Siicon Blue ICE6S v icE6SL04 v cezas 4 Project aon m Creation Prc Device Mapping Options New Project BD Chose Project 5 Q ur cesi Open Project B E verkx Option Velue P M adire IP Cn Fanout Guide 10000 Close Project 5 synthesis rol TT 3 Add Synthesis Files e AT ema Pee Design Files Fix Generated Cloc
106. ons Rise From Enter the source pin or port of the constrained path The constraint is applied only for the paths launched on rising transitions Fall From Enter the source pin or port of the constrained path The constraint is applied only for the paths launched on falling transitions To Enter destination pin or port up to which the path is defined The constraint is applied for the paths captured on both rising and falling transitions Rise To Enter destination pin or port up to which the path is defined The constraint is applied only for the paths captured on rising transitions Fall To Enter destination pin or port up to which the path is defined The constraint is applied only for the paths captured on falling transitions Through Specify a pin to ensure that the constrained path passes through this pin This field is optional Note The fields From Rise From Fall From are mutually exclusive Similarly the fields To Rise To Fall To are mutually exclusive For example when a Max Delay constraint is specified as displayed in Figure 5 9 the following SDC command is generated set max delay from get pins pipel0 Q to get pins pipell D J S UD Output timingconstraints sdc Enabled Delay Value ns From Rise From Fall From To Rise To Fall To Through 3 pipe10 Q pipe 1 0 2 Figure 5 9 Max Delay Constraints False Path Exceptions To create False Path exceptions select the False Path tab The following fiel
107. onstraints User can create groups with different logic elements like LUT FF Carry Chain RAM and IO The logic elements are placed relative each other based on the location constraint x y z given to each element in the group The location constraint of every element can be a fixed value like 1 2 3 or a floating value 1 1 1 x y gives the location of the instance on the device In case of LUT FF Carry Chain Z value gives the location of a BLE in CLB Since a CLB contains 8 BLE s the valid values of Z are 0 to 7 In case of IO z value gives the location of an IO in a tile Since an IO tile contains two values the valid values of Z are 0 and 1 RAM instance contains only x y location User can place the elements in a group relative to a origin location by constraining the group elements to an origin When a group is set to an origin point then the location constraint of an element in the group is the sum of origin value and its location constraint value given in the group For example when a LUT location constraint in a group is 1 2 3 and the group is set to origin 3 4 then the location constraint on the LUT becomes 4 6 3 By default the origin point of any group is 0 0 In case of RAM IO the constraints are absolute So they will be placed at the location mentioned in the group origin constraint will be ignored Group creation and setting their origin point can be done from GUI The following
108. ools In order for Static Timing Analysis to be performed at the desired Operating Conditions the software provides the ability to select the Best Case Typical Case or Worst Case conditions Output Window The iCEcube2 Project Flow Manager software provides an Output Window to display messages warnings and errors PLL Module Generator Certain devices of the iCE65 iCE40 family include a Phase Lock Loop PLL function The PLL function requires configuration before it can be used in a design To help configure the PLL the iCEcube2 Project Flow Manager includes a PLL Module Generator which can be launched from the Tool gt Configure PLL Module menu item as displayed in Figure 3 6 37 www SiliconBlueTech com iCEcube2 User Guide Timing Constraints Editor Pin Constraints Editor Output Floor Planner Close Pr ct Directory is C 4 Synthesis Tc Package View ools 2010_06_May04 SBTools examples blinky test_blinky 4 Synthesi 4 Desi ZzE Programmer b 4 Cons Power Estimator Timing Analysis PLL Parameter Editor t Configure PLL Module D Laur 4 P amp R Flow View Report Select In gt Addition 4 Run D RunAll Ctrl A D I RunTo d D F D F Tool Options Stop Synthesis D Generate Bitmap 4 Output Files Reports Bitmap Simulation Netlist 4 Device Operating Condition 4 Device Info DeviceFamily iCE65 Device LOS Device Package CB284 Power Grade L 4 Operating Condition
109. opening the Floorplanner You can open the Floorplanner by going to the menu and selecting Tool gt Floorplanner or you can also select the Floorplanner Icon See Figure 2 18 23 www SiliconBlueTech com iCEcube2 User Guide SiliconBlue iCEcube2 icetest Floor Planner E eee aM ee e La 4 CT Bae s ej amp s se m Floor Planner amp Specify Synthesis Input Files amp Design Files Constraint Files e Synthesis amp PRR Input Files ef Select Implementation qui quick start edf quick start scf amp Specify Additional Files e Import P amp R Input Files e Place D Route g D Bitmap E 4h IN MUX bfv 15 4 S Output Files x dy CONSTANT ONE L reports amp S Divider to 1Hz un bitmap S 4M Divider to 1Hz un amp A IN MUX bfv 14 7 D lt gt IN MUX bfv 14 8 w w i lt O O Cc O O0 O e a mo OOK SWN eK 0m simulation netlist a Divider to 1Hz un Device Operating Condition t Divider to 1Hz un S Device Info DIVIDE 32MHz un DeviceFamily iCE65 Device LO4 Device Package CB284 Power Grade L Operating Condition Core Voltage V 1 14 Temperature C 70 Figure 2 18 Floorplanner View the Package Viewer You can also see how pins were placed for your design by selecting the Package Viewer You can select the package viewer by going to the menu and selecting Tool gt gt Package Viewer or y
110. or Planner Selecting the Search menu item brings up the user interface displayed in Figure 4 6 Note that the same dialog box can also be invoked from the Edit gt Search menu item The type of design node Logic Net IO RAM Port should be specified in order to filter the search process In addition a search pattern with wildcards to match the required node names can be specified Clicking on the Search Button identifies and lists the nodes whose names match the search pattern for the specified node type When a node from the Search Results window is selected it is highlighted in the corresponding tab of the Logic IO RAM Net pane as well as in the Floor Plan view 53 www SiliconBlueTech com iCEcube2 User Guide Using search pattern mux ROM C16 Case sensitive Search results mux if out ROM 0 ROM blk mux 0 C16 I0 mux if out ROM 0 ROM blk mux C16 1 Figure 4 6 Search Functionality in the Floor Planner A Right Mouse Click on the selected node in the Floor Plan View invokes a menu that allows the user to display the nets connected to the node This menu can be invoked for Logic Cells Block RAM and IO Cells The resulting menu for a Block RAM cell is displayed inFigure 4 7 iCEcube2 User Guide www SiliconBlueTech com 54 TM Display fan in nets Display fan out nets Display fan in amp fan out nets Figure 4 7 Invoking the Move and Net Tracing Capability in the Floor Planner
111. or an input of a RAM block Launch Clock The clock and its polarity at which the data is launched Capture Clock The clock and its polarity at which the data is captured Slack The slack value computed for the path The critical path has the lowest slack Delay The delay of the path as computed by the sum of the logic and routing elements between the Start and End Points This includes the Clock to Out delay of the starting FF or RAM block Skew The clock skew between the edges of the launch clock and the latch clock Save Summary and Save Detail sections are useful in saving the reported path details in a text format Save Summary option writes out the simple delay computation details used in computing the path delay Save Detail option writes out detailed path delay computation details Sort Option in the clock summary section helps the user to sort the generated path results By clicking on the sort option a window would popup asking for the feature to be used for sorting User can sort the results hierarchically based on every filed displayed in the summary section So the sort option in critical path report section would sort according to Start Point End iCEcube2 User Guide www SiliconBlueTech com 76 Silicon Point Slack Delay Skew Start Edge and End Edge Using the Add Level feature user can add these fields in priority basis and select their order in which the results need to be sorted E i i Column O
112. ou can also select the Package Vierwer Icon See Figure 2 19 iCEcube2 User Guide www SiliconBlueTech com 24 V SiliconBlue iCEcube2 Output Package View File Edit View Tool Window Help iel B om um A amp DA BASHLCH Bee Qaxve Project Name quick_start 8 X blnkypdf Output Pin Constraints Editor Floor Planner Package View Project A Port Bx Package Pin Legend New Project J n Direction O PIO le A Output 7 PIO GBIN i aem oo PMOD_B2R_ Output SPI SI SPI SO SPI SCK SPI 55 B Synthesis Too PMOD_BOR_ Output B oc Add Synthesis Files PMOD B3B J Output B cc Design Files PMOD B1T J Output blinky vhd PMOD B1B J Output B vccrojvbbro ser PMOD_BOL_J Output E CDONE CRESET B DRESET B E vpPjvDDP Constraint Files BIN3 E vnEF blinky syn sdc ur TCK TDI TDO TMS TRST B Input PMOD B2L J Output iP sw3 Input BL CLK 32 Input Bl CLK 32K Input iP sw Input e Launch Synthesis Tool P amp R Flow Gef Select Implementation quick sta quick start edf quick start scf Add P amp R Files Design Files IP Design Files Constraint Files Run co World View e Import P amp R Input Files 9960 sf Run Placer 10 7 NOOOCOOOGOOO 717117 p Run Router Generate Bitmap S Output Files iCE 65L04 CB284 Reports FE Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 Device LO4 pemeq epum
113. pecification allows the user to specify 0 degrees or 90 degrees phase shift C PLL Module Generator PLL Input Output Frequency Input frequency Mhz 50 Output frequency Mhz 133 Others Create a LOCK output port Create a BYPASS port that will bypass the PLL reference clack to the PLL output port i Mote that the PLL requires re lacking when the BYPASS signal is de asserted For all modes other than Ehe Wo Compensation made Low Power Mode Enable latching of PLL output clock iCEGate i Mote that the PLL requires re locking after the latch signal is de asserted when the Feedback path is external to the PLL Enable latching of PLL source clock Figure 3 14 iCE40 PLL Configuration Frequency Specification Frequency Specification The input and output frequency of the PLL should be specified in MHz as shown in Figure 3 14 Depending on the values provided by the user the PLL is internally configured to generate the specified output frequency Frequency Specification window also checks for the input and output frequencies given by the user If the specified frequencies are at a range that cannot be generated by the PLL then a popup dialog box is displayed as shown in Figure 3 91 asking the user to enter the frequencies in valid range LOCK A Lock signal is provided to indicate that the PLL has locked on to the incoming signal Lock asserts High to indicate that the PLL has achieved frequency lock wit
114. phase and the pad to pad delay for combinational paths If there are multiple clocks in the design then the delays are reported for each port with every relevant clock and phase Example3 is a typical Data Sheet Report generated by iCEcube2 STA tool Delays are computed using the following formulas Setup delay Data delay from Input pad to FF FF setup time Clock Path Delay Clock to out delay Clock Path Delay FF clock to out time Data delay from FF to output pad Pad to Pad delay Delay from PI to PO Example3 Datasheet Report iCEcube2 User Guide www SiliconBlueTech com 90 TM Silicontdlils ClockName Phase n 54 JA J clock clockb F clocka F clocka R ClockName Phase clocka R clockb F Note For tri state able output pads separate paths will be reported for output and output enable ports Detailed Report of All Timing Paths The Detailed Report section gives detailed slack report for all the constrained paths in the design Following section shows slack calculation for a Register to Register timing path by iCEcube2 STA A detailed Timing report contains three sections 1 Reference Points 2 Slack computation 3 Detailed Clock path and Data path delays Path start point Path end point Setup time 441ps Launch Clock Clock to Q delay Capture Clock lock del ay 1880ps Figure 5 26 Flop to Flop Path Reference Points 91
115. r start point and number of paths per end point and filtering paths based on maximum slack value Full Screen Mode allows the user to view all the paths and customize window lengths in Full Screen 83 www SiliconBlueTech com iCEcube2 User Guide Silicon Clock Summary Clock Relationship Summary Datasheet Analyze Paths Generate timing report and sdf Exit Full Screen Mode By Slack ByPaths Point to Point No Path Limit gt UC Limit Report to 100 paths More Options Path Endpoints Find Resource Resource Type Resources Query From To list From Resources Comment E IOs 4 Inputs G Outputs E InOuts 1 GROUPO GROUPOD COUNTER19 Q 0 Register Registers in IOs Registers GROUPO GROUPOD COUNTEROO Q 0 GROUPO GROUPOO COUNTEROO Q 10 GROUPO GROUPOO COUNTEROO Q 11 GROUPO GROUPOO COUNTEROO Q 12 List of Resources E GROUPO GROUPOO COUNTEROO Q 13 GROUPO GROUPOO COUNTEROO Q 14 GROUPO GROUPOO COUNTEROO Q 15 GROUPO GROUPOO COUNTEROO OF 1 Resource Type gt Resource Type gt gt 1 GROUPO GROUPOO COUNTER10 Q 10 Register RAMs 2 GROUPO GROUPOO COUNTERI8 O 6 Register v Caw lt Paths Paths Summary 2 Save Detail Customize Columns Start Point start Edgt End Point Slack Delay Skew Launch Clock Capture Clock 1 GROUPO GROUPOD COUNTER19 Q 0 LC 2 17
116. ransitions Through Specify a pin to ensure that the constrained path passes through this pin This field is optional Note The fields From Rise From Fall From are mutually exclusive Similarly the fields To Rise To Fall To are mutually exclusive For example when a Multi Cycle exception is specified as displayed in Figure 5 11 the following SDC command is generated set multicycle path from get pins pipel0 0Q to get pins pipell D 2 Output sdc_genck scf timingconstraints sdc Enabled Meycles From Rise From Fal Fram To Rise To Fall To Through 1 pipel old piped 1 0 Figure 5 11 Multi Cycle Path Exception Analyzing Reports Generated by the Static Timing Analyzer STA The output of STA is a path report giving the details of each path in the design along with delays along the paths This section explains the timing reports generated by STA in the Timing Analyzer window for a design targeted for iCE40 family and also provides directions on performing queries on specific paths of interest The Timing Analyzer window can be opened by selecting the Timing Analysis tab on the top left corner or through the Tools Timing Analysis menu item The Timing Analyzer window provides the following features each of which is explained below 1 Clock Summary 2 Clock Relationship Summary 3 Data Sheet 4 Analyze Paths Clock Summary Pane The first window shown after opening the Timing Analyzer is the Clock Summary
117. rder Column Order Sort by Y Sortby Slack Largest to Smallest Start Point Start Edge End Point End Edge Then by Start Edge A to Z v Launch Clock Capture Clock Figure 5 13 Sorting Reported Paths For example in Figure 5 13 Slack was added first in ascending order Then Start Edge was added next in ascending order So the results are displayed with ascending order of slack first and then the results with same slack are sorted in ascending order of Start Edge It should be noted that Frequency computations are performed only on paths starting from input pads and flip flop RAM outputs and ending at output pads and flip flop RAM inputs 2 If there are failing paths the critical path i e the path with the worst clock cycle time is displayed at the top 3 Ifthe paths triggered by a clock are not constrained timing start point and timing end points then the columns Worst Slack FMAX and Failing Paths are shown as N A Appropriate constraints are required in order for clock frequencies to be reported 4 Frequency calculations do not include paths involving IO s unless the IO s are constrained with Input and Output Delays 5 Cross clock domain paths are not reported in this pane 6 If there are no failing paths then only the critical path is displayed Detailed Path Report When a path in the Critical Path pane is selected detailed path summary section for the path is displayed The det
118. router in making intelligent decisions when routing signals to the inputs of the Look Up table Logic cell Invoke timing driven algorithms while routing Permit pin permutation Figure 4 1 Router Options iCEcube2 User Guide www SiliconBlueTech com 48 Floor Planner The device Floor Plan Figure 4 2 can be viewed by selecting Tool gt Floor Planner from the Tool menu by or clicking the Floor Planner icon in the Tools tree in the Project Name pane The subsequent details in this section pertain to the viewing capabilities of the Floor Planner The Floor Planner also allows the user to manually modify the placement of logic Logic Cells and RAM blocks as well as IO pins Additional details on the creation application of Physical Constraints are provided in Chapter 6 Physical Constraints in iCEcube2 9 SiliconBlue iCEcube Version 2009 03 7127 xuart Floor Planner scm ea X Ble fdt Joo Window Help x IJ AS 5 Q s Q H Floor Planner i ax TT gt xnm uart topa uart rxvr 1 data reg 0_ gt Inst uart topa uart xmit 1 tx data reg re gt 38 uart data ina reg 4 THRU LUTA O SB L gt F xnm uart topa uart control 1 wr fifo C4 xnm rt topb uart control 1 wr fifo exp gt 38 Inst uart topb uart xmit 1 C1 13 SB LU 5 xnm_opa_uart_xmit_1_tx_data_reg_reg_6_ gt Inst_uart_topb_uart_control_1_wr_fifo_C1_ HF C112 bfv 26521 SB LUT4 xnm rt topa uart co
119. rt syn prj FES blinky syn sdc quick start srs B blinky hd pening object pening object pening object pening object source source source source TCL Script Messages ee M M jp M IAHVC E file file file file c c c c Information x Watch sbttools examples blinky blinky vhd sbttools examples blinky blinky vhd sbttools examples blinky blinky vhd sbttools examples blinky blinky vhd Log Parameter quick_start_Implmnt Log Watch Figure 2 11 Double clicking on a block will reveal its HDL code in HDL Analyst Select Implementation In order to ensure that the synthesized design can be successfully imported into iCEcube2 exit the Synplify Pro GUI Return to the iCEcube2 Navigator and Double click on Select Implementation See Figure 2 12 This will tell iCEcube2 which synthesis implementation to process for place and route If you have different synthesis implementations you will be able to select the synthesis implementation you wish to place and route Since we only have one implementation select OK when the Select Synthesis Implementation dialog box appears 19 www SiliconBlueTech com iCEcube2 User Guide SiliconBlue iCEcube2 Output Brie ve DA Project Name quick_start a EE aaa 4 F 9 a zx m TT mx Output Project New Project Project G SBToo Directory
120. s iCEcube2 Tool 1o TORO E AA R 6 IB udi c 7 Chapter 2 Quick Start Guide cccccssscssssccsssscssssccsssccsssccsescccssscessseoss O RS ABN IT o eset esse terse 8 Synthesizing the NE MR A 12 Iain ore qoa ala a PAEA EEN O rer 32 Proe ce Mana e ONU aon E EOR E OOA ENEE 33 Adding Deleting Design and Constraint Files eese rennen 33 Selecting the Target Device and Operating Conditions eene 35 RE VV TI OV sesh E E O EA 37 PEE MOda ener 9 eee E a E A EE A EA E AEE E EE A AEA eer 37 Chapter 4 iCEcube2 Physical Implementation Tools 47 Booo A A E A A P 47 Tools for Physical Implementation snssssanccasctavaveiusenscnu sanctuosusecssanetaeaueueses osoin asinan inir inana 47 Placing and Routine the Desiri c 48 PE TVA a EE S PEA AE AEE OT TOT 49 WE NS VIE a E I E E ER O EE T E E E 56 Peo Tra e E Oea E E E TE A M 58 Fowo E a O a R R 59 RS FN Fein lk D aa sna tes sameeren eau M cue stece atau msauaiee ssa ereaene tase ntercen ttc sarragesnennmeet 61 eor atalaia a dB valor RD 62 OIN Ehe ROUE DES IS Bs iadsscodi Qd deter Cente A te dentis duse ipm E a ee dE 66 Chapter 5 Timing Constraints and Static Timing Analysis
121. s Route Virtual ns Clock Y CLK_32KHz CLK 32KHz default clkgroup 0 CLK 32MHZ 31 25 default clkgroup 3 N CLK 32MHZ Click on Project tab to return to Project GUI 3 E g 3 g a bo m Co Clocks Clock to Clock ollections Inputs Outputs Registers Delay Paths Attributes I O Standards P quick start syn prj Timing constraints Compile Points e uw eee wj mmo License synplifypro sbt node locked Other Watch quick start Implmnt Figure 2 9 View Timing Constraints Viewing Hierarchical View of Synthesis Results Under the HDL Analyst menu Select RTL gt Hierarchical View You will see a hierarchical RTL view of the design just synthesized See Figure 2 10 17 www SiliconBlueTech com iCEcube2 User Guide Synplify Pro D 2009 12S Early Access 2 Sheet 1 of 1 top level of module icetest RTL View quick start Implmnt quick start srs SE eC re File Edit View Project Run Analysis HDL Analyst Options Window Tech Support Web Help CJ amp TOS ODABROD AB AaVHSHO Sm OFF 5 FSD7AKA WA A BY os D P bo PR FR Fa PF ot 9 oo ky Instances 6 Ports 13 Oe 9 ckck dikkr Hz H H Nets 13 Clock Tree Dikkr b 1Hz chek dikk r 32MHz PMOD LEFT B quick start syn prj ES blinkly syn sdc 2 quick_start htm i quick_start srm 3 quick start srs Information Ex 3 quick star
122. s by performing a Right mouse click gt Show Content on a selected Logic Cell as displayed in Figure 4 3 This brings up a window that shows the portions that have logic placed within An example of a Logic Cell which contains a used LUT and flip flop but an unused Carry In is displayed in Figure 4 4 below EH ES m E Move zd x Show Content i mm Display Fan in nets upon cell selection umm T Display Fan out nets upon cell selection E um Display Fan in amp Fan out nets upon cell selection PE f Pin Permutation Lack Figure 4 3 Viewing the utilized portions of a Logic Cell iCEcube2 User Guide www SiliconBlueTech com 50 TM Ks Logic Cell Content Figure 4 4 Example of the utilized portions of a Logic Cell Ihe View gt Zoom In and View gt Zoom Out menu items zoom in and out of the Floor Plan respectively Mousing over a cell or net also displays instance information for that cell or net A World View pane provides a view of the entire Floor Plan and can be used to navigate the floor plan when the Zoom In factor is high The placed Logic tiles in the Floor Planner have the following Color conventions White color represents an empty cell Green color represents a placed cell When you select a particular cell it would be highlighted in Yellow A cell which was locked at a location would be highlighted in green color with red checks Also a Lock symbol would be shown on the cell Navigating the Design Plac
123. sary to provide a number n in the range 0 15 to specify the delay contributed to the feedback path The delay for a setting n is calculated as follows FDA delay n 1 0 15 ps where n is the value specified by the user and 0 n 15 Additional Delay Adjustment In addition to Fine Delay Adjustment in the feedback path the user can specify additional delay on the PLL output ports as shown in Figure 3 13 The delay contributed by the delay block can be Fixed or controlled dynamically during FPGA operation If Fixed it is necessary to provide a number n in the range 0 15 to specify the delay contributed to the feedback path The delay for a setting n is calculated as follows FDA delay n 1 0 15 ps where n is the value specified by the user and lt n lt 15 This additional delay is applied on the output of single port PLL and port A of two port PLL types c PLL Module Generator Phase Shift Specification Specify the phase shift For Ehe PLL output Odeg ww Additional Delay Settings Do vou wish to specify additional delay on Ehe PLL outputs n Yes Do you want to dynamically control Ehe delay of this Additional Delay Adjustment Black n Yes Ce Ma Fine Delay Adjustment Block setting Enter a value in the range O 15 Figure 3 13 iCE40 PLL Configuration Additional Delay and Phase Shift Options 45 www SiliconBlueTech com iCEcube2 User Guide Silicon Phase Shift Specification Phase Shift s
124. section explains how to create the constraints from GUI N sew vi N 7 S Output Group Bx LogicGroup Region Logic Group Logic group name En FFs Origin point 3 5 Region name Create Logic Group T Logic GPIO Global RAM Net Group Region Figure 6 3 Creating a Logic Group Once the Synthesis is done and after importing the P amp R files user can create the relative placement location constraints User has to invoke the floor planner from Tools gt Floor Planner or by clicking the Floor Planner symbol on the left top corner tools pane iCEcube2 User Guide www SiliconBlueTech com 96 Creating a Group from Floor Planner is shown in Figure 6 3 In order to create a group go to the Group tab in the Floor Planner window Right clicking on the empty space provides an option to Create Logic Group On selecting this option a popup comes out asking the user to give the details of the Logic Group such as its name and its origin location Logic RAM IO tabs in the Floor Planner gives the list of all logical elements in the design User can add elements to a created logic group by right clicking on any element and selecting the option Add to Logic Group as shown in Figure 6 4 A popup will come out asking the user to select the group into which the element needs to be added SHB ae h e amp s5s vq Output Logic ex Logic Instance Instance Type Location A H i nxm pwm 3 US
125. stimator tool To launch the power estimator to the menu and select Tool gt gt Power Estimator You can alternatively select the power estimator icon Figure 2 23 There are multiple tabs in the Power Estimator tool including Summary IO and Clock Domain On the Summary tab change the Core Vdd to 1 0V and make sure all IO voltages are at 2 5V Then hit calculate The estimator will update with power information for both static and dynamic power For more information on using the IO and Clock Domain tabs please refer to the detailed section on the Power Estimator tool iCEcube2 User Guide www SiliconBlueTech com 26 Silicon 5 Power Estimator Summary IO Clock Domain Core vddiv Power Grade Dynamic Power Breakdown IO voltage Core Power mW 1 30151 Left Bank IO voltage 2 1D Pewerimwj Right Bank IO Woltage V 2 Putus Credite a Static Powertm W 0 013 Dynamic PowertmW 3 30151 Bottom Bank TO Voltage V 2 Total Pawer mW 3 31451 Top Bank IO Volkagely Reset All Calculate Figure 2 23 Power Estimator Programming the Device In order to program a device you will need to generate a programming file In the project navigator double click on Bitmap You are now ready to program an iCE65 mobileFPGA deice with the generated bitmap Invoke the programmer from the Programming icon which is now enabled in the Project Navigator Alternately you may invoke it from the Tool gt Programmer
126. t srs SBTiCE6S Mapper Completed with warnings Return Code 1 Completion Time 13 37 50 TCL Script Messages Log Watch E MM Figure 2 10 Hierarchical RTL View in HDL Analyst If you double click on one of the blocks it will take you to the RTL for that block See Figure 2 11 iCEcube2 User Guide www SiliconBlueTech com 18 Synplify Pro D 2009 12S Early Access 2 E Fie Edit view Project Run Analysis HDL Analyst Options Window Tech Support Web Help M i i Ej e ki el A Ji Qe amp W a io e amp ws O uo 2 C 3 2979 3 2 23 9 3 Vj a mo PS 3 Fa p Nets 13 Clock Tree 4 Ports 13 a Instances t E chek dukker 32MHz DI IDE 32M Hz PMO D_LEFT PMOD BOL Jl2 PMOD BOR J13 PMOD BlT J20 PMOD B1B J21 PMOD BZR J30 PMOD BZL J31 PMOD B3B J38 PMOD B3T J39 C sbttools examples blinky blinky TOP EDGE 7 downto 4 TOP EDGE 3 downto 0 RIGHT EDGE 7 downto 4 RIGHT EDGE 3 downto 0 BOTTOM EDGE 7 downto 4 BOTTOM EDGE 3 downto 0 LEFT EDGE 7 downto 4 LEFT EDGE 3 downto 0 Divide 32 kHz clock to 1 Hz 1 second port map clock divider lHz CLK_3ZkHz gt CLK 32KHz CLK_1Hz LED CLK 3 gt CLK_lHz gt LED CLK 102 Top edge PMOD Drivers rotate led 103 104 105 106 107 108 109 port map CLK gt LED CLE sw3 gt swa SUZ gt sw BTN3 gt BTN3 LED gt TOP EDGE B quick sta
127. tart Implmnt isbt Temp sbt temp sdc EDF Parser run time l sec ef Import P amp R Input Files Run Placer Run Router D Generate Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 edif EE Figure 2 16 Successful Import of P amp R Input Files iCEcube2 User Guide www SiliconBlueTech com 22 Place the Design Double click on Run Placer Once placement is complete a green check will appear and the Output window will show information about the placement of the design See Figure 2 17 W SiliconBlue iCEcube2 Output W File View Tool Window Help Dem di E EDS OM eese Project Name quick start Bx Output Project New Project Open Project Close Project Number of clocks 4 Synthesis Tool Clock Clk 32Mhz highfreq Frequency 97 2 MHz Target 32 0 MHz Add Synthesis Files Clock Clk 3Zkhz lowfreq Frequency 160 3 MHz Target 1 0 MHz a Design Files Clock ock divider lHz LED CLK inferred clock Frequency 295 6 MHz Target 1 0 MHz 56 blinky vhd Clock clock divider 32MHz UPPER COUNT inferred clock 7 Frequency 278 2 MHz Target 1 0 MHz SSZSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSESSS Constraint Files blinky_syn sdc End of Clock Summary e Launch Synthesis Tool SSSSSSSSSSSSSISSSSSSSSSSSSSSSESSSSSSOSESSSSSSSSSESSSSESESESESESESSSEAE P amp R Flow H m4 Select Implementation quick start
128. tatus showing synthesis has been completed Double Click on the blinky syn sdc file under the Constraint folder See Figure 2 8 It will open the timing constraints for the project shown in Figure 2 9 15 www SiliconBlueTech com iCEcube2 User Guide Synplify Pro D 2009 12S Early Access 2 C SbtTools examples blinky quick start quick start syn prj CER P File Edt View Project Run Analysis HDL Analyst Options Window Tech Support Web Help J8 x ib E eE e Aa KAYE E M A E FS o 3939 9 A ty ai amp EJ a l PHRRR S amp 4 53 5 Synplify Pro quick start Implmnt Silicon Blue iCE65 iCE65L04 CB284 L quick start syn C SbtTools examples blinky quick_start quick_start_syr VHDL j blinky vhd work backup coreip sbt syntmp xplace identify 8 Open the SDC file i SEERRER a g quick quick E ix E i n SI amp e ew aa m aa License synplifypro sbt node locked t oemae oG Ji 474E M 2 Figure 2 8 Open the SDC file to View Timing Constraints iCEcube2 User Guide www SiliconBlueTech com 16 Synplify Pro D 2009 12S Early Access 2 C SbtTools examples blinky blinkly_syn sdc D File Edt View Project Run Analysis HDL Analyst Options Window Tech Support Web Help RPFfOOOReBADHE AQAA ANTA DOGM OVD Ej 0 PRR RP 3 Fal At Duty Cycle k Clock Object n
129. tilized resources depicted in green 49 www SiliconBlueTech com iCEcube2 User Guide Silicon The IO Tiles are depicted in grey and are located along the periphery of the chip Each IO Tile has 2 or 3 IO Pin locations Non bonded IOs i e an IO cell that does not bond out to a pin on the device package is unusable Such non bonded IOs are depicted in a dark shade of grey The RAM block locations are depicted by the two brown columns running vertically through the Floor Plan Utilized RAM blocks are depicted in green and the corresponding RAM Tile in a dark brown The Logic Tiles are depicted by the blue tiles and contain 8 rectangular blocks each signifying a Logic Cell 4 input LUT a flip flop and Carry logic and a small square in the bottom left corner of each tile signifying the Carry In from the Logic Tile directly below it The layout of the cells follows an X Y Z co ordinate numbering scheme with the origin at the bottom left corner of the device Mousing over the logic and IO tiles displays the location co ordinates of the tile as a two dimensional X Y co ordinate location Since each IO and Logic tile has multiple IO and logic cells respectively the IO and Logic cells within a tile are identified by the Z co ordinate resulting in a X Y Z triplet that uniquely identifies each cell As mentioned above the Logic Cell has multiple resources LUT flip flop Carry logic It is possible to view the utilized portion
130. tions can coexist at same time Ex set io ff A1 in oe 2 Unmerge FF from IO seperate io ff Sport name in out oe Ex separate io ff A1 in oe Global Buffer Promotion Demotion 1 115 Promote Signal to be Global Buffered promote signal gbuffered signal name Ex promote signal gbuffered A1 Demote Global buffered Signal demote signal unbuffered signal name Ex demote signal unbuffered A1 www SiliconBlueTech com iCEcube2 User Guide
131. u will se a list of pin assignments that are Locked under the locked column Uncheck and Recheck one of the pins under the locked column The save icon will now become an active icon Click on the Save physical constraints icon This will bring up a dialog box where you can save the PCF file Hit OK See Figure 2 30 The PCF file contain physical constraints in the design used for place and route 31 www SiliconBlueTech com iCEcube2 User Guide Window Help S NUDO Bec Save Physical Constraints es m C Om M Cw B X Output Pin Constraints Editor Project Object List Type Pin Location Bank IO Standard Pull Up Project Name quick star New Project i ora Project Pin Constraints onm ies LOO sl 3 Synthesis bles Editor Icon PMeD B3T J39 2 Output M8 Left Add Synthesis Files Design Files blinky vhd Constraint Files blinky_syn sdc e Launch Synthesis Tool P amp R Flow Gef Select Implementation quick sta quick start edf quick start scf S Add P amp R Files Design Files IP Design Files Constraint Files blinky constraints mtel Run All e Import P amp R Input Files Run Placer gt Run Router gt Generate Bitmap Output Files Reports Bitmap Simulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 Device L04 Device Package CB284 Power Grade L Operating Condition Core voltage v Temperature C Kk Output N Left S PMOD B3T J39 4 Output 5 Left Uncheck
132. udes a utility for estimating device power consumption for a given design The Power Estimator Figure 4 135 can be invoked by selecting Tools gt Power Estimator from the main menu The utility includes a listing of utilized device resources and power dissipated at the estimated maximum operating frequency The user can modify several design parameters to analyze their impact on power consumption These parameters can be modified on the various tabs of the Power Estimator GUI The Summary tab displayed in Figure 4 135 below allows the specification of the following operational parameters for the purpose of power calculation only Note that the operating conditions specified earlier for Timing Analysis are not impacted by changes to the Power Estimation parameters e Core Vdd The voltage at which the core of the chip operates in Volts IO Voltage The voltage at which the IO cells operate in Volts This can be specified individually per bank Clicking on Calculate computes the estimated power dissipation and displays the results under Dynamic Power Breakdown and Power Consumption Clicking Reset resets the values to the initial power estimates and also resets all the changes back to their default values 59 www SiliconBlueTech com iCEcube2 User Guide W Power Estimator summary 10 Clock Domain Core vdd Vv Dynamic Power Breakdown 10 Voltage Core PowertmW 0 304676 Left Bank IO Volage IO Power mW
133. ulation Netlist Device Operating Condition Device Info DeviceFamily iCE65 SiliconBlue iCEcube 2 Output DA m Bs CE e 9 Project Name quick start mx Project c New Project f Open Project C SBTools Mayl72011 Trunk sbt_backend bin win3Z opt edifparser exe C E Close Project SBTools_Mayl72011l1_Trunk sbt_backendidevices ICES dev a Synthesis Tool C SbtTools examples blinky quick start quick start Implmnt quick start edf i 5 Add Synthesis Files E PT M axEEDIEMIGU IER NUEICK start qulck scart DNDONUE sbtinetlist pCBZ284 gt B Desian Files yC SbtTools examples blinky blinky pcf c 71 a SiliconBlue Tech Edif Parser blinky vhd Release 2011 03 16214 Constraint Files Build Date May 17 2011 11 54 40 blinky syn sdc i A Launch Synthesis Tool Parsing edif file C SbtTools examples blinky quick start quick start Implmnt quick start edf P amp R Flow Parsing constraint file C SbtTools examples blinky blinky pcf BW Select Implementation quick sta Stored edif netlist at C labpTools axaxplas blinky quick sharb quick start Tuplint sbtinatlistioadb icetast a quick phic dif sdc reader OK C SbtTools examples blinky quick_start quick start Implmnt quick start scf quick_start scf Add P amp R Files Design Files EDIF Parser succeeded F IP Design Files Top module is icetest Constraint Files blinky pcf write Timing Constraint to C SbtTools examples blinky quick start quick s
134. ustment can be controlled dynamically through signals connected to the PLL or it can be fixed i e once configured the delay contributed by the delay block can only be changed upon re programming the FPGA with a different bit configuration 3 Delay Compensation using the Phase Shifter and the Fine Delay Adjustment FDA Block For single port PLL types the Phase Shifter provides 2 outputs corresponding to a phase shift of 0 degrees and 90 degrees For two port PLL types the Phase Shifter has two modes Divide by 4 mode and Divide by 7 In Divide by 4 mode the output of B port can be shifted either 0 degrees or 90 degrees w r t to A port outputs In Divide by 7 mode the B iCEcube2 User Guide www SiliconBlueTech com 44 Silicon port output frequency can be set to have a frequency ratio of 3 5 1 or 7 1 w r t the port A output frequency In addition to the delay compensation provided by the phase shifter this feedback path provides additional delay adjustment through the FDA block 4 Delay Compensation using a feedback path external to the PLL The feedback path traverses through FPGA routing external to the PLL followed by the Fine Delay Adjustment FDA Block Hence in effect 2 delay controls are available the external path for coarse adjustment and the FDA block for fine delay adjustment Fine Delay Adjustment The delay contributed by the FDA block can be Fixed or controlled dynamically during FPGA operation If Fixed it is neces
135. uter is run a report file for the IO pins is generated This file is named project pin table CSV Comma delimited text file is located in the project directory2 project Impl sbt outputs packer directory iCEcube2 User Guide www SiliconBlueTech com 58 W SiliconBlue iCEcube2 Output Pin Constraints Editor Silicon r Q TE i 0 5 f Load Capacitance Entry Project Name qui stat 8X Output Ca csr ity S Project Objet Lit Type Pinlocatin Bak 10 Standard pully New Project Open Project PMOD BOT J39 1 Output FS Left Close Project 3 Synhesis To 2 MOD B3T 233 7 Opt amp Left gt Add Synthesis Files n Dom d 3 PMOD_B3T 239 3 Outpt X Left blinky vhd 4 PMOD B3T 394 ient OD B3T 39 4 Out Di Left 7 Launch Synthesis Too 5 PMOD BOR JIN Output amp l Left 3 PER Flow 3 Select Implementation quick_start_Implmnt 6 pWop gos 3307 Op G Left quick start edf quick startscf 7 PMOD_B2R 33063 Opt fl Left Run all 8 PMOD_B2R_230 4 Outpt amp Top SBMS Yes 20 ef Import PER Input Files d Run Placer 9 PMOD_BOR J131 Opt X Left Run Router P Generate Bitmap 10 PMOD_BOR J132 Opt 2X Left 3 Output Fi rely IL PMOD_BOR_ 13 3 Opt R Bottom B LCMOS Yes 3 Bitmap PMOD BOR JIJA Left Simulation Netlist PO AR A i Device Operating Condition 13 PMOD_B36_J38 1 Output G Left 2 Device Info i Power Estimator The iCEcube2 Tool Suite incl
136. www SiliconBlueTech com iCEcube2 User Guide Silicon Reference point section gives details about the start point end point and reference launch clock and the slack of the timing path Typical Reference Points report is as shown below Path Begin reg 0 LC 1 4 O lcout Path End reg 1 LC 1 4 I in3 Capture Clock reg 1 LC 1 4 I clk Setup Constraint 10000p Path slack 8357p In this example the starting point is the flop output Icout which is in the BLE reg 0 LC 1 4 0 The end point is the flop input in3 input pin of BLE which drives the flop which is in the BLE reg 1 LC 1 4 1 Capture Clock is the capture clock of the timing path and it is the clock pin BLEreg 1 LC 1 4 1 The Setup Constraint between the launch and capture clock is 10000ps Slack computed for the path is 8357ps Slack Computation Slack is the difference between the signal required time and signal arrival time and is computed using the below formula slack End of path required time End of path arrival time Capture Clock Arrival Time Clock Source latency Clock Path Delay Setup Time Launch clock Arrival Time Clock Source latency Clock Path delay Clock to Q Data Path Delay Typical Slack Computation Report is as shown below Capture Clock Arrival Time clk R 2 10000 Capture Clock Source Latency 0 Capture Clock Path Delay 1880 Setup Time 441 End of path required time ps 11439 Launch Clock Arrival Time clk R 1 0 Launch
137. y Network Save as type All Files edf Figure 7 6 Exporting the IP into EDF Format Reporta System Design Flow This section explains the process to integrate the placed IP into the top level designs First the user needs to instantiate the IP as a black box in his RTL For example the system Top instantiates the IP So the customer needs to add a black box attribute IP as shown below iCEcube2 User Guide www SiliconBlueTech com 110 TM Silicontdlils module top clock reset enable up count out down count out y input clock input reset input enable output 7 0 up count out output 7 0 down count out reg 7 0 down count out always posedge clock begin if reset 1 down count out lt 0 else begin if enable 1 down count out lt down count out 1 end end ip up count inst IP Instantiation clock clock reset reset enable enable out up count out y endmodule BLACK BOX DECLARATION module ip clock reset enable out synthesis syn blackbox 71 input clock input reset input enable output 7 0 out endmodule The IP can be declared as black box by using the attribute syn blackbox during the IP declaration The steps involved in running the System Design Flow are 111 www SiliconBlueTech com iCEcube2 User Guide 1 Launch iCEcube2 tool and create a new project from File New Project I
138. you are targeting For this example change the Device Family to iCE65 4 Device Fields This section allows you to specify the SiliconBlue device and package you are targeting For this example change the Device to L04 and change the device package to the CB284 For iCE65 family the user has to set the device Power Grade Set Power Grade to L www SiliconBlueTech com TM iCEcube2 User Guide Silicon 5 Operating Condition Fields This section allows you to specify the operating conditions of the device which will be used for timing and power analysis The IO Bank Voltage option shown in Figure 2 2 is not available for iCE65 family devices 6 Start From Synthesis This option allows you to start the flow from Synthesis using Synopsys Synplify Pro tool For current example select this option 7 Start From BackEnd This option allows the user to start from Post Synthesis flow After the above selections the New Project GUI Wizard has the following settings New Project Project Project Mame Project Directory Device Device Family Device Device Package Power Grade Operating Condition Ambient Temperature fin degrees Celsius Range Best Typical Worst NM Core valragerv voltage Tolerance Range Best Typical Worst T 5 95 datasheet defaul Perform timing analysis based on Best Typical worst Start From Synthesis Start From BackEnd C IP Generation Cancel iCEcu

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