Home

Infineon C540U-E User`s Manual

1. Buffer Length Valid Buffer Base Addresses 8 bytes 08H 10H 18 204 28H 304 38y 40H 48H 501 58h 60y 68H 70H 78H 16 bytes 10H 20H 30 404 504 604 70H 32 bytes 20H 40H 60H 64 bytes 40H In order to avoid unused memory space between two endpoint buffers the largest buffer should be located at the highest address This structure should be used to allocate USB memory for all endpoint buffers The base address for the setup packet is always located at address 00 This leads to a typical USB buffer structure as shown in figure 6 38 with a buffer length of 64 bytes for endpoint 2 16 bytes for endpoints 1 and 3 8 bytes for endpoint 0 and a predefined length of 8 bytes for endpoint 0 and the setup token Endpoint 2 Buffer Endpoint 3 Buffer Endpoint 1 Buffer Endpoint 0 Buffer Setup Token 004 Figure 6 38 4 Buffer Block EPBAn EPLENn Endpoint 2 EPBA2 081 EPLEN2 40 Endpoint 3 EPBA3 06 EPLEN3 10 Endpoint 1 EPBA1 04 EPLEN1 10y Endpoint 0 EPBA0 03 EPLENO 08y Setup Token Adress 00y on page 0 8 Bytes Endpoint Buffer Allocation Example 4 Endpoints Semiconductor Group 6 47 1997 10 01 SIEMEN On Chip Peripheral Components 2 C540U C541U 6 4 4 USB Memory Buffer Address Generation The generation of an USB memory address for USB access read or write depends on the EPNum endpoint numbe
2. USB Address Offset Register ADROFF Address D4 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D4y 0 0 AO5 AO4 AO3 AO2 AO1 AOO ADROFF r r rw rw rw rw rw rw Bit Function AO5 0 USB address offset register AO5 0 stores the 6 bit offset address for USB memory buffer addressing by the CPU After each modification automatical or by write action of the address offset register ADROFF the value pointed to is automatically read out of USB memory and transferred to register USBVAL Semiconductor Group 6 55 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U The global endpoint interrupt request register GEPIRn n 0 4 contains one flag for each endpoint which indicates whether one or more of the eight endpoint specific interrupt requests have become active If a request flag in GEPIR is set it is automatically cleared after a read operation of the corresponding endpoint specific EPIRn register USB Global Endpoint Interrupt Request Register GEPIR Address D6y Reset Value 00H Bit No MSB LSB 6 5 4 3 2 1 0 D6H 0 0 EPIA EPI3 EPI2 EPI1 EPIO GEPIR r r r r r r r Bit Function EPI4 Endpoint 4 interrupt request flag If EPI4 is set an endpoint 4 interrupt request is pending EPIS Endpoint 3 interrupt request flag If EPIS is set an endpoint 3 interrupt request is pending EPI2 Endpoint 2 interrupt request flag If EPI2 is set an endpoint 2 interrupt
3. Note A 1 means that the lock bit is unprogrammed 0 means that lock bit is programmed For a OTP verify operation at protection level 1 the C540U C541U must be put into the OTP verification mode 2 If a device is programmed with protection level 2 or 3 it is no more possible to verify the OTP content of a customer rejected FAR OTP device When a protection level has been activated by programming of the lock bits the basic programming mode must be left for activation of the protection mechanisms This means after the activation of a protection level further OTP program veriry operations are still possible if the basic programming mode is maintained The state of the lock bits can always be read if protection level 0 is selected If protection level 1 to 3 has been programmed and the programming mode has been left it is no more possible to enter the programming mode In this case also the lock bits cannot be read anymore Figure 10 8 shows the waveform of a lock bit write read access For a simple drawing the PROG pulse is shortened In reality for Lock Bit programming a 100us PROG low puls must be applied Semiconductor Group 10 10 1997 10 01 SIEMEN OTP Memory Operation gt C540U C541U PMSEL1 0 PALE Port 0 D1 DO PROG PRD MCTO3421 The example shows the programming and reading of a protection level 1 Figure 10 8 Write Read Lock Bit Waveform Semiconductor Group 10 11 1997 10 01 I
4. Note SSCCON must be programmed only when the SSC is idle Modifying the contents of SSCCON while a transmission is in progress will corrupt the current transfer and will lead to unpredictable results Semiconductor Group 6 28 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U This register enables or disables interrupt request for the status bits SCIEN must only be written when the SSC interrupts are disabled in the general interrupt enable register IEN2 9Apj using bit ESSC otherwise unexpected interrupt requests may occur Special Function Register SCIEN Address AC Reset Value XXXXXX00p MSB LSB Bit No 7 6 5 4 3 2 1 0 ACH WCEN TCEN SCIEN Bit Function Reserved for future use WCEN SSC write collision interrupt enable WCEN 0 No interrupt request will be generated if the WCOL bit in the status register SCF is set WCEN 1 An interrupt is generated if the WCOL bit in the status register SCF is set TCEN SSC transfer completed interrupt enable TCEN 0 No interrupt request will be generated if the TC bit in the status register SCF is set TCEN 1 Aninterrupt is generated if the TC bit in the status register SCF is set Note The SSC interrupt behaviour is in addition affected by bit ESSC in the interrupt enable register IEN2 and by bit 2 in the interrupt priority registers IPO and IP1 Semiconductor Group 6 29 1997 10 01
5. CBFn CPU buffer full Bit CBFn indicates the status of the CPU memory buffer for endpoint n CPU read access If CBFn 0 the CPU buffer for endpoint n is empty If CBFn 1 the CPU buffer for endpoint n is not empty CPU write access If CBFn 0 the CPU buffer for endpoint n is not full If CBFn 1 the CPU buffer for endpoint n is full DIRn Direction of USB memory access Bit DIRn indicates the direction of the last USB memory access for endpoint n If DIRn 0 the last data flow for endpoint n was from host to CPU If DIRn 1 the last data flow for endpoint n was from CPU to host ESPn Enable status phase If bit ESPn is set the next status phase of endpoint n will automatically be acknowledged by an ACK except the endpoint n is stalled If the status phase was successfully completed bit ESPn is automatically reset by hardware and no status interrupt request STI is generated If the CPU detects a corrupted control transfer endpoint 0 bit STALLO should be set by software instead of bit ESPO in order to indicate an error condition which cannot be recovered by the USB device itself Note bit EPSn can only be set by software Any read operation of register EPBSn returns ESPn 0 SETRDn Set direction of USB memory buffer to read Bit SETRDn is used to predict the direction of the next USB access for endpoint n as an USB read access A faulty prediction causes no errors since the USB module determines the real dire
6. 2 3 XXXXp 894 TMOD 00y GATE C T M1 MO GATE C T M1 MO 8A TLO 001 7 6 5 3 2 E 0 8By TL1 001 Y 6 ib 3 2 4 0 8CyH THO 00H i 6 5 3 2 d 0 8Dy TH1 001 7 6 5 3 2 1 0 90 P1 FFy A 6 SLS STO SRI SCLK LED1 LEDO 934 SSCCON 074 SCEN TEN MSTR CPOL CPHA BRS2 BRS1 BRSO 944 STB XXQ 7 6 5 4 3 2 E 0 954 SRB XXy 17 6 5 4 3 2 1 0 964 SSCMOD 004 LOOPB TRIO 0 0 0 0 0 LSBSM 9A ITCON XXXX METF METR IOETF IOETR 1010p A0y P2 FFH olf 6 5 4 ES 2 1 0 A8y IENO OXXX EA ET1 EX1 ETO EX0 0000p A94 IEN1 XXXX EUDI EUEI ESSC X000p ABy SCF XXXX WCOL TC 4 XX00p 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set 4 This SFR is only available in the C541U Semiconductor Group 1997 10 01 IE Memory Organization SIEMENS C540U C541U Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Reset Bit7 Bit6 Bit5 Bit4 AX Bit3 Bit2 Bit1 Bit 0 Value ACH SCIEN XXXX WCEN TCEN XX00p BOH P3 FFH RD WR T1 TO INT1 INTO DADD LED2 Bi SYSCON XX10 EALE RMAP XXXXB B8y IPO XXXX E E PTI PX1 PTO PXO 0000p B94 P1 X
7. mA Y Bit addressable 4 Request flag is cleared by hardware after the corresponding register has been read MCB03383 IE0 7 Figure 7 49 Interrupt Request Sources Part 3 Semiconductor Group 7 3 1997 10 01 IE Interrupt System SIEMENS C540U C541U 7 14 Interrupt Registers 7 1 1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO or IEN1 Register IENO also contains the global disable bit EA which can be cleared to disable all interrupts at once The SSC and USB interrupts sources have further enable bits for individual interrupt control Such interrupt enable bits are controlled by specific bits in the SFRs of the corresponding peripheral units The IENO register contains the general enable disable flags of the external interrupts 0 and 1 as well as the timer interrupts The SSC interrupt C540U only and the two USB interrupts are enabled disabled by bits in the IEN1 register After reset the enable bits of IENO and IEN1 are set to 0 That means that the corresponding interrupts are disabled Special Function Registers IENO Address A8y Reset Value OXXX0000p Bit No MSB LSB AFy AEH ADH ACH ABH AAH A9H A8H A8H EA ET1 EX1 ETO EXO IENO Bit Function EA Enable disable all Interrupts If EA 0 no interrupt will be acknowledged If EA 1 each int
8. 12 ns Fall time tr 12 12 ns Oscillator duty cycle DC 0 4 0 6 33 CLP 1 33 CLP Clock cycle TCL 33 50 CLP DCmin CLP DC NS SSC Interface Characteristics Parameter Symbol Limit Values Unit min max Clock Cycle Time Master Mode fgcix 667 ns Slave Mode scik 667 ns Clock high time scH 300 ns Clock low time tso 300 ns Data output delay to 100 ns Data output hold tuo 0 ns Data input setup ts 100 ns Data input hold f 50 ns TC bit set delay totc 8 CLP ns SLS low to first SCLK clock edge tsc 2 toa ns Last SCLK clock edge to SLS high fos feel ns SLS low to STO active trs 0 100 ns SLS high to STO tristate tst 100 ns Data output delay already to 100 ns defined Semiconductor Group 11 6 1997 10 01 Device Specifications SIEMENS C540U C541U t LHLL i MCT00096 Figure 11 12 Program Memory Read Cycle Semiconductor Group 11 7 1997 10 01 Device Specifications SIEMENS C540U C541U tavwL t avov P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00097 Figure 11 13 Data Memory Read Cycle Semiconductor Group 11 8 1997 10 01 Device Specifications SIEMENS C540U C541U Instr IN E tavwL P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00098 Figure 11 14 Data Memory Write Cycle tF 07 Vec 02 Vog 0 1 MCT03310 Fig
9. 2 E Lu Q T 2 O D D E The shaded units are not available in the C540U MCA03373 Figure 1 1 C540U C541U Functional Units Semiconductor Group 1 1 1997 10 01 SIEMENS Introduction C540U C541U Listed below is a summary of the main features of the C541U Enhanced 8 bit C500 CPU Full software toolset compatible to standard 80C51 80C52 microcontrollers 12 MHz external operating frequency 500 ns instruction cycle Built in PLL for USB synchronization On chip OTP program memory C540U 4K byte C541U 8K byte Alternatively up to 64K byte external program memory Optional memory protection Up to 64K byte external data memory 256 byte on chip RAM Four parallel I O ports P LCC 44 package three 8 bit ports and one 6 bit port P SDIP 52 package four 8 bit ports LED current drive capability for 3 pins 10 mA Two 16 bit timer counters C501 compatible On chip USB module Compliant to USB specification Full speed or low speed operation Five endpoints one bidirectional control endpoint four versatile programmable endpoints Registers are located in special function register area On chip USB transceiver SSC synchronous serial interface SPI compatible only C541U Master and slave capable Programmable clock polarity clock edge to data phase relation LSB MSB first selectable 1 5 MBaud transfer rate at 12 MHz operating frequency 7 interrupt sources 2 external 5 internal
10. 13 Bit Timer Counter Semiconductor Group 6 17 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 2 1 3 Mode 1 Mode 1 is the same as mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in figure 6 18 d 0 e TLO THO 8 Bits 8 Bits TFO Interrupt C T 1 Control P3 4 TO o P3 2 INTO MCS02727 Figure 6 18 Timer Counter 0 Mode 1 16 Bit Timer Counter Semiconductor Group 6 18 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 2 1 4 Mode 2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in figure 6 19 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged TFO Interrupt P3 4 T0 o Gate E P3 2 INTO o Control MCS02728 Figure 6 19 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 6 19 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 2 1 5 Mode 3 Mode 3 has different effects on timer O and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode 3 establishes TLO and THO as two seperate counters The logic for mode 3 on timer 0 is shown in figure 6 20 TLO uses the timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer func
11. Address data hold after PROG or PRD tech 0 ns PMSEL setup to PROG or PRD ENS 10 ns PMSEL hold after PROG or PRD lomi 10 ns PROG pulse width Ion 100 us PRD pulse width ae 100 ns Address to valid data out PAD 75 ns PRD to valid data out Ton 20 ns Data hold after PRD frou 0 ns Data float after PRD Tube 20 ns PROG high between two consecutive PROG few 1 us low pulses PRD high between two consecutive PRD low foo 100 ns pulses XTAL clock period cikp 83 3 500 ns Semiconductor Group 11 12 1997 10 01 Device Specifications SIEMENS C540U C541U PMSEL1 0 tras PAH LRN OT MCT03369 Figure 11 18 Programming Code Byte Write Cycle Timing Semiconductor Group 11 13 1997 10 01 Device Specifications SIEMENS C540U C541U PMSEL1 0 tras PAH Notes PROG must be high during a programming read cycle MCT03392 Figure 11 19 Verify Code Byte Read Cycle Timing Semiconductor Group 11 14 1997 10 01 Device Specifications SIEMENS C540U C541U PMSEL1 0 777 PRD Note PALE should be low during a lock bit read write cycle MCT03393 Figure 11 20 Lock Bit Access Timing Note PROG must be high during a programming read cycle MCT03394 Figure 11 21 Version Byte Read Timing Semiconductor Group 11 15 1997 10 01 SIEMENS Device Specifications C540U C541U 11 5 OT
12. If NODIEn 1 the no data interrupt is enabled Semiconductor Group 6 68 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Bit Function EODIEn End of data interrupt enable Bit EODIEn enables the generation of an endpoint specific end of data interrupt when bit EODn in register EPIRn is set If EODIEn 0 the end of data interrupt is disabled If EODIEn 1 the end of data interrupt is enabled SODIEn Start of data interrupt enable Bit SODIEn enables the generation of an endpoint specific start of data interrupt when bit SODn in register EPIRn is set If SODIEn 0 the start of data interrupt is disabled If SODIEn 1 the start of data interrupt is enabled Semiconductor Group 6 69 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U The endpoint interrupt request register EPIRn contains the interrupt request flags of the different endpoint specific interrupts In general the bits in EPIRn are reset by hardware after a EPIRn read operation Endpoint Interrupt Request Register EPIRn n 0 4 Address C4y Reset Value EPIRO 11 4 Reset Value EPIR1 to EPIR4 10y Bit No MSB LSB 7 6 5 4 3 2 1 0 C4y ACKn NACKn RLEn DNRn NODn EODn SODn EPIRn r r r r r r r r For accessing EPIRn SFR EPSEL must be Ong Bit Function ACKn USB acknowledge Bit ACKn 1 indicates a succesful action on the USB NACKn USB not acknow
13. Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of timer O TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer O If not explicity noted this applies also to timer 1 Semiconductor Group 6 13 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 2 1 1 Timer Counter 0 and 1 Registers Totally six special function registers control the timer counter 0 and 1 operation TLO THO and TL1 TH1 counter registers low and high part TCON and TMOD control and mode select registers Special Function Register TLO Address 8Aq Reset Value 00y Special Function Register THO Address 8C Re
14. To protect the system against software upset the user s program has to clear this watchdog within a previously programmed time period If the software fails to do this periodical refresh of the watchdog timer an internal hardware reset will be initiated The software can be designed so that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The watchdog timer in the C541U is a 15 bit timer which is incremented by a count rate of fog 12 or foso 192 The system clock of the C541U is divided by two prescalers a divide by two and a divide by 16 prescaler which are selected by bit WDTPSEL WDTREL 7 For programming of the watchdog timer overflow rate the upper 7 bit of the watchdog timer can be written Figure 8 1 shows the block diagram of the watchdog timer unit WDT Reset Request WDCON CO y L dE jeveswors wor swor Control Logic MCB03384 Figure 8 1 Block Diagram of the Programmable Watchdog Timer Note WDTH and WDTL cannot be accessed by software Semiconductor Group 8 1 1997 10 01 IE Fail Safe Mechanisms gt yi ENS C540U C541U 8 1 1 Input Clock Selection The input clock rate of the watchdog timer is derived from the system clock of the C541U There is a prescaler available which is software selectable and defines the input clock rate This prescaler is controlled by bit WDTPSEL in the SFR WDTREL T
15. contents of the P2 special function register 32 38 The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periods except during external data memory accesses The signal remains high during internal program execution ALE 33 39 The Address Latch enable output is used for latching the address into external memory during normal operation It is activated every six oscillator periods except during an external data memory access Input O Output Semiconductor Group 1 8 1997 10 01 SIEMENS Introduction C540U C541U Table 1 1 Pin Definitions and Functions cont d Symbol Pin Numbers P LCC 44 P SDIP 52 1 0 Function EA 35 42 External Access Enable When held high the C540U C541U executes instructions from the internal ROM as long as the PC is less than 1000y for the C540U or less than 2000p for the C541U When held low the C540U C541U fetches all instructions from external program memory For the C540U L C541U L this pin must be tied low PO0 0 PO 7 44 36 50 43 I O Port 0 is an 8 bit open drain bidirectional I O port Port O pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during
16. the SLS input may stay active during the transmission of consecutive bytes When CPHA 0 and the transmitter is enabled the MSB or LSB of the shift register is provided immediately after the SLS input is pulled to active state low The receiver will sample the input with the first clock edge and the transmitter will shift out the next bit with the following clock edge If the transmitter is disabled the output will remain in the high impedance state In this case CPHA 0 correct operation requires that the SLS input to go inactive between consecutive bytes When SLS is inactive the internal shift clock is disabled and the content of the shift register will not be modified This also means that SLS must stay active until the transmission is completed If during a transmission SLS goes inactive before all eight bits are received the reception process will be aborted and the internal frame counter will be reset TC will not be set in this case With the next activation of SLS a new reception process will be started SCLK CPOL 0 ___ SCLK CPOL 1 Input Sample at SRI STO Input Sample at SRI MCS02441 1 MSB shift first mode is assumed Bit LSBSM in register SCCMOD is 0 Figure 6 24 Slave Mode Operation of SSC Semiconductor Group 6 26 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 3 7 Register Description The SSC interface has six SFRs which are liste
17. 0 Endpoint 0 register set selected 0 0 0 1 Endpoint 1 register set selected 0 0 1 0 Endpoint 2 register set selected 0 0 1 1 Endpoint 3 register set selected 0 1 0 0 Endpoint 4 register set selected 0 1 0 1 reserved 0 1 1 X reserved Table 6 11 shows the register definitions of each endpoint or device register block in detail Semiconductor Group 6 53 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Table 6 11 Endpoint Device Register Set Address Assignment EPSEL SFR Addr Selected Register 1XXXXXXXp C1H DCR Device Control Register C2y DPWDR Device Power Down Register C3H DIER Device Interrupt Enable Register Device register C44 DIRR Device Interrupt Request Register block selected C54 reserved address C6H FNRL Frame Number Register low byte C7y FNRH Frame Number Register high byte OXXXXnnnp C1H EPBCn Endpoint n Buffer Control Register n 0 4 nnn C2y EPBSn Endpoint n Buffer Status Register n 0 4 000g to 100p C3y EPIEn Endpoint n Interrupt Enable Register n20 4 C4y EPIRn Endpoint n Interrupt Request Register n 0 4 Endpoint nnng C5y EPBAn Endpoint n Base Address Register n 0 4 register block C6 EPLENn Endpoint n Buffer Length Register n 0 4 selected C7H reserved address The data transfers between USB memory and the CPU are handled via the SFR USBVAL With a CPU write access to USBVAL the value written into it is transfe
18. 01 SIEMEN Introduction 3 C540U C541U N C P1 5 SLS P0 0 ADO P0 1 AD1 P0 2 AD2 P0 3 AD3 P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 EA D D N C N C P1 0 LEDO P1 1 LED1 P1 2 SCLK oO 0 N O o A WO n o Voc Vss RESET P1 4 STO P3 0 LED2 P1 7 P1 3 SRI ALE P1 6 PSEN P3 1 DADD N C P3 2 INTO N C P3 3 INTI P2 7 A15 P3 4 TO P2 6 A14 P3 5 T1 P2 5 A3 P3 6 WR P2 4 A12 P3 7 RD P2 3 A11 XTAL2 P2 2 M0 XTAL1 P2 1 A9 Vss P2 0 A8 Vcc N C Po oo MCP03344 This pin functionality ist not available for the C540U Figure 1 4 Pin Configuration P SDIP 52 Package top view Semiconductor Group 1 5 1997 10 01 SIEMENS Introduction C540U C541U 1 2 Pin Definitions and Functions This section describes all external signals of the C541U with its function Table 1 1 Pin Definitions and Functions Symbol Pin Numbers 1 0 Function P LCC 44 P SDIP 52 D 3 3 O USB D Data Line The pin D can be directly connected to USB cable transceiver is integrated on chip D 4 4 O USB D Da
19. 1 In the example the USB buffer has not been read out It is still full for the USB and can not be swapped CBF UBF 1 When the USB read access has occured CBF 0 the buffers are automatically swapped and bit SOD is set Number of Data Bytes MaxLen Swap Buffer Buffer UBF 1 USB Buffer Frame n 1 SOF n 1 SOF n 2 Set Set Set V A USB read Accesses ES CPU write Accesses MCT03410 Figure 6 37 Double Buffer Mode USB Read Access Data Length greater than Packet Length MaxLen Semiconductor Group 6 45 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U In general three criteria for buffer switching are implemented in the USB module a For sequential access the address offset register ADROFF is automatically incremented after each read or write action of the CPU The address offset value before incrementing represents the number of bytes stored in USB memory for a specific endpoint If the address offset value after incrementing reaches the value stored in endpoint length register EPLENn the currently active buffer is tagged full USB read access all bytes have been written by CPU CBF 1 or empty USB write access all bytes have been read by CPU CBF 0 b When Bit DONE which is located in the endpoint buffer status register EPBSn is set software buffer switching is initiated This action is independent from the number of bytes which have been handled by
20. 6 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the 4 l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO to P3 activate the read latch signal while others activate the read pin signal Int Bus Port Driver Circuit MCS01822 Figure 6 10 Basic Structure of a Port Circuitry Semiconductor Group 6 2 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Port 1 2 and 3 output drivers have internal pullup FET s see figure 6 11 Each I O line can be used independently as an input or output To be used as an input the port bit stored in the bit latch must contain a one 1 that means for figure 6 11 Q 0 which turns off the output driver FET n1 Then for ports 1 2 and 3 the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current Z or For this reason these ports are sometimes called quasi bidirectional Voc Internal Pull Up
21. 7 Detection of connected devices 6 75 A nee m S Lm LET 3 6 6 30 7 10 Device registers 6 57 to 6 63 WERE C uta oe ecd s eL 3 7 6 29 7 5 Endpoint registers 6 64 to 6 72 GOIN weiss te pics 3 4 3 6 6 15 7 9 Global registers 6 53 to 6 56 TEN Leere aan be Ral ese eee 3 6 6 27 Initialization 6 49 TEO asus Ras ci SERES 3 6 6 15 7 9 Memory buffer address generation 6 48 E ERR 3 6 6 15 7 9 Memory buffer modes 6 34 to 6 46 ENO ees Ete ere dts 3 4 3 6 6 14 Double buffer mode 6 40 to 6 46 TA ats tarios Pob dede duh 3 4 3 6 6 14 Single buffer mode 6 35 to 6 39 Timer coutter 3 22 4 2 5 RA IE s 6 13 Memory buffer organization 6 47 Timer counter 0 and 1 6 13 to 6 20 On chip USB transceiver 6 73 Mode 0 13 bit timer counter 6 17 Register set 6 52 to 6 72 Mode 1 16 bit timer counter 6 18 Transfer modes 6 33 Mode 2 8 bit rel timer counter 6 19 USBVAL 0005 3 5 3 7 6 54 Mode 3 two 8 bit timer counter 6 20 REGISIELS o ps 6 14 to 6 16 Version byteS 10 12 Timings Version registers 10 12 Data memory read cycle 11 8 MEUS eu cea M merits 3 4 3 7 10 12 Data memory write cycle 11 9 VRI oiana EN 3 4 3 7 10 12 External clock timing 11 9 MEO ws s nC T 3 4 3 7 10 12 Lock bit access timing 1115 Ww Program memory read cy
22. 9 EOD En i 6 ticas do Codes 6 69 7 7 ESPII ris telde cord 6 66 POD Msi tes TR 6 70 7 12 ESSC esses 3 6 7 5 EPBAQ i S2 ON ISEEELOR YAT Rt 3 8 ETO 0 eee eee eee eee ee 3 6 7 4 ERBA cacti to a AT aoe 3 8 EI 3 6 7 4 EPBA2 iurc Se Lose MP eti ia freie 3 9 EUDI 20s eee e eee 3 6 7 5 Semiconductor Group 12 2 1997 10 01 SIEMENS meee C540U C541U EUE C he Sdchedd ead Sue wake 3 6 7 5 IE Tess ho ADS 3 6 7 9 EWPBC cesta betae hoa 3 6 9 2 JENO ons eda d caro pe ion 3 4 3 6 7 4 EX LS su soon de xcu wee us SR E 3 6 7 4 VEEL S oss aie donk CR OR RR A 3 4 3 6 7 5 EX Acn ihe on GS isi Shans 3 6 7 4 I ED aaa aaa 3 8 Execution of instructions 2 4 2 5 INGET mu 2 a a 3 8 External bus interface 4 1 to 4 4 NM b Re ele EAS 3 9 ALE SiGtial 26s ene rn Reg 4 4 INCE nenna ret trees to miedo 3 9 ALE switch off control 4 4 INGES co ccna RE Rd ewe Lee ated 3 9 Overlapping of data program memory 4 3 INGER 3256 grid tated nar wat dora as 6 65 Program memory access 4 3 A Quz dst den efte 3 3 7 7 18 Program data memory timing 4 2 INE rase dent A T ads S 3 7 7 18 PSEN sigtial essa 25298 xum 4 3 IGterrBupIs sse gis oe Race 7 1 to 7 20 Role of PO and P2 seg Res 4 1 Entry sequence timing 7 16 F External interrupts 7 18 d NN TROC 2 3 3 7 Handling procedure 7 16 Bi TERT HE TETTE bd ica 2 3 3 7 Registers o 7 4 to 7 14
23. 9 POON nre RE Qe os 3 5 3 6 9 2 NO DIBA tac o ete a 3 9 PONT e caia dad 3 5 3 6 9 2 BODIES 22 Sus ste scit ato sentit 6 68 7 7 POE 225 ce Ente e 3 6 9 2 NOD eer hore fon 6 70 7 12 POS istics see Lei REL 3 6 9 2 O Pin configuration crasas 1 4 to 1 5 Oscillator operation 5 6 to 5 8 P LCC 44 package 1 4 External clock source 5 8 P SDIP 52 package 1 5 On chip oscillator circuitry 5 8 Pin definitions and functions 1 6 to 1 9 Recommended oscillator circuit 5 7 Ports coco 6 1 to 6 12 Oscillator watchdog 8 5 to 8 7 Alternate functions 6 8 to 6 9 Behaviour at reset 5 3 Port loading and interfacing 6 11 Block diagram um ic exe ts 8 6 Port timing ooooooo o 6 10 OTP memory operation 10 1 to 10 14 Quasi bidirectional port structure Access mode selection 10 7 Output driver circuitry 6 4 Basic prog mode selection 10 6 Port 0 2 as address data bus 6 7 Pe eee 10 10 Read modify write function 6 12 OTP memory protection levels 10 10 Power saving modes 9 1 to 9 8 OTP protection Behaviour of external pins 9 3 Level 1 verifiy timimg 10 13 Idle mode 9 3 to 9 4 OTP verification example 10 14 Power down mode 9 5 to 9 8 Protection level 1 10 13 Entering eee 9 6 Pin configuration Ex
24. Arrangement Int Bus o Pin MCS01823 Figure 6 11 Basic Output Driver Circuit of Ports 1 2 and 3 Semiconductor Group 6 3 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U In fact the pullups mentioned before and included in figure 6 11 are pullup arrangements as shown in figure 6 12 One n channel pulldown FET and three pullup FETs are used Delay 1 State Input Data Read Pin MCS03230 Figure 6 12 Output Driver Circuit of Ports 1 to 5 and 7 The pulldown FET n1 is of n channel type It is a very strong driver transistor which is capable of sinking high currents 7o it is only activated if a 0 is programmed to the port pin A short circuit to Vc must be avoided if the transistor is turned on since the high current might destroy the FET This also means that no 0 must be programmed into the latch of a pin that is used as input The pullup FET p1 is of p channel type It is activated for 1 state S1 if a O to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a O The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources
25. Buffer Frame n 1 SOF n SOF n1 and EOD and EOD Set Set V A USB read Accesses ES CPU write Accesses MCT03404 Figure 6 31 Single Buffer Mode USB Read Access with Start of Frame Done Enabled Semiconductor Group 6 39 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 2 3 Dual Buffer Mode In dual buffer mode both USB memory pages page 0 and page 1 are used for data transfers The logical assignment of the memory pages to CPU or USB is automatically switched The following two figures show the buffer handling concept in dual buffer mode for the USB read access and USB write access CPU Buffer Handling USB Buffer Handling 34 m CPU Page is empty CBF 0 USB Page is full UBF 1 CPU write Access Enabled USB read Access Enabled CPU writes 1 Byte USB read Request CPU Buffer TER full USB reads Buffer YES CPU Buffer is full CBF 1 USB Buffer is empty UBF 0 CPU write Access Disabled USB read Access Disabled EA full YES Pages are swapped CBF 1 and UBF 0 MCB03405 Figure 6 32 USB Read Access in Dual Buffer Mode Buffer Handling Semiconductor Group 6 40 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U CPU Buffer Handling USB Buffer Handling Y CPU Page is full CBF 1 USB Page is empty UBF 0 CPU read Access Enabled USB write Access Enabled CPU reads 1 Byte USB write Request CPU Buffer YES
26. PRD YM PSEL YM PALE Uff EA Vpp YM PA During this Period Signals are not actively driven MCT03389 Ready for Access Mode Selection Figure 10 5 Basic Programming Mode Selection Semiconductor Group 10 6 1997 10 01 IE OTP Memory Operation SIEMENS C540U C541U The basic programming mode is selected by executing the following steps With a stable Vcc a clock signal is applied to the XTAL pins the RESET pin is set to 1 level and the PSEN pin is set to 0 level PROG PALE PMSEL1 and EA Vpp are set to O level PRD PSEL and PMSELO are set to 1 level PSEL is set to from 1 to O level and thereafter PROG is switched to 1 level PMSEL1 0 can now be changed after EA Vpp has been set to V high level or to Vpp the OTP memory is ready for access The pins RESET and PSEN must stay at 1 respectively 0 static signal level during the whole programming mode With a falling edge of PSEL the logic state of ALE PROG and Vpp EA is internally latched These two signals are now used as programming write pulse signal PROG and as programming voltage input pin Vpp After the falling edge of PSEL PSEL must stay at 0 state during all programming operations Note If protection level 1 to 3 has been programmed see section 10 6 and the programming mode has been left itis no more possible to enter the programming mode 10 4 2 OTP Memory Access Mode Selection W
27. SIEMENS On Chip Peripheral Components C540U C541U Special Function Register SCF Address ABy Reset Value XXXXXX00p MSB LSB Bit No 7 6 5 4 3 2 1 0 ABH WCOL TC SCF Bit Function Reserved for future use WCOL SSC write collision detect If WCOL is set it indicates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed This bit will be set at the trailing edge of the write signal during the erronous write attempt This bit can be reset in two different ways 1 writing a 0 to the bit bit access byte access or read modify write access 2 by reading the bit or the status register followed by a write access to STB If bit WCEN in the SCIEN register is set an interrupt request will be generated if WCOL is set TC SSC transfer completed If TC is set it indicates that the last transfer has been completed It is set with the last sample clock edge of a reception process This bit can be reset in two different ways 1 writing a O to the bit bit access byte access or read modify write access after the receive buffer register SRB has been read 2 by reading the bit or the status register followed by a read access to SRB If bit TCEN in the SCIEN register is set an interrupt request will be generated if TC is set The register STB at SFR address 9414 holds the data to be transmi
28. Semiconductor Group 6 27 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U Bit Function CPOL Clock polarity This bit controls the polarity of the shift clock and in conjunction with the CPHA bit which clock edges are used for sample and shift CPOL 0 SCLK idle state is low CPOL 1 SCLK idle state is high CPHA Clock phase This bit controls in conjunction with the CPOL bit controls which clock edges are used for sample and shift CPHA 0 The first clock edge of SCLK is used to sample the data the second to shift the next bit out at STO In master mode the transmitter will provide the first data bit on STO immediately after the data was written into the STB register In slave mode the transmitter if enabled via TEN will shift out the first data bit with the falling edge of SLS CPHA 1 The first data bit is shifted out with the first clock edge of SCLK and sampled with the second clock edge BRS2 Baudrate selection bits BRS1 These bits select one of the possible divide factors for generating the baudrate out BRSO of the micrcontroller clock rate fosc The baudrate is defined by Baudratass fosc E fosc Dividefactor 5 BRS 2 0 for BRS 2 0 0 BRS 2 0 Divide Example Factor Baudrate for fosc 12 MHz 0 reserved reserved 1 reserved reserved 2 8 1 5 MBaud 3 16 750 kBaud 4 32 375 kBaud 5 64 187 5 kBaud 6 128 93 75 kBaud 7 256 46 875 kBaud
29. Table 6 6 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANL P1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P1 DEC Decrement byte e g DEC P1 DJNZ Decrement and jump if not zero e g DJNZ P3 LABEL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor approx 0 7 V i e alogic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch However reading the latch rater than the pin will return the correct value of 1 Semiconductor Group 6 12 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 2 Timers Counters The C540U C541U contains two 16
30. The FNRH FNRL registers are read only registers which are reset to 00y by a hardware reset Frame Number Register High Byte FNRH Address C7 Reset Value 00000XXXp Frame Number Register Low Byte FNRL Address C6y Reset Value XXy Bit No MSB LSB 7 6 5 4 3 2 1 0 C7y 0 0 0 0 0 FNR10 FNR9 FNR8 FNRH r r r r r r r r C6H FNR7 FNR6 FNR5 FNR4 FNR3 FNR2 FNR1 FNRO FNRL Bit Function FNR10 0 Frame number value FNRH 2 0 and FNRL 7 0 hold the current 11 bit frame number of the latest SOF token FNRL holds the lowest 8 bits while FNRH holds the upper 3 bits of the frame number Semiconductor Group 6 63 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U 6 4 7 3 Endpoint Registers Each of the five endpoints has its own endpoint register set which contains the following registers n 0 4 EPBCn Endpoint n Buffer Control Register EPBSn Endpoint n Buffer Status Register EPIERn Endpoint n Interrupt Enable Register EPIRRn Endpoint n Interrupt Request Register EPBAn Endpoint n Base Address Register EPLENn Endpoint n Buffer Length Register The endpoint buffer control registers control the endpoint specific operations Endpoint 1 Buffer Control RegisterEPBCn n 0 4 Address C1 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 Cip STALLn 0 0 GEPIEn SOFDEn I
31. a much lower current than p1 therefore the pin may also be tied to ground e g when used as input with logic low input level The pullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This provides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used as input In this configuration only the weak pullup FET p2 is active which sources the current 7 If in addition the pullup FET p3 is activated a higher current can be sourced 1 Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving capability is stronger if a logic high level is output Semiconductor Group 6 4 1997 10 01 SIEMEN On Chip Peripheral Components 2 C540U C541U The described activating and deactivating of the four different transistors results in four states which can be input low state IL p2 active only input high state IH steady output high state SOH p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loade
32. accesses to external program and data memory In this application it uses strong internal pullup resistors when issuing 1 s Vocu Supply voltage for the on chip USB transceiver circuitry Vssu Ground 0V for the on chip USB transceiver circuitry Vcc 8 23 10 26 Supply voltage for ports and internal logic circuitry during normal idle and power down mode Vss 9 22 11 25 Ground 0V for ports and internal logic circuitry during normal idle and power down mode Input O Output Semiconductor Group 1 9 1997 10 01 SIEMEN Introduction 3 C540U C541U Semiconductor Group 1 10 1997 10 01 IE Fundamental Structure gt yi EN 3 C540U C541U 2 Fundamental Structure The C540U C541U is fully compatible to the architecture of the standard 8051 C501 microcontroller family While maintaining the typical architectural characteristics of the C501 the C541U incorporates a SSC synchronous serial interface a versatile USB module as well as some enhancements in the Fail Save Mechanism Unit Functionally the C540U is a subset of the C541U with a smaller OTP program memory and without the SSC interface and the watchdog timer Figure 2 1 shows a block diagram of the C540U C541U Oscillator Watchdog OTP Memory 4k x 8 C540U OSC amp Timing 8k x 8 C541U Emulation Progr Watchdog Support Timer C541U only Logic Port 0 Timer 0 8 Bit Digi
33. and external events to the processor to cause a change in the program execution sequence Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU Semiconductor Group 2 2 1997 10 01 SIEMENS Fundamental Structure C540U C541U Special Function Register PSW Address DOj Reset Value 00H Bit No MSB LSB D7y D6y D5y D4y D3y D2y Diy DOy DOy CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instruction AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 005 074 0 1 Bank 1 selected data address 08y 0F y 1 0 Bank 2 selected data address 1054 17 1 1 Bank 3 selected data address 18y 1Fy OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity B Register The B register is used during multiply and divide and serves as both source and desti
34. and must not set bit PDS PCON 6 the following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS does not initiate the power down mode Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0 This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly freeze the chip s activity in an undesired status Important the USB module must be switched off from the system clock prior to enabling the power down mode by software PCON is not a bit addressable register so the above mentioned sequence for entering the power down mode is obtained by byte handling instructions as shown in the following example ANL DCR 11111101B clear bit UCLK USB clock is switched off ANL DCR 11111110B clear bit PCLK stop PLL required only in full speed mode ORL PCON 00000010B set bit PDE bit PDS must not be set ORL PCON 01000000B set bit PDS bit PDE must not be set enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode When the double instruction sequence shown above is used and when bit EWPD in SFR PCON1 is 0 the power down mode can only be left by a reset operation If the wake up from power down capability is required its function must
35. bit timers counters timer 0 and 1 which are useful in many applications for timing and counting In timer function the timer register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 6 oscillator periods the counter rate is 1 6 of the oscillator frequency In counter function the timer register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin TO or T1 alternate functions of P3 4 and P3 5 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 12 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 12 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle 6 2 1 Timer Counter 0 and 1 Timer counter 0 and 1 of the C540U C541U are fully compatible with timer counter O and 1 of the 80C51 C501 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1 16 bit timer counter
36. by software After each modification of ADROFF the data value pointed to is automatically read out of USB memory and transferred to the USBVAL register If INCE 0 the auto increment function is disabled If INCE 1 the auto increment function is enabled DBMn Dual buffer mode Bit DBM allows the selection between single buffer mode and dual buffer mode If DBM 0 single buffer mode is selected If DBM 1 dual buffer mode is selected Note For accessing the EPBCn registers SFR EPSEL D2y must be set with the appropriate value Semiconductor Group 6 65 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U The bits of the endpoint buffer status registers indicate the status of the endpoint specific USB memory buffers and allows setting of certain USB memory buffer conditions Endpoint Buffer Status Register EPBSn n 0 4 Address C2 Bit No C2y MSB 7 6 5 4 3 2 1 Reset Value 201 LSB 0 UBFn CBFn DIRn ESPn SETRDn SETWRn CLREPn DONEn EPBSn r r r Ww Ww Ww Ww Ww Bit Function UBFn USB buffer full Bit UBFn indicates the status of the USB memory buffer for endpoint n USB read access If UBFn 0 the USB buffer for endpoint n is empty If UBFn 1 the USB buffer for endpoint n is not empty USB write access If UBFn 0 the USB buffer for endpoint n is not full If UBFn 1 the USB buffer for endpoint n is full
37. controlled by timer 1 control bits Timer 1 Timer counter 1 stops Semiconductor Group 6 16 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 2 1 2 Mode 0 Putting either timer counter 0 1 into mode 0 configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 6 17 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all 0 s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Substitute TRO TFO THO TLO and INTO for the corresponding timer 1 signals in figure 6 17 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 i i et TLO THO A 5 Bits 8 Bits TFO Interrupt CT 1 Control P3 4 T0 o P3 2 NTO o MCS02726 Figure 6 17 Timer Counter 0 Mode 0
38. empty USB writes Buffer YES CPU Buffer is empty CBF 0 USB Buffer is full UBF 1 CPU read Access Disabled USB write Access Disabled Pages are swapped CBF 0 and UBF 1 MCB03406 Figure 6 33 USB Write Access in Dual Buffer Mode Buffer Handling Semiconductor Group 6 41 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U Figure 6 34 describes an example of a USB read operation in sequential mode with both buffers empty at the beginning of the USB read operation The CPU starts writing data with sequential access INCE 1 to the buffer assigned to the CPU at D By definition the buffer is full when MaxLen is reached at 2 The second buffer assigned to the USB is empty UBF 0 and as a result both buffers are logically swapped Now the buffer assigned to USB is full UBF 1 and an USB read access can take place After the USB read access the buffer assigned to the USB is empty again with UBF 0 During the USB read access the CPU is still allowed to write into its assigned buffer When reaching MaxLen at 3 the CPU buffer is full and both buffers are again logically swapped The USB further execute its read access Number of Data Bytes MaxLen CPU Buffer O UJ Th Sa MaxL did UBF 77 o Frame n Frame n 1 SOF n SOF n 1 SOF n 2 Set Set Set V A USB read Accesses ES CPU write Accesses MCT03407 Figure 6 34 Dual Buffer Mode USB Read Ac
39. for several alternate functions as listed in table 6 5 Table 6 5 Alternate Functions of Port 1 and 3 Port Pin Alternate Function P1 0 T2 Input to counter 2 P1 1 T2EX Capture reload trigger of timer 2 up down count P3 0 RxD Serial port s receiver data input asynchronous or data input output synchronous P3 1 TxD Serial port s transmitter data output asynchronous or data clock output synchronous P3 2 INTO External interrupt 0 input timer 0 gate control P3 3 INT1 External interrupt 1 input timer 1 gate control P3 4 TO Timer O external counter input P3 5 T1 Timer 1 external counter input P3 6 WR External data memory write strobe P3 7 RD External data momory read strobe Semiconductor Group 6 9 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 1 3 Port Handling 6 1 3 1 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the previous phase 1 Consequently the new value in the port latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next machine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 ph
40. in SFR DCR 9 1 2 Exit from Idle Mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset After leaving the idle mode through e g an interrupt with a switched off USB module a well defined procedure must be executed foragain switching on the USB module in full speed mode only USB PLL is switched on setting bit PCLK in SFR DCR and waiting 3 ms for PLL being locked USB module clock is switched on setting bit UCLK in SFR DCR This switch off on procedure assures a proper operation of the USB clock system If the idle mode is terminated by a hardware reset the USB module has to be reconfigured as defined for the hardware reset case Semiconductor Group 9 4 1997 10 01 IE Power Saving Modes gt ii ENS C540U C541U 9 2 Power Down Mode In the power down mode the RC osciillator and the on chip oscillator which operates with the XTAL pins is stopped Therefore all functions of the microcontroller are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port
41. is particularly done when the power down mode is to be terminated Additional to the hardware reset which is applied externally to the device there are two internal reset sources the watchdog timer C541U only and the oscillator watchdog This chapter deals only with the external hardware reset The RESET input is an active high input An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held high for at least two machine cycles 12 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again During reset pins ALE and PSEN are configured as inputs and should not be stimulated or driven externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins At the RESET pin a pulldown resistor is internally connected to Vss to allow a power up reset with an external capacitor only An automatic power up reset can be obtained when Vec is applied by connecting the RESET pin to Vec via a capacitor After Voc has been turned on the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset The time required for a reset operation is the oscillator sta
42. low speed 1 5 MBaud mode This bit can only be written with bit SWR 1 software reset After hardware reset the USB module runs in low speed mode and the PLLx4 is automatically disabled If SPEED 0 low speed mode selected default after reset If SPEED 1 full speed mode selected DA Device attached Bit DA reflects the state of pin DADD which can be used to indicate whether the device is attached to the USB bus or not in self powered mode If pin DADD is 0 bit DA 0 If pin DADD is 1 bit DA 1 SWR Software reset Setting bit SWR initiates a software reset operation of the USB device This bit is cleared by hardware after successful reset operation SWR can not be reset by software SUSP Suspend mode This bit is set when the USB is idle for more than 3 ms It will remain set until there is a non idle state on the USB cable or when bit RSM is set Semiconductor Group 6 57 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U Bit Function DINIT Device initialization in progress At the end of a software reset bit DINIT is set by hardware After software reset of the USB module the USB module must be initialized by the CPU When DINIT is set after a software reset 5 bytes for each endpoint must be written to SFR USBVAL After the 25th byte bit DONEO has to be set by software Bit DINIT is reset by software after a successful initialization sequence RSM Resume bus activity When the US
43. no on chip support for multimaster configurations switching between master and slave mode operation Operating the SSC as a master in a multimaster environment requires external circuitry for swapping transmit and receive lines SCLK Master SSC STO SRI Px x Px y Px z SCLK EE oe Dedicated r Slave Select Lines Common r Slave Select Lines Slave SSC MCS02439 Figure 6 22 Typical SSC System Configuration Semiconductor Group 6 24 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 3 6 Data Clock Timing Relationships The SSC provides four different clocking schemes for clocking the data in and out of the shift register Controlled by two bits in SSCCON the clock polarity idle state of the clock control register bit CPOL and the clock data relationship phase control control register bit CPHA i e which clock edges will be used for sample and shift The following figures show the various possibilities 6 3 6 1 Master Mode Operation Figure 6 23 shows the clock data control relationship of the SSC in master mode When CPHA is set to 1 the MSB or LSB of the data that was written into the shift register will be provided on the transmitter output after the first clock edge the receiver input will sample with the next clock edge The direction rising or falling of the respective clock edge is depending on the clock polarity selected After the last bit has been shifted out the data
44. of the USB module the C540U C541U must operate with 12 MHz external clock The microcontroller except the USB module is capaable to operate down to 2 MHz Semiconductor Group 5 6 1997 10 01 IE Reset System Clock SIEMENS C540U C541U After a hardware reset operation bits PCLK SPEED and UCLK are set to 0 Depending on the required operating mode of the USB module a well defined procedure must be executed for switching on the clock for the USB module Full speed mode USB PLL is switched on by setting bit PCLK waiting 3 ms for PLL being locked setting bit UCLK Low speed mode setting bit UCLK only The switch on procedure after hardware reset assures a proper operation of the USB clock system A software reset operation of the USB module must follow this clock system switch on procedure Details of the software reset operation are described in chapter 6 XTAL1 and XTAL2 are the input and output of a single stage on chip inverter which can be configured with off chip components as a Pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip These signals define the internal phases states and machine cycles Figure 5 7 shows the recommended oscillator circuit C 20pF 10 pF for crystal operation MCS03424 Figure 5 7 Recommended Crystal Oscillator Circuit In this application the on chip oscillator is used as a crys
45. of the reset signal then depends on the prescaler selection either 8 or 128 machine cycles This internal reset differs from an external one in so far as the watchdog timer is not disabled and bit WDTS is set The WDTS is a flip flop which is set by a watchdog timer reset and can be cleared by an external hardware reset Bit WDTS allows the software to examine from which source the reset was activated The bit WDTS can also be cleared by software Semiconductor Group 8 4 1997 10 01 IE Fail Safe Mechanisms gt yi ENS C540U C541U 8 2 Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of typ 1 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Fast internal reset after power on The oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started The oscillator watchdog unit also works identically to the monitoring function Control of e
46. request is pending EPI1 Endpoint 1 interrupt request flag If EPI is set an endpoint 1 interrupt request is pending EPIO Endpoint 0 interrupt request flag If EPIO is set an endpoint 0 interrupt request is pending Bit 4 GEPIEn of the specific endpoint buffer control register EPBCn must be set if EPIn should generate an interrupt Additionally bit EA IENO 7 and bit EUEI IEN1 1 must be set when an endpoint interrupt should be triggered Semiconductor Group 6 56 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U 6 4 7 2 Device Registers The device registers can only be accessed when global register EPSEL D2 804 The following SFRs are defined as device register DCR Device Control Register PDWDR Device Power Down Register DIER Device Interrupt Enable Register DIRR Device Interrupt Request Register FNRL Frame Number Register low byte FNRH Frame Number Register high byte The device control register includes control and status bits which indicate the current status of the USB module and the status of the USB bus USB Device Control Register DCR Address C1H Reset Value 000X0000p Bit No MSB LSB 7 6 5 4 3 2 1 0 Cty SPEED DA SWR SUSP DINIT RSM UCLK PCLK DCR rw r rw r r rw rw rw Bit Function SPEED Low full speed select Bit SPEED configures the USB module in the C540U C541U for full speed 12 MBaua or
47. the CPU possible in sequential access mode INCE 1 and random access mode INCE 0 On CPU read accesses the buffer is declared empty and bit CBF is cleared If the buffer assigned to the USB is full UBF 1 the buffers are immediately swapped In this case register EPLENn contains the number of received bytes On CPU write accesses two different cases must be distinguished For random accesses the number of bytes of one packet is fixed by the value in register EPLENn and does not change For sequential accesses the number of written bytes represents the packet size In this case the actual value of register ADROFF is transferred to register EPLENn when bit DONE is set C The third criteria for buffer switching is the automatic buffer switching on detection of SOF see figure 6 37 This feature can be individually enabled SOFDE 1 or disabled SOFDE 0 by software selectively for each endpoint Semiconductor Group 6 46 1997 10 01 On Chip Peripheral Components IE SIEMENS C540U C541U 6 4 3 USB Memory Buffer Organization The address generation of the USB memory buffer is based on address offset and base address pointer This scheme allows flexible and application specific buffer allocation and management The length of an endpoint buffer can be up to 8 16 32 or 64 bytes The start address of each endpoint buffer can be located to memory locations according table 6 9 Table 6 9 USB Buffer Length and Base Addresses Values
48. the idle mode respectively If the power down mode and the idle mode are set at the same time power down takes precedence Furthermore register PCON contains two general purpose flags For example the flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle Then an instruction that activates idle can also set one or both flag bits When idle is terminated by an interrupt the interrupt service routine can examine the flag bits Semiconductor Group 9 1 1997 10 01 SIEMENS Power Saving Modes C540U C541U Special Function Register PCON Address 874 Reset Value X00X0000p Special Function Register PCON1 Mapped Address 88H Reset Value OXXOXXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 87H PDS IDLS GF1 GFO PDE IDLE PCON 884 EWPD WS PCON1 The function of the shaded bit is not described in this section Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting of the power down is enabled IDLE Idle mode enable bit When set starting of the idle mode is enabled EWPD External wake up fr
49. the ports 1 2 and 3 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters and in the C540U C541U DC characteristics specify these currents Port 0 has floating inputs when used for digital input Semiconductor Group 6 11 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 1 3 3 Read Modify Write Feature of Ports 1 2 and 3 Some port reading instructions read the latch and others read the pin The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in table 6 6 If the destination is a port ora port pin these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin respectively is performed by reading the SFR PO P1 P2 and P3 for example MOV A P3 reads the value from port 3 pins while ANL P3 0AAH reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in table 6 6 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch
50. used Further the inputs PMSEL1 0 are required to select the access types e g program verify data write lock bits in the programming mode In programming mode Vcc Vss and a clock signal at the XTAL pins must be applied to the C541U The 11 5V external programming voltage is input through the EA Vpp pin Figure 10 2 shows the pins of the C540U C541U which are required for controlling of the OTP programming mode PMSELO EA Vpp PMSEL1 PROG PRD RESET PSEN PSEL MCS03386 Figure 10 2 C540U C541U Programming Mode Configuration Semiconductor Group 10 1 1997 10 01 SIEMEN OTP Memory Operation gt C540U C541U 10 2 Pin Configuration Figure 10 3 shows the detailed P LCC 44 pin configuration of the C540U C541U in programming mode Figure 10 4 shows the detailed P SDIP 52 pin configuration C540U 35 1 EA Vpp C541U Programming Mode MCP03387 Figure 10 3 P LCC 44 Pin Configuration of the C540U C541U in Programming Mode top view Semiconductor Group 10 2 1997 10 01 SIEMENS OTP Memory Operation C540U C541U Figure 10 4 N C N C N C N C N C N C N C N C N C Voc Vss RESET PMSELO N C N C PMSEL PSEL PRD PALE GND GND GND XTAL2 XTAL1 Vss Voc C540U C541U Programming Mode NC P1 5 SLS DO D1 D2 D3 D4 D5 D6 D7 N C N C N C N C A7 A6 A5 M A12 A8 A11 A21 A10 A1 A9 A0 A8 N C MCP0
51. 10 12 RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the C540U C541U A small internal pulldown resistor permits power on reset using only a capacitor connected to Vcc P3 0 P3 7 11 13 19 13 16 22 I O Port 3 is an 8 bit quasi bidirectional I O port with internal pullup resistors Port 3 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current 7 y in the DC characteristics because of the internal pullup resistors Port 3 also contains the interrupt timer serial port and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows P3 0 LED2 LED2 output P3 1 DADD Device attached input P3 2 INTO External interrupt 0 input timer O gate control input External interrupt 1 input timer 1 gate control input Timer 0 counter input Timer 1 counter input WR control output latches the data byte from port 0 into the external data memory RD control output enables the external data memory P3 3 INT1 P3 4 TO P3 5 T1 P3 6 WR P3 7 RD XTAL2 20 23 XTAL2 is the output of the inverti
52. 11 1 11 1 Absolute Maximum Balls sacar nto e eee a be 11 1 11 2 DG Gharactersil6S 2 aes vedas cleat Geeta ens 11 2 11 3 PG CGh aracteristi S s ots v esac ce Gi asia ut un el ete ae ec eel o A e Fon Staa td 11 4 11 4 AC Characteristics of Programming Mode 0000e0 cetera 11 12 11 5 OTP Verification Characteristics a gna ok eoe IRE RO ee Dep Va wea 11 16 11 6 USB Transceiver Characteristics liiis 11 17 11 7 Package Information uk wex Re Ret RELIER lee EXER EUN 11 20 12 Ndek cuis E eo M EERsxRE ERE ERE EXE 12 1 Semiconductor Group l 3 SIEMENS Introduction C540U C541U 1 Introduction The C540U and C541U are members of the Siemens C500 family of 8 bit microcontrollers They are fully compatible to the standard 80C51 architecture The C540U C541U especially provide an on chip USB module compliant to the USB specification which is capable to operate either in low or full speed mode The five endpoints can be easily controlled by the CPU via special function registers Due to the on chip USB transceiver circuits the C540U C541U can be directly connected to the USB bus Figure 1 1 shows the different functional units of the C540U C541U and figure 1 2 shows the simplified logic symbol of the C540U C541U Oscillator Watchdog Watchdog Timer SSC USB Module OTP Prog Memory pe ts C540U 4 kx8 USB Transceiver C541U 8kx8 2 2 o o t o o o gt o c 2 E
53. 1U 11 7 Package Information Plastic Package P LCC 44 1 SMD Plastic Leaded Chip Carrier Package 12 038 x 45 074t0 07 eT O MEE Et ff 15 5105 17 53 013 A 4 Index Marking 0 5 MAX x45 LL 1150085 x 45 166 057 17 53 043 1 0 05 A B D 1 Does not include plastic or metal protrusion of 0 15 max per side Figure 11 27 P LCC 44 1 Package Outline Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Dimensions in mm Semiconductor Group 11 20 1997 10 01 SIEMEN Device Specifications gt C540U C541U Plastic Package P SDIP 52 1 Plastic Shrink Dual In Line Package 15 24 199 14 02 02 9 0 25 0 05 1524 t7 45 97 95 9 Index Marking 1 Does not include plastic or metal protrusion of 0 25 max per side Figure 11 28 P SDIP 52 1 Package Outline Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information Dimensions in mm Semiconductor Group 11 21 1997 10 01 Device Specifications SIEMENS C540U C541U Semiconductor Group 11 22 1997 10 01 SIEMENS meee C540U C541U 12 Index BHS0s scher AAT ESETSR AVE 3 6 6 28 Not
54. 20 ns High speed mode fall time ler 4 20 ns Low speed mode rise time lig 75 300 ns Low speed mode fall time fie 75 300 ns Semiconductor Group 11 17 1997 10 01 IE Device Specifications SIEMENS C540U C541U 0 2 V c 0 9 Test Points 0 45 V MCT00039 AC Inputs during testing are driven at Voc 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at Vii for a logic 1 and Vi ma for a logic 0 Figure 11 23 AC Testing Input Output Waveforms Timing Reference Points VoL 40 1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vo Vo level occurs Ig Ig 2 X 20 mA Figure 11 24 AC Testing Float Waveforms CL 2 50 pF full speed CL 2 50 pF low speed min timing CL 850 pF low speed max timing 1 5 kQ on D low speed or D full speed only MCS03425 Figure 11 25 Load for D D Semiconductor Group 11 18 1997 10 01 SIEMENS Device Specifications C540U C541U Crystal Oscillator Mode C i XTAL2 Baio ils MHz XTAL1 Crystal Mode C 20 pF 10 pF Incl Stray Capacitance Figure 11 26 Driving from External Source External Oscillator Signal MCS03426 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 11 19 1997 10 01 SIEMEN Device Specifications x C540U C54
55. 3388 P SDIP 52 Pin Configuration of the C540U C541U in Programming Mode top view Semiconductor Group 10 3 1997 10 01 IE OTP Memory Operation SIEMENS C540U C541U 10 3 Pin Definitions The following table 10 2 contains the functional description of all C540U C541U pins which are required for OTP memory programming Table 10 2 Pin Definitions and Functions in Programming Mode Symbol Pin Numbers 1 0 Function P LCC 44 P SDIP 52 RESET 10 12 Reset This input must be at static 1 active level during the whole programming mode PMSELO 11 13 Programming mode selection pins PMSEL1 13 16 These pins are used to select the different access modes in programming mode PMSEL1 0 must satisfy a setup time to the rising edge of PALE When the logic level of PMSEL1 0 is changed PALE must be at low level PMSEL PMSEL Access Mode 1 0 0 0 Reserved 0 1 Read version bytes 1 0 Program read lock bits 1 1 Program read OTP memory byte PSEL 14 17 Basic programming mode select This input is used for the basic programming mode selection and must be switched according figure 10 5 PRD 15 18 Programming mode read strobe This input is used for read access control for OTP memory read version byte read and lock bit read operations PALE 16 19 Programming mode address latch enable PALE is used to latch the high address lines The high address lines must satisf
56. 500 microcontrollers This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON RSYSCON TCON RTCON TCON RTCON C500 Enhanced Hooks MCU Interface Circuit Optional m 1 0 Ports Port3 Port RPort2 RPort0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4 2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware ICE system and the C500 MCU 1 Enhanced Hooks Technology is a trademark and patent of Metalink Corporation licensed to Siemens Semiconductor Group 4 5 1997 10 01 External Bus Interface SIEMENS C540U C541U Semiconductor Group 4 6 1997 10 01 IE Reset System Clock SIEMENS C540U C541U 5 Reset and System Clock Operation 5 1 Hardware Reset Operation The hardware reset function incorporated in the C540U C541U allows for an easy automatic start up at a minimum of additional hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This
57. 7 must be stable when PROG is low or PRD is low If subsequent OTP address locations are accessed with constant address information at the high address lines A8 12 A8 A12 must only be latched once page address mechanism Figure 10 6 shows a typical OTP memory programming cycle with a following OTP memory read operation In this example A0 A12 of the read operation are identical to A8 A12 of the preceeding programming operation For the C540U address line A12 is not required PMSEL1 0 1 1 Por SC nS iu 1 A8 A12 Port 0 Do D7 min 100 us e 0 ns PRD MCT03419 Figure 10 6 C541U Programming VerifyOTP Memory Access Waveform If the address lines A8 A12 must be updated PALE must be activated for the latching of the new A8 A12 value Control address and data information must only be switched when the PROG and PRD signals are at high level The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode Semiconductor Group 10 8 1997 10 01 IE OTP Memory Operation SIEMENS C540U C541U Figure 10 7 shows a waveform example of the program read mode access for several OTP memory bytes In this example OTP memory locations 3FDy to 4004 are programmed Thereafter OTP memory locations 4004 and 3FDy are read PMSEL1 0 A PALE 3FD 3FE 3FF 400 400 3FD 719 ro re rr jo o o jo ro pz el eg Eud 0 0 cel be MC
58. AA 3 2 3 3 General Purpose Registers 0 00000 c eee eee 3 2 3 4 Special Function Registers sione Oe on twee eos Pv Oe e Do bn 3 3 4 External Bus Interface ees criar 4 1 4 1 Accessing External Memory 0 000 e eee tees 4 1 4 1 1 Role of PO and P2 as Data Address BUS 000 eee es 4 1 4 1 2 SERIO oett uq ue Cee Seat Me near tn Rake Clu Ga E E Mo ge 4 3 4 1 3 External Program Memory Access 00 000 eee eee eens 4 3 4 2 PSEN Program Store Enable oro opu cies oad be LE nM 4 3 4 3 Overlapping External Data and Program Memory Spaces 4 3 4 4 ALE Address Latem Enable ce et Soe Raa ei 4 4 4 5 Enhanced Hooks Emulation Concept 0000 cece eee eee 4 5 5 Reset and System Clock Operation ooooooococccnn o 5 1 5 1 Hardware Reset Operation o ooocccococcco eee 5 1 5 2 Fast Internal Reset after Power On 00000 cece eee eens 5 3 5 9 Hardware Reset TIMING esse RE Cha e RE ek pes ERE ERE REY ER 5 5 5 4 Oscillator and Clock GIFGUIL o oot xe dr DEDE EROR SON Oo S cya ware 5 6 6 On Chip Peripheral Components 000 00 ce cece ee eee eee 6 1 6 1 Parallel lO ecc or med ett fa odie IE e Ev pe e indie dd 6 1 6 1 1 POR SUUCIUICS as us edu ara Ut edi sem eee son obe loe NEG ER eta es 6 2 6 1 1 1 Port 0 and Port 2 used as Address Data Bus oooccoccccooo 6 7 6 1 2 Alternate FUNCTIONS ubiera A e G 6 8 6 1 3 POR Handing s ius des aont adus bue E MH Abi P
59. B ea i a Fa AE PCH DPH OUT OR PCH OUT P2 OUT OUT DATA ro AN He A ou An A A A PCL OUT DPL or Ri PCL OUT valid valid valid MCT03220 Figure 4 1 External Program Memory Execution Semiconductor Group 4 2 1997 10 01 IE External Bus Interface S MENS C540U C541U 4 1 2 Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustated in figure 4 1 a and b Data memory in a write cycle the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port O before the read strobe is deactivated Program memory Signal PSEN functions as a read strobe 4 1 3 External Program Memory Access The external program memory is accessed under two conditions whenever signal EA is active low or whenever the program counter PC content is greater than 7FFFy When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and must not be used for general purpose l O The content of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the
60. B device is in suspend mode setting bit RSM resumes bus activity of the device In response to this action the USB will disassert the suspend bit and will perform the remote wake up operation Writing 0 to RSM has no effect the bit is reset if bit SUSP is 0 UCLK UDC clock selection Bit UCLK controls the functionality of the USB core clock in full speed mode SPEED 1 as well as in low speed mode SPEED 0 If UCLK 0 the USB core clock 48 MHz or 6 MHz is disabled If UCLK 1 the USB core clock 48 MHz or 6 MHz is enabled PCLK PLL clock select Bit PCLK controls the 48 MHz PLL If PCLK 0 the 48 MHz PLL is disabled default after reset If PLCK 1 the 48 MHz PLL is enabled For power consumption and EMI reasons the 48 MHz PLL should be disabled in low speed mode SPEED 0 Semiconductor Group 6 58 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U The device power down register DPWDR includes two bits which allow to switch off the USB transmitter and receiver circuitry selectively for power down mode operation USB Device Power Down Register DPWDR Address C2py Reset Value 00y BitNo MSB LSB 6 5 4 3 2 1 0 C2y 0 0 0 0 0 TPWD RPWD DPWDR r r r r r rw rw Bit Function TPWD USB Transmitter Power Down Setting bit TPWD puts the USB transmitter into power down mode After a wake up from software power down mode operation bit TPWD must be cleared by s
61. Bit Function Not implemented Reserved for future use EALE Enable ALE output EALE 0 ALE generation is disabled disables ALE signal generation during internal code memory accesses EA 1 With EA 1 ALE is automatically generated at MOVX instructions and code memory accesses with an address greater OFFFy C540U or greater 1FFFy EALE 1 ALE generation is enabled If EA 0 the ALE generation is always enabled and the bit EALE has no effect on the ALE generation Semiconductor Group 4 4 1997 10 01 SIEMEN External Bus Interface 3 C540U C541U 4 5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each C500 production chip has built in logic for the supprt of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensures that emulation and production chips are identical The Enhanced Hooks Technology 1 which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C
62. Bit2 Bit 1 Bit 0 Value EPSEL 0XXX X010g Endpoint 2 Registers Ciy EPBC2 00y STALL2 0 0 GEPIE2 SOFDE2 INCE2 0 DBM2 C24 EPBS2 20y UBF2 CBF2 DIR2 ESP2 SETRD2 SETWR2 CLREP2 DONE2 C34 EPIE2 00H AIE2 NAIE2 RLEIE2 DNRIE2 NODIE2 EODIE2 SODIE2 C44 EPIR2 10H ACK2 NACK2 RLE2 DNR2 NOD2 EOD2 SOD2 C5y EPBA2 00y PAGE2 0 0 0 A62 A52 A42 A32 C6y EPLEN2 OXXX 0 L62 L52 L42 L32 L22 L12 Lo2 XXXXp C7y reserved EPSEL 0XXX X011g Endpoint 3 Registers Ciy EPBC3 00H STALL3 0 0 GEPIE3 SOFDE3 INCE3 0 DBM3 C2y EPBS3 20H UBF3 CBF3 DIR3 ESP3 SETRD3 SETWR3 CLREP3 DONES3 C3y EPIE3 00H AIE3 NAIE3 RLEIE3 DNRIE3 NODIE3 EODIES SODIE3 C4y EPIR3 10H ACK3 NACK3 RLE3 DNR3 NOD3 EOD3 SODS3 C5H EPBAS 00y PAGES 0 0 0 A63 A52 A43 A33 C6y EPLEN3 OXXX 0 L63 L53 L43 L33 L23 L13 L03 XXXXB C74 reserved EPSEL 0XXX X100g Endpoint 4 Registers Cip EPBC4 004 STALL4 O 0 GEPIE4 SOFDE4 INCE4 0 DBM4 C24 EPBS4 20y UBF4 CBF4 DIR4 ESP4 SETRD4 SETWR4 CLREP4 DONE4 C34 EPIE4 004 AlE4 NAIEA RLEIE4 DNRIE4 NODIE4 EODIE4 SODIE4 C44 EPIR4 104 ACK4 NACK4 RRLE4 4 DNR4 NOD4 EOD4 SOD4 C5y EPBA4 00y PAGE4 0 0 0 A64 A54 A44 A34 C6y EPLEN4 OXXX 0 L64 L54 L44 L34 L24 L14 L04 XXXXp C7y reserved Semiconductor Group 3 9 1997 10 01 SIEM ENS Memor
63. D is set at 3 to indicate a full buffer The USB memory buffer address offset is automatically incremented with every CPU write access to USB memory buffer if bit INCE is set During the next frame after SOF n 1 is set at 4 the USB memory buffer can be read by the USB Bit SOD is set again when the USB memory buffer becomes empty again If bit DONE is set by the CPU at 5 the buffer is declared by the CPU to be full even if the address offset does not reach the value of MaxLen Number of Data Bytes in USB Buffer A MaxLen o Y A A Frame Frame n 1 Mee ie ern SOF n 1 SOF n 2 Set Set V A USB read Accesses ES CPU write Accesses MCT03403 Figure 6 30 Single Buffer Mode Standard USB Read Access Semiconductor Group 6 38 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U The start of frame done enable feature SOFDE 1 is useful for USB memory read accesses when the number of data bytes to be transferred from CPU to USB is not predictable see figure 6 31 The CPU can write data as desired to USB memory until a SOF occures every 1 ms The automatic setting of bit SOF causes bit EOD to be set at 1 This indicates the CPU that no CPU action on this buffer is required until a USB read operation has been finished bit SOD set at 2 Setting of SOD indicates an empty USB memory to the CPU which can start again writing data into USB memory Number of Data Bytes in USB
64. DIER USB Device Interrupt Control Register C3H 00H DIRR USB Device Interrupt Request Register C4y 00H FNRL USB Frame Number Register Low Byte C6y XXH FNRH USB Frame Number Register High Byte C7H 00000XXXp EPBCn USB Endpoint n Buffer Control Register Cip 00H EPBSn USB Endpoint n Buffer Status Register C2y 20H EPIEn USB Endpoint n Interrupt Enable Register C3y 00H EPIRn USB Endpoint n Interrupt Request Register C44 10y 9 EPBAn USB Endpoint n Base Address Register C5H 00H EPLENn USB Endpoint n Buffer Length Register C6H OXXXXXXXB 1 These register are multiple registers n 0 4 with the same SFR address selection of register n is done by SFR EPSEL 2 The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset 3 The reset value of EPIRO is 11g Semiconductor Group 1997 10 01 SIEMENS Memory Organization C540U C541U Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses Addr Register Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 Value 804 PO FFH 7 6 iS 4 ES 2 1 0 814 SP 07 7 6 5 4 3 2 1 0 824 DPL 00 7 6 iB 4 3 2 E 0 834 DPH 00H 7 6 5 4 3 2 1 0 8649 WDTREL 00y WDT 6 5 4 3 2 1 0 PSEL 874 PCON X00X PDS IDIS GF1 GFO PDE IDLE 0000p 884 TCON 00H TF1 TR1 BED TRO IE1 IT1 IEO ITO 884 PCON1 0XXO EWPD WS
65. E OTP Memory Operation SIEMENS C540U C541U 10 7 Access of Version Bytes The C540U C541U provides three version bytes at address locations FCy FDy and FEy The information stored in the version bytes is defined by the mask of each microcontroller step Therefore the version bytes can be read but not written The three version bytes hold information as manufacturer code device type and stepping code For reading of the version bytes the control lines must be used according table 10 3 and figure 10 9 The address of the version byte must be applied at the port 1 address lines PALE must not be activated PMSEL10 ZY WY PALE Pre ZA rc Fo FE PROG PRD MCT03422 Figure 10 9 Read Version Byte s Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specifc device characteristics such as OTP size etc Note The 3 version bytes are implemented in a way that they can be also read during normal program execution mode as a mapped register with bit RMAP in SFR SYSCON set The addresses of the version bytes in normal mode and programming mode are identical and therefore they are located in the SFR address range The first step of the C540U C541U will contain the following information at the version bytes Name Address Value Version Byte 0 FCH C5H Version Byte 1 FDH Ciy Version Byte 2 FEH 01y Future steppings of the C540U C541U w
66. ED e EN 3 8 SODIET ee 3 8 BEBE E E 3 8 SODIE2 1 eee eee eee eee 3 9 Lu o T 3 9 SODIES 6 eee eee eee 3 9 BUE Ac Eros er buc Ea 3 9 SODIE4 eee eee eee eee 3 9 RULEA REDE 3 9 SODIEn cesses 6 69 7 7 REE ros con code 3 8 SODN 0 sees eee 6 71 7 12 A E ERT 3 8 SOFDEO e aani AE EAEE 3 8 RULE tesiei oros de iens 3 9 SOFDE1 cococccconocrrr rr 3 8 HUEIESS aee Eher SupOUUS 3 9 SOFDE2 esses 3 9 zz pe 3 9 SOFDES 6 cece eee eee ees 3 9 RLEIEN d ias 6 68 7 7 SOFDE4 0 eee eee 3 9 PAE A Sa beet A 6 70 7 12 SORDEN vt vical Ea 6 64 RMAP cen ke tO ibe dk be EOS iis 3 3 3 7 10 de 3 8 6 62 7 11 RPWD PEE ERLEE 3 8 6 59 SOFIE esses 3 8 6 61 7 6 PSO mM T 2 3 3 7 SP 2 3 3 4 3 6 BOT m Aia ric nri 2 3 3 7 Special Function Registers 3 3 ij pa 3 8 6 58 Access with RMAP 3 3 S Table address ordered 3 6 to 3 9 SBI uted tent Aedes oe 3 8 6 62 7 11 Table functional order 3 4 to 3 5 S cet see ened 3 3 660 76 SEED scswsteeuseebsnense 3 8 6 57 A 0027 PP phe SCE CEN 3 4 3 6 6 30 7 10 SP occur q e ree 3 6 6 21 SCIEN LLL 3 4 3 7 6 29 7 5 SSG Interface soe rtm 6 21 to 6 31 ob CORRER 3 6 6 21 Baudrate generation 6 23 CO AMORC ARR 3 8 6 62 7 11 BOO ala gra se pre pue OIE hoo acd ae ALL neste 3 8 6 60 7 6 General operation 6 22 O M int 3 8 6 62 7 11 MASSE Toup MINING saan ses ee GEIS incre cy emac
67. ENS C540U C541U The register EPIRn n 0 4 contains USB endpoint specific interrupt request flags This SFR is availble for each endpoint If a request flag in EPIRn is set it is automatically cleared after a read operation of the EPIRn register Endpoint Interrupt Request Register EPIRn n 0 4 Address C4y Reset Value EPIRO 115 Reset Value EPIR1 to EPIR4 10H Bit No MSB LSB 7 6 5 4 3 2 1 0 C4y ACKn NACKn RLEn DNRn NODn EODn SODn EPIRn r r r r r r r r For accessing EPIRn SFR EPSEL must be Ong Bit Function ACKn USB acknowledge Bit ACKn 1 indicates a succesful action on the USB NACKn USB not acknowledge Bit NACK is set for all unsuccessful actions on the USB RLEn Read length error Bit RLEn is automatically set if the number of bytes read by the USB does not correspond to the packet length programmed by the CPU Reserved bit for future use DNRn Data not ready This bit is set by hardware if the USB module requires an access to USB memory but no buffer is available NODn No data This bit indicates an incorrect CPU read or write access to USB memory EODn End of data During an USB read access EOD is set if the CPU has written a programmable number of bytes in the transmit buffer During an USB write access EOD is set if the CPU has read a programmable number of bytes out of the receive buffer SODn Start of data During an USB read
68. EWPD enable wake up from power down mode in SFR PCONI is set If these two conditions are met and when the oscillator watchdog unit start up phase after a wake up condition INTO 0 is finished the C540U C541U starts with an interrupt at address 007By All other interrupts are now disabled until the RETI instruction of the power down interrupt routine has been executed Semiconductor Group 7 17 1997 10 01 IE Interrupt System SIEMENS C540U C541U 7 4 External Interrupts The external interrupts 0 and 1 can be programmed to be level activated or transition activated by setting or clearing bit ITO or IT1 in register TCON If ITx 0 x 0 or 1 external interrupt x is triggered by a detected low level at the INTx pin In edge triggered mode ITx two bits of the ITCON register define the type of signal transition for which the external interrupt inputs are sensitive Edge triggered interrupt can be activated for an interrupt input signal at the rising edge atthe falling edge or at both signal transitions In edge triggered mode if successive samples of the INTx pin show a different logic level in two consequent machine cycles the corresponding interrupt request flag IEx in TCON is set Flag bit IEx 1 then requests the interrupt If the external interrupt O or 1 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the inter
69. En SODIEn EPIEn rw rw rw rw rw rw rw rw For accessing EPIEn SFR EPSEL must be Ony Bit Function AlEn USB acknowledge interrupt enable Bit AlEn enables the generation of an endpoint specific acknowledge interrupt when bit ACKn in register EPIRn is set If AIEn 0 the USB acknowledge interrupt is disabled If AlEn 1 the USB acknowledge interrupt is enabled NAIEn USB not acknowledged interrupt enable Bit NAIEn enables the generation of an endpoint specific not acknowledged interrupt when bit NACKn in register EPIRn is set If NAIEn 0 the USB not acknowledged interrupt is disabled If NAIEn 1 the USB not acknowledged interrupt is enabled RLEIEn Read length error interrupt enable Bit RLEIEn enables the generation of an endpoint specific read length error interrupt when bit RLEn in register EPIRn is set If RLEIEn 0 the read length error interrupt is disabled If RLEIEn 1 the read length error interrupt is enabled Reserved bit for future use DNRIEn Data not ready interrupt enable Bit DNRIEn enables the generation of an endpoint specific data not ready interrupt when bit DNRn in register EPIRn is set If DNRIEn 0 the data not ready interrupt is disabled If DNRIEn 1 the data not ready interrupt is enabled NODIEn No data interrupt enable Bit NODIEn enables the generation of an endpoint specific no data interrupt when bit NODn in register EPIRn is set If NODIEn O the no data interrupt is disabled
70. Fail save mechanisms 8 1 to 8 7 Request flagS 7 9 Fast power on reset 5 3 8 7 Response tiMe 7 20 FOROS coi ea PECORE P ere 1 2 Sources and vector addresses 7 17 ENRIO D oooooocoooocoo o 3 8 6 63 IPO eee eee eee eee 3 4 3 7 7 14 ENEBEB nica perra s 3 5 3 8 6 63 ls Tcr DT 3 4 7 14 FNB 55 amo sot rasta 3 5 3 8 6 63 LTD es on iue o io A sent 3 6 7 9 Functional units 05 1 1 IPs 3 6 7 9 Fundamental structure 2 1 ITCON ooo 3 4 3 6 7 19 G L EA AIR A 3 6 6 16 E006 L 00 1d teg 3 8 6 72 GEPIEO Ge uice hi oam ot Lar get 3 8 LIG LI0 0 eee eee eee 3 8 6 72 GEPIE T o acsiso odetipa i reme red 3 8 L26 L20 occ 3 9 6 72 GEPIES oeste best etes s n 3 9 L36 L30 1 0 0 eee eee 3 9 6 72 O dak D db toed 3 9 L46 L40 esee 3 9 6 72 GEPIEA ae te ee ee culo rante 3 9 REDO sos d 431 eN EX 3 6 GEPIEH oc ccd eke eek IDE 6 64 7 8 LED cscs iR TEGERE UMS 3 6 GEPIR 151 22 5 os 3 5 3 7 6 56 7 13 L ED2 Sosa cia a aaa 3 7 Fis a tot 3 6 9 2 Logic symbol oocoocoooomoo gt 1 3 Ela pablo bbs 3 6 9 2 LOOPB 05 3 6 6 31 H ESBSM AAA ae a XR wR 3 6 6 31 Hardware reset oo o 5 1 M I c T 3 6 6 16 VO POS risa eg coja sordes 6 1 to 6 12 Misses E COE ETE 3 06 86 foci SEPAN Oe AAT 3 6 7 19 Memory organization 3 1 eee eee T 3 6 7 19 Dara MEMO Seine LE oe METE vrai tu p r
71. LA PO PCL Inst M PCL OUT in OUT PCH PCH ALE MCT02092 Figure 5 5 CPU Timing after Reset Semiconductor Group 5 5 1997 10 01 SIEMENS Reset System Clock C540U C541U 5 4 Oscillator and Clock Circuit The oscillator and clock generation circuitry of the C540U C541U is shown in figure 5 6 The crystal oscillator generates the system clock for the microcontroller The USB module can be provided with the following clocks Full speed operation 48 MHz with a data rate of 12 Mbit s Low speed operation 6 MHz with a data rate of 1 5 Mbit s The low speed clock is generated by a dividing the system clock by 2 The full speed clock is generated by a PLL which multiplies the system clock by a fix factor of 4 This PLL can be enabled or disabled by bit PCLK of SFR DCR Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock Bit UCLK is a general enable bit for the USB clock XTAL1 System Clock 12 MHz gt Bie of the scillator Microcontroler XTAL2 Divider by 2 to USB Module C540U C541U DCR 7 DCR 1 MCB03377 Figure 5 6 Block Diagram of the Clock Generation Circuitry In low speed mode the PLL is not required Therefore the PLL should be always disabled in low speed mode This also reduces the power consumption and the EMC of the C540U C541U when used in low speed mode Note For correct function
72. NCEn 0 DBMn EPBCn rw r r rw rw rw r rw Bit Function STALLn Endpoint stall Bit STALL can be set to indicate that the endpoint is stalled If STALL 0 the endpoint n is active If STALL 1 the endpoint n is stalled Note If the stall bit for endpoint O STALLO is set the next incoming setup token will automatically clear it GEPIEn Global endpoint interrupt enable Bit GEPIEn enables or disables the generation of the global endpoint interrupt n based on the endpoint specific interrupt request bits in register EPIRn If GEPIE 0 the USB endpoint n interrupt is disabled If GEPIE 1 the USB endpoint n interrupt is enabled SOFDEn Start of frame done enable If bit SOFDE is set the current CPU buffer in USB memory is automatically tagged full data flow from the CPU to the USB or empty data flow from the USB to the CPU on each detection of a start of frame on the USB auto done If SOFDE 0 no action on SOF If SOFDE 1 the automatical generation of DONE on SOF is enabled Semiconductor Group 6 64 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Bit Function INCEn Auto increment enable If bit INCE is set the address offset register ADROFF for CPU access to USB memory is automatically incremented after each data write or data read action of the USBVAL register This allows the user to handle the USB memory like a FIFO without modification of the address of the desired memory location
73. O 7 43 38 50 43 O Data lines 0 7 During programming mode data bytes are read or written from or to the C540U C541U via the bidirectional DO 7 lines which are located at port 0 Vas 9 22 11 25 Circuit ground potential must be applied to these pins in programming mode Voc 8 23 10 26 Power supply terminal must be applied to these pins in programming mode N C 1 12 1 9 14 Not Connected 34 44 15 27 36 These pins should not be connected in programming 37 40 41 mode 52 GND 17 19 20 22 Ground pins In programming mode these pins must be connected to V level Input O Output Semiconductor Group 10 5 1997 10 01 SIEMEN OTP Memory Operation P C540U C541U 10 4 Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts Basic programming mode selection Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic Further after selection of the basic programming mode OTP memory accesses are executed by using one of the access modes These access modes are OTP memory byte program read version byte read and program read lock byte operations 10 4 1 Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 10 5 Voc mae XTAL2 UM Stable st es T o LA gt
74. O ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 10 MHz clock Variable Clock Duty Cycle 1 CLP 2 MHz to 0 4 to 0 6 12 MHz min max min max ALE pulse width finu 43 CLP 40 ns Address setup to ALE favi 13 TCLymin 20 ns Address hold after ALE tax 13 TCLumin 20 ns ALE to valid instruction in tow 80 2 CLP 87 ns ALE to PSEN fp 13 TCL min 20 ns PSEN pulse width pi phi 86 CLP ns TCLumin 30 PSEN to valid instruction in fpi 51 CLP ns TCLymin 65 Input instruction hold after PSEN texiy 0 0 ns Input instruction float after PSEN toxiz 23 TCL min 10 ns Address valid after PSEN texa 28 TCLimin 5 ns Address to valid instruction in Laviv 140 2 CLP ns TCLumin 60 Address float to PSEN AZPL 0 0 ns Interfacing the C540U C541U to devices with float times up to 28 ns is permissible This limited bus contention will not cause any damage to port 0 drivers 7 For correct function of the USB module the C540U C541U must operate with 12 MHz external clock The microcontroller except the USB module operates down to 2 MHz Semiconductor Group 11 4 1997 10 01 SIEMENS Device Specifications C540U C541U AC Characteristic
75. P Verification Characteristics OTP Verification Mode for Protection Level 1 Parameter Symbol Limit Values Unit min typ max ALE pulse width Tawo 2 tere ns ALE period tacy 12 faic ns Data valid after ALE Tova 4 feci ns Data stable after ALE Losa 8 fora ns P3 5 setup to ALE low Tas Toei ns Oscillator frequency lao 4 6 MHz CERA Duevad MCT02613 Figure 11 22 OTP Verification Mode for Protection Level 1 Semiconductor Group 11 16 1997 10 01 SIEMENS Device Specifications C540U C541U 11 6 USB Transceiver Characteristics Voc 4 0V to 5 5V 5V 41096 20 Vss 0 V T 0 to 70 C Parameter Symbol Limit Values Unit Test Condition min max Output impedance high state Row 28 43 Q 1 Output impedance low state Rov 28 51 Q Input leakage current I ED uA Vin Vss Or Vec Tristate output off state current loz t uA Vout Vss or Vec Y Crossover point Vcn 1 3 2 0 V 2 Notes 1 This value includes an external resistor of 30Q 1 see Load for D D diagram for testing details 2 The crossover point is in the range of 1 3V to 2 0V for the high speed mode with a 50pF capacitance In the low speed mode with a 100pF or greater capacitance the crossover point is in the range of 1 3V to 2 0V Parameter Symbol Limit Values Unit min max High speed mode rise time ler 4
76. RDn or SETWRn simultaneously with one instruction is not allowed This means that the information of SETRDn or SETWRn is ignored in this case DONEn Buffer done by CPU If bit DONE is set the current USB memory buffer assigned to CPU is automatically tagged full data flow from the CPU to the USB or empty data flow from the USB to the CPU This bit is reset by hardware after it has been set A read operation on this bit will deliver always 0 Note If the direction of endpoint n is read USB read access and auto increment is enabled INCEn 1 and DONEn is set the content of register ADROFF is copied automatically to register EPLENn of the actual endpoint Register EPLENn is not changed if the auto increment capability is disabled INCEn 0 Semiconductor Group 6 67 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U The endpoint interrupt enable registers contain the endpoint specific interrupt enable bits With these bits the endpoint specific interrupts can be individually enabled or disabled Additionally to a bit in an EPIEn register the global interrupt bit EPIn in GEPIR for endpoint n and the general endpoint interrupt bit EUEI in IEN1 and the general interrupt enable bit EA in IENO must be set for the interrupt becoming active Endpoint Interrupt Enable Register EPIEn n 0 4 Address C3 Reset Value 00H BitNo MSB LSB 7 6 5 4 3 2 1 0 C3H NAIEn RLEIEn DNRIEn NODIEn EODI
77. SIEMENS C540U C541U 8 Bit CM OS M icrocontroller User s Manual 10 97 C540U C541U User s Manual Revision History 1997 10 01 Previous Releases Original Version Page Page Subjects changes since last revision previous new version version Edition 1997 10 01 Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the cos
78. T03420 Figure 10 7 Typical OTP Memory Programming Verify Access Waveform Semiconductor Group 10 9 1997 10 01 IE OTP Memory Operation SIEMENS C540U C541U 10 6 Lock Bits Programming Read The C540U C541U has two programmable lock bits which when programmed according tabie 10 4 provide four levels of protection for the on chip OTP code memory The state of the lock bits can also be read Table 10 4 Lock Bit Protection Types Lock Bits at D1 DO Protection Protection Type D1 DO Level 1 1 Level 0 The OTP lock feature is disabled During normal operation of the C540U C541U the state of the EA pin is not latched on reset 1 0 Level 1 During normal operation of the C540U C541U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset An OTP memory read operation is only possible using the OTP verification mode for protection level 1 Further programming of the OTP memory is disabled reprogramming security 0 1 Level 2 Same as level 1 but also OTP memory read operation using OTP verification mode is disabled 0 0 Level 3 Same as level 2 but additionally external code execution by setting EA Iow during normal operation of the C540U C541U is no more possible External code execution which is initiated by an internal program e g by an internal jump instruction above the ROM boundary is still possible
79. TP verification mode The first data byte to be verified is always the byte which is assigned to the internal OTP address 0000H and must be put onto the data bus with the first ALE pulse after the falling edge of RESET With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next OTP address must be delivered externally Between two ALE pulses the data at port 0 is latched at 3 CLP after ALE rising edge and compared internally with the OTP content of the actual address If an verify error is detected the error Semiconductor Group 10 13 1997 10 01 IE OTP Memory Operation SIEMENS C540U C541U condition is stored internally After each 16th data byte the cumulated verify result pass or fail of the last 16 verify operations is output at P3 5 This means that P3 5 stays at static level low for fail and high for pass during the time when the following 16 bytes are checked In OTP verification mode the C540U C541U must be provided with a system clock at the XTAL pins Figure 10 11 shows an application example of a external circuitry which allows to verify a protected OTP inside the With RESET going inactive the C540U C541U starts the OTP verify sequence Its ALE is clocking an 14 bit address counter This counter generates the addresses for an external EPROM which is programmed with the content of the internal protected OTP The verify detect logic typically displays the state of t
80. USB not acknowledged interrupt is enabled RLEIEn USB read length error interrupt enable If RLEIEn 0 the USB read length error interrupt is disabled If RLEIEn 1 the USB read length error interrupt is enabled Reserved bit for future use DNRIEn USB data not ready interrupt enable If DNRIEn 0 the USB data not ready interrupt is disabled If DNRIEn 1 the USB data not ready interrupt is enabled NODIEn USB nodata interrupt enable If NODIEn 0 the USB no data interrupt is disabled If NODIEn 1 the USB no data interrupt is enabled EODIEn USB end of data interrupt enable If EODIEn 0 the USB end of data interrupt is disabled If EODIEn 1 the USB end of data interrupt is enabled SODIEn USB start of data interrupt enable If SODIEn 0 the USB start of data interrupt is disabled If SODIEn 1 the USB start of data interrupt is enabled Semiconductor Group 7 7 1997 10 01 SIEMENS Interrupt System C540U C541U Endpoint n Buffer Control RegisterEPBCn n 0 4 Address C1y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 Ciy STALLn 0 0 GEPIEn SOFDEn INCEn 0 DBMn EPBCn rw r r rw rw rw r rw The shaded bits are not used for interrupt control Bit Function GEPIEn Global endpoint interrupt enable Bit GEPIEn enables or disables the generation of the global endpoint interrupt forr endpoint n based on the endpoint specific interrupt request bits in reg
81. V and in high state above 2 8 V with a 15 kQ load to Vss The driver outputs support tri state operation to achieve bi directional half duplex operation control bits RPWD and TPWD High impedance is also required to isolate the port from devices that are connected but powered down The driver tolerates a voltage on the signal pins of 0 5 V to 3 8 V with respect to local ground reference without damage This voltage is tolerated for 10 0 us while the driver is active and driving When the driver is in its high impedance state it tolerates this condition an indefinitely long time For a full soeed USB connection the impedance of the USB driver must be between 29 Q and 44 Q The data line rise and fall times are between 4 ns and 20 ns smoothly rising or falling monotonic and are well matched to minimize RFI emissions and signal skew Figure 6 42 shows how the full speed driver is realized using two identical CMOS buffers Figure 6 43 shows the full speed driver signal waveforms Semiconductor Group 6 73 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U One Bit Time 12 MB s P d Signal Pins Pass Receiver Input Spec Levels Signal Pins after one Cable XG Delay MCT03414 Figure 6 43 Full Speed USB Driver Signal Waveforms For a low speed USB connection the rise and fall time of the signals are greater than 75 ns to keep RFI emissions under FCC class B limits and less than 300 ns to limit timing delays an
82. Value XXXX 0000p Bit No MSB LSB 7 5 4 3 2 1 0 COH OWDS WDTS WDT SWDT WDCON Bit Function Reserved bits for future use OWDS Oscillator watchdog timer status flag Set by hardware when an oscillator watchdog reset occured Can be set and cleared by software WDTS Watchdog timer status flag Set by hardware when a watchdog timer reset occured Can be cleared and set by software WDT Watchdog timer refresh flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer SWDT Watchdog timer start flag Set to activate the watchdog timer When directly set after setting WDT a watchdog timer refresh is performed Semiconductor Group 8 3 1997 10 01 SIEMEN Fail Safe Mechanisms 3 C540U C541U 8 1 3 Starting the Watchdog Timer The watchdog timer can be started by software bit SWDT in SFR WDCON but it cannot be stopped during active mode of the device If the software fails to clear the watchdog timer an internal reset will be initiated The reset cause external reset or reset caused by the watchdog can be examined by software status flag WDTS in WDCON is set A refresh of the watchdog timer is done by setting bits WDT SFR WDCON and SWDT consecutively This double instruction sequence has been implemented to increase system security It must be noted however that the watchdog timer is halted during the id
83. XXX PUDI PUEI PSSC 0000p 2 COy WDCON XXXX E E OWDS WDTS WDT SWDT 2 0000p C1y to C7y USB Device and Endpoint Register definition see table 3 3 DOW PSW 00H CY AC FO RS1 RSO OV F1 P 2 D2y EPSEL 80y EPS7 0 0 0 0 EPS2 EPS1 EPSO D34 USBVAL 00H E 6 5 4 3 2 1 0 D44 ADROFF j00y 0 0 AO5 AO4 AO3 AO2 AO1 AOO D6y GEPIR 00y 0 0 0 EPI4 EPI3 EPI2 EPM EPIO EO0j ACC 00 7 6 2 4 3 2 1 0 FO B 00H 7 6 I5 4 3 2 1 0 FCH VRO C5y 1 1 0 0 0 1 0 1 3 5 FDH VRI CiH 1 1 0 0 0 0 0 1 3 5 FEW VR2 6 f 6 5 4 3 2 0 3 5 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set 4 This SFR respectively bit is only available in the C541U 5 These are read only registers 6 The content of this SFR varies with the actual of the step C541U e g 01 y for the first step 7 The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset Semiconductor Group 3 7 1997 10 01 SIEMENS Memory Organization C540U C541U Table 3 4 mi of the USB Device and Endpoint Registers Addr C14 to C7 4 Addr Register Reset Bit7 Bit6 Bit5 Bit4 Bit 3 B
84. abel 8 1 shows resulting timeout periods at fosc 12 MHz Special Function Register WDTREL Address 86 Reset Value 00y MSB LSB BitNo 7 6 5 4 3 2 1 0 Bep eee Reload Value WDTREL Bit Function WDTPSEL Watchdog timer prescaler select bit If WOTPSEL 0 the watchdog timer is clocked by fosc 12 default after reset If WDTPSEL 1 the watchdog timer is clocked by fosc 192 WDTREL 6 0 Seven bit reload value for the high byte of the watchdog timer This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT Immediately after start the watchdog timer is initialized to the reload value programmed to WDTREL 0 WDTREL 6 After an external hardware reset an oscillator watchdog power on reset or a watchdog timer reset register WDTREL is cleared to 00y The lower seven bits of WOTREL can be loaded by software at any time Table 8 1 Watchdog Timer Time Out Periods WDTPSEL 0 WDTREL Time Out Period Comments fosc 12 MHz 00H 32 768 ms This is the default value 80y 0 55 s Maximum time period 7Fy 256 us Minimum time period Semiconductor Group 8 2 1997 10 01 SIEMENS Fail Safe Mechanisms C540U C541U 8 1 2 Watchdog Timer Control Status Flags The watchdog timer is controlled by control and status flags which are located in SFR WDCON Special Function Register WDCON Address CO Reset
85. access SOD is set if the USB has read a fixed number of bytes from the transmit buffer During an USB write access SOD is set if the USB has written a fixed number of bytes to the receive buffer Semiconductor Group 7 12 1997 10 01 IE Interrupt System SIEMENS C540U C541U The global endpoint interrupt request register GEPIRn n 0 4 contains one flag for each endpoint which indicates whether one or more of the seven endpoint specific interrupt requests has become active If a request flag in GEPIR is set it is automatically cleared after a read operation of the GEPIR register USB Global Endpoint Interrupt Request Register GEPIR Address D6y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D6H 0 0 0 EPI4 EPI3 EPI2 EPI1 EPIO GEPIR r r r r r r r r Bit Function EPI4 Endpoint 4 interrupt request flag If EPI4 is set an endpoint 4 interrupt request is pending EPIS Endpoint 3 interrupt request flag If EPIS is set an endpoint 3 interrupt request is pending EPI2 Endpoint 2 interrupt request flag If EPI2 is set an endpoint 2 interrupt request is pending EPI1 Endpoint 1 interrupt request flag If EPI is set an endpoint 1 interrupt request is pending EPIO Endpoint 0 interrupt request flag If EPIO is set an endpoint 0 interrupt request is pending Semiconductor Group 7 13 1997 10 01 SIEMENS Interrupt System C540U C541U 7 1 3 Interrupt Prioritiy Reg
86. age 0 at address 00y to 071 An6 An3 Endpoint n buffer start address The bits 0 to 3 of EPBAn are the address bits A6 to A3 of the USB memory buffer start address for endpoint n A7 and A2 A0 of the resulting USB memory buffer start address are set to 0 Ln6 LnO Endpoint n buffer length The bits 0 to 6 if EPLENn define the length of the USB memory buffer for endpoint n and cannot be written if DINIT 1 The USB buffer allocation and organization is described in detail in section 6 4 3 Semiconductor Group 6 72 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 4 8 On Chip USB Transceiver The C540U C541U provides on chip receiver and transmitter circuitries which allows to connect the C540U C541U directly to the USB bus The USB driver circuitry is shown in figure 6 42 The USB transceiver is capable of transmitting and receiving serial date at full speed 12 MBits s and low speed 1 5 Mbit s data rates Transceiver and receiver can be separately disabled for power down mode operation A single ended zero error condition D and D both at low level can be detected 19 DPWDR 1 Transmit Data Receive Data jo cr po DPWDR 0 MCS03413 Figure 6 42 USB On chip Driver Circuitry The USB driver circuitry is a differential output driver which drives the USB data signal onto the cable of the USB bus The static output swing of the transmitter is in low state below 0 3 V witha 1 5 KQ load to 3 6
87. ame begins with a SOF token start of frame Semiconductor Group 6 36 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U 6 4 2 2 2 USB Read Access Figure 6 29 shows the basic flowchart of a USB read access from one USB memory buffer in single buffer mode Buffer is empty USB read Access Disabled CPU write Access Enabled Buffer can be written by CPU Buffer is full USB read Access Enabled CPU write Access Disabled USB read Request T YES Buffer is read by USB Buffer empty MCD03402 Figure 6 29 USB Read Access in Single Buffer Mode Buffer Handling Semiconductor Group 6 37 1997 10 01 SIEMEN On Chip Peripheral Components 2 C540U C541U The standard USB read access as shown in figure 6 30 supports random and sequential CPU access mode of the USB memory The memory buffer full condition is true when a predefined number of bytes MaxLen has been written by the CPU or when bit DONE has been set by software After SOF n occured at 1 with a full USB memory buffer the USB reads the buffer Bit SOD is set at the end of the USB buffer read operation at 2 indicating an empty USB memory buffer Now the CPU can write again data into the USB memory buffer until a determined number MaxLen of bytes are transfered or until bit DONE has been set by software The MaxLen value must be previously set by software When the actual USB memory buffer address offset is equal to MaxLen bit EO
88. and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset The USB clock system must be cotrolled as described for the hardware reset in chapter 5 Figure 9 1 shows the procedure which must is executed when the power down mode is left via the wake up capability Execution of Power Down Latch Watchdog Circuit Interrupt at Mode Phase Oscillator Start Up Phase 007B y 1 4 P3 2 INTO or Activity Detected on USB Bus at RETI Instruction Detailed Timing of Beginning of Phase 4 ALE PSEN P2 Invalid Address oH YX Invalid Address Data UBHX 1st Instr of ISR MCT03418 Figure 9 1 Wake up from Power Down Mode Procedure Semiconductor Group 9 7 1997 10 01 IE Power Saving Modes gt ii ENS C540U C541U When the power down mode wake up capability has been enabled bit EWPD in SFR PCON1 set prior to entering power down mode the power down mode can be exit either via P3 2 INTO or an activity on the USB bus 9 2 2 1 Exit via Pin P3 2 INTO The following procedure 1 In power down mode pin INTO must be held at high level 2 Power down mode is left when INTO goes low With INTO low the internal RC oscillator is started INTO is then latched by the RC oscillator clock signal Therefore INTO should be held at low level for at least 10 us latch phase After this delay INTO can be set again to high level if required Thereafter
89. and the output of this shift register are each connected via a control logic to the pin P1 3 SRI SSC Receiver In and P1 4 STO SSC Transmitter Out This shift register can be written to SFR STB and can be read through the Receive Buffer Register SRB Pin P1 2 SCLK Pin P1 3 SRI Clock Divider Pin Control Logic Shift Register Clock Selection i ag SRB Pin P1 5 SLS Receive Buffer Register Interrupt gt SCIEN Int Enable Reg Control Logic SSCCON SCF Control Register Status Register Internal Bus MCB03379 Figure 6 21 SSC Block Diagram Semiconductor Group 6 21 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U As the SSC is a synchronous serial interface for each transfer a dedicated clock signal sequence must be provided The SSC has implemented a clock control circuit which can generate the clock via a baud rate generator in the master mode or receive the transfer clock in the slave mode The clock signal is fully programmable for clock polarity and phase The pin used for the clock signal is P1 2 SCLK When operating in slave mode a slave select input SLS is provided which enables the SSC interface and also will control the transmitter output The pin used for this is P1 5 SLS In addition to this there is an additional option for controlling the transmitter output by software The SSC control block is responsible for controlling the different m
90. ardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine Semiconductor Group 6 15 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Special Function Register TMOD Address 894 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 89 Gate C T Mf MO Gate C T Mi MO TMOD Timer 1 Control Timer 0 Control Bit Function GATE Timer 1 0 gating control When set timer counter x is enabled only while INT x pin is high and TRx control bit is set When cleared timer x is enabled whenever TRx control bit is set C T Timer 1 0 counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock M1 Timer 1 0 mode select bits MO F M1 MO Function 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves as 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer 0 TLO is an 8 bit timer counter controlled by the standard timer O control bits THO is an 8 bit timer only
91. as bodes wees 6 70 7 12 DAL eife Corea bes 3 8 6 62 7 11 ADROFF 3 5 3 7 6 55 DATE Ae ve eR 3 8 6 60 7 6 AEO oa ea E ESEESE Carus 3 8 DBMO seee n n 3 8 REV MER ETE 3 8 DBMi eseseeee n 3 8 EO Ec hoi bor Asi tops 3 9 DBM2 1 eee eee ene 3 9 ABS ee ee Sal Ne 3 9 DBM3 0 eee eee nnn 3 9 BIET oic ova er oet ovv Guten ths 3 9 DBM4 eese nne 3 9 AEA e a LIT aio do 6 68 7 7 DBM iwi duin eme 6 65 ALE signal ecc tailed heen wane 4 4 DC characteristics 11 2 to 11 3 ROSE a E EUN 3 7 6 55 DCR coococconrcrrro 3 5 3 8 6 57 B DDD case cte oon e 3 8 6 62 7 11 Bun ipe cea io 2434 37 DDIB reeni nee eas Sh Rear I0 Basic CPU timing 2 4 ore characteristics pU Mule is Block diagram 2 uve One oe aes 2 1 DINIT EER 3 8 6 58 Semiconductor Group 12 1 1997 10 01 SIEMENS Index C540U C541U A ene ree ae E 3 8 EPBAS road de bend de 3 9 A A 3 8 EPBA4 aio 3 9 DIR2 deetan Sia ee a Beene 3 9 EPBAN utar asco erase 3 5 6 72 Dc PEE 3 9 o DM DM caldos 3 8 n EN NET CT ECTS 3 9 EPBG so Soon Mn DAC AR nf 3 8 DIBI Seer cotto Odie du de abs Gaal 6 66 EPBC2 rr ce 3 9 DIRR 0005 3 5 3 8 6 62 7 11 EPBC3 MER CORPS 3 9 AA src Su Ma 3 8 EPBC4 D 3 9 D ar RE E ET 3 8 EPBCN e ener p hin 3 5 6 64 7 8 A EEE TP 3 9 EPSSU a ee a quo USC ERE 3 8 DN c PER P ee ee TER 3 9 EBBST A bate wove be 3 8 PNRA sata isneei A paa 3 9 EPBS2 th sed ae cios da ai dU Sr 3 9 DNRIEDG Coo
92. ase 1 or phase 2 depending on port and alternate functions Figure 6 16 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before Therefore there must be met certain requirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees that this logic level is noticed by the port at least once p Sn NN UNE NE UN Pi P2 PI P2 P1 P2 PI P2 Pi P2 Pi P2 L P1 Active Input sampled driver Transistor e g MOV A P1 or Port Old Data Y New Data MCT03397 Figure 6 16 Port Timing Semiconductor Group 6 10 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 1 3 2 Port Loading and Interfacing The output buffers of ports 1 2 and 3 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be looked up in the C540U C541U DC characteristics in chapter 10 The corresponding parameters are Vo and Voy The same applies to port 0 output buffers They do however require external pullups to drive floating inputs except when being used as the address data bus When used as inputs it must be noted that
93. be enabled prior to executing the double instruction sequence shown above ORL SYSCON 00010000B set RMAP ORL PCON 1 280H enable wake up from power down by setting EWPD 80H wake up through pin P3 2 INTO 90H wake up through USB bus ANL SYSCON 11101111B reset RMAP for future SFR accesses Note Before entering the power down mode the port latch of SFR P3 2 P3 2 INTO pin should contain a 1 pin operates as input Otherwise the wake up sequence discussed in the next chapter will be started immediately when power down mode is entered If the wake up from software power down mode through USB bus capability is selected the USB receiver must be enabled in order to detect any activity on the USB bus lines Therefore bit RPWD in the USB device power down register DPWDR must be cleared before enering software power down mode The USB module enters the suspend state when it detects no activity on teh USB bus for more than 6 ms Semiconductor Group 9 6 1997 10 01 IE Power Saving Modes gt ii ENS C540U C541U 9 2 2 Exit from Power Down Mode If the power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the power down mode also restarts the RC oscillator and the on chip oscillatror The reset operation should not be activated before Vcc is restored to its normal operating level
94. bit address Note The registers of the USB module are accessed through special function registers in the SFR area 3 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in chapter 2 This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction op code indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV RO Reset initializes the stack pointer to location 074 and increments it once to start from location 08 4 which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the SP should be initialized to a different location of the RAM which is not used for data storage Semiconductor Group 3 2 1997 10 01 IE Memory Organization SIEMENS C540U C541U 3 4 Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area The specia
95. but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored too as shown in the following table 7 13 Table 7 13 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003H IEO Timer 0 Overflow 000By TFO External Interrupt 1 0013y IE1 Timer 1 Overflow 001By TF1 SSC Interrupt C541U only 0043H USB Endpoint Interrupt 004By USB Device Interrupt 0053H Wake up from power down 007By Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged A special interrupt source is the power down mode interrupt This interrupt is automatically enabled when the C540U C541U is in power down mode and bit
96. cess Buffer Switching when MaxLen is reached In dual buffer mode the physical assignment of the USB memory pages page 0 or page 1 to either CPU buffer or USB buffer is controlled automatically in the USB module and cannot be selected by software Semiconductor Group 6 42 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U Another way to initiate buffer switching is setting bit DONE by software This feature which is shown in figure 6 35 for USB read access can be used to transfer a variable number of bytes The maximum number of bytes to be transferred is still determined by MaxLen which is not changed when bit DONE is set The actual packet length Len1 or Len2 is the number of bytes which have been written to the buffer before bit DONE is set Number of Data Bytes MaxLen Lent Len2 MaxLen Lent Len2 Frame n 1 SOF n 1 SOF n42 Set Set Set V A USB read Accesses ES CPU write Accesses MCT03408 Figure 6 35 Dual Buffer Mode USB Read Access Buffer Switching by Setting Bit DONE Semiconductor Group 6 43 1997 10 01 SIEMEN On Chip Peripheral Components gt C540U C541U If bit SOFDE is set buffer switching is done automatically after SOF start of frame has been detected by the USB Figure 6 36 describes this functionality for USB read access for this case The buffer which contains the latest data from the CPU is tagged valid for USB access UBF 1 at D a
97. cle ddr Watchdog timer 8 1 to 8 4 Programming mode read cycle 11 14 Block diagram sese Rete 8 1 Programming mode write cycle vee 11 13 Control status flags 8 3 Protected ROM OTP vedtysiming e MIT Input clock selection 8 2 ROM verification mode 2 11 16 Semiconductor Group 12 6 1997 10 01 SIEMENS Ox C540U C541U Refreshing of the WDT 8 4 Reset operation 8 4 Starting of the WDT 8 4 Time out periodS 8 2 WEN stes del et ate io 3 7 6 29 7 5 WC OL teo fett oat 3 6 6 30 7 10 WDQGOON css 3 4 3 7 8 3 MIDI Ts uie Sousse de eem diee 3 7 8 3 WDTIPSEE Sila 3 6 8 2 WDTREL 3 2c Gre iex vn 3 4 3 6 8 2 WDTS cS nd an peut es whet 3 7 8 3 Winter eat 3 7 A y case e act on 3 6 9 2 Semiconductor Group 12 7 1997 10 01
98. cle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When RESET is found active high level the internal reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all special function registers contain their default values the port latches contain 1 s etc Note that this reset procedure is also performed if there is no clock available at the device This is done by the oscillator watchdog which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins The RESET signal must be active for at least two machine cycles after this time the C540U C541U remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external program memory in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 5 5 shows this timing for a configuration with EA O external program memory Thus between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles I One Machine Cycle gt a S3 S4 dE Abd 2e d agb P1 P2 AYA
99. ction A change in the data direction is only executed if both USB memory buffers are empty SETRD cannot be set together with CLREPn because a change of bit DIRn during a transfer is not allowed Note bits SETRDn and SETWRn must not be set at a time Semiconductor Group 6 66 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U Bit Function SETWRn Set direction of USB memory buffer to write Bit SETWRnh is used to predict the direction of the next USB access for endpoint n as an USB write access A faulty prediction causes no errors since the USB module determines the real direction A change in the data direction is only executed if both USB memory buffers are empty SETWR cannot be set together with CLREPn because a change of bit DIRn during a transfer is not allowed Note bits SETWRn and SETRDn must not be set at a time CLREPn Clear endpoint Setting bit CLREPn will set the address offset register for a CPU access to USB memory to 0 The bits CBFn and UBFn will be reset when CLREPn is set Bit CLREPn is reset by hardware A read operation on this bit will always deliver 0 Setting of CLREPn does not change the direction of endpoint n This means bit DIRn is not changed Note When bits CLREPn and ESPn are set simultaneously with one instruction bit ESPn remains set and the next status phase is enabled If only CLREPn is set bit ESPn is reset and the status phase is disabled Setting bits CLREPn and SET
100. ctivated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Executing of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If itis a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Semiconductor Group 2 4 1997 10 01 SIEMENS Fundamental Structure C540U C541U BE e So S6 A s S5 S6 P2 P1 F2 B P2 P1 P2 P1 P2 P1 P2 5 P2 P1 P2 a P2 P1 P2IP1 P2 P1 P2 OSC cu LI LE LILI LILI LILI LILI LIL ALE Read Read Next Read Next Opcode Opcode Discard Opcode Again SISTsIRSTSIS a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd Read Next Opcode Byte NE Opcode sIgIsISISIsT b 2 Byte 1 Cycle Instruction e g ADD A DATA Read Read Next Opcode Discard Read Next Opcode Opcode Again SIsIsI IsIsISISISI ISIS c 1 Byte 2 Cycle Instruction e g INC DPTR Read Read Next Read Next Opcode Again Opcode Opcode No Fetch MOVX Discard No ALE OECD E SIsTsI TSISISISISTSTSIS
101. d MOVX 1 Byte 2 Cycle ADDR DATA Access of External Memory MCD03287 Figure 2 2 Fetch Execute Sequence Semiconductor Group 2 5 1997 10 01 Fundamental Structure SIEMENS C540U C541U Semiconductor Group 2 6 1997 10 01 SIEMEN Memory Organization gt C540U C541U 3 Memory Organization The C540U C541U CPU manipulates operands in the following four address spaces 80r4 KByte on chip OTP program memory Totally up to 64 Kbyte internal external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 3 3 illustrates the memory address spaces of the C540U C541U External External Indirect Addr ER Internal Special Function RAM Register 2000 y 1 80 y FFF y 1 Internal External Internal EA 1 EA 0 RAM 0000 y 0000 y 00 y Y J V Y J Y Code Space External Data Space Internal Data Space 1 For the C504U the int ext program memory boundary is at OFFF yy 1000 y MCD03375 Figure 3 3 C540U C541U Memory Map Semiconductor Group 3 1 1997 10 01 SIEMEN Memory Organization gt C540U C541U 3 1 Program Memory Code Space The C541U has 8 Kbyte C540U 4 Kbyte of OTP program memory which can be externally expanded up to 64 Kbytes If the EA pin is held high the C541U executes program code out of the internal OTP program memory unless the program c
102. d in table 6 7 Table 6 7 Special Function Registers of the COMP Unit Symbol Description Address SSCCON SSC Control Register 93H SCIEN SSC Interrupt Enable Register ACH SCF SSC Status Register ABH STB SSC Transmit Buffer Register 94H SRB SSC Receive Buffer Register 95H SSCMOD SSC Mode Test Register 96H The register SSCCON provides the basic control of the SSC functions like general enable disable mode selections and transmitter control Special Function Register SSCCON Address 934 Reset Value 074 MSB LSB Bit No 7 6 5 4 3 2 1 0 934 SCEN TEN MSTR CPOL CPHA BRS2 BRS1 BRSO SSCCON Bit Function SCEN SSC system enable SCEN 0 SSC subsystem is disabled related pins are available as general I O SCEN 1 SSC subsystem is enabled TEN Slave mode transmitter enable TEN 0 Transmitter output STO will remain in tristate state regardless of the state of SLS TEN 1 and SLS O Transmitter will drive the STO output In master mode the transmitter will be enabled all the time regardless of the setting of TEN MSTR Master mode selection MSTR 0 Slave mode is selected MSTR 1 Master mode is selected This bit has to be set to the correct value depending on the hardware setup of the system before the SSC will be enabled It must not be modified afterwards There is no on chip support for dynamic switching between master and slave mode operation
103. d signaling skews and distortions The driver reaches the specified static signal levels with smooth rise and fall times and minimal reflections and ringing when driving the USB cable see figure 6 44 This cable and driver are used only on network segments between low speed devices and the ports to which they are connected One Bit Time 1 5 MB s Driver f Output Spec Levels Signal Pins Xe with minimal Reflections Vss MCT03415 Figure 6 44 Low Speed USB Driver Signal Waveforms Semiconductor Group 6 74 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 9 Detection of Connected Devices Full speed and low speed USB devices are differentiated by the position of the pullup resistor on the downstream end of the cable Full speed devices are terminated with the pull up on the D line and low speed devices are terminated with the pull up in the D line see figure 6 The pull up terminator is a 1 5 kO resistor tied to a voltage source between 3 0 and 3 6 V referenced to the local ground When a device is attached to the host or hub the data line with the pull up is above 2 8 V and the other data line is near ground idle state A connect condition will be detected when one of the data lines is pulled above the single ended high threshold level for more than 2 5 us 30 full speed data bit times When a device is detached from the USB the pull down resistors will cause both D and D lines to b
104. d with O the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 no state change will occur At the beginning of power on reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH SOH state If itis is used as output the weak pull up p2 will pull the voltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 J the pin might remain in the IL state and provide a week 1 until the first O to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities If the load exceeds J the pin can be forced to 1 by writing a 0 followed by a 1 to the port pin Semiconductor Group 6 5 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Port 0 in contrast to ports 1 2 and 3 is considered as true bidirectional because the port 0 pins float
105. dditionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of software power down mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence Using a crystal or ceramic resonator for clock generation the external reset signal must be held active at least until the on chip oscillator has started and the internal watchdog reset phase is completed after phase III in figure 5 4 When an external clock generator is used phase ll is very short Therefore an external reset time of typically 1 ms is sufficent in most applications Generally for reset time generation at power on an external capacitor can be applied to the RESET pin Semiconductor Group 5 3 1997 10 01 dnouJt 1ojonpuooruleg v S L0 01 2661 v S enDi4 fiLESO 9u1 JO 1eseg uQ 19wog Power On undef Ports typ 18 us max 34 us Clock from RC Oscillator RESET at Ports On Chip Osc starts Final RESET Sequence by Osc WD max 768 RC Clock Cycles Port remains in RESET because of active ext RESET Signal gt Start of Program Execution MCT02627 SNIIN3IS 320 9 uiejs S josoy N LVSO NOVSI SIEMENS Reset System Clock C540U C541U 5 3 Hardware Reset Timing This section describes the timing of the hardware RESET signal The input pin RESET is sampled once during each machine cy
106. device detached interrupt is disabled If DDIE 1 the USB device detached interrupt is enabled SBIE USB suspend begin interrupt enable If SBIE 0 the USB suspend begin interrupt is disabled If SBIE 1 the USB suspend begin interrupt is enabled SEIE USB suspend change interrupt enable If SEIE 0 the USB suspend change interrupt is disabled If SEIE 1 the USB suspend change interrupt is enabled STIE USB status interrupt enable If STIEZO the USB status interrupt is disabled If STIE 1 the USB status interrupt is enabled SUIE USB setup interrupt enable If SUIE 0 the USB setup interrupt is disabled If SUIE 1 the USB setup interrupt is enabled SOFIE USB start of frame interrupt enable If SOFIE 0 the USB start of frame interrupt is disabled If SOFIE 1 the USB start of frame interrupt is enabled Semiconductor Group 7 6 1997 10 01 SIEMENS Interrupt System C540U C541U Special Function Registers EPIEn n 0 4 Address C3 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 C3y AlEn NAIEn RLEIEn DNRIEn NODIEn EODIEn SODIEn EPIEn For accessing EPIEn SFR EPSEL must be Ony Bit Function AlEn USB acknowledge interrupt enable If AIEn 0 the USB acknowledge interrupt is disabled If AlEn 1 the USB acknowledge interrupt is enabled NAIEn USB not acknowledged interrupt enable If NAIEn 0 the USB not acknowledged interrupt is disabled If NAIEn 1 the
107. device interrupt Semiconductor Group 6 76 1997 10 01 IE Interrupt System SIEMENS C540U C541U 7 Interrupt System The C541U provides seven C540U six interrupt sources with two priority levels Five interrupts can be generated by the on chip peripherals timer 0 timer 1 SSC interface and USB module and two interrupts may be triggered externally P3 2 INTO and P3 3 INT1 Figure 7 47 and 7 48 give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections Timer 0 Overflow Timer 1 Overflow Y Bit addressable 4 Request Flag is cleared by hardware Figure 7 47 Interrupt Request Sources Part 1 Semiconductor Group 7 1 1997 10 01 Interrupt System SIEMENS C540U C541U Endpoint Interrupts Endpoint 4 Interrupts Endpoint 3 Interrupts Endpoint 2 Interrupts Endpoint 1 Interrupts Endpoint 0 Interrupts Low Priority High Priority EPIE0 0 SSC See Interrupts SCIEN 1 C541U only 7 SCF 0 SCIEN O C Bit addressable 4 Request flag is cleared by hardware after the corresponding register has been read MCB03382 Figure 7 48 Interrupt Request Sources Part 2 Semiconductor Group 7 2 1997 10 01 IE Interrupt System SIEMENS C540U C541U Device Interrupts E TL Ef DIRR 6 o fe SBI Low Priority DIRR 4 4 High Priority sm ED KA DIRR 1 ED
108. ditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in figure 7 50 gt S5P2 Se SS 1 Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCT01859 Figure 7 50 Interrupt Response Timing Diagram Semiconductor Group 7 16 1997 10 01 IE Interrupt System SIEMENS C540U C541U Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7 50 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IEO and IE1 only if they were transition activated The hardware generated L CALL pushes the contents of the program counter onto the stack
109. e Bold page numbers refer to the main definition BRS occ 3 6 6 28 part of SFRs or SFR bits A IT 3 6 6 28 A C e RR 3 8 6 72 GI Toa c ga tuae RR CR EA 3 6 6 16 ju EE ROME 3 8 6 72 iz 0 REED EDT MN 3 8 PO EUER a 3 9 6 72 OPP SERERE ERN 3 8 Ada n 3 9 6 72 CBR Loss dni ERR ERE b eR 3 9 malu eed EE 3 9 6 72 A EAO 3 9 Absolute maximum ratings 11 1 CBE usui A saat J P OU ARR MD SERA 2 3 3 7 CBE MH ENIM MEME 6 66 AC characteristics Heta a Eaa oe SE E VIE GURERI Lo st dos dadebsa mad 3 8 AO S A pte SE 3 9 External clock timing 11 9 GEREP S vecsded e oi 2a Lock bit access timing 11 15 EE ES Program olvida Ordesa So 12 7 GEREP tes se seine eO dtes 6 67 a corre nee ae CPRANI us citations 3 6 6 28 Programnd mode read velo ves i fld POE EREA ET 3 6 6 28 Programming mode write cycle 11 13 GPU Protected ROM OTP verify timing 11 16 Accumulator AAA 2 2 Version byte access timing 11 15 7 UIE aes ESSA UNE RSA RARE ey AC Testing Basic timing LEE 2 4 Float waveforms 11 18 a e Input output waveforms 11 18 Functionality tek exea 2 2 Load for D D n o 11 18 ELO gran SISIUS WONG ci Genres ae rs Ge LLL 2 2 3 4 3 7 Stack pointer ccs d ERES 2 3 o UR MENDA canna tase ma CPIM popa x ROK A TN B of quive EE es Ros ae tele e 39 D BOR ao eset ees t en tis 3 9 DA eee nnn 3 8 6 57 ROKE oae tfe duse nae 3 9 DADD eesseeeene 3 7 6 76 ACKN onto coi dan
110. e in the related SFR EPBCRn is set After a specific number of CPU accesses as defined in SFR EPLENn the buffer has been read written by the CPU and is empty full Setting of bit DONE by software manually or automatically marks the USB buffer ready Note Only buffers for device to host pipes can be written Semiconductor Group 6 34 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 2 2 Single Buffer Mode In single buffer mode the USB and the CPU share one common USB memory page The active buffer page can be either page 0 or page 1 Back to back transfers are not possible in this mode Easy data storage and controlling can be achieved in this mode E g a once created data set for an interrupt endpoint can be stored permanently in USB memory As a result an additional memory space for data storage is no longer needed 6 4 2 2 1 USB Write Access Figure 6 27 shows the basic flowchart of a USB write access to one USB memory buffer in single buffer mode Buffer is empty USB write Access Enabled CPU read Access Disabled USB write Request Buffer is written by USB J Buffer is full USB write Access Disabled CPU read Access Enabled Buffer can be read by CPU Buffer empty MCD03400 Figure 6 27 USB Write Access in Single Buffer Mode Buffer Handling Semiconductor Group 6 35 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U Figure 6 28 shows more deta
111. e not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes FFy to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not only for two oscillator periods Semiconductor Group 4 1 1997 10 01 External Bus Interface SIEMENS C540U C541U One Machine Cycle One Machine Cycle gt S1 s2 3 s4 s5 se St s2 S3 s4 S5 S6 A without MOVX PCH PCH PCH PCH OUT OUT OUT OUT PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid One Machine Cycle lt One Machine Cycle gt s1 s2 s3 s4 s5 se s1 s2 s3 s4 S5 S6
112. e 8 7 9 Power Saving Modes 0 200 e cece eee eee eee 9 1 9 1 Idle Mode uox 6 Secu faece Sans ovs Sono MEM NI ate eae ATi EMRE gE E iut 9 3 9 1 1 Entering ldle Mode 23 240 rri annie ebbe deor e deo ede pan dud te tee nd 9 4 9 1 2 Exitirom idle MOUG so EIEESEDOTXERREPETERTRMRSIORR ewes DHETEE E ES 9 4 9 2 Power Down Mode eer RE E ele we Xp X GR CE NOR LR 9 5 9 2 1 Entering Power Down Mode v ub Eee ebbe enr LEE e ue E es 9 6 9 2 2 Exit from Power Down Mode 000 c eee eee eee ree 9 7 9 2 2 1 SO Stone d tone ora tht ratto o at erstattet a iA ttu 9 8 9 2 2 2 Exitvia UBS BUS usada as e RIDE E qu Pons sod cid sud to aeu C edunt ped 9 8 10 OTP Memory OperallOh 20 9 9 he XB re cee Reese kee 10 1 10 1 Programming Configuration re kato d e optics reb Ped e URP Tube 10 1 10 2 Pin Config ration ceo cere en bea aoe oes 645 atan cra 10 2 10 3 Pin Definitions 23 veseEmeekem Seda E ee ee eee 10 4 10 4 Programming Mode Selection 1539 PERI PIN RRIMERY SPARE EE eee Y ge 10 6 10 4 1 Basic Programming Mode Selection 0200 cee eee 10 6 10 4 2 OTP Memory Access Mode Selection ia eet rtr ure aun Ere tes 10 7 10 5 Program Read OTP Memory Bytes 000000 c eee eee 10 8 10 6 Lock Bits Programming Read voir e Rh RR wR ee Ree 10 10 10 7 Access of Version BIOS ores m CEPR an A erbe ORC UD tu 10 12 10 8 OTP Verify with Protection Level tres PO ew ee see ee 10 13 11 Device Specifications 00 c cece
113. e pulled below the single ended low threshold of the host or hub port This creates a state called a single ended zero SEO on the downstream port A disconnect condition is indicated if an SEO persists on a downstream port for more than 2 5 us 30 full speed data bit times FS LSUSB Ff Twisted Pair Shielded p FS LS USB Transceiver Z Transceiver 5 meters max Ry il ii Ry Full Speed Device Host or Hub Port FS LSUSB HS Unwisted Unshielded FS LS USB Transceiver v Transceiver 3 meters max Ry H Ry Low Speed Device Host or mub Or MCS03416 Figure 6 45 Low Speed High Speed Device Cable and Resisitor Connection Resistor R has to be external In some cases it might be necessary to hide the USB device from the host even when it is plugged in To accomplish this the pull up resistor Ro can be made switchable with a port a transistor Semiconductor Group 6 75 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 10 Detach Attach Detection The USB device can be used in two different modes concerning its power supply the bus powered mode and the self powered mode 6 4 10 1 Self Powered Mode In self powered mode the USB device has its own power supply The USB device has to detect whether it is connected to USB bus or not This detection is done by hardware by using the Device Attached Device Detached pin DADD as shown in figure 6 46 When the device attached condition i
114. e termination of the suspend state triggers the watchdog unit and starts the wake up procedure After the start trigger by the USB bus activity the actions 3 to 5 as described above are executed The wake up trigger signal from the USB module can only be generated if the USB receiver circuitry was enabled in software power down mode Semiconductor Group 9 8 1997 10 01 SIEMEN OTP Memory Operation P C540U C541U 10 OTP Memory Operation The C541U contains a 8k byte one time programmable OTP program memory C540U 4k byte With the C540U C541U fast programming cycles are achieved 1 byte in 100 usec Also several levels of OTP memory protection can be selected This chapter describes in detail the C540U C541U programmimg interface 10 1 Programming Configuration For programming of the device the C540U C541U must be put into the programming mode This typically is done not in system but in a special programming hardware In the programming mode the C540U C541U operates as a slave device similar as an EPROM standalone memory device and must be controlled with address data information control lines and an external 11 5V programming voltage In the programming mode port 0 provides the bidirectional data lines and port 2 is used for the multiplexed address inputs The upper address information at port 2 is latched with the signal PALE For basic programming mode selection the inputs RESET PSEN EA Vpp ALE PMSEL1 0 and PSEL are
115. easured under following conditions EA Port 0 Voc XTAL2 N C XTAL1 Vss RESET Vgg all other pins are disconnected the USB transceiver is switched off 4 cc active mode is measured with XTAL1 driven with ci cH a toHcL 5ns j Vi Vss 0 5 V Vin Voc 0 5 V XTAL2 N C EA RESET Port 0 Port 1 Voc all other pins are disconnected Icc would be slightly higher if a crystal oscillator is used appr 1 mA 5 Zcc idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with ci cH A toHcL 5 ns Vi Vss 0 5 V Vin Voc 0 5 V XTAL2 N C EA RESET V4 Port 0 Voc all other pins are disconnected 6 Overload conditions occur if the standard operating conditions are exceeded ie the voltage on any pin exceeds the specified range i e Voy gt Vcc 0 5 V or Voy lt Vss 0 5 V The supply voltage Veg and Vss must remain within the specified limits The absolute sum of input currents on all port pins may not exceed 50 mA 7 Not 100 tested guaranteed by design characterization 8 The typical cc values are periodically measured at T 25 C but not 100 tested 9 The maximum Tec values are measured under worst case conditions T 0 C and Voc 5 5 V Semiconductor Group 11 3 1997 10 01 IE Device Specifications SIEMENS C540U C541U 11 3 AC Characteristics Voc 4 0V to 5 5V 5V 10 20 Vss 0 V T 0 to 70 C C for port
116. ecifies the number of the endpoint 0 4 for which the actual configuration byte block is valid This 3 bit field must be referenced in byte 0 and byte 3 of a configuration byte block EPType This 2 bit field defines the type of the endpoint 00 Control endpoint 01 Isochronous endpoint 10 Bulk endpoint 11 Interrupt endpoint Endpoint 0 must be setup for control endpoint EPDir This bit defines the direction of the endpoint 0 In packets to be transferred from CPU to Host 1 Outr packets to be transferred from Host to CPU EPPackSize This 10 bit field defines the maximum packet size to be transferred to this endpoint within the range from zero up to 1023 bytes The configuration of EPPackSize has to be in harmony to the USB specification Semiconductor Group 6 50 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 6 Control Transfer A control transfer consists of at least two and perhaps three stages This chapter gives a short description of these stages of a control transfer and the associated configuration of the control and status bits 6 4 6 1 Setup Stage Control transfer always begin with a setup stage that transfers information to a target device defining the type of request being made to the USB device The standard commands except the set descriptor and get descriptor command are handled by the USB module automatically without CPU interaction If the command i
117. ed Mode cu ir tegit pae p sap p eR oet eo meee qa 6 76 7 Interrupt Systemic eec eere a s Eod a EE MEER Nene edet 7 1 7 1 Interrupt Registers uua es a s eo ada 7 4 7 1 1 Interrupt Enable Registers ic ue be See Das Seas Rae cower aes 7 4 7 1 2 Interrupt Request Control Flags 00 00 cee eee 7 9 7 1 3 Interrupt Priority Registers iso iros ve eH nte nc en tet e C Rea 7 14 7 2 Interrupt Priority Level Structure oooooccccocccocoo ee 7 15 7 3 How Interrupts are Handled pose stile tate sas deus ant bases 7 16 7 4 External MGM UDS sei tics es XS EPA DEINDE EE SONG UE 7 18 7 5 Interrupt Response Time 349 es Heads ede send ea Bea 7 20 8 Fail Safe Mechanisms oooccooccnc nnne 8 1 8 1 Programmable Watchdog Timer C541U only 02000 0 eee eee 8 1 8 1 1 Inp t Clock Seleccion usd exa ext bowie ten iE AERE 8 2 Semiconductor Group I 2 SIEMENS General Information C541U Table of Contents Page 8 1 2 Watchdog Timer Control Status Flags oooocooccconcc o 8 3 8 1 3 Starting the Watchdog Timer supra EE RISE E REED RAE ER 8 4 8 1 4 Refreshing the Watchdog Timer 000 eee ees 8 4 8 1 5 Watchdog Reset and Watchdog Status Flag 00 c eee eee 8 4 8 2 Oscillator Watchdog Ulla vc dum Chatto Din oe rbd Behe oet der ground 8 5 8 2 1 Functionality of the Oscillator Watchdog Unit 00 0c e eee oo 8 6 8 2 2 Fast Internal Reset after Power On 00 00 cece eee ee
118. ed ates 6 32 6 4 1 Econo n 6 33 6 4 2 USB Memory Buffer Modes 00 00 cece eee es 6 34 6 4 2 1 OVERVIEW cdm wasn AE te D o t de De RE EUER asiento OS f etpaud nit tet dre 6 34 6 4 2 2 SingleBultrer Mode eui cesi ar cam tut tan esto su Ad Me 6 35 6 4 2 2 1 USB Write ACCESS carrito cette 6 35 p4222 USB Read Access yeti itr od etae Url nare UM ace Caec vore iced en 6 37 6 4 2 3 Dual Butt r MOJO ceca rre RARE bx Tes ERG REGERE 6 40 6 4 3 USB Memory Buffer Organization liliis 6 47 6 4 4 USB Memory Buffer Address Generation llli liess 6 48 6 4 5 Initialization of USB Module sectaria E pP E ER cae eee RITTER TE 6 49 6 4 6 Goto Dransiel reinar ews ps o sr ESI 6 51 6 4 6 1 Set p Staje r ex ERR KERN PEIPER t 6 51 6 4 6 2 Data lage zoersimere inser equ qup nuns bi NISI MICI e 6 51 6 4 6 3 Status Stage 2 pts Bi eat Bid Lt ken Bin a s ad tta bt e E DM c Led 6 51 6 4 7 lisi gel E MEET 6 52 6 4 7 1 Global Hagis BI5 credete dut od o Ces Sob e UE ACER EOS Rae eet 6 53 6 4 7 2 Device Bedislers 4c oves suse dee eh Lavoe Ra VE A eee eS 6 57 6 4 7 3 Endpoint Registers 35 mores Deme ere hee site eme 6 64 6 4 8 On Chip USB Transcelver sik tere ad RE RE EN RUN 6 73 6 4 9 Detection of Connected Devices 0 00 e eee ee 6 75 6 4 10 Detach Attach Detection atte De su s ate ne ca hte ne a te to cu LA MAG 6 76 6 4 10 1 Seit PoweredJMOGd6 sus Se retire ed dae ed hema ied vot woo eol 6 76 6 4 10 2 Bus Power
119. ee ES pd 6 10 6 1 3 1 POU MUNN BO ct ante oerte D re eR eoo Ef ec e I aa Doi e 6 10 6 1 3 2 Port Loading and Interfacing seis A 6 11 6 1 3 3 Read Modify Write Feature of Ports 1 2 and3 0000 cease 6 12 6 2 TIMES COUNTES uo sutil atate trist ads 6 13 6 2 1 Timer Counter 0 and 1 ott nie ot aif sa Escudo Percent dE OR ted 6 13 6 2 1 1 Timer Counter O and 1 Registers o ococccoccoccnc eee 6 14 6 2 1 2 Mode O tater a AMT EMT TELE TEUER RR EE 6 17 6 2 1 3 MOOG Tenes Ed UASIEQACSUER MEC LER E deg aoe ee mes 6 18 6 2 1 4 MOde 2 227 22 TO peras das isis nte is 6 19 6 2 1 5 MOS A tea a b dw qe poe ins 6 20 6 3 SSC Interface C541U only cerca ie Pete Eee aether fb 6 21 6 3 1 General Operation of the SSC accus ied eese duae TE NEN EHE 6 22 Semiconductor Group l 1 SIEMENS General Information C541U Table of Contents Page 6 3 2 Enable Bisabl Control a Ebert a ee ae a ESSE 6 22 6 3 3 Baudrate Generation Master Mode only 20000 cee eee eee 6 23 6 3 4 Write Collision Detection e voies 8426654 34942 raras Sadat eee 6 23 6 3 5 Master Slave Mode Selection 0 00 cee eee eee ee 6 24 6 3 6 Data Clock Timing Relationships 3 ss ene ee dade oboe de beeen 6 25 6 3 6 1 Master Mode Operation 0 000 c cette 6 25 6 3 6 2 Slave Mode Operation coats etit fec SERA 6 26 6 3 7 Register DEScription 3 ug aoe erten tatere sued Date Se eee gt 6 27 6 4 LUSB MOUUIG uoiosdeaesiSOSUsbxUPEUSYNE Ru NAE AA a
120. en 3 6 7 19 General purpose registers ss a REN MS RUE OAM 3 6 7 19 ridi MARE EE S eo rogram memory ooo 3 2 DS M M cHE c 36 627 Elvis aC a Ne 3 6 7 9 Semiconductor Group 12 3 1997 10 01 SIEMENS Index C540U C541U N Programming mode 10 1 NACKO isst A testes qos 3 8 Version byte access 10 12 roc m 3 8 OV nnn 2 3 3 7 D NG cele NOE ti 3 9 OWDS 1 eect n 3 7 8 3 NAC MN D ETE 39 P NACA S Gr SS etn ds EODEM 3 9 Peck arietes DS techo M ole Ge at 2 3 3 7 WACK vows seas iS obese See sad 6 70 7 12 Eo sies 6 Bale se Th edu SUE 3 4 3 6 NAIEU 5 usce dnt fece dios 3 8 PA TL ETE 3 4 3 6 BAIE DT 0er e 3 8 Pres sono a a 3 4 3 6 NAIE 2 tai deta 3 9 Ps att t sii EE oes 3 4 3 7 BITE S eoe dari bts cs 3 9 Package information NAAA Sani Ge 2s Gree DIS EVEN 3 9 P LCC 44 package 11 20 NAIEN aterrado 6 68 7 7 P SDIP 52 package 11 21 NODO 4 essa iras Es 3 8 PAGEI erario 3 8 NOD Guaro atole ac 3 8 PAGE Vee eatin tex E 3 8 NODA Gi tks SS wie iden S ot Shoah at 3 9 PAGB2 id nsus t Ri unb bein dea 3 9 NODS aks cA eel fh ole CIE Ds 3 9 PAGES s artis fie ol o ade Ol 3 9 PA se et OG Se js D veri te tec 3 9 PAGES ode iste tret oni aene ta 3 9 NODIEN Sy rome ie PISA EET a 3 8 PAGE aimara tegeg ega rd eq 6 72 NODIEL 3 cut pes obl bua ROS 3 8 Parallel VO ivi x menm 6 1 to 6 12 NODIES atol n 3 9 POLK noa edd dde eoo HESS 3 8 6 58 NODIBES us IO uev oe ee dedos Bae 3
121. errupt source is individually enabled or disabled by setting or clearing its enable bit Not implemented Reserved for future use ET1 Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disabled If ET1 2 1 the timer 1 interrupt is enabled EX1 External interrupt 1 enable If EX1 0 the external interrupt 1 is disabled If EX1 1 the external interrupt 1 is enabled ETO Timer 0 overflow interrupt enable If ETO 0 the timer O interrupt is disabled If ETO 1 the timer O interrupt is enabled EXO External interrupt 0 enable If EXO 0 the external interrupt 0 is disabled If EXO 1 the external interrupt O is enabled Semiconductor Group 7 4 1997 10 01 Interrupt System SIEMENS C540U C541U Special Function Registers IEN1 Address A9j Reset Value XXXXX000p Special Function Registers SCIEN C541U only Address AC Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 A9H EUDI EUEI ESSC IEN1 ACH ES a WCEN TCEN SCIEN Bit Function Not implemented Reserved for future use EUDI Enable USB device interrupt enable If EUDI 0 the general USB device interrupt is disabled If EUDI 1 the general USB device interrupt is enabled EUEI Enablel USB endpoint interrupt If EUEI 0 the general USB endpoint interrupt is disabled If EUEI 1 the general USB endpoint inter
122. et at a time MCD03411 Figure 6 39 USB Memory Address Generation With the software initialization of the USB modul as described in section 6 4 5 each endpoint is initialized with the EPNum value which is used at the USB memory address generation to select the actual endpoint base address register Further in single buffer mode the bit PAGEn is used to select one of the USB memory pages In dual buffer mode bit PAGEn has no effect Semiconductor Group 6 48 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 4 5 Initialization of USB Module After a hardware reset operation bits PCLK SPEED and UCLK are set to 0 Depending on the required operating mode of the USB module a well defined procedure must be executed for switching on the clock for the USB module Full speed mode USB PLL is switched on by setting bit PCLK waiting 3 ms for PLL being locked setting bit UCLK Low speed mode setting bit UCLK only This switch on procedure after a hardware reset assures a proper operation of the USB clock system When the USB clock system is switched on a software initialization procedure must follow This procedure must execute the following steps Setting bit SWR in register DCR starts the software reset operation for the complete USB module For a full speed device bit SPEED must be set together with SWR in the same instruction write protection of SPEED bit When the software reset is finished bi
123. external data memory access is a MOVX DPTR or a MOVX Ri 4 2 PSEN Program Store Enable The read strobe for external program memory fetches is PSEN It is not activated for internal program memory fetches When the CPU is accessing external program memory PSEN is activated twice every instruction cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 6 oscillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 3 oscillator periods The execution sequence for these two types of read cycles is shown in figure 4 1 a and b 4 3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the C540U C541U the external program and data memory spaces can be combined by the logical AND of PSEN and RD A positive result from this AND operation produces alow active read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 4 3 1997 10 01 IE External Bus Interface S MENS C540U C541U 4 4 ALE Address Latch Enable The mai
124. functionality of the C501 Special Function Registers ITCON Address 9A y Reset Value XXXX1010p Bit No MSB LSB 7 6 5 4 3 2 1 0 9AH METF METR IQETF IOETR ITCON A 4 INT1 INTO Bit Function Reserved bit for future use IXETF External Interrupt Edge Trigger Mode Selection IXETR x 0 1 refers to INTO INT1 IXETF xETR Function 0 0 INTx inputs are not sensitive for either rising or falling edge 0 1 INTx operates in rising edge triggered mode 1 0 INTx operates in falling edge triggered mode default after reset NTx operates in falling and rising edge triggered mode Semiconductor Group 7 19 1997 10 01 IE Interrupt System SIEMENS C540U C541U 7 5 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was bloc
125. g only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions Vi gt Vcc Or Vin lt Vss the Voltage on Vcc pins with respect to ground Vss must not exceed the values defined by the absolute maximum ratings Semiconductor Group 11 1 1997 10 01 SIEMENS Device Specifications C540U C541U 11 2 DC Characteristics Voc 4 0V to 5 5V 5V 41096 20 Vss 0 V T 0 to 70 C Parameter Symbol Limit Values Unit Test Condition min max Input low voltage except EA Vu 0 5 0 2Vo IV RESET 0 1 Input low voltage EA Vis 0 5 0 2 Voo IV 0 3 Input low voltage RESET Vio 0 5 0 2 Voec IV 0 1 Input high voltage except XTAL1 Vi 0 2 Voece Voot 0 5 V RESET 0 9 Input high voltage to XTAL1 Vi 0 7 Voc Vec 40 5 IV Input high voltage to RESET Vino 0 6 Voc Voo 0 5 IV Output low voltage Ports 1 2 3 VoL 0 45 V Ig 1 6 mA P1 0 P1 1 P3 0 0 45 V Ig 10 mA Output low voltage port 0 ALE Voi 0 45 V Ig 3 2 mA PSEN Output high voltage ports 1 2 3 Vo 2 4 V Toy 80 uA 0 9 Voc Tow 10 uA Output high voltage port 0 in Vone 2 4 V Tou 800 uA external bu
126. gister while a transfer is in progress the WCOL bit in the status register will be set The transfer in progress continues uninterrupted the write will not access the shift register and will not corrupt data However the data written erroneously will be stored in a shadow register and can be read by reading the STB register Depending on the operation mode there are different definitions for a transfer being considered to be in progress Master Mode CPHA 0 from the trailing edge of the write into STB until the last sample clock edge CPHA 1 from the first SCLK clock edge until the last sample clock edge Note that this also means that writing new data into STB immediately after the transfer complete flag has been set also initiated with the last sample clock edge will not generate a write collision However this may shorten the length of the last bit especially at slow baudrates and prevent STO from switching to the forced 1 between transmissions Slave Mode CPHA 0 while SLS is active CPHA 1 from the first SCLK clock edge until the last sample clock edge Semiconductor Group 6 23 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 3 5 Master Slave Mode Selection The selection whether the SSC operates in master mode or in slave mode has to be made depending on the hardware configuration before the SSC will be enabled Normally a specific device will operate either as master or as slave unit The SSC has
127. h Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8By 00H TMOD Timer Mode Register 89H 00H SSC SSCCON SSC Control Register 93H 07H Interface STB SSC Transmit Buffer 94H XXH C541U SRB SSC Receive Register 95H XXH only SCF SSC Flag Register ABH 1 XXXXXX00p SCIEN SSC Interrupt Enable Register ACH XXXXXXO00p SSCMOD SSC Mode Test Register 96H 00H Watchdog WDCON Watchdog Timer Control Register COW XXXX0000p C541U WDTREL Watchdog Timer Reload Register 86H 00H only 1 Bit addressable special function registers 2 X means that the value is undefined and the location is reserved 3 The content of this SFR varies with the actual of the step C540U C541U eg 01 yy for the first step 4 This SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 10 01 SIEMENS Memory Organization C540U C541U Table 3 2 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Pow PCON Power Control Register 87H X00X0000p Sav PCON1 Power Control Register 1 881 OXXOXXXXp Modes USB EPSEL USB Endpoint Select Register D2y 80H Module USBVAL_ USB Data Register D3y 00H ADROFF USB Address Offset Register D4y 00y GEPIR USB Global Endpoint Interrupt Request Reg D6y 00H DCR USB Device Control Register Ciy 000X0000p DPWDR _ USB Device Power Down Register C2y 00H
128. he transmit buffer As a result the buffer is empty now and the CPU can process write actions again USB Write action SODn is set if the USB has written a fixed number USBLen of bytes to the receive buffer As a result the buffer is full and the CPU can start read actions In dual buffer mode bits SODn and EODn can be set simultaneously if the corresponding buffer page is swapped Semiconductor Group 6 71 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U The endpoint base address register defines the location and size start address and length of the endpoint specific buffers in the USB memory See also figure 6 38 for an example of EPBAn and EPLENn register setup Endpoint n Base Address Register EPBAn n 0 4 Address C5H Reset Value 00H Endpoint n Buffer Length Register EPLENn nz0 4 Address C6y Reset Val OXXXXXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 C5y PAGEn 0 0 0 An6 An5 An4 An3 EPBAn r r r r rw rw rw rw C6H 0 Ln6 Ln5 Ln4 Ln3 Ln2 Ln1 LnO EPLENn r rw rw rw rw rw rw rw Bit Function PAGEn Buffer page for endpoint n single buffer mode only In single buffer mode the endpoint n can be either located on USB memory buffer page 0 PAGEn 0 or on USB memory buffer page 1 PAGEn 1 by clearing or setting this bit In dual buffer mode this bit has no effect Note The SETUP token is always stored on USB memory buffer p
129. he verify error output P3 5 P3 5 can be latched with the falling edge of ALE When the last byte of the internal OTP has been handled the C540U C541U starts generating a PSEN signal This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal OTP verification CY CLK 121 13 Bit Address Counter Compare Code ROM MCS03423 Figure 10 11 OTP Verification with Protection Level 1 External Circuitry Example Semiconductor Group 10 14 1997 10 01 SIEMENS Device Specifications C540U C541U 11 Device Specifications Advance Information 11 1 Absolute Maximum Ratings Ambient temperature under bias Ta ccccoonccnoccccnnnnccnonccnccnnncccnannnannncnonancnnnnnnns 0 C to 70 C Storage temperature Tet uoa aue otto teda i 65 C to 150 C Voltage on Vec pins with respect to ground Vas coooocccccccccccnocananaccninnncnanannnos 0 5Vto6 5V Voltage on any pin with respect to ground Vgs cccooocccccnnnnnonanccaaacccnnnncnnnannnnos 0 5V to Voc 0 5 V Input current on any pin during overload condition esessssssss 10 mA to 10 mA Absolute sum of all input currents during overload condition 100 mA PoWerdissIDallOH s deae shaticov lali TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress ratin
130. hen the C540U C541U has been put into the programming mode using the basic programming mode selection several access modes of the OTP memory programming interface are available The conditions for the different control signals of these access modes are listed in table 10 3 Table 10 3 Access Modes Selection EA PMSEL Address Data Access Mode Vpp PROG PRD gt 0 Port 2 Port 0 Program OTP memory byte Vpp LJ H H H AO0 7 DO 7 Read OTP memory byte Vin H LI A8 15 Program OTP lock bits Vep LT H H L D1 D0 see Read OTP lock bits Via H Lr table 4 Read OTP version byte Vin H AEF IL H Byte addr DO 7 of sign byte The access modes from the table above are basically selected by setting the two PMSEL1 0 lines to the required logic level The PROG and PRD signal are the write and read strobe signal Data is transfered via port 0 and addresses are applied to port 2 The following sections describes the details of the different access modes Semiconductor Group 10 7 1997 10 01 IE OTP Memory Operation SIEMENS C540U C541U 10 5 Program Read OTP Memory Bytes The program read OTP memory byte access mode is defined by PMSEL1 0 1 1 It is initiated when the PMSEL1 0 1 1 is valid at the rising edge of PALE With the falling edge of PALE the upper addresses A8 A12 of the 13 bit OTP memory address are latched After A8 A12 has been latched AO A7 is put on the address bus port 2 AO A
131. ill have a different version byte 2 incremented value version bytes 0 and 1 will remain unchanged for future steppings of the C540U C541U Semiconductor Group 10 12 1997 10 01 SIEMEN OTP Memory Operation P C540U C541U 10 8 OTP Verify with Protection Level 1 If the C540U C541U OTP program memory is protected in protection level 1 an OTP verification as shown in figure 10 10 is used to verify the content of the OTP The detailed timing characteristics of this OTP verification mode is shown in the AC specifications chapter 11 RESET LT 1 ALE pulse after reset ES a b Es s X iu Data for Addr 0 X Date for Data tor Addr X 16 Data for Addr Low Verify Error High Verify ok Inputs ALE Vas PSEN EA Vi RESET 4_ MCT03289 Figure 10 10 OTP Verification Mode Timing The OTP verification mode is selected when the inputs PSEN EA and ALE are put to the specified logic levels With RESET going inactive the OTP verification mode sequence is started The C541U outputs an ALE signal with a period of 3 CLPand expects data bytes at port 0 The data bytes at port 0 are assigned to the OTP addresses in the following way 1 Data Byte content of internal OTP address 0000y 2 Data Byte content of internal OTP address 0001 3 Data Byte content of internal OTP address 00024 16 Data Byte content of internal OTP address 000FH The C540U C541U does not output any address information during the O
132. ils of an USB write access to USB memory in single buffer mode After SOF n start of frame occured at 1 the USB starts writing at 2 a fixed number of bytes into the USB memory A byte counter is incremented after every USB memory write operation When the USB memory write operation Len n is finished correctly bit SOD start of data is set at 3 indicating a full USB memory buffer Furthermore the byte counter value is stored in the corresponding length register indicating the number of bytes which have been transferred and can be now read by the CPU Subsequently the CPU can read data bytes from USB memory generating an EOD end of data at 4 after the last byte has been read Bit EOD set indicates an empty USB buffer which now can be written again by the USB Figure 6 28 also shows a second USB write access operation with a different number of bytes Len n 1 where the CPU read operation from the USB memory is interrupted twice Number of Data Bytes in USB Buffer SOD Set y O Len n Len n 1 SRS RRR RRR RN D OY Time Frame n Frame n 1 gt al SOF n 2 Set USB write Accesses ES CPU read Accesses MCT03401 Figure 6 28 Single Buffer Mode Standard USB Write Access Note The CPU accesses shown in the following diagrams assume that bit INCE in the corres ponding endpoint control register is set A frame is the 1 ms time interval defined by the USB host Every fr
133. inal reset sequence which takes typ 1 ms Within that time the clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog toggles the clock supply back to the on chip oscillator and releases the reset request If no reset is applied in this moment the part will start program execution If an external reset is active however the device will keep the reset state until also the external reset request disappears Furthermore the status flag OWDS is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS 8 2 2 Fast Internal Reset after Power On The C540U C541U can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally the members of the 8051 family e g SAB 80C52 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to por
134. ion decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU They have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear complement jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal
135. ister EPIRn If GEPIEn 0 the USB endpoint n interrupt is disabled If GEPIEn 1 the USB endpoint n interrupt is enabled Note For accessing the EPBCn registers SFR EPSEL D2y must be set with the appropriate value Semiconductor Group 7 8 1997 10 01 IE Interrupt System SIEMENS C540U C541U 7 1 2 Interrupt Request Control Flags The external interrupts 0 and 1 INTO and INT1 can each be either level activated or negative transition activated depending on bits ITO and IT1 in register TCON The flags that actually generate these interrupts are bits IEO and IE1 in TCON When an external interrupt is generated the flag that generated this interrupt is cleared by the hardware when the service routine is vectored too but only if the interrupt was transition activated If the interrupt was level activated then the requesting external source directly controls the request flag rather than the on chip hardware The timer 0 and timer 1 interrupts are generated by TFO and TF1 in register TCON which are set by a rollover in their respective timer counter registers When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored too Special Function Register TCON Address 884 Reset Value 00y MSB LSB Bit No 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON The shaded bits are not used for inte
136. isters Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFRs IPO or IP1 interrupt priority O low priority 1 high priority Special Function Registers IPO Address B8pj Reset Value XXXX0000p Special Function Registers IP1 Address B9p Reset Value XXXXX000p Bit No MSB LSB 7 6 5 4 3 2 1 0 B8y PT1 PX1 PTO PXO IPO BOY PUDI PUEI PSSC IP1 Bit Function Reserved for future use PT1 Timer 1 overflow interrupt priority level If PT1 0 the timer 1 interrupt has a low priority If PT1 1 the timer 1 interrupt has a high priority PX1 External interrupt 1 priority level If PX1 0 the external interrupt 1 has a low priority If PX1 1 the external interrupt 1 has a high priority PTO Timer 0 overflow interrupt priority level If PTO 0 the timer O interrupt has a low priority If PTO 1 the timer 0 interrupt has a high priority PXO External interrupt 0 priority level If PXO O the external interrupt O has a low priority If PXO 1 the external interrupt O has a high priority PUDI USB device interrupt priority level If PUDI 0 the USB device interrupt has a low priority If PUDI 1 the USB device interrupt has a high priority PUEI USB endpoint interrupt priority level If PUEI 0 the USB endpoint interrupt has a low priori
137. it2 Bit 1 Bit 0 Value EPSEL 1XXX XXXXp_ Device Registers C1y DCR 000X SPEED DA SWR SUSP DINIT RSM UCLK PCLK 0000p C2y DPWDR 00H 0 0 0 0 0 0 TPWD RPWD C3H DIER 00H SEOIE DAIE DDIE SBIE SEIE STIE SUIE SOFIE C4y DIRR 00H SEOI DAI DDI SBI SEI STI SUI SOFI C54 reserved C64 FNRL XXj FNR7 FNR6 FNR5 FNR4 FNR3 FNR2 FNRI FNRO C74 FNRH 0000 0 0 0 0 0 FNR10 FNR9 FNR8 OXXXp EPSEL 0XXX X000p Endpoint 0 Registers Ciy EPBCO 00H STALLO 0 0 GEPIEO SOFDEO INCEO 0 DBMO C2y EPBSO 20H UBFO CBFO DIRO ESPO SETRDO SETWRO CLREPO DONEO C3y EPIEO 00H AIEO NAIEO RLEIEO DNRIEO NODIEO EODIEO SODIEO C4y EPIRO 11H ACKO NACKO RLEO DNRO NODO EODO SODO C5H EPBAO 00H PAGEO 0 0 0 A06 A05 A04 A03 C6y EPLENO OXXX 0 LO6 LO5 L04 L03 L02 L01 LOO XXXXp C7y reserved EPSEL OXXX X001p Endpoint 1 Registers Ciy EPBC1 00H STALL1 O 0 GEPIE1 SOFDE1 INCE1 0 DBM1 C2y EPBS1 20H UBF 1 CBF1 DIR1 ESP1 SETRD1 SETWR1 CLREP1 DONE1 C3y EPIE1 00H AIE1 NAIE1 RLEIE1 DNRIE1 NODIE1 EODIE1 SODIE1 C4y EPIR1 10H ACK1 NACK1 RLE1 EH DNR1 NOD1 EOD1 SOD1 C5y EPBA1 00y PAGE1 0 0 0 A16 A15 A14 A13 C6y EPLEN1 OXXX 0 L16 L15 L14 L13 L12 L11 L10 XXXXp C7y reserved Semiconductor Group 3 8 1997 10 01 IE Memory Organization SIEMENS C540U C541U Table 3 4 Contents of the USB Device and Endpoint Registers Addr C14 to C74 conta Addr Register Reset Bit7 Bit6 Bit5 Bit4 Bit 3
138. ked by one of the three previously listed conditions If an interrupt of equal or higer priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to registers IE or IP the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 7 20 1997 10 01 IE Fail Safe Mechanisms gt yi ENS C540U C541U 8 Fail Safe Mechanisms The C540U C541U offers enhanced fail safe mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 256 us up to approx 0 55 us at 12 MHz The WDT is not available in the C540U an oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also provides the clock for a fast internal reset after power on 8 1 Programmable Watchdog Timer C541U only
139. l function register area consists of two portions the standard special function register area and the mapped special function register area One special function register of the C540U C541U PCONY 1 is located in the mapped special function register area All other SFRs are located in the standard special function register area For accessing PCON 1 in the mapped special function register area bit RMAP in special function register SYSCON must be set Special Function Register SYSCON Address B1 y Reset Value XX10XXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH EALE RMAP SYSCON The functions of the shaded bits are not described in this section Bit Function RMAP Special function register map bit RMAP 0 The access to the non mapped standard special function register area is enabled RMAP 1 The access to the mapped special function register area PCON 1 is enabled As long as bit RMAP is set a mapped special function register can be accessed This bit is not cleared by hardware automatically Thus when non mapped mapped registers are to be accessed the bit RMAP must be cleared set by software respectively each The registers except the program counter and the four general purpose register banks reside in the special function register area All SFRs with addresses where address bits 0 2 are 0 e g 80y 88H 90H 98H F8y FF are bitaddressable The 75
140. le mode and power down mode of the processor see section Power Saving Modes Therefore it is possible to use the idle mode in combination with the watchdog timer function But even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally 8 1 4 Refreshing the Watchdog Timer At the same time the watchdog timer is started the 7 bit register WDTH is preset by the contents of WDTREL O to WDTREL 6 Once started the watchdog timer cannot be stopped by software but can be refreshed to the reload value only by first setting bit WDT WDCON and by the next instruction setting SWDT WDCON Bit WDT will automatically be cleared during the third machine cycle after having been set This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog unit The reload register WDTREL can be written at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer Thus a wrong reload value caused by a possible distortion during the write operation to WDTREL can be corrected by software Note the watchdog timer registers WDTH and WDTL cannot be accessed by software 8 1 5 Watchdog Reset and Watchdog Status Flag If the software fails to clear the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCy The duration
141. ledged Bit NACKn is set for all unsuccessful actions on the USB RLEn Read length error Bit RLEn is automatically set if the number of bytes read by the USB does not correspond to the packet length programmed by the CPU Reserved bit for future use DNRn Data not ready This bit is set by hardware if the UDC requires an access to USB memory but no buffer is available USB Read action DNRn is set if UBF is not set USB Write action DNRn is set if UBF is set NODn No data This bit indicates an incorrect CPU read or write access to USB memory It is set if the CPU processes a read access to an empty USB buffer or a write access to a full buffer NODn is also set if the direction is write DIRn 0 for USB write access and the CPU tries to write to the USB memory buffer EODn End of data USB Read action EODn is set if the CPU has written a programmable number MaxLen of bytes in the transmit buffer As a result the buffer is full and no more write actions from the CPU are allowed USB Write action EODn is set if the CPU has read a programmable number USBLen of bytes out of the receive buffer As a result the buffer is empty now and no more read actions from the CPU are allowed Semiconductor Group 6 70 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Bit Function SODn Start of data USB Read action SODn is set if the USB has read a fixed number USBLen of bytes from t
142. n address data bus port 0 uses a pullup FET as shown in figure 6 13 When a 16 bit address is used port 2 uses the additional strong pullups p1 to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Addr Control Voc Internal Pull Up Arrangement Int Bus Nae o Port Pin Write to Latch MCS02123 Figure 6 14 Port 2 Circuitry Semiconductor Group 6 7 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 1 2 Alternate Functions The pins of ports 1 and 3 are multifunctional They are port pins and also serve to implement special features as listed in table 6 5 Figure 6 15 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pulldown FET is on and the port pin is stuck at 0 After reset all port latches contain ones 1 Alternate V Output e Function Internal Pull Up Arrangement e o Pin Int Bus MCS01827 Alternate Input Function Figure 6 15 Circuitry of Ports 1 and 3 Semiconductor Group 6 8 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Ports 1 and 3 are provided
143. n function of ALE is to provide a properly timed signal to latch the low byte of an address from PO into an external latch during fetches from external memory The address byte is valid at the negative transition of ALE For that purpose ALE is activated twice every machine cycle This activation takes place even if the cycle involves no external fetch The only time no ALE pulse comes out is during an access to external data memory when RD WR signals are active The first ALE of the second cycle of a MOVX instruction is missing see figure 4 1 b Consequently in any system that does not use data memory ALE is activated at a constant rate of 1 6 of the oscillator frequency and can be used for external clocking or timing purposes The C540U C541U allows to switch off the ALE output signal If the internal ROM is used EA 1 and ALE is switched off by EALE 0 ALE will only go active during external data memory accesses MOVX instructions and code memory accesses with an address greater than OFFFy for the C540U or greater than 1FFFy for the C541U external code memory fetches If EA 0 the ALE generation is always enabled and the bit EALE has no effect After a hardware reset the ALE generation is enabled Special Function Register SYSCON Address B1 y Reset Value XX10XXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 Bly EALE RMAP SYSCON The function of the shaded bit is not described in this section
144. nation For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control Semiconductor Group 2 3 1997 10 01 IE Fundamental Structure gt yi ES 3 C540U C541U 2 2 CPU Timing The C540U C541U has no clock prescaler Therefore a machine cycle of the C540U C541U consists of 6 states 6 oscillator periods Each state is devided into a phase 1 half and a phase 2 half Thus a machine cycle consists of 6 oscillator periods numbererd S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts one oscillator period Typically arithmetic and logic operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 2 2 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the XTAL2 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally a
145. nction Register SCF C541U only Address ABy Reset Value XXXXXX00p MSB LSB Bit No 7 6 5 4 3 2 1 0 ABH WCOL TC SCF Bit Function Reserved bits for future use WCOL SSC write collision interrupt flag WCOL set indicates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed Bit WCEN in the SCIEN register must be set if an interrupt request will be generated when WCOL is set TC SSC transfer complete interrupt flag If TC is set it indicates that the last transfer has been completed Bit TCEN in the SCIEN register must be set if an interrupt request will be generated when TC is set The SSC interrupt is generated by a logical OR of flag WCOL and TC in SFR SCF Both bits can be cleared by software when a 0 is written to the bit location WCOL is reset by hardware when after a preceeding read operation of the SCF register the SSC transmit data register STB is written with data TC is reset by hardware when after a preceeding read operation of the SCF register the receive data register SRB is read the next time The interrupt service routine will normally have to determine whether it was the WCOL or the TC flag that generated the interrupt and the bit will have to be cleared by software Semiconductor Group 7 10 1997 10 01 IE Interrupt System SIEMENS C540U C541U The USB device interrupt request
146. nction registers and the interrupt control logic A clock generation unit provides the clock signal for the USB module for full speed and low speed USB operation Figure 6 25 shows the block diagram of the functional units of the USB module with their interfaces USB Bus D XTAL1 XTAL2 D Module Page 0 Transceiver On chip USB Memory 128 x 8 Internal MCU Bus Data Interface Address MMU gt USB Memory Control Management Control MCB03380 Figure 6 25 USB Module Block Diagram Semiconductor Group 6 32 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 1 Transfer Modes USB data transfers take place between host software and a particular endpoint on a USB device A given USB device may support multiple data transfer endpoints The USB host treats communications with any endpoint of a USB device independently from any other endpoint Such associations between the host software and a USB device endpoint are called pipes As an example a given USB device could have an endpoint supporting a pipe for transporting data to the USB device and another endpoint supporting a pipe for transporting data from the USB device The USB architecture comprehends four basic types of data transfers Table 6 8 USB Transfer Modes Mode Function Control Control data are used to configure devices data transmission is lossless Control pipes are bidirectional data transfer is po
147. nd the setting of the CPOL ad CPHA bits After eight bits have been shifted in the content of the shift register is transferred to the receive buffer register and the transmission complete flag TC is set If the transmitter is enabled in slave mode TEN bit set to 1 the SSC will shift out at STO at the same time the data currently contained in the shift register If the transmitter is disabled the STO output will remain in the tristate state This allows more than one slave to share a common select line If SLS is inactive the SSC will be inactive and the content of the shift register will not be modified 6 3 2 Enable Disable Control Bit SSCEN of the SSCCON register globally enables or disables the synchronous serial interface Setting SSCEN to 0 stops the baud rate generator and all internal activities of the SSC Current transfers are aborted The alternate output functions at pins P1 3 SRI P1 4 STO P1 5 SLS and P1 2 SCLK return to their primary I O port function These pins can now be used for general purpose I O Semiconductor Group 6 22 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U When the SSC is enabled and in master mode pins P1 3 SRI P1 4 STO and P1 2 SCLK will be switched to the SSC control function P1 4 STO and P1 2 SCLK actively will drive the lines P1 5 SLS will remain a regular I O pin The output latches of port pins dedicated to alternate functions must be programmed to l
148. nd the buffers are swapped if the USB buffer is empty After the USB read access has occured at 2 this buffer assigned to USB is empty again UBF 0 and can be swapped again as soon as the CPU has filled its buffer at The number of bytes in the buffer is less or equal MaxLen The MaxLen threshold is always active but an occurrence of SOF if SOFDE 1 or setting bit DONE by software are used to tag the CPU buffer full before reaching MaxLen Number of Data Bytes A cad A SIS SHEA lt x Swap Swap Buffer Buffer MaxLen Lent Len2 Frame n Frame n 1 SOF n 1 SOF n 2 Set Set Set USB read Accesses ES CPU write Accesses MCT03409 Figure 6 36 Dual Buffer Mode USB Read Access Buffer Switching on SOF with SOFDE 1 Semiconductor Group 6 44 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U If the number of data bytes to be transferred is greater than the maximum packet size given by MaxLen the data is split up automatically into packets which are transferred one after the other Figure 6 37 gives an example of an USB read access where data from the CPU is split up into two packets When MaxLen is reached during the CPU write access the currently active buffer is switched to USB side UBF 1 The CPU continues writing data to the buffer When the complete data packet has been written to the buffer by the CPU bit DONE is set by software to indicate the end of the data packet CBF
149. ng oscillator amplifier This pin is used for the oscillator operation with crystal or ceramic resonator Input O Output Semiconductor Group 1 7 1997 10 01 SIEMENS Introduction C540U C541U Table 1 1 Pin Definitions and Functions cont d Symbol Pin Numbers P LCC 44 P SDIP 52 1 0 Function XTAL1 21 24 XTAL1 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed P2 0 P2 7 24 31 28 35 1 0 Port 2 is an 8 bit quasi bidirectional I O port with internal pullup resistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current 7 y in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullup resistors when issuing 1 s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the
150. not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state see figure 5 4 Under worst case conditions fast Voc rise time e g 1 us measured from Vec 4 25 V up to stable port condition the delay between power on and the correct port reset state is Typ 18 us Max 34us The RC oscillator will already run at a Voc below 4 0V lower specification limit Therefore at slower Voc rise times the delay time will be less than the two values given above After the on chip oscillator has finally started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of max 768 cycles of the RC oscillator clock in order to allow the oscillation of the on chip oscillator to stabilize figure 5 4 Il Subsequently the clock is supplied by the on chip oscillator and the oscillator watchdog s reset request is released figure 5 4 IIl However an externally applied reset still remains active figure 5 4 IV and the device does not start program execution figure 5 4 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is a
151. nterrupt System SIEMENS C540U C541U 7 3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IEO IE1 or IPO IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 then at least one more instruction will be executed before any interrupt is vectored too this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the con
152. odes and operation of the SSC checking the status and generating the respective status and interrupt signals 6 3 1 General Operation of the SSC After initialization of the SSC the data to be transmitted has to be written into the shift register STB In master mode this will initiate the transfer by resetting the baudrate generator and starting the clock generation The control bits CPOL and CPHA in the SSCCON register determine the idle polarity of the clock polarity between transfers and which clock edges are used for shifting and sampling data see figure 6 23 While the transmit data in the shift register is shifted out bit per bit starting with the MSB or LSB the incoming receive data are shifted in synchronized with the clock signal at pin SCLK When the eight bits are shifted out and the same number is of course shifted in the contents of the shift register is transferred to the receive buffer register SRB and the transmission complete flag TC is set If enabled an interrupt request will be generated After the last bit has been shifted out and was stable for one bit time the STO output will be switched to 1 forced 1 the idle state of STO This allows connection of standard asynchronous receivers to the SSC in master mode In slave mode the device will wait for the slave select input SLS to be activated low and then will shift in the data provided on the receive input according to the clock provided at the SCLK input a
153. oftware to enable again data transmission If TPWD 0 the transmitter is active default after reset If TPWD 1 the transmitter is in power down mode RPWD USB Receiver Power Down Setting bit RPWD puts the USB receiver into power down mode After a wake up from software power down mode operation bit RPWD must be cleared by software to enable again data reception If RPWD is set the USB bus cannot wake up the C540U C541U form power down mode If RPWD O the USB receiver is active default after reset If RPWD 1 the USB receiver is in power down mode Semiconductor Group 6 59 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U The device interrupt enable register DIER contains the enable bits for the different types of device interrupts With these bits the device interrupts can be individually enabled or disabled The general device interrupt enable bit EUDI is located in SFR IEN1 A device interrupt can be only generated if EUDI and EA global interrupt enable bit in IENO are set too USB Device Interrupt Enable Register DIER Address C3py Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 C34 SEOIE DAIE DDIE SBIE SEIE STIE SUIE SOFIE DIER rw rw rw rw rw rw rw rw Bit Function SEOIE Single ended zero Interrupt Enable Setting bit SEOIE enables the generation of a device interrupt each time a single ended zero is detected for more than 2 5us reset by hos
154. ogic 1 state after reset In slave mode all four control pins will be switched to the alternate function However STO will stay in the tristate state until the transmitter is enabled by SLS input being low and the TEN control bit is set to 1 This allows for more than one slave to be connected to one select line and the final selection of the slave will be done by a software protocol 6 3 3 Baudrate Generation Master Mode only The baudrate clock is generated out of the processor clock fosc This clock is fed into a resetable divider with seven outputs for different baudrate clocks fosc 4 to fosc 256 One of these eight clocks is selected by the bits BRS2 1 0 in SSCCON and provided to the shift control logic Whenever the shift register is loaded with a new value the baudrate generation is restarted with the trailing edge of the write signal to the shift register In the case of CPHA 0 the baudrate generator will be restarted in a way that the first SCLK clock transisition will not occur before one half transmit clock cycle time after the register load This ensures that there is sufficient setup time between MSB or LSB valid on the data output and the first sample clock edge and that the MSB or LSB has the same length than the other bits No special care is necessary in case of CPHA 1 because here the first clock edge will be used for shifting 6 3 4 Write Collision Detection When an attempt is made to write data to the shift re
155. om powe down enable bit Setting EWPD before entering power down mode enables the external wake up from power down mode capability via the pin P3 2 INTO or by the USB module WS Wake up from software power down mode source select WS 0 wake up via pin P3 2 INTO selected default after reset WS 1 wake up via USB bus selected Reserved bits for future use Semiconductor Group 9 2 1997 10 01 IE Power Saving Modes gt ii ES C540U C541U 9 1 Idle Mode In the idle mode the main oscillator of the C540U C541U continues to run but the CPU is gated off from the clock signal However the interrupt system the SSC C541U only the USB module and the timers with the exception of the watchdog timer C541U only are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all peripherals are disabled or stopped the maximum power reduction can be achieved This state is also the test condition for the idle mode Tec So the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depend
156. ounter address exceeds 1FFFy C540U OFFFy Address locations 2000 through FFFFy C540U 1000H through OFFFy are then fetched from the external program memory If the EA pin is held low the C540U C541U fetches all instructions from the external 64K byte program memory 3 2 Data Memory Data Space The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of data memory can be accessed through direct or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit multi purpose registers occupy locations 0 through 1Fy in the lower RAM area The next 16 bytes locations 204 through 2Fy contain 128 directly addressable bit locations The stack can be located anywhere in the internal data memory address space and the stack depth can be expanded up to 256 bytes The external data memory can be expanded up to 64 Kbyte and can be accessed by MOVX instructions that use a 16 bit or an 8
157. output STO will go to the high output level logic 1 and remain there until the next transmission is started However when enabling the SSC after reset the logic level of STO will be undefined until the first transmission starts When CPHA is 0 the MSB or LSB will output immediately after the data was written into the shift register The first clock edge of SCLK will be used for sampling the input data the next to shift out the next bit Between transmissons the data output STO will be 1 SCLK CPOL 0 SCLK CPOL 1 Write to STB Register STO Inout Sample at SRI Write to STB Register STO Input Sample at SRI MCS02440 1 MSB shift first mode is assumed Bit LSBSM in register SCCMOD is 0 Figure 6 23 Master Mode Operation of SSC Semiconductor Group 6 25 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 3 6 2 Slave Mode Operation Figure 6 24 shows the clock data control relationship of the SSC in slave mode When SLS is active low and CPHA is 1 the MSB or LSB of the data that was written into the shift register will be provided on the transmitter output after the first clock edge if the transmitter was enabled by setting the TEN bit to 1 the receiver input will sample the input data with the next clock edge The direction rising or falling of the respective clock edge is depending on the clock polarity selected In this case CPHA 1
158. pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode ALE and PSEN hold at logic low level see table 9 1 The power down mode can be left either by an active reset signal or by a low signal at the P3 2 INTO pin or any activity on the USB bus The USB module enters the suspend state when it detects no activity on the USB bus for more than 6 ms The suspend state is left when bus activity is detected on the USB bus Leaving the suspend state can if selected and enabled wake up the power down mode Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state Using the INTO pin or USB bus for power down mode exit maintains the state of the SFRs which has been frozen when power down mode is entered In the power down mode of operation Voc can be reduced to minimize power consumption It must be ensured however that is Vo not reduced before the power down mode is invoked and that Voc is restored to its normal operating level before the power down mode is terminated Semiconductor Group 9 5 1997 10 01 SIEMEN Power Saving Modes P C540U C541U 9 2 1 Entering Power Down Mode The power down mode is entered by two consecutive instructions The first instruction has to set the flag bit PDE PCON 1
159. r information which has been transmitted to the USB module during the software initialization procedure This EPNum information is used for the selection of an endpoint specific base address register As the maximum data packet length of each endpoint can individually be programmed there are some fixed start addresses for the endpoints The user program defines the base address for the first data byte of the corresponding endpoint by writing the endpoint specific base address register EPBAn The length depends on the amount of data to be read or written The user must take care to assign a buffer space at least as large as the maximum packet size of the endpoint The address of the currently accessed byte in the USB memory area of the selected endpoint is defined by an address offset which must be added to the endpoint base address in order to get the correct address for the USB memory buffer The structure is shown in figure 6 39 EPBA 0 PAGEO 0 0 Q A06 A05 A04 A03 EPBA 1 PAGE1 0 0 0 A16 A15 A14 A13 EPBA 2 EPNum PAGE2 0 o o A26 A25 A24 A23 of the Actual EPBA 3 Endpoint PAGE 3 0 0 A836 A35 A34 A33 EPBA 4 PAGE 4 o o age a45 EPBAn An3 ADROFF 0 O AO5 AO4 AO3 AO2 AO1 USB Memory Addr 0 AD6 AD5 AD4 AD3 AD2 AD1 Note Only one Bit of the Bit pairs An5 AO5 An4 AO4 An3 AO3 can be s
160. ral Components C540U C541U Bit Function SUIE Setup interrupt enable Bit SUIE enables the generation of a device interrupt on a succesful reception of a setup packet which must be processed by the CPU If SUIE 0 the setup interrupt is disabled If SUIE 1 the setup interrupt is enabled SOFIE Start of frame interrupt enable bit SOFIE enables the generation of a device interrupt on the detection of a start of frame packet on the USB If SOFIE 0 the start of frame interrupt is disabled If SOFIE 1 the start of frame interrupt is enabled Semiconductor Group 6 61 1997 10 01 On Chip Peripheral Components SIEMENS C540U C541U The device interrupt request register DIRR contains the interrupt request flags of the different types of device interrupts All Interrupt request flags in DIRR are reset by hardware after DIRR has been read USB Device Interrupt Request Register DIRR Address C4py Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 C4y SEOI DAI DDI SBI SEI STI SUI SOFI DIRR r r r r r r r r Bit Function SEOI Single ended zero interrupt Bit SEOI is set each time a single ended zero is detected for equal or greater than 2 5us EOP 2 bit times is not detected DAI Device attached interrupt Bit DAI is automatically set after detection of the USB device being attached to the USB bus DDI Device detached interrupt Bit DDI is automatically set af
161. re 8 2 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 10 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the C540U C541U in its defined reset state The reset is performed because a clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions The watchdog timer status flag WDTS is not reset the watchdog timer however is stopped and bit OWDS is set This allows the software to examine error conditions detected by the watchdog timer even if meanwhile an oscillator failure occured Semiconductor Group 8 6 1997 10 01 SIEMENS Fail Safe Mechanisms C540U C541U The oscillator watchdog is able to detect a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference the watchdog starts a f
162. register contains the device specific interrupt flags of the USB module These flags describe special events of the USB module If a request flag is set it is automatically cleared after a read operation of the DIRR register Special Function Registers DIRR Address C4py Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 C4y SEO DAI DDI SBI SEI STI SUI SOFI DIRR For accessing DIRR SFR EPSEL must be 80H Bit Function SEO Single ended zero interrupt Bit SEO is set each time a single ended zero is detected for equal or greater than 2 5us EOP 2 bit times is not detected DAI Device attached interrupt Bit DAI is automatically set after detection of the USB device being attached to the USB bus DDI Device detached interrupt Bit DDI is automatically set after detection of the device being detached from the USB bus SBI Suspend begin interrupt Bit SBI is automatically set when the suspend mode is entered SEI Suspend end interrupt Bit SBI is automatically set when the suspend mode is left STI Status interrupt Bit STI is set if the host requests a status transfer and the device answers with NACK SUI Setup interrupt Bit SUI is automatically set after a successful reception of a setup packet SOFI Start of frame Bit SOF is automatically set after detection of a start of frame packet on the USB Semiconductor Group 7 11 1997 10 01 IE Interrupt System SIEM
163. rred to the USB memory location which is defined by the content of the endpoint specific endpoint base address register EPBAn and the content of the address offset register ADROFF At USB memory read accesses from the CPU the data is transfered in reverse direction A write operation to USBVAL is only successfull if either DIR 0 and CBF 1 write operation or DIR 1 and CBF 0 read operation USB Data Register USBVAL Address D3 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D3H T 6 5 4 3 2 1 0 USBVAL rw rw rw rw rw rw rw rw Bit Function USBVAL 7 0 USB data value USBVAL stores the 8 bit data byte during transfers from CPU to USB memory and from USB memory to CPU Bit NOD in the EPIRn register indicates when the CPU processes an USBVAL read operation with an empty USB buffer or a USBVAL write operation to a full USB buffer Semiconductor Group 6 54 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U In most cases the CPU accesses only one endpoint buffer until it is full CBF 1 at CPU write access or empty CBF 0 at CPU read access As the USB memory size is 128 bytes per page the maximum packet length is limited to 64 bytes Therefore only the lowest 6 bits of ADROFF AO5 AOO are required for offset definiton A write operation to ADROFF is only successfull if either DIR 0 and CBF 1 write operation or DIR 1 and CBF 0 read operation
164. rrupt control Bit Function TF1 Timer 1 overflow flag Set by hardware on timer counter 1 overflow Cleared by hardware when processor vectors to interrupt routine TFO Timer 0 overflow flag Set by hardware on timer counter 0 overflow Cleared by hardware when processor vectors to interrupt routine IE1 External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when processor vectors to interrupt routine IT1 External interrupt 1 level edge trigger control flag If IT1 0 low level triggered external interrupt 1 is selected If IT1 1 edge triggered mode for external interrupt 1 is selected The bits IE1TR and IE1TF in SFR ITCON see section 7 4 further define which signal transition at pin INT1 rising and or falling edge generates an interrupt IEO External interrupt 0 request flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when processor vectors to interrupt routine ITO External interrupt 0 level edge trigger control flag If ITO 0 low level triggered external interrupt O is selected If ITO 1 edge triggered mode for external interrupt 0 is selected The bits IEOTR and IEOTF in SFR ITCON see section 7 4 further define which signal transition at pin INTO rising and or falling edge generates an interrupt Semiconductor Group 7 9 1997 10 01 SIEMENS Interrupt System C540U C541U Special Fu
165. rs Registers Registers MCD03312 Figure 6 41 Register Structure of the USB Module Note In the description of the USB module registers bits are marked as rw r or w Bits marked as rw can be read and written Bits marked as r can be read only Writing any value to r bits has no effect Bits marked as w are used to execute internal commands which are triggered by writing a 1 Writing a O to w bits has no effect Reading w bits returns a 0 Semiconductor Group 6 52 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 7 1 Global Registers The global registers GEPIR EPSEL ADROFF and USBVAL describe the global functionality of the USB module and can be accessed via unique SFR addresses The Endpoint Select Register EPSEL contains 4 bits which are used to select one of the register blocks of the five endpoint register blocks or the device register block These register blocks are mapped to the same SFR address range of C14 to C7 USB Endpoint Select Register EPSEL Address D24 Reset Value 80y Bit No MSB LSB 7 6 5 4 3 2 1 0 D24 EPS7 0 0 0 0 EPS2 EPS1 EPSO EPSEL rw r r r r rw rw rw Bit Function EPS7 Endoint device register block select bits EPS2 These four bits select the active register block of endpoint or device registers ae EPS7 EPS2 EPS1 EPSO Selected Register 1 X X X Device register set selected 0 0 0
166. rt up time plus 2 machine cycles which under normal conditions must be at least 10 20 ms for a crystal oscillator This requirement is typically met using a capacitor of 4 7 to 10 uF The same considerations apply if the reset signal is generated externally figure 5 1 b In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive Semiconductor Group 5 1 1997 10 01 IE Reset System Clock SIEMENS C540U C541U MCD03376 Figure 5 3 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location 0000 After reset is internally accomplished the port latches of ports 0 to 3 are set to FFy This leaves port 0 floating since it is an open drain port when not used as data address bus All other I O port lines ports 1 and 3 output a one 1 Port 2 lines output a zero or one after reset if EA is held low or high The content of the internal RAM of the C540U C541U is not affected by a reset After power up the content is undefined while it remains unchanged during a reset if the power supply is not turned off A reset operation of the USB module in the C540U C541U can only be achieved under software control A hardware reset operation puts only the internal CPU interface of the USB module and its MMU into a well defined reset state The software reset which must be execu
167. rupt is enabled ESSC SSC general interrupt enable C541U only If ESSC 0 the SSC general interrupt is disabled If ESSC 1 the SSC general interrupt is enabled WCEN SSC write collision interrupt enable C541U only If WCEN 0 the SSC write collision interrupt is disabled If WCEN 1 the SSC write collison interrupt is enabled Additionally bit ESSC must be set if the SSC write collision interrupt should be generated TCEN SSC transfer completed interrupt enable C541U only If TCEN 0 the SSC transfer completed interrupt is disabled If TCEN 1 the SSC transfer completed interrupt is enabled Additionally bit ESSC must be set if the SSC transfer completed interrupt should be generated Semiconductor Group 7 5 1997 10 01 SIEMENS Interrupt System C540U C541U Special Function Registers DIER Address C3p Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 C34 SEOIE DAIE DDIE SBIE SEIE STIE SUIE SOFIE DIER For accessing DIER SFR EPSEL must be 804 Bit Function SEOIE USB single ended zero interrupt enable If SEOIE 0 the single ended zero interrupt is disabled If SEOIE 1 the single ended zero interrupt is enabled DAIE USB device attached interrupt enable If DAIE 0 the USB device attached interrupt is disabled If DAIE 1 the USB device attached interrupt is enabled DDIE USB device detached interrupt enable If DDIE 0 the USB
168. rupt service routine is completed or else another interrupt will be generated Since the external interrupt pins are sampled once in each machine cycle an input high or low should be held for at least 6 oscillator periods to ensure sampling If the external interrupt is transition activated the external source has to hold the request pin high for at least one cycle and then hold it low for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set see figure 7 51 The external interrupt request flags will automatically be cleared by the CPU when the service routine is called a Level Activated Interrupt Low Level Threshold 1 Machine Cycle b Transition Activated Interrupt High Level Threshold IXETF 1 1 Machine Cycle 1 Machine Cycle Low Level Threshold Transition to be detected High Level Threshold INTx N y IXETR 1 A Low Level Threshold MCT02577 Figure 7 51 External Interrupt Detection Semiconductor Group 7 18 1997 10 01 IE Interrupt System SIEMENS C540U C541U The edge triggered interrupt mode selection for the external interrupts is selected by bits in SFR ITCON External Interrupt Trigger Condition Register The edge trigger mode selection is defined in a way default value of ITCON after reset that their function is upward compatible to the basic external interrupt
169. s cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 10 MHz Variable Clock clock 1 CLP 2 MHz to 12 MHz Duty Cycle 0 4 to 0 6 min max min max RD pulse width fai RH 180 3CLP 70 ns WR pulse width twi wn 180 3CLP 70 ns Address hold after ALE uLaxe 56 CLP 27 ns RD to valid data in fai pv 110 l 2 CLP ns TCL himin 90 Data hold after RD RHDX 0 0 ns Data float after RD RHDZ 63 CLP 20 ns ALE to valid data in fiiov 200 4 CLP 133 ns Address to valid data in lavov 211 4 CLP ns TCL 155 ALE to WR or RD fiw 66 166 CLP CLP ns TCL min 50 TCL mint 50 Address valid to WR CavwL 70 2CLP 97 ns WR or RD high to ALE high twin 18 58 TCLumn 25 TCLymin 25 ns Data valid to WR transition favwx 8 TCLi min 25 ns Data setup before WR favwH 163 3 CLP ns TCL min 120 Data hold after WR wHox 8 TCLiimin 25 ns Address float after RD TRLaz 0 0 ns Semiconductor Group 11 5 1997 10 01 SIEMENS Device Specifications C540U C541U External Clock Drive Characteristics Parameter Symbol CPU Clock 12 MHz Variable CPU Clock Unit Duty cycle 0 4 to 0 6 1 CLP z 2 to 12 MHz min max min max Oscillator period CLP 83 3 83 3 83 3 500 ns High time TCLy 33 33 CLP TCL ns Low time TCL 33 33 CLP TCL ns Rise time ta 12
170. s ate 3 8 6 60 7 6 Master slave mode 6 24 GSE TRDO eara e oder a beau ai 3 8 pe UR oo IOR O 3 8 Save Mode MUNG ateos 6 20 Semiconductor Group 12 5 1997 10 01 SIEMENS Index C540U C541U Write collision detection 6 23 SSG Iming is svxo atiae non 11 10 SSCCON sess 3 4 3 6 6 27 Version byte access timing 11 15 SSCMOD 3 4 3 6 6 31 A e mes Pasa 3 4 3 6 6 14 S DADO t 50 dd Conf 3 8 SPI doses Puls eta eed Der Rte 3 4 3 6 6 14 SA ru atas due A E 3 8 05912 PD E 3 4 3 6 6 16 SLAELB as ee uota et iru 3 9 TPWD eaaet te ee el BRS 3 8 6 59 STADIES osea ote Rc od 3 9 TRO 3 6 6 15 STALLA cath a Ree Sarees 3 9 TE cc RS RERO 3 6 6 15 STALCI e sedet IIo er et pst p SUE 6 64 TRIO anos eit dn the ehh ad 3 6 6 31 S Brens s iano ne ine een t 3 4 3 6 6 31 ro 3 8 6 62 7 11 UB FO PE 3 8 STIE 6 eee eee eee eee 3 8 6 60 7 6 Be A ea Ea 3 8 STO cece eee eee eee 3 6 6 21 A moles Md 3 9 SUI lesse 3 8 6 62 7 11 WEES uae aa ani ae i 3 9 SUIE 2 ee eee eee 3 8 6 61 7 6 Wl HC ee ree Meer 3 9 SUSP coco 3 8 6 57 A cat nci soar 6 66 SW Dale ie it tard Rods 3 7 8 3 B ex METTE CEN 3 8 6 58 SWR sa aauaaaaranarenra ne 3 8 6 57 USB module 6 32 to 6 75 SYSCON ccoo 3 3 3 4 3 7 4 4 Block diagram 6 32 Control transfer 6 51 A D a doter aed scs 3 7 Detach attach detection 6 76 SM aasa eth Tp c EE MTM 3
171. s detected bit DA in the device control register DCR is set and a device interrupt can be generated if required bit DAI in SFR DIRR is set The interrupt service routine of this device interrupt must completely initialize the USB device module The device detached detection resets bit DA and sets bit DDI in SFR DIRR and can generate a device interrupt too P3 1 DADD C540U N Channel FET MCS03417 Figure 6 46 Device Attached Device Detached detection in self powered mode 6 4 10 2 Bus Powered Mode In bus powered mode the USB device is driven by the power supply from the USB bus The maximum power consumption is given by the USB specification In order to respect this specification the power consumption in suspend mode should not exceed 500 uA An explicit device attached detection in this mode is not necessary If the CPU is running the device is attached so the USB device module has to be configured only after power on The device detach action has no significance concerning software because the device is no longer powered and the CPU stops As a result no attach detach detection is needed In this mode pin DADD can be used as standard lO pin with bit DA monitoring its status and the interrupt generation on DA should not be used If the interrupt generation on bit DA remains activated a request must not be interpreted as attached detached action but as an external interrupt request on pin DADD which is generating a
172. s mode ALE PSEN 0 9 Voc Tou 80 nA Logic 0 input current ports 1 2 3 J 10 50 uA Vin 0 45 V Logical 1 to 0 transition current Hi 65 650 uA Vin 2V ports 1 2 3 Input leakage current port 0 EA J 1 uA 0 45 lt Vn lt Vec Pin capacitance Cio 10 pF f 1 MHz Ta 25 C 7 Overload current Iov t5 mA 197 Programming voltage Vpp 10 9 12 1 V 11 5V 5 Notes see next page Semiconductor Group 11 2 1997 10 01 SIEMENS Device Specifications C540U C541U Power Supply Current Parameter Symbol Limit Values Unit Test Condition typ 9 max 9 Active mode 12MHz ec 15 TBD mA Idle mode 12 MHz ec TBD TBD mA 5 Power down mode Ipp TBD 50 pA Vec 2 5 5 V9 Notes 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input 2 Capacitive loading on ports O and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0 9 Voc specification when the address lines are stabilizing 3 Ipp power down mode is m
173. s not handled by the USB module automatically a setup interrupt bit SUI is set indicates the end of a setup phase Additionally the status and control bits UBF CBF and SOD are reset 6 4 6 2 Data Stage This stage is defined only for requests that require data tranfers The direction of this data stage is always predicted to be from Host to Device bit DIR is automatically cleared after the setup stage occured The first data packet may immediately be send from the Host to the control endpoint according to this configuration of bit DIR while NACK will be automatically returned from the Device to the Host in case of USB read access The configuration of bit DIR 0 predicts an USB write access while an USB read access causes automatically a NACK no acknowledge to be generated and the direction bit to be changed DIR 1 USB read access The direction of the next transfer can also be predicted under software control bit SETWR is set to be an USB read access DIR 1 This feature is used if the direction of the data stage is known and the data packet to be transferred from the CPU to the Host is set up before the next USB access occured Therefore the direction bit must be changed under software control to be able to transfer the data packet within the first USB read access Status bit SOD is set under hardware control to indicate valid data to be read by CPU in case of USB write access or data to be written by CPU in case of USB read acce
174. s on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on This applies to the serial interface in case it cannot finish reception or transmission during normal operation The control signals ALE and PSEN hold at logic high levels Table 9 1 Status of External Pins During Idle and Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low Port 0 Data Data Float Float Port 2 Data Data Address Data Port 3 Data alternate Data last output Data alternate Data last output outputs outputs As in normal operation mode the ports can be used as inputs during idle mode Therefore the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode Semiconductor Group 9 3 1997 10 01 IE Power Saving Modes g
175. s only LOOPB 0 The SSC operates as specified LOOPB 1 The STO output is connected internally via an inverter to the SRI input allowing to check the transfer locally without a second SSC device TRIO SSC disable tristate mode of SSC inputs This bit should be used for test purposes only TRIO 0 The SSC operates as specified TRIO 1 The SSC inputs will be connected to the output latch of the corresponding port pin This allows a test of the SSC in slave mode by simulating a transfer via a program setting the port latches accordingly 5 1 All bits of this register are set to O after reset When writing SSCMOD these bits must be written with O LSBSM SSC LSB shift mode If LSBSM is cleared the SSC will shift out the MSB of the data first LSB last If LSBSM is set the SSC will shift out LSB first and MSB last Semiconductor Group 6 31 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 4 USB Module The USB module in the C540U C541U handles all transactions between the serial USB bus and the internal parallel bus of the microcontroller The USB module includes several units which are required to support data handling with the USB bus the on chip USB bus transceiver the USB memory with two pages of 128 bytes each the memory management unit MMU for USB and CPU memory access control the UDC device core for USB protocol handling the microcontroller interface with the USB specific special fu
176. set Value 00y Special Function Register TL1 Address 8By Reset Value 00y Special Function Register TH1 Address 8D Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 8AH 7 6 iD 4 3 2 1 0 TLO 8Cy 7 6 5 4 EO 2 1 0 THO 8By 7 6 5 4 3 2 1 0 TL1 8DH 7 6 5 4 a 2 1 0 TH1 Bit Function TLx 7 0 Timer counter 0 1 low value imd Operating Mode Description 0 TLx holds the 5 bit prescaler value 1 TLx holds the lower 8 bit part of the 16 bit timer counter value 2 TLx holds the 8 bit timer counter value 3 TLO holds the 8 bit timer counter value TL1 is not used THx 7 0 Timer counter 0 1 high value ud Operating Mode Description 0 THx holds the 8 bit timer counter value THx holds the higher 8 bit part of the 16 bit timer counter value THx holds the 8 bit reload value 1 2 3 THO holds the 8 bit timer value TH1 is not used Semiconductor Group 6 14 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Special Function Register TCON Address 884 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 8Fy 8Ey 8DyH 8Ch 8By 8AH 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON The shaded bits are not used for controlling timer counter 0 and 1 Bit Function TRO Timer 0 run control bit Set cleared by software to turn timer counter 0 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by h
177. special function registers SFRs in the SFR area include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C540U C541U are listed in table 3 2 and table 3 3 In table 3 2 they are organized in groups which refer to the functional blocks of the C540U C541U Table 3 3 illustrates the contents of the SFRs in numeric order of their addresses Semiconductor Group 3 3 1997 10 01 SIEMENS Memory Organization C540U C541U Table 3 2 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator E0y 00H B B Register FO 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 824 00H PSW Program Status Word Register DOW 00H SP Stack Pointer 81H 07H VRO Version Register 0 FCH C5H VR1 Version Register 1 FDH C1H VR2 Version Register 2 FEH YY y SYSCON System Control Register BiH XX10XXXXp Interrupt IENO Interrupt Enable Register 0 A8y OXXX0000p System IEN1 Interrupt Enable Register 1 A9H XXXXX000p IPO Interrupt Priority Register O B8y XXXX0000p IP1 Interrupt Priority Register 1 BOL XXXXX000p ITCON External Interrupt Trigger Condition Register 9A XXXX101 Op Ports PO Port 0 804 FFH P1 Port 1 90H FFH P2 Port 2 A0y FFH P3 Port 3 Boy FFy Timer 0 TCON Timer 0 1 Control Register 88y 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 Hig
178. ss 6 4 6 3 Status Stage The status stage is always performed to report the result of the requested operation A status stage initiated by the Host but not terminated according to the configuration of ESP ESP 0 is indicated by a status interrupt bit STI is set Bit ESP has to be set under software control to enable the acknowledge of the status stage Semiconductor Group 6 51 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U 6 4 7 Register Set Two different kinds of registers are implemented in the USB module The global registers GEPIR EPSEL ADROFF USBVAL describe the basic functionality of the complete USB module and can be accessed via unique SFR addresses For reduction of the number of SFR addresses which are needed to control the USB module inside the C540U C541U device registers and endpoint registers are mapped into an SFR address block of seven SFR addresses C14 to C74 The endpoint specific functionality of the USB module is controlled via the device registers DCR DPWDR DIER DIRR and the frame number registers An endpoint register set is available for each endpoint n 0 4 and describes the functionality of the selected endpoint Figure 6 41 explains the structure of the USB module registers Global Registers GEPIR D6 yy USBVAL D34 ojejo jala elho ADROFF D4 0 0 5 43 29 Device Endpoint 0 Endpoint 1 Endpoint 2 Endpoint 3 Endpoint 4 Registers Registers Registers Registe
179. ssible in both directions via one pipe Endpoint 0 is always configured as control endpoint with a maximum buffer length of 8 bytes The control endpoint can be configured to handle data packets of 64 bytes maximum length isochronous Isochronous data are continuous and real time in creation and consumption full speed such as voice data In this case real time is defined from frame to frame mode only Isochronous data transfer has the highest priority but is not always lossless Isochronous pipes are always unidirectional so one endpoint can be associated to an IN pipe or an OUT pipe The C540U C541U supports up to 64 bytes Interrupt Interrupt data are a small amount of data which are transferred to the host every n frames with n being programmable by the host Data delivery is lossless Interrupt pipes are always unidirectional IN pipes the maximum data packet length is limited to 64 bytes Bulk Bulk data can be a larger amount of data which can be split by the host in several full speed data packets witin one frame Data delivery is lossless mode only Bulk pipes are always unidirectional so one endpoint can be associated to an IN pipe or an OUT pipe The maximum data packet length is limited to 64 bytes Semiconductor Group 6 33 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 4 2 USB Memory Buffer Modes 6 4 2 1 Overview Every endpoint of the USB module in the C540U C541U can opera
180. t 1 0 Timer 1 Port 1 i 6 8 Bit Digit 1 0 SSC SPI Interface C541U only Port 2 8 Bit Digit 1 0 Port 3 8 Bit Digit I O Transceiver Interrupt Unit 1 P LCC 44 6 Bit Port P SDIP 52 8 Bit Port MCB03345 Figure 2 1 Block Diagram of the C540U C541U Semiconductor Group 2 1 1997 10 01 IE Fundamental Structure gt yi ES 3 C540U C541U 2 1 CPU The CPU is designed to operate on bits and bytes The instructions which consist of up to 3 bytes are performed in one two or four machine cycles One machine cycle requires six oscillator cycles this number of oscillator cycles differs from other members of the C500 microcontroller family The instruction set has extensive facilities for data transfer logic and arithmetic instructions The Boolean processor has its own full featured and bit based instructions within the instruction set The C541U uses five addressing modes direct access immediate register register indirect access and for accessing the external data or program memory portions a base register plus index register indirect addressing Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 12 MHz clock 58 of the instructions execute in 500 ns The CPU Central Processing Unit of the C540U C541U consists of the instruct
181. t ii ENS C540U C541U 9 1 1 Entering Idle Mode The idle mode is entered by two consecutive instructions The first instruction sets the flag bit IDLE PCON O and must not set bit IDLS PCON 5 the following instruction sets the start bit IDLS PCON 5 and must not set bit IDLE PCON 0O The hardware ensures that a concurrent setting of both bits IDLE and IDLS does not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after being set If one of these register bits is read the value that appears is 0 This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer s task of system protection without effect PCON is not a bit addressable register so the above mentioned sequence for entering the idle mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode In idle mode the USB module can be fully functional or can be switched off If it is switched off in idle mode the following steps must be processed before entering the idle mode USB module clock is switched off by software resetting bit UCLK in SFR DCR additionally in full speed mode USB PLL is switched off resetting bit PCLK
182. t not EOP If SEOIE 0 the single ended zero interrupt is disabled If SEOIE 1 the single ended zero interrupt is enabled DAIE Device attached interrupt enable Setting bit DAIE enables the generation of a device interrupt when it is attached to the USB bus If DAIE 0 the device attached interrupt is disabled If DAIE 1 the device attached interrupt is enabled DDIE Device detached interrupt enable Setting bit DDIE enables the generation of a device interrupt when it is detached from the USB bus If DDIE 0 the device detached interrupt is disabled If DDIE 1 the device detached interrupt is enabled SBIE Suspend begin interrupt enable Setting bit SBIE enables the generation of a device interrupt if bit SBI is set this means the suspend mode is entered If SBIE 0 the suspend begin interrupt is disabled If SBIE 1 the suspend begin interrupt is enabled SEIE Suspend change interrupt enable Setting bit SEIE enables the generation of a device interrupt if bit SEI is set this means the suspend mode is left If SEIE 0 the suspend change interrupt is disabled If SEIE 1 the suspend change interrupt is enabled STIE Status interrupt enable Bit STIE enables the generation of a device interrupt at the end of the status phase of a control transfer If STIE 0 the status interrupt is disabled If STIE 1 the status interrupt is enabled Semiconductor Group 6 60 1997 10 01 SIEMENS On Chip Periphe
183. t SWR is cleared by hardware and bit DINIT is set to indicate the start of the initialization sequence The USB module must be functionally initialized from the CPU by writing five configuration bytes for each endpoint to the USBVAL register Thereafter bit DONEO in register EPBSO must be set by software Figure 6 40 shows the 5 byte configuration block which must be transmitted by the CPU to the USB module via the USBVAL register for each endpoint The gray shaded fields have a fixed 0 or 1 value for each endpoint while the white bitfields have to be filled by parameters according table 6 10 EPPackSize Isb 0 0 0 Constant data for each USB configuration block Figure 6 40 USB Configuration Block The five byte USB configuration block must be transfered sequentially byte O to byte 4 from the CPU to the USB module for each endpoint beginning with endpoint 0 followed by the USB configuration block for endpoint 1 and so on up to the USB configuration block for endpoint 4 Semiconductor Group 6 49 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U EPNum is set to 000p 001p up to 100p for endpoints 0 up to 4 After this action bit DINIT is reset by hardware and the software reset and initialization sequence are finished Table 6 10 Bitfield Definition of USB Configuration Block Bitfield Description EPNum This 3 bit field sp
184. t pins In the C540U C541U the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip This allows correct resetting of the part and brings all ports to the defined state The delay time between power on and correct reset state is max 34 us More details about the fast internal reset procedure after power on are described in chapter 5 of this manual Semiconductor Group 8 7 1997 10 01 SIEMENS Fail Safe Mechanisms C540U C541U Semiconductor Group 8 8 1997 10 01 IE Power Saving Modes gt ii ENS C540U C541U 9 Power Saving Modes The C540U C541U provides two power saving modes Idle mode Power down mode The functions of the power saving modes are controlled by bits which are located in the special function registers PCON und PCON1 PCON is located at address 874 PCON1 is located in the mapped SFR area and is accessed with RMAP 1 Bit RMAP is located in SFR SYSCON B1 bit 4 The bits PDE PDS and IDLE IDLS located in SFR PCON select the power down mode or
185. ta Line The pin D can be directly connected to USB cable transceiver is integrated on chip P1 0 P1 4 5 7 7 9 14 41 1 0 Port 1 12 34 44 51 15 40 is an 6 bit P LCC 44 or 8 bit P SDIP 52 quasi bidirectional I O port with internal pullup resistors Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current 7 q in the DC characteristics because of the internal pullup resistors Port 1 also contains two outputs with LED drive capability as well as the four pins of the SSC C541U only The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate except when used for the compare functions The secondary functions are assigned to the port 1 pins as follows 5 7 P1 0 LEDO LEDO output 6 8 P1 1 LED1 LED1 output 7 9 P1 2 SCLK SSC Master Clock Output SSC Slave Clock Input C541U only 12 13 P1 3 SRI SSC Receive Input C541U only 34 41 P1 4 STO SSC Transmit Output C541U only 44 51 P1 5 SLS SSC Slave Select Inp C541U only 15 P1 6 P SDIP 52 only 40 P1 7 P SDIP 52 only Input O Output Semiconductor Group 1 6 1997 10 01 SIEMENS Introduction C540U C541U Table 1 1 Pin Definitions and Functions cont d Symbol Pin Numbers P LCC 44 P SDIP 52 1 0 Function RESET
186. tal controlled positive reactance oscillator a more detailed schematic is given in figure 5 8 It operates in fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal Semiconductor Group 5 7 1997 10 01 IE Reset System Clock SIEMENS C540U C541U To Internal Timing Circuitry C540U XTAL2 XTAL1 C541U THE pS MCD03395 Figure 5 8 On Chip Oscillator Circuiry To drive the C540U C541U with an external clock source the external clock signal has to be applied to XTAL1 as shown in figure 5 9 XTAL2 has to be left unconnected A pullup resistor is suggested to increase the noise margin but is optional if Vo of the driving gate corresponds to the V specification of XTAL1 C540U C541U N C XTAL2 External Clock gt XTAL1 Signal MCD03396 Figure 5 9 External Clock Source Semiconductor Group 5 8 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 On Chip Peripheral Components This chapter gives detailed information about all on chip peripherals of the C540U C541U except for the integrated interrupt controller which is described separately in chapter 7 6 1 Parallel I O The C540U C541U in the P SDIP 52 package has four 8 bit I O ports In
187. te in two modes dual buffer mode and single buffer mode Each mode provides random or sequential access to the USB memory Figure 6 26 shows the possible buffer modes Buffer Modes Dual Buffer Mode Single Buffer Mode Sequential Random Sequential Access Access Access MCD03399 Figure 6 26 Buffer Modes of the C540U C541U USB Module Single Buffer Mode In single buffer mode the USB and the CPU use one common USB memory page The active buffer page is either page 0 or page 1 Dual Buffer Mode In dual buffer mode the USB and the CPU write into different USB memory pages allowing back to back data transfers Switching between the pages is done fully automatically enabling a high data transfer rate between CPU and USB module Random Access Random access is available in single buffer mode and dual buffer mode Random access allows to change only a few bytes in a data block of the USB memory buffer When the CPU has modified the bytes in the data block setting of bit DONE by software marks the buffer ready for transmission or reception of data over the USB pipe For modification of a specific byte in the buffer the CPU must write the address to SFR ADROFF and read write the data byte from to register USBVAL Sequential access In sequential access mode the CPU accesses the data register USBVAL continuously without setting the address of the next USB memory buffer location This is done automatically if bit INCE increment enabl
188. ted after a hardware reset is initiated by setting bit SWR in SFR DCR by software Bit SWR is reset automatically by hardware when the software reset operation of the USB module is finished Further with the reset of bit SWR bit DINIT in DCR is set indicating the CPU that it has to initialize the endpoints of USB module Semiconductor Group 5 2 1997 10 01 SIEMEN Reset System Clock x C540U C541U 5 2 Fast Internal Reset after Power On The C540U C541U uses the oscillator watchdog unit for a fast internal reset procedure after power on Figure 5 1 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family do not enter their default reset states before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the C540U C541U the oscillator watchdog unit avoids this situation In this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has
189. ter detection of the device being detached from the USB bus SBI Suspend begin interrupt Bit SBI is automatically set when the suspend mode is entered SEI Suspend end interrupt Bit SBI is automatically set when the suspend mode is left STI Status interrupt Bit STI is set if the host requests a status transfer and the device answers with NACK if bit ESP is set the device answers with ACK and STI is not set SUI Setup interrupt Bit SUI is automatically set after a successful reception of a setup packet which is not handled by the USB module and must be forwarded to the CPU The setup packet itself is limited to 8 bytes and is stored at USB memory adresses 00 to 07y and can be accessed with EPSEL 7 1 If a setup interrupt occurs STI is set the control and status bits UBFO CBFO SODO and DIRO in the endpoint 0 registers EPBSO and EPIRO are cleared DIRO 0 predicts the direction of the next USB access data phase to be from host to CPU Bit DIRO is automatically set CPU to host if the host tries to perform a read access in the first data packet SOFI Start of frame Bit SOF is automatically set after detection of a start of frame packet on the USB Semiconductor Group 6 62 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U The frame number registers stores an 11 bit value which defines the number of an USB frame The frame number rolls over upon reaching its maximum value of 7FFy
190. ternal wake up timing 9 7 P LCC 44 package 10 2 Functionality sisi 24 eke Rec 9 5 P SDIP 52 package 10 3 Termination eds care Met ee T 9 7 Pin definitions and functions 10 4 10 5 Power supply current 11 3 Program read operation 10 8 10 9 PSEN siglal s sb scit rab SOS 4 3 Semiconductor Group 12 4 1997 10 01 SIEMEN cox 3 C540U C541U PSG at sedis need dues 3 7 7 14 SETAD2 ouvir 3 9 POV s cd ruta ba dedu 2 3 3 4 3 7 SE THIS S a aa up woo ts 3 9 III eas ae E 3 7 7 14 SELHUA 2 to Sect ee Red RE Rd 3 9 EE paces e eat diuo ted 3 7 7 14 SETRDH 3 2t aliada eae Oe 6 66 RUDI 4 ouis sues Siete n etes 3 7 7 14 SETIWEHO 18 tdeo e DAS aa 3 8 PUE Lia 3 7 7 14 SEIWR incita veto cae 3 8 o eaoin nr aan granen ea 3 7 7 14 DE IV Res 25 ete e e o ae 3 9 PXT ae R4 RAE SG A Ses 3 7 7 14 SEIWRS ds ER Paha wre ds ped 3 9 R SEI RA toria TERREA EE 3 9 o RR 3 SBEDWBDGoes six te ae nios qat 6 67 Recommended oscillator circuits 11 19 SLS oo eee eee 3 6 6 21 Reset it caves uie Gk oo anes oe at 5 1 to 5 5 SODO cocooccocccrnrn o 3 8 Fast power on reset 5 3 SOU ety eee Ge te 3 8 Hardware reset timing 5 5 SOD2 1 eee ne 3 9 of USB module 5 2 MOD Gas sata LLL E MEE lite ate 3 9 Power on reset timing 5 4 SOLD Sra tree S a eh Open Ears Sacer ay 3 9 Reset circuitries 2 emend eru 5 2 SODIEO 1 ee eee eee eee eee 3 8 RE
191. the P LCC 44 package port 1 is a 6 bit I O port only Port O is an open drain bidirectional I O port while ports 1 to 3 are quasi bidirectional I O ports with internal pullup resistors That means when configured as inputs ports 1 to 3 will be pulled high and will source current when externally pulled low Port O will float when configured as input The output drivers of port 0 and 2 and the input buffers of port O are also used for accessing external memory In this application port O outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents In this function port 0 is not an open drain port but uses a strong internal pullup FET Two port lines of port 1 P1 0 LEDO P1 1 LED1 and one port line of port 3 P3 0 LED2 have the capability of driving external LEDs in the output low state Semiconductor Group 6 1 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 1 1 Port Structures The C540U C541U allows for digital I O on 30 lines P LCC 44 or 32 lines P SDIP 52 grouped into 4 bidirectional 8 6 bit ports Each port bit consists of a latch an output driver and an input buffer Read and write accesses to the I O ports PO through P3 are performed via their corresponding special function registers PO to P3 Figure
192. the oscillator watchdog unit controls the wake up procedure in its start up phase 3 The oscillator watchdog unit starts its operation When the on chip oscillator clock is detected for stable nominal frequency the microcontroller further waits for a delay of typically 5 ms and then starts again with its operation initiating the power down wake up interrupt The interrupt address of the first instruction to be executed after wake up is 007By 4 The clock system of the USB module must be setup again by software USB PLL is switched on by setting bit PCLK in SFR DCR only required in full speed mode Therafter the PLL must be stabilized by waiting typically 3 ms Now bit UCLK in SFR DCR can be set 5 After the RETI instruction of the power down wake up interrupt routine has been executed the instruction which follows the initiating power down mode double instruction sequence will be executed The peripheral units timer 0 1 SSC and WDT are frozen until end of phase 4 All interrupts of the C541U are disabled from phase 2 until the end of phase 4 Other Interrupts can be first handled after the RETI instruction of the wake up interrupt routine Depending on the requirements point 4 can also be executed in pahse 5 after the execution of the RETI instruction described in point 5 above 9 2 2 2 Exit via UBS Bus If the wake up from software power down mode through USB bus capability has been selected any activity on the USB bus causes th
193. tion counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself fosc 6 OSC n q Timer Clock C 2 vu TLO 6 Bits TFO Interrupt C T 1 P3 4 T0 o Control i P3 2 INTO o er THO 6 Bits TF1 Interrupt MCS02729 Figure 6 20 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Semiconductor Group 6 20 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 3 SSC Interface C541U only The C541U microcontroller provides a Synchronous Serial Channel unit the SSC This interface is compatible to the popular SPI serial bus interface It can be used for simple I O expansion via shift registers for connection of a variety of peripheral components such as A D converters EEPROMs etc or for allowing several microcontrollers to be interconnected in a master slave structure It supports full duplex or half duplex operation and can run in a master or a slave mode Figure 6 21 shows the block diagram of the SSC The central element of the SSC is an 8 bit shift register The input
194. ts of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS General Information C541U Table of Contents Page 1 IMTFOdUCUOA Met oa 1 1 1 1 Fiti CONNGUIAION pias id dada ds 1 4 1 2 Pin Definitions and PIrelons ausesxa ld EA A 1 6 2 Fundamental Structure ccesee rr RR RE RR 2 1 2 1 GPL cote ddipteastrte rev oe b eV trs 2 2 2 2 CPU TII eoa oe 5 4 tote oco DER ae e g o re AA FA Ba Ca p oa SD erg 2 4 3 Memory Organization eor te IER RIdex S ia 3 1 3 1 Program Memory Code Space 00 0 eee eee 3 2 3 2 Data Memory Data Space qiie ku als dee beens
195. tted while SRB at SFR address 95H contains the data which was received during the last transfer A write to the STB places the data directly into the shift register for transmission Only in master mode this also will initiate the transmission reception process When a write collision occurs STB will hold the value written erroneously This value can be read by reading from STB A read from the receive buffer register SRB will transfer the data of the last transfer completed This register must be read before the next transmission completes or the data will be lost There is no indication for this overrun condition Semiconductor Group 6 30 1997 10 01 SIEMENS On Chip Peripheral Components C540U C541U Special Function Register STB Address 94 Reset Value XXy Special Function Register SRB Address 95 Reset Value XXy MSB LSB Bit No 7 6 5 4 3 2 1 0 94y Y 6 5 4 3 2 A 0 STB 95H m 6 5 4 3 2 1 0 SRB After reset the contents of the shift register and the receive buffer register are undefined The register SSCMOD is used to enable test modes during factory test It must not be written or modified during normal operation of the C541U Special Function Register SSCMOD Address 96 Reset Value 00y MSB LSB Bit No 7 6 5 4 3 2 1 0 964 LOOPB TRIO 0 0 0 0 0 LSBSM SSCMOD Bit Function LOOPB SSC loopback enable This bit should be used for test purpose
196. ty If PUEI 1 the USB endpoint interrupt has a high priority PSSC SSC interrupt priority level C541U only If PSSC 0 the SSC interrupt has a low priority If PSSC 1 the SSC interrupt has a high priority Semiconductor Group 7 14 1997 10 01 SIEMENS Interrupt System C540U C541U 7 2 Interrupt Priority Level Structure A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence vertical and horizontal as shown in table 7 12 below If e g the external interrupt 0 and the SSC interrupt have the same priority and if they are active simultaneously the external interrupt 0 will be serviced first Table 7 12 Interrupt Source Structure Interrupt Source Priority High Priority Low Priority External Interrupt 0 SSC Interrupt C541U only High Timer O Interrupt USB Endpoint Interrupt External Interrupt 1 USB Device Interrupt Timer 1 Interrupt Low Semiconductor Group 7 15 1997 10 01 IE I
197. ure 11 15 External Clock Drive on XTAL1 Semiconductor Group 11 9 1997 10 01 IE Device Specifications SIEMENS C540U C541U Shown is the data clock relationship for CPOL CPHA 1 The timing diagram is valid for the other cases accordingly In the case of slave mode and CPHA 0 the output delay for the MSB applies to the falling edge of SLS if transmitter is enabled In the case of master mode and CPHA 0 the MSB becomes valid after the data has been written into the shift register i e at least one half SCLK clock cycle before the first clock transition Figure 11 16 SSC Master Mode Timing Semiconductor Group 11 10 1997 10 01 SIEMEN Device Specifications gt C540U C541U tscH fscL SCLK CPOL 1 SCLK CPOL 0 N tsc tt S tp STO CPHA 0 DOUT7 X tp STO CPHA 1 DOUT 7 Figure 11 17 SSC Slave Mode Timing MCT03390 Semiconductor Group 11 11 1997 10 01 SIEMENS Device Specifications C540U C541U 11 4 AC Characteristics of Programming Mode Vec 25V 1096 Vp 2 11 5V 595 T4225 Ct 10 C Parameter Symbol Limit Values Unit min max ALE pulse width paw 35 ns PMSEL setup to ALE rising edge tems 10 Address setup to ALE PROG or PRD falling tpas 10 ns edge Address hold after ALE PROG or PRD tran 10 ns falling edge Address data setup to PROG or PRD pcs 100 ns
198. vaas uero vta verre 3 8 EPBSS eeu gr teeter ket stetur 3 9 DNRIEV insensato 3 8 EPDS ras 3 9 DNRIE2 Ca ecers at onda tata 3 9 EPM Lee ea 3 5 6 66 DINE Sc PN m 3 9 EPA 3 7 6 56 7 13 A iiid eus etus tate egent 3 9 EPIEO ae retocada oy 3 8 AA 6 68 7 7 A ecabncanacaananaise 3 8 DINI dr M 6 70 7 12 EPIE2 aa foca 3 9 DONEC tos s tados 3 8 A tae tB 3 9 A tette Tes 3 8 EPIE4 oana eee 3 9 A e 3 9 A al estu 3 5 6 68 7 7 DIONEBU ie fait oak Dude EA 3 9 EPIRO cuits id 3 8 O 3 9 EPIRI asa ti aida ties 3 8 DONEN TT 6 67 A ume 3 9 A TEMERE 3 4 3 6 EPIRI resi aa hae Me 3 9 DPE cct stia eve eau a 3 4 3 6 EPIRA MEME HET 3 9 DPWDR ssssss 3 5 3 8 6 59 EPIRn 000 ue 3 5 6 70 7 12 E EPEENO acute anita dre lie ay 3 8 eso alpine Cs ee eds ee aah 3 6 7 4 BRE EIN Ge eene EIERRVESSEEYS 3 8 PRE ec oe tebe le LAT 3 7 4 4 EP EN2 cakes da ocd a Belk en 3 9 Emulation concept 065 4 5 EPLENS 6 2 6 eee eee eee 3 9 BODO sk Ce matched Verum bourke 3 8 EPLEN4 0 0 e eee eee 3 9 A eda ee Nt 3 8 EPLENn 0 5 3 5 6 72 ED MMC 3 9 EPS2 0 2 eee eee eee 3 7 6 53 EDS contas Bouse seed 3 9 EPS7 0 ee eee eee eee 3 7 6 53 EOD4 A ae bene eee ree een Sey 3 9 EPSEL 05 3 5 3 7 6 53 BODIED wana n 3 8 SU 3 8 BODIED meto ii ceda 3 8 ESPA oooococcnrnrrr 3 8 A eer 3 9 SICE 3 9 BODIES acne carente dl 3 9 ESP eee eee eee eee ee 3 9 ze cats Wii detesto 3 9 ESPA owe eee eee 3
199. when configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see figure 6 13 is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to the port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port O is configured as general I O port and has to emit logic high level 1 external pullups are required Addr Data Control Int Bus MCS02122 Figure 6 13 Port 0 Circuitry Semiconductor Group 6 6 1997 10 01 IE On Chip Peripheral Components SIEMENS C540U C541U 6 1 1 1 Port 0 and Port 2 used as Address Data Bus As shown in figure 6 13 and below in figure 6 14 the output drivers of ports 0 and 2 can be switched to an internal address or address data bus for use in external memory accesses In this application they cannot be used as general purpose I O even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the P2 SFR remains unchanged while the PO SFR has 1 s written to it Being a
200. with 2 USB interrupts selectable at 2 priority levels Enhanced fail safe mechanisms Programmable watchdog timer only C541U Oscillator watchdog Power saving modes idle mode software power down mode with wake up capability through INTO pin or USB On chip emulation support logic Enhanced Hooks Technology P LCC 44 and P SDIP 52 packages Power supply voltage range 4 0V to 5 5V Temperature Range SAB C540U T 0 to 70 C SAB C541U T 0 to 70 C Semiconductor Group 1 2 1997 10 01 Introduction SIEMENS C540U C541U Port 0 8 Bit Digital O Port 1 P LCC 44 6 Bit Digital O P SDIP 52 8 Bit Digital O Port 2 8 Bit Digital O Port 3 8 Bit Digital O MCL03374 Figure 1 2 Logic Symbol Semiconductor Group 1 3 1997 10 01 Introduction SIEMENS C540U C541U 1 4 Pin Configuration This section describes the pin configrations of the C540U C541U in the P LCC 44 and P SDIP 52 packages P1 2 SCLK Voc Vss RESET P3 0 LED2 P1 3 SRI P3 1 DADD P3 2 INTO P3 3 INT1 P3 4 TO P3 5 T1 AD3 18 19 20 21 22 23 24 25 26 27 P2 2 A10 P2 4 M2 This pin functionality ist not available for the C540U P0 4 AD4 P0 5 ADS P0 6 AD6 P0 7 AD7 EA P1 4 STO ALE _ PSEN P2 7 M5 P2 6 A14 P2 5 M3 MCP03343 Figure 1 3 Pin Configuration P LCC 44 Package top view Semiconductor Group 1 4 1997 10
201. xternal wake up from software power down mode description see chapter 9 When the power down mode is left by a low level at the INTO pin or by the USB the oscillator watchdog unit assures that the microcontroller resumes operation execution of the power down wake up interrupt with the nominal clock rate In the power down mode the RC oscillator and the on chip oscillator are stopped Both oscillators are started again when power down mode is released When the on chip oscillator has a higher frequency than the RC oscillator the microcontroller starts operation after a final delay of typ 1 ms in order to allow the on chip oscillator to stabilize Note The oscillator watchdog unit is always enabled Semiconductor Group 8 5 1997 10 01 IE Fail Safe Mechanisms gt yi ENS C540U C541U 8 2 1 Functionality of the Oscillator Watchdog Unit Figure 8 2 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on chip oscillator EWPD WS Power Down PCON1 7 PCON1 4 Mode Activated Activity on Power Down Mode USB Bus Wake Up Interrupt Control Control P3 2 INTO Logic Logic Internal Reset O Start Stop RC Oscillator RC 3 MHz Frequency Start Comparator Stop On Chip Oscillator WDCON CO y L E d ds Int Clock ea E Rd MCD03385 Figu
202. y Organization C540U C541U Semiconductor Group 3 10 1997 10 01 IE External Bus Interface S MENS C540U C541U 4 External Bus Interface The C540U C541U allows for external memory expansion The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture 4 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 Port 0 and port 2 with exceptions are used to provide data and address signals In this section only the port O and port 2 functions relevant to external memory accesses are described Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri 4 1 1 Role of PO and P2 as Data Address Bus When used for accessing external memory port O provides the data byte time multiplexed with the low byte of the address In this state port 0 is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port O pins ar
203. y a setup and hold time to from the falling edge of PALE PALE must be at low level whenever the logic level of PMSEL1 0 is changed XTAL2 20 23 O XTAL2 Output of the inverting oscillator amplifier Input O Output Semiconductor Group 10 4 1997 10 01 OTP Memory Operation SIEMENS C540U C541U Table 10 2 Pin Definitions and Functions in Programming Mode cont d Symbol Pin Numbers 1 0 Function P LCC 44 P SDIP 52 XTAL1 21 24 XTAL1 Input to the oscillator amplifier AO A8 24 31 28 35 Address lines A7 P2 0 7 are used as multiplexed address input lines A0 A7 and A8 A12 A8 A12 must be latched with PALE Address A12 is requred only for the C541U PSEN 32 38 Program store enable This input must be at static 0 level during the whole programming mode PROG 33 39 Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations During basic programming mode selection a low level must be applied to PROG EA V pp 35 42 External Access Programming voltage This pin must be at 11 5 V Vpp voltage level during programming of an OTP memory byte or lock bit During an OTP memory read operation this pin must be at high level Vi This pin is also used for basic programming mode selection At basic programming mode selection a low level must be applied to EA Vpp D

Infineon C540U-E User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents