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Lattice 7:1 LVDS Video Demo Kit User`s Guide

1. IDDRX2B BN IDDRX2B i y 41 RC out 7 7 IDDRX2B RD in d aN 7 3 RD out 7 129198 1ndino IDDRX2B RCK out reset sync ECLK sysclockPLL RESET CLKOS CLKI x3 5 phase shifted CLKI reset sync generation logic A i CLKOK CLKI x3 5 2 0deg DPHASE LOCK reset sync out The block diagram of the 7 1 LVDS transmitter is shown in Figure 12 Four 7 to 4 serializers are used for serializing the parallel R G B VSYNC HSYNC and DE signals There is another serializer used for generating the LVDS out put clock The 1100011 value is feeding to this serializer so that the generated LVDS clock has a clock data rela tionship that complies to the Channel Link 7 1 LVDS specification The 4 bit outputs of the serializers are sent to the 2x gearing ODDRX2B modules for pumping out of the LVDS I Os For more information about the transmitter please refer to Lattice reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface Lattice Semiconductor Lattice 7 1 LVDS Video Demo Kit Figure 12 Block Diagram of 7 1 LVDS Transmitter Module TA_in 7 4 Serializer 4 TB_in E TC in Bech Y TD_in E
2. Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide Figure 3 Lattice 7 1 Video Demo Kit Contents LatticeECP2 Advanced Evaluation Board Video Demo Board 3 Video Demo Board 2 DES Compact Flash ill o o o oj o s s o Eod cum Video Demo 2 p a E B TI E E d y 83 3 A HERR CC LatticeECP2 50 OO OO ja d x1 x1 DDR2 DIMM 0 DDR2 DIMM 1 la LKO Red Banana Plug Cable x1 Video Demo Board 1 Video Demo Board 4 or the reworked Video Demo Board 1 E E o Be o Si o n o S or ol II DI x1 x1 x2 5V Wall Mount Power Adapter DVI Cable MDR 26 Channel Link Cable Black Banana Plug Cable x1 x1 x2 x2 After you verify you have the proper equipment for the video demo make sure all the jumpers on the boards are set correctly The default jumper settings of Video Demo Boards 2 and 3 are shown below The detailed functions of these jumpers ca
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4. This demo requires two DVI cables The video demo kit contains only one DVI cable Therefore you must use the original DVI cable that comes with the LCD display as well If you are using a VGA to DVI converter to supply the DVI input please be sure to set the converter s input and output switches to RGB then connect the converter s power the VGA and DVI cables Before you connect the two DVI cables to the Video Demo boards 2 and 3 set the screen resolution to any of those listed in the Prepare for the Video Demo section earlier in this document and check if your LCD display can display the image properly at this resolution Note that the DVI interface includes pins to allow the video source getting the EDID Extended Display Identification Data from the video sink These pins are not imple mented on Video Demo boards 2 and 3 Some video source will not send out the video stream if it is not get ting a proper EDID from the video sink To prevent this from happening you should first set the screen resolution and check if the video stream is transmitting properly to the LCD display before disconnecting the DVI cable then reconnecting the cable to the demo system The DVI port of your PC should be connected to the Video Demo board 3 Video Demo board 2 should be con nected to the LCD display e Step 4 Connect the JTAG Download Cable The JTAG download cable is used for downloading the demo bitstream from a PC to the LatticeECP
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6. switch Coi g 8 From Pushbotton Switch Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide In addition to the Rx and Tx modules this design also contains the modules for the RGB gain control the Con trast Brightness Hue Saturation controls the OSD module and the LatticeMico8 microprocessor that automatically demonstrates the adjustments These modules are an example design You may implement other video applica tions in the LatticeECP2 50 FPGA using the video demo kit The Gain Control modules are 9x9 9 bit by 9 bit multipliers implemented using the sysDSP blocks of the LatticeECP2 FPGA The 9 bit gain value defines a positive real number between O and 1 99609375 with 1 bit of integer part and 8 bits of fractional part as shown in Figure 10 Figure 10 18 Bit Data Value MSB LSB Integer Part 9 bits SY ea Cs TS T ETT T MSB LSB Integer Part 10 bits Fractional Part 8 bits eae pa Ea The R G B in this design are colors with 8 bit color depth Each color is represented by 8 binary bits Before feed ing them to the multiplier s multiplicand port they are expanded from 8 bits to 9 bits with the most significant bit set to 0 The R G B gains are real numbers between 0 and 1 and are feeding to the multiplier port After reset these gains are set to their default values 1 0 The real number 1 0 is represented by the 9 bit binary 100000000 The maximum value of the gains
7. Wa J oe 22 10 DDR Registers 2x gearing ODDRX2B sysCLOCK PLL RST_Tx RESET CLKOP CLKI x3 5 Odeg CLK_Tx CLKI CLKOK CLKI x3 5 2 Odeg LOCK Troubleshooting Camera Link video camera is not supported Users Guide TA out TB out TC out TD out TCLK out Please note this kit uses the Channel Link MDR 26 standard not Camera Link These two LVDS video standards use the same MDR 26 connector but have different pinouts and data packet standards and are not compatible Please use a standard DVI source such as a laptop or desktop computer or a Channel Link source to the LVDS No video output when everything is connected There are a number of possible causes some of the most common include Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide 1 Boards 1 and 4 are not installed properly After these boards are installed on the LatticeECP2 Advanced Evaluation Board the metal pieces of the VHDM connectors of Boards 1 and 4 should be touching each other 2 If using a computer for the DVI source it may need to identify the monitor for initialization Refer to the Boards and Cable Connections section of this document Step 3 3 Check switches and jumpers Make sure that DIP switch SW1 switches 1 and 2 on the LatticeECP2 Advanced Evaluation Board are in the up position to correctly set the power supply options There are a number of other jumper and switch setti
8. are limited to 1 0 The product of the 9x9 multiplier is an 18 bit value with 10 integer part bits and 8 fractional part bits However only 8 integer part bits bit 15 down to bit 8 are passed to the OSD module Figure 11 shows the block diagram of the 7 1 LVDS receiver module This is the same receiver module as in the Lattice reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface There is an auto alignment logic in the receiver module that utilizes the deserialized data of RCLK_in to select the proper outputs of the four data pairs This ensures the four data outputs are aligned at the pixel boundary This logic will be reset whenever the PLL lock is lost The DDR software primitives IDDRX2B with x2 gearing ratio are used for receiving the high speed 7 1 LVDS video stream The 4 bit output of the IDDRX2B modules will then be sent to the 4 to 7 deserializers Refer to refer ence design RD1030 for more detailed information This can be found on the Lattice web site at www lattices emi com by searching for RD1030 Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide Figure 11 7 1 Receiver Side Block Diagram IO DDR Registers Auto Alignment 2x gearing Module RA_in x El RB_in gt RC in 1 ii IDDRX2B 4 7 Deserializer 4 7 Deserializer 4 7 Deserializer 4 7 Deserializer 4 7 Deserializer cd d LZ HRA out 7 7 e D gt RB out 7
9. simple converter will not work Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide If your PC does not have a DVI output you may purchase a VGA to DVI converter such as the CP 261D to con vert your PC s video signal from VGA to DVI The PC screen resolution needs to be set to any of the following to run this demo 640x480 75Hz 800x600 60Hz or 75Hz 1024x768 60Hz or 75Hz 1152x864 75Hz 1280x1024 60Hz The Lattice 7 1 Video Demo Kit includes the following items Table 1 Lattice 7 1 Video Demo Kit Contents Item Description Quantity 1 LatticeECP2 672fpBGA Advanced Evaluation board 1 5V wall mount power adapter Video Demo board 1 Video Demo board 4 Video Demo board 2 Video Demo board 3 DVI cable MDR 26 Channel Link cable Black banana plug cable Red banana plug cable 2 1 The Lattice 7 1 Video Demo Kit is available with or without the LatticeECP2 Advanced Evaluation Board and 5V wall mount power adapter 2 Some early versions of this kit may include a modified version of Video Demo Board 1 as a substitute for the Video Demo Board 4 In these cases Video Demo Board 4 can be differentiated by two small wires connected to the MDR I O See the diagram below for an example In this document this board will be referenced only as Video Demo Board 314 as the function of either version is the same o o NI o aj A OJN Kl pf a a al al al a A o
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11. 2 FPGA device Connect it to the J46 on the LatticeECP2 Advanced Evaluation Board The functions of the pins of J46 are shown on the board Be sure the cable wires are connected to the right J46 pins You should also make sure there is a jumper installed on J34 and no jumper installed on J55 so that the LatticeECP2 50 is the only device in the JTAG chain For further information see the LatticeECP2 Advanced Evaluation Board User Manual avail able from the Lattice website at www latticesemi com boards e Step 5 Connect the Power Cables Video Demo boards 2 and 3 require 3 3V power which can be obtained from the LatticeECP2 Advanced Eval uation Board using the red and black banana plug cables Lattice Semiconductor Lattice 7 1 LVDS Video Demo Kit User s Guide Figure 8 Power Cable Connections for Lattice 7 1 LVDS Video Demo Kit After connecting the banana plug cables you should connect the 5V wall mount power adapter to the LatticeECP2 Advanced Evaluation Board After completion of this step the video demo system should look like Figure 8 Step 6 Download the Video Demo Bitstream and Run the Video Demo The DIP switch SW5 on the LatticeECP2 Advanced Evaluation Board controls several functions of this demo design The functions of these controls and their default settings are listed in the flowing table When the specific controls are selected the push button SW4 needs to be toggled to activate the adjustment Note that once t
12. 4 convert the LVDS signals on the MDR 26 Channel Link cable to the VHDM connector so the LVDS signals can be transmitted to the LatticeECP2 50 672 fpBGA device Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide Board 4 is used for the LVDS input on the Rx side and should be installed onto J36 of the LatticeECP2 Advanced Evaluation Board Board 1 is used for the LVDS output on the Tx side and should be installed onto J35 of the LatticeECP2 Advanced Evaluation Board After installation of these two boards the boards should be perpendicular to the LatticeECP2 Advanced Evalua tion Board Figure 6 shows the proper installation of Board 1 Tx side on the left and Board 4 Rx side on the right installed on the LatticeECP2 Advanced Evaluation Board Note in this figure the Board 4 shown is the earlier modified version of Board 1 Figure 6 Proper Installation of Video Demo Boards 1 and 4 to the Lattice ECP2 Advanced Evaluation Board Step 2 Connect the MDR 26 Cables The two MDR 26 Channel Link cables are used for connecting the Rx and the Tx LVDS signals They are used between the following boards Rx Between Video Demo board 3 and 4 Tx Between Video Demo board 2 and 1 Figure 7 shows the connections between these boards Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide Figure 7 Proper Connection of the MDR 26 Channel Link Cables e Step 3 Connect the DVI Cables
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14. Design Modules This video demo design uses the Rx and Tx modules of Lattice reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface For more information on this reference design see the Lattice web site Search for RD1030 or navigate to the web page for the Lattice 7 1 LVDS Video Demo Kit at www latticesemi com boards Figure 9 is a representation of the top level VHDL file of this design The gray color blocks shown below are imple mented in other VHDL files The light green color blocks are modules generated using the IPexpress tool included with the Lattice ispLEVER design software Figure 9 Video Processing Design Example RA_in RB_in RC_in 7 1 LVDS Receiver reset sync RD in LVDS_7_to_1_RX RCLK in T m b ma 3 r Vsync r Hsync r DE sa eg d Delay 3 rgb_Vsync rgb Hsync rgb DE CBHS adj 4 9 A ie E Delay alo ljustments SI o o 8 8 8 3 E L cbhs_R cbhs_G cbhs_B cbhs Vsync a A cbhs Hsync 3 3 cbhs DE o o a 2 o OSD o 5 8 On Screen Display Controlled by Mico8 up E a s 7 Mico8 uP Delay 8 8 8 3 3 e t Vsync D 7 tR tG tB t Hsync SIS t_DE e 3 g E Tx Signal Mapping 2 2 EE sl T 7 7 Ji 2 2 tx_d Tc tx b tx a a ug a JE Adjustment geen TAout 7 1 LVDS Transmitter EM From DIP a EE LVDS 7 to 1 TX baie
15. El attice Lattice 7 1 LVDS Video Demo Kit nama as Semiconductor User s Guide au u n a a Corporation June 2007 Technical Note TN1134 Introduction The Lattice 7 1 LVDS Video Demo Kit is a set of boards intended to bring RGB video data into the LatticeECP2 FPGA where it can be processed and transmitted to an output display It is intended to be used as a reference design and to demonstrate the capabilities of the LatticeECP2 FPGA in video processing applications The complete kit consists of up to five boards The heart of the kit is the LatticeECP2 Advanced Evaluation Board featuring a LatticeECP2 50 FPGA device The kit is optionally available without this board The other four boards feature the required I O interfaces to complete the demonstration These are described in more detail below About This Guide This document includes descriptions of the design of the boards the design of the IP for the LatticeECP2 M FPGA the items required to run the demonstration and how to connect the boards and the cables for the demo Additional Resources Additional resources related to the Lattice 7 1 LVDS Video Demo Kit including updated documentation HDL source and bitstream programming files for the LatticeECP2 FPGA a users guide for the LatticeECP2 Advanced Evaluation Board and other related materials can be downloaded from the Lattice web site at www lattices emi com boards Navigate to the page for the Lattice 7 1 LVDS Video Demo K
16. Pina low TFP401A s Pixel select Selects between one or two pixels per p J7 PIXS clock output modes Pin2 and Pin3 low J8 STAGN Staggered pixel select of TFP401A Pin2 and Pin3 low Output strength select of TFP401A The default setting set the A 2 ST drive strength to low drive strength Pin2 and Pin3 low This is an active low power down control of TP401A During pow p sio CON erdown mode all output buffers are in the high impedance state Pin1 and Pin2 high This is an active low output drive power down control of TP401A J11 PDON During output drive powerdown mode all output drivers except Pin1 and Pin2 high SCDT and CTL1 are driven to a high impedance state 17 Lattice 7 1 LVDS Video Demo Kit User s Guide Lattice Semiconductor Appendix C Schematics of the Video Demo Boards 1 2 3 and 4 Video Demo Board 1 Figure 14 Video Demo Board 1 Schematic x z T v 2 Bquny yusuunoog Wor3exodio io3onpuoopueg Sara 2 000 gt 0 518 op 0057 DCH bk 0S0 L 0001 1 Buiweag Ajqwessy L peog ouieg oapiA Buimeig jeoiueysow L pjeog Owag OSPIA 3A01Z1 92Z01 WE HOW WE Uld 9z siejem Q1 L000 LEOFZ XAN WAHA L sjueuoduio pue urejBeig yoolg L paeog owaq o9piA 18 Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide Figure 12 Video Demo Board 1 Schematic Cont STONE e
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19. he Auto Demo is enabled the OSD will be moving its position and bounce back when it hits the edge of the display This is for demonstration purpose and cannot be turned off Table 3 Switch for Video Color Adjustments Demo and OSD Controls SW5 Pin Number ON Pushed Down OFF Pulled Up Pin 1 R gain or Contrast deselected R gain or Contrast selected Pin 2 G gain or Brightness deselected G gain or Brightness selected Pin 3 B gain or Hue deselected B gain or Hue selected Pin 4 Opacity or Saturation deselected Opacity or Saturation selected Pin 5 OSD enabled OSD disabled Pin 6 Auto Demo enabled Auto Demo disabled Pin 7 Select RGBO group Select CBHS group Pin 8 Decrease the selected controls when SW4 is toggled Increase the selected controls when SW4 is toggled Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide Now you can apply power to the demo system by turning on the SW6 of the LatticeECP2 Advanced Evaluation Board Then launch ispVM to download the demo bitstream For full details on how to download the bitstream to the LatticeECP2 FPGA please refer to the LatticeECP2 Advanced Evaluation Board User Guide The bitstream file for this demo as well as other resources can be downloaded from the Lattice web site at www latticesemi com boards Navigate to the page for the Lattice 7 1 Video Demo Kit and see the documents and downloads link at the left of the page Video Demo
20. ice Semiconductor User s Guide Jumpers J34 and J55 are used for the JTAG chain connection setting Please make sure they are at their default settings J34 short and J55 open which makes the LatticeECP2 50 the only device in the JTAG chain The OSD of this demo is controlled by a LatticeMico8 microprocessor that requires an external clock from the on board oscillator If a full size oscillator is used make sure the oscillator on Y2 is installed on pins 1 7 10 and 16 as seen in Figure 5 If a half size oscillator is used make sure the oscillator on Y2 is installed on pins 1 4 13 and 16 In addition Jumper J18 must be shorted to connect the oscillator clock output to the LatticeECP2 50 device The locations of these jumpers are shown below Figure 5 Jumper Settings on the LatticeECP2 Advanced Evaluation Board 2 5V J55 Open PO i D J34 Short s J18 Short OSC installed on 3 3V Y2 pin 1 7 10 16 If you are using the optional CP 261D VGA to DVI converter to convert your PC s video signal from VGA to DVI set both the input switches and the output switches to RGB Boards and Cables Connections Once you have everything needed for the demo and all the board settings are correct you may start connecting the boards and cables step by step If this is your first time to run this demo it s highly recommended to follow the steps below Step 1 Install Board 1 and Board 4 Boards 1 and
21. it and see the documents and downloads link on the left side of the page 7 1 Video Demonstration Setup and Design Figure 1 is an overview of the connection between the boards the required cables and a block diagram of the demo design implemented in LatticeECP2 50 The video signals are color coded to indicate the different I O stan dards including TMDS pink LVCMOS LVTTL orange and LVDS yellow Figure 1 Block Diagram of the Lattice 7 1 LVDS Video Demo Kit Setup Board 3 60 pin connection TMDS Receiver TI TFP401A Board 1 or 4 LatticeECP2 Advanced Evaluation Board LatticeECP2 50 Device LVDS 7 1 Rx Deserializer Ir R NI B hr Gain Gain Gain Control Control Control R G B di HO WE uld 9z O TMDS signals a LVCMOS LVTTL signals O LVDS signals V H D M GLWZ8cHo06sa HAW We utd 9z SD TI e sjuawysnipy O8plA SYDIIMS pieog uo MDR 26 Channel Link Cable RGB to YCbCr Converter bo Desktop PC MDR 26 Channel Link Cable Contrast Brightness Hue Saturation Adjustments DVD Player ATSC Tuner H DVD YCbCr to RGB Converter d EH 4 OSD LVDS 7 1 Tx Serializer s DVI Cable LCD Display DVI Cable Board 1 Board 2 TMDS Driver TI TFP410 60 pin connection 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal A
22. ll other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice www latticesemi com 1 in1134_01 2 6 pin 3M MDR GW We uld 9z GlWveszuooesa H V H D M EF Lattice 7 1 LVDS Video Demo Kit Lattice Semiconductor User s Guide In this setup DVI I video signals must first be generated by a PC or an equivalent source On Video Demo board 3 the TMDS signals of the DVI I interface are first converted to LVCMOS LVTTL using the TFP401A then con verted again to LVDS using the DS90CR287MTD These LVDS signals are then fed to the LatticeECP2 50 through the MDR Channel Link cable and Video Demo Board 4 Video Demo Board 4 is connected to the LatticeECP2 Advanced Evaluation Board with a VHDM connector The demo design is implemented in the LatticeECP2 50 FPGA This design is described in further detail later in this guide and is based on Lattice reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface Source code for this design is available in both the VHDL and Verilog languages The LVDS video signal is de serialized by the LatticeECP2 50 for extracting the 8 bit R 8 bit G and 8 bit B pixel datum Then the 8 bit R G B pixel datum are adjusted by their own gain control block and then the Contrast Brightness Hue Saturation adjustment block before adding the OSD On Screen Display After the OSD is added to
23. n be found in Appendix A and Appendix B at the end of this user s guide Video Demo Board 2 Default Jumper Settings Install jumpers on pin1 pin2 of J3 J7 J8 J9 J11 J13 and J21 Install jumpers on pin2 pin3 of J10 and J12 Install jumpers on pin1 pin3 of J4 and J6 Install jumper on pin4 pin6 of J5 Lattice Semiconductor Video Demo Board 3 Default Jumper Settings Lattice 7 1 LVDS Video Demo Kit Install jumpers on pin1 pin2 of J4 J5 J10 and J11 Install jumpers on pin2 pin3 of J6 J7 J8 and J9 Install jumper on pin3 pin4 of J3 Figure 4 Block Diagram and Default Jumper Settings of Video Demo Boards 2 and 3 Board 2 3M 10226 1210VE O O Y An Co pe em din Q O g lt o D x Board 3 User s Guide v00L 0c v4 Solo IAC For the I O bank voltage setting on the LatticeECP2 Advanced Evaluation Board bank 2 and bank 3 must be to be set to 2 5V Bank 0 1 4 7 should all be set to 3 3V The following table shows the proper jumper settings for the Lattice 7 1 Video Demo Table 2 Jumper Settings for the LatticeECP2 Advanced Board syslO Bank Jumper Jumper on Pins 0 J14 l 488 1 3 gt VCC_3 3V 2 5V ADJ 2 J40 2 4 gt VCC_2 5V Pn2 e e B rns 3 J41 3 5 gt VCC_1 8V in NE 4 328 4 6 gt VCC_ADJ 23V 18V 7 J27 5 NA Tied to 1 8V 6 Cannot be changed Lattice 7 1 LVDS Video Demo Kit Latt
24. n the Rx side Note that the reworked Video Demo Board 1 is not equivalent to Video Demo Board 4 Please modify the Ipf preference file of reference design RD1030 LatticeECP2 M 7 1 LVDS Video Interface to match the board that you are using on the Rx side The Tx side can use either the reworked Board 1 non reworked Board 1 or Board 4 1 Solder a short wire from J2 pin 6 to J2 pin 20 2 Use another short wire with the same length to connect J2 pin 7 to J2 pin 21 26
25. nd Cable Connections section of this document step 3 Figure 13 shows this arrangement Figure 13 Setup to Test Boards 2 and 3 LCD Display oueg vam Aa E wm i 88888383P dl Desktop PC Note Power connections are not shown in Figure 13 but power must be applied 14 Lattice Semiconductor Ordering Information Lattice 7 1 LVDS Video Demo Kit User s Guide Description Ordering Part Number China RoHS Environment Friendly Use Period EFUP LatticeECP2 7 1 Video Development Kit Includes LatticeECP2 Advanced Evaluation Board LFE2 50E VID EV Lattice 7 1 Video Interface Kit HW VID KIT O Technical Support Assistance Hotline 1 800 LATTICE North America 1 503 268 8001 Outside North America e mail techsupport latticesemi com Internet www latticesemi com Revision History Date Version Change Summary December 2006 01 0 Initial release March 2007 01 1 Added Ordering Information section June 2007 01 2 Updated to match RD1030 version 01 2 2007 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their
26. ngs which may affect the operation of the demo Be sure to check the jumpers and switches on all the video demo boards as well as the LatticeECP2 Advanced Evaluation Board 4 The red LEDs on Boards 2 and 3 are not turned on These LEDs indicate the 3 3V powers on these boards are properly supplied All of the different power supplies on the LatticeECP2 Advanced Evaluation Board are controlled by the Lattice Power Manager II POWR1220AT8 If SW1 Pin 1 is on pushed down the POWR1220AT8 device will be reset and all powers including the 3 3V will be disabled 5 The monitor being used is a VGA monitor with a DVI gt VGA adapter The monitor must be a DVI digital monitor There is no analog component output from the Video Demo See the Preparing for the Video Demo section of this document for more information 6 Make sure your monitor source is set to the supported resolutions and refresh rates listed in the Prepare for the Video Demo section earlier in this document Testing for Board 2 and Board 3 If you suspect that something may be wrong with Board 2 or 3 you may wish to test them independently as part of the troubleshooting To do this disconnect Board 2 from the LatticeECP2 Advanced Evaluation Board and con nect its LVDS cable directly into the input of Board 3 This removes the FPGA from the circuit The video path then goes though the DVI LVDS DVI conversion and should be displayed If it is not refer to the Boards a
27. ock input of TP410 Pin1 and Pin2 high J12 DSEL SDA DSEL or FC bidirectional data line of TP410 Pin2 and Pin3 low This is an active low power down control of TP410 During power J13 PDN down mode only the digital I O buffers and FC interface remain Pin1 and Pin2 high active The power of the DS90CR288A is supported through this jumper s default setting This jumper is used for disconnecting the J21 NS VDD DS90CR288A power and forcing its output to the high impedance Pini and Pin2 16 Lattice Semiconductor Lattice 7 1 LVDS Video Demo Kit User s Guide Appendix B Jumpers of the Video Demo Board 3 Table 5 Functions of the Jumpers on Video Demo Board 3 Jumper Function Description Default Setting This jumper selects which multifunctional pins of the TFP401A J3 TxIN7 CTL3 CTL2 or CTL1 is connected to the DS90CR287 s TxIN7 Pin3 and Pin4 input CTL2 is selected by default This is an active low control for forcing the DS90CR287 into the J4 POWERDOWN powerdown mode The DS90CR287 s LVDS outputs stay in the Pin1 and Pin2 high tri state mode under powerdown mode TFP401A s ODCK Polarity Selects ODCK edge on which pixel J5 OCK_INV data QE 23 0 and QO 23 0 and control signals HSYNC Pin1 and Pin2 high VSYNC DE CTL1 3 are latched TFP401A s Output clock data format Controls the output clock 5 A ER DFO ODCK format for either TFT or DSTN panel support Pin2 and
28. oup Aer PP S6eysed 4OSSL peer 95 GLINZ8ZHD06SC sipubis SOA yO sued c O JAOIZL 9ZZOL WE HOW WE Uld 9z siajem 0L LOOO LEOPL XAW WAHA sjeubis SQL jo szed y g sjuauodwo9 pue weibeig 490 98 ft peog owaq OSPIA Buimeig Ajquiessy EN pueog ow q OSPIA 22 User s Guide 1 LVDS Video Demo Ki Lattice 7 Y I z v 2 P guy wwa e UOFIPIOAIOD io3onpuoorpueg eor33 T pr ST YT S Dr r or T T aH m 23 T 090 090 090 EZ eo 9 mos amo mio 1 aer XV VE pi usawa wakaamini ES wa D T E T 5 Tum au 3 R J iode diis THEN K 2222222222 9999999999 99999999
29. respective holders The specifications and information herein are subject to change without notice Lattice Semiconductor Lattice 7 1 LVDS Video Demo Kit Appendix A Jumpers of the Video Demo Board 2 Table 4 Functions of the Jumpers on Video Demo Board 2 User s Guide state Note that the powerdown mode puts the DS90CR288A out puts into low state instead of high impedance state Jumper Function Description Default Setting This is an active low control for forcing the DS90CR288A into the J3 POWERDOWN powerdown mode The DS90CR288A outputs stay low under the Pin1 and Pin2 high powerdown mode J4 CTL3 Multifunctional CTL3 input of TFP410 Pini and Pin3 J5 CTL2 Multifunctional CTL2 input of TFP410 Pin4 and Pin6 J6 CTL1 Multifunctional CTL1 input of TFP410 Pini and Pin3 This is the input reference voltage used to select the swing range of J7 VREF the TFP410 digital inputs High swing 3 3V input signal level is Pin1 and Pin2 high selected by the default setting J8 EDGE Edge select or hot plug input of TFP410 Pini and Pin2 high J9 DKEN Data de skew enable control of TFP410 Pin1 and Pin2 high This is an active high DC select signal of TFP410 used for enabling the TFP410 s PC interface The IPC state machine can be reset by a J10 SELASIN bringing this signal low then back high FC is disable by the default ine and ns low setting J11 BSEL SCL Input bus select or lC cl
30. sz Lei N SOA Xo R amari ToT E roo 8 elo om SS anga FE og San 192500650 soar feo Gea pag XE 100 anga _ A gana SIET SONL ao 7 SEU y e EE Ee g aana 13 y Kaz re 3A0VZV 9ZZ0V XL We and H PPus s omed saw SE em Le d we ka js SIS HH or tomeg 3r nod BE E TH vard sani Samara L e son us Sugar ER bs SE ashy Ee 34 bal vs PB Tews GE 0 e sx Fy ET o E Det Y Bnid y ge aon ES i mos Ha at spr sa enia on ESCH T ge neos sel sorna Fe wou aw ans Lgs ze mim prn anasa el SRG bye rr kemea sani EES EE med sant NOSON anv h h pes ime samu SORT EN ww ASAT ao OPE NOD SOL Lc eg d ye sunt 1 SE ined sont neet mae Lys PA E dELNOKL NOXH by ji d tino xr T SES Te N oviva SONT I T no Xr alin ner ur d Ovivd San T d m Nov ouks earen Bous s SEL Ted anon Zi WS i ane o 8 ld zen Hex __ el aunou leen H Pda nino wr o HHP ver SORT I ONL YE 1 NET Pu ar d WIVO SONL T pe riri suono a gunos Fo ZH ea sant Weides TE H4 vanos ow Ll H t raa ga EE s iov E 3 q rms weg sau aan E h sited lt lt LJ pce a NOY by wed SONL E up u NOM pre GEET X T H or EVO SONT X ee SIT ed S CNL peqes6e3ur rad in T T z T T T 7 T z Figure 14 Video Demo Board 3 Schematic Cont Lattice Semiconductor Lattice 7 1 LVDS Video Demo Kit User s Guide Lattice Semiconductor Video Demo Board 4 Figure 17 Video Demo Board 4 Schematic x z
31. the video stream the final R G B datum are serialized and transmitted via the LatticeECP2 50 LVDS I Os The remainder of the setup is similar to the video input side but reversed The LVDS signals are fed via a VHDM connector to the Video Demo board 1 then to the Video Demo board 2 via the MDR cable The LVDS signals are then converted to LVCMOS LVTTL using the DS90CR288A on the Video Demo board 2 Finally the LVC MOS LVTTL video signals are converted to the DVI TMDS signals using the TFP410 and sent to the LCD display Figure 2 shows a complete Video Demo system setup with an input source laptop and monitor In this example power is supplied to Video Demo Boards 2 and 3 from an external source not shown Figure 2 Video Demo System Setup Prepare for the Video Demo Before running the demo you need the following video source and video sink Video source a desktop or a laptop PC with a DVI output port Video sink a LCD display with a DVI input port and a DVI cable Note The display must be an actual DVI digital display Some DVI sources also include an RGB analog compo nent which allow the use a simple VGA gt DVI converter to supply input to an analog VGA monitor These con verters simply adapt the physical plugs to supply the RGB component signals contained in the DVI cable to a VGA style plug However this video demo kit does not re transmit any analog component signals the output is purely digital As such a

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