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M16C Assembler Manual

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1. 000016 004016 000116 004116 000216 004216 000316 004316 000416 Processor mode register 0 PMO E 000516 Processor mode register 1 PM1 EE 000616 System clock control register 0 CM0 004615 000718 System clock control register 1 CM1 Te 000816 Chip select control register CSR come 000918 Address match interrupt enable register AIER 004916 000A16 Protect register PRCR Te 000B16 004816 DMAO interrupt control register DMOIC 000C16 004C16 DMA interrupt control register DM1IC 000D16 004D16 Key input interrupt control register KUPIC 000E16 Watchdog timer start register WDTS 004E16 A D conversion interrupt control register ADIC 000F16 Watchdog timer control register WDC oom 001016 005016 00116 Address match interrupt register 0 RMADO 005116 YARTO transmit interrupt control register SOTIC 001216 005216 UARTO receive interrupt control register SORIC 001316 005316 UART1 transmit interrupt control register S1TIC 001416 005416 UART1 receive interrupt control register S1RIC 001516 Address match interrupt register 1 RMAD1 005516 Timer AO interrupt control register TAOIC 001616 005616 Timer A1 interrupt control register TA1IC 001716 005716 Timer A2 interrupt control register TA2I
2. 03A316 03E316 Port P1 direction register PD1 03A416 YARTO transmit receive control register 0 UOCO Wie Port P2 P2 03516 UARTO transmit receive control register 1 U0C1 93E516 Port P3 P3 03A616 a 03E616 Port P2 direction register PD2 SCH UARTO receive buffer register UORB 03E716 Port P3 direction register PD3 03A816 UART1 transmit receive mode register U1MR 03E816 Port P4 P4 034916 UART1 bit rate generator U1BRG 03E916 Port P5 P5 03AA16 P 8 03EA16 Port P4 direction register PD4 Se UART1 transmit buffer register U1TB 03EB16 Port P5 direction register PD5 03AC16 UART1 transmit receive control register 0 U1CO 03EC16 Port P6 P6 03AD16 UART1 transmit receive control register 1 U1C1 03ED16 Port P7 P7 03AE16 i A 03EE16 Port P6 direction register PD6 oaapue UART1 receive buffer register U1RB 03EF16 Port P7 direction ES o 03B016 UART transmit receive control register 2 UCON 03F016 Port P8 P8 03B116 03F116 Port P9 P9 03B216 03F216 Port P8 direction register PD8 03B316 03F316 Port P9 direction register PD9 03B416 03F416 Port P10 P10 03B516 O3F516 03B6i6 03F616 Port P10 direction register PD10 03B716 03F716 03B816 DMAO cause select register DMOSL 03F816 03B916 03F916 03BA16 DMA1 cause select register DM1SL O3FAt6 03BB16 03FB16 03BC16 8 03FC16
3. J 2 3 4 Figure 2 6 3 Typical operations of string instructions 66 2 2 6 3 Arithmetic Instructions CPU Programming Model 2 6 Instruction Set There are 31 arithmetic instructions available This section explains the characteristic arithmetic instructions of the M16C 60 series Multiply Instruction There are two multiply instructions signed and unsigned multiply instructions These two instructions allow the user to specify the desired size When B is specified calculation is performed in 8 bits x 8 bits 16 bits when W is specified calculation is performed in 16 bits x 16 bits 32 bits If B is specified address registers cannot be used in both src and dest Note also that the flag does not change in the multiply instruction Figure 2 6 4 shows an example of how the multiply instruction works Table 2 6 4 Multiply Instruction Mnemonic Description Format src dest src dest Explanation Signed multiply instruction dest lt src X dest src dest src dest 63 x 20 1260 SF x 8 bits 1000 x 365 365000 03 E8 4 x 16 bits 8 bit mim 16 bits Figure 2 6 4 Typical operations of multiply instructions 67 Unsigned multiply instruction dest src X dest 16 bits 32 bits CPU Programming Model 2 6 Instruction Set Divide Instruction There are thr
4. Decrements DIV size src RO quotient R2 remainder R2R0 src Divides with sign DIVU size src RO quotient R2 remainder lt R2R0 src Divides without sign DIVX size src RO quotient R2 remainder R2R0 src Divides with sign DSBB size src dest dest dest src C flag Subtracts decimal with borrow DSUB size src dest dest lt dest src Subtracts decimal without borrow EXTS size dest dest EXT dest Extends sign in dest INC size dest dest lt dest 1 Increments MUL size src dest dest lt dest src 52 Multiplies with sign CPU Programming Model 2 6 Instruction Set Addressing Flag change General instruction Special instruction Immediate register direct register indirect register relative register direct Register direct 20 bit Control 32 bit 32 bit OJO Ol Of o ojo ojoj jo ojo O OJO O Oo O oa o o o o o o o oi oi ol oo g srcis selected from ROH and R1 dest is selected from ROL and RO h Selected from ROL ROH AO and A1 i dsp 8 SB or dsp 8 FB is selected Selected from ROL RO and R1L 53 CPU Programming Model 2 6 Instruction Set Mnemonic Write W or B for size MULU size _ src d
5. Example of source program Dummy argument p1 p2 p3 MACPARA 3 JS p1 byte MOV B Macro definition part ELSE MOV W ENDIF MACPARA 2 AIF p1 byte MOV B ELSE MOV W ENDIF MOV W SECTION program j Actual argument word 10 r0 Macro call After expansion SECTION program Macro expansion part 10 RO Figure 3 2 5 Example of macro definition and macro call 116 Functions of Assembler 3 2 Method for Writing Source Program Macro Definition To define a macro use macro directive command MACRO and define a set of instructions consisting of more than one line in one macro name Use ENDM to indicate the end of definition The lines enclosed between MACRO and ENDM are called the macro body All instructions that can be written in the source program but a bit symbol can be used in the macro body Macros can be nested in up to 65 535 levels including macro definitions and macro calls Macro names and macro arguments are case sensitive so they are discriminated between uppercase and lowercase letters Macro Local Macro local labels declared with directive command LOCAL can be used in only the macro definition Labels declared to be macro local are such that the same label can be written anywhere outside the macro Figure 3 2 6 shows a description example In this example m1 is the macro local label name MACRO source dest top LOCLA m1 m
6. 3 Frame base register FB This register consists of 16 bits and is used in FB relative addressing 4 Static base register SB This register consists of 16 bits and is used in SB relative addressing Control registers 5 Program counter PC This counter consists of 20 bits indicating the address of an instruction to be executed 6 Interrupt table register INTB This register consists of 20 bits indicating the start address of an interrupt vector table 7 Stack pointers USP ISP There are two stack pointers a user stack pointer USP and an interrupt stack pointer ISP Both of these pointers consist of 16 bits The stack pointers used USP or ISP are switched over by a stack pointer select flag U flag The U flag is assigned to bit 7 of the flag register FLG 8 Flag register FLG This register consists of 11 bits each of which is used as a flag CPU Programming Model 2 2 Register Set Register bank 0 Data registers Register bank 1 lt 8 bits gt lt 8 bits gt RO ROH lt 20 bits gt d lt 4 bits gt 16 bits gt INTB INTBH INTBL Interrupt table register Address registers lt 16 bits gt User stack pointer PEETER usel i O p AO O ISP O OOOO O O Interrupt stack pointer SB O O Static base register Frame base register FLG SS Flag Me 16bits gt eC Figure 2 2 1 Register structure CPU Programming Model 2 2
7. Branch instructions 10 instructions Bit manipulate instructions 14 instructions String instructions 3 instructions Other instructions 19 instructions 8 bit variable length 91 instructions e Transfer instructions e Push pop instructions e Extended data area transfer instructions e 4 bit transfer instructions e Exchange between register and register memory instruction e Conditional transfer instructions e Add instructions e Subtract instructions e Multiply instructions e Divide instructions e Decimal add instructions e Decimal subtract instructions e Increment decrement instructions e Sum of products instruction e Compare instruction e Others absolute value 2 s complement sign extension e Logic instructions e Test instruction e Shift rotate instructions e Unconditional branch instruction e Conditional branch instruction e Indirect jump instruction e Special page branch instruction e Subroutine call instruction e Indirect subroutine call instruction Special page subroutine call instruction e Subroutine return instruction e Add subtract and conditional branch instructions e Control register manipulate instructions e Flag register manipulate instructions e OS support instructions e High level language support instructions e Debugger support instruction e Interrupt related instructions e External interrupt wait instruction e No operation instruction MOV MOVA PUSH
8. CPU Programming Model 2 5 Addressing Modes NO 2 5 Addressing Modes This section explains the M16C 60 M16C 20 series addressing 2 5 1 Types of Addressing Modes The three types of addressing modes shown below are available 1 General instruction addressing An area from address 00000H to OFFFFH is accessed 2 Special instruction addressing The entire address area from 00000H to FFFFFH is accessed 3 Bit instruction addressing An area from address 00000H to OFFFFH is accessed in units of bits This addressing mode is used in bit instructions List of Addressing Modes All addressing modes are summarized in Table 2 5 1 below Table 2 5 1 Addressing Modes of M16C 60 M16C 20 Series Item Content Addressing mode General instruction Special instruction Bit instruction Immediate O imm 8 16 bits Register direct O Data and address O R2RO0 or R3R1 or A1A0 registers only SHL SHA JMPI and JSRI instructions only Absolute O abs 16 bits 0 to FFFFH O abs 20 bits 0 to FFFFFH LDE STE JMP and JSR instructions only Address register O A0 or A1 without dsp O A1A0 without dsp A0 or A1 without dsp indirect LDE and STE instructions only 0 to 1FFFH Address register O A0 or A1 dsp 8 16 bits O A0 dsp 20 bits only relative LDE STE JMPI and JSRI instructions only SB relative and O SB dsp 8 16bit SB dsp 8 11 16 bits l FB relative 0 to 255
9. BLKB LEN f2 Macro ENDM definition bufset 1 Printout_data bufset 2 Sample Macro call Macro expansion butter butter Figure 3 2 8 Example of LEN statement Example of INSTR Statement In the example of Figure 3 2 9 the position 7 of character string se from the beginning x top of a specified character string japanese is extracted Example of macro description top EQU 1 point_set MACRO source dest top Macro point EQU INSTR source dest top definition ENDM point_set Japanese sel Macro call Macro expansion point Figure 3 2 9 Example of INSTR statement 122 Functions of Assembler 3 3 2 Method for Writing Source Program Example of SUBSTR Statement In the example of Figure 3 2 10 the length of a character string given as the macro s actual argument is given to the operand of MREPEAT Each time the BYTE line is executed MACREP is incremented from 1 to 2 3 4 and so on Consequently characters are passed one character at a time from the character string given as the actual macro argument to the operand of BYTE sequentially beginning with the first character Example of macro description MACRO data MREPEAT LEN data Macro BYTE SUBSTR data MACREP 1 definition ENDR ENDM Macro call Macro expansion Figure 3 2 10 Example of SUBSTR statement 123 Functions of Assembler 3 3 2 Method for Writing Source Program 3 2 5 Structured Descri
10. ORG ROM_TOP SB SB_BASE Declares SB register value to the assembler ER ER BASE Declares FB register value to the assembler START LDC RAM_END 1 ISP Sets initial value in stack pointer LDC SB_BASE SB Sets initial value in SB register LDC FB_BASE FB Sets initial value in FB register MOV B 03H PRCR Removes protect MOV W 0087H PMO Sets processor mode registers 0 and 1 MOV W 2008H CMO Sets system clock control registers 0 and 1 MOV B 0 PRCR Protects all registers 147 LDC LDINTB MOV W MOV W MOV W MOV W SSTR W JSR MAIN_10 MOV W DIV B INTO MOV B MOV W MOV W MOV W MOV W MOV W RMPA W INTO MOV W MOV W INIT_END RTS Programming Style 4 3 Setting Interrupts 0 FLG Sets initial value in flag register VECT_TOP Sets initial value in interrupt table register 0FFFOH PUR1 Connects internal pull up resistors 0 RO Clears WORK_RAM to 02 RAM_END 1 RAM_TOP 2 R3 WORKRAM_TOP A1 INIT Sets initial value in work RAM WORK_1 RO 4 Signed division If operation results in overflow O flag 1 executes INTO instruction and an interrupt is generated ROL WORK_2 0 RO 0 R2 1234H A0 5678H A1 0FFH R3 Sum of products calculation If operation results in overflow O flag 1 executes INTO instruction and an interrupt is generated R2 ANS_H RO ANS_L MAIN_10 OFFFFH WORK_1 0FFH WORK_2 0 ANS_L 0 ANS_H 148 Programming Style 4 3 S
11. src Z flag src C flag src Tests bit BTSTC dest Z flag dest C flag lt dest dest 0 Tests and clears bit BTSTS dest Z flag lt dest C flag dest dest lt 1 Tests and sets bit BXOR src C flag src C flag 50 Exclusive ORs bits CPU Programming Model 2 2 6 Instruction Set Addressing Flag change Bit instruction Flag direct Register direct Register indirect O O Absolute Ojo O O 0 0 0 0 0 0 0 0 0 OI O OJ OO O OF CO OF OO O O OJ OO O OJ O OJ OO OO 0 0 0 0 0 0 0 0 0 0 f Flag changes when C flag is specified for dest 51 Arithmetic Mnemonic Write W or B for size ABS size dest Explanation dest lt dest CPU Programming Model 2 6 Instruction Set Absolute value of dest ADC size src dest dest lt src dest C flag Adds hexadecimal with carry ADCF size dest dest lt dest C flag Adds carry flag ADD size src dest dest lt src dest Adds hexadecimal without carry CMP size src dest dest src Compares result determined by flag DADC size src dest dest lt src dest C flag Adds decimal with carry DADD size src dest dest lt src dest Adds decimal without carry DEC size dest dest dest 1
12. 8 LOCAL EQU BIT SYMBOL INFORMATION HBA BREE HEH AEE EEE AEE smp smp r30 sym4 1 0000000 Figure 4 7 4 Example of map file 183 Link information Section information ATR TYPE START LENGTH ALIGN MODULENAME smp smp Global label information This information is output only when command option MS is specified Global symbol information This information is output only when command option MS is specified Global bit symbol information This information is output only when command option MS is specified Local label information This information is output only when command option MS is specified Local symbol information This information is output only when command option MS is specified Local bit symbol information This information is output only when command option MS is specified Programming Style 4 4 7 Generating Object Files 4 7 3 Generating Machine Language File The following explains the files generated by the load module converter Imc30 and how to start up the converter Files Generated by Imc30 1 Motorola S format file MOT Generated normally This is a machine language file normally generated by the converter 2 Intel HEX format file HEX Generated when option H is specified This is a machine language file generated by the converter when an option H is specified
13. Attr Size Name DATA 0000006 00006H WORK DATA 0000256 00100H STACK CODE 0000083 00053H PROGRAM ROMDATA 0000004 00004H VECT S Outputs section type section size and section name Figure 4 7 1 Example of assembler list file 178 Programming Style 4 7 Generating Object Files Assemble Error Tag File Figure 4 7 2 shows an example of an assembler error tag file Assemble source file name Error message Error line number sample err 21 Error asp30 Operand value is not defined sample err 72 Error asp30 Undefined symbol exist work2 Figure 4 7 2 Example of assembler error tag file 179 Programming Style 4 4 7 Generating Object Files 4 7 2 Linking The following explains the files generated by the linkage editor In30 and how to start up the linkage editor Files Generated by In30 1 Absolute module file X30 Generated as necessary This file is based on IEEE 695 It consists of the relocatable module files output by as30 that have been edited into a single file Map file MAP Generated when option M or MS is specified This file contains link information section s last located address information and symbol information Symbol information is output to this map file only when an option MS is specified Link error tag file TAG Generated when option T is specified This file contains error messages for errors that
14. Default is current directory Processes structured description instruction Outputs local symbol information to relocatable module file DM System label information also is output Generates tag file Displays version of assembler system each program X command name Generates error tag file and invokes command 176 Programming Style 4 7 Generating Object Files Example for Using as30 Commands Seperate each option with a space Example gt as30 L O work SAMPLE This command generates SAMPLE LST and SAMPLE R30 from SAMPLE A30 and outputs them to the work directory Command options can be written in uppercase or lowercase as desired gt as30 sm SEET This command outputs the system label and local symbol information of SAMPLE A30 to the relocatable module file SAMPLE R30 if extension is omitted A30 is assumed Assembler List File Figure 4 7 1 shows an example of the assembler list file Line number of list Location address Object code Assemble processing information of as30 Assembly source line M16C FAMILY ASSEMBLER URCE IST a 6 15 17 37 1996 PAGE 001 SEQ LOC OBJ OXMDA SOURCE STATEMENT soa rert ense Buraco eren O rasa rena 1 EILE COMM ENT E AEE EEEE EEEE EEEE EEEE EEEE 2 SAMPLE PROGRAM 3 INCLUDE m30600 inc 4 1 LIST OFF 5 1 LIST ON 6 1 Indicates the nested level of include
15. Figure 2 6 13 Typical operation of conditional bit transfer instruction 76 CPU Programming Model 2 2 6 Instruction Set 2 6 6 Branch Instructions There are ten branch instructions available with the M16C 60 series This section explains some characteristic branch instructions among these Unconditional Branch Instruction This instruction causes control to jump to label unconditionally The jump distance specifier normally is omitted When this specifier is omitted the assembler optimizes the jump distance when assembling the program Figure 2 6 14 shows an example of how the unconditional branch instruction works Table 2 6 14 Unconditional Branch Instruction JMP LABELI LABEL1 e JMP LABELI The asterisk denotes the start address of the JMP instruction s operand JMP LABEL1 LABEL1 JMP LABEL1 The asterisk denotes the start address of the JMP instruction s operand Figure 2 6 14 Typical operation of unconditional branch instruction 77 CPU Programming Model 2 6 Instruction Set Indirect Branch Instruction This instruction causes control to jump indirectly to the address indicated by src If W is specified for the jump distance specifier control jumps to the start address of the JMPI instruction plus src added including the sign In this case if src is memory the instruction requires 2 bytes of memory capacity If A is specified for the jump distance specifier
16. Maskable interrupts are enabled and disabled by an interrupt enable flag I flag an interrupt priority level select bit and the processor interrupt priority level IPL Software interrupts generate an interrupt request by executing a software interrupt instruction There are four types of software interrupts an INT instruction interrupt a BRK instruction interrupt an overflow interrupt and an undefined instruction interrupt Hardware interrupt Software interrupts DMAO BRK instruction Key input Peripheral Block transfer VO a DMA1 INT instruction A D conversion Overflow INTO instruction 8 Undefined instruction Serial UO UART1 transmit UND instruction UART1 receive UARTO transmit UARTO receive I Timer Ad to AO Timer B2 to BO External pin INT2 to INTO Special Reset NMI DBC Watchdog timer Single step Address match interrupt 1 Address match i Address match interrupt 0 Figure 2 7 1 Interrupt sources in M16C 60 group Note Peripheral functions vary with each type of microcomputer used For details about peripheral interrupts refer to the data sheet and user s manual of your microcomputer 86 CPU Programming Model 2 2 7 Outline of Interrupt 2 7 2 Interrupt Sequence The following explains the interrupt sequence performed in the M16C 60 group Interrupt Sequence When an interrupt request occurs during instruction execution interrupt priorities are resolved after completing the instr
17. Method for Starting Up Imc30 gt Imc30 option absolute module file name Table 4 7 3 Command Options of Imc30 Command Option Inhibits all messages but error messages from being output to the file E start address Sets program s start address and generates machine language file in Motorola S format This option cannot be specified simultaneously with option H Generates machine language file in extended Intel HEX format This option cannot be specified simultaneously with option E Sets data length that can be handled in S2 records to 32 bytes Sets Intel HEX format s data length to 32 bytes Specifies file name of machine language file generated by Imc30 This file is generated in current directory Always be sure to insert space between option and machine language file name Extension of machine language file can be omitted Motorola S format mot Intel HEX format hex Displays version of Imc30 on screen Converter is terminated without performing anything else Example for Using Imc30 Commands Options are not discriminated between uppercase and lowercase Example gt Ilmc30 E 0f0000 DEBUG ee Write the option before specifying the absolute module file This command generates a machine language file DEBUG MOT from the absolute module file DEBUG X30 using Of0000 as the start address eA Extension X30 can be omitted gt Ilmc30 O TEST DEBUG This command generate
18. PUSHM PUSHA POP POPM LDE STE MOVDir XCHG STZ STNZ STZX ADD ADC ADCF SUB SBB MUL MULU DIV DIVU DIVX DADD DADC DSUB DSBB INC DEC RMPA CMP ABS NEG EXTS AND OR XOR NOT TST SHL SHA ROT RORC ROLC BCLR BSET BNOT BTST BNTST BAND BNAND BOR BNOR BXOR BNXOR BMCnd BTSTS BTSTC SMOVF SMOVB SSTR LDC STC LDINTB LDIPL PUSHC POPC FSET FCLR LDCTX STCTX ENTER EXITD BRK REIT INT INTO UND WAIT NOP Chapter 2 CPU Programming Model 2 1 Address Space 2 2 Register Sets 2 3 Data Types 2 4 Data Arrangement 2 5 Addressing Modes 2 6 Instruction Set 2 7 Outline of Interrupt CPU Programming Model 2 1 Address Space 2 2 1 Address Space The M16C 60 M16C 20 series has 1 Mbytes of address space ranging from address 00000H to address FFFFFH This section explains the address space and memory mapping the SFR area and the fixed vector area of the M16C 60 group 2 1 1 Operation Modes and Memory Mapping The M16C 60 group chooses one operation mode from three modes available single chip memory expansion and microprocessor modes The M16C 60 group address space and the usable areas and memory mapping varies with each operation mode Address Space Figure 2 1 1 shows the address space of the M16C 60 group Addresses 00000H to 003FFH are the Special Function Register SFR area The SFR area in each type of M16C 60 group microcomputer begins with ad
19. Pull up control register 0 PURO 03BD16 CRC data register CRCD 03FD16 Pulku control AEE 1 PURT 03BE16 CRC input register CRCIN 03FE16 _Pull up control register 2 PUR2 O3BFis 03FF16 Figure 2 1 4 Control register allocation 2 13 CPU Programming Model 2 2 1 Address Space Determination of Operation Mode The M16C 60 group operation mode is determined by bits 0 and 1 of the processor mode register 0 address 00004 Figure 2 1 5 shows the configuration of processor mode register 0 Processor mode register 0 Note 1 Symbol Address When reset Rapp PMO 000416 0016 Note 2 AW H bi b0 PMoo Processor mode bit 0 0 Single chip mode 0 1 Memory expansion mode 1 0 Inhibited om 1 1 Microprocessor mode PM02 R W mode select bit 0 RD BHE WR 1 RD WRH WRL Software reset bit The device is reset when this bit is set to 1 The value of this bit is 0 when read P b5 b4 PM04 Multiplexed bus space 0 0 Multiplexed bus is not used select bit 0 1 Allocated to CS2 space 1 0 Allocated to CS1 space 1 1 Allocated to entire space Note 4 PMO6 Port P40 to P4s function Address output select bit Note 3 Port function Address is not output BCLK output disable bit BCLK is output BCLK is not output Pin is left floating Note 1 Set bit 1 of the protect register address 000A16 to 1 when writing new values to this register Note 2 If the Vcc voltage is appl
20. Sets SB and FB registers back again LDC 00500H FB Define address with EQU in advance Enable to write to the processor made register 0 1 Removes protect Software reset Weg Remove protect before setting e the software reset bit to 1 to reset the system in software SECTION VECT ROMDATA ORG OFFFFOH LWORD WDT_INT Sets start address of interrupt handler routine to watchdog timer interrupt vector in advance Y Note 1 If the program runs out of control the contents of the base registers SB FB are not guaranteed Therefore they must be set correctly again before writing values to the SFR Note 2 The system enters a reset sequence immediately after the software reset bit is set to 1 Therefore no instructions following it are executed Figure 4 5 7 Example of runaway detection program 2 171 Programming Style 4 4 6 Sample Program 4 6 Sample Programs This section shows examples of commonly used processing in programming of the M16C 60 M16C 20 series For more information refer to Application Notes M16C 60 M16C 20 Series Sample Programs Collection Conditional Branching Based on Specified Bit Status BTST 0 WORK_1 JC LABEL1 Branches to LABEL1 if specified bit 1 Conditional branched by two instructions LABEL1 BTST 1 WORK_1 JNC LABEL2 Branches to LABEL2 if specified bit 0 e LAB
21. Table 2 6 9 Add Subtract amp Conditional Branch Instruction Mnemonic Description Format Explanation ADJNZ B IMM dest label Adds immediate to dest ADJNZ W IMM dest label Jump to label if result is not 0 SBJNZ B IMM dest label Subtracts immediate from dest SBJNZ W IMM dest label Jump to label if result is not 0 Note 1 IMM can only be a 4 bit immediate 8 to 7 for the ADJNZ instruction 7 to 8 for the SBJNZ instruction Note 2 The range of addresses to which control can jump in PC relative addressing is 126 to 129 from the start address of the ADJNZ SBUJNZ instruction ADJNZ W 2 R0 LOOP SBJNZ W 2 R0 LOOP LOOP RO lt RO 2 RO amp RO 2 YES YES Figure 2 6 8 Typical operations of add subtract amp conditional branch instructions 72 CPU Programming Model 2 6 Instruction Set Sum of Products Calculate Instruction This instruction calculates a sum of products and if an overflow occurs during calculation generates an overflow interrupt Set the multiplicand address multiplier address and sum of products calculation count in each register as shown in Figure 2 6 9 Figure 2 6 10 shows an example of how the sum of products calculate instruction works Multiplicand address Multiplier address Sum of products calculation count Calculation result When operating in bytes the register used to store the calculation result is RO Figure 2 6 9 Setting registers for sum
22. This addressing can be used in LDE and STE instructions Symbol A1A0 Example LDE B A1A0 ROL 00000H ey Mbytes of memory space Al AO A1A0 0002H 0000H L000 pe Ro xn ser FFFFFH a Figure 2 5 17 32 bit address register indirect addressing 36 CPU Programming Model 2 2 5 Addressing Modes Address Register Relative with 20 Bit Displacement The value of an address register plus dsp is the effective address to be operated on The range of effective addresses is 00000H to FFFFFH If the addition result exceeds FFFFFH the most significant bits above and including bit 21 are ignored This addressing can be used in LDE STE JMPI and JSRI instructions Symbol dsp 20 A0 dsp 20 A1 1 When used in LDE STE instruction Example LDE B 40000H AO ROL 00000H 0 to FFFFH AO 40000H 1000H 41000H RO FFFFFH Figure 2 5 18 Address register relative addressing with 20 bit dsp 1 2 When used in JMPI JSRI instruction Example JMPI A 40000H AO 00000H 40000H AO 40000H 1000H 41000H PC 10000H FFFFFH Figure 2 5 19 Address register relative addressing with 20 bit dsp 2 37 CPU Programming Model 2 5 Addressing Modes PC Relative The value of the program counter PC plus dsp is the effective address to be operated on The value of the PC here is the start address of an instruction in which this addressing is used The PC relative addressing can be used in JMP and J
23. When using a relocatable assembler it is normally desirable to write the program source separately in several files The following lists the advantages that can be obtained by dividing the source file 1 Shared program and data Data exchanges between development projects are facilitated making it possible to reuse only a necessary part from existing software 2 Reduced assemble time When modifying or correcting the program only the modified or corrected file needs to be reasssembled This helps to reduce the assemble time The following explains how to write the source program in cases when the file is divided into three definition main program and subroutine processing 156 Programming Style 4 4 4 Dividing Source File Division Example 1 Definition WORK A30 Write definitions of the work RAM area and data table in file 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk File 1 WORK A30 skkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk In order for work RAM and labels to SECTION WORK DATA be referenced from another file ORG RAM_TOP declare global labels using GLB GLB WORK_1 WORK_2 WORK_3 WORK_4 Processed as global label GLB DATA_TABLE Processed as global label BTGLB W1_b0 W2_b1 Processed as global bit symbol GLOBAL_WORK_TOP WORK_1 BLKB Allocates work RAM area WORK_2 BLKB In order for bit symbol define
24. control jumps to src In this case if src is memory the instruction requires 3 bytes of memory capacity When using this instruction always be sure to specify a jump distance specifier Figure 2 6 15 shows an example of how the indirect branch instruction works Table 2 6 15 Indirect Branch Instruction Mnemonic Description Format Explanation Jumps indirectly to the address indicated by src Range of jump W Jump in PC relative addressing from 32 768 to 32 767 A Jump in 20 bit absolute addressing JMPI A A0 AO JMPI A A0 m 01000H 02000H Jump address 12345H Figure 2 6 15 Typical operation of indirect branch instruction 78 CPU Programming Model 2 2 6 Instruction Set Special Page Branch Instruction This instruction causes control to jump to the address that is set in each table of the special page vector table plus FOOOOH The range of addresses to which control jumps is FOOOOH to FFFFFH Although the jump address is stored in memory this instruction can execute branching at high speed Use a special page number or label to specify the jump address Be sure to add before the special page number or before the label If a label is used to specify the jump address the assembler obtains the special page number by calculation Figure 2 6 16 shows an example of how the special page branch instruction works Table 2 6 16 Special Page Branch Instruction Mnemonic Descr
25. instructions only Absolute O abs 16 bits 0 to FFFFH O abs 20 bits 0 to FFFFFH LDE STE JMP and JSR instructions only Address register O A0 or A1 without dsp O A1A0 without dsp A0 or A1 without dsp indirect LDE and STE instructions only 0 to 1FFFH Address register O A0 or A1 dsp 8 16 bits O A0 dsp 20 bits only relative LDE STE JMPI and JSRI instructions only SB relative and O SB dsp 8 16bit SB dsp 8 11 16 bits i FB relative 0 to 255 0 to 65534 0 to 31 0 to 255 0 to 8191 O FB dsp 8bit 128 to 127 FB dsp 8bit 16 to 15 Stack pointer D O SP dsp 8 bits 128 to 127 relative MOV instruction only Program counter O label S 2 to 9 relative B 128 to 127 i W 32768 to 32767 JMP and JSR instructions only Control register O INTBL INTBH ISP USP SB FB direct FLG LDC STC PUSHC and POPC instructions only l FLG direct U I O B S Z D and C flags FCLR and FSET instructions only Instruction Set Overview of M16C 60 M16C 20 Series 1 3 Introduction to CPU Architecture Table 1 3 3 lists the instructions of the M16C 60 M16C 20 series classified by function There is a total of 91 discrete instructions Table 1 3 3 Instruction Set of M16C 60 M16C 20 Series Item Content Instruction set Data transfer instructions 14 instructions Arithmetic logic instructions 31 instructions
26. they are located If start address is not specified sections are located beginning with address 0 Outputs error tag file Displays version on screen Linker is terminated without performing anything else command file name Starts up In30 using specified file as command parameter Do not insert space between and command file name This option cannot be used with any other option simultaneously 181 Programming Style 4 7 Generating Object Files Example for Using In30 Commands Example Extension R30 can be omitted gt In30 SAMPLE1 SAMPLE2 O_ABSSMP This command generates ABSSMP X30 J Command option can be gt In30 cmdfile This command starts up In30 using the content of cmdfile as a command parameter written in uppercase or lowercase as desired Use hexadecimal number to write address If address begins Typical description of with alphabet add 0 at the beginning Do not add H to SAMPLE1 SAMPLE2 denote hexadecimal SAMPLE3 ORDER RAM 80 ORDER PROG SUB DATA M A Section names are discriminated between uppercase and lowercase Link Error Tag File Relocatable file name Specifies 80H for start address of RAM section Specifies sequence in which order sections are located Command option to generate map file Add at the beginning of a comment Figure 4 7 3 shows an example of a link error tag file Assembl
27. 0 to 65534 0 to 31 0 to 255 0 to 8191 O FB dsp 8bit 128 to 127 FB dsp 8bit 16 to 15 Stack pointer D O SP dsp 8 bits 128 to 127 l relative MOV instruction only Program counter O label S 2 to 9 relative B 128 to 127 f W 32768 to 32767 JMP and JSR instructions only Control register O INTBL INTBH ISP USP SB FB direct FLG LDC STC PUSHC and POPC instructions only FLG direct D and C flags i ET instructions 24 CPU Programming Model 2 2 5 Addressing Modes 2 5 2 General Instruction Addressing This section explains each addressing in the general instruction addressing mode Immediate The immediate indicated by IMM is the subject on which operation is performed Add a before the immediate Symbol IMM IMM8 IMM16 IMM20 Example 123 decimal 7DH hexadecimal 01111011B binary Absolute The value indicated by abs16 is the effective address on which operation is performed The range of effective addresses is 00000H to OFFFFH Symbol abs16 Example 8000H DATA label 00000H Range of effective DATA 8000H addresses O8000H P OFFFFH 10000H FFFFFH Figure 2 5 1 Absolute addressing Register direct A specified register is the subject on which operation is performed However only the data and address registers can be used here Symbol 8 bits ROL ROH R1L R1H 16 bits RO R1 R2 R3 AO A1 25 CPU Pr
28. 10010001B Write B or b at the end of the operand 10010001b 607020 Write O or o at the end of the operand 607020 Decimal 9423 Do not write anything at the end of the operand Hexadecimal OA5FH Use numerals 0 to 9 and alphabets a to f or A to F 5FH to write the operand and add H or h at the end Oadfh However if the operand value begins with an 5fh alphabet add 0 at the beginning Floating Write an exponent including the sign after E or e in point number the exponent part For 3 4 x 1095 write 3 4E35 Name foo Write a label or symbol name directly as it is Expression 256 2 Use a numeric value name and operator in label 3 combination to write an expression Character string Enclose a character string with single or double string string quotations when writing it 97 Functions of Assembler 3 2 Method for Writing Source Program Floating point number Numeric values within the range shown below that are represented by floating point numbers can be written in the operand of an instruction The method for writing floating point numbers and description examples are shown in Table 3 2 2 in the preceding page Floating point numbers can only be used in the operands of the directive commands DOUBLE and FLOAT Table 3 2 3 lists the range of values that can be written in each of these directive commands Table 3 2 3 Description Range of Floating point Numbers Directive Command Description Ra
29. 2 Initial Setting the CPU 4 2 Initial Setting the CPU Each register as well as RAM and other resources must be initial set immediately after power on or after a reset If the CPU internal registers remain unset or there is unintended data left in memory before program execution all this could cause the program to run out of control Therefore the internal resources must be initial set at the beginning of the program This initial setting includes the following e Declaration to the assembler e Initialization of the CPU internal registers flags and RAM area e Initialization of work area e Initialization of built in peripheral functions such as port timer and interrupt i 4 2 1 Setting CPU Internal Registers After a reset is canceled normally it is necessary to set up the registers related to the processor modes and system clock For a setup example refer to Section 4 2 7 Sample Program List 2 Initial Setting 2 4 2 2 Setting Stack Pointer When using a subroutine or interrupt the return address etc are saved to the stack Therefore the stack pointer must be set before calling the subroutine or enabling the interrupt For a setup example refer to Section 4 2 7 Sample Program List 2 Initial Setting 2 4 2 3 Setting Base Registers SB FB The M16C 60 M16C 20 series has an addressing mode called base register relative addressing to allow for efficient data access Since a relative address from an address that se
30. 2 Method for Writing Source Program Assemble Control Usage and Description Example Defines a symbol Defines a bit symbol Forward referenced symbol names cannot be written A symbol or expression can be written in the operand Symbols and bit symbols can be specified as global Example symbol EQU 1 symbol1 EQU symbol symbol bito BTEQU 0 0 biti BTEQU 1 symbol1 Declares the end of the assemble source Write at least one instance of this command in one assembly source file The as30 assembler does not check for errors in the lines that follow this directive command Example END Assumes an SB register value Chooses SB relative addressing Chooses bit instruction SB relative addressing Assumes an FB register value Chooses FB relative addressing Always be sure to set each register before choosing the desired addressing mode Since register values are not set in the actual register write an instruction to set the register value immediately before or after this directive command Example SB 80H LDC 80H SB ER OCOH LCD 80H FB SBSYM sym1 sym2 FBSYM sym3 sym4 Reads a file into a specified position 110 Always be sure to write the extension for the file name in the operand Directive command FILE or a character string including can be written in the operand Example INCLUDE INCLUDE initial a30 FILE inc Functions of Assembler 3 2 Metho
31. 6 Instruction Set e To know how to use interrupts Chapter 2 CPU Programming Model 2 7 Interrupts Chapter 4 Programming Style 4 3 Interrupts e To check the functions of and the method for writing directive commands Chapter 3 Functions of Assembler 3 2 Writing Source Program e To know the M16C 60 M16C 20 series programming techniques Chapter 4 Programming Style e To know the M16C 60 M16C 20 series development procedures Chapter 4 Programming Style 4 7 Generating Object File M16C Family related document list Usages Microcomputer development flow Selection of Type of document Outline design Data sheet and data book Contents Hardware specifications pin assignment memory map specifications of peripheral functions electrical characteristics timing charts Hardware ee Detail design of system User s manual Detailed description about hardware specifi cations operation and application examples connection with peripherals relationship with software Programming manual Method for creating programs using assem bly and C languages Hard 2 ware Software manual Software System evaluation M16C Family Line up M16C 80 Series M16C Family M16C 60 Series M16C 20 Series Detailed description about operation of each instruction assembly language M16C 80 Group
32. 8 bits x 1 channel UART 8 bits x 1 channel M16C 60 series16 bit CPU core Registers Program counter Watchdog timer Lat 15 bits ROH ROL pc RIL Vector table INTB Stack pointer ISP USP R2 Multiplier FLG Note 1 ROM size depends on MCU type Note 2 RAM size depends on MCU type Figure 1 2 1 Block diagram of the M16C 60 group Overview of M16C 60 Series 1 2 Outline of M16C 60 Group M16C 20 Group Outline Specifications of the M16C 60 Group Table 1 2 1 lists the outline specifications of the M16C 60 group Table 1 2 1 Outline Specifications of M16C 60 Group 2 7 to 5 5 V with 7 MHz external oscillator 1 wait state 100 pin plastic molded QFP 10 MHz with 10 MHz external oscillator 100 ns with 10 MHz external oscillator Internal memory 100 ns with 10 MHz external oscillator Basic bus cycle External memory 100 ns with 10 MHz external oscillator no wait state ROM capacity RAM capacity 10 Kbytes Internal memory Note 64 Kbytes Single chip memory expansion and Operation mode microprocessor modes External address space 1 Mbytes linear 64 Kbytes Address bus 20 bits 16 bits External data bus width 8 bits 16 bits Bus specification Separate bus multiplexed bus 4 chip select lines built in Clock generating circuit 2 circuits built in ext
33. Example of multiple interrupt execution 11 153 Programming Style 4 4 4 Dividing Source File 4 4 Dividing Source File Write the program separately in several source files This helps to make your program put in order and easily readable Furthermore since the program can be assembled separately one file at a time it is possible to reduce the assemble time when correcting the program This section explains how to divide the source file 4 4 1 Concept of Sections A program written in the assembly language generally consists of a work area program area and constant data area When the source file AS30 is assembled by the assembler as30 relocatable module files R30 are generated The relocatable module files contain one or more of these areas A section is the name that is assigned to each of these areas Consequently a section can be considered to be the name that is assigned to each constituent element of the program Note that the assembler as30 requires that even in the case of the absolute file there must always be at least one section specified in one file 154 Programming Style 4 4 Dividing Source File Functions of Sections When linking the source files the areas of the same section name are located at contiguous addresses sequentially in order of specified files Furthermore the start address of each section can be specified when linking This means that each section can be relocated any number of
34. Figure 3 2 8 Indicates the start position of a search character string in character strings specified in operand Always be sure to enclose the operand with brackets and the character string with quotations Character strings can be written using 7 bit ASCII code characters If the search start position 1 it means the beginning of a character string lt Description format gt INSTR string Search character string search start position INSTR string search character string search start position lt Description example gt Refer to Figure 3 2 9 SUBSTR Extracts a specified number of characters from the character string position specified in operand 121 Always be sure to enclose the operand with brackets and the character string with quotations Character strings can be written using 7 bit ASCII code characters If the extraction start position 1 it means the beginning of a character string lt Description format gt SUBSTR string start position number of characters SUBSTR _ string start position number of characters lt Description example gt Refer to Figure 3 2 10 Functions of Assembler 3 3 2 Method for Writing Source Program Example of LEN Statement In the example of Figure 3 2 8 the length of a specified character string is 13 for Printout_data and 6 for Sample Example of macro description bufset MACRO f1 f2 buffer f1
35. Relative In SB relative addressing the value of the SB register plus dsp is the effective address to be operated on The relative range is 0 to 255 FFH for dsp 8 SB and 0 to 65 535 FFFFH for dsp 16 SB In FB relative addressing the value of the FB register plus minus dsp is the effective address to be operated on The relative range is 128 to 127 80H to 7FH In this addressing mode addresses can be accessed in the negative direction An 8 bit dsp is the only valid displacement 16 bit dsp cannot be used 16 bits 00000H A 0 dsp 8 SB 255 FFH 16 bits SE e Effective address range TJ S i dsp 8 FB 127 7FH OFFFFH y 10000H T Y Figure 2 5 9 SB relative and FB relative addressing 30 CPU Programming Model 2 5 Addressing Modes Application Example of SB Relative Column SB relative addressing can be used in the specific data tables of tasks as shown in Figure 2 5 10 The data necessary to operate on each task is switched over as tasks are switched from one to another If SB relative addressing is used for this purpose data can be switched over simply by rewriting the SB register lt Dynamic control of SB gt l I EE X X p Bearer el eed Data table specific to task 1 sg 4 Bann te H Lea are at Data table specific to task 2 X X Figure 2 5 10 Application example of SB relative addressing Application Example of FB Relative Column FB relative add
36. Write subroutine processing in file 3 KK KKK KKK KK KK KK KK KK RIK KK KK IKK KK KK KK KKK KR IKK KK RK KK KKK KERR RK KK RK KKK RK File 3 SUB_1 A30 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk H skkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Allocation of work RAM area SECTION WORK DATA Unless declared as global labels are handled as local labels in file 3 SUB_1 A30 LOCAL_WORK_TOP LOCAL_1 BLKB Allocates area for local data LOCAL_2 BLKB LOCAL_WORK_END Since subroutine SUB_1 is called from file 2 MAIN A30 specify SUB_1 to be a global label xxx USiNg GLB before call Because the label exists in the file this becomes a global declaration EE Declaration to assembler SECTION PROGRAM CODE SUB_1 Processed as global label DATA_TABLE Processed as external reference label 00380H Sets SB register value for assembler 00480H Sets FB register value for assembler LOCAL_1 LOCAL_2 Encodes specified label in SB relative addressing mode Because the label is defined in another file file 1 specify external reference Sets initial value in SB register Sets initial value in FB register Accesses local data _OCAL_1 in SB relative addressing Ke 40 LOCAL_ 2 Retrieves fixed data table by external reference ADD B LOCAL_1 LO L_2 Adds local data LOCAL_1 LOCAL_2 Retu
37. and handled as such by specifying addresses with ORG immediately after directive command SECTION e Addresses in the section are made relocatable values when assembling the program e The values of labels defined in this type of section become absolute 132 Programming Style 4 1 Hardware Definition 4 1 5 Sample Program List 1 Initial Setting 1 DI KR IR RR RK peluda ege ee eee ee Ree A RAEN e Reads include file INCLUDE m30600 inc Le into source file skkkkkkkkkkkkkkkkkkkkkkkk ries kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Symbol definition RAM_TOP EQU 00400H Start address of RAM RAM_END EQU 02BFFH End address of RAM ROM_TOP EQU OFOOO0H Start address of ROM FIXED _VECT_ TOP EQU OFFFDCH Start address of fixed vector SB_BASE EQU 00380H Base address of SB relative addressing FB BASE EQU 00480H Base address of FB relative addressing skkkkkkkkkkkkkkkkkkkkkkk Allocation of work RAM VEA EE Add colon at the end of a label Matched to hardware name SECTION WORK DATA RAM area ORG RAM_TOP WORKRAM_TOP char BLKB 1 Allocates a 1 byte area short BLKW 1 Allocates a 2 byte area addr BLKA 1 Allocates a 3 byte area long BLKL 1 Allocates a 4 byte area WORKRAM_END Do not add 7 colon for a bit symbol chat bo BTEOU Ochar Bit 0 of char Megetetetteeeieetetreeeebiebehrieheg Definition of bit symbo short_b1 BTEQU 1 sho
38. bit This section describes these data types Integer An integer may be a signed or an unsigned integer A negative value of a signed integer is represented by a 2 s complement Signed byte 8 bit integer b7 b Unsigned byte 8 bit integer Signed word 16 bit integer Unsigned word 16 bit integer Signed long word 32 bit integer Unsigned long word 32 bit integer Figure 2 3 1 Integer data Decimal BCD The BCD code is handled in packed format This type of data can be used in four kinds of decimal arithmetic instructions DADC DADD DSBB and DSUB 1 byte packed format 2 digits 2 byte packed format 4 digits Figure 2 3 2 Decimal data 21 CPU Programming Model 2 2 3 Data Types String A string is a block of data comprised of a consecutive number of 1 byte or 1 word 16 bit data This type of data can be used in three kinds of string instructions SMOVB SMOVF and SSTR e String of byte 8 bit data lt 83 gt e String of word 16 bit data lt 16 Figure 2 3 3 String data Bit Bit can be used in 14 kinds of bit instructions including BCLR BSET BTST and BNTST Bits in each register are specified by a register name and a bit number 0 to 15 Memory bits are specified by a different method in a different range depending on the addressing mode used For details refer to Section 2 5 4 Bit Instruction Addressing b15 bo RO Rien A 2 R0 RO register bit 2 b1
39. can be set for each section Note that the instructions which can be written in the section vary with this section type For details refer to AS30 User s Manual Programming Part If ALIGN is specified for a section the linker In30 locates the beginning of the section at an even address Example for Setting Up Sections Figure 4 1 6 shows an example for setting up each section SECTION WORK DATA Specifies a section name and a WORK work BLKB 1 section type section Specifies only a section name The assembler assumes section type CODE as it SECTION PROGRAM processes this line NOP PROGRAM section i Specifies a section name and a section SECTION PROGRAM CODE type NOP Specifies a section name a section type and that the beginning of the section be l located at an even address CONST SECTION CONST ROMDATA ALIGN section BYTE 12H END Figure 4 1 6 Example for setting up sections 131 Programming Style 4 1 Hardware Definition Section Attributes Each section is assigned an attribute when assembling the program There are two attributes relative and absolute 1 Relative attribute e Location of each section can be specified when linking source files Relocatable e Addresses in the section are made relocatable values when assembling the program e The values of labels defined in this type of section become relocatable 2 Absolute attribute e A section is assigned an absolute attribute
40. destination address and R3 as transfer count SSTR size 60 CPU Programming Model 2 6 Instruction Set Addressing General instruction Special instruction Flag change register direct register indirect register relative register direct 32 bit 2 5 O E 16 bit absolute Register direct Register indirect Register relative absolute 20 bit There is no addressing that can be used for string operation 61 Other Mnemonic BRK CPU Programming Model 2 6 Explanation Generate BRK interrupt Instruction Set ENTER Build stack frame EXITD Clean up stack frame and return from subroutine FCLR Clear dest flag FSET Set dest flag INT Generate software interrupt INTO When O flag 1 generate overflow interrupt LDC src dest Transfer to control register of src LDCTX abs16 abs20 Restore task context from stack LDINTB src Transfer src to INTB LDIPL src Transfer src to IPL NOP No operation POPC Restore control register from stack area PUSHC Save control register to stack area REIT Return from interrupt routine Returns from interrupt STC src dest Transfer from control register to dest STCTX abs16 abs20 Save task context to stack UND Generate interrupt for undefined instruction WA
41. flag 0 LEU C 0 Z 1 Equal or smaller NE NZ Z 0 Not equal Zero flag 0 PZ 0 Positive or zero GT S 1 amp O 1 amp Z 0 S 0 amp 0 0 amp Z 0 Signed and greater NO O 0 Overflow flag 0 LT S 1 amp O0 0 S 0 amp O0 1 Signed and smaller Range of jump 127 to 128 PC relative for GEU C GTU EQ Z N LTU NC LEU NE NZ and PZ 126 to 129 PC relative for LE O GE GT NO and LT JEQ LABEL1 SL Jumps to LABEL1 if Z flag 1 JEQ LABELI LABEL1 Figure 2 6 17 Typical operation of conditional branch instruction 80 CPU Programming Model 2 2 6 Instruction Set 2 6 7 High level Language Support Instructions These instructions are used to build and clean up a stack frame They execute complicated processing matched to high level languages in one instruction Building Stack Frame ENTER is an instruction to build a stack frame Use IMM to set bytes of the automatic variable area Figure 2 6 18 shows an example of how this instruction works Table 2 6 18 Stack Frame Build Instruction Mnemonic Description Format Explanation ENTER IMM Builds stack frame Note IMM indicates the size in bytes of the automatic variable area with only IMMB8 unsigned 8 bit immediate ENTER 3 1 Saves FB register to stack area 2 Transfers SP to FB 3 Subtracts specified immediate from SP to modify SP to allocate automatic variable area of ca
42. number 1 NOON SP correction value of Si ST eleele 1 Transfers register to stack area 0 Does not transfer register to stack area e Register information of task number n SP correction value of task number n Figure 2 6 20 Context table 83 Operation for Saving Context STCTX instruction Operation 1 Double abs16 task number and add abs20 start address of context table to it Read out the memory content indicated by the calculation result of task number x 2 abs20 as register information 8 bit data Operation 2 Save the registers indicated by the register information to the stack area Operation 3 Read out the content at the address next to the register information i e an address incremented by 1 as the SP correction value 8 bit data Operation 4 Subtract the SP correction value from SP to modify it 84 FFFFFH 00000H abs20 CPU Programming Model Stack area 2 6 Instruction Set Task number x 2 Context information Task number x 2 Context information SP correction value SP SP correction value CPU Programming Model 2 6 Instruction Set Operation for Restoring Context LDCTX instruction Operation 1 00000H Double abs16 task number and add abs20 A Task number x 2 base address of context table to it Read out the memory content indicated by the calculation result of task number x 2 abs20 as register information 8 bit data C
43. of products calculation instruction Table 2 6 10 Sum of Products Calculate Instruction Mnemonic Description Format Explanation Calculates a sum of products using AO as multiplicand address A1 as multiplier address and R3 as operation count Note 1 If an overflow occurs during calculation the overflow flag O flag is set to 1 before terminating the calculation Note 2 If an interrupt is requested during calculation the sum of products calculation count is decremented after completing the addition in progress before accepting the interrupt request RMPA W Calculation result of 1 Calculation result of 2 Calculation result of 3 Calculation result of 4 Figure 2 6 10 Typical operation of sum of products calculation instruction 73 CPU Programming Model 2 2 6 Instruction Set 2 6 4 Sign Extend Instruction This instruction substitutes sign bits for the bits to be extended to extend the bit length This section explains the sign extend instruction Sign Extend Instruction This instruction performs 8 bit or 16 bit sign extension If W is specified for the size specifier the bit length is sign extended from 16 bits to 32 bits In this case be sure to use the RO register Figure 2 6 11 show an example of how the sign extend instruction works Table 2 6 11 Sign Extend Instruction Mnemonic Descriptio
44. processor mode registers 0 and 1 74 RD WRH WRL all separate 75 16 output BCLK output 76 10010 75CF06000820 Z Indicates that zero format has been selected for instruction format wait 77 S Indicates that short format has been selected for instruction format sets registers 0 1 78 10016 B70A00 Z Q Indicates that quick format has been selected for instruction format ratio f Xin subclock 79 i 80 10019 EB300000 LDC 0 FLG Sets FLG value stack pointer ISP is used 81 1001D EB400011 LDC STACK_TAIL ISP Sets value of interrupt stack pointer ISP 82 10021 D9EA7D Q MOV W 0FFFEH PUR1 Port P44 to P47 port P5 to port P 85 Main program s 87 10024 MAIN 88 10024 F50700 WwW JSR INIT Calls initial setup routine 89 Jump range 32 768 to 32 767 90 10027 F51400 W JSR DISP LED display routine 93 94 1002A 95 1002A FEFF MAIN_10 Jump range 128 to 127 96 178 i S Indicates that jump distance specifier S has been selected 179 END B Indicates that jump distance specifier B has been selected W Indicates that jump distance specifier W has been selected A Indicates that jump distance specifier A has been selected Information List TOTAL ERROR S 00000 TOTAL WARNING S 00000 TOTAL LINE S 00179 LINES Outputs total number of errors derived from assembling as well as total number of warnings and total number of list lines Section List
45. repeat macro Write this command in relation to MREPEAT definition lt Description example gt Refer to Figure 3 2 5 119 Functions of Assembler 3 2 Method for Writing Source Program Macro Symbol Usage and Description Example MACPARA Indicates the number of actual This symbol can be written in the body of arguments given when calling a macro definition as a term of an expression If macro written outside the macro body value 0 is assumed lt Description example gt Refer to Figure 3 2 5 MACHER Indicates the number of times a This symbol can be written in the body of repeat macro is expanded macro definition as a term of an expression It can also be written as an operand of conditional assemble The value increments from 1 to 2 3 and so on each time the macro is repeated If written outside the macro body value 0 is assumed lt Description example gt Refer to Figure 3 2 5 120 Character String Function Usage and Description Example Indicates the length of a character string written in operand Functions of Assembler 3 2 Method for Writing Source Program Always be sure to enclose the operand with brackets and the character string with quotations Character strings can be written using 7 bit ASCII code characters This function can be written as a term of an expression lt Description format gt LEN string LLEN string lt Description example gt Refer to
46. times without having to change the source program Figure 4 4 1 shows an example of how sections actually are located in memory File1 File2 File3 Work area Work area Section name WORK Section name WORK Program area Section name PROGRAM Program area Program area Section name Section name PROGRAM PROGRAM Interrupt program area Section name Interrupt program INTRRUPT E e aE Constant data area INTRRUPT Section name Vector area constant data Section name VECT Linked l In30 File1 Flle2 Pie ORDER WORK 400 PROGRAM F0000 Address The address of VECT is already 00400H specified to be FFFOOH by Section name WORK ORG in the source file WORK of File1 WORK of File2 Free area 0000H Section name PROGRAM PROGRAM of File1 PROGRAM of File2 PROGRAM of File3 Addresses are specified when linking Section name INTRRUPT l INTRRUPT of File1 Sections whose addresses are INTRRUPT of File2 not specified are located after the sections which have had their addresses specified Section name CONST without leaving spaces CONST of File3 e Free area Section name VECT Sections whose addresses VECT of File3 are fixed as in the case of interrupt vectors can have their addresses fixed by ORG Figure 4 4 1 Example of sections located in memory 155 Programming Style 4 4 4 Dividing Source File 4 4 2 Dividing Source File The as30 used in this manual is a relocatable assembler
47. to be used ISP or USP When using only the assembler normally choose the ISP For details refer to Section 4 3 7 ISP and USP Set the initial value in the selected stack pointer register Since the M16C 60 group stack is a FILO type Mitsubishi recommends setting the initial value of the stack pointer at the last RAM address Example Setting 2C00H in interrupt stack pointer LDC 00000000B FLG Uses interrupt stack pointer ISP LDC 02C00H ISP Sets 2COOH in ISP Note 1 FILO first in last out When saving registers they are stacked in order of addresses beginning with the largest address When restored they are removed from the stack in order of addresses beginning with the smallest address one that was saved last Note 2 FLG and ISP are control registers Use the LDC instruction transfer to a control register to set up these registers 164 Programming Style 4 4 5 A Little Tips Saving and Restoring to and from Stack Area Registers and internal other resources are saved and restored to and from the stack area in the following cases 1 When an interrupt is accepted When an interrupt is accepted the registers listed below are saved to the stack area Program counter PC 2 low order bytes Flag register FLG 2 bytes Total 4 bytes After the interrupt is serviced the above registers that have been saved to the stack area are restored from the stack by the REIT instruction Stack area m 4
48. uod A Timer Timer TAO 16 bits Timer TA1 16 bits Timer TA2 16 bits Expandable up to 10 channels UART clock synchronous SI O 8 bits x 2 channels H 8d 7 Timer TA4 16 bits Timer TBO 16 bits Timer TB1 16 bits Timer TB2 16 bits CRC arithmetic circuit CCITT Polynomial X16 X12 X5 1 Timer TA3 16 bits M16C 60 series16 bit CPU core S8d E Registers Stack pointer Watchdog DALL DAL timer 15 bits ea Vector table DMAC Ge 2 channels AO Al RAM D A converter F Multiplier 10K bytes 8 bits X 2 channels Note 1 UART clock synchronous SI O In case of the M16C 61 group 1 UART clock synchronous SI O 1 clock asynchronous SI O 3 timer B In case of the M16C 62 group 6d Od 8 atl Old HOd ry 2 M16C 20 group ppp pp gg Port PO Port P5 Port P6 Port P7 I O ports Port P3 Port P4 Port P1 Internal peripheral functions System clock generator XIN XOUT XCIN XCOUT A D converter 10 bits x 8 channels Expandable up to 13 channels Timer Timer TAO Timer TBO Timer TB1 Timer TXO Timer TX1 Timer TX2 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits UART clock synchronous SI O
49. 00000 SECTION C SECTION B Y Absolute attribute section Relative attribute section Figure 3 2 2 Example of address control 104 Functions of Assembler 3 3 2 Method for Writing Source Program Reading Include File into Source Program The AS30 system allows the user to read an include file into any desired line of the source program This helps to increase the program readability Reading include file into source program Write the file name to be read into the source program in the operand of directive command INCLUDE All contents of the include file are read into the source program at the position of this line Example INCLUDE initial inc Source file sample a30 Include file initial inc SECTION memory DATA BLKB 10 10 A0 BLKW 1 0 work A0 SECTION init AO INCLUDE initial inc loop SECTION program CODE 0 flags D be E Cc 2 Ka C be Si x lt Lu After program is assembled SECTION memory DATA 000000 BLKB 10 00000A BLKW 1 SECTION init 000000 INCLUDE initial 000000 10 A0 000002 0 work A0 000006 AO 000007 loop 000009 0 flags 000000 SECTION program CODE Addresses output by as30 Figure 3 2 3 Reading include file into source program 105 Functions of Assembler 3 2 Method for Writing Source Program Global and Local Address Control The following explains how the values of labels symbols and bit symbols are controlled by the AS30 system The AS30 system classifi
50. 1 nop jmp ENDM Figure 3 2 6 Example of macro definition and macro call Macro Call The contents of the macro body defined as a macro can be called into a line by writing the macro name defined with directive command MACRO in that line Macro names cannot be referenced externally When calling the same macro from multiple files define a macro in an include file and include that file to call the macro 117 Functions of Assembler 3 2 Method for Writing Source Program Repeat Macro Function The macro body enclosed with macro directive commands MREPEAT and ENDM is expanded into a specified line repeatedly as many times as specified Macro call of a repeat macro is not available Figure 3 2 7 shows the relationship between macro definition and macro call of a repeat macro Example of source program Dummy argument MACRO num MREPEAT num Ge AF num gt 49 definition part EXITM ENDIF nop ENDR SECTION program Actual argument Macro call After expansion SECTION program main Macro expansion part Figure 3 2 7 Example of macro definition and macro call 118 Functions of Assembler 3 2 Method for Writing Source Program Macro Directive Commands There are following types of macro commands available with AS30 e Macro directive commands These commands indicate the beginning end or suspension of a macro body and declare a local label in the macro e Macro symbols
51. 1 Hardware Definition 4 1 Hardware Definition This section explains how to define an SFR area and create an include file how to allocate RAM data and ROM data areas and how to define a section 4 1 1 Defining SFR Area It should prove convenient to create the SFR area s definition part in an include file There are two methods for defining the SFR area as described below Definition by EQU Figure 4 1 1 shows an example for defining the SFR area by using directive command EQU Define the address at which processor mode register 0 is placed In the following lines define the addresses of other registers Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register Define the start address of a register that consists of more than 2 bytes WDTS EQU OOOEH Watchdog timer start register WDC EQU 000FH Watchdog timer control register RMADO EQU 0010H Address match instruction register 0 RMAD1 EQU 0014H Address match instruction register 1 H SARO EQU 0020H DMAO source pointer DARO EQU 0024H DMAO destination pointer TCRO EQU 0028H DMAO transfer counter DMOCON EQU 002CH DMAO control register SAR1 EQU 0030H DMA1 source pointer DAR1 EQU 0034H DMA1 destination pointer TCR1 EQU 0038H DMA1 transfer c
52. 10 tt flag2 flag1 flags Reference method The bit symbol can be written in the operand of a single bit manipulating instruction Example BCLR BCLR BCLR flag1 flag2 flag3 96 Symbol Function Indicates a constant value Definition method Use a directive command that defines a numeral Example valuel EQU 1 value2 EQU 2 Reference method Write a symbol in the operand of an instruction Example MOV W RO value2 1 value3 EQU value2 1 Location symbol Function Indicates the current line of the source program Definition method Unnecessary Reference method Simply write a dollar mark in the operand to indicate the address of the line where it is written Example JMP 5 Functions of Assembler 3 2 Method for Writing Source Program Description of Operands For mnemonics and directive commands write an operand to indicate the subject to be operated on by that instruction Operands are classified into five types by the method of description Some instructions do not have an operand For details about use of operands in instructions and types of operands refer to explanation of the method for writing each instruction e Numeric value Numeric values can be written in decimal hexadecimal binary and octal Table 3 2 2 shows types of operands description examples and how to write the operand Table 3 2 2 Description of Operands Type Description Method of Description Example
53. 38516 g vers 1 A D register 2 AD2 038616 8 03C616 opze TimMer AO TAO zc A D register 3 AD3 038816 e 03C816 o3agie mer A1 TA1 See A D register 4 AD4 038A16 S 03CA16 F ogsBie TimMer A2 TA2 zeen AH register 5 ADS 038Ci6 03CC16 ogsDie TimMer A3 TA3 Act A D register 6 AD6 038E16 j 03CE16 o38F1e Timer A4 TA4 oseke A D register 7 AD7 039016 E 03D016 039116 Timer BO TBO 03D116 039216 03D216 o39316 Timer B1 TB1 03D316 k 03D416 A D control register 2 ADCON2 039516 Timer B2 TB2 039616 Timer AO mode register TAOMR 0306168 A D control register 0 ADCONO 039716 Timer A1 mode register TA1MR 03D716 A D control register 1 ADCON1 039816 Timer A2 mode register TA2MR 03D818 D A register 0 DAO 039916 Timer A3 mode register TASMR 03D516 03D916 039A16 Timer A4 mode register TA4MR 03DA16 D A register 1 DA1 039B16 Timer BO mode register TBOMR 03DB16 039C16 Timer B1 mode register TB1MR et D A control register DACON 039D16 Timer B2 mode register TB2MR D n O39E16 O3DE16 039F16 03DF16 03A016 UARTO transmit receive mode register UOMR 03E016 Port PO PO 03A116 UARTO bit rate generator UOBRG 03E116 Port P1 P1 03A216 03E216 Port PO direction register PDO UARTO transmit buffer register UOTB
54. 5 b0 An Heen 14 A0 AO register bit 14 Figure 2 3 4 Specification of register bits Address b7 00000H A Address nH bit 2 base Figure 2 3 5 Specification of memory bits 22 CPU Programming Model 2 2 4 Data Arrangement 2 4 Data Arrangement The M16C 60 M16C 20 series can handle nibble 4 bit and byte 8 bit data efficiently This section explains the data arrangements that can be handled by the M16C 60 M16C 20 series Data Arrangement in Register Figure 2 4 1 shows the relationship between the data sizes and the bit numbers of a register As shown below the bit number of the least significant bit LSB is 0 The bit number of the most significant bit MSB varies with the data sizes handled Nibble 4 bits Byte 8 bits Word 16 bits b31 MSB Figure 2 4 1 Data arrangement in register Data Arrangement in Memory Figure 2 4 2 shows the data arrangement in the M16C 60 M16C 20 series memory Data is arranged in memory in units of 8 bits as shown below A word 16 bits is divided between the lower byte and the upper byte with the lower byte DATA L placed in a smaller address location Similarly addresses 20 bits and long words 32 bits are located in memory beginning with the lower byte DATA L or DATA LL DATA LL DATA LH DATA HL DATA HH Byte 8 bits Word 16 bits Address 20 bits Long word 32 bits g Figure 2 4 2 Data arrangement in memory 23
55. 8 2 6 2 Transfer and String INStructions est nite ta cine aiaia 64 2 6 3 ege E e Le 67 20 4 Sigm Extend MStUCTON ET 74 2 6 5 BILIMSMUCIIONS tee EE antennae EE eee 75 2 6 6 Branch INStruCtiOns seisnesid ee eeceeeeeeeee cece ee anena reai aidaa an aiaa anie aA a 77 2 6 7 High level Language Support Instructions ssessseeeseeeesenesneesnnessntennntrnnnsnnssrnnssrnssernssennsenn 81 216 8 OS lee eigene EE 83 2 7 Outline OF Interrupt egene deed Eed ee EES 86 2 7 1 Interrupt Sources ANd Control 86 EE Del ne 87 Chapter 3 Functions of Assembler 3 1 Outline OF ASSO Sy Stem ic SES EEN eege ENNEN 90 3 2 Method for Writing Source Program ccccesesceeeeseeeeeeeeeseeneeeeeneeeeseeeeneaeseeensaaeseeensnanseeeneenes 93 ST Basic Rule sides daciedevcesscedsdevendse adds aad ENER SE dee cance date dened dd 93 3 22 Address G10 E EE 101 3 2 3 Directive Commande nandai nenda areri iaia adanan naa nda EAEE aaa iaaa 108 3 2 4 Macro Wille te EE 116 8 2 5 Structured Description FUunCtion sais scccassscdcecsens daceneesslecsveca REENEN ENEE aa aE aaea 124 Chapter 4 Programming Style 4 1 Hardware Definition E 126 4 1 1 Defining SFR Area ken 126 412 Allocating RAM Data DEE hie ase eee 129 Ee lees Me Le RE 130 4 1 4 Defining a SOCOM NEE 131 4 1 5 Sample Program List 1 Initial Setting 1 133 4 2 Initial Setting the CPU iaiia aeaaeae naaa aaaeeeaa aaaea aeara EENEG 136 4 2 1 Setting CPU Internal Registers ceeeeee
56. ADVANCED AND EVER ADVANCING JITSUBISHI ELECTRIC MITSUBISHI 16 BIT SINGLE CHIP MICROCOMPUTER M16C FAMILY MITSUBISHI ELECTRIC Keep safety first in your circuit designs e Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents informa
57. ANA NANANA ENNAN EA SENE KNAAR 153 4 4 Dividing Source File eebe ee EENS 154 4 4 1 CONCEPT of Sections a a aaa ae aiaa Ni EE 154 4 4 2 RI le e SOUCE UE 156 e Library UE 162 45 VE LUES 164 45A Stack ALO EE 164 4 5 2 Setup Values of SB and FB ReQisters AAA 166 4 5 3 Alignment Specificato Meissie a e a eai a aS 167 4 5 4 Watchdog lr EE 169 4 6 Sample Programs 2eegoeskieeeeEeEEe seed 172 4 7 Generating Object Files ssunnsennnnennnnunnnnunnnunnnnnnnnnnnnnnnnnnnnn nunnu nnnnnnnnnnnnnnnnnnnnnnnn unnn nnn nunne nnmnnn 174 ATW AS ele ln ET 175 Chapter 1 Overview of M16C 60 M16C 20 Series 1 1 Features of M16C 60 M16C 20 Series 1 2 Outline of M16C 60 M16C 20 Group 1 3 Introduction to CPU Architecture Overview of M16C 60 M16C 20 Series 1 1 1 Features of M16C 60 M16C 20 Series 1 1 Features of M16C 60 M16C 20 Series The M16C 60 M16C 20 series is a line of single chip microcomputers that have been developed for use in built in equipment This section describes the features of the M16C 60 M16C 20 series Features of the M16C 60 M16C 20 series The M16C 60 M16C 20 series has its frequently used instructions placed in a 1 byte op code For this reason it allows you to write a highly memory efficient program Furthermore although the M16C 60 M16C 20 series is a 16 bit microcomputer it can perform 1 4 and 8 bit processing efficiently The M16C 60 M16C 20 series has many instructions that can be execute
58. BLKB_ 1 00400H ALIGN 00401H Address is incremented by 1 WORK_2 BLKW 1 00402H WORK_3 BLKA 1 00404H ALIGN 00407H Address is incremented by 1 WORK A BLKL 1 00408H SECTION PROGRAM CODE ORG OFOOOOH MOV W 0 RO FOOOOH D900H Figure 4 5 4 Example of alignment specification 168 Programming Style 4 4 5 A Little Tips 4 5 4 Watchdog Timer The following explains the precautions on and the method for using the watchdog timer What Does a Watchdog Timer Do The watchdog timer is a 15 bit timer used to prevent the program from going wild If the program runs out of control the watchdog timer underflows thereby generating a watchdog timer interrupt The program can be restarted by a software reset etc in the interrupt handler routine The watchdog timer interrupt is a nonmaskable interrupt The watchdog timer is idle immediately after a reset is deactivated it is invoked to start counting by writing to the watchdog timer start register Method for Detecting Program Runaway The chart below shows an operation flow when the program is found out of control and the method of runaway detection 1 Operation flow When normal ss e Write to the watchdog timer start register before the watchdog timer underflows Runaway detected see An interrupt is generated unless some processing is executed to write to the watchdog timer start register before the watchdog timer underflows due to progra
59. C 001816 005816 Timer A3 interrupt control register TA3IC 001916 005916 Timer A4 interrupt control register TA4IC 001A16 005A16 Timer BO interrupt control register TBOIC 001B16 005B16 Timer B1 interrupt control register TB1IC 001C16 005C16 Timer B2 interrupt control register TB2IC 001D16 005D16 INTO interrupt control register INTOIC 001E16 005E16 _INT1 interrupt control register INT11C 001F16 005F16 _INT2 interrupt control register INT2IC 002016 002116 DMAO source pointer SARO 002216 002316 002416 002516 DMAO destination pointer DARO 002616 002716 002816 DMAO transfer counter TCRO 002916 002A16 002B16 002C16 DMAO control register DMOCON 002D16 002E16 002F16 003016 003116 DMA1 source pointer SAR1 003216 003316 003416 003516 DMA1 destination pointer DAR1 003616 003716 003816 003915 DMA1 transfer counter TCR1 003A16 003B16 Die DMA1 control register DM1CON 003D16 003E16 003F16 Figure 2 1 3 Control register allocation 1 12 CPU Programming Model 2 1 Address Space 038016 Count start flag TABSR acre AD reoi S ter 0 ADO 038116 Clock prescaler reset flag CPSRF 03C116 register 0 ADO 038216 One shot start flag ONSE 086218 T AD register 1 ADI 038316 Trigger select register TRGSR 030316 9 AD1 038416 Up down flag UDF 0341s 0
60. Definition Line Function This is the line in which only a label name is written Description method Always be sure to write a colon immediately following the label name Example Assembly Source Line Function This is the line in which a mnemonic is written Description method A label name at beginning and a comment can be written in the assembly source line Precautions Only one mnemonic can be written in one line No mnemonic can be written along with a directive command in the same line Example MOV W RTS MOV W RTS 0 RO main 0 A0 Comment Line Function This is the line in which only a comment is written Description method Always be sure to write a semicolon before the comment Example Comment line MOV W 0 A0 Blank Line Function This is the line in which no meaningful character is written Description method Write only a space tab or new line code in this line 100 Functions of Assembler 3 3 2 Method for Writing Source Program 3 2 2 Address Control The following explains the AS30 system address control method The AS30 system does not take the RAM and ROM sizes into account as it controls memory addresses Therefore consider the actual address range in your application when writing the source programs and linking them Method of Address Control The AS30 system manages memory addresses in units of sections The division of each section is defined as foll
61. EL2 Figure 4 6 1 Sample program for conditional branching based on specified bit status Retrieving Data Table MOV W 1 A0 LDE B DATA_TABLE A0 ROL Stores 2nd byte 34H of data table in ROL Performed by address register relative addressing Table data is retrieved by using the start address of the table as the base address and by placing a relative address from that location in the address registers AO A1 DATA_TABLE BYTE 12H 34H 56H 78H Sets 1 byte data Figure 4 6 2 Sample program for table retrieval 172 Programming Style 4 4 6 Sample Program Table Jump Using Argument Since 4 bytes is set for the jump address PARAMETER EQU 1 with LWORD the relative address value is quadrupled MOV W S Sets AO for argument SHL W Calculates offset value of jump table JSRI A Jump table indirect subroutine call Control jumps to the address indicated by a relative value argument from the base address that is the start address of the table where the jump address is set Program SUB1_END RTS Program SUB2_END RTS Program SUB3_END RTS Program f Set the start address of SUB4_END each subroutine in the table RTS in advance LWORD Routine 1 LWORD Routine 2 LWORD Routine 3 LWORD Routine 4 JUMP_TABLE_END Figure 4 6 3 Sample program for table jump using argument 173
62. FH FFFFFH Figure 2 5 27 Bit instruction address register indirect addressing Address Register Relative Operation is performed on the bit that is away from bit 0 at the address indicated by base by a number of bits indicated by the address register AO or A1 The address range that can be specified is an 8 Kbyte area 1FFFH from the address indicated by base However the range of effective addresses is 00000H to OFFFFH If the address of the bit to be operated on exceeds OFFFFH the most significant bits above and including bit 17 are ignored Symbol base 8 A0 base 16 A0 base 8 A1 base 16 A1 Example BCLR 5 A0 Effective address rang 0 to OFFFFH Specifiable address range up to 8 Kbytes from base Figure 2 5 28 Bit instruction address register relative addressing 41 CPU Programming Model 2 5 Addressing Modes SB Relative In this mode the address is referenced to the value indicated by the SB register The value of the SB register has base added without a sign The resulting value indicates the reference address so operation is performed on the bit that is away from bit 0 at that address by a number of bits indicated by bit The address range that can be specified is an 8 Kbyte area from the address indicated by the SB register However the range of effective addresses is 00000H to OFFFFH If the address of the bit to be operated on exceeds OFFFFH the most significant bits above and including bit 17 are i
63. G Generated when option T is specified This file contains error messages for errors that occurred when assembling the source file This file is not generated when no occur was encountered This file allows errors to be corrected easily when it is used an editor that has the tag jump function 175 Programming Style 4 4 7 Generating Object Files Method for Starting Up as30 gt as30 file name extension file name extension option Be sure to write at least one file name The extension A30 can be omitted Table 4 7 1 Command Options of as30 Command Option Inhibits assemble processing messages from being output Evaluates mnemonic operand Displays command options when as30 has started up mac30 and asp30 D symbol name Sets symbol constant constant F expansion file name Fixes expansion file of directive command FILE L L Generates assembler list file LI Outputs parts that were found false in conditional assemble to list also LM Outputs expansion parts of macro description to list also LIM Outputs parts that were found false in conditional assemble as well as expansion parts of macro description to list Generates structured description instruction in byte type Inhibits line information of macro description from being output to relocatable module file Specifies directory for file generated by assembler Do not insert space between the letter O and directory name
64. HIJKLMNOPQR STUVWXYZ Lowercase English alphabets abcdefghijklmnopqrstu VWXYZ Numerals 0123456789 Special characters S amp t 5 _ 7 Blank characters space tab New line characters return line feed 93 Functions of Assembler 3 3 2 Method for Writing Source Program Reserved Words The following lists the reserved words of the AS30 system The reserved words are not discriminated between uppercase and lowercase Therefore abs ABS Abs ABs AbS abS aBs aBS all are the same as the reserved word ABS Mnemonic ABS ADC ADCF ADD ADJNZ AND BCLR BMC BMEQ BMGE BMGEU BMGT BMLE BMLEU BMLT BMLTU BMN BMNC BMNO BMNZ BMO BMPZ BMZ BNAND BNOT BNTST BNXOR BOR BRK BSET BTSTC BISTS BXOR CMP DADC DADD DIV DIVU DIVX DSBB DSUB ENTER EXTS FCLR FSET INC INT INTO JEQ JGE JGEU JGT JGTU JLE JLT JLTU JMP JMPI JMPS JN JNE JNO JNZ JO JPZ JSR JSRS JZ LDC LDCTX LDE LDINTB MOV MOVA MOVHH MOVHL MOVLH MOVLL MULU NEG NOP NOT OR POP POPM PUSH PUSHA PUSHC PUSHM REIT ROLC RORC ROT RTS SBB SBJNZ SHL SMOVB SMOVF SSTR STC STCTX STNZ STZ STZX SUB TST UND XCHG XOR Register flag AO FLG PC R2 U SIZEOF TOPOF IF ELIF ELSE ENDIF FOR NEXT WHILE ENDW SWITCH CASE DEFAULT ENDS REPEAT UNTIL BREAK CONTINUE FOREVER System labels all names that begin with 94 Functions of Assembler 3 3 2 Method for Writing Source Program Description of Names Any desired names can be used in the source progra
65. IT Halt program Program can be restarted by interrupt or reset 62 CPU Programming Model 2 6 Instruction Set Addressing General instruction Special instruction Flag change Immediate 16 bit absolute Register direct Register indirect register direct register relative Control absolute register direct 32 bit register indirect Register relative 20 bit 32 bit 20 bit lected flag is cleared to 0 lected flag is set to 1 Flag changes only w FLG Returns to FLG state before interrupt request was accepted s The immediate can be specified using 8 bits t The range of immediate is 0 lt IMM lt 63 mu The immediate can be specified using 20 bits v The range of immediate is 0 lt IMM lt 7 w Any control register except PC register can be selected 63 CPU Programming Model 2 2 6 Instruction Set 2 6 2 Transfer and String Instructions Transfers normally are performed in bytes or words There are 14 transfer instructions available Included among these are a 4 bit transfer instruction that transfers only 4 bits a conditional store instruction that is combined with conditional branch and a string instruction that transfers data collectively This section explains these three characteristic instructions of the M16C 60 M16C 20 series among its data transfer related instruc
66. L Allocates a RAM area in units of 4 bytes BLKF Allocates a RAM area for floating point numbers in units of 4 bytes BLKD Allocates a RAM area in units of 8 bytes Write the number of areas to be allocated in the DATA section When defining a label name always be sure to add a colon Example BLKB 1 BLKW number BLKA number 1 BLKL 1 BLKF BLKD number number 1 BYTE Stores data in the ROM area in length of 1 byte WORD Stores data in the ROM area in length of 2 bytes ADDR Stores data in the ROM area in length of 3 bytes When writing multiple operands separate them with a comma When defining a label always be sure to add a colon For FLOAT and DOUBLE write a floating point number in the operand Example LWORD Stores data in the ROM area in length of 4 bytes FLOAT Stores a floating point number in the ROM area in length of 4 bytes DOUBLE Stores a floating point number in the ROM area in length of 8 bytes SECTION BYTE BYTE WORD ADDR LWORD FLOAT constant DOUBLE value ROMDATA 1 1 2 3 4 5 da ta symbol symbol 1 5E2 5e2 ALIGN Corrects odd addresses to even addresses 109 This command can be written in the relative or absolute attribute section where address correction is specified when defining a section Example SECTION program CODE 0 RO Functions of Assembler 3
67. M16C 60 Group M16C 61 Group M16C 62 Group M16C 20 Group M16C 21 Group Table of contents Chapter 1 Overview of M16C 60 M16C 20 Series 1 1 Features of M16C 60 M16C 20 Series cc sscsccecceseeeeensenssnesscaneeeseseeeeenssnsessssoansaeaeseeeeeneennees 2 1 2 Outline Of M16C 60 M16C 20 Group eccceeeseeeeeseeeenneeeeeeneensaaeeeneeeeesaaeseneeeeeseaesseseeeesenesseseeneeees 3 1 3 Introduction to CPU Architecture cccccccssscsssnsedcsssssscssssnsnsnsnssnsesncedereusceedecencnecsicensusacnsassesesenenees 5 Chapter 2 CPU Programming Model 2 TEE 10 2 1 1 Operation Modes and Memory Mapping isisisi 10 A GOP ACA EE 12 21 3 Feed Vector Ane aiicacicctiscsinies egege Eege ege Sege ASSEN dee Seefe 15 E UE Ben neo en E ee ener 16 2 3 Data TYPOS ees 21 2 4 Data Arrangement cseeccecceeeeeeeeeeeeeeseeeeeneeeseeeenneeseeeesneee sess nneeseeeesnneeseeeenueeesesesnnaeseesesneneseesennaes 23 2 5 Addressing MOS og EENS cteceevecetervacdyecenudeesttvercueced cradvesdecceectdareruereetuee 24 201 Typos or Addressing Wel TE 24 2 5 2 General Instruction Addressing cccceceeeeeeeeeeeeeeeceeeeeeeaeeeceeeeecaaeeeseeeeescaeeeseaeeeseaeeeseaeeseaees 25 2 5 39 Special Instruction Address Monnan a aai dd uge 34 2 5 4 Bit Instruction Addressing cccceeceeeeeeeeeeeeeeeaeeeeeaeeeceaeeeeeaaeeseeeeeesaaeeseneeeseaaeeeseaeeeseeeeseeeete 39 2 920 IMSTMUCUION ee CEET 46 26r lu E de ue GE 47 2 6 1 ln Et euer EE 4
68. Note The displacement dsp refers to a displacement from the reference address In this manual 8 bit dsp is expressed as dsp 8 and 16 bit dsp is expressed as dsp 16 27 CPU Programming Model 2 5 Addressing Modes SB Relative The value of the SB register plus dsp is the effective address to be operated on The range of effective addresses is 00000H to OFFFFH If the addition result exceeds OFFFFH the most significant bits above and including bit 17 are ignored Symbol dsp 8 SB dsp 16 SB Example MOV B 12H 5 SB Relative address range Onis 0 to FFFFH 00105H FFFFFH Figure 2 5 6 SB relative addressing 28 CPU Programming Model 2 2 5 Addressing Modes FB Relative The value of the FB register plus dsp is the effective address to be operated on The range of effective addresses is 00000H to OFFFFH If the addition result exceeds OFFFFH the most significant bits above and including bit 17 are ignored Symbol dsp 8 FB 1 When dsp is a positive value Example MOV B 12H 5 FB pm 01000H Relative address range FB _1000H 5 01005H EECH 0 to 127 01005H FFFFFH Figure 2 5 7 FB relative addressing 1 Relative address range FB 1000H 5 OOFFBH 128 to 0 OOFFBH 2 When dsp is a negative value Example MOV B 12H 5 FB p gt 01000H FFFFFH Figure 2 5 8 FB relative addressing 2 29 CPU Programming Model 2 5 Addressing Modes Column Difference between SB Relative and FB
69. PU Programming Model 2 5 Addressing Modes Column Relationship between Number of Bits and Address To get an address from a number of bits it is necessary to convert the number of bits into a number of bytes and number of bits first For this conversion the number of bits is divided by 8 because one byte is eight bits This is shown in Figure 2 5 31 The conversion is accomplished by shifting the bit train right by three bits so that 1234H bits are changed to 246H bytes 4 bits as shown below Figures 2 5 32 through 2 5 34 show examples of main addressing calculations 1i 2 3i 4 ololo i olo i o o o 1 i lofi o o 12347 l Bits Shifted right by three bits 0 2 4 6 i 4 0 of of oa ojojoj Jo 1foj 0 246H 4 bits l T Bytes Bit position Figure 2 5 31 Conversion from a number of bits to address 1 Address register indirect Example BCLR A0 Address 1234H Address Bit Bit position Bit 5 is cleared position ti 2 3 4 i 5 ao 1fojoj1fofojoj1f1 fol 1 of o 1 0 1 A0 91A5H l sk Figure 2 5 32 Calculation of bit position in address register indirect addressing 2 Address register relative Example BCLR 5 A0 AO is a number of bits dsp is an address Therefore the bit train is shifted right by three bits to obtain a number of bytes or an address 1 2 3 i 4 5 Ao Dog 4 0 0 0 4 1 0 1 oo 1 of 1 A0 91A5H 0 5 dsp8 O O O O O o 7 as
70. Processor interrupt priority level Levels 0 to 7 larger the number higher the priority Saves 4 high order bits of PC when interrupt occurs Stack pointer select flag ISP when U 0 USP when U 1 Interrupt enable flag Enabled when 1 Overflow flag 0 1 when overflow occurs Register bank select flag Register bank 0 when B 0 register bank 1 when B 1 Sign flag S 1 when operation resulted in negative S 0 when positive Zero flag Z 1 when operation resulted in zero Debug flag Program is single stepped when D 1 Carry flag carry or borrow 2 OON more Overview of M16C 60 M16C 20 Series 1 3 Introduction to CPU Architecture Addressing Modes There are three types of addressing modes 1 General instruction addressing A 64 Kbyte area 00000H to OFFFFH is accessed 2 Special instruction addressing A 1 Mbyte area 00000H to FFFFFH is accessed 3 Bit instruction addressing A 64 Kbyte area 00000H to OFFFFH is accessed in units of bits Table 1 3 2 lists the M16C 60 M16C 20 series addressing modes that can be used in each type of addressing described above Table 1 3 2 Addressing Modes of M16C 60 M16C 20 Series Item Content Addressing mode General instruction Special instruction Bit instruction Immediate O imm 8 16 bits D Register direct O Data and address O R2RO0 or R3R1 or A1A0 registers only SHL SHA JMPI and JSRI
71. Program counter low PC i SP Stack pointer after m 3 Program counter middle PCy interrupt is accepted m 2 Flag register low FLG Flag register Program counter m 1 high FLG4 high PC Stack pointer m before interrupt occurs Figure 4 5 1 Saving and restoring to from stack when interrupt is accepted 2 When subroutine is called when JSR JSRI or JSRS instruction is executed When the JSR JSRI or JSRS instruction is executed the following register is saved to the stack area Program counter PC gt 3 bytes Total 3 bytes After subroutine execution is completed the above register that has been saved to the stack area is restored from the stack by the RTS instruction Stack area m 3 Program counter low PC e SP Stack pointer after m 2 Program counter middle DC subroutine is called m 1 Program counter high PCy subroutine is called Figure 4 5 2 Saving and restoring to from stack when subroutine is called 165 Programming Style 4 4 5 A Little Tips 4 5 2 Setup Values of SB and FB Registers The following explains the setup values of the SB and FB registers General Setup Values of SB and FB Registers Setting the start addresses of the areas that contain frequently accessed data in the SB and FB registers should prove effective Therefore it is advisable to set the start address of the SFR or the work RAM area in these registers Figure 4 5 3 shows an examp
72. Programming Style 4 4 7 Generating Object Files 4 7 Generating Object Files The AS30 system is a program development support tool consisting of an assembler as30 linkage editor In30 load module converter Imc30 and other tools lb30 abs30 and xrf80 This section explains how to generate object files using the AS30 system a30 Assembly source file Assembler list file Relocatable module file Cross reference file A Input file Output file Absolute module file Absolute list file Motorola S format Intel HEX format file J file Figure 4 7 1 Outline of processing by AS30 Note In this manual the AS30 system is referred to by AS30 system uppercase when it means the entire system or by as30 lowercase when it means only the assembler as30 174 4 Programming Style 4 7 Generating Object Files 4 7 1 Assembling The following explains the files generated by the relocatable assembler as30 and how to start up the assembler Files Generated by as30 1 Relocatable module file R30 Generated as necessary This file is based on IEEE 695 It contains machine language data and its relocation information 2 Assembler list file LST Generated when option L is specified This file contains list lines location information object code and line information It is used to output these pieces of information to a printer 3 Assembler error tag file TA
73. Register Set Flag Register FLG Figure 2 2 2 shows the bit configuration of the flag register FLG The function of each flag is described below e Bit 0 Carry flag C flag This bit holds a carry or borrow that has occurred in an arithmetic logic operation or a bit that has been shifted out e Bit 1 Debug flag D flag This flag enables a single step interrupt When this flag is 1 a single step interrupt is generated after instruction execution When the interrupt is accepted this flag is cleared to 0 Bit 2 Zero flag Z flag This flag is set to 1 when the operation resulted in 0 otherwise the flag is 0 Bit 3 Sign flag S flag This flag is set to 1 when the operation resulted in an negative number The flag is O when the result is positive Bit 4 Register bank specifying flag B flag This flag chooses a register bank Register bank 0 is selected when the flag is 0 Register bank 1 is selected when the flag is 1 Bit 5 Overflow flag O flag This flag is set to 1 when the operation resulted in an overflow Bit 6 Interrupt enable flag I flag This flag enables a maskable interrupt The interrupt is enabled when the flag is 1 and is disabled when the flag is 0 This flag is cleared to 0 when the interrupt is accepted Bit 7 Stack pointer specifying flag U flag The user stack pointer USP is selected when this flag is 1 The interrupt stack pointer ISP is selected when the flag is 0 This flag is cle
74. SR instructions 1 When jump distance specifier length is S Symbol label PC 2 lt label lt PC 9 Instruction Relative range 1 Mbytes of 2 to 9 i memory Space Figure 2 5 20 PC relative addressing 1 2 When jump distance specifier length is B Symbol label PC 128 lt label lt PC 127 00000H label Relative address 128 to 0 Instruction Instruction 1 Mbytes of Relative memory space address label range 0 to 127 FFFFFH Figure 2 5 21 PC relative addressing 2 3 When jump distance specifier length is W Symbol label PC 32768 lt label lt PC 32767 Relative el address range D SSES Mbytes of Instruction Relative memory space 0 to 32767 Figure 2 5 22 PC relative addressing 3 38 CPU Programming Model 2 2 5 Addressing Modes 2 5 4 Bit Instruction Addressing In this mode an address space from 00000H to OFFFFH is accessed in units of bits This addressing is used in bit manipulating instructions This section explains each addressing in the bit instruction addressing mode Absolute Operation is performed on the bit that is away from bit 0 at the address indicated by base by a number of bits indicated by bit The range of addresses that can be specified is 00000H to 01FFFH Symbol bit base16 Specifiable address range 0 to 01FFFH Figure 2 5 23 Bit instruction absolute addressing 1 Example 1 BCLR 18 base_addr Example 2 BCLR 4 b
75. Setting Interrupts 4 3 3 Enabling Interrupt Enable Flag Since interrupts are disabled immediately after power on or after a reset is deactivated they must be enabled in the program This can be accomplished by setting the flag register flag to 1 Interrupts are enabled the moment the flag is set to 1 If interrupts are enabled at the beginning of the program the program could run out of control To prevent this problem be sure to initial set the CPU internal resources before enabling interrupts 4 3 4 Setting Interrupt Control Register Bits 0 to 2 in each interrupt control register can be used to set the interrupt priority level of each interrupt Level 0 results in the interrupt being in effect disabled Therefore set a level that is equal to or greater than 1 Bit 3 of the interrupt control register is the interrupt request flag Although this flag is cleared to 0 after a reset is deactivated there is a possibility that the flag remains set 1 For safety reason therefore clear this flag to 0 before enabling the interrupt enable flag I flag For the bit arrangement of each interrupt control register priority levels and other details refer to the user s manual of your microcomputer 144 Programming Style 4 4 3 Setting Interrupts 4 3 5 Saving and Restoring Registers in Interrupt Handler Routine When an interrupt is accepted the following resources are automatically saved to the stack For details on how they are sa
76. These symbols are written as terms of an expression in macro description e Character string functions These functions show information on a character string Macro Directive Commands Usage and Description Example Defines a macro name and Always be sure to write a conditional expression indicates the beginning of macro in the operand Up to 80 dummy arguments can definition be written Do not enclose a dummy argument with double quotations lt Description format gt Macro definition macro name MACRO dummy argument dummy argument Macro call macro name actual argument actual argument lt Description example gt Refer to Figure 3 2 5 Indicates the end of macro Write this command in relation to MACRO definition lt Description example gt Refer to Figure 3 2 5 Declares that the label shown in Write this command within the macro body the operand is a macro local label Multiple labels can be written by separating operands with a comma The maximum number of labels that can be written in this way is 100 lt Description example gt Refer to Figure 3 2 6 Forcibly terminates expansion of Write this command within the body of macro a macro body definition lt Description example gt Refer to Figure 3 2 7 MREPEAT Indicates the beginning of repeat The maximum number of repetitions is 65 535 macro definition lt Description example gt Refer to Figure 3 2 7 Indicates the end of
77. ack pointer ISP e Multiple interrupts are disabled e Debug mode is cleared program is not single stepped c The content of the temporary register in the CPU to which FLG has been saved and that of the PC register are saved to the stack area d The interrupt request bit for the accepted interrupt is reset to 0 e The interrupt priority level of the accepted interrupt is set to the processor interrupt priority level IPL f The address written in the interrupt vector is placed in the PC register lt Stack status after interrupt request is accepted gt PC middle FLG lower S Ir PC s 4 most significant bits are stored here lt FLG status after interrupt request is accepted gt AEE Eee rier No change Priority level of each accepted interrupt is stored here Figure 4 3 5 When an interrupt of software interrupt number 0 to 31 occurs 151 Programming Style 4 4 3 Setting Interrupts 2 When an interrupt of software interrupt number 32 to 63 occurs a The content of the FLG register is saved to a temporary register in the CPU b The and D flags of the FLG register are cleared By operation in b e The stack pointer used in this case is one that was active when the interrupt occurred e Multiple interrupts are disabled e Debug mode is cleared program is not single stepped c The content of the temporary register in the CPU to which FLG has been saved and that of the PC register are
78. ag is used to determine whether the condition is true or false This instruction must be preceded by an instruction that causes the flag to change Figure 2 6 13 shows an example of how the conditional bit transfer instruction works Table 2 6 13 Conditional Bit Transfer Instruction Mnemonic Description Format Explanation BMCnd_ dest BMCnd C Transfers a 1 if condition is true or a 0 if condition is false True false determining conditions 14 conditions C 1 Equal or greater Carry flag 1 C 1 amp Z 0 Unsigned and greater Z i Equal Zero flag 1 S 1 Negative Z 1 S 1 amp O 0 S 0 amp 0 1 Equal or signed and smaller O 1 Overflow flag 1 S 18 amp 0 1 S 08 amp 80 0 Equal or signed and greater LTU NC C 0 Smaller Carry flag 0 LEU C 0 Z 1 Equal or smaller NE NZ Z 0 Not equal Zero flag 0 PZ S 0 Positive or zero GT S 18 amp 0O Signed and greater NO O 0 1 amp Z 0 S 0 amp O 0 amp Z 0 LT S 1 amp O 0 S 0 amp 0 1 BMGEU 3 1000H SB If SB and FLG register status is as follows 13 12 LO BSZ D U ne lolololo alalololololololol o 00000H sB 0500H 1000H 01500H FFFFFH b7 T bO nmn DSDS Overflow flag 0 Signed and smaller Since C 1 the condition is true Therefore bit 3 at address 01500H is set to 1
79. and LIST OFF at the beginning and end of an include file it is possible to inhibit the include file from being output to an assembler list file Figure 4 4 6 shows examples of assembler list files one not using these directive commands expansion 1 and one using them expansion 2 Source file SYMBOL INC INCLUDE SYMBOL INC LIST OFF SECTION WORK DATA ON EQU 1 A OFF EQUO RAMTOP EOU 00400H HAMEND EQU 02BFFH LIST ON N aam 2 wn C 2 gt x lt Ke When not using directive command When using directive LIST command LIST INCLUDE SYMBOL INC INCLUDE SYMBOL INC ON EQU 1 LIST OFF OFF EQU 0 LIST ON RAMTOP EQU 00400H HAMEND EQU 02BFFH SECTION WORK DATA SECTION WORK DATA Figure 4 4 6 Utilization of directive command LIST 161 A Programming Style 4 4 Dividing Source File A library file refers to a collection of several relocatable module files If there are frequently used modules collect them in a single library file using the librarian lib30 that is included with the AS30 system When linking source files specify this library file LIB By so doing only the necessary modules those specified in the file as externally referenced can be extracted when linking This makes it possible to reduce the assemble time and reuse the program The following shows an example of how a library file is created an
80. ands of the assembler refer to Chapter 3 Functions of Assembler If you want to know practical techniques refer to Chapter 4 Programming Style The instruction set of the M16C 60 M16C 20 series is detailed in M16C 60 M16C 20 Series Software Manual Refer to this manual when the knowledge of the instruction set is required For information about the hardware of each type of microcomputer in the M16C 60 M16C 20 series refer to the user s manual supplied with your microcomputer For details about the development support tools refer to the user s manual of each tool Guide to Using This Manual This manual is an assembly language programming manual for the M16C 60 M16C 20 series This manual can be used in common for all types of microcomputers built the M16C 60 series CPU core This manual is written assuming that the reader has a basic knowledge of electrical circuits logic circuits and microcomputers This manual consists of four chapters The following provides a brief guide to the desired chapters and sections e To see the overview and features of the M16C 60 M16C 20 series Chapter 1 Overview of M16C 60 M16C 20 Series e To understand the address space register structure and addressing and other knowledge required for programming Chapter 2 CPU Programming Model e To know the functions of instructions the method for writing instructions and the usable addressing modes Chapter 2 CPU Programming Model 2
81. ared to 0 when a hardware interrupt is accepted or an INT instruction of software interrupt numbers 0 to 31 is executed Bits 8 to 11 Reserved Bits 12 to 14 Processor interrupt priority level IPL The processor interrupt priority level IPL consists of three bits specifying the IPL in eight levels from level 0 to level 7 If the priority level of a requested interrupt is greater than the IPL the interrupt is enabled e Bit 15 Reserved CPU Programming Model 2 2 2 Register Set Flag Register FLG Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 2 2 2 Bit configuration of flag register FLG CPU Programming Model 2 2 2 Register Set Register Status after Reset is Cleared Table 2 2 1 lists the status of each register after a reset is cleared See Note below Table 2 2 1 Register Status after Reset Cleared Register Name Status after Reset is Cleared Data registers RO R1 R2 R3 0000H Address registers A0 A1 0000H Flag register FLG Note For the control register status in the SFR area after a reset is cleared refer to the M16C 60 group data sheets and user s manuals 20 CPU Programming Model 2 2 3 Data Types 2 3 Data Types There are four data types handled by the M16C 60 M16C 20 series integer decimal BCD string and
82. ase_addr2 Example 3 10 base_addr2 Example 3 cannot be specified bO gs base_addr 00000H 7 0 Specifiable 00001H 8 address range 0 to 01FFFH This bit is cleared Example 1 This bit is cleared Example 2 This bit cannot be specified Example 3 Figure 2 5 24 Bit instruction absolute addressing 2 39 CPU Programming Model 2 2 5 Addressing Modes Register Direct In this mode a bit of a 16 bit register RO R1 R2 R3 AO or A1 is specified directly A number from 0 to 15 is used to specify the bit position Symbol bit RO bit R1 bit R2 bit R3 bit AO bit A1 Example BCLR 6 RO This bit is cleared Figure 2 5 25 Bit instruction register direct addressing FLG Direct This addressing can be used in FCLR and FSET instructions The bit positions that can be specified here are only the 8 low order bits of the FLG register Symbol U I O B S Z D C Example FSET U U flag is set Figure 2 5 26 Bit instruction FLG direct addressing 40 CPU Programming Model 2 5 Addressing Modes Address Register Indirect Operation is performed on the bit that is away from bit O at address 00000H by a number of bits indicated by the address register AO or A1 The range of addresses that can be specified is 00000H to 01FFFH Symbol A0 A1 Example BCLR A0 00000H Specifiable address range 0 to 01FFFH 01FF
83. ative addressing 2 32 CPU Programming Model 2 5 Addressing Modes Column Relative Address Ranges of Relative Addressing The relative address ranges of relative addressing are summarized in Table 2 5 2 Table 2 5 2 Relative Address Ranges of Relative Addressing Addressing Mode Description Format Address register dsp 8 An relative dsp 16 An dsp 20 An Note Relative Range 0 to 255 0F FH 0 to 65535 0FFFFH 0 to 1048575 0F FFFFH SB and FBrelative dsp 8 SB dsp 16 SB dsp 8 FB Oo 255 0FFH 0 to 65535 0FFFFH 128 80H to 127 7FH Stack pointerrelative dsp 8 SP Note dsp 20 An can be used in LDE STE JMPI and JSRI instructions 33 128 80H to 127 7FH CPU Programming Model 2 2 5 Addressing Modes 2 5 3 Special Instruction Addressing In this addressing mode an address space from 00000H to FFFFFH can be accessed This section explains each addressing in the special instruction addressing mode 20 Bit Absolute A specified 20 bit value is the effective address to be operated on The range of effective addresses is 00000H to FFFFFH This 20 bit absolute addressing can be used in LDE STE JMP and JSR instructions Symbol abs20 Example LDE B DATA ROL RO XXH 55H y DATA 30000H 1 Mbytes of memory space FFFFFH Figure 2 5 14 20 bit absolute addressing 34 CPU Programming Model 2 2 5 Addressing Modes 32 Bit Register Direc
84. broutine 58 CPU Programming Model 2 6 Instruction Set Addressing General instruction Flag change op O O Q v 5 D o CG O E O 5 register direct register indirect register relative register direct 16 bit absolute Register direct Register indirect Register relative 32 bit 20 bit Immediate 32 bit label label 9 label dsp 20 A0 label dsp 20 A0 The range of immediate is 8 lt IMM lt 7 The range of immediate is 7 lt IMM lt 8 The immediate is 8 bits The range of label is PC 126 lt label lt PC 129 If condition is LE O GE GT NO or LT the range of label is 126 lt label lt PC 129 Otherwise the range is 127 lt label lt PC 128 r The range of label is PC 32 767 lt label lt PC 32 768 t 4 WK EE 59 CPU Programming Model 2 2 6 Instruction Set String Mnemonic Explanation Write W or B for size String transfer in decrementing address direction using R1H and AO as source SMOVB Size address A1 as destination address and R3 as transfer count String transfer in incrementing address direction using R1H and AO as source SMOVF size address A1 as destination address and R3 as transfer count String store in incrementing address direction using RO as transfer data A1 as
85. d by WORK 3 BLKB BTEQU to be referenced from WORK 4 BLKB another file declare global symbols using BTGLB GLOBAL_WORK_END WI b BTEQU 0 WORK_1 Defines bit symbols BTEQU 1 WORK_2 SECTION CONSTANT ROMDATA ORG CONST_TOP DATA_TABLE BYTE Sets 1 byte data BYTE BYTE BYTE DATA_TABLE_END H END Figure 4 4 2 Divided file 1 WORK A30 157 Programming Style 4 4 4 Dividing Source File Division Example 2 Main Program MAIN A30 Write the main program in file 2 RK RK KK KKK RK KK KKK KK KKK IK IKK RIK KK KK KKK KKK KK IKK KK KK KKK KKK KEK KERR KK KEKE KKK RK D File 2 MAIN A2 Because labels are defined in i another file specify external reference using GLB skkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Declaration to assembler s Because bit symbols are defined in another file SECTION PROGRAM CODE specify external reference using BTGLB GLB WORK_1 WORK_2 WORK_3 WORK Processed as external reference label GLB SUB_1 Processed as external reference label BTGLB W1_b0 W2_b1 Processed as external reference bit symbol SB 00380H Sets SB register value for assembler FB 00480H Sets FB register value for assembler SBSYM WORK_1 WORK_2 Encodes specified labels in SB relative addressing mode FBSYM WORK_3 WORK_4 Encodes specified labels in FB relative addressing mode OPTJ JSRW Generates subroutine call instructions that are
86. d for Writing Source Program Link Control Usage and Description Example SECTION Defines a section name When specifying section type and ALIGN simultaneously separate them with a comma The section type that can be written here is CODE ROMDATA or DATA If section type is omitted CODE is assumed Example SECTION NOP SECTION ram DATA BLKB 10 SECTION dname ROMDATA BYTE abcd END program CODE Specifies a global label Specifies a global bit symbol When writing multiple symbol names in operand separate them with a comma Example GLB BTGLB SECTION MOV W BCLR name1 name2 mane3 flag4 program 0 name1 flag4 Outputs a specified character string to a map file as version information 111 Write operands within one line This command can be written only once in one assembly source file Example VER VER strings strings Functions of Assembler 3 2 Method for Writing Source Program List Control Usage and Description Example Controls line data output to a list file Write OFF in the operand to stop line output or ONT to start line output If this specification is omitted all lines are output to the list file Example LIST OFF MOV B MOV B MOV B ON 0 ROL 0 ROL 0 ROL LST Breaks page at a specified position in a list file Enclose the operand with single or double quotations when writing it The operand can be omit
87. d how it is linked Creating Library File Figure 4 4 7 shows an example of how a library file is created Module 1 Module 2 Module 3 Relocatable module file SUB1 R30 SUB2 R30 SUB3 R30 Library file lt Librarian lib30 LIB1 LIB Edited into a single library file SUB1 R30 SUB2 R30 SUB3 R30 Figure 4 4 7 Creating a library file 162 Programming Style 4 4 Dividing Source File Example for Linking Library Files Figure 4 4 8 shows an example of how library files are linked FILE1 A30 JSR SUB1 JSR SUB3 JSR SUBS Assemble as30 FILE1 R30 LIB1 LIB LIB2 LIB LIB3 LIB SUB1 R30 SUB3 R30 SUB5 R30 SUB2 R30 SUB4 R30 SUB6 R30 FILE1 X30 Relocatable modules required in FILE1 are retrieved from specified library files to link only the necessary modules Load module convert Imc30 FILE1 MOT FILE1 HEX Wa Figure 4 4 8 Example for linking library files and relocatable module file 163 Programming Style 4 4 5 A Little Tips 4 5 A Little Tips This section provides some information knowledge of which should prove helpful when using the M16C 60 series This information is provided for several important topics so refer to the items in interest 4 5 1 Stack Area The following explains how to set up stack pointers and how to save and restore to and from the stack area when using an interrupt and a subroutine Setting Up Stack Pointers ISP USP a Choosing the stack pointer
88. d in one clock period For this reason it is possible to write a high speed processing program The M16C 60 M16C 20 series provides 1 Mbytes of linear addressing space Therefore the M16C 60 M16C 20 series is also suitable for applications that require a large program size The features of the M16C 60 M16C 20 series can be summarized as follows The M16C 60 M16C 20 series allows you to create a memory efficient program without requiring a large memory capacity The M16C 60 M16C 20 series allows you to create a high speed processing program The M16C 60 M16C 20 series provides 1 Mbytes of addressing space making it suitable for even large capacity applications 1 2 Outline of M16C 60 M16C 20 M16C 20 Group This section explains the M16C 60 group as a typical internal structure of the M16C 60 series and M16C 20 group as a typical internal structure of the M16C 20 series The M16C 60 M16C 20 group is a basic product of the M16C 60 M16C 20 series For details about this product refer to the data sheets and user s manuals Overview of M16C 60 Series 1 1 2 Outline of M16C 60 Group M16C 20 Group Internal Block Diagram Figure 1 2 1 shows a block diagram of the M16C 60 group 1 M16C 60 group t CF y Y UO ports _ Port Po Port P3 Port P4 Internal peripheral functions System clock generator XIN XOUT XCIN XCOUT A D converter 10 bits x 8 channels Ld
89. dress OO3FFH and expands toward smaller addresses Addresses following 00400H constitute the memory area The memory area in each type of M16C 60 group microcomputer consists of a RAM area which begins with address 00400H and expands toward larger addresses and a ROM area which begins with address FFFFFH and expands toward smaller addresses However addresses FFEOOH to FFFFFH are the fixed vector area 00000H e N Direction in which Gen SFR area J SFR area expands 00400H Direction in which Internal RAM internal RAM OFFFFH eem expands 10000H External memory area Internal ROM area FFFFFH D a Figure 2 1 1 Address space internal ROM Direction in which expands CPU Programming Model 2 2 1 Address Space Operation Modes and Memory Mapping e Single chip mode In this mode only the internal areas SFR internal RAM and internal ROM can be accessed e Memory expansion mode In this mode the internal areas SFR internal RAM and internal ROM and an external memory area can be accessed e Microprocessor mode In this mode the SFR and internal RAM areas and an external memory area can be accessed The internal ROM area cannot be accessed Figure 2 1 2 shows the M16C 60 group memory mapping in each operation mode C Internal area aed poate Rae ce External area using external memory chips Cannot be used ROM 64 Kbytes RAM 10 Kbytes 00400H Internal RAM area Internal RAM area Interna
90. dule file Library list file Cross reference file Absolute list file Functions of Assembler 3 3 2 Method for Writing Source Program 3 2 Method for Writing Source Program This section explains the basic rules address control and directive commands that need to be understood before writing the source programs that can be processed by the AS30 system For details about the AS30 system itself refer to AS30 User s Manuals Operation Part and Programming Part 3 2 1 Basic Rules The following explains the basic rules for writing the source programs to be processed by the AS30 system Precautions on Writing Programs Pay attention to the following precautions when writing the source programs to be processed by the AS30 system e Do not use the AS30 system reserved words for names in the source program e Do not use a character string consisting of one of the AS30 system directive commands with the period removed because such a character string could affect processing by AS30 They can be used in names without causing an error e Do not use system labels the character strings that begin with because they may be used for future extension of the AS30 system When they are used in the source program created by the user the assembler does not output an error Character Set The characters listed below can be used to write the assembly program to be processed by the AS30 system Uppercase English alphabets ABCDEFG
91. e SHA size src dest src dest Rotates dest the number of bits specified by src Numerically shifts dest the number of bits specified by src SHL size src dest Logically shifts dest the number of bits specified by src 56 CPU Programming Model 2 6 Instruction Set Addressing General instruction Special instruction Flag change register direct register indirect register relative register direct Immediate 32 bit 16 bit absolute Register direct Register indirect Register relative absolute 32 bit Control 20 bit 20 bit O O O0 O 0 O0 0 0 10 oioloioloiololoio o olo olo ololoio oioloioloiololoio Addressing Flag change General instruction Special instruction 7 Immediate register direct Register direct Control o ololo k The range of values that can be used for the immediate is 8 lt IMM lt 8 However 0 cannot be used R2R0 or R3R1 is selected 57 Jump Write W or B for size Mnemonic ADJNZ size src dest label CPU Programming Model 2 6 Instruction Set Explanation dest lt dest src If result of dest src is not 0 jump to label Add and conditional branch SBJNZ size src dest label dest lt dest src If result of dest src is not 0 jump to label Subtract and conditi
92. e vector table FFFDCH Undefined instruction nterrupt FFFEOH E Overflow INTO instruction vector table FFFE4H EBRK instruction FFFE8H E address match FFFECH Single step PEREON Watchdog timer ies FFFF8H FFFFCH Figure 2 1 6 Memory mapping in fixed vector area CPU Programming Model 2 2 2 Register Set 2 2 Register Set This section describes the general purpose and control registers of the M16C 60 series CPU core Register Structure Figure 2 2 1 shows the register structure of the M16C 60 series CPU core Seven registers RO R1 R2 R3 AO A1 and FB are available in two sets each The following shows the function of each register General purpose registers 1 Data registers RO R1 R2 R3 These registers consist of 16 bits each and are used mainly for data transfer and arithmetic logic operations Registers RO and R1 can be used separately for upper bytes ROH R1H and lower bytes ROL R1L as 8 bit data registers For some instructions registers R2 and RO and registers R3 and R1 can be combined for use as 32 bit data registers R2RO R3R1 respectively 2 Address registers AO A1 These registers consist of 16 bits and have the functions equivalent to those of the data registers In addition these registers are used in address register indirect addressing and address register relative addressing For some instructions registers A1 and AO can be combined for use as a 32 bit address register A1A0
93. e assembly source file and performs preprocessing for the assembly processor thereby generating an intermediate file This intermediate file is erased after processing by the assembler processor is completed e Assembler processor asp30 This program converts the intermediate file generated by the macroprocessor into a relocatable module file e Linkage editor In30 This program links the relocatable module files generated by the assembler processor to generate an absolute module file e Load module converter Imc30 2 This program converts the absolute module file generated by the linkage editor into a machine language file that can be programmed into ROM e Librarian lb30 By reading in the relocatable module files this program generates and manages a library file e Cross referencer xrf30 This program generates a cross reference file that contains definition of various symbols and labels used in the assembly source file created by the user e Absolute lister abs30 Based on the address information in the absolute module file this program generates an absolute list file that can be output to a printer Note 1 IEEE stands for the Institute of Electrical and Electronics Engineers Note 2 The load module converter is a program to convert files into the format in which they can be programmed into M16C 60 M16C 20 series ROMs 90 Functions of Assembler 3 1 Outline of Interrupt Outline of Processing by AS30 System Fig
94. e source file name Error line number Error message smp inc 2 Warning In30 smp2 r30 Absolute section is written after the absolute section ppp smp inc 2 Error In30 smp2 r30 Address is overlapped in CODE section ppp Figure 4 7 3 Example of link error tag file Note Absolute module files are output in the format based on IEEE 695 Since this format is binary the files cannot be output to the screen or printer nor can they be edited 182 Programming Style 4 4 7 Generating Object Files Map File Figure 4 7 4 shows an example of a map file ERE AEE EEE EEE EEE 1 LINK INFORMATION FERRE HAE EEE EEE EEE EH In30 ms smp LINK FILE INFORMATION smp smp r30 Jun 27 14 58 58 1995 EE 2 SECTION INFORMATION FE ARRANA AHHAA HHRRHHHH SECTION ram REL DATA 000000 000014 program REL CODE 000014 000000 HAHAHAHA 3 GLOBAL LABEL INFORMATION HAHA work 000000 HERE A HAHAHA AHAHA HHHH HHHHH 4 GLOBAL EQU SYMBOL INFORMATION A AE EET EE sym2 000000 EEE AEE EEE AEE EEE at 5 GLOBAL EQU BIT SYMBOL INFORMATION EERE ETE EEE AE EEE HAHAHAAH HAHHHHRHHHH sym1 1 000001 EERE TEE EEE AE EEE a 6 LOCAL LABEL INFORMATION REE EEE EEE AE EEE EE AHAHAH HHHHHHHH smp smp rs0 main 000014 tmp 00000a HEE EE A AHAHAH HHHHHHHH 7 LOCAL EQU SYMBOL INFORMATION HERE A HAHAHAHAHA HHHHHHHHH smp smp r30 sym3 00000003 HBB ABBE HE AEE AEE EH AEE
95. ears WORK_RAM to 0 MOV W RAM_END RAM_TOPY 2 R3 MOV W WORKRAM_TOP A1 SSTR W MAIN JSR INIT Sets initial value in work RAM FSET Enables interrupts MAIN_10 MOV B WORK_1 ROL JMP MAIN 10 jecseseescemes NIT TOP INIT MOV B 0FFH WORK_1 MOV B 0FFH WORK_2 MOV B 00000111B TAOIC Clears interrupt request bit Enables timer AO interrupt priority level 7 MOV B 01000000B TAOMR Sets timer AO mode register MOV W 2500 1 TAO Sets count value in timer AO BSET 0 TABSR Timer AO starts counting INIT_END RTS TAQ interrupt processing program INT_TAO PUSHM RO R1 R2 R3 A0 A1 Program POPM RO R1 R2 R3 A0 A1 INT_TAO_END REIT Dummy interrupt program s dummy 140 H Programming Style 4 2 Initial Setting the CPU ER of variable vector eler SECTIONVECT ROMDATA ORG LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD H VECT_TOP 11 4 dummy DMAO interrupt vector dummy DMA interrupt vector dummy Key input interrupt vector dummy A D interrupt vector dummy Unused dummy Unused dummy UARTO transmit interrupt vector dummy UARTO receive interrupt vector dummy UART1 transmit interrupt vector dummy UART1 receive interrupt vector INT_TAO Sets jump address in timer AO
96. ed DMAO source pointer DMAO destination pointer DMAO transfer counter 7 DMADO control register l DMA1 source pointer l DMA1 destination pointer l DMA1 transfer counter DMA1 control register Figure 4 1 2 Example of SFR area definition by BLKB 127 Programming Style 4 4 1 Hardware Definition Creating Include File When creating the source program in separate files create an include file for SFR definition and other parts that are used by multiple files Normally add an extension INC for the include file Precautions on creating include file 1 When using EQU in include file Directive command EQU defines values for symbols It can also be used to define addresses as in SFR definition However since this is not a command to allocate memory areas make sure that the addresses defined with it will not overlap The include file created using EQU can be used in multiple files by reading it in When using ORG in include file If an include file created using ORG is read into multiple files a link error will result This is because the include file contains the absolute addresses specified by ORG Consequently the defined addresses overlap with each other When using BLKB BLKW and BLKA in include file Directive commands BLKB BLKW and BLKA are used to allocate memory areas If an include file created using these directive commands is read into multiple files areas w
97. ed term in an expression with Table 3 2 5 Calculation Priority Priority Calculation priority modifying operator OU Monadic operator 1 SIZEOF TOPOF Dyadic operator 1 1 Dyadic operator 2 Dyadic operator 3 Dyadic operator 4 Dyadic operator 5 Conditional operator lt gt lt 99 3 Description of Lines Functions of Assembler 3 2 Method for Writing Source Program AS30 processes the source program one line at a time Lines are separated by the new line character A section from a character immediately after the new line character to the next new line character is assumed to be one line The maximum number of characters that can be written in one line is 255 Lines are classified into five types by the content written in the line Table 3 2 6 shows the method for writing each type of line e Directive command line e Assembly source line e Label definition line e Comment line e Blank line Table 3 2 6 Types of Lines Directive Command Line Function This is the line in which as30 directive command is written Description method Only one directive command can be written in one line A comment can be written in the directive command line Precautions No directive command can be written along with a mnemonic in the same line Example SECTION program DATA ORG 00H EQU 0 BLKB 1 ALIGN PAGE ALIGN sym work newpage Label
98. ee types of divide instructions two signed divide instructions and one unsigned divide instruction All these three instructions allow the user to specify the desired size When B is specified calculation is performed in 16 bits 8 bits 8 bits remainder in 8 bits when W is specified calculation is performed in 32 bits 16 bits 16 bits remainder in 16 bits Only the O flag changes state in the divide instruction Figure 2 6 5 shows an example of how the divide instruction works Table 2 6 5 Divide Instruction Mnemonic Description Format Explanation Signed divide instruction Sign of remainder matches that of dividend Signed divide instruction Sign of remainder matches that of divisor Unsigned divide instruction DIV 1263 20 63 3 H Remainder H 8 bits src 8 bits ROL 8 bits ROH A 01 6D 4 16 bits src 32 bits R2RO Remainder 16 bits RO 8 bits src 8 bits ROL 8 bits ROH Remainder 32 bits R2RO 16 bits src 16 bits RO 16 bits R2 Figure 2 6 5 Typical operations of divide instructions 68 CPU Programming Model 2 6 Instruction Set Difference between DIV and DIVX Instructions Both DIV and DIVX are signed divide instructions The difference between these two instructions is the sign of the remainder As shown in Table 2 6 6 the sign of the remainder deriving from the DIV instruction is the same as that of the dividend Wit
99. eeeeeeeeeeeeeeeeeeaeeeeeeeeseaaeeeeaeeeseaaeeeeaaeesecaeeeeaeeseaas 136 42 27 SEUNG Stack ie lt 136 4 2 3 Setting Base Registers SB EBI 136 4 2 4 Setting Interrupt Table Register INTE 136 4 2 5 Setting Variable Fixed VeOCtor ccsccceceeeceseeeeeeeeeeceaeeeeeneeeceaeeeeeaaeeseaeeeseaaessseeeeesaeesseneeeeaas 137 4 2 6 Setting Peripheral FUNCtIONS ccccceeeeeeeeeeeeneeeeeeeeeeeeaeeeeeeeeecaaeeeeeeeeecaeeeseaeeeseaeeeseneeeseaees 137 4 2 7 Sample Program List 2 Initial Setting 2 139 4 3 Setting Interr ptS iarann oaiae aeaa aa aaraa aaa N aaa daaa aa Kaa aa aaa aaaea a aa daaa 142 4 3 1 Setting Interrupt Table Register cccccceceeeesceeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeescaeeeseeeeseieeestaeeseaes 142 4 3 2 Setting Variable Fixed Vechors ccceeceececeeceeseeececeeeeeeaeeeeeeeeeeaaaeseaeeeseaaeseeeeeeseaeetenaeeeeeas 143 4 3 3 Enabling Interrupt Enable Flag cccccceeceeeeeeeceeeeeeeeeeeeeeeeeeeeeesaeeeseaeeeseaeeessaeeeseieeeesaeeeeaes 144 4 3 4 Setting Interrupt Control Register cceccecceceeeeeneececeeeeeaaeeeeeeeeeaaeeseeeeeesaaeessaeeestiaeessenes 144 4 3 5 Saving and Restoring Registers in Interrupt Handler Routine seeseeeeeseesseerreeren 145 4 3 6 Sample Program List 3 Software Interrupt cecceceeeeeseceeceeeeeeeeaeeceeeeeesaeeeeeeeeeseaeeneees 147 453 7 ISP and USP E 150 4 3 8 Multiple Interrupts 2 00 0 eee eeeee teeter ee teeta eee een ae ee eer REAS eee KAN
100. ernal ceramic or crystal resonator Interrupt 17 internal sources 5 external sources 4 software i sources 7 levels including key input interrupt Multifunction 16 bit timer 5 timer A 3 timer B Serial UO 2 channels asynchronous synchronous switchable A D converter 10 bits 8 2 channel input 10 8 bits switchable D A converter 8 bits 2 channel output DMAC 2 channels trigger 15 factors CRC calculation circuit 1 circuit built in Watchdog timer 15 bit counter Programmable input output 87 lines Input port 1 line shared with P8s and NMI pin Note This does not include the M30600SFP an external ROM version Overview of M16C 60 Series 1 2 Outline of M16C 60 Group M16C 20 Group Outline Specifications of the M16C 20 Group Table 1 2 2 lists the outline specifications of the M16C 20 group Table 1 2 2 Outline Specifications of M16C 20 Group Item Content Supply voltage 2 7 to 5 5 V with 7 MHz external oscillator 1 wait state Package 52 pin plastic molded SDIP 56 pin plastic molded QFP Operating frequency 10 MHz with 10 MHz external oscillator Shortest instruction execution time 100 ns with 10 MHz external oscillator Basic bus cycle Internal memory 100 ns with 10 MHz external oscillator Internal memory ROM capacity RAM capacity 32 Kbytes 1024bytes Operation mode Single chip mode Clock generating circuit 2 circuits built in external ceramic or crystal resonator Built in per
101. es labels symbols and bit symbols between global and local and between relocatable and absolute as it handles them These classifications are defined below e Global The labels and symbols specified with directive command GLB are handled as global labels and global symbols respectively The bit symbols specified with directive command BTGLB are handle as global bit symbols If a name defined in the source file is specified as global it is made referencible from an external file If aname not defined in the source file is specified as global it is made an external reference label symbol or bit symbol that references a name defined in an external file Local All names are handled as local unless they are specified with directive command GLB or BTGLB Local names can be referenced in only the same file where they are defined Local names are such that the same label name can be used in other files Relocatable The values of local labels symbols and bit symbols within relative sections are made relocatable The values of externally referenced global labels symbols and bit symbols are made relocatable Absolute The values of local labels symbols and bit symbols defined in an absolute attribute section are made absolute The labels symbols and bit symbols handled as absolute have their values determined by as30 The values of all other labels symbols and bit symbols are determined by In30 when linking programs Figu
102. est Explanation dest lt dest src Multiplies without sign NEG size dest dest 0 dest 2 s complement RMPA size R2RO lt sum of products calculation using AO as multiplicand address A1 as multiplier address and R3 as operation count Calculates sum of products SBB size src dest dest dest src C flag Subtracts with borrow SUB size src dest dest lt dest src Subtracts without borrow 54 CPU Programming Model Instruction Set 2 6 Addressing General instruction Flag change Dap Jose 101 U09 l lol lolo lo O 0 O 0 aaqelas 19 S1691 uq 0z C 2 O el Be 5 n E 5 D Q Kei ainjosqe 4q 9 L ye paww 55 CPU Programming Model 2 6 Instruction Set Logic Mnemonic Write W or B for size AND size src dest Explanation dest src amp dest Logical AND NOT size dest dest lt dest Inverts all bits OR size src dest dest lt src dest Logical OR TST size src dest src amp dest XOR size Shift src dest Mnemonic Write W or B for size ROLC size dest dest lt dest src Exclusive OR Explanation Rotates dest left by 1 bit including C flag RORC size dest Rotates dest right by 1 bit including C flag ROT siz
103. est when Z flag 1 Transfers src2 to dest when Z flag 0 STZX src1 src2 dest Note Only IMMB8 8 bit immediate can be used for src src1 and src2 First immediate Second immediate STZ 5 ROL STNZ 5 ROL STZX 5 8 ROL YES YES A YES Figure 2 6 1 Typical operations of conditional store instructions 65 CPU Programming Model 2 6 Instruction Set String Instruction This instruction transfers data collectively Use it for transferring blocks and clearing RAM Set the source address destination address and transfer count in each register before executing the instruction as shown in Figure 2 6 2 Data is transferred in bytes or words Figure 2 6 3 shows an example of how the string instruction works SMOVF SMOVB SSTR HIH AO Source address au 16 Value to be transferred Al Destination address 16 R3 Transfer count 16 Destination address Transfer count Figure 2 6 2 Setting registers for string instructions Table 2 6 3 String Instruction Mnemonic 3 Description Format Explanation Transfers string in incrementing address direction Transfers string in decrementing address direction Stores string in incrementing address direction SMOVF B SMOVB B SSTR B ROL A
104. etting Interrupts INT_OVER_FLOW PUSHM RO R1 R2 R3 A0 A1 Program POPM RO R1 R2 R3 A0 A1 INT_OVER_FLOW_END REIT skkkkkkkkkkkkkkkkkkkkkkk i 7 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Setting of fixed vector SECTION F_VECT ROMDATA ORG FIXED_VECT_TOP LWORD dummy Undefined instruction interrupt vector LWORD INT_OVER_FLOW Sets overflow interrupt vector LWORD dummy BRK instruction interrupt vector LWORD dummy Address match interrupt vector LWORD dummy Single step interrupt vector normally inhibited from use LWORD dummy Watchdog timer interrupt vector LWORD dummy DBC interrupt vector normally inhibited from use LWORD dummy NMI interrupt vector LWORD START Sets reset vector END Figure 4 3 3 Example for using software interrupt 149 Programming Style 4 4 3 Setting Interrupts 4 3 7 ISP and USP The M16C 60 series has two stack pointers an interrupt stack pointer ISP and a user stack pointer USP Use of these stack pointers is selected by the U flag 1 ISP is used when U 0 Registers are saved and restored to and from the address indicated by ISP 2 USP is used when U 1 Registers are saved and restored to and from the address indicated by USP Be sure to use ISP when creating the program in only the assembly language i e when not using the OS Although it is possible to use USP caution is required in using peripheral I O interrupts in this case For details refer to Relati
105. f Operators Conditional operators Positive value gt Left side value is greater than right side value Negative value lt Right side value is greater than left side value NOT gt Left side value is equal to or greater thanright SIZEOF Section size in bytes side value TOPOF Start address of section Right side value is equal to or greater thanleft side value Left side value and right side value are equal Add I Left side value and right side value are not equal Subtract Calculation priority modifying operator Multiply A term enclosed with is calculated before any Divide other term If multiple terms in an expression are Remainder enclosed with the leftmost term has priority Shift bits right Parentheses can be nested Shift bits left AND OR Exclusive OR Monadic operators Dyadic operators Note 1 For operators SIZEOF and TOPOF be sure to insert a space or tag between the BEE ang operand Note 2 Conditional operators can only be written in the operands of directive commands IF and ELIF Calculation Priority Calculation is performed in order of priorities of operators beginning with the highest priority operator Table 3 2 5 lists the priorities of operators If operators in an expression have the same priority calculation is performed in order of positions from left to right The priority of calculation can be changed by enclosing the desir
106. ff is determined by a conditional expression FOR NEXT statement hereafter called the FOR NEXT statement This statement is an instruction to control repetition The statement is executed repeatedly as long as a specified condition is true FOR TO STEP NEXT statement hereafter called the FOR STEP statement This statement is an instruction to control a repeat count by specifying the initial incremental and final values DO WHILE statement hereafter called the DO statement This statement is executed repeatedly as long as a conditional expression is satisfied true SWITCH CASE DEFAULT ENDS statement hereafter called the SWITCH statement This statement causes control to branch to one of CASE blocks depending on the value of a conditional expression BREAK statement This statement halts execution of the relevant FOR DO or SWITCH statement and branches to the next statement to be executed CONTINUE statement This statement causes control to branch to a repeat statement of minimum repetition including itself in FOR or DO statement FOREVER statement This statement repeatedly executes a control block by assuming that a conditional expression in the relevant FOR and DO statements is always true 124 Chapter 4 Programming Style 4 1 Hardware Definition 4 2 Initial Setting of CPU 4 3 Interrupts 4 4 Dividing Source File 4 5 A Little Tips 4 6 Sample Programs 4 7 Generating Object File Programming Style 4 4
107. file 7 coon Allocation of work RAM areg thinset 8 SECTION WORK DATA 9 00400 ORG 00400H 10 11 00400 WORKRAM_TOP 12 00400 000001H AAA BLKB 1 13 00401 000001H BBB BLKB 1 14 00402 000001H CCC BLKB 1 15 00403 000001H ALIGN 16 00404 000002H DDD BLKW 1 e 17 00406 WORKRAM_END 18 penean Definition of bit symbol 8 tether aa ARR AREER 19 2 00000400h bitsym BTEQU 2 AAA Defines bit symbol 20 prenen Allocation of stack area Heeei 21 00000100h STACK_SIZE EQU 256 22 SECTION STACK DATA 23 01000 ORG 01000H 24 01000 000100H STACK_TOP BLKB STACK_SIZE Allocates stack area 256 bytes 25 00001100h STACK_TAIL EQU STACK_TOP STACK_SIZE 177 Programming Style 4 4 7 Generating Object Files M16C FAMILY ASSEMBLER SOURCE LIST Wed Mar 6 15 17 37 1996 PAGE 002 SEQ LOC OBJ OXMDA SOURCE STATEMENT ra Tecra ruse Bever iora Goera iens ESSE SSSI IIE AER 61 Program area 62 Jesessssssssssssss Startup routine s s s 63 SECTION PROGRAM CODE 64 10000 ORG 10000H 65 SB 00380H Declares SB register value to assembler 66 ER 00500H Declares FB register value to assembler 67 68 10000 START 69 10000 EB608003 LDC 380H SB Sets initial value in SB register 70 10004 EB700005 LDC 500H FB Sets initial value in FB register 71 S 72 10008 C7030A00 S MOV B 03H PRCR Removes protect 73 1000C D97F0400 Q MOV W 0007H PMO Sets
108. g OFFFFH long 2 Figure 4 2 1 Example for initial setting a work area 137 Programming Style 4 4 2 Initial Setting the CPU Initial Setting Ports It is when a port direction register is set for output that data is output from a port To prevent indeterminate data from being output from ports set the initial value in each output port before setting their direction register for output Figure 4 2 2 shows an example for initial setting ports 0FFFFH P6 Sets initial value in ports P6 and P7 0FFFFH PD6 Sets ports P6 and P7 for output 04H PRCR Removes protect 0000H PD8 Sets ports P8 and P9 for input Figure 4 2 2 Example for initial setting ports Setting Timers When using the M16C 60 M16C 20 series built in peripheral functions such as a timer initial set the related registers in SFR area Figure 4 2 3 shows an example for setting timer AO TAOS BTEQU 0 TABSR MOV B 01000000B TAOMR Setting of timer AO mode register Mode timer mode Divide ratio 1 8 MOV B 00000111B TAOIC Clears timer AO interrupt request bit Enables timer AO interrupt priority level 7 MOV W 2500 1 TAO Sets count value in timer AO BSET TAOS Timer AO starts counting Figure 4 2 3 Example for setting timer 138 Programming Style 4 4 2 Initial Setting the CPU 4 2 7 Sample Program List 2 Initial Setting 2 RIK KR RK RRR KK pelt eler e eer y INCLUDE m30600 inc kkkkkk
109. gnored Symbol bit base 8 SB bit obase 11 SB bit oase 16 SB Note bit base 8 SB One bit in an area of up to 32 bytes can be specified bit base 11 SB One bit in an area of up to 256 bytes can be specified bit base 16 SB One bit in an area of up to 8 Kbytes can be specified Example BCLR 13 8 SB 00000H SB address gt Effective address range 0 to OFFFFH 8 Figure 2 5 29 Bit instruction SB relative addressing 42 CPU Programming Model 2 5 Addressing Modes FB Relative In this mode the address is referenced to the value indicated by the FB register The value of the FB register has base added with the sign included The resulting value indicates the reference address so operation is performed on the bit that is away from bit 0 at that address by a number of bits indicated by bit The address range that can be specified is a 16 byte area in the direction toward smaller addresses or a 15 byte area in the direction toward larger addresses from the address indicated by the FB register However the range of effective addresses is 00000H to OFFFFH If the address of the bit to be operated on exceeds OFFFFH the most significant bits above and including bit 17 are ignored Symbol bit base 8 FB Example BCLR 5 8 FB 00000H If the value of base is negative 8 T Effective address range F address gt 0 to OFFFFH Figure 2 5 30 Bit instruction FB relative addressing 43 C
110. h the DIVX instruction however the sign is the same as that of the divisor Table 2 6 6 Difference between DIV and DIVX Instructions The sign of the remainder is the same as that of the dividend The sign of the remainder is the same as that of the divisor 69 Decimal Add Instruction CPU Programming Model 2 6 Instruction Set There are two types of decimal add instructions one with a carry and the other without a carry The S Z and C flags change state when the decimal add instruction is executed Figure 2 6 6 shows an example of how these instructions operate Table 2 6 7 Decimal Add Instruction Mnemonic Description Format src dest src dest Explanation Add in decimal not including carry DADD 2 digits 62 50 112 10 s place 1 s place ealo C flag DADC 2 digits 62 30 C flag 1 93 10 s place 1 s place SC SC 3 0 H C flag KOR 3 C flag src dest src dest Add in decimal including carry 4 digits 1234 9000 10234 1000 s 100 s 10 s 1 s place place place place e Re el pO l2 3 4 C flag 4 digits 1234 9000 C flag 1 10234 1000 s 100 s 10 s 1 s place place place place 8 O TOTO C flag LD 2 3 5 C flag Figure 2 6 6 Typical operations of decimal add instructions 70 CPU Programming Model 2 2 6 Instruction Set Decimal Subtract Instruction There are two types of decimal subtract instructions one with a bo
111. have occurred when linking the relocatable module files This file is not generated when no error was encountered This file allows errors to be corrected easily when it is used an editor that has the tag jump function 180 4 Method for Starting Up In30 Programming Style 4 7 Generating Object Files gt In30 relocatable file name relocatable file name option Be sure to write at least one file name The extension R30 can be omitted Table 4 7 2 Command Options of In30 Inhibits link processing messages from being output E address value Sets start address of absolute module file Always be sure to insert Space between option symbol and address value and use label name or hexadecimal number to write address value G Outputs source debug information to absolute module file L library file Specifies library file to be referenced when linking LD path name Specifies directory of library file M Generates map file This file is named after absolute module file by changing its extension to map MS Generates map file that includes symbol information NOSTOP Outputs all encountered errors to display screen If not specified up to 20 errors are output to screen O absolute file name Specifies absolute module file name File extension can be omitted If omitted extension x30 is assumed ORDER Specifies section arrangement and sequence in which order
112. ied to the CNVss the value of this register when reset is 0316 PMOO and PMO1 are both set to 1 Note 3 Valid in microprocessor and memory expansion modes Note 4 In microprocessor mode multiplexed bus for the entire space cannot be selected In memory expansion mode when multiplexed bus for the entire space is selected address bus range is 256 bytes in each chip select Figure 2 1 5 Processor mode register 0 14 2 CPU Programming Model 2 1 Address Space 2 1 3 Fixed Vector Area The M16C 60 group fixed vector area consists of addresses FFEOOH to FFFFFH Addresses FFEOOH to FFFDBH in this area constitute a special page vector table This table is used to store the start addresses of subroutines and jump addresses so that subroutine call and jump instructions can be executed using two bytes helping to reduce the number of program steps Addresses FFFDCH to FFFFFH in the fixed vector area constitute a fixed interrupt vector table for reset and NMI This table is used to store the start addresses of interrupt routines An interrupt vector table for timer interrupts etc can be set at any desired address by an internal register INTB For details refer to the section dealing with interrupts in Chapter 4 Memory Mapping in Fixed Vector Area Figure 2 1 6 shows memory mapping for the special page vector table and fixed vector area FFEOOH FFEO2H FFFDBH FFFDCH FFFFFH Special page number Special pag
113. ier S B W A Transfers in the direction of arrow Add Subtract Multiply Divide Logical AND Logical OR Exclusive OR Negate Absolute value U O B S Z D C Extend sign in Flag name ROL ROH R1 R1H 8 bit register name RO R1 R2 R3 AO A1 16 bit register name R2R0 R3R1 A1A0 32 bit register name SB FB SP PC Register name MOVDir BMCnd JCnd Dir direction and Cnd condition mnemonics are shown in italic JGEU C JEQ Z Indicate that JGEU C is written as JGEU or JC and that JEQ Z is written as JEQ or JZ Addressing Can be used Flag change Flag changes according to execution result change Flag does not change 47 2 2 6 1 Instruction List In this and following pages instructions are summarized by function in list form showing the content of each mnemonic addressing and flag changes Transfer Write W or B for size Mnemonic MOV size src dest CPU Programming Model 2 6 Instruction Set Explanation Transfers src to dest or sets immediate in dest MOVA src dest Transfers address in src to dest MOVHH _ src dest MOVHL src dest MOVLH _ src dest MOVLL src dest Transfers 4 high order bits in src to 4 high order bits in dest Transfers 4 high order bits in src to 4 low order bits in dest Transfers 4 low order bits in src
114. ill be allocated separately in each file Although no error may occur when using symbols in the include file locally care must be taken when using them globally because it could result in duplicate definitions If use of acommon area in multiple files is desired define the area allocated part in a shared definition file and link it as one of the source files Then define the symbol s global specification part in an include file Reading Include File into Source File Use directive command INCLUDE to read an include file into the source file Specify the file name to be read in with a full name Example When reading an include file M30600 INC that contains a definition of the SFR area INCLUDE M30600 INC 128 Programming Style 4 4 1 Hardware Definition 4 1 2 Allocating RAM Data Area Use the following directive commands to allocate a RAM area BLKF Allocates a 4 byte area BLKD Allocates a 8 byte area floating point floating point BLKB Allocates a 1 byte area integer BLKW Allocates a 2 byte area integer BLKA Allocates a 3 byte area integer BLKL Allocates a 4 byte area integer Example for Setting Up Work Area Figure 4 1 3 shows an example for setting up a work area Figure 4 1 3 Example for setting up a work area 129 Programming Style 4 4 1 Hardware Definition 4 1 3 Allocating ROM Data Area Use the directive commands listed bel
115. interrupt enable flag I flag is cleared to 0 interrupts disabled No other interrupts are accepted until after the enabled interrupt is serviced However it is possible to accommodate multiple interrupts by setting the interrupt enable flag to 1 to enable interrupts in the program Example of Multiple Interrupt Execution As an example of multiple interrupt execution Figure 4 3 7 shows a flow of program execution in cases when multiple interrupts a b and c occur a Interrupt 1 occurs when executing the main routine b Interrupt 2 occurs when servicing interrupt 1 In this example the following is assumed DI IPL processor interrupt priority level 0 c Interrupt 3 occurs when servicing interrupt 2 interrupt priority level of interr pt 1 3 Interrupt priority level of interrupt 2 5 Interrupt priority level of interrupt 3 1 Main routine IPL 0 Interrupt 1 d occurs Interrupt priority level 3 here IPL 3 Interrupt priority level 1 Interrupt 3 Interrupt 2 Interrupt 2 occurs Interrupt priority cm here level 5 as IPL 5 REIT 1 instruction REIT instruction X Interrupt 3 Interrupt 3 Interrupt priority level 1 occurs REIT here instruction Since the priority level of interrupt 3 is lower than that of interrupt 1 this interrupt is not accepted and is kept pending Set in hardware execution until after interrupt 1 i is serviced Set in software Figure 4 3 7
116. interrupt vector dummy Timer A1 interrupt vector dummy Timer A2 interrupt vector dummy Timer A3 interrupt vector dummy Timer A4 interrupt vector dummy Timer BO interrupt vector dummy Timer B1 interrupt vector dummy Timer B2 interrupt vector dummy INTO interrupt vector dummy INT1 interrupt vector dummy INT2 interrupt vector skkkkkkkkkkkkkkkkkkkkkkk ai K kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Setting of fixed vector SECTIONF_VECT ROMDATA ORG LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD LWORD END FIXED_VECT_TOP dummy Undefined instruction interrupt vector dummy Overflow INTO instruction interrupt vector dummy BRK instruction interrupt vector dummy Address match interrupt vector dummy Single step interrupt vector normally inhibited from use dummy Watchdog timer interrupt vector dummy DBC interrupt vector normally inhibited from use dummy NMI interrupt vector START Sets reset vector Figure 4 2 4 Description example 2 for initial setting 141 Programming Style 4 3 Setting Interrupts 4 3 Setting Interrupts This section explains the method of processing and description that is required when executing an interrupt handling program and how to execute multiple interrupts Following processing is required when executing an interrupt handling program 1 Setting interrupt table register 2 Setting variable fixed vectors Enabling inte
117. ion also 2 bytes 0 to 3 bytes 0 to 3 bytes 2 Quick format Q The op code contains a verb and immediate data and dest addressing information also However the immediate data included in the op code is a numeral that can be expressed by 7 to 8 or 8 to 7 varies with each instruction dest code 0 to 2 bytes Short format S The op code contains src and dest addressing information also This format is used in some limited addressing modes 1 byte 0 to 2 bytes 0 to 2 bytes Zero format Z The op code contains a verb and immediate data and dest addressing information also However the immediate data is fixed to 0 This format is used in some limited addressing modes dest code 0 to 2 bytes 46 2 2 6 Instruction Set CPU Programming Model 2 6 Instruction Set This section explains the instruction set of the M16C 60 series The instruction set is summarized by function in list form In addition some characteristic instructions among the instruction set are explained in detail The table below shows the symbols used in the list and explains their meanings Symbol Meaning Operand that does not store processing result Operand that stores processing result Operand that means an address 16 bit absolute value 20 bit absolute value 8 bit displacement 16 bit displacement 20 bit displacement Immediate Size specifier B W Jump distance specif
118. ipheral functions Interrupt 9 internal sources 3 external sources 4 software sources 7 levels including key input interrupt Multifunction 16 bit timer 1 timer A 2 timer B 3 timer X g Serial UO 2 channels one is clock asynchronous synchronous switchable the other is clock asynchronous A D converter 10 bits 8 2 channel input 10 8 bits switchable Programmable input output 43 lines Overview of M16C 60 M16C 20 Series 1 1 3 Introduction to CPU Architecture 1 3 Introduction to CPU Architecture This section explains the CPU architecture of the M16C 60 M16C 20 series Each item explained here is detailed in Chapter 2 of this manual Register Structure Table 1 3 1 shows the register structure of the M16C 60 M16C 20 series Seven registers RO R1 R2 R3 AO A1 and FB are available in two sets each These sets are switched over by a register bank select flag Table 1 3 1 Register Structure of M16C 60 M16C 20 Series Item Content Register structure Data registers 16 bits x 4 32 bits x 2 8 bits x 4 R2R0 Lk RO E E R1 L Address registers 16 bits x 2 32 bits x 1 AO A1 A1A0 SE Base registers 16 bits x 2 SB FB Control registers i bus IPL b Cf 9 20 bits x 2 Details of FLG mmm ee PC PC INTB 16 bits x 3 USP ISP FLG IPL
119. iption Format l JMPS special page number NES MPS ebel 18 lt special page number lt 255 JMPS 251 JMPS 251 FFEOOH Number 255 01000H Tee jumps to the address that is set in special page number 251 FFEO8H Number 251 plus FOOOOH FFEOAH Number 250 v r SERERE Special page FFFDBH Number 18 F1500H FFFDCH Interrupt vector table y FFFFFH High order address is fixed to OFH Figure 2 6 16 Typical operation of special page branch instruction 79 CPU Programming Model 2 6 Instruction Set Conditional Branch Instruction This instruction examines flag status with respect to the conditions listed below and causes control to branch if the condition is true or executes the next instruction if the condition is false Figure 2 6 17 shows an example of how the conditional branch instruction works Table 2 6 17 Conditional Branch Instruction Mnemonic Description Format Explanation Jumps to label if condition is true JCnd label or executes next instruction if condition is false True false determining conditions 14 conditions C 1 Equal or greater Carry flag 1 C 1 amp Z 0 Unsigned and greater 224 Equal Zero flag 1 S 1 Negative Z 1 S 1 amp O 0 S 0 amp O0 1 Equal or signed and smaller O 1 Overflow flag 1 S 1 amp O0 1 S 0 amp O0 0 Equal or signed and greater LTU NC C 0 Smaller Carry
120. kkkkkkkkkkkkkkkkkk m Set kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Symbol definition RAM_TOP EQU 00400H Start address of RAM RAM_END EQU 02BFFH End address of RAM ROM_TOP EQU OFOOOOH Start address of ROM FIXED_VECT_TOP EQU OFFFDCH _ Start address of fixed vector SB_BASE EQU 00380H Base address of SB relative addressing FB_BASE EQU 00480H Base address of FB relative addressing H EE Allocation of work RAM eie a SECTION WORK DATA ORG RAM_TOP WORKRAM_TOP WORK_1 BLKB 1 WORK_2 BLKB 1 WORKRAM_END skkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Program area SECTION PROGRAM CODE Declares section name and section type ORG ROM_TOP Declares start address SB SB_BASE Declares SB register value to the assembler ER EB BASE Declares FB register value to the assembler START LDC RAM_END 1 ISP Sets initial value in stack pointer LDC SB_BASE SB Sets initial value in SB register LDC FB_BASE FB Sets initial value in FB register MOV B 03H PRCR Removes protect MOV W 0007H PMO Sets processor mode registers 0 and 1 MOV W 2008H CMO Sets system clock control registers 0 and 1 MOV B 0 PRCR Protects all registers LDC 0 FLG Sets initial value in flag register LDINTB VECT_TOP Sets initial value in interrupt table register 139 Programming Style 4 2 Initial Setting the CPU MOV W 0FFFOH PUR1 Connects internal pull up resistors MOV W 0 RO Cl
121. l RAM area 02C00H Internal reserved area Internal reserved area 23 SCH a GE hy SCH Ges 3 SCH e SCH SCH 3 e 3 2 3 SE ty SCH a t SCH a GE t y SCH ch SCH Ges a SCH SCH e 3 2 3 SCH hy SCH Ges 3 SCH SCH Internal reserved area e SCH 3 SCH SCH a t hy FOOOOH 7 SCH 7 t 3 SC 3 SCH SE hy SCH e 3 SCH 38 e SCH 2 SCH Ge 38 SCH 38 Internal ROM area Internal ROM area 7 SCH 3 e 3 2 SCH SCH 3 SE hy SCH SC 3 SCH SCH t 3 Ze E SE 7 t me i oy K FFFFFH Single chip mode Memory Microprocessor mode expansion mode Figure 2 1 2 Operation modes and memory mapping 11 CPU Programming Model 2 2 1 Address Space 2 1 2 SFR Area A range of control registers are allocated in this area including the processor mode register that determines the operation mode and the peripheral unit control registers for I O ports A D converter UART and timers For the bit configurations of these control registers refer to the M16C 60 group data sheets and user s manuals The unused locations in the SFR area are reserved for the system and cannot be used by the user SFR Area Control Register Allocation Figures 2 1 3 and 2 1 4 show control register allocations in the SFR area
122. le for setting values in the SB and FB registers Less frequently accessed register group 00000H More frequently accessed register group O00 SFR area lt 4 SB register setup value Effective range of SBrelative addressing lt FB register setup value Effective range of FB relative addressing Internal RAM area By locating the SB and FB registers at contiguous effective range of addresses it is possible to access data in a total 512 bytes of area by SB and FB relative addressing Note The M16C 60 group memory map is used here Figure 4 5 3 General method for setting SB and FB register values 166 Programming Style 4 4 5 A Little Tips 4 5 3 Alignment Specification The following explains about alignment specification What Does Alignment Specification Mean When alignment is specified the assembler corrects the address that contains code for the line immediately after directive command ALIGN is written to an even address If the section type is CODE or ROMDATA a NOP instruction is written into the space that is made blank as a result of address correction If the section type is DATA the address value is incremented by 1 If the address where this directive command is written happens to be an even address no correction is made This directive command can be written under the following conditions 1 For relative attribute sections Only when address correction is specified in section definitio
123. lectric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein Preface This manual describes the basic knowledge of application program development for the M16C 60 M16C 20 series of Mitsubishi CMOS 16 bit microcomputers The programming language used in this manual is the assembly language If you are using the M16C 60 M16C 20 series for the first time refer to Chapter 1 Overview of M16C 60 M16C 20 Series If you want to know the CPU architecture and instructions refer to Chapter 2 CPU Programming Model or if you want to know the directive comm
124. lled function Before executing ENTER instruction After executing ENTER instruction Stack area Automatic variable area of called function Old FB lower Stack area Old FB upper Return address Return address low low Return address etun address middle middle Return address Return address high high Argument 2 Argument 2 Argument 1 Argument 1 Automatic Automatic variable of variable of main main Figure 2 6 18 Typical operation of stack frame build instruction 81 CPU Programming Model 2 2 6 Instruction Set Cleaning Up Stack Frame The EXITD instruction cleans up the stack frame and returns control from the subroutine It performs these operations simultaneously Figure 2 6 19 shows an example of how the stack frame clean up instruction works Table 2 6 19 Stack Frame Clean up Instruction Mnemonic Description Format Explanation Cleans up stack frame EXITD 1 Transfers FB to SP 2 Restores FB from stack area 3 Returns from subroutine function operates in the same way as RTS instruction Before executing EXITD instruction After executing EXITD instruction Stack area Stack area Automatic Automatic variable area of variable area of called function F called function Old FB lower Old FB lower Old FB upper Old FB upper Return address Stack frame Return address low low Return address Return address middle middle Return address Ret
125. m as defined Names can be divided into the following four types Description range varies with each type Note that the AS30 system reserved words cannot be used in names Note e Label e Symbol e Bit symbol e Location symbol Rules for writing names 1 Names can be written using alphanumeric characters and _ underscore Each name must be within 255 characters in length 2 Names are case sensitive so they are discriminated between uppercase and lowercase 3 Numerals cannot be used at the beginning of a name Note Program operation cannot be guaranteed if any reserved word is used 95 Functions of Assembler 3 2 Method for Writing Source Program Types of Names Table 3 2 1 shows the method for defining names Table 3 2 1 Types of Names Defined by User Label Function Indicates a specific memory address Definition method Always add colon at the end of each name There are two methods of definition 1 Allocate an area with a directive command Example flag BLKB 1 work BLKB 1 2 Write a name at the beginning of a source line Example name _name sum_name Reference method Write the name in the operand of an instruction Example J MP sym_name Bit symbol Function Indicates a specific bit address in memory Definition method Use a directive command that defines a bit symbol Example flag1 flag2 flag3 BTEQU 1 flags BTEQU 2 flags BTEQU 20 flags 7654 32
126. m runaway se e When a watchdog timer interrupt occurs the program is restarted by a software reset in the interrupt handler routine Program restarted Figure 4 5 5 Operation flow when program runaway is detected 2 Method of runaway detection Program a procedure so that a write to the watchdog timer start register is performed before the watchdog timer underflows By writing to the watchdog timer start register the initial count 7FFFH is set in the watchdog timer This is fixed and not other value can be set If this write operation is inserted in a number of locations it can happen that a write to the watchdog timer start register is performed at a place to which the program has been brought by runaway Thus no where in the program can it be detected to have run out of control Therefore be careful that this write operation is inserted in only one location such as the main routine that is always executed However consider the length of the main routine and that of the interrupt handler routine to ensure that a write to the watchdog timer start register will be performed before a watchdog timer interrupt occurs 169 Programming Style 4 5 A Little Tips 3 Restarting the program which is out of control Program a procedure so that bit 3 software reset bit of processor mode register 0 is set to 1 in the interrupt handler routine This causes a software reset to occur allowing the program to restart after being reset In
127. mple SECTION mem DATA ROMDTA e This is an area where fixed data other than the program is fixed data area written e ROMDATA type sections must be specified in the absolute module that they be located in the ROM area Example SECTION const ROMDATA 102 Functions of Assembler 3 2 Method for Writing Source Program Section Attribute A section in which units memory addresses are controlled is assigned its attribute when assembling the program Table 3 2 8 Section Attributes Attribute Content and Description Example Relative e Addresses in the section become relocatable values when the program is assembled e The values of labels defined in the relative attribute section are relocatable Absolute Addresses in the section become absolute values when the program is assembled e The values of labels defined in the absolute attribute section are absolute e To make a section assume the absolute attribute specify the address with directive command ORG in the line next to one where directive command GECTION is written Example SECTION program DATA ORG 1000H Section Alignment Relative attribute sections can be adjusted so that the start address of each of these sections determined when linking programs is always an even address If such adjustment is required specify ALIGN in the operand of directive command SECTION or write directive command ALIGN in the line next to one where directi
128. n SECTION WORK DATA ALIGN 2 For absolute attribute sections No specific restrictions SECTION WORK DATA ORG 400H 167 Programming Style 4 4 5 A Little Tips Advantages of Alignment Specification Correction to Even Address If data of different sizes such as a data table are located at contiguous addresses the data next to an odd size of data is located at an odd address In the M16C 60 series word data 2 byte data beginning with an even address is read written in one access those beginning with an odd address requires two accesses for read write Consequently instruction execution can be sped up by locating data at even addresses In this case however ROM or RAM efficiency decreases Figure 4 5 4 shows an example of a program description that contains alignment specification 1 For relative attribute sections Address Code SECTION WORK DATA ALIGN WORK_1 BLKW 1 00000H WORK _2 BLKW 1 00002H WORK 2 BLKB 1 00004H ALIGN 00005H Address is incremented by 1 Set data tables and similar other sections at even addresses as much as possible SECTION CONST ROMDATA ALIGN BYTE 12H 00000H 12H ALIGN 00001H 04H NOP code is inserted WORD 3456H 00002H 5634H 2 For absolute atiribute sections Address Code SECTION WORK DATA Set data tables and similar other sections ORG 400H at even addresses as much as possible WORK_1
129. n Format Explanation EXTS B dest Sign extends dest from 8 bits to 16 bits or from 16 bits RO to 32 bits Register memory 8 bit sign extension R2 RO Sign bits are substituted for the extended bits Figure 2 6 11 Typical operation of sign extend instruction 74 CPU Programming Model 2 2 6 Instruction Set 2 6 5 Bit Instructions This section explains the bit instructions of the M16C 60 series Logical Bit Manipulating Instruction This instruction ANDs or ORs a specified register or memory bit and the C flag and stores the result in the C flag Figure 2 6 12 shows an example of how the logical bit manipulating instruction works Table 2 6 12 Logical Bit Manipulating Instruction Mnemonic Description Format Explanation Cesre amp C ANDsC and erc Cesrc amp C ANDsC and src C src C ORsC and src Cesrc C_ ORsC and src Cesre C Exclusive ORs C and src Cesrc C Exclusive ORs C and src BAND 4 R1 R1 LTTTEPTTPEETEET EET Logica operation Operation ANDs the R1 register s result bit 4 and the C flag C flag Figure 2 6 12 Typical operation of logical bit manipulating instruction 75 CPU Programming Model 2 6 Instruction Set Conditional Bit Transfer Instruction This instruction transfers a bit from depending on whether a condition is met If the condition is true it transfers a 1 if the condition is false it transfers a 0 In all cases a fl
130. n hardware BYTE 12H 34H 56H 78H Sets 1 byte data WORD 1234H 5678H Sets 2 byte data ADDR 123456H 789ABCH Sets 3 byte data LWORD 12345678H 9ABCDEFOH Sets 4 byte data DATA_TABLE_END 134 Programming Style 4 1 Hardware Definition skkkkkkkkkkkkkkkkkkkkkkk K 7 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Setting of fixed vector SECTION F_VECT ROMDATA a Set jump addresses sequentially beginning with the least significant ORG FIXED_VECT TOP address of the fixed vector LWORD dummy Undefined instruction interrupt vector LWORD dummy Overflow INTO instruction interrupt vector LWORD dummy BRK instruction interrupt vector LWORD dummy Address match interrupt vector LWORD dummy Single step interrupt vector normally inhibited from use LWORD dummy Watchdog timer interrupt vector LWORD dummy DBC interrupt vector normally inhibited from use LWORD dummy NMI interrupt vector LWORD START Sets reset vector Set the program start address for the END reset vector Immediately after power Set jump addresses for unused interrupts in on or after a reset is deactivated the dummy processing REIT instruction only to program starts from the address written prevent the program from running out of control in this vector when an unused interrupt is requested Figure 4 1 7 Description example 1 for initial setting 135 Programming Style 4
131. nge FLOAT 32 bits long 1 17549435 x 10 8 to 3 40282347 x 10 DOUBLE 64 bits long 2 2250738585072014 x 10 to 1 7976931348623157 x 10 Name Label and symbol names can be written in the operand of an instruction The method for writing names and a description example are shown in Table 3 2 2 in the preceding page Expression An expression consisting of a combination of a numeric value name and operator can be written in the operand of an instruction A combination of multiple operators can be used in an expression When writing an expression as a symbol value make sure that the value of the expression will be fixed when the program is assembled The value that derives from calculation of an expression is within the range of 2 147 483 648 to 2 147 483 648 Floating point numbers can be used in an expression The method for writing expressions and description examples are shown in Table 3 2 2 in the preceding page Character string A character string can be written in the operand of some directive commands Use 7 bit ASCII code to write a character string Enclose a character string with single or double quotations when writing it The method for writing character strings and description examples are shown in Table 3 2 2 in the preceding page 98 Functions of Assembler 3 2 Method for Writing Source Program Operator Table 3 2 4 lists the operators that can be written in the source programs for AS30 Table 3 2 4 List o
132. not included in optimization by using JSR W Because this is an externally referenced symbol whether it is within the base register relative addressing range cannot be determined when assembling Consequently it is forcibly encoded in base MAIN register relative addressing using SBSYM or FBSYM LDC 380H SB Sets initial value in SB register LDC 480H FB Sets initial value in FB register MOV B WORK_1 WORK_2 Externally references each work RAM MOV B WORK_3 WORK_4 Accessed in SB BSET W1_b0 relative addressing lt eferences each bit symbol BCLR W2 p1 Accessed in FB relative addressing JSR SUB _1 Calls SUB1 in file 3 When calling jumping to a subroutine label in another file since Encoded in JSR W addresses are not fixed yet all addresses normally are encoded with and branches in PC JSR A This is because JSR instructions cannot be optimized by jump relative addressing address calculation Therefore all JRS instructions are encoded in JSR W using OPTJ Precaution Before specifying JSRW or JMPW for encoding always check to see that the subroutine label exists within 64 Kbytes from the address where the call jump instruction exists Figure 4 4 3 Divided file 2 MAIN A30 158 Programming Style 4 4 Dividing Source File Division Example 3 Subroutine Processing SUB_1 A30
133. ogramming Model 2 2 5 Addressing Modes Address Register Indirect The value of an address register is the effective address to be operated on The range of effective addresses is 00000H to OFFFFH Symbol A0 A1 Example MOV B 12H A0 Specifiable address range 0 to 01FFFH Figure 2 5 2 Address register indirect addressing 26 CPU Programming Model 2 2 5 Addressing Modes Address Register Relative The value of an address register plus a displacement dsp is the effective address to be operated on The range of effective addresses is 00000H to OFFFFH If the addition result exceeds OFFFFH the most significant bits above and including bit 17 are ignored Symbol dsp 8 A0 dsp 16 A0 dsp 8 A1 dsp 16 A1 1 When dsp is handled as a displacement Example MOV B 34H 5 A0 Relative address range A 1000H 5 01005H 0 to FFFFH 01005H OFFFFH FFFFFH Figure 2 5 3 Address register relative addressing 1 2 When address register A0 is handled as a displacement Example MOV B 56H 1234H A0 SR lz gt 01234H Relative address range 1234H 0005H 01239H REES 0 to FFFFH 01239H OFFFFH FFFFFH Figure 2 5 4 Address register relative addressing 2 3 When the addition result exceeds OFFFFH Example MOV B 56H 1234H A0 a a BR Relative address range 1234H Eesen bh 2381 0 to FFFFH i e Ignored wun FFFFFH Figure 2 5 5 Address register relative addressing 3
134. ogramming Model 2 6 Instruction Set Explanation ANDs bits BCLR dest dest 0 Clears bit BMGEU C BMLTU NC BMEQ Z BMNE NZ BMGTU BMLEU BMPZ BMN BMGE BMLE BMGT BMLT BMO BMNO dest dest dest dest dest dest dest dest dest dest dest dest dest dest If C 1 dest 1 otherwise dest lt 0 If C 0 dest 1 otherwise dest 0 If Z 1 dest lt 1 otherwise dest 0 If Z 0 dest 1 otherwise dest lt 0 Conditionally transfers bit If C amp Z 1 dest lt 1 otherwise dest 0 lf C amp Z 0 dest lt 1 otherwise dest lt 0 If S 0 dest lt 1 otherwise dest 0 If S 1 dest 1 otherwise dest 0 lf S O 0 dest lt 1 otherwise dest lt 0 If S O Z 1 dest lt 1 otherwise dest 0 If S O Z 0 dest 1 otherwise dest 0 If S O 1 dest 1 otherwise dest 0 If O 1 dest lt 1 otherwise dest lt 0 If O 0 dest 1 otherwise dest 0 BNAND src C flag src amp C flag ANDs inverted bits BNOR src C flag lt sre C flag ORs inverted bits BNOT dest Inverts dest and stores in dest Inverts bit BNTST src Z flag src C flag lt src Tests inverted bit BNXOR src C flag src C flag Exclusive ORs inverted bits BOR src C flag lt src C flag ORs bits BSET dest dest 1 Sets bit BTST
135. ol directive command To direct execution of AS30 e Link control directive command To define information for controlling address relocation e List control directive command To control the format of list files generated by AS30 e Branch optimization control directive command To direct selection of the optimum branch instruction to AS30 e Conditional assemble control directive command To choose a block for which code is generated according to preset conditions when assembling the program e Extended function directive command To exercise other control than those described above e Directive command output by M16C family tool software All of this type of directive command and operand are output by the M16C family tool software These directive commands cannot be written in the source program by the user 108 Functions of Assembler 3 2 Method for Writing Source Program Address Control Usage and Description Example Declares an address Write this command immediately after directive command SECTION Unless this command is found immediately after the section directive command the section is not made a relative attribute section This command cannot be written in relative attribute sections ORG OFOOOOH ORG offset ORG OFOOOOH offset BLKB Allocates a RAM area in units of 1 byte BLKW Allocates a RAM area in units of 2 bytes BLKA Allocates a RAM area in units of 3 bytes BLK
136. onal assemble block Example Same as described above Indicates the beginning of a block to be assembled when condition is false This directive command can be written more than once in the conditional assemble block This command does not have an operand Example Same as described above Indicates the end of conditional assemble 114 This directive command must be written at least once in the conditional assemble block This command does not have an operand Example Same as described above 3 2 Functions of Assembler Method for Writing Source Program Directive Commands Output by M16C Family Tools Usage and Description Example Name beginning with _ Output by M16C family tool software 115 This command cannot be written in the source program by the user Program operation cannot be guaranteed unless this rule is observed Example _ FILE Functions of Assembler 3 3 2 Method for Writing Source Program 3 2 4 Macro Functions This section explains the macro functions that can be used in AS30 The following shows the macro functions available with AS30 e Macro function A macro function can be used by defining it with macro directive commands MACRO to ENDM and calling the defined macro e Repeat macro function A repeat macro function can be used by writing macro directive commands MREPEAT to ENDM Figure 3 2 5 shows the relationship between macro definition and macro call
137. onal branch Write A or W for length JGEU C JLTU NC JEQ Z JNE NZ JGTU JLEU JPZ JN label label label label label label label label label label label label label label If C 1 jump to label otherwise execute next instruction Conditional branch If C 0 jump to label otherwise execute next instruction If Z 1 jump to label otherwise execute next instruction If Z 0 jump to label otherwise execute next instruction If C amp Z 1 jump to label otherwise execute next instruction If C amp Z 0 jump to label otherwise execute next instruction If S 0 jump to label otherwise execute next instruction If S 1 jump to label otherwise execute next instruction If S O 1 jump to label otherwise execute next instruction If S O Z 1 jump to label otherwise execute next instruction If S O Z 0 jump to label otherwise execute next instruction If S O 1 jump to label otherwise execute next instruction If O 1 jump to label otherwise execute next instruction If O 0 jump to label otherwise execute next instruction label Jump to label Unconditional branch JMPI length src Jump to address indicated by src Indirect branch JMPS src Special page branch JSR label Subroutine call JSR length src Indirect subroutine call JSRS src Special page subroutine call RTS Return from su
138. onship between Software Interrupt Numbers and Stack Pointer in the next page Assignment of Software Interrupt Numbers In the M16C 60 series software interrupt numbers are available in the range of 0 to 63 Numbers 11 through 31 are reserved for peripheral I O interrupts Therefore assign the remaining numbers 0 through 10 and 32 through 63 to software interrupts INT instruction However for reasons of application of the M16C 60 series software interrupt numbers 32 through 63 are assigned for the software interrupts that are used by the OS real time monitor MR30 etc Basically Mitsubishi recommends using software interrupt numbers 0 through 10 User s software interrupts INT instruction Reserved for peripheral I O interrupts Software interrupts INT instruction used by the OS etc Interrupts that require context switching Figure 4 3 4 Assignment of software interrupt numbers Note When not using the OS software interrupts can be assigned numbers 32 through 63 In this case stack pointer setup requires caution 150 Programming Style 4 3 Setting Interrupts Relationship between Software Interrupt Numbers and Stack Pointer 1 When an interrupt of software interrupt number 0 to 31 occurs a The content of the FLG register is saved to a temporary register in the CPU b The U I and D flags of the FLG register are cleared By operation in b e The stack pointer is forcibly switched to the interrupt st
139. ontext information FFFFFH Operation 2 Stack area Restore the registers indicated by the register information from the stack area The SP sP gt Se register value does not change at this point in time gt Restored to each register Operation 3 Read out the content at the address next to the Task number x 2 register information i e an address incremented by 1 as SP correction value 8 bit data Context information SP correction value Operation 4 Add the SP correction value to SP to modify it SP SP correction value 85 CPU Programming Model 2 7 Outline of Interrupt 2 7 Outline of Interrupt This section explains the types of interrupt sources available with the M16C 60 group and the internal processing interrupt sequence performed after an interrupt request is accepted until an interrupt routine is executed For details on how to use each interrupt and how to set refer to Chapter 4 i 2 7 1 Interrupt Sources and Control The following explains the interrupt sources available with the M16C 60 group Interrupt Sources in M16C 60 Group Figure 2 7 1 shows the interrupt sources available with the M16C 60 group Hardware interrupts consist of six types of special interrupts such as reset and NMI and various peripheral I O interrupts that are dependent on built in peripheral functions such as timers and external pins Special interrupts are nonmaskable peripheral I O interrupts are maskable
140. ounter DM1CON EQU 003CH DMA1 control register Figure 4 1 1 Example of SFR area definition by EQU 126 Definition by BLKB Programming Style 4 1 Hardware Definition Figure 4 1 2 shows an example for defining the SFR area by using directive command BLKB SECTION SFR DATA Declare a section name Specify an absolute address according to the address at which processor mode register 0 is ORG 00004H PMO BLKB placed Processor mode register 0 Allocate an area where PM1 BLKB CMO BLKB CM1 BLKB CSR BLKB AIER BLKB PRCR BLKB processor mode Processor mode register 1 register 0 is placed System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register Note that unless 0000EH is specified for the absolute address here the area for the watchdog timer start register will be set at OOOOBH a location next to the ORG 0000EH WDTS BLKB WDC BLKB RMADO BLKA BLKB RMAD1 BLKA ORG 00020H SARO DARO TCRO DMOCON SAR1 DAR1 TCR1 DM1CON protect register Watchdog timer start register Watchdog timer control register Address match instruction register 0 Address match instruction register 1 Allocate areas even for locations where nothing is plac
141. ow to set fixed data in ROM For a description example refer to Section 4 1 5 Sample Program List 1 Initial Setting 1 FLOAT Sets 4 byte data DOUBLE Sets 8 byte data floating point floating point BYTE ees Sets 1 byte data integer WORD Sets 2 byte data integer ADDR Sets 3 byte data integer LWORD Sets 4 byte data integer Retrieving Table Data Figure 4 1 4 shows an example of a data table Figure 4 1 5 shows a method for accessing this table by using address register relative addressing DATA_TABLE Figure 4 1 4 Example for setting a data table MOV W 1 A0 LDE B DATA _TABLE A0 ROL Stores the data table s 2nd byte 34H in ROL DATA_TABLE BYTE 12H 34H 56H 78H Sets 1 byte data Figure 4 1 5 Example for retrieving data table 130 A Programming Style 4 1 Hardware Definition 4 1 4 Defining a Section Directive command SECTION declares a section in which a program part from the line where this directive command is written to the next SECTION is allocated Description Format of Section Definition SECTION section name section type ALIGN Specification in can be omitted A range of statements from one directive command SECTION to a position before the line where the next SECTION or directive command END is written is defined as a section Any desired section name can be set Furthermore one of section types DATA CODE or ROMDATA
142. ows Sections cannot be nested as they are defined Division of section a An interval from the line in which directive command SECTION is written to the line in which the next directive command SECTION is written b An interval from the line in which directive command SECTION is written to the line in which directive command END is written SECTION ram DATA Range of ram section BLKB 10 SECTION program Range of program section JSR sub1 SECTION sub1 Range of sub section nop MOV W 0 work RTS END Figure 3 2 1 Range of sections in AS30 system 101 Functions of Assembler 3 2 Method for Writing Source Program Types of Sections A type can be set for sections in which units memory addresses are managed The instructions that can be written in a section vary with each type of section Table 3 2 7 Types of Sections Content and Description Example CODE e This is an area where the program is written program area e All instructions except some directive commands that allocate memory can be written in this area e CODE type sections must be specified in the absolute module that they be located in the ROM area Example SECTION program CODE DATA e This is an area where memory whose contents can be data area changed is located e Directive commands that allocate memory can be written in this area e DATA type sections must be specified in the absolute module that they be located in the RAM area Exa
143. p men io 2 i 3 i 9 5 Ao 1 0 0 1 o o o 1 1 o o 1 1 0 1 Ao 91CDH T Address 1239H Bit Bit position Bit 5 is cleared Address position Figure 2 5 33 Calculation of bit position in address register relative addressing 44 CPU Programming Model 2 5 Addressing Modes 3 SB relative Example BCLR 5 0500H SB Since SB and base are addresses they are added directly Since bit is a number of bits it is shifted right three bits to calculate the address 0 1 O 0 SB ololo o o o o ololo o o o olo SB 0100H 0 5 0 Oo 5 base16 o 0 1 0 1 0 ofolo ojojofol o 1 bit dsp13 bit oi 6e i ee sB olololo ol1 1 ololololololojolo 1 o 1 SB 0600H 1 T Address 0600H Address Bit Bit position Bit 5 is cleared position Figure 2 5 34 Calculation of bit position in SB relative addressing 45 CPU Programming Model 2 2 5 Addressing Modes 2 5 5 Instruction Formats There are four instruction formats generic quick short and zero The assembler chooses one format from these four in order to reduce a number bytes in the operand as it generates code for the instruction Since the assembler has a function to optimize the generated code the user do not need to specify Only when it is desirable to specify the format of the code generated by the assembler add a format specifier Instruction Formats 1 Generic format G The op code contains src and dest addressing informat
144. ption Function In AS30 programming it is possible to write structured statements using structured instructions This is called structured description in this manual Note that only the structured description function outline is described here For more information about AS30 refer to the AS30 User s Manual Programming Part The following explains AS30 structured description function e The assembler generates branch instructions in the assembly language that correspond to structured description instructions e The assembler generates jump labels for the generated branch instructions e The assembler outputs the assembly language generated from structured description instructions to an assembler list file when a command option is specified e Structured description instructions allow the user to choose a control block to be branched to by a structured description statement and its conditional expression A control block refers to a program section from one structured description statement not including substitution statements to the next structured description statement Types of Structured Description Statements In AS30 following 9 types of statements can be written Substitution statement The right side is substituted for the left side IF ELIF ELSE ENDIF statement hereafter called the IF statement This statement is an instruction to change the flow of control in one of two directions The direction in which control branches o
145. racter string to a When outputting a character string enclosed with double quotations to a file specify the file name following gt or gt gt The bracket gt creates a new file so a message is output to it If a file of the same name exists a message is overwritten in it The bracket gt gt outputs a message along with the contents of the file If the specified file does not exist it creates a new file Directive command FILE can be written in the file name Example ASSERT ASSERT ASSERT string gt sample dat string gt gt sample dat string gt FILE Specifies and references a temporary label Write in the line to be defined as a temporary label To reference a temporary label that is defined immediately before write 2 in the instruction operand To reference a temporary label that is defined immediately after write in the instruction operand Example a JMP 2 hr Q we 2 Indicates source file name information This command can be written in the operand of directive command ASSERT or INCLUDE If command option F is specified FILE is fixed to the source file name that is specified in the command line If the option is omitted the indicated source file name is the file name where FILE is written Example ASSERT INCLUDE ASSERT sample gt FILE FILE inc sample gt FILE mes Concatenates character string
146. re 3 2 4 shows the relationship of various types of labels 106 Functions of Assembler 3 2 Method for Writing Source Program file1 a30 GLB versub port Declaration of label as global essential SECTION device ORG 40H Absolute labels in file1 BLKW 1 port Global it can be referenced from external file main Local SECTION program ORG 8000H Relocatable labels in file1 ver Global it can be referenced from external file JSR subi sub1 Global it references external file SECTION str ROMDATA j i BYTE program version 1 END file2 a30 GLB ver sub1 port Declaration of label as global essential SECTION program ORG OCO0OH Absolute labels in file2 sub1 Global it can be referenced from external file LDM W 0 A0 loop_s1 Local LDM B ver AO port Relocatable labels in file2 INC W AO ver Global it references external file port Global it references external file CMP B ver A0 0 JNZ loop_s1 RTS END Figure 3 2 4 Relationship of labels 107 Functions of Assembler 3 3 2 Method for Writing Source Program 3 2 3 Directive Commands In addition to the M16C 60 series machine language instructions the directive commands of the AS30 system can be used in the source program Following types of directive commands are available This section explains how to use each type of directive command e Address control command To direct address determination when assembling the program e Assemble contr
147. ressing can be used for the stack frame that is created when calling a function as shown in Figure 2 5 11 Since the local variable area in the stack frame is located in the negative direction of addresses FB relative addressing is needed because it allows for access in both positive and negative directions from the base lt Accessing local variable area gt Stack area i The number of bytes used is allocated by the ENTER instruction Prete re rarer erat G Lee ere Old FB upper Stack frame Return address lower Return address upper Argument Xy X Figure 2 5 11 Application example of FB relative addressing 31 CPU Programming Model 2 5 Addressing Modes Stack Pointer Relative SP Relative In this addressing mode the value of SP plus dsp or the value of the SP register minus dsp is the effective address to be operated on This addressing mode can only be used in the MOV instruction Note that the immediate cannot be transferred in this mode The range of effective addresses is 00000H to OFFFFH If the addition result exceeds OFFFFH the most significant bits above and including bit 17 are ignored Symbol dsp 8 SP 1 When dsp is a positive value Example MOV B ROL 5 SP Relative address range 0 to 127 FFFFFH Figure 2 5 12 SP relative addressing 1 2 When dsp is a negative value Example MOV B ROL 5 SP RO Relative address range 128 to 0 Figure 2 5 13 SP rel
148. rns from subroutine Because this is a relative attribute section label addresses remain unfixed until files are linked Therefore forcibly encode it in SB register relative addressing using SBSYM Caution Before specifying data with SSBSYM FBSYM check to see that the data is within the SB FB relative addressing range Figure 4 4 4 Divided file 3 SUB_1 A30 159 Programming Style 4 4 4 Dividing Source File Making Use of Include File Normally write part of external reference specification of symbols and bit symbols those defined with EQU BTEQU and or labels those having address information in one include file In this way without having to specify external reference in each source file it is possible to externally reference symbols and labels by reading include files into the source file 1 Example for referencing symbols File a SYMBOL INC INCLUDE SYMBOL INC ON EQU 1 OFF EQU 0 RAMTOP EQU 00400H RAMEND EQU 02BFFH SECTION WORK DATA 4 2 Example for referencing global labels File p An INCLUDE GLOBALING r GLB WORK 1 8 GLB WORK_2 GLB WORK_3 SECTION WORK DATA GLB WORK_4 GLB DATA TABLE GLOBAL INC Figure 4 4 5 Example of include file 160 Programming Style 4 4 4 Dividing Source File Making Use of Directive Command LIST By writing directive commands LIST ON
149. rrow and the other without a borrow The S Z and C flags change state when the decimal subtract instruction is executed Figure 2 6 7 shows an example of how these instructions operate Table 2 6 8 Decimal Subtract Instruction Mnemonic Description Format Explanation src dest Subtract in decimal not including src dest borrow src dest Subtract in decimal including src dest borrow DSUB 2digits 78 11 67 4 digits 1234 1111 0123 1000 s 100 s 10 s 1 s 10 s place 1 s place place place place place _ ojl e 7 loJLo i 273 C flag C flag DSBB 2 digits 78 11 Cflag 1 66 4digits 1234 1111 C flag T 0122 1000 s 100 s 10 s 1 s 10 s place 1 s place place place place place 7 8 Lo lo Lo Ti 2 2 C flag C flag Figure 2 6 7 Typical operations of decimal subtract instructions 71 CPU Programming Model 2 6 Instruction Set Add Subtract amp Conditional Branch Instruction This instruction is convenient for determining whether repeat processing is terminated or not The values added or subtracted by this instruction are limited to 4 bit immediate Specifically the value is 8 to 7 for the ADJNZ instruction and 7 to 8 for the SBUNZ instruction The range of addresses to which control can jump is 126 to 129 from the start address of the ADJNZ SBJNZ instruction Figure 2 6 8 shows an example of how the add subtract amp conditional branch instruction works
150. rrupt enable flag Setting interrupt control register 3 4 5 Saving and restoring register in interrupt handler routine 4 3 1 Setting Interrupt Table Register The start address of variable vectors can be specified by the interrupt table register INTB The variable vector area is comprised of 256 bytes four bytes per vector beginning with the address specified in the interrupt table register Each vector is assigned a software interrupt number ranging from 0 to 63 142 Programming Style 4 4 3 Setting Interrupts 4 3 2 Setting Variable Fixed Vectors When an interrupt occurs the program jumps to the address that is preset for each interrupt source This address is called the interrupt vector To set interrupt vectors register the start address of each interrupt handler program in the variable fixed vector table For an example of how the vectors actually are registered refer to Section 4 3 6 Sample Program List 3 Software Interrupt Variable Vector Table The variable vector table is a 256 byte interrupt vector table with its start address indicated by a value in the interrupt table register INTB This vector table can be located anywhere in the entire memory space One vector consists of four bytes with each vector assigned a software interrupt number from 0 to 63 INTB E Software interrupt 4 number Figure 4 3 1 Variable vector table 143 Programming Style 4 3
151. rt Bit 1 of short addr_b2 BTEQU 2 addr Bit 2 of addr long_b3 BTEQU 3 long Bit 3 of long E POG ram area KKK KK KKK KK KKK K KKK KK KEK KKK RRR KERR KERR Declaration to the assembler j Startup SECTION PROGRAM CODE Declares section name and section type ORG ROM_TOP Declares start address SB SB_BASE Declares SB register value to the assembler ER EB BASE Declares FB register value to the assembler Values declared LDC RAM_END 1 ISP Sets initial value in stack pointer Bee LDC SB_BASE SB Sets initial value in SB register LDC FB_BASE SB Sets initial value in FB register 133 Programming Style 4 1 Hardware Definition MOV B 03H PRCR Removes protect MOV W 0007H PMO Sets processor mode registers 0 and 1 MOV W 2008H CMO Sets system clock control registers 0 and 1 MOV B 0 PRCR Protects all registers LDC 0 FLG Sets initial value in flag register 0FFFOH PUR1 Connects internal pull up resistors MOV W 0 RO Clears WORK_RAM to 0 MOV W RAM_END RAM_TOP 2 R3 pues nached MOV W WORKRAM_TOP A1 to hardware and SSTR W the contents selected in programming MAIN MOV B DATA _TABLE A0 ROL MOV W 1234H R1 BSET char_b0 JMP MAIN dummy REIT SECTION CONSTANT ROMDATA Declares section name and section type ORG XXXXX Declares start address Must be matched to ROM area DATA_TABLE i
152. rves as the base is used for access in this mode it is necessary to set the base address before this addressing mode can be used For a setup example refer to Section 4 2 7 Sample Program List 2 Initial Setting ST 4 2 4 Setting Interrupt Table Register INTB The interrupt vector table in the M16C 60 M16C 20 series is variable Therefore the start address of vectors must be set before using an interrupt For a setup example refer to Section 4 2 7 Sample Program List 2 Initial Setting 2 136 Programming Style 4 2 Initial Setting the CPU 4 2 5 Setting Variable Fixed Vector There are two types of vectors in the M16C 60 M16C 20 series variable vector and fixed vector For details on how to set these types of vectors when using interrupts and about measures to prevent the program from going wild when not using interrupts refer to Section 4 2 7 Sample Program List 2 Initial Setting 2 l 4 2 6 Setting Peripheral Functions The following explains how to initial set the RAM ports and timers built in the M16C 60 M16C 20 series For more information refer to functional description in the user s manual of your microcomputer Initial Setting Work Areas Normally clear the work areas to 0 by initial setting If the initial value is not 0 set that initial value in each work area Figure 4 2 1 shows an example for initial setting a work area 0FFH char 0OFFFFH short OFFFFH addr 0OFFH addr 2 OFFFFH lon
153. s before and after 113 This command can be written a number of times in one line If the concatenated character strings are going to be used as a name do not enter a space or tab before and after this command Example ASSERT sample gt FILE dat Following macro definition is also possible mov_nibble MACRO p1 src p2 dest MOV p1 p2 src dest ENDM Functions of Assembler 3 2 Method for Writing Source Program Conditional Assemble Directive Commands Usage and Description Example Indicates the beginning of conditional assemble Always be sure to write a conditional expression in the operand Example AF TYPE 0 BYTE Proto Type Mode TYPE gt 0 BYTE Mass Production Mode ELIF ELSE lt BYTE ENDIF Debug Mode Rules for writing conditional expression The assembler does not check whether the operation has resulted in an overflow or underflow Symbols cannot be forward referenced e symbols defined after this directive command are not referenced If a forward referenced or undefined symbol is written the assembler assumes value 0 for the symbol as it evaluates the expression Typical description of conditional expression sym lt 1 sym lt 1 sym 2 lt data1 sym 2 lt data1 2 smp1 name Indicates condition for conditional assemble Always be sure to write a conditional expression in the operand This directive command can be written a number of times in one conditi
154. s machine language file TEST MOT from the absolute module file DEBUG X30 184 MITSUBISHI SINGLE CHIP MICROCOMPUTERS M16C 60 M16C 20 Series Programming manual lt Assembler language gt Rev A July First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp Kitaitami Works This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1998 MITSUBISHI ELECTRIC CORPORATION
155. saved to the stack area d The interrupt request bit for the accepted interrupt is reset to 0 e The interrupt priority level of the accepted interrupt is set to the processor interrupt priority level IPL f The address written in the interrupt vector is placed in the PC register lt Stack status after interrupt request is accepted gt ISP USP gt PC low PC middle FLG lower FLG PC s 4 most significant bits are stored here lt FLG status after interrupt request is accepted gt b15 bO LPL U I OB SZDC Aal Priority level of each accepted interrupt is stored here X ol Hol No change Figure 4 3 6 When an interrupt of software interrupt number 32 to 63 occurs Note If multiple interrupts of the same interrupt priority level that is set in software occur simultaneously during execution of one instruction the interrupts are accepted according to hardware interrupt priority levels Example The following lists the M16C 60 group hardware interrupt priority levels INT1 gt Timer B2 gt Timer BO gt Timer A3 gt Timer A1 gt INT2 gt INTO gt Timer B1 gt Timer A4 gt Timer A2 gt UART1 receive gt UARTO receive gt A D conversion gt DMA1 gt Timer A0 gt UART1 transmit gt UARTO transmit gt Key input interrupt gt DMAO 152 Programming Style 4 4 3 Setting Interrupts 4 3 8 Multiple Interrupts When one interrupt is enabled in normal interrupt handling the
156. t A 32 bit register consisting of two concatenated 16 bit registers is the subject on which operation is performed Register pairs R2RO and R3R1 can be used in SHL logical shift and SHA arithmetic shift instructions Register pairs R2RO R3R1 and A1A0 can be used in JMPI indirect jump and JSRI indirect subroutine call instructions Symbol R2R0 R3R1 AT AO Figure 2 5 15 32 bit register Example SHL L 4 R2R0 A 32 bit value in R2R0 is shifted by 4 bits to the left E Number of times the bits are shifted Example JMPI A R2RO0 Control jumps to the effective address 20000H indicated by the value in R2RO0 00000H 08000H JMPI A R2R0 pang 0002H 0000H l Le 20000H 1 Mbytes of memory space FFFFFH Figure 2 5 16 32 bit register direct addressing Control Register Direct This is an addressing mode where a control register is accessed This addressing mode can be used in LDC STC PUSHC and POPC instructions Symbol INTBL INTBH ISP SP SB FB FLG Note If SP is specified operation is performed on the stack pointer indicated by the U flag 35 CPU Programming Model 2 5 Addressing Modes 32 Bit Address Register Indirect A 32 bit value of two concatenated address registers is the effective address to be operated on The range of effective addresses is 00000H to FFFFFH If the value of the concatenated registers exceeds FFFFFH the most significant bits above and including bit 21 are ignored
157. t processing enger Interrupt sequence 7 Instructions in interrupt routine ee of suspended KE K 18 to 20 cycles No interrupt but a reset is accepted when executing the interrupt sequence Figure 2 7 3 Interrupt sequence 2 Note These include flag register and processor interrupt priority level 87 CPU Programming Model 2 2 7 Outline of Interrupt MEMO 88 Chapter 3 Functions of Assembler 3 1 Outline of AS30 System 3 2 Method for Writing Source Program Functions of Assembler 3 3 1 Outline of AS30 System 3 1 Outline of AS30 System The AS30 system is a software system that supports development of programs for controlling the M16C 60 M16C 20 series single chip microcomputers at the assembly language level In addition to the assembler the AS30 system comes with a linkage editor and a load module converter This section explains the outline of AS30 Functions e Relocatable assemble function e Optimized code generating function e Macro function e High level language source level debug function e Various file generating function e IEEE 695 format file generating function Configuration The AS30 system consists of the following programs e Assembler driver as30 This is an execution file to start up the macroprocessor and assembler processor This assembler driver can process multiple assembly source files e Macroprocessor mac30 This program processes macro directive commands in th
158. ted Example PAGE PAGE PAGE strings strings Specifies a number of columns and number of lines in one page of a list file Branch Instruction Optimization Control This command can be written a number of times in one assembly source file Symbols can be used to specify the number of columns or lines Forward referenced symbols cannot be used however If this specification is omitted the list file is output with 140 columns and 66 lines per page Example FORM FORM FORM FORM 20 80 60 100 line culmn Usage and Description Example Controls optimization of branch instruction and subroutine call Various items can be written in the operand here such as those for optimum control of a branch instruction and selection of an unconditional branch instruction or subroutine call instruction to be excluded from optimization These items can be specified in any order and can be omitted If omitted the initial value or previously specified content is assumed for the jump distance Example Following combinations of operands can be written OPT OPT OPT OPT OPT OPT OPT OPT OPT OFF ON ON JMPW ON JMPW JSRW ON JMPA ON JMPA JSRW ON JMPA JSRA ON JMRW ON JMRA 112 Functions of Assembler 3 2 Method for Writing Source Program Extended Function Directive Commands Usage and Description Example ASSERT file or standard error output device Outputs a specified cha
159. terrupt Register bank 0 Returns from interrupt H Figure 4 3 2 Saving and restoring registers in interrupt handling Note If both register banks 0 and 1 are used in the main program the method for saving and restoring registers by register bank switchover cannot be used 146 Programming Style 4 4 3 Setting Interrupts 4 3 6 Sample Program List 3 Software Interrupt The INTO instruction overflow interrupt is a software interrupt where an interrupt is generated by executing this instruction when the overflow flag is set to 1 Figure 4 3 3 shows an example for using this software interrupt skkkkkkkkkkkkkkkkkkkkkkk inelo can ee kk a INCLUDE m30600 inc H kkkkkkkkkkkkkkkkkkkkkkkk m AE kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Symbol definition RAM_TOP EQU 00400H Start address of RAM RAM_END EQU 02BFFH End address of RAM ROM_TOP EQU OFO000H Start address of ROM VECT_TOP EQU OFFFOOH Start address of variable vector FIXED_VECT TOP EQU OFFFDCH Start address of fixed vector SB_BASE EQU 00380H Base address of SB relative addressing FB_BASE EQU 00480H Base address of FB relative addressing H skkkkkkkkkkkkkkkkkkkkkkk 7 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Allocation of work RAM area SECTION WORK DATA ORG RAM_TOP WORKRAM_TOP WORK_1 BLKW 1 WORK_2 BLKB 1 ANS L BLKW 1 ANS_H BLKW 1 WORKRAM_END SORES Dro ram ATEA TEENAAN WEE le E SECTION PROGRAM CODE
160. this case the internal RAM holds the contents that were stored in it immediately before the system was reset Before this facility can be used the start address of the interrupt handling program must be set to the interrupt vector of the watchdog timer interrupt When resetting the system to restart the program be sure to use a software reset If the same value address as the reset vector happens to be set to the interrupt vector of the watchdog timer interrupt the IPL processor interrupt priority level remains 7 without being cleared Consequently all other interrupts are disabled and remain disabled when the program is restarted after being reset 170 Programming Style 4 5 A Little Tips Examples of Runaway Detection Programs Figures 4 5 6 and 4 5 7 show sample programs in which the watchdog timer is used to detect program runaway Example 1 Operation subroutine for writing to the watchdog timer start register is executed periodically at predetermined intervals WDT_SET Define address with EQU in advance MOV B ROL WDTS Writes to watchdog timer start register RTS Because no arbitrary value can be written to the watchdog timer start register the value of ROL can be indeterminate Figure 4 5 6 Example of runaway detection program 1 Example 2 Interrupt handling program to restart the system is executed when a watchdog timer interrupt occurs WDT_INT LDC 00380H SB Hoe
161. tion on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Mitsubishi Electric Corporation by various means including the Mitsubishi Semiconductor home page http www mitsubishichips com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss resulting from the information contained herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi E
162. tions 4 Bit Transfer Instruction This instruction transfers 4 high order or low order bits of an 8 bit register or memory This instruction can be used for generating unpacked BCD code or I O port input output in 4 bits The mnemonic placed in Dir varies depending on whether the instruction is used to transfer high order or low order 4 bits When using this instruction be sure to use ROL for src or dest Table 2 6 1 4 Bit Transfer Instruction Mnemonic Description Format 7 Explanation Transfer src dest 4 high order bits src 4 high order bits dest MOVDi src dest 4 high order bits src 4 low order bits dest H src dest 4 low order bits src 4 high order bits dest src dest 4 low order bits src 4 low order bits dest Note Either src or dest must always be ROL 64 CPU Programming Model 2 6 Instruction Set Conditional Store Instruction This is a conditional transfer instruction that uses the Z flag state as the condition of transfer This instruction allows the user to perform condition determination and data transfer in one instruction There are three types of conditional store instructions STZ STNZ and STZX Figure 2 6 1 shows an example of how the instruction works Table 2 6 2 Conditional Store Instruction Mnemonic Description Format Explanation Transfers src to dest STZ src dest when Z flag 1 Transfers src to dest STNZ src dest when Z flag 0 Transfers erc to d
163. to 4 high order bits in dest Transfers 4 low order bits in src to 4 low order bits in dest POP size dest Restores value from stack area POPM dest Restores multiple register values collectively from stack area PUSH size src Saves register memory immediate to stack area PUSHA srce Saves address in src to stack area PUSHM src Saves multiple registers to stack area LDE size src dest Transfers src from extended data area STE size src dest Transfers src to extended data area STNZ src dest Transfers src when Z flag 0 STZ src dest Transfers src when Z flag 1 src1 src2 dest XCHG size src dest Transfers src1 when Z flag 1 or src2 when Z flag 0 Exchanges src and dest 48 CPU Programming Model 2 6 Instruction Set a ROL register is selected for src or dest d ROL or ROH is selected b Can be selected from ROL ROH RiL orR1H e dsp 8 SB or dsp 8 FB is selected c Immediate is 8 bits Addressing em Flag change General instruction Special instruction 3 Immediate Register direct absolute 32 bit register direct 32 bit register indirect 20 bit register relative Control register direct dsp 20 A0 dest src dest src1 src2 49 Bit Manipulation Mnemonic BAND src C flag lt sre amp C flag CPU Pr
164. toring registers collectively POPM RO R1 R2 R3 A0 A1 Switching over register banks to save and restore registers This method will be effective when it is necessary to reduce the overhead time of interrupt processing a Using register bank 1 FSET B b Using register bank 0 FCLR B 145 Programming Style 4 4 3 Setting Interrupts Description of Interrupt Handling Program Figure 4 3 2 shows an example for writing an interrupt handling program KK KKK KK KK KKK kk kkk kk kk kkk kk kkk kk kk kkk EK socn Saving and restoring registers individually INT_AO PUSH B ROL Saves ROL PUSH B RiL Saves R1L PUSH W R2 Saves R2 If registers are saved individually be sure when s restoring them to reverse b the order in which they Restores R2 were saved Restores R1L Restores ROL Returns from interrupt CZ Interrupt handling KKK KKK KKK e KEK KEKE K KER KK KKK KER ek EEE ene Saving and restoring registers collectively INT_A1 PUSHM RO R1 R2 R3 Saves registers RO R1 R2 and R3 collectively Interrupt handling POPM RO R1 R2 R3 Restores registers RO R1 R2 and R3 collectively REIT Returns from interrupt H kk kkk kk k kkk kk kkk kkk TTT Switching over register banks to save and restore registers INT_A2 FSET B Register bank 1 In this case registers in bank 1 A RO R1 R2 R3 AO AT and mtemupt haneling FB are used in the in
165. uction execution under way and the processor enters an interrupt sequence beginning with the next cycle See Figure 2 7 2 However if an interrupt request occurs when executing a string instruction SMOVB SMOVF or SSTR or sum of product calculating instruction RMPA the operation of the instruction under way is suspended before entering an interrupt sequence See Figure 2 7 3 In the interrupt sequence first the contents of the flag register and program counter before the interrupt request was accepted are saved to the stack area and interrupt related register values are set When the interrupt sequence is completed the processor goes to interrupt processing Note that no interrupt but a reset is accepted when executing the interrupt sequence 1 Interrupt under normal condition Interrupt request generated Interrupt request accepted Interrupt processing p instruction Interrupt sequence H Instructions in interrupt routine c 18 to 20 cycles No interrupt but a reset is accepted when executing the interrupt sequence Figure 2 7 2 Interrupt sequence 1 2 Interrupt under exceptional condition If an interrupt request is generated when executing one of the following instructions the interrupt sequence occurs in the middle of that instruction execution 1 String transfer instruction SGMOVF SMOVB SSTR 2 Sum of product calculating instruction RMPA Interrupt request generated Interrupt request accepted Interrup
166. ure 3 1 1 schematically shows the assemble processing performed by the AS30 system a30 Assembly source file Relocatable module Assembler list file x file Cross reference file A Input file A Output file Absolute module file Motorola S format Intel HEX format Absolute list file file file NJ NJ Figure 3 1 1 Outline of assemble processing performed by AS30 91 Input output Files Handled by AS30 Functions of Assembler 3 1 Outline of AS30 System The table below separately lists the input files and the output files handled by the AS30 system Any desired file names can be assigned However if the extension of a file name is omitted the AS30 system automatically adds a default file extension These default extensions are shown in parenthesis in the table below Table 3 1 1 List of Input output Files Input File Name Extension Assembler Source file as30 Include file Linkage editor Relocatable module file In30 Library file Load module converter Absolute module file Imc30 Librarian Relocatable module file Ib30 Library file Cross referencer Assemble source file xrf30 Assembler list file Absolute lister Absolute module file abs30 Assembler list file 92 Output File Name Extension Relocatable module file Assembler list file Assembler error tag file Absolute module file Map file Link error tag file Motorola S format file Extended Intel HEX format file Library file Relocatable mo
167. urn address high high Argument 2 Argument 2 Argument 1 Argument 1 Automatic Automatic variable of variable of main main Figure 2 6 19 Typical operation of stack frame clean up instruction 82 CPU Programming Model 2 2 6 Instruction Set 2 6 8 OS Support Instructions These instructions save and restore task context They execute context switching required for task switchover in one instruction OS Support Instructions There are two types of instructions STCTX and LDCTX The STCTX instruction saves task context The LDCTX instruction restores task context Figure 2 6 20 shows a context table of tasks Use the context table s register information to specify whether register values be transferred to the stack area Use the SP correction value to set the register bytes to be transferred The OS support instructions save and restore task context to and from the stack area by using these pieces of information Table 2 6 20 OS Support Instructions Mnemonic Description Format Explanation STCTX abs16 abs20 Saves task context LDCTX abs16 abs20 Restores task context Note 1 abs16 indicates the memory address where task number 8 bits is stored Note 2 abs20 indicates the start address of the context table Register information of task number 0 Start address of context table SP correction value of gt task number 0 Z S Register information of Bit configuration of register information task
168. ve command SECTION is written Example SECTION program CODE ALIGN or SECTION program CODE ALIGN 103 Functions of Assembler 3 2 Method for Writing Source Program Address Control by AS30 System The following shows how an assembly source program written in multiple files is converted into a single execution format file Address control by as30 a For sections that will be assigned the absolute attribute the assembler determines absolute addresses sequentially beginning with a specified address b For sections that will be assigned the relative attribute the assembler determines addresses sequentially for each section beginning with 0 The start address of all relative attribute sections are 0 Address control by In30 Sections of the same name in all files are arranged in order of specified files Absolute addresses are determined for the arranged sections sequentially beginning with the first section The start addresses of sections are determined sequentially for each section beginning with O unless otherwise specified Different sections are located at contiguous addresses unless otherwise specified Address values determined by as30 FILE1 00000 Absolute module file Address values determined by f SECTION A In30 Operand values of ORG i SECTION B SECTION A 00900 ORGE H 00000 SECTION A SECTION C E SECTION B ORG GR 00000 RS SECTION B SECTION A Operand values of ORG
169. ved and restored to and from the stack refer to Section 4 5 2 Stack Area e PC program counter e FLG flag register Always be sure to use the REIT instruction to return from the interrupt handler routine After the interrupt processing is completed this instruction restores the registers return address etc from the stack thus allowing the main program to restart processing where it left off In addition to the automatically saved registers there may be some other register which is used in the interrupt handler routine and therefore whose previous content needs to be retained If there is a such a register save it to the stack in software For an example of how registers are saved and restored in the interrupt handler routine refer to Section 4 3 6 Sample Program List 3 Software Interrupt Methods for Saving and Restoring Registers If in addition to the automatically saved registers there is any register which is used in the interrupt handler routine and therefore whose previous content needs to be retained save it to the stack area in software There are two methods for saving and restoring this register The following shows the processing procedure for each method 1 Using push pop instructions to save and restore registers 1a Saving registers individually PUSH B ROL PUSH W_ Rit 1b Restoring registers individually POP B ROL POP W R1 2a Saving registers collectively PUSHM RO R1 R2 R3 A0 A1 2b Res

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