Introduction to ModelSim 6.0 Debug GUI
Contents
1. of ModelSim s powerful TCL commands and standard TCL TK commands ModelSim SE is packaged with a full TCL TK interpreter command line New GUI in ModelSim 6 0 1 Debug Windows in ModelSim 6 0 There are ten debug windows including Active Process Assertions Dataflow Functional Coverage List Local Memory Monitor Objects and Wave windows In addition there are tools such as Code Coverage and the new Memory and Performance Profiler with their respective user interfaces Chapter 12 of the ModelSim User s Manual has more information on profiling performance and memory utilization during elaboration and simulation Chapter 13 of the ModelSim User s Manual has more details on measuring code coverage The Main window is laid out into a workspace area the MDI pane and Transcript window In the Workspace area of the Main window there are tabs for Library Structure Project Files Memories and Compare tabs depending on how ModelSim is used The figure below shows the new layout of the ModelSim GUI J ModelSim SE PLUS 6 0 File Edit Wew Format Compile Simulate Add Tools Window Help Oe OS SBS MES ame tT om HO ey ml om ai X i GQ Bo Design unit top wishbone B mimt mim D iha bi cup af hup eat tup i eth memory eth memory eth host eth host RALWAYSHS top 796 797 begin PROCESS 2 798 wait top endpoint small pkt gt 5 799 lispley Mininse SMALL PACK2. ck gen tb mac se ScMethod mA top wbl mem sl wb dat o Ha teset_gen tb mac sc ScThread mA op wbl mem sl wb dat i LD main tb mac se ScThread Bie mi4 t0p wbl mem sl wb sel i IEAI H HASSIGN 36 top Process tod HASSIGNHS7 top Process gt Ssi P B gt gt 8 EEE E dR Ei esi wove C mp3 decoder h hJeth memory sv Clmp3 decoder cpp Transcript gt gt gt 0 Hr Loading work sysc eth memory Loading work sysc systemc so Loading work sysc tb mac se Loading work sysc mp3 decoder SIM 3 gt view mdiwave main_pane mdi interior cs vm paneset cli_O SIM 4 gt do sysc_wave do SIM 5 gt edit tb sysc mp3_decoder cpp VSIM 6 gt 4 Now Ons Delta O sim top i_eth_memory mp3 A You can also add all the signals in a particular region hierarchical block to the Wave window Select the region e g top in the Sim tab do a RMB click to open a popup menu and select Add gt Add to Wave This opens the Wave window and adds the signals from the region test ringbuf Select block1 in the Sim tab of the Main window Go to the Objects window and drag and drop the signal clock to the Wave window Select block2 in the Sim tab of the Main window and drag and drop the signal reset from the Object window to the Wave window You can also add signals using add wave command ModelSim uses a proprietary database for storing simulation information called the w f database This information
3. is tight integration between all the debug windows within ModelSim This integra tion allows you to find the sources of bugs faster during debug New GUI in ModelSim 6 0 7 N ModelSim SE PLUS 6 0 File Edit view Format Compile Simulate Add Tools Window Help JUEN ODS GRATA sn nu QQQkx CHAM Workspace HDX wave default 2 x ri Instance Design unit Design unit tyr EB op ethtop cover_seq_n1156 B A wb wishbone Interface m Aop ethtop cover seq n1340 mp i de E top ethtop cover_seq_n1500 Jf top mp3 decoder Top mp3 ScModule Endpoint FrameDropped te reset pulse mp3 decoder ScThread 4 Aop endpoint dropped frame stream mem proc mp3 decoder ScThread PHY signs Ho HASSIGNHE2 eth_memory Process Prarie Had ASSIGNHES eth memory Process x yell tat E sassiantiss eth memory Process Meee top MRD Had HASSIGNHE7 eth memory Process A Hab ASSIGNHES eth_memory Process Ea Rop MRsD Hab HASSIGNHES eth memory Process Aopithis_field Ho HASSIGNH7O eth memory Process Ree N Lo sessions eth memory Process a a at Lo s assiana7s eth memory Process PERSA o E Had HASSIGNH77 eth memory Process Nop i eth memory p w a Lg ASSIGNH7B eth memory Process AOLE memow np si GHJ tb mac sc tb mac se ScModule Atop i eth memory mp mp J wb_ck sc clock ScModule F ck sc clock ScModule W te ck se clock ScModule EA Aop wbl mem sl wb adr i Ha
4. of an executable line ModelSim will automatically enable C debugging by starting and connecting to gdb in the background if gdb is not already started It then sets the breakpoint at the requested line number You must compile your C C code with the g option to enable debugging You can setup both HDL and SystemC breakpoints and both will be managed by the ModelSim UI When debugging the initialization phase of FLI PLI VPI based C C code you have to start the C debug interface manually by clicking on Tools gt C debug gt Start C Debug and by clicking on Tools gt C debug gt Init Mode so that user has the opportunity to set breakpoints on initial ization functions before they are run as ModelSim goes through its elaboration loading phase Chapter 16 C Debug of the online ModelSim User s Manual has a section that goes into details You can set a breakpoint on source cpp files as well as h files To do this open a cpp or h file containing C C code in the ModelSim Source window and click on an executable line A red dot will appear to the left hand side before the line number A solid red dot indicates that the breakpoint is enabled while a hollow red dot indicates that the breakpoint is disabled You can enable disable or delete this breakpoint by clicking on the RMB right mouse button and selecting from the options in the popup menu that opens You can also use the ModelSim com mand bp c to set C C break points You
5. support in ModelSim for SystemVerilog SystemC and PSL Within this environment there is source level debug for C C based PLI VPI DPI FLI and SystemC code just as there has been for HDL In addition there is full visibility in the GUI for SystemC based models The following SystemC primitive channels can be debugged in the GUI sc_signal aggregates of sc_signal ports of sc_signal sc_fifo ports of sc_fifo sc_mutex and sc_semaphore You can also view these primitive channels in the List and Wave windows The familiar ModelSim debug commands such as bp examine show tb bd step etc can be used for both HDL and SystemC source level debug Providing all the debug capabilities within one environment improves verification performance reduces the learning curve associated with using multiple tool chains and improves your debug productivity For more information call us or visit www model com Copyright 2004 Mentor Graphics Corporation This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposed only provided that this entire notice appears in all copies In accepting this document the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information Mentor Graphics is a registered trademark of Mentor Graphics Corporation All other trademarks are the property of their respect
6. will need to invoke it as bp c lt function name gt lt file_name gt lt line gt lt line gt 0x lt hex_address gt in order to set breakpoints in C C Chapter 16 of the online ModelSim User s Manual has more information on C Debug New GUI in ModelSim 6 0 5 Z ModelSim SE PLUS 6 0 File Edit Mew Format Compile Simulate Add Tools Window Lae Ge Gtk Se BD gt dA ES demo ifg_len 38 break case LONG IFG cout lt lt L mre lt lt endl ifg_len 100 break case SHORT_IFG cout lt lt short IPG lt lt endl ifg_len 5 break case RANDOM IFG cout lt lt Random IFG lt lt endl random ifg len gt next ifg len random ifg len for i 0 i lt ifg len i wait mix clk posedge event pkt tupe gt next switch pkt type case SEND MP3 cout lt lt sending HP Packet lt lt endl payload size gt mext siz ent payload size nu siz ent cout lt lt nu siz ont lt lt bytes sent lt lt ont lt lt frames lt lt endl pkt preamble DOSEBESESSESEESS pkt sfd 0x0d 0x500423bci2Zce View Declaration Most of the debug TCL commands available for View Instantiation HDL debugging are also available for SystemC EEE debugging For instance you can at anytime examine Create Wave ss ji F ae the current value of sc signal sc mutex or sc_fifo Eoey Log primitive channel objects using the examine
7. APPLICATION NOTE Introduction to ModelSim 6 0 Debug GUI www model com ModelSim Introduction to the New GUI ModelSim provides an Integrated Debug Environment that facilitates efficient design debug for SoC and FPGA based designs This GUI has continuously evolved to include new windows and support for new languages This application note aims to give an introduction to the ModelSim 6 0 debug environment This environment is trilingual supporting designs based on VHDL Verilog all standards including SystemVerilog Verilog 2001 and Verilog 1995 and SystemC Subsequent releases of ModelSim will enable even more debug capabilities support ing higher levels of abstractions for verification and modeling in SystemVerilog and SystemC In ModelSim 6 0 the GUI has been enhanced and is based on Multiple Document Interface MDI layout standard In addition the debug windows have been re organized in such a way as to display design data and simulation results in an intuitive manner The primary reason for updating the GUI in ModelSim 6 0 is to provide support for new data types and design structures introduced by ModelSim s support for new languages such as SystemVerilog SystemC and PSL At the same time utilize the screen real estate more effi ciently there by facilitating debug with fewer windows To illustrate some of the debug capabilities we will be using a design modeled using SystemC SystemVerilog and Verilog The design under verific
8. ET TARGET REACHEDi n n stime 800 mp stop 801 set dis Structure that feeds stream mp3 file the veig 1 ii nea Ajorribnrion nf marker sivos eaa O Note Loverage event cover sendmp3 Eeri ee Line 943 covered Tine 437086 res Ieicliura 1 Iristarma Aup tdh jt Note Coverage event cover seq n 28 Fie SE Dethieth 1 top sv Line 1008 covered Time 437216 ns Iteratiort 1 Instance Aop ethtop Note Coverage event cover pkl small File ee 1 top sv Line 1009 covered R Time 437216 ns iterator Instance Aop etht 437216 ns SMALL PACKET TARGET REACHED Now 437 216 ns Delta 1 sim ftop tb_rmac The Structure tab named sim now displays HDL and SystemC processes In previous versions of ModelSim there was a process window that showed this information All hierarchical blocks such as SystemC SC_Module VHDL entity architecture Verilog Modules and SystemVerilog Interface blocks appear as squares while processes appear as spheres Tasks and Functions appear as squares also All VHDL objects are colored navy blue while SystemC and SystemVerilog Verilog are colored green and sky blue respectively 2 New GUI in ModelSim 6 0 In ModelSim 6 0 the memory browser is now integrated into the workspace area It appears as a tab named Memories All HDL memories are automatically extracted and displayed in this browser ModelSim simply looks for a two or more dimensional array in sourc
9. ace sev smart ptr lt so uint lt 48 gt gt random src miim Interface Sov snart ptr lt sc_uintt8 gt gt random data scv_smart_ptr lt packet_type gt pkt_type i_eth_cop eth cop Module sov smart ptr lt ifg A its type 44 sov_bag lt ifg gaps gt if ethtop eth top Module sov rpagcpacket opel Facket dist i_eth_memory eth_memory Module br sovbag lt int gt pkt size dist th rmac sc tb rmac sc ScModule a am write ETK MODER ETH_MODER_RXEN ASSIGN 36 top Process een EENE MODEN NUSEI ASSIGN 37 top Process ETH_MODER_CRCEN ETH_MODER_PAD ALWAVS 114 top Process ETH_MODER_FULLD wb_read ETH_MODER Oxf nul filep fopen zd ie status Hen ah ca fakes mp3sz ftell filep status fseek fileP OL SEEK SET buf new char mp3sz status fread but sizeof char mp3sz filer if status mp3sz cout lt lt pel Estas W lt lt status the same as mpisz lt lt mpSsz lt lt lt lt endl si tos o talos Filep cout lt lt n n Receive an MPS file in a stream of Ethemet Fackets n cout lt lt Interleaved with other randomized ethernet traffic noise n cout lt lt and with randomized interframe gaps cout lt lt A PSL endpoint spots dropped frames and triggers a retranenitya n cout lt lt MPS file is lt lt mp3sz lt lt bytes lt lt endl mp3sz Ignore the EOF byte KKK for i 0 i lt 100 i wait mrx_olk posedge_event pkt_size dist ada
10. appears when your pointer s cursor hovers on a SystemC signal in the Source window Another way of showing the value of an HDL SystemC or C C variable or signal at current simulation time is as fol lows Select the variable or signal of interest in the Source window Click on Edit gt Advanced gt Examine in the Main window s menu bar and a popup window will appear showing the current value for the signal or variable at current simulation time or in the Source window do a RMB click and a popup menu will appear Select Examine and a popup window will appear showing the current value for the signal or variable at current simulation time Using the Wave Window and List Window The Wave window allows you to view the results of simulation It also allows you to view assertion status and PSL cover statement status and count All objects are indicated as dia monds in the respective language colors The exception is for PSL cover statements and associated endpoints which are indicated by purple chevrons ModelSim 6 0 expands the SystemC primitive channels that can be visualized in the Wave window In addition to being able to view SystemC sc_signal and ports of sc_signal you can now view aggregates of sc signal including structures classes and arrays of sc signal You can also view sc fifo and ports of sc fifo in this window You can view virtual items indicated by orange diamonds and comparison items indicated by yellow diamonds in this w
11. ation is an Open Source Ethernet MAC IP from Opencores org The testbench is modeled using SystemVerilog The testbench sends Ethernet packets through a PHY interface to the Ethernet MAC RX block The MAC is con nected to two wishbone busses via a crossbar switch The master wishbone bus is connected to a host interface and the slave wishbone bus is connected to a behavioral MP3 decoder modeled in SystemC The Host sets up the MAC RX registers via the wishbone master bus This pre pares the MAC for receiving Ethernet packets from the testbench When the MAC RX block receives a packet it is forwarded to a memory interface which is modeled as a MP3 Decoder SystemC High level model via the slave wishbone bus There is also a similar testbench described in SystemC using SCV Library capabilities such as random stimulus generation ModelSim requires that SystemC stubs be created for all HDL VHDL SystemVerilog and Verilog design units instantiated under SystemC Please refer to the Application note titled SystemC Verification with ModelSim for details of ModelSim s SystemC support in Version 6 0 Launch ModelSim in GUI mode by typing vsim or vsim gui on the command prompt Most tasks that can be done via the GUI have equivalent TCL commands useful for running scripts during regressions in batch mode or command line mode Since ModelSim s interface is based on TCL TK users can very quickly extend their verification environment using a combination
12. can be used for post simulation debug in the Wave window or List window or it can be used for interactive debug The commands used for logging include add wave add list add dataflow and add log The first three commands open the appropriate window add the signals to that window and log them automatically in the wlf database The default database created is called vsim w f The designer has control of how much data to log Please refer to the Chapter on WLF Files datasets and Virtuals in the ModelSim User s Manual for more information ModelSim also supports VCD file creation New GUI in ModelSim 6 0 To run the simulation of the example above type the following in the Transcript window VSIM gt run all The simulation breaks on line 248 of tb rmac sc cpp and we have used step over command to step up to line 274 Line 275 will be executed next if we issue another step over command in the Transcript window Also since the breakpoint is in C C code the ModelSim prompt changes in the transcript window from VSIM gt to CDBG gt Zi Modelsim SE PLUS 6 0 File Edit Mew Format Compile Simulate Add Tools Window Os MS BAO we 41 Bes mw BRR R comm z enamn home gabrielcidemos DAC_2004 Suite_DACdemo_0406_SB tb sysc tb_rmac_sc cpp Design unit top sow smart ptr lt sc uintc48 gt gt rand dest r sov_smart_ptr lt int gt papload_size random_ifg_len random_len wishbone Interf
13. com Find mand This works whether or not you have C debug Expand Selected enabled In all cases examine command gets its Collapse Selected value from the simulator kernel ao Within a particular region selected by clicking on an instance in the structure browser you can type Save List show to display the declared signals and variable Code Coverage gt For SystemC designs this will be the debuggable primitive channels objects and SC_Module member End Simulation variables for that instance 6 New GUI in ModelSim 6 0 The design SyscTB Verilog SV amp SysC Models is loaded by typing Modelsim gt vsim lib work sysc sclib work sysc top The prompt will change to VS M to indicate that a design is loaded into the simulator kernel Open the Wave Signal Source and Process windows after the design has loaded by typing the command VSIM gt view s or VSIM gt view source Let us set a breakpoint at line 336 in the file tb rmac sc cpp by using the command bp c tb rmac sc cpp 336 Alternatively you can use the method described earlier where you open the file in the source window and click on line number 336 ModelSim will automatically enable C debugging and set the breakpoint as c 1 Subsequent breakpoints in C C code will be numbered c 2 c 3 etc You can also set breakpoints in the HDL VHDL and or Verilog portions of the design Type the ModelSim TCL command bp after setting all your breakpoints and y
14. e code in order to identify it as a memory block Selecting a memory from the browser opens up the contents of that memory in the MDI pane The Source Wave Dataflow and List windows are opened in the MDI pane area The new Objects window replaces the Signal window in previous versions of ModelSim and the new Locals window replaces the Variables window in previous version of ModelSim Both windows retain to a large extent functionality of the old windows that they replace The Monitor window is a new free form window onto which you can drag and drop any declared persistent variable signal constants net parameter or generic for continuous moni toring during simulation These objects can be of abstract data types such as structures or records This window works for all HDL objects and SystemC objects that are supported for debug in ModelSim The Dataflow window is a valuable debug aid It allows you to view the connectivity of your design at the process level You can use it to trace events that propagate through your design There is the unique ChaseX and associated TraceX capability that allows you to trace back in time and logic the cause of unknown or Xs in your design The GUI reference online docu ment goes into details about the Dataflow window When the Dataflow window is used during debug with assertions PSL in 6 0 and System Verilog assertions in future releases it allows you to quickly identify the source of the failures f
15. indow You can drag and drop SystemC supported primitive channels and HDL signals from the Objects window or the structure browser in the workspace area of the Main window to the Wave window 10 New GUI in ModelSim 6 0 wave default File Edit view Insert Format Tools Window E06 mea RX mina a ka EM cover seg n1340 INACTIVE EM cover seq ni500 INACTIVE Endpoint FrameDropped 4 endpaint_dropped_frame 0 PHY signals 4 mex clk 4 MAxEn 4 MRxDV EA MAxD 4 this field MP3 Decoder Signals mp3 length wb_adt_i 46140 B37A90C6 wb seli 1111 wb_ack_o true top i eth memory mp3 wb dat i 589330 ns Wbcdatio 0 ppEFA17M4E b mp3_data i eaae ea mp3 start ij mp3 done t Memory WB Slave Now 4813181 ns Cursor 1 588799 ns E Fie a S T 588511 ns to 589483 ns Now 4 813 181 ns Delta O sc_fifo object Most debugging capabilities of the Wave window that apply to HDL signals also apply to SystemC signals One exception is the ability to set breakpoints on signals You can instruct ModelSim to break or perform any action when a signal gets to a particular value In the Wave window select the signal then in the Main window menu bar click on Add gt Breakpoint A breakpoint is added and will trigger on any change in the value of this signal Click on Tools gt Breakpoints to open the Breakpoints Dialogue box where you can now modify all break poi
16. ive owners Corporate Headquarters Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070USA Phone 503 685 7000 North American Support Center Phone 800 547 4303 Fax 800 684 1795 Silicon Valley Europe Pacific Rim Japan Mentor Graphics Corporation Mentor Graphics Mentor Graphics Taiwan Mentor Graphics Japan Co Ltd Mentor 1001 Ridder Park Drive Deutschland GmbH Room 1603 16F Gotenyama Hills Graphics San Jose California 95131 USA Amulfstrasse 201 International Trade Building 7 35 Kita Shinagawa 4 chome Phone 408 436 1500 80634 Munich No 333 Section 1 Keelung Road Shinagawa Ku Tokyo 140 Fax 408 436 1501 Germany Taipei Taiwan ROC Japan Phone 49 89 57096 0 Phone 886 2 27576020 Phone 81 3 5488 3030 Fax 49 89 57096 400 Fax 886 2 27576027 Fax 81 3 5488 3031 CBAT 04 TECH6440 w
17. lagged by an assertion firing during simulation This feature makes use of the show drivers binding between the Wave window and the Dataflow window Double clicking on any signal trace in the Wave window opens up the Dataflow window to show the driver of that sig nal or net You can select the process or block in the Dataflow window to get to the source code for that process which is displayed in the Source window A blue arrow points at the beginning of process in the Source window usually the first executable line in the process Chapter 14 PSL Assertions of the online ModelSim SE User s Manual goes into detail on using assertions in ModelSim New GUI in ModelSim 6 0 3 The Wave window in ModelSim 6 0 SE has been enhanced to allow waveform editing You can select an HDL and create stimuli for that block using the waveform editor The resultant wave form can drive the simulation directly Alternatively you can write out a testbench in VHDL or Verilog or you can write out a VCD file all of which can be used at a later time to drive simu lation of the selected block dataflow File Edit view Navigate Trace Tools Window Sii api t BAIA Jee E DAA QQ e Bom art Preamble art idle Start Data art Datat Selecting a process in the Dataflow window causes ModelSim to open the source code for that process 7 ModelSim SE PLUS 6 0 File Edit view J Format Compile Simulate Add Tools Window Help Dmg i WRL MEY der
18. nts that you have in this design This GUI is based on ModelSim s when command It cur rently supports HDL signals only To delete these conditional breakpoints use nowhen command In ModelSim 6 0 the Wave window has a new waveform editor This editor offers functionality that allows you to quickly verify hierarchical blocks as you develop these blocks You can drive simulations directly with the created waveform or you can export the waveform to VCD or HDL testbench Chapter 10 Generating Stimulus and Waveform Editor of the online ModelSim User s Manual goes into details on the capabilities of this feature in ModelSim The List window displays similar information as the Wave window in tabular format In addition delta cycles are also shown for SystemC VHDL and Verilog signal updates in the List window Please refer to the Graphical User Interface Reference for more detail on all features of the GUI New GUI in ModelSim 6 0 11 Summary ModelSim 6 0 provides a trilingual debug environment This environment has been enhanced to facilitate increased verification productivity through support for new verification methodolo gies such as Assertion Based Verification ABV The combined use of methodologies such as ABV and ModelSim s existing debug windows such as the Dataflow window improves debug productivity There is also support for new data types and design structures in the GUI which has been intro duced because of new language
19. o 4 E oe BPS a ax Co ER 0 Dats Mia DAC_2004 demos Suite_DACdemo_0406_SB eth eth_rxstatem ln j Defining the next state assign StartIdle MRxDV StateDrop StatePreamble StateSFD StateData assign StartPreamble MRxDV amp MRxDEqS Stateldle Transmitting ifdef SFDBUG tay initial display SFDBUG enabled 138 gt assign StartSFD MRxDV amp MRxDEqS StateIdle Transmitting StatePreamble 139 Pine 140 assign StartSFD MRxDV MRxDEq5S StateIdle Transmitting StatePreamble 141 endif 142 143 assign StartDataD MRxDV StateSFD MRxDEqD IFGCounterEq24 StateDatal htep sv hJeth_rastatem f Now 33 336 ns Delta 1 sim Atop ethtop rxethmact rxstatem1 ASSIGN 38 Ln 138 Cok O REAC 4 New GUI in ModelSim 6 0 Debugging SystemC and HDL Models The Integrated C Debugger facilitates source level debugging of C C and SystemC source code within the ModelSim Source window ModelSim connects to open source GNU gdb executable via ModelSim s User Interface GNU gdb 6 0 is included in the installation for ModelSim since version 5 8 It is recommended that you use this version of gdb in order to get the best debug experience Enabling source level debugging on runtime code is as easy as setting a breakpoint on an exe cutable line of C C SystemC code in the Source window You set a breakpoint by clicking on the leftmost column at the start
20. ou get a listing of all breakpoints in C and HDL code You can use the bd command to delete breakpoints in SystemC or HDL code Using the Structure tab of the Workspace pane in the Main window you can navigate up or down the loaded design s hierarchy Open the Active Process pane in the Main window to see current status of all HDL and SystemC processes SC_THREADS and SC_METHODS The Object window shows all signals wires variables generics and parameters that are declared in the currently selected region in the structure tab of the Workspace pane and their values either tied to the current cursor position or tied to the current simulation time In addition you can see the results of toggle coverage and extended toggle coverage when cov erage is enabled in this window You can force values onto HDL signals from the Object win dow To do this select the signal and click on Edit gt Advanced gt Force or Edit gt Advanced gt Clock in the main menu In either case an appropriate dialogue box opens to allow configura tion of the force command This GUI feature makes use of the ModelSim TCL force command Only HDL VHDL and Verilog signals are currently supported With the Objects window selected you can add signals to the List or Wave windows either by drag and drop or by doing a RMB click to open a popup menu in the Objects window Select Add to Wave gt selected signal signal in region signals in design from this popup menu There
21. s4 1 7 Jz ae mma A Receive an MP3 file in a stream of Ethernet Packets Interleaved with other randomized ethernet traffic noise 4 and with randomized interframe gaps 4 A PSL endpoint spots dropped frames and triggers a retransmit 4 MP3 file is 41488 bytes CDBG 21 gt gdb print mp3sz print mp3sz 3 41488 CDBG 22 gt show 4 ptype this type class th_rmac_sc public sc module On the CDBG gt prompt we can also send gdb commands directly by prefixing the commands with gdb e g gdb print mp3sz Once we are done with debugging the C C code we can delete the breakpoint using TCL commands bd command The command run continue on CDBG prompt takes us out of the C debugger and into the simulator kernel Alternatively you can click on the run continue i 100 ns icon in the Main Source or Wave windows At any point in the simulation you can examine the values of SystemC and or HDL signal using the examine command You could also use this command to find out values of SystemC objects on the CDBG prompt while in c debug mode New GUI in ModelSim 6 0 9 You can also enable the ToolTips that show values for C C variables in the Source window at the current simulation time To do this click on Tools gt C Debug gt C debug setup and click on show balloon button in the dialogue box that appears The ToolTip
Download Pdf Manuals
Related Search