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Synario ABEL Designer User Manual

1. cccccceeccessecceessennenneeeeeeeenegs Using X in Truth tables conditions ccccceeeeee eee eeeeeeeeeneeees Using X on the right Seria Special case Empty ON eet REENEN Registered Logic in Truth tables REENEN EEN A Equation Simulation AAA Overview of Equation SGimulatton cece esse eee eeeeeeeeeeeeees What iS Equation Simulation ooccccccccccccnnnnncnnnnnnnnnn anno SIMIO PIO tacos The Simulator e e us E enne TEE How to Use the Equation Simulator ccc cc cccccceeeee essen eee ee eeeeeeeeas Test Vector FIGS EE vi Synario ABEL Designer User Manual B JEDEC Simulation kk KKK KEN EN ENN EEN ENKEN EN ENN ENEE ENER ENNEN ENEE Table of Contents How to Invoke Simulation c cece cece cee eececececeucesacaveusesenaueunens A 4 What is JEDEC Simulation cccccccsseceeeeeeeeeeeeeueeeeeseueuensuenesnegs What iS Equation Simulation cc cccccccceeee cece eee e eee eeeeeeeaaaaaeee Simulation le E The Simulator MOG Sl E JEDEC and Dr AT e How to Use the JEDEC Simulator cece cecceeeseeeeeeeeeeeeesseeeeeeneeaes Tesk Vector EE How to Invoke Simulation ccccccncccccnncncccnnnannnna nn rr Ga Waveform RTE ue D What is Waveform VMiewing Editing cece cece eee e eee e ee eeeeeeees Starting the Waveform Viewer 00ccccccccccccccccccnnnnnnnnnn ana nn rn nn Waveform Viewer WINKOW cc ccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeanaaanes Selecting the Waveforms tO VieW ccccecceceeeeeee seen eee
2. The following code defines the instances for the interfaces using the functional_block statement For the andl interface there is one instance named my_and my a a Eer Lona block andi my not tTu unctional block not EQUATIONS my_and INl 11 my_and IN2 E my_not INl andinst OUT1 Ol my_not OUT1 END Figure 2 3 Lower level Schematic for AND1 Interface 2 4 IN wms OUT fi If you are in a lower level schematic you can choose This Block from the Add New Symbol dialog box to automatically create a functional block symbol for the current schematic The name of the lower level schematic must match the Block Name schematic the component name VHDL or the interface name ABEL HDL in the upper level module This associates the lower level module with the symbol representing it The above schematic must be named AND1 sch Synario ABEL Designer User Manual Hierarchical Design in ABEL The nets in the lower level schematic correspond to the pin names schematics component port names VHDL or pin names ABEL HDL in the upper level module ote Some device specific tools require that you not use busses in top level schematics Figure 2 4 Lower level ABEL HDL Module for AND1 Interface MODULE andl TITLE andl gate Instantiated by nandl Simple hierarchy example The pins must match the Symbol pins schematic component port names VHDL or interface names ABEL HDL in t
3. cccccccececeec eee ee ee eee eases eases eases ease eaeaeeaeeeaeeeeaeaneananeanas 5 13 RE 5 31 emulation WIEM X ORS mansa data si cnenyasnana ness 5 27 Synario ABEL Designer User Manual Index 3 Index State e elen CC PSIG SS WIC E Selz OS EE Sie FPGAS ABEL AIDL SY MUNCSIS E describing in ABEL HDL design SU ACCS S mireia rodados Hierarchical design het ge E EEN ek AN OCS E aP OaS 16 E Kegel le ON defined for E E IT EE ae geo EE ARDE E e E E E Hierarchical levels AT EE wll Tree building a hierarchical project leien al EE top level behavioral mogule RENE ENEE NNN RENE ENNEN IC Design SE LE e Po E E 4 20 Lea DESIGM PrO e E 1 4 Identifiers SEAS TAC EE 5 29 Inside out design PIC 2 4 _PIC 2 4 fatale uge EE 5 1 Interface lei nell D EEN 5 2 Intermediate Signals describing in ABEL HDL for FPGAS EE 3 17 invert invert and polarity control polarity ccccceeceeeeeseeseeeeeeeeeeseeeeeeeeesgeeeeetttseggennenegs 5 47 TEE EE 5 11 Istype and polarity Control polarity ccccececeeeeeseeeeeeeeeeeeeeeeeeeetseggeeeeetnseggs 5 17 Index 4 Synario ABEL Designer User Manual Index J JEDEC SAO EE A E A JEDEC SiO ug Cen EEN JK flip flop ns El CAUS EEN 5 27 keen aile Glete neie 5 5 Linking modules merging A elt Te 5 4 pOSt linked OptmizZa OM BEE 5 4 Logic description Select EE Lower level sources rn nn nn nn rn nn nn rra na nn nn rra nena rn nana r nana
4. 10 deg T24 es 14 RS GreenB goto 07 goto 0 goto 0 if SenA if SenA if SenA goto 10 goto Il goto 12 GreenB YellowB goto I3 YellowB RedB RedA GreenA goto 0 goto 0 Power up RedA YellowA GreenA RedB YellowB GreenB goto 0 On 3 amp SenB then 8 amp SenB then 12 SenB then 9 and preset state Off Off On On Off Off Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Number Adjacent States for One bit Change You can reduce the number of product terms produced by a state diagram by carefully choosing state register bit values Your state machine should be described with symbolic names for the states as described above Then if you assign the numeric constants to these names so the state register bits change by only one bit at a time as the state machine goes from state to state you will reduce the number of product terms required to describe the state transitions As an example take the states A B C and D which go from one state to the other in alphabetical order The simplest choice of bit values for the state register is a numeric sequence but this is not the most efficient method To see why examine the following bit value assignments The preferred bit values cause a one bit change as the machine moves from state B to C whereas the simple bit values cause a change in both bit values for the same t
5. Be careful when using X in conditions This can lead to overlapping conditions which look not consistent see example below Due to the way the compiler work this type of inconsistency is not checked nor reported In fact only the ON set condition is taken into account the OFF set condition is ignored The following example illustrates this MODULE DEMO3 TITLE Example A Inputs Ap Br E pin QUEDUE OULD In astype com Synario ABEL Designer User Manual 5 45 Synario ABEL HDL Design Considerations Equivalence X X Truth_Table A B C gt Out E 0 1 gt 0 Ll ignored in fact 0 1 0 A es 1 X x gt le E POs Oy 1 gt 1 L4 incompatible Pilas ly 0 gt 0 L5 incompatible END Result Out A B C B amp C L1 is in fact ignored Out is active high therefore only line L4 is taken into account Likewise L5 intersects L3 but is ignored since it is not in the ON set for Out Globally only L2 L3 and L4 are taken into account as we can check in the resulting equation without any error reported Using X on the right side 5 46 The syntax allows to use X as a target value for an output In this case the condition is simply ignored ote This is not the method to specify optimizable don t care states See example 2 for such an example Example 6 shows that gt X states are not optimized if DC type or DCSET are not used These lines
6. Truth_Table A B C gt Dut EF 0 se gt da hi Li 1 A E SE E EZ 0 0 1 EA Oe JN do 1 0 0 gt 0 14 END Resulting Reduced Equation ZZ QuE BB Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Influence of Signal polarity Well see now with example 3 how the polarity of the signal may influence the truth table In this example Outi and Out2 are strictly equivalent For Out1 note that the ON set is the O values The third line L3 is ignored MODULE DEMO2 TITLE Example 3 Inputs Ay BO A Output Out 1 pin istype com neg Out 2 pin istype com neg Out 3 pin istype com neg BEWARE Truth Table CLA B C gt Out1 Out2 Out3 LO 0 1 gt 0 dig O gd Tad PO Ka 1 SES KE OY da E ebe NS 0 gt 1 O 1 L3 END Resulting Equations Outil 10ut2 A TG or Outl Out2 A C BUT Out3 A amp B amp C lt lt what you wanted For active low outputs one must be careful to specify 1 for the active state if the Output appears without the exclamation point O must be used when output is defined in the table header We recommend the style used for Outi For Out3 line used is L3 L1 and L2 are ignored Using X in Truth tables conditions Don t Care used on the left side in Truth tables have no optimization purpose they only serve as a shortcut to write several conditions in one single line
7. key_star which_code_enter which_code_enter 3 19 Overview of ABEL HDL Sources Figure 3 8 State Machine Description with Intermediate Signals 3 20 CASE enter_from_disarmed_ready CASE sensors_off amp key_numeric code_entry_ X WITH which code enter sensors_off amp key_none code_entry_ Y WITH which code enter key_pound_star error sensors_off error ENDCASE enter from_armed CASE key_numeric code_entry_ X WITH which code enter key_pound_star armed WITH which code _enter key_none code_entry_ Y WITH which code enter ENDCASE ENDCASE Synario ABEL Designer User Manual which_code_enter which_code_enter which_code_enter which_code_enter Which code 6nter Overview of ABEL HDL Sources The declarations and equations required to create the intermediate Signals used in Figure 3 8 are shown in Figure 3 9 Figure 3 9 Intermediate Signal Declarations and Equations esoe and node declarations sens_code 0 sens_code_l sens code 2 sens code 3 Oun key_code_0 key_code 1 key_code_2 key_code_3 pin which_code_enter_0O which_code_enter_1 which_code_enter_ 2 node istype reg set declarations which_code_enter which_code _enter_0 which_code _ enter 2 sens_code sens_code_0 sens_code_3 key_code key_code_0 key_code_3 code entry sub states key from_disarmed_ready Se Klee D OM
8. Q1 Preset there is an ambiguous feedback condition The signal Q1 appears on the right side of the equation but there is no indication of whether that fed back signal Should originate at the register come directly from the combinational logic that forms the input to the register or come from the I O pin associated with Q1 There is also no indication of what type of register Should be used although register synthesis algorithms could theoretically map this equation into virtually any register type The equation could be more completely specified in the following manner OU Clik Clock Register clocked from input Ol ze LOL KR Preset Reg feedback normalized to pin value This set of equations describes the circuit completely and specifies enough information that the circuit will operate identically in virtually any device in which you can fit it The feedback path is specified to be from the register itself and the CLK equation specifies that the memory element is clocked rather than latched Synario ABEL Designer User Manual 5 7 Synario ABEL HDL Design Considerations Detailed Circuit Descriptions In contrast to a pin to pin description the same circuit can be specified in a detailed form of design description in the following manner OLeGhh Cl ck Register clocked from input Ol D 101 0 Preset D type f f used for register In this form of the design specifying the D input to a D type flip flop an
9. block counter INTERFACE This statement defines the input and output ports of a lower level module FUNCTIONAL_BLOCK This statement specifies one or more instances of the lower level module You must assign a unique name to every instance of a lower level module in this case the name is cntrl1 Synario ABEL Designer User Manual 3 13 Overview of ABEL HDL Sources Connecting Lower level Module Ports After a lower level module has been instanced in a higher level module you must connect the ports of the lower level module or more precisely the ports of the instance of the lower level module to Signals in the higher level module These signals can be inputs outputs or ports of other module instances In this example two of the ports the clock and register clear signals of the lower level module are connected directly to input pins of the higher level module This is done with the following equations cntrl clk cik Choe Lars clr The outputs of the lower level module ports q7 through q0 are not tied directly to pins or nodes at the higher level Instead these signals are grouped into a set named count Count is then used within the equations for the design s outputs count cntr1 q7 q0 Equations load count 250 Time for next data byte Since the outputs of the lower level module count are registered eight automatically generated nodes will be added to the top level design
10. CARRY directive causes comparators and adders to be generated using intermediate equations for carry logic This results in an efficient multilevel implementation You should design for multi level FPGAs in a multi level fashion using intermediate signals as much as possible An FPGA device fitter is capable of transforming two level PLD designs into multi level FPGA designs but it takes a lot of time and occasionally fails Rewriting your PLD designs to reflect the multi level nature of the FPGA architecture often reduces the time for fitting increases the chance of a fit and simplifies your design descriptions Synario ABEL Designer User Manual Overview of ABEL HDL Sources Figure 3 10 Typical FPGA Design gt gt gt BLOCK STATE Es MACHINE Op schematics Implemented by ABEL KZ STATE MACHINE a gt gt gt gt DL Zb DL gt OTHER gt FUNCTIONAL BLOCK E RSR Implemented gt by lower level schematics 1071 1 Integrating ABEL HDL Designs into Larger Circuits A typical FPGA design might have a top level schematic showing the device s pin out and lower level function blocks and a collection of functional blocks see Figure 3 10 Some functional blocks point to lower level schematics and others point to subcircuits that are described behaviorally If the design is large some functional blocks may have sub blocks To integrate an ABEL HDL subcircuit into a schematic the functional block in the
11. Mie DESCH e Ee gk eee oh OR E ie a e OD SO g OOO Ae ae eel Beg Y op Eh A E D ee ae OG e a A my A a O a DECK GE E br Gre A WOR tg COD tye OS ei ea Ea O a a E Ig end Powerup Register States If a state machine has to have a specific starting state you must define the register powerup state in the state diagram description or make sure your design goes to a known state at powerup Otherwise the next state is undefined Unsatisfied Transition Conditions D Type Flip Flops For each state described in a state diagram you specify the transitions to the next state and the conditions that determine those transitions For devices with D type flip flops if none of the stated conditions are met the state register shown in the following figure is cleared to all Os on the next clock pulse This action causes the state machine to go to the state that corresponds to the cleared state register This can either cause problems or you can use it to your advantage depending on your design Figure 5 14 D type Register with False Inputs NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM ye LOGIC 0 Wi SN Ek You can use the clearing behavior of D type flip flops to eliminate some conditions in your state diagram and some product terms in the converted design by leaving the cleared register state transition implicit If no specified transition con
12. This design has lower level ABEL HDL files not shown ABEL uses the Project Navigator interface as the front end to all the design tools in the ABEL Designer The Project Navigator creates an integrated design environment that links together proprietary and third party design simulation and place and route tools For instance we believe the people that know the most about programmable ICs are the people who manufacture them The Project Navigator links together our design tools with place and route tools created by us in close cooperation with the IC vendors or by the IC vendors themselves Synario ABEL Designer User Manual 1 1 ABEL Design Figure 1 1 Example of a Top level ABEL HDL source for a IC Design MODULE twocnt TITLE two counters having a race Demonstrates ability to use multiple levels of ABEL HDL Hierarchy and to collapse lower level module nodes into upper level modules For example each counter has four REGISTER nodes and this module has four COMBINATORIAL pins The lower level registers are correctly flattened into the top level combinatorial outputs No dot extensions are used allowing the system to determine the best feedback path to use This design uses the advanced fit properties REMOVE REDUNDANT NODES and MERGE EQUIVALENT FEEDBACK NODES Constants Cp A a Inputs clk enl en2 rst pin Outputs ad al al a0 DS B27 BLBO pin ovl ov2 pin istype reg buffer Submodule declarat
13. ABEL HDL Module The Text Editor loads and a dialog box prompts you for a module name filename and title For the module name enter andff For the filename enter andff abl the file extension can be omitted Note The module name and file name should have the same base name as demonstrated above The base name is the name without the 3 character extension If the module and file names are different some automatic functions in the Project Navigator might fail to run properly Si 6 If you like enter a descriptive title in the Title text box When you have finished entering the information click on the OK button or press Enter You now have a template ABEL HDL source file as shown in the following figure synario Text Editor andtft abl File Edit View Templates Tools Options Window Help TITLE AND gate and a flip flop END 7 AWA Rec Of NoWrap DOS INS Synario ABEL Designer User Manual Overview of ABEL HDL Sources Enter the Logic Description 7 Add declarations for the three inputs two AND gate inputs and the clock and the output by entering the following statements in the ABEL HDL source file If a TITLE statement exists in the template file enter these statements after the TITLE statement input l input 2 Cik Dairy Output ag pin istype reg These two statements declare four signals input_1 input_2 CIk and output_q ote ABEL HDL does not have an expli
14. ABEL HDL source file as shown below Figure 5 9 Source File Showing Don t Care Optimization module dc I Sep dee aly SE pan EE ER pin istype dc com truth table MS a UA 0 0 O ES 10 51 E Dis Oe 305 7 7 7 7 7 7 0 gt 0 0 gt 1 1 gt 1 e De dag A ee yo dey a 1 po bet skye AS e 1 1 1 1 gt 0 0 gt 0 0 gt 0 0 gt 0 ES Ek AE ER o 1 CO L k a k CO OC CO CO k a rero orr rroo E Et ee CO CO CO L k k Li end 5 24 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations This example results in a total of four single literal product terms one for each output The same example with no istype dc results in a total of twelve product terms For truth tables Don t Care optimization is almost always the best method For state machines however you may not want undefined transition conditions to result in unknown states or you may want to use a default state determined by the type of flip flops used for the state register for state diagram simplification When using don t care optimization be careful not to specify overlapping conditions specifying both the on set and dc set for the same conditions in your truth tables and state diagrams Overlapping conditions result in an error message For state diagrams you c
15. IC system or board Design Flows in the Processes Window One of ABEL s most powerful features is that it knows how to process any kind of design for any kind of architecture because the Project Navigator is context sensitive which helps prevent information overload The steps in the Processes window are context sensitive in two ways First the processes change depending on what kind of source file you ve highlighted in the Sources window source level flow Second the processing for a given file changes depends on what target device kit you ve chosen project level flow For instance a schematic targeted for an XYZ PLD is processed differently than a schematic targeted for an ABC PLD Project level Design Flow For IC Design projects click on the device icon GER in the Sources Window The processes that appear in the Processes Window represent the Project level Design Flow Source level Design Flow Click on any source such as a schematic or HDL source in the Sources Window The processes that appear in the Processes Window if any represent the Source level Design Flow 1 12 Synario ABEL Designer User Manual ABEL Design Create a New Project in the Project Navigator After starting the Project Navigator see page 1 8 for instructions you can create a new project by doing the following 1 In the Project Navigator s File menu click on New Project ote A project contains the sources and processes for a s
16. Off GreenB YellowB RedB COMP Off Off On state_diagram Count State 0 if SenA SenB then O with COMP 1 if SenA amp SenB then 4 with COMP 1 if SenA SenB then 1 with COMP 1 State 1 goto 2 with COMP 1 State 2 goto 3 with COMP 1 State 3 goto 4 with COMP 1 State 4 GreenA Off YellowA On goto 5 with COMP 1 State 5 YellowA Off RedA On RedB Off GreenB On goto 8 with COMP 1 State 8 if SenA SenB then 8 with COMP 1 if Sen amp SenB then 12 with COMP 1 if Sen SenB then 9 with COMP 1 State goto 10 with COMP 1 State 10 goto 11 with COMP 1 State 11 goto 12 with COMP 1 State 12 GreenB Off YellowB On goto 13 with COMP 1 State 13 YellowB Off RedB On RedA Off GreenA On goto 0 with COMP 1 end 5 34 This design uses the complement array feature of the Signetics FPLA devices to perform an unconditional jump to state 0 0 0 0 If you use the DCSET directive the equation that specifies this transition SO poe el Re COME Es Mir dp dg bis will conflict with the dc set generated by the state diagram for S3 R S2 R S1 R and SO R If equations are defined for state bits the DCSET directive is incompatible This conflict would result in an error and failure when the logic for this design is optimized Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations T
17. Print Sends the plot to the printer using the current settings If you decide not to print double click on the System button at the upper left corner of the dialog box to close the box C 10 Synario ABEL Designer User Manual lol alternate flip flop TVDOS sassperenctaciceiciapaneashesinepenriantrateianeieseeetenehiraneeeneasaness Carry INtermetllate SIGN ONS EE 3 22 DCSET ELE ee DCSET dcset Bissen EE 5 23 with state MACHINES STATE mission 5 33 ABEL HDL a first look EE design considerado te EE enter an ABEL HDL description 3 8 enter logie descripcion A EE E lge mejo EE oro AA O A o e TEET AREE iT SUS GSS xe aan AA RU NIE warning about ABEL HDL Synthesis cece ccc eee eeeeeeeee seen ee eeeeeeeesenaaaaaes ABE AIDE Comp lll e EE 4 1 ABEL HDL en e elt EE ee e Ee lg ONS EE E A e E liste ee EE Architecture independence COC E Ee LEE dot extensions Cxalni EE eege Synario ABEL Designer User Manual Index 1 Index FESOlVING AMDIQUIN CS EE Ef Arrays complemen summer doo 5 40 attribute a a DOLE COO EE 5 17 A Attributes and architecture independencelarchit oooocccccccccncncncnnnnnnnnnnnnnn nn rrrr nr 5 6 collapsing nodes scene eect eect eee e eee ea eee ea eee ea eee eaeaeeaeaeeataneananeaeaneaeas 5 5 mower EEN 5 2 Alle Ree EEN 4 2 B Seet ei fie roer tonsa rte do tooo TET Geet Seege aU de e EE PIC 2 4 2 4 buffer buffer anda polarity CONtrO
18. Using Dot Extensions e DCSET Considerations and Precautions e Exclusive OR Equations e State Machines e Using Complement Arrays e Accessing Device specific and Complex Architectural Elements e ABEL HDL and Truth Tables Hierarchy in ABEL HDL You use hierarchy declarations in an upper level ABEL HDL source to refer to instantiate an ABEL HDL module To instantiate an ABEL HDL module In the lower level module optional 1 Identify lower level I O Ports signals with an Interface statement In the top level source 2 Declare the lower level module with an Interface declaration Synario ABEL Designer User Manual 5 1 Synario ABEL HDL Design Considerations 3 Instantiate the lower level module with Functional_block declarations ote Hierarchy declarations are not required when instantiating an ABEL HDL module in a Synario schematic For instructions on instantiating lower level modules in schematics refer to your schematic reference Instantiating a Lower level Module in an ABEL HDL Source Identifying I O Ports in the Lower level Module The way to identify an ABEL HDL module s input and output ports is to place an Interface statement immediately following the Module statement The Interface statement defines the ports in the lower level module that are used by the top level source el You must declare all input pins in the ABEL HDL module as ports and you can specify default values of 0 1 or Don t c
19. and Naming Projects Use the following guidelines when saving and naming source files and projects e Avoid saving more than one project in the same directory e Use the Create Directory option to save linked projects in subdirectories of the top level project This will allow you to later reference the linked projects using relative paths which will allow you to move your design files without having to relink projects Avoid saving a project which has the same base file name as one of its sources If a source and project have the same base name you may have problems with the Project Navigator s automake feature For instance avoid calling your project myfile syn if it contains a source named myfile abl Change the Title of the Project Do the following to change the title of an open project 1 The project appears in the Sources window of the Project Navigator Double click on the title of the project The Project Title dialog box appears Project Properties ES Title OK Cancel 2 In the Project Title dialog box enter the name you want for your project and then click on the OK button The project title can be as long as you like but only the first 20 characters will show The title can contain spaces and any other keyboard character except tabs and returns ate For some Vendor Kits the project directory and project name should be the same Synario ABEL Designer User Manual 1 15 ABEL Design Define
20. and routing your design you need to select the target device for your design The process of selecting a device is the same for FPGAs as it is for PLDs and CPLDs A device is selected in the following manner 1 Double click on the device icon GER to change the device 2 In the Choose Device dialog box select a Vendor Kit from the Device list box Select an FPGA from the Device list box Choose the OK button to exit the Choose Device dialog box Synario ABEL Designer User Manual ABEL HDL Compiling When you exit the window if the Project Navigator warns you that changing to a Device Kit has an impact on your project and prompts for confirmation Choose the Yes button There can be a noticeable pause while the Project Navigator reconfigures all the processes in the project to reflect the change in target device When this operation is finished the Processes for Current Source window is updated with processes that are specific to the devices supported by the current Device Kit Mapping the Design to the Selected Device How the Project Navigator maps this design to any FPGA depends on the Device Kit you are using In general most Device Kits convert your HDL sources to BLIF or EDIF create necessary simulation models and then translate your design to a format that can be routed using Vendor specific Place and Route tools Simulation The processes for simulation require that you have simulation test files and or simulat
21. are ALWAYS ignored MODULE DEMO6 TITLE Example pi Inputs A B C pin Output Out pin istype com Equivalence X X Truth_Table A B Sal gt Out Dt D 0 gt 0 0 O 1 gt Xi Op Loy 0 gt 1 0 1 1 gt Xi 1 X X gt X END 1 1 As is Out IA amp B amp IC With istype com DC Out B They are in fact of no use except maybe as a way to document that output does not matter Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Special case Empty ON set There is a special case which is unlikely to happen but may sometimes occurs Consider this example MODULE DEMO5 TICLE Example e Inputs Fa Bye Co Oun QOQutput EIERE com pos Truth_Table A B G gt Qon 0 O 1 gt Q PO 1 0 gt 03 KEE 0 gt 0 Ee GE 0 gt 1 changes everything END Without the last line 14 FJ TOUC amp 1B amp UC Ya IA E Bee LC AIA TBS E L7 META D4 e Out UA TB Et What we obtain is slightly unexpected This table should produce Out 0 as the result We enumerated only OFF conditions and the polarity is POS or default so unlisted cases should also turn into Zeroes One reason to build such a table could be when multiple outputs are defined and when Out needs to be shut off for whatever reason In the absence of the line L4 the result is not intuitive The output is O only for the listed cases L1 L2 L3 and
22. d2 Clk Toggle Ena Qout equations Qout D Qout CLK Qout ER test_vectors end Cus O Q oO Er QO device E0320 pin L PIN 23 pra gt pin 19 istype reg_D 0 O e OF CO CO OC CH Qout Q amp Toggle Cik lEna Clik Ena Toggle LC 0 PRP PPP Pp A Lol ee ee ee eee Qout e e e e e ON FN OF CH FF D e se ae This design would result in the same circuit and E0320 fuse pattern previously illustrated in figure at the bottom of page 5 29 Figure 5 6 Dot Extensions and Architecture independence Circuit 3 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Using Don t Care Optimization Use Don t Care optimization to reduce the amount of logic required for an incompletely specified function The DCSET directive used for logic description sections and ISTYPE attribute oC used for signals specify don t care values for unspecified logic Consider the following ABEL HDL truth table truth_table Masa lado ado Ca e ker E lh Ee De OD Te DS EE GER EC 0 De Bee Ene Dis Eu llo Di po lee ile e fen de o do ao lak SET lb e db ae E IDO e en Blan les Ci ka Osel ba thes O ET Et en E CONS ap Ze o O Eh Ed MU Ue keen Be Dr dE This truth table has four inputs and therefore sixteen 2 possible input combinations The function specified however only indicates eight significant
23. files by clicking on Add New to Project from the Source menu or if you want to use sources that are already created you can import them using the Add to Project command from the Source menu When you import or create a new source the source file is saved in the same directory as the project syn file Design Strategies The following design strategies are helpful when designing for FPGAs You will find more detailed information in later sections Define external and internal signals with pin and node statements respectively For state machines and truth tables include DCSET or dc attributes if possible since it usually reduces logic Use only dot extensions that are appropriate for FPGA designs You can find information about using dot extensions in the specific FPGA Device Kit manual Synario ABEL Designer User Manual 3 15 Overview of ABEL HDL Sources e Use intermediate signals to create multi level logic to match FPGA architectures Declaring Signals The first step in creating a logic module for an FPGA is to declare the Signals in your design In ABEL HDL you do this with pin and node statements Pin Pin Statements indicate external signals used as inputs and outputs to the functional block Pin numbers are optional in ABEL HDL and are not recommended for FPGAs since pin statements don t actually generate pins on the device package If you declare an external signal as a node instead of a pin the d
24. is 1 for all other cases even if dc or pos is used When line L4 is restored then the output equation becomes Out A amp IB amp IC because we fall in the general situation where the ON set is not empty Registered Logic in Truth tables Truth Tables can specify registered outputs In this case the assignment become gt instead of gt For more information refer to the ABEL HDL Reference Manual Synario ABEL Designer User Manual 5 47 Synario ABEL HDL Design Considerations 5 48 Synario ABEL Designer User Manual A Equation Simulation Overview of Equation Simulation This appendix is an overview of Equation Simulation For detailed information about Equation Simulation refer to the Equation and JEDEC Simulators Manual What ts Equation Simulation Equation Simulation is similar to Functional Simulation because it tests your design without using device specific information Therefore Equation Simulation can be conducted before you select a device Equation Simulation however only tests the equations in your design as specified by test stimulus ABEL HDL test vectors Simulation Flow Figure A 1 shows a flow diagram of simulation during evaluation of the inputs to the output This flow is the same for both Equation and JEDEC simulation see Appendix B The simulator applies the first test vector and performs any setup of internal registers that results from the vector applied to the inputs The sim
25. is placed underneath myboard in the Sources window If the source is a test file the source is placed underneath the source that the file is associated with Synario ABEL Designer User Manual 1 19 ABEL Design Remove a Source 1 From the Sources window click on the source the source is highlighted 2 From the Source menu click on Remove Note Removing a source from a project does not delete the underlying file Modify a Source You can edit any of the sources that make up your project by double clicking on them if you have file associations set up in Windows and have enabled Use File Associations in Options Environment in the Project Navigator See Also For IC Design projects refer to the Vendor Kit Device Kit or Interface Kit manual for specific design information about a device family In Windows 95 and NT you can associate text files with the ABEL Text Editor by using the Windows 95 Explorer See the documentation for the Windows 95 Explorer for more information Common Tasks in Programmable IC Design Creating a New IC Design Project A project contains the sources and processes for a single IC Design and if you have various Device Kits you ll be able to pick various technologies with which to implement that IC The IC projects have the flexibility to change ICs if the design is done with the virtual chip libraries and symbols After starting the Project Navigator you can create a new I
26. it reaches the product term you specify The result is an equation that is optimized to fit the device constraints Selective Collapsing In some instances you may want to prevent the collapsing of certain nodes For example some nodes may help in the Simulation process You can specify nodes you do not want collapsed as Istype keep and the optimizer will not collapse them Synario ABEL Designer User Manual 5 5 Synario ABEL HDL Design Considerations Pin to pin Language Features ABEL HDL is a device independent language You do not have to declare a device or assign pin numbers to your signals until you are ready to implement the design into a device However when you do not specify a device or pin numbers you need to specify pin to pin attributes for declared signals Because the language is device independent the ABEL HDL compiler does not have predetermined device attributes to imply signal attributes If you do not specify signal attributes or other information such as the dot extensions which are described later your design might not operate consistently if you later transfer it to a different target device Device independence vs Architecture independence The requirement for signal attributes does not mean that a complex design must always be specified with a particular device in mind You may still have to understand the differences between for example a P22V10 PAL and an EP600 EPLD but you do not have to specif
27. me O 0 Lolas O e 1 Los E i 1 LJ LL Li Ld V e Synario ABEL Designer User Manual 3 9 Overview of ABEL HDL Sources The following figure shows the complete ABEL HDL source file describing the circuit oynario Text Editor andtf abl TITLE AND gate and a flip flop input_1 input_2 Clk pin output_q pin istype reg Equations output_q input_1 amp input_2 output_q clk Clk Test_vectors C1k input_1 input_2 gt output_q fo 0 0 gt 0 Laos 0 0 gt 0 C 0 1 gt 0 c 1 1 gt 1 21 HWA Bee Dit Nokwuap DOS INS To save the ABEL HDL source file choose Save from the Text Editor File menu Choose Exit from the File menu The Project Navigator updates the Sources in Project window to include the new ABEL HDL source notice the ABEL HDL source icon The Project Navigator also updates the Processes for Current Source window to reflect the steps necessary to process this source file Note You can run the Text Editor with an ABEL HDL source loaded by double clicking on the source in the Sources in Project window When you are finished entering or importing source files you are ready to process your design Refer to Chapter 4 ABEL HDL Compiling for more information The ABEL HDL Reference 3 10 If you have questions about the ABEL HDL language refer to the ABEL HDL Reference manual Synario ABEL Designer User Manual Overview of ABEL H
28. met situation and reset the state machine to a known state Precautions for Using Don t Care Optimization When you use don t care optimization you need to avoid certain design practices The most common design technique that conflicts with this optimization is mixing equations and state diagrams to describe default transitions For example consider the design shown in the following figure Figure 5 15 State Machine Description with Conflicting Logic module TRAFFIC title Traffic Signal Controller Kim Fu Lim Data I O Corp traffic device FT67 Clk SenA SenB pin Le Gg T7 PR pin 16 Preset control GA YA RA PEN Aras GB YB RB pin Us Node numbers are not required if fitter is used GH node 31 34 istype reg_sr buffer COMP node 43 Be Oke Ee ON A aey Count S3 S0 Define Set and Reset inputs to traffic light flip flops GreenA GA S GA R YellowA YA S YA R RedA RA S RA R GreenB GB S GB R YellowB YB S YB R RedB RB S RB R On F ifr aly e IGS Ig Off Se iO e de de test_vectors edited equations GB YB RB AP PR GA YA RA AP PR GB YB RB CLK Clk GA YA RA CLK Clk S3 S0 Ab PR Synario ABEL Designer User Manual 5 33 Synario ABEL HDL Design Considerations ste 50 CLK Clk Use Complement Array to initialize or restart S33 S0 eR LEOME by Ek ETY GreenA YellowA RedA COMP amp On Off
29. must asynchronously reset to state Start when the Reset input is true you write ASYNC_RESET Start Reset Synario ABEL Designer User Manual 5 39 Synario ABEL HDL Design Considerations Symbolic Test Vectors You can also write test vectors to refer to symbolic state values by entering the symbolic state register name in the test vector header in the output sections and the symbolic state names in the test vectors as output values Using Complement Arrays 5 40 The complement array is a unique feature found in some logic sequencers This section shows a typical use ending counter sequence You can use transition equations to express the design of counters and state machines in some devices with JK or SR flip flops A transition equation expresses a state of the circuit as a variation of or adjustment to the previous state This type of equation eliminates the need to specify every node of the circuit you can specify only those that require a transition to the opposite state An example of transition equations is shown in Figure 5 18 a source file for a decade counter having a single clock input and a single latched output This counter divides the clock input by a factor of ten and generates a 50 duty cycle squarewave output The device used is an F105 FPLS In addition to its registered outputs this device contains a set of buried or feedback registers whose outputs are fed back to the product term inputs T
30. polarity as follows y neg Istype neg optimizes the circuit for negative polarity Unspecified logic in truth tables and state diagrams becomes a O Dos Istype pos optimizes the circuit for positive polarity Unspecified logic in truth tables and state diagrams becomes a 1 OC Istype dc uses polarity for best optimization Unspecified logic in truth tables and state diagrams becomes don t care X Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Using invert and buffer to Control Programmable Inversion An optional method for specifying the desired state of a programmable polarity output is to use the invert or butter attributes These attributes ensure that an inverter gate either does or does not exist between the output of a flip flop and its corresponding output pin When you use the invert and buffer attributes you can still use automatic polarity selection if the target architecture features programmable inverters located before the associated flip flop These attributes are particularly useful for devices such as the P22V10 where the reset and preset behavior is affected by the programmable inverter Note The invert and buffer attributes do not actually control device or equation polarity they only enforce the existence or nonexistence of an inverter between a flip flop and its output pin The polarity of devices that feature a fixed inverter in this loc
31. project In the Project Navigator one project represents one IC For more information about creating projects refer to the rest of this chapter Project Sources In ABEL projects consist of ABEL HDL sources For more information about ABEL HDL sources refer to Chapters 3 4 and 5 1 4 Synario ABEL Designer User Manual ABEL Design Design Simulation and Testing Equation and JEDEC simulation is available using ABEL HDL Test Vector abv files For more information about simulation e For Equation simulation refer to Appendix A e For JEDEC simulation refer to Appendix B e For Waveform viewing refer to Appendix C Device Independence By targeting your design to a Virtual Device you can create designs that are portable to different device architectures You can later select a specific device family to target your design to so that you can physically implement your design into a specific device Many processes for IC Designs can be conducted using a Virtual Device For instance you can Functionally Simulate an IC Design targeted to a Virtual Device Because ABEL s Project Navigator is context sensitive changes with the context of your design when you choose a Virtual Device only those processes allowed for a virtual device are shown If you choose a specific device family the processes change to reflect your selection the processes should be those allowed for a Virtual Device plus those specific to the devi
32. project notebook icon or project name E Untitled that appears at the top of the Sources in Project window to change the project name In the Project Properties dialog box text field enter a descriptive title for the project such as Pulse width Modulated D A Converter 2 From the File menu click on Save the changes to your new project Now you are ready to enter the design Synario ABEL Designer User Manual 3 11 Overview of ABEL HDL Sources Create or Import ABEL HDL Sources This design consists of two ABEL HDL source files ABEL HDL supports hierarchy in the language allowing large designs to be easily entered and managed Begin by creating the two ABEL HDL source files shown below and adding them to your project If you don t want to enter these sources you can import them from the examples directory synario4 examples tutorial tutor3 using the Add to Project command from the Source menu The module name and file name should have the same base name The base name is the name without the 3 character extension If the module and file names are different some automatic functions in the Project ABEL HDL Source EE Navigator might fail to run properly MODULE pwmdac TITLE Pulse width modulated Digital to Analog converter CARRY 2 Constants Spas VCE pee Inputs Clk rolki CId A 10 A e a QUEDUES pwm Din Lstype gom load pin AStype Com Nodes E e node istype reg buffer Sub module declarations coun
33. the generic macrocell in its requirements you can probably use simple pin to pin descriptions Using for Alternative Flip flop Types In ABEL HDL you can specify a variety of flip flop types using attributes such as istype reg_D and reg Jk However these attributes do not enforce the use of a specific type of flip flop when a device is selected and they do not affect the meaning of the assignment operator You can think of the assignment operator as a memory operator The type of register that most closely matches the assignment operator s behavior is the D type flip flop The primary use for attributes such as istype reg D reg JK and Ted GR is to control the generation of logic Specifying one of the Ted attributes for example istype reg_D instructs the AHDL compiler to generate equations using The D extension regardless of whether the design was written using D or some other method for example state diagrams Note You also need to specify istype invert or buffer when you use detailed syntax Using for flip flop types other than D type is only possible if register synthesis features are available to convert the generated equations into equations appropriate for the alternative flip flop type specified Since the use of register synthesis to convert D type flip flop stimulus into JK or SR type stimulus usually results in inefficient circuitry the use of for these flip flop types is di
34. the project can contain documentation files simulation models and test files you can associate test files with a piece of the design or the entire design depending on what you want simulated A project represents one IC design but you have the option of targeting your design to a specific IC vendor s device or to a virtual device When you switch the target device the processes and design flow in the Project Navigator changes to one that is appropriate for the new target device For example Figure 1 2 shows the sources as they appear in the Project Navigator for an example IC Design project Figure 1 2 Sources in an Example IC Design Project Sources in Project SC A Project Title EIOUALCNTR SYN Eer Ed P22V 10 Device twoont vectors Vectors M twoent twocnt abl A hierent hiercnt abl Lower level ABEL HDL file obcb obcb abl Lower level ABEL HDL file In Figure 1 2 the top level ABEL HDL file twocnt contains Interface statements that instantiate links to the lower level ABEL HDL file called hiercnt Simulating IC Designs You can use JEDEC and Equation simulation on your ABEL HDL test vectors to simulate your design Synario ABEL Designer User Manual 1 3 ABEL Design Overview of IC Design With ABEL you can create and test designs that will be physically implemented into Programmable ICs also called chips and devices Projects IC Designs are built in the Project Navigator using a
35. C design project by doing the following 1 In the Project Navigator s File menu click on New Project 2 In the Create New Project dialog box enter a name for the project file syn that will be used for your design The project name can be up to 8 characters long plus the syn extension 3 Choose the directory in which you want to place your project files You can navigate through the directories and click on the Create Dir button to create additional directories 1 20 Synario ABEL Designer User Manual ABEL Design When you are finished navigating to the directory for the project click on the OK button ote We do not recommend placing more than one project in the same directory You can use the Create Directory button to create a meaningful structure of directories to hold each project 4 The project appears in the Sources window of the Project Navigator Double click on the title of the project Untitled The Project Title dialog box appears 5 In the Project Title dialog box enter the name you want for your project and then click on the OK button The project title can be as long as you like but only the first 20 characters will show The title can contain spaces and any other keyboard character except tabs and returns 6 In the Project Navigator s File menu click on Save to save your project 7 Add sources and documentation to your project by using the commands in the Sources menu You can create ne
36. D Ek des Y ze E De ye Des AU Jeer Oi e St ay gt d dE d ee E O Ou d los tU Oo ok 0 e b Ek E ASA E e ka G ig WO La a H H H es lh e ge hg O O Ee e e CS ep LO ye Jee E ug Or e O7 Or Di ME e A H n ES d Steals Oaa Ae te io O A Kee EK 0 Go Ah gt Oy Ue che Oy Oe 10 50 ey END How to Invoke Simulation To start the Simulate Equations process available do the following 1 Select the test vector ABV file in the Sources in Project window The simulation processes will then appear in the Processes for Current Source window 2 To change simulation properties single click on Simulate Equations and then click on the Properties button Click on OK to exit the Properties dialog box when you are finished 3 To start a simulation double click on Simulate Equations Refer to online help and the Equation and JEDEC Simulators Manual for more information A 4 Synario ABEL Designer User Manual B JEDEC Simulation What is JEDEC Simulation This appendix is an overview of JEDEC Simulation For detailed information about JEDEC Simulation refer to the Equation and JEDEC Simulators Manual What is Equation Simulation JEDEC Simulation is similar to Timing Simulation because it tests a device specific model of your design Therefore JEDEC Simulation must be conducted after you select a device it requires that a JEDEC programmer file is created for your design JEDEC Simulati
37. DL Sources Creating a Hierarchical ABEL HDL Design for a CPLD This section is a tutorial that describes how to enter an ABEL HDL design description The circuit in this tutorial consists of a simple AND gate with a flip flop This tutorial demonstrates how to use ABEL HDL to describe the circuit behaviorally This example demonstrates e Use hierarchy to combine multiple ABEL HDL sources e Design entry for a CPLD Complex PLD Description of the Circuit The circuit for this tutorial is a pulse width modulated digital to analog converter This circuit converts 8 bit input data into a pseudo analog representation by producing a pulse width modulated output The off time of the output is directly proportional to the value of the input This type of pulse width modulated output is suitable for driving the audio speakers in most personal computers Entering the Circuit To start a new project and set up a new directory for this tutorial 1 Start Synario or ABEL The Project Navigator window appears 2 From the File menu click on New Project 3 Select IC Design as the project type 4 Click on the Create Directory button to add a new project directory We will assume that the name of the directory is Vtutor3 5 In the Create New Project dialog box enter tutor3 syn for the Project Filename 6 Click on the OK button to exit the New Project dialog box To change the name of the project design 1 Double click on the
38. Data I O Corp decade device F105 Clk Clr FO PR pin 1 8 18 19 P3 PO node 40 37 COMP node 49 FO P3 P0 istype reg_sr buffer _State P3 P2 P1 PO H L Ck X Le De Le ib equations P3 P2 P1 P0 F0 ap PR LEO P3 P2 Pl PO erte Clk Output Next State Present State Input F0 S COMP P0 S P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 0 to 1 COMP P1 S PO R P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 1 to 2 COMP P0 S P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 2 to 3 COMP P2 S P1 R PO R P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 3 to 4 COMP P0 S P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 4 to 5 F0 R COMP P1 S PO R P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 5 to 6 COMP P0 S P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 6 to 7 COMP P3 SP2 Rye KEE en GE ae te P2O0 te TRO amp POLO me HC has TT tO 8 COMP P0 S P3 Q amp P2 Q amp P1 Q amp P0 Q amp Clr 8 to 9 P3 R P2 R P1 R P0 R COMP Clear After Preset clocking is inhibited until High to Low clock transition test_vectors C1k PR Clr gt _State F0 L O es dE ER rees X y XI i E a lg 20 sor ZE iil Ais Preset Aigi 1 0 O gt TT H Preset low L Ck 0z 0 A gt O H COMP forces to State 0 L Ck vis 0 a Sal t HJ K vectors edited Ck 0 1 es O H Clear end The second equation p
39. EREEREER n 5 26 A e E 5 27 OF sh OF EE 5 26 X XORS and operator priority Operator cccccccccccccccccnnnnncnannnnnn nn EXIDO Ee 5 27 flip flop emulation eg OO TEE optimization of Synario ABEL Designer User Manual Index 9 Index Index 10 Synario ABEL Designer User Manual
40. L Designer User Manual ABEL Design How to Use the Project Navigator Figure 1 3 ABEL Project Navigator af ABEL Project Navigator File Options Window Help olrategy Sources in Project Processes for Current Source No Project Open No Processes Available select New Project or Open Open a projectto make processes available Project inthe File menu to open a project ME Open Start View Properties log What is the Project Navigator The Project Navigator is the primary interface for accessing ABEL Designer Since ABEL consists of many parts the Project Navigator connects all the pieces in a seamless environment The Project Navigator supports top down design through the concept of sub projects A designer can create a top level block diagram that represents a system which may be an IC ICs on boards a board or a set of boards As a designer further defines the system each level can be identified as a sub project type designing it as an IC Design or Multi project Simulation For example from the Project Navigator you can select all the components for a design such as HDL sources as well as specification documents and test files The Project Navigator helps you keep track of all of the parts of your design and keeps track of the processing steps necessary to move the design from the conceptual stage through to implementation in an actual programmable IC The Project Navigato
41. L HDL to describe the circuit behaviorally This example best demonstrates design entry for a PLD Describing the Circuit using ABEL HDL To start a new project and set up a new directory for this tutorial 1 2 3 S Start Synario The Project Navigator window appears From the File menu click on New Project In the Choose Project Type dialog box click on IC Design for the project type In the Create New Project dialog box navigate to a directory where you want to save your project files Click on the Create Directory button to add a new project directory We will assume that the name of the directory is tutor2 In the Create New Project dialog box enter tutor2 syn for the Project Filename Click on the OK button to exit the New Project dialog box To change the name of the project design 1 Double click on the project notebook icon or project name E Untitled that appears at the top of the Sources in Project window to change the project name In the Project Properties dialog box text field enter a descriptive title for the project such as Tutorial session 2 From the File menu click on Save the changes to your new project Now you are ready to enter the ABEL HDL version of this design Synario ABEL Designer User Manual 3 7 Overview of ABEL HDL Sources To enter the ABEL HDL description 1 3 8 Choose Add New to Project from the Source menu to create a new design source Select
42. Navigator Shows all the design files associated with a project Each object in the list is identified with an icon For example at the top of the Sources window is the Project Notebook El it is denoted with the engineering notebook icon In multi the Project Notebook is labeled as three bit multiplier To see all the objects in the project use the scroll bar at the right edge of the Sources window to move up and down in the list There are several kinds of design sources in ABEL including ABEL HDL modules and ABEL HDL test vectors for simulation The Notebook Icon El In the Project Navigator Sources window projects are organized by collecting all of a project s files into a Project Notebook represented by the notebook con Bb The Project Notebook lists the schematics and behavioral sources that create the logic of your design testing files and the device specification The Project Notebook can also include any other design documents you want to keep with the design such as design specifications meeting notes or other supplementary files Each project is stored in its own directory to simplify archiving To rename the project double click the project icon Bl in the Source window Project Sources Your design can be represented in various ways Those representations are called sources A source is any element in the design such as a HDL file schematic or simulation file Sources are displayed in the Project Navi
43. OR This is because the XOR operator and the OR operator have the same priority in ABEL HDL See example octalf abl Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Using Implied XORs in Equations High level operators in equations often result in the generation of XOR operators If you specify the XOR attribute these implied XORs are preserved decreasing the number of product terms required For example module X2 dor dar Ee pin istype reg xor CLOCK pun count q3 q0 equations count cik clock count count FB 1 end This design describes a simple four bit counter Since the addition operator results in XOR operators for the four outputs the xor attribute can reduce the amount of circuitry generated Note The high level operator that generates the XOR operators must be the top level lowest priority operation in the equation An equation such as count count FB 1 amp reset does not result in the preservation of top level XOR operators since the amp operator is the top level operator Using XORs for Flip flop Emulation Another way to use XOR gates is for flip flop emulation If you are using an XOR device that has outputs featuring an XOR gate and D type flip flops you can write your design as if you were going to be implementing it in a device with T type flip flops The XOR gates and D type flip flops emulate the specified T type flip flops When using
44. Project a lj Collapse Project Title d Virtual Device Etopabel topabel abl Top level ABEL HDL source M subl sub1 abl F sub sub2 abl Lower level ABEL HDL sources SLI su z ad What Is a Hierarchical Design ABEL supports full hierarchical design Hierarchical structuring permits a design to be broken into multiple levels either to clarify its function or permit the easy reuse of lower level sources For instance a large complex design does not have to be created as a single module By using hierarchical design each component or piece of a complex design could be created as a separate module A design is hierarchical when it is broken up into modules For example you could create a top level ABEL HDL describing an IC In the ABEL HDL file you could interface to lower level modules that describe pieces of the design The module represented by the ABEL HDL interface is said to be at one level below the ABEL HDL file in which the interface statement appears Regardless of how you refer to the levels any design with more than one level is called a hierarchical design In ABEL there is no limit to the number of hierarchical levels a design can contain Synario ABEL Designer User Manual 2 1 Hierarchical Design in ABEL Why Use Hierarchical Design The primary advantage of hierarchical design is that it encourages modularity For instance a careful choice of the circuitry you select to be a module will g
45. Q1 d D O Q1 TE e Be Mux Q1 clk gt Clk AR Q1 ar Q1 q a Q1 pin IQ1 pin a Detailed descriptions are written for the various input ports of the macrocell shown in the figure above with dot extension labels Note that the macrocell features a configurable inversion between the Q output of the flip flop and the output pin labeled Q1 If you use this inverter or select a device that features a fixed inversion the behavior you observe on the Q1 output pin will be inverted from the logic applied to or observed on the various macrocell ports including the feedback port Q1 q 0665 3 Pin to pin descriptions on the other hand allow you to describe your circuit in terms of the expected behavior on an actual output pin regardless of the architecture of the underlying macrocell The following figure illustrates the pin to pin concept Figure 5 2 Pin to pin Macrocell a Q1 b OR a Q1 b 1748 1 When pin to pin descriptions are written in ABEL HDL the generic macrocell t Synario ABEL Designer User Manual 5 13 shown above is synthesized from whatever type of macrocell actually exists in the target device Synario ABEL Designer User Manual 5 9 Synario ABEL HDL Design Considerations Examples of Pin to pin and Detailed Descriptions Two equivalent module descriptions one pin to pin and one detailed are shown below for comparison Pin to pin Module Description module OI 1 Q1 pin isty
46. Sy Ors legs ty is I Orc 0p I 0 0 1 0 0 1 Oy 0 O 0 0 O 0 0 O 0 0 O t 0 0 Op i ick Lys Ue 1 0 0 1 0O 0 1 0 0 1 0 0 O 0 0 O 0 0 O xy O 0 1 O 0 O 0 0 E O 0 O y 0 O 0 O 0 Lac Lac E Les Lac Lac O Lac Lac Lac Lac Lac Lac Lac Lac Lac Lac Lac Lal ETS PAT Pet ee ne eS E ZZ eee Est Se ZE eee Eer E ZZ St Eet lr yd yd dd dd dd ld Lac Lac ee ee dd Lac do dd ee Lac eee B 5 Synario ABEL Designer User Manual JEDEC Simulation How to Invoke Simulation To start the Simulate JEDEC process do the following 1 Select the test vector ABV file in the Sources in Project window The simulation processes will then appear in the Processes for Current Source window 2 To change simulation properties single click on Simulate JEDEC and then click on the Properties button Click on OK to exit the Properties dialog box when you are finished 3 To start a simulation double click on Simulate JEDEC Refer to online help and the Equation and JEDEC Simulators Manual for more information B 6 Synario ABEL Designer User Manual C Waveform Viewing What is Waveform Viewing Editing The Waveform Viewer displays the results of logic or timing Simulations The logic states of schematic nets are displayed as time line traces waveforms The nets whose waveforms are to be displayed can be intera
47. Synario ABEL Designer User Manual June 1998 MINC Washington Corp and Data I O have made every attempt to ensure that the information in this document is accurate and complete MINC Washington Corp and Data I O assume no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies No part of this document may be reproduced or transmitted in any form or by any means electronic or mechanical for any purpose without written permission from MINC Washington Corp and Data I O MINC Washington Corp Sales 1 888 SYNARIO or edasales synario com Technical Support 1 800 789 6507 or sts synario com World Wide Web www synario com Acknowledgments MINC is a registered trademark of MINC Incorporated Data I O is a registered trademark of Data I O Corporation Synario Synario ECS and ABEL are either trademarks or registered trademarks of Data I O Corporation in the United States and or other countries Other trademarks are the property of their respective owners Copyright 1996 1997 Data I O Corporation Portions copyright 1997 1998 MINC Washington Corp All rights reserved Table of Contents Preface 1 ABEL Design 1 1 ADOL MHIS En TEE Programmable IC Design in ABEE What is Prog
48. The ABEL HDL modules you create can vary depending on how you want to physically implement your design For instance a design created for a PLD might be different than one for a Complex PLD and both designs would be different than one for an FPGA Chapter 5 discusses these ABEL HDL design considerations language features and more Synario ABEL Designer User Manual 4 ABEL HDL Compiling Overview of ABEL HDL Compiling In Synario when you create an ABEL HDL module and import that module into a design this is called Design Entry Design Entry for ABEL HDL modules is primarily a function of the Project Navigator and a text editor used to enter the ABEL HDL code Compiling in general involves every process after Design Entry that prepares your design for simulation and implementation These processes include compiling and optimizing steps which can be done at the level of a single module or for the entire design However which processes are available for your design depends entirely on which device architecture you want to implement your design In other words the available processes are purely a function of which type of device PLD CPLD or FPGA you are designing for and which Vendor Kit Device Kit or Interface Kit you are currently using This chapter discusses some of the general considerations and processes used in ABEL HDL compiling For a more detailed discussion of ABEL HDL compiling refer to the documentation incl
49. When Q3 is high the machine is in one of the Cn states Q3 can be assigned directly to an output pin on the device Notice also that these bit values change by only one bit as the machine cycles through the states as is recommended in the section above Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Using Symbolic State Descriptions Symbolic state descriptions describe a state machine without having to specify actual state values A symbolic state description is shown below Figure 5 17 Symbolic State Description module SM a bye lock pun TAPUS a_reset s_reset DLN reset inputs AY pin istype com simple outputs sregl state_register S0 S3 state equations sregl clk clock state_diagram sregl state SO GOL Sch wash Za a b y H state Sl if a amp b then S2 with x 0 Yi ar g state S2 x a b Al if a then S1 else S2 state S3 GOCO 0 wiih x cle FE E async_reset SO a_reset sync_reset S0 s_reset end Symbolic state descriptions use the same syntax as non symbolic state descriptions the only difference is the addition of the State_register and State declarations and the addition of symbolic synchronous and asynchronous reset statements Symbolic Reset Statements In symbolic state descriptions the Sync_Reset and Async_Reset statements specify synchronous or asynchronous state machine reset logic For example to specify that a state machine
50. XORs in this way you should not use the xor attribute for output Signals unless the target device has XOR gates JK Flip Flop Emulation You can emulate JK flip flops using a variety of circuitry found in programmable devices When a T type flip flop is available you can emulate JK flip flops by ANDing the Q output of the flip flop with the K input The Q output is then ANDed with the J input This specific approach is useful in devices such as the Intel Altera E0600 and E0900 The following figure illustrates the circuitry and the Boolean expression Synario ABEL Designer User Manual 5 27 Synario ABEL HDL Design Considerations Figure 5 10 JK Flip flop Emulation Using T Flip flop 4 AND2 Preset K 2 We 3 Clear 5 Q OR2 AND2 3 ved 3 g gt 6 zl _ Clock Q J amp IQ K 8 Q 0777 1 You can emulate a JK flip flop with a D flip flop and an XOR gate This technique is useful in devices such as the P20X8 The circuitry and Boolean expression is shown below Figure 5 11 T Flip flop Emulation Using D Flip flop Preset Clear 5 Q j XOR 3 i gt 6 Clock Q T6 0Q 0755 1 Finally you can also emulate a JK flip flop by combining the D flip flop emulation of a T flip flop Figure 5 11 with the circuitry of Figure 5 1 The following figure illustrates this concept Figure 5 12 JK Flip flop Emulation D Flip flop with XOR Q ON A 02104 Ke UI negated Simui in Digital Electronics Apad Bama and Can Porat J
51. ZK re era zez E ks ae Ae EE Ta E ene y RO E ES Ha loe ze Zb hr kt EE 2 Lts p e ER op Ke E eg E Abee ck o EW end Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Design 2 Explicit Pin to Pin Active low module act_lowl Goyal pin istype reg Clock pirg reset pan equations dl 00 clock llal q0 q1 q0 FB 1 amp reset test_vectors clock reset gt ql q0 Cotes y E A eee O a GE Le A O aly ls ose o Ue dE pe SID ke E de 0 J gt Ii p ZE JS D weed 3 Y MIA we EE als Luca OE ss MO a is ES ffe ps e ahs ee Kr Ors ge G Ce end Design 3 Explicit Detailed Active low module act_low3 a0 ql pin istype reg_d buffer clock pin reset pirn equations q1 q0 c1ik clock q1 q0 D q1 q0 Q 1 amp reset test_vectors clock reset gt q1 q0 DH Be age SR res O O a E ees e 2 Jh ee ll O Ale LK Lk t ge E ees E a KEE gt aCe y Et ZE es HK 2 e a Ae DH oft e th SSH Ok EE e ak da ege lt 9 E Kies E Oe ee Ae AC Kies E J eat E O15 end Both of these designs describe an up counter with active low outputs The first example inverts the signals explicitly in the equations and in the test vector header while the second example uses an active low declaration to accomplish the same thing Synario ABEL Designer User Manual 5 15 Synario ABEL HDL Design Considerations Polarity Control Automatic polarity control is a p
52. an individual source file by highlighting the file in the Sources in Project window and double clicking on Compile Logic in the Processes for Current Source window Alternatively you can double click on a report in the Processes for Current Source window and compile automatically To compile an ABEL HDL file and view the report 1 Highlight the ABEL HDL source file andff abl in the Sources in Project window 2 Double click on Compiled Equations in the Processes for Current Source window The source file is compiled and the resulting compiled equations are displayed in the Report Viewer as shown in the figure on the next page If the ABEL HDL file contains syntax errors the errors are displayed in a view window and an error indication appears in the Processes for Current Source window Synario ABEL Designer User Manual 4 3 ABEL HDL Compiling The following figure shows compiled equations for AND Gate and Flip flop EL raro Project navigator TUTORZSYN _ File View Source Process Options Window Help Dausse d Pisti O OOOO E Tutorial session 2 eg O Compile Logic Virtual Device GCheck Syntax Elandff vectors Compiler Listing til andff andff abl P Terms Fan in Fan out Type Name attributes Pin output_q REG Pin output_q c Best P Term Total 2 Total Pins Nodes 4 Average P Term Output 1 Equations output_q input_1 amp input_2 output_q C Clk Reverse Polarity Equations fo
53. an perform additional optimization for design outputs if you specify the dcstate attribute If you enter dcstate in the source file all state diagram transition conditions are collected during state diagram processing These transitions are then complemented and applied to the design outputs as don t cares You must use dcstate in combination with dcset or the dc attribute Synario ABEL Designer User Manual 5 25 Synario ABEL HDL Design Considerations Exclusive OR Equations Designs written for exclusive OR XOR devices should contain the vor attribute for architecture independence Optimizing XOR Devices You can use XOR gates directly by writing equations that include XOR operators or you can use implied XOR gates XOR gates can minimize the total number of product terms required for an output or they can emulate alternate flip flop types Using XOR Operators in Equations 5 26 If you want to write design equations that include XOR operators you must either specify a device that features XOR gates in your ABEL HDL source file or specify the xor attribute for all output signals that will be implemented with XOR gates This preserves one top level XOR operator for each design output For example module X1 Q1 pin ZE COM or 4 arby 0 pany equations OL as Oc Es end Also when writing equations for XOR PALs you should use parentheses to group those parts of the equation that go on either side of the X
54. an save the Waveform Viewer configuration using the Save and Save As commands The information saved consists of e Waveform names displayed e Trigger conditions Printing Waveforms The Print command from the File menu prints the waveform display A dialog box Figure 3 is displayed with the following controls Figure 3 Print Waveforms Dialog Box Print YWaweforms Start T ime End Time 100 000 0 ms Time Scale 11 145 5 nsfinch sheets Dn Names Width 1 50 inches Ix Names On All Sheets O Portrait 0 Landscape Start Time Simulation time at which the plot is to begin Stop Time Simulation time at which the plot is to finish Time Scale Scale of plot in nanoseconds inch Changing the time scale changes the number of pages required to display the waveform Sheets Number of sheets to plot the waveforms The time scale is automatically adjusted to fill the specified number of sheets Names Width Waveform names are shown in a vertical strip along the left hand edge of the page This parameter determines the width of this strip Names on The Names strip is printed on every page if the Names On All Sheets Sheets check box is marked Otherwise only the first sheet displays the names of waveforms and there is more display space on the following sheets Portrait Displays the time axis along the short edge of the paper Landscape Displays the time axis along the long edge of the paper This is the default
55. archical path of the level you re currently on All signals at a given level are shown in the right list box To add a Signal to the display click on its name then click the Add Wave button Or just double click on the signal s name The signal is immediately added at the bottom of the Waveform Viewer display Synario ABEL Designer User Manual Waveform Viewing The waveform display can contain up to 256 waveforms Use the vertical scroll bar to select the waveforms to view Using the Probe Item Command If there is a schematic for the design the Probe Item command is the easiest way to add waveforms to the display Click on the desired net in the Hierarchy Navigator and the waveform for that net is added to the display Buses from the schematic can be probed but the bus must be probed at the highest level at which it exists in the hierarchy The Probe Item command is available only when the Waveform Viewer is used with the Hierarchy Navigator Creating Multi Signal Buses You can create a bus display of two or more signals whether or not they are related Highlight the first signal you want in the bus then click on Add to Bus The signal is added to the edit box at the top left Continue adding signals this way until the bus is arranged the way you want it Then click on the Show button to add the bus to the display To change your bus selections click on the edit box You can then manually edit the list to del
56. are You do not have to declare all output pins as ports Any undeclared outputs become No Connects or redundant nodes Redundant nodes can later be removed from the designs during post link optimization The following source fragment is an example of a lower level interface statement module lower interface a 0 d3 dqd0 7 gt z0 z7 3 title example of lower level interface statement This statement identifies input a d3 d2 d1 and dO with default values and outputs zO through z7 For more information see Interface lower level in the ABEL HDL Reference Manual Specifying Signal Attributes Attributes specified for pins in a lower level module are propagated to the higher level source For example a lower level pin with an invert attribute affects the higher level signal wired to that pin it affects the pin s preset reset preload and power up value s Output Enables OE Connecting a lower level tristate output to a higher level pin results in the output enable being specified for the higher level pin If another OE is specified for the higher level pin it is flagged as an error Since most tristate outputs are used as bidirectionals it might be important to keep the lower level OE J2 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Buried Nodes Buried nodes in lower level sources are handled as follows Dangling Nodes Lower level nodes that do not fanout are propag
57. arge number of test vectors for this design simply add the following statements to the end of the pwmdac abl source just prior to the end statement If you do not want to type in these statements use the source file editor to cut and paste the statements from the pwmdac abl file provided in the examples directory If you imported the pwmdac abl file at the beginning of this tutorial your design will already contain the test vectors and you can skip this step declarations Ri testPWM macro i test_vectors clk clr rclilk d7 dqd0 gt pwm load store K RM es oe aCe valk IA gt Og EE a ek dg repeat 1 elem oO Us 0 LL gs DER EENS repeat lt 41 pe Dor Us 0 egen i Bis e SOP ig les Kenn Ub 5 Un 0 AS y MOE Sch hy Ley A CU 0 d de ds Salle oy Or aci E a Ue 0 A bk en Us 0 ls testPEwM 12 testPWM 187 testPWM 36 testPWM 20 testPWM 8 3 1 4 16 Synario ABEL Designer User Manual ABEL HDL Compiling Since this design requires many clock cycles to test the function of the circuit the test vectors are written using the Project Navigator s macro and directive facilities First a macro testPWM is defined that generates the required test vectors to test one sequence of the circuit approximately 250 clock cycles for a given value repeat directives are used to run the design through the specified number of cycles and check that the pwm output remains low Then another repeat directive gener
58. ated to the higher level module and become dangling nodes Optimization may remove dangling nodes Combinational nodes Combinational nodes in a lower level module become collapsible nodes in the higher level module Registered nodes Registered nodes are preserved with hierarchical names assigned to them Declaring Lower level Modules in the Top level Source To declare a lower level module you match the lower level module s interface statement with an interface declaration For example to declare the lower level module given above you would add the following declaration to your upper level source declarations lower interface a d3 d0 gt z0 z7 You could specify different default values if you want to override the values given in the instantiated module otherwise the instantiated module must exactly match the lower level interface statement See Interface top level in the ABEL HDL Reference Manual for more information Instantiating Lower level Modules in Top level Source Use a functional_block declaration in an top level ABEL HDL source to instantiate a declared lower level module and make the ports of the lower level module accessible in the upper level source You must declare sources with an interface declaration before you instantiate them To instantiate the module declared above add an interface declaration and signal declarations to your top level declarations and add port connection equations to your t
59. ates the remaining cycles and tests to ensure that the pwm output remains high To perform Equation simulation save the modified pwmdac abl source You will notice that after the source has been saved a Test Vector file pwmdac abv is automatically created by the system Highlight this ABV file and double click on the Simulate Equations process in the process window to begin the simulation Synario Project Navigator TUTOR3 5 YN View Source Process Options Jools Window Help NI Strategy Normal El Processes for Current Source A pwmdac pwendac all Equation Simulation Report A counter counter all O Equation Simulation Waveform Double click to open the selected test Double click the item in the list or select the Start button to Wechors Before simulating the design the Project Navigator will re compile the pwmdac abl source file and process the design through the linking optimization and fitting steps When this procedure is finished the actual simulation begins Because this set of test vectors is quite large consisting of over 1000 individual vectors the simulation will take a noticeable amount of time Synario ABEL Designer User Manual 4 17 ABEL HDL Compiling After the Equation simulation is complete double click on the Equation Simulation Report process A file viewing window appears containing the simulation results in tabular form You can sel
60. ation and a programmable inverter before the register cannot be specified using invert and buffer Flip flop Equations Pin to pin equations using the assignment operator are only Supported for D flip flops ABEL HDL does not support the assignment operator for T SR or JK flip flops and has no provision for specifying a particular output pin value for these types If you write an equation of the form OL aus vile and the output Q1 has been declared as a T type flip flop the ABEL HDL compiler will give a warning and convert the equation to Q1 T 1 Since the T input to a T type flip flop does not directly correspond to the value you observed on the associated output pin this equation will not result in the pin to pin behavior you want To produce specific pin to pin behavior for alternate flip flop types you must consider the behavior of the flip flop you used and write detailed equations that stimulate the inputs of that flip flop A detailed equation to set and hold a T type flip flop is shown below Q1 T 01 0 Synario ABEL Designer User Manual 5 17 Synario ABEL HDL Design Considerations Feedback Considerations Dot Extensions 5 18 The source of feedback is normally set by the architecture of the target device If you don t specify a particular feedback path the design may operate differently in different device types Specifying feedback paths with the FB Q or PIN dot extens
61. ce architectures The AP extension like the D and Q extensions is associated with a flip flop input not with a device output pin If the target device has inverted outputs the design will not reset properly so this ambiguous reset behavior is removed by using the buffer attribute which reduces the range of target devices to those with non inverted outputs Using ASET instead of AP can solve this problem if the fitter being used supports the ASET dot extension Versions 5 and 7 of the design above and below are unambiguous but each is restricted to certain device classes module Q1_ 71 ol pin istype reg invert Clock Preset pin equations Q1 CLK Clock Q1 AR Preset Q1 Ol bo gt test_vectors Clock Preset gt 01 EE 2 dee ol Ses les La Os of gt 08 EC 4 E gt 1 EA L KE E de ME 1 Jj gt 1 E ae dr ls end Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations When to Use Detailed Descriptions Although the pin to pin description is preferable there will frequently be situations when you must use a more detailed description If you are unsure about which method to use for various parts of your design examine the design s requirements If your design requires specific features of a device such as register preset or unusual flip flop configurations detailed descriptions are probably necessary If your design is a simple combinational function or if it matches
62. ce architecture you have selected Synario ABEL Designer User Manual 1 5 ABEL Design Vendor Kits IC designs are physically implemented into a chip more efficiently when the design is optimized and routed for the IC For example fitters and place and route software designed for the target IC can utilize special features of the IC and map the resource usage more efficiently The Vendor Kit Device Kit or Interface Kit not only controls the processes that are available but it also changes the entire design environment such as the default property values for the target device architecture Depending on which semiconductor vendor you prefer the most you can purchase a Vendor Kit that supports the ICs such as PLDs and FPGAs for that vendor For information about a Vendor Kit refer to the documentation included with the Device Kit or Interface Kit Design Hierarchy 1 6 When designs can be broken into multiple levels this is called hierarchical designing ABEL supports full hierarchical design which permits you to create a design that is divided into multiple levels either to clarify its function or permit the easy reuse of functional blocks For instance a large complex design does not have to be created as a single module By using hierarchical designing each component or piece of a complex design could be created as a separate module For more information on hierarchical designing refer to Chapter 2 Synario ABE
63. cess 3 Examine the compiled equations for the source by double clicking on the Compiled Equations process The Report Viewer displays the Boolean equations that were generated as a result of compiling the ABEL HDL description 4 Select the other ABEL HDL source and repeat the previous two steps to compile it To link the ABEL HDL sources into a single design 1 Click on the device icon GER next to the selected device in the Sources in Project window 2 Double click on Linked Equations in the Processes for Current Source window This process runs the linker and displays the resulting Boolean equations for the entire design in the Report Viewer Scroll down to the equations as shown in the following figure Synario ABEL Designer User Manual 4 13 ABEL HDL Compiling 9ynario Report Viewer File Edit View Options Window Help EASE S tutors eq 2 96 105 Best P Term Total Total Pins Total Nodes Average P Term Output Equations pum ecntri gt qrT tr6 cntr1 gt q6 trr tr6 amp entrl gt q6 trr entrl gt gf entri gt q7 cntrl gt q6 amp CARRYAZ tr entrl gt q6 CARRY 2 entri gt ar amp tr6 amp CARRY 2 tr tr6 amp CARRYAZ2 entri gt qr amp cntrl gt q6 amp CARRYAS rf dT rT C relk r6 d6 r6 C relk Ln 1 Col 1 The design has now been linked into a single Open ABEL design that is ready for device fitting Synario ABEL Designer U
64. cit declaration for inputs and outputs whether a given signal is an input or an output depends on how it is used in the design description that follows The signal output_q is declared to be type reg which implies that it is a registered output pin The actual behavior of output_q however is specified using one or more equations 8 To describe the actual behavior of this circuit enter two equations in the following manner Equations output_q input_1 amp Input 7 Clk output_q cik These two equations define the data to be loaded on the registered output and define the clocking function for the output Test Vectors The traditional method for testing ABEL HDL designs is to use test vectors Test vectors are sets of input stimulus values and corresponding expected outputs that can be used with both Equation and JEDEC simulators Test vectors can be specified in two ways They can be specified in the ABEL HDL source or they can be specified in an external Test Vector file ABV When you specify the test vectors in the ABEL HDL source the system will create a dummy ABV file that points to the ABEL HDL source containing the vectors This file is necessary because an ABV file is required in order to have access to the Equation and JEDEC simulation processes Add test vectors to the source file as shown below Test_vectors Clk inp t l y ENEE 2 0 l 0 0 gt OULDUL q gt 0 0 gt O 1 Lae A
65. converts JEDEC vectors to tmv format When reading JEDEC test vectors the simulator copies the H L and Z into the output vector and all test conditions into the input vector It also makes the following conversions H Converted to 1 L Converted to 0 Converted to 1 or the user specified value Converted to O or the user specified value Kei Expanded to three vectors with C taking on the values 0 1 and then 0 Use a Trace Type of Clock to observe the clock conversions LU Expanded to two vectors taking on the values O and then 1 Use a Trace Type of Clock to observe the clock conversions K Expanded to three vectors with K taking on the values 1 0 and then 1 Use a Trace Type of Clock to observe the clock conversions D Expanded to two vectors taking on the values 1 and then 0 Use a Trace Type of Clock to observe the clock conversions Synario ABEL Designer User Manual B 3 JEDEC Simulation How to Use the JEDEC Simulator Test Vector Files To use the JEDEC simulator you will have to create test stimulus with ABEL HDL test vectors See the ABEL HDL Reference for more information about test vector syntax There are two ways to specify test vectors The most common method is to place test vectors in the ABEL HDL source file If you use this method the Project Navigator will detect the presence of test vectors in the source file and create a dummy test vector file This file indicates to the system t
66. ctively chosen from the schematic Query functions can be used to trace signals to their source on the schematic Trigger functions can be used to locate the occurrence of a specific logic event Delays between events can be measured with markers The Waveform Editor for Synario lets you create the stimulus graphically by clicking and dragging with the mouse You see exactly what each waveform will look like as well as its timing relationship to all the other waveforms The Waveform Editor is discussed in the Waveform Tools Manual This appendix discusses the following topics e Starting the Waveform Viewer e Selecting the Waveforms to View e Moving Around e Analysis Techniques e Saving and Printing Waveforms e Waveform Viewer Configuration For information on the following topics refer to the Waveform Tools Manual e The Waveform Editor e Waveform Viewer and Editor Command Reference e The Waveform Description Language WDL e Drawing Waveforms Synario ABEL Designer User Manual C Waveform Viewing Starting the Waveform Viewer The Waveform Viewer is typically used in conjunction with a simulator You must run the simulator before you can run the Waveform Viewer without simulation information the Waveform Viewer has no data to display Synario ABEL Designer User Manual Waveform Viewing Waveform Viewer Window Figure 1 shows a typical Waveform Viewer display Following it is a description of the elements of t
67. d Jumps to the beginning or end of the waveform To Marker Jumps to the current marker position To Time The display is centered on a time you specify Next Change Jumps to the next change in signal polarity Next Trigger Jumps to the next trigger point Jumping to Events Events are logic level changes A change in any signal in a bus is considered an event on that bus Timing measurements are usually made between events Several commands in the Waveform Viewer make it easier to find events and align the cursor to events These commands are especially helpful when the display is zoomed out and the resolution is too low to accurately position the cursor The Jump Next Change command moves the query cursor to the next event on the selected waveform It s commonly used to measure the time difference from one event to another 1 Position the query cursor on the waveform with the first event before the first event 2 Move the query cursor to the first event by selecting the Next Change command This positions the cursor exactly at the first event 3 Execute the Place Mark command to set the marker at the first event 4 Position the query cursor on the waveform containing the second event before the second event 5 Move the cursor to the second event by selecting the Next Change command The time difference between the two events is displayed on the prompt line This procedure works the same way with the Jump Next Trig
68. d specifying feedback directly from the register restricts the device architectures in which the design can be implemented Furthermore the equations describe only the inputs to and feedback from the flip flop and do not provide any information regarding the configuration of the actual output pin This means the design will operate quite differently when implemented in a device with inverted outputs a simple P16R4 PAL device for example versus a device with non inverting outputs such as an E0600 To maintain the correct pin behavior using detailed equations one additional language element is required a buffer attribute or its complement an invert attribute The buffer attribute ensures that the final implementation in a device has no inversion between the specified D type flip flop and the output pin associated with Q1 For example add the following to the declarations section Ql pin istype buffer 5 8 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Detailed Descriptions Designing for Macrocells One way to understand the difference between pin to pin and detailed description methods is to think of detailed descriptions as macrocell specifications A macrocell is a block of circuitry normally but not always associated with a device s I O pin The following figure illustrates a typical macrocell associated with signal Q1 Figure 5 1 Detailed Macrocell HI ap OT oe AP
69. d statements exactly as you do when you create an ABEL HDL source file Also note that all pin and node declarations must be included as well as any constant declarations It s important to remember to change the pin declarations in the test vector file every time you change the pin declarations in the source You may wonder if there are any advantages to placing test vectors in the ABV file instead of in the ABEL HDL source The most obvious advantage is an improvement in processing time By placing test vectors in the ABV file you will be able to change the test vectors and re simulate without having to re compile the logic This can make a significant difference in large hierarchical designs Figure A 2 Example ABV File module scan_tv O EAN A TSE clk pin q5 q4 q3 q2 q1 q0 pin istype reg invert up down pin istype com invert test vectors rst cilik gt q5 q4 q3 q2 0 00 up down KE EE CL eee E R Xa Xyp Ro Ry X x e EL ig SO Al Ss Ls De Ue Os O des jo Dl EJ gp ee a A Mi O ip di Us OP Je E li E Oly O da Ue De e E es EP a e Us o Ee Oye Aen d Wa les K On Zo Se LA age Os On Ue Dig ER 8 os E e ds UL E OO 0y Os TU ir dE ls E Ue die lO as Dr DU Oe Ay Mig les Ei Bl e AE O ds Ben Ue Oe E o le EU e a La De Oe ly HO Dio ie a Js 0 as Ee Eben os ge Be G 29 E T3 Synario ABEL Designer User Manual A 3 Equation Simulation H E ge es Tl AE Ue Ue Oye e MOG ee On Ge SDS
70. d with the PIN extension for example count count pin 1 the pin feedback path will be used If the specified device does not feature pin feedback an error will be generated Output enables frequently affect the operation of fed back signals that originate at a pin Q Extension Signals specified with the Q extension for example count d count g 1 will originate at the Q output of the associated flip flop The fed back value may or may not correspond to the value you observe on the associated output pin if an inverter is located between the Q output of the flip flop and the output pin as is the case in most registered PAL type devices the value of the fed back signal will be the complement of the value you observe on the pin D Extension Some devices such as the MACH210 and P18CV8 allow feedback of the input to the register To select this feedback use the D extension Some device kits also Support COM for this feedback refer to your device kit manual for detailed information Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Dot Extensions and Architecture Independence To be architecture independent you must write your design in terms of its pin to pin behavior rather than in terms of specific device features such as flip flop configurations or output inversions For example consider the simple circuit shown in the following figure This circuit toggles high when the Toggle in
71. dition is met the machine goes to the cleared register state This behavior can also cause problems if the cleared register state is undefined in the state diagram because if the transition conditions are not met for any state the machine goes to an undefined state and stays there WW 0774 1 Synario ABEL Designer User Manual 5 31 Synario ABEL HDL Design Considerations To avoid problems caused by this clearing behavior always have a state assigned to the cleared register state Or if you don t assign a state to the cleared register state define every possible condition so some condition is always met for each state You can also use the automatic transition to the cleared register state by eliminating product terms and explicit definitions of transitions You can also use the cleared register state to satisfy illegal conditions 5 32 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Other Flip flops If none of the state conditions is met in a state machine that employs JK RS and T type flip flops the state machine does not advance to the next state but holds its present state due to the low input to the register from the OR array output In such a case the state machine can get stuck in a state You can use this holding behavior to your advantage in some designs If you want to prevent the hold you can use the complement array provided in some devices such as the F105 to detect a no conditions
72. dule Hierarchical Design Considerations ccccceecceeeeeeeeeeeeeeeeeeeeeeeeeeas Prevent Node CollapsSing ccccssseneeccceeeeeessecceesennannteeeseseegs Whati ADELA e EE Mixed Design ENU EE A First Look at a Design using ABEL HDL Gources Opening an Existing Deelgn ke ENN ENN KENNEN KENNEN KEN gent we ee geteilt Silver EE E Examining the Project Gources Creating a PLD Design Consisting of ABEL HDL Sources s es Describing the Circuit using ABEL HDL ccccceeee eee eeeeeeeees The ABEL HDL Reference cccccccecssceueeuveeuseuueeueeeneeuueureenns Creating a Hierarchical ABEL HDL Design for a CPLD Description of the UCI aa ENN ENN EEN Entering the e leet E LEE To change the name of the project design cece eee e ees Create or Import ABEL HDL Sources Using ABEL ADL Hierarchy EE The ABEL HDL Reference ccccccuecssccueeuueesseuuceueeenseuueureeens Creating an FPGA Design using ABEL HDL ccc cccce cece eee e enna Entering the D SIQN ccccccccsseeceessenneneeeeeeeeesseeeeegnnnnnannees Create or Import ABEL HDL Sources Integrating ABEL HDL Designs into Larger Circuits Synario ABEL Designer User Manual Table of Contents The ABEL HDL References xx NNN SNE EKNNKNKKN EK NNN NEE ERKENNEN KN KEN ABFE el EI ei nl TU e RE ABEL HDL Design Considerations 4 ABEL HDL Compiling suscitada eli rl it iia Overview of ABEL HDL Compiling e
73. e eee eeeeeeeaaaaaaes SOW PE An E II DUDIC O parda proa Mie PP a nO Selecting the Bus Value RadiX ssnsssssssssssnessnnssssnssnsnrensnrns Movino ATONG EE View EE eg polo y PP Poe o A e o E E E Poo Moving the Query CUPSO Paisa JUMPA LO EVE ns ssp rara sara lala Lee AivalysiS TECORIQUES sia Logic Level and Time Measurements ccceceeeeeeeeeeeeeeeeeeeeeees Interaction with the Hierarchy Navigator Displaying Simulation Values on a Schematic 00coccccccccnnnccccnoso VIEW REDO E Saving and Printing Waveforms C 10 SAVING E e e EE Printing WaveformS EE C 10 Synario ABEL Designer User Manual vii Table of Contents viii Synario ABEL Designer User Manual 1 ABEL Design About this Manual This manual discusses Programmable IC entry testing and design in ABEL This manual assumes that you have a basic understanding of IC design ote Tf you are using the Programmable IC Designer product instead of ABEL Designer please refer to the Synario Programmable IC Designer User Manual for information on IC Design The information in this manual is intended for ABEL users Programmable IC Design in ABEL What ts Programmable IC Designing Programmable IC designing is creating a design that can be implemented into a programmable IC also called a chip or device PLDs Programmable Logic Devices and CPLDs Complex PLDs are a few examples of programmable ICs Figure 1 1 on the next page shows an example IC Design
74. ect other report formats by highlighting the Simulate Equation process and then clicking on the Properties button You can view the waveform results by double clicking on the Equation Simulation Waveform process ABEL HDL for FPGAs This section continues the FPGA discussion started in Chapter 3 in the section titled Creating an FPGA Design using ABEL HDL Since the FPGA design process can vary drastically from one device architecture to another you should refer to the Device Kit manual and its online help for information on ABEL HDL synthesis for FPGA devices Running Processes To start a process such as Verilog Functional Simulation click on the appropriate source in the Project Navigator Sources for Current Project window then double click on the process in the Processes for Current Source window Using Properties and Strategies For many processes such as the compiling and optimizing there are processing options you can specify These options include compiler options such as custom arguments or processing changes and optimization options such as node collapsing You can use properties to specify these options Properties and Strategies are set in the same manner as described in the previous sections for PLDs and CPLDs For more information about properties refer to the Device Kit manual and online help for the device architecture you are using Selecting a Device 4 18 At some point before fitting or Place
75. ee eeeeeeeeeeeeaaaaaees Architecture Independent Compiling ccccccccccccccccnnnnnnnnnnnnnnn nn ABEL ADE TOF PCOS toni Keeping Track of Processes Auto Update ccccccnccccccnccnnnananans Compiling an ABEL HDL Source File Using Properties and Strategies for BU DS Simulating the PLD Deen REENEN REENEN ABEL ADLTOFCPEDS anios Using Properties and Strategies cccccconcnoccccccnnnnannnnnn ranas SCICCUNG a DEVIN Mapping the Design to the Selected Device To fit the design into the selected CPLD device c cece eee es To create a JEDEC format programming data file Using Test Vectors for CPLD SGmmulaton cece eeeeeeeeeeeees ABEL HDL for FPGAS EE RUNNINO PROCESSES EE Using Properties and Strategies ccceceeeesseeseeeeeeeeeeeeeeeeees Selecting a DOV e rior Mapping the Design to the Selected Device EE ie Io EET ENRERE ESARTE ENEE 5 Synario ABEL HDL Design Considerations ccccssseesesseeseenseseees Overview of ABEL HDL Design ConsideratiONS cccccccccccccnnccccnnn noo Pora rchy Be DL Instantiating a Lower level Module in an ABEL HDL Source Hierarchy and Retargeting and Fttmg Hierarchy and Test Vectors PLD JEDEC Simulation Node CONS SING BE Selective Collapeing enee REENEN REENEN Pin to pin Language gl Device independence vs Architecture independence 5 Signal gg ef Signal Dot EXlENSIONS EEN Pin to pin vs Detailed Descriptions for Regi
76. erforms a transition from state 1 to state 2 by setting the P1 register and resetting the PO register The R dot extension is used to define the reset input of the registers In state 2 the FO register remains set maintaining the high output The third equation again sets the PO register to achieve state 3 PO and P1 both set while the fourth equation resets PO and P1 and sets P2 for state 4 and so on Synario ABEL Designer User Manual 5 4 1 Synario ABEL HDL Design Considerations Wraparound of the counter from state 9 to state O is achieved by means of the complement array node node 49 The last equation defines state O P3 P2 P1 and PO all reset as equal to COMP that is node 49 at a logic low When this equation is processed the fuses are blown as indicated in Figure 5 19 Figure 5 19 shows that state 9 PO and P3 set provides no product term to pull node 49 high Asa result the ICOMP signal is true to generate product term 9 and reset all the buried registers to zero Figure 5 19 Abbreviated F105 Schematic CLR 1 Ss PPP A A HHHH AT AAA es COTTA TR AAA TR cu anpuT LILI LLL LLL Note Clock input not shown on schematic FO OUTPUT 0776 1 FO 00 5 42 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations ABEL HDL and Truth Tables Truth Tables in ABEL HDL represent a very easy and straightforward description method well suited in a number of s
77. ete or rearrange signals Duplicate The Duplicate command copies waveforms The original waveform remains in the display Duplicate is often used to add multiple copies of clock or other control signals Move You can move a waveform from one display location to another Click on one or more waveforms to highlight them Then drag the names to the new position and release the mouse button Hide The Hide command from the Edit menu removes waveforms from the display The Undo command can be used to restore hidden waveforms Selecting the Bus Value Radix Bus values are displayed on the bus waveforms and on the prompt line if a bus is selected You can change the bus radix using the Bus Radix command from the Options menu Click on the Binary Octal Decimal or Hexadecimal radio button in the dialog box that appears Synario ABEL Designer User Manual C 5 Waveform Viewing Moving Around Once the waveforms are displayed there are several ways to manipulate the waveform display area The following sections briefly describe them View Commands The View commands change the horizontal time dimension Different time segments of the displayed waveforms can be viewed Zoom In Zoom Out Pan Full Fit Scroll Bars Increases the horizontal magnification each time it s executed You see a shorter time segment in more detail You can also drag around any part of a waveform to view it in more detail Reduces the current ma
78. evice fitter may interpret the signal incorrectly and delete it Node Node Statements indicate internal signals not accessible by circuitry outside the functional block Signals declared as nodes are expected to have a source and loads For example Figure 3 1 shows a state machine as a functional block State bits S1 through S7 are completely internal all other signals are external Figure 3 1 Hypothetical State Machine as a Functional Block IO IN I2 Ia CLOCK RESET FUNCTIONAL BLOCK CH State bits use internally only TTT Figure 3 2 shows the corresponding signal declarations The CLOCK RESET input and output signals must connect with circuitry outside the functional block so they are declared as pins The state bits are not used outside the functional block so they are declared as nodes Figure 3 2 Signal Declarations CLOCK RESET EOE EE OL ZO STPS erie Pacer aor Ar erode Pin Pin Pin Node Synario ABEL Designer User Manual Overview of ABEL HDL Sources Using Intermediate Signals An intermediate signal is a combinatorial signal that is declared as a node and used as a component of other more complex signals in a design Intermediate signals minimize logic by forcing it to be factored Creating intermediate signals in an ABEL HDL logic description has the following benefits e Reduces the amount of optimization a device fitter has to perform e Increases the chances of a fit e Si
79. f transitions from one state to another In areal device such a state machine is implemented with registers that contain enough bits to assign a unique number to each state The states are actually bit values in the register and these bit values are used along with other Signals to determine state transitions As you develop a state diagram you need to label the various states and state transitions If you label the states with identifiers that have been assigned constant values rather than labeling the states directly with numbers you can easily change the state transitions or register values associated with each state When you write a state diagram you should first describe the state machine with names for the states and then assign state register bit values to the state names Synario ABEL Designer User Manual 5 29 Synario ABEL HDL Design Considerations For an example see the following source file for a state machine named sequence This state machine is also discussed in the design examples Identifiers A B and C specify the states These identifiers are assigned a constant decimal value in the declaration section that identifies the bit values in the state register for each state A B and C are only identifiers they do not indicate the bit pattern of the state machine Their declared values define the value of the state register sreg for each state The declared values are O 1 and 2 Figure 5 13 Using Identifier
80. f one of the bus signals To measure the time difference between two events Le Move the query cursor to the first event Set the marker at this location with the Place Mark command Move the query cursor to the second event The relative time between these two events is shown on the prompt line under the heading Delta Synario ABEL Designer User Manual Waveform Viewing Interaction with the Hierarchy Navigator The Find Item command from the Hierarchy Navigator locates the part of the circuit driving a particular waveform The Navigator automatically displays the appropriate schematic The net associated with the waveform is highlighted This command is useful when you find an interesting event in the waveform display and want to locate the source of the event on the schematic The Find Item command works only with the Hierarchy Navigator The Query command highlights the net associated with the currently selected waveform If the query window in the Hierarchy Navigator is already open its contents change to reflect the latest net queried with the Query command in the Waveform Viewer The Probe Item command adds waveforms to the Waveform Viewer display when you probe a net in the schematic Displaying Simulation Values on a Schematic The logic values determined during simulation are displayed on the schematic loaded in the Hierarchy Navigator As the query cursor is clicked at different points along the time line the log
81. features inverted outputs the design equation is automatically modified to take the feedback from Q bar instead of Q Figure 5 5 Dot Extensions and Architecture independence Circuit 2 SE SEKR gt re ERR Sch 2 BEE EE S E GER TP K D gt aaa Sl 0768 1 If you implement this design in a device with a different architecture such as an E0320 the resulting circuit could be quite different But because this is a pin to pin design description the circuit behavior is the same The following figure illustrates the circuit that results when you specify an E0320 Figure 5 6 Dot Extensions and Architecture independence Circuit 3 5 20 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Dot Extensions and Detail Design Descriptions You may need to be more specific about how you implement a circuit in a target device More complex device architectures have many configurable features and you may want to use these features in a particular way You may want a precise powerup and preset operation or in some cases you may need to control internal elements The circuit previously described using architecture independent dot extensions could be described for example using detailed dot extensions in the following ABEL HDL source file Figure 5 7 Detailed One bit Synchronous Circuit with Inverted Qout module detaill al device P16R8 Sue pain L3 Toggle pan 2 Ena
82. from_armed Oy Ek 05 sens_off 0 0 0 O encoding key_pnd Se fag day Oy 0 key_str dE SOG ley leche key_non Op 0 0 O intermediate signals enter_from_disarmed_ready node enter _ from_armed node sensors_off node key_numeric node key_none node key_pound_star node equations intermediate equations enter_from_disarmed_ready which_code_enter from_disarmed_ready enter _from_armed which_code_enter from_armed sensors off sens_code sens_off key_numeric key_code key_pnd key_code key_str amp key_code key_non key_none key_code key_non key_pound_star key_code key_pnd key_code key_str Synario ABEL Designer User Manual 3 21 Overview of ABEL HDL Sources 3 22 For large designs using intermediate signals can be essential An expression such as IF input code_1 generates a product term AND gate If the input is 8 bits wide so is the AND gate If the expression above is used 10 times the amount of logic generated will cause long run times during compilation and fitting or may cause fitting to fail If you write the expression as an intermediate equation code 1 found node equations code_1 found input code 1 you can use the intermediate signal many times without creating an excessive amount of circuitry IF code 1 found Another way to create intermediate equations is to use the CARRY directive The
83. gator Source s Window They include not only the description of the circuits as represented by schematics state diagrams and hardware description languages but also include waveforms for simulation simulation test fixtures links that connect represent connections to other projects and documentation of the design All those pieces are part of the whole design which includes not only the circuits but the things you need to do to assure yourself that those circuits work as they ought to The design description logic for a project is contained ABEL HDL sources One source file in a project is the top level source for the design The top level source defines the inputs and outputs that will be mapped into the device and references the logic descriptions contained in lower level sources The referencing of another source is called instantiation Lower level sources can also instantiate sources to build as many levels of logic as necessary to describe your design Synario ABEL Designer User Manual ABEL Design ote Ir you build a project with a single source that source is automatically the top level source You might have sources other than ABEL HDL modules These sources might include simulation test vectors documentation files or other files related to Windows applications The type of a source is indicated by the icon to the left of the source name in the Sources Window ote Listed below are the sources for the p
84. ger command Synario ABEL Designer User Manual C 7 Waveform Viewing Triggers A trigger is an event that meets some specified criterion The signal conditions used to define a trigger in the Waveform Viewer are High Low Unknown Change Positive Edge Negative Edge Bus value The Set Trigger command lets you apply any of the above conditions to one or more waveforms A trigger event occurs when all the conditions on all the waveforms are met You can locate a highly specific event by applying these criteria to several waveforms The Next Trigger command advances the query cursor to the next defined trigger event If there is no trigger event the cursor advances to the end of the waveform display Time End Analysis Techniques This section explains the waveform analysis commands You might find it easier to use their accelerator keys than to select them from the menus Logic Level and Time Measurements To measure logic levels and times on a waveform 1 Select Options Query A query cursor appears on the screen 2 Click on the waveform you want to query A vertical line passes through the point you clicked on and the selected signal is highlighted in the name field The prompt line displays the time and logic level at the cursor position If the selected signal is a bus the logic levels of the bus Signals are displayed as a single numerical value in which each binary digit represents the logic level o
85. gnification each time it s executed You see a longer time span with less detail Slides the current viewing window across the waveforms The point you click on becomes the new center point of the display The magnification does not change Clicking in the window fills the display with the full time span of the displayed waveforms Two options are then available e Click at a location you want to see in more detail This returns the window to the previous magnification and pans the view to the selected point e Drag the mouse to form a box around the area you want to zoom in on The magnification is adjusted to display that area The horizontal scroll bar under the waveform display positions the time scale The vertical scroll bar controls the position within the set of visible waveforms Synario ABEL Designer User Manual Waveform Viewing Moving the Query Cursor Several commands from the Jump menu move the query cursor Tick Left Move the cursor left and right by one small tick mark Tick Right They are useful for slowly scanning a waveform or for accurately positioning the cursor at an event The time represented by one small tick mark changes as the scale is changed with the View commands 10 Left Move the query cursor to the left or right by one large 10 Right tick mark equal to 10 small tick marks The time represented by a large tick mark changes as the scale is changed with the View commands Time 0 Time En
86. hat the actual test vectors are in the ABEL HDL source file The other way to specify test vectors is to create a real test vector file by selecting the New menu item in the Source menu and then choosing test vectors Note that test vector files have the ABV file extension and must have the same name as the top level module An example test vector file is shown on the following page Note that you must use the Module and End statements exactly as you do when you create an ABEL HDL source file Also note that all pin and node declarations must be included as well as any constant declarations It s important to remember to change the pin declarations in the test vector file every time you change the pin declarations in the source You may wonder if there are any advantages to placing test vectors in the ABV file instead of in the ABEL HDL source The most obvious advantage is an improvement in processing time By placing test vectors in the ABV file you will be able to change the test vectors and re simulate without having to re compile the logic This can make a significant difference in large hierarchical designs Synario ABEL Designer User Manual JEDEC Simulation Figure B 2 Example ABV File l module scan tv pin cik Go 944037 EE 1 40 rst reg invert pin istype com invert pin istype up down vectors test ZE EK eE Oe tee e TK ETE ETE coe C EE EZ ETE TK cos ETE coe Ek E EZ Ry eye
87. he Waveform Viewer window Figure 1 Waveform Viewer Window Wavetorm Viewer Silos RANDNUM File Edit View Object Options Jump Help Y 400 0 ns CLAS tO t 06 iOS TEL t 03 toz to 00 D7 1 D6 D5 COMP 4 103 02 101 t 00 Time 200 0 ns Delta 200 0 ns Level Low Driving 0 a Title Bar The title bar across the top shows the name of the current design This name is the base name of the design being examined Waveform This area contains the names of any waveforms displayed You can Name Area resize this area by placing the mouse cursor over the vertical line between the name and display area and dragging the line where you want it Waveform The waveform display area has a time scale on the top The horizontal Display Area scroll bar pans left and right in a waveform The vertical scroll bar displays additional waveforms when there are more than can fit in the window at one time Prompt Line The prompt line is below the bottom scroll bars The prompt line displays the following information Time The time corresponding to the Query Cursor a solid vertical line in the waveform display Level The digital level of the selected waveform at the intersection with the Query Cursor The selected waveform is highlighted in the waveform name field Level takes the values supported by the simulator being used typically zero 0 one 1 or unknown X Bus values are shown with the current radi
88. he design into modules with the appropriate functions This approach is called stepwise refinement you move in order from a general description to modularized functions to the specific circuits that perform those functions Synario ABEL Designer User Manual Hierarchical Design in ABEL In a top down design the uppermost schematic usually consists of nothing but Block symbols representing modules plus any needed power clocking or support circuitry These modules are repeatedly broken down into simpler modules or the actual circuitry until the entire design is complete Bottom up Design In bottom up design you start with the simplest modules then combine them in schematics at increasingly higher levels Bottom up design is ideal for projects such as interfaces in which the top level behavior cannot be defined until the low level behavior is established Inside out Mixed Design Inside out design is a hybrid of top down and bottom up design combining the advantages of both You start wherever you want in the project building up and down as required ABEL fully supports the mixed approach to design This means that you can work bottom up on those parts of the project that must be defined in hardware first and top down on those parts with clear functional definitions How To Specify a Lower level Module in an ABEL HDL Module The following steps outline how to specify a lower le
89. he upper level module INL IN2 OUTI pin EQUATIONS OUT1 IN1 IN2 ThST_ VECTORS INI IN2 gt OUT1 0 HI EU Oy LI 1015 ly GO gt E O17 1 i e i ak END Z It is best to create the lowest level sources first and then import or create the higher level sources Synario ABEL Designer User Manual 2 5 Hierarchical Design in ABEL Hierarchical Design Considerations The following considerations apply to hierarchical design Prevent Node Collapsing Use the signal attribute keep to indicate that the combinational node Should not be collapsed removed For example the following ABEL HDL source uses the keen signal attribute MODULE subl TITLE sub module 1 apr PLI d pin e node istype keep Equations e It SOS d c bk ei END 2 6 Synario ABEL Designer User Manual 3 Overview of ABEL HDL Sources What is ABEL HDL ABEL HDL is a hierarchical logic description language ABEL HDL design descriptions are contained in an ASCII text file in the ABEL Hardware Description Language ABEL HDL For example the following ABEL HDL code describes a one bit counter block MODULE obcb TITLE One Bit Counter Block Inputs clk rst ci pia 4 Outputs Co pin istype com a pin istype reg Equations q lt clk cilk a lt Fer Zb amp cl amp lrst toggle if carry in and not reset Y gfb amp lci amp lrst hold if not carry in and not reset 0 amp
90. hese nodes must be declared and can be given any names Node 49 the complement array feedback is declared as COMP so that it can be entered into each of the equations In this design the complement array feedback is used to wrap the counter back around to zero from state nine and also to reset it to zero if an illegal counter state is encountered Any illegal state and also state 9 will result in the absence of an active product term to hold node 49 at a logic low When node 49 is low Figure 5 19 shows that product term 9 resets each of the feedback registers so the counter is set to state zero To simplify the following description of the equations in Figure 5 18 node 49 and the complement array feedback are temporarily ignored The first equation states that the FO output register is set to provide the counter output and the PO register is set when registers PO P1 P2 and P3 are all reset counter at state zero and the clear input is low Figure 5 19 shows how the fuses are blown to fulfill this equation the complemented outputs of the registers with the clear input low form product term 0 Product term O sets register PO to increment the decade counter to state 1 and sets register FO to provide an output at pin 18 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Figure 5 18 Transition Equations for a Decade Counter module DECADE title Decade Counter Uses Complement Array Michael Holley
91. higher level drawing representing the subcircuit must point to the ABEL HDL logic description How that is done depends on the architecture and schematic capture system you are using but the basic principle is similar in most cases To reference an ABEL HDL logic description label the functional blocks representing ABEL HDL subcircuits with the name of the ABEL HDL design see Figure 3 11 The Vendor Kit manuals contain more detailed information on the kinds of subcircuits ABEL HDL is good at implementing for specific architectures Synario ABEL Designer User Manual 3 23 Overview of ABEL HDL Sources Figure 3 11 Functional Block Labeled with ABEL Module Name A functional block representing an ABEL design Netlist name points to ABEL output FILE DESIGN XXX 1073 1 When you are finished entering or importing source files you are ready to process your design Refer to Chapter 4 ABEL HDL Compiling for more information The ABEL HDL Reference If you have questions about the ABEL HDL language refer to the ABEL HDL Reference manual ABEL HDL Compiling ABEL HDL modules must be compiled in order to physically implement your design Compiling includes compiling logic reduction and any other process that translates the ABEL HDL sources to information that can be used by fitter or Place And Route software Chapter 4 discusses ABEL HDL compiling in more detail ABEL HDL Design Considerations 3 24
92. ic values on the schematic change to those for that simulation time All logic values are displayed and updated not just those for waveforms in Waveform Viewer s display The logic values are displayed on the schematic in two ways e Asmall colored square is attached to any probed symbol nodes on the schematic The color of the square indicates the logic value The default value is green for high red for low The colors can be changed with the INI Editor These colored squares are useful when the schematic is displayed at a low magnification and the text is too small to be read e Inside the small colored square is the text representation of the logic value The text value is 0 1 X unknown Z high impedance or the value of a bus View Report The View Report command reads error information from a file and displays the errors interactively in a list box one error to each line Clicking left on a line moves the waveform display to the corresponding error If View Report is used with the Hierarchy Navigator the schematic is displayed and the pin driving the net with the problem is highlighted Any third party tool can be used to create the error file Refer to the Waveform Tool Command Reference or the Waveform Tools online help for more details of the View Report command Synario ABEL Designer User Manual C 9 Waveform Viewing Saving and Printing Waveforms Saving Waveforms After completing a waveform analysis you c
93. ign Re optimizing may further reduce the product terms count For example if you have the equation CuSO eS LL r e 2y and i0 is tied to 1 the resulting equation would be simplified to out 11 Hierarchy and Test Vectors PLD JEDEC Simulation If you are targeting a PLD device and want to do JEDEC simulation of your project you must specify your test vectors in the top level source If you have existing test vectors in lower level sources you can merge the inputs stimulus of blocks that are connected to the top level pins with the expected values of blocks that are connected to the top level outputs The test vectors in the lower level modules can still be used for individual JEDEC simulation 5 4 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Node Collapsing All combinational nodes are collapsible by default Nodes that are to be collapsed or nodes that are to be preserved are flagged through the use of signal attributes in the language The signal attributes are Istype keen Do not collapse this node collapse Collapse this node Collapsing provides multi level optimization for combinational logic Designs with arithmetic and comparator circuits generally generate a large number of product terms that will not fit to any programmable logic device Node collapsing allows you to describe equations in terms of multi level combinational nodes then collapse the nodes into the output until
94. in the Processes for Current Source window 3 Click the Properties button below the Processes for Current Source window The Properties dialog box appears with a menu of options as Shown in the figure on the next page This options menu is specific to the Compile Logic process for an ABEL HDL source 4 In the Properties dialog box select the Generate Listing property Click on the arrow to the right of the text box at the top of the properties menu and select the Expanded listing option 6 Click on the Close button to exit the Properties dialog box To get information on a property click on the property in the Properties Dialog box and then press Synario ABEL Designer User Manual 4 5 ABEL HDL Compiling The following figure shows the Properties dialog box for the Compile Logic Process Synario Project Navigator TUTOR2 SYN a File View Source Process Options Jools Window Help W i Processes for Current Source El Tutorial session 2 TAS Compile Logic E Virtual Device G Check Syntax B andff vectors Compiler Listing PETE 4 E Compiled Equations GS Reduce Logic Reduced Equations Properties Normal ABEL Generate Listing Module Arguments Compile Control Definitions Advanced Retain Redundant Logic fF ABEL Compatibility List Double click the selected item to cycle through possible choices or use the combo box in the edit region tora list of choices Strategies Another
95. indow on the left side of the Project Navigator display The Sources in Project window lists all of the sources that are part of the tutori project design In addition to the sources that describe the function of the design every project contains at least two special types of sources the project notebook and the device E Project Notebook The project notebook is where you enter the title and name of the project You can also use the project notebook to keep track of external files such as document files that are related to your project You ll learn how to use the project notebook in a later tutorial L Device The device is a source that includes information about the currently selected device This design has been entered without a device specified so the device shown is Virtual Device The remaining sources listed in the tutor1 project are e A top level ABEL HDL module multiply abl e A lower level ABEL HDL module adder abl e A test vector file multiply abv Project Processes The Project Navigator has two primary windows that display information about your design The Sources in Project window described above contains all of the sources in your design Some sources have a unique set of tasks processes that must be performed to complete the design for simulation or implementation When you select a source the Processes for Current Source window reflects the processing required for that source Synario ABEL De
96. ingle IC also called chip or device design and if you have various Vendor Kits you ll be able to pick various technologies with which to implement that IC The IC projects have the flexibility to change devices if the design is done with the virtual device libraries and symbols 2 In the Create New Project dialog box enter a name for the project file syn that will be used for your design The project name can be up to 8 characters long plus the syn extension Create New Project Save bt E belzo ecos 55 EE En license 3 config pld File name New syn Save as type Project File syr Cancel Help 3 Choose the directory in which you want to place your project files You can navigate through the directories and click on the Create Dir button to create additional directories When you are finished navigating to the directory for the project click on the OK button ote We do not recommend placing more than one project in the same directory You can use the Create Directory button to create a meaningful structure of directories to hold each project 4 The project appears in the Sources window of the Project Navigator Double click on the title of the project Untitled The Project Title dialog box appears 5 In the Project Title dialog box enter the name you want for your project and then click on the OK button The project title can be as long as you like but only the first 20 charac
97. input combinations For each of the design outputs f3 through fO the truth table specifies whether the resulting value should be 1 or 0 For each output then each of the eight individual truth table entries can be either a member of a set of true functions called the on set or a set of false functions called the off set Using output f3 for example the eight input conditions can be listed as on sets and off sets as follows maintaining the ordering of inputs as specified in the truth table above on set of f3 off set of f3 0O 1 1 1 0000 1 1 1 1 Oy RK Os l HS 0 HE e Er 0 1 1 1 100 LC HEH The remaining eight input conditions that do not appear in either the on set or off set are said to be members of the dc set as follows for f3 dc set of f3 0010 0100 Dr 101 Eh 110 1 00 1 1 0O 1 20 iy Se a d E O Synario ABEL Designer User Manual 5 23 Synario ABEL HDL Design Considerations Expressed as a Karnaugh map the on set off set and dc set would appear as follows with ones indicating the on set zeroes indicating the off set and dashes indicating the dc set LEO 1746 1 If the don t care entries in the Karnaugh map are used for optimization the function for f3 can be reduced to a single product term f3 i2 instead of the two f3 3 amp i2 amp i0 i2 8 11 amp iO otherwise required The ABEL HDL compiler uses this level of optimization if the DCSET directive or ISTYPE dc is included in the
98. ion conditions 000s Trigger EE geen lee EE Trigger conditions CISD IOV EE Triggers defined Deere ee eee eee SOLITO TEE signal conditions ceeeee eee TEST Sisi carnada Truth Tables ABEL HDL sico VendorkKte VHDL OVELVICW viccccececccucuavaucuunuavanes Waveform Description Language referenced ENN EEN Waveform Viewer analysis techniques 05 bus logic values 1 ccc ceeeeeeeee ees CFOSS PIODING au NNRNKNKN EN KN NN NNN described aa E ENN display Commande displaying error information displaying signals sssssesssnn displaying simulation values in Find Item Commang FUNCTIONS EE Sschematic non no nora interaction with Hierarchy Navigator jumping to events 0085 locating nete EEN logic level measurements printing the display Probe Item command Probe Item command from Hierarchy Navigator prompt Ime cece cece eeeeeeeeeeees Query Commande saving configuration selecting waveforms to view Setting triggers ua NN NNN KENNEN Show Commande simulation value display simulator required Sa CHG EE time difference measurements Ego e EE triggers defined an waveform analysis Index 8 Synario ABEL Designer User Manual window components eV E o Elo a C 3 WDL ip AA e e a C 1 X KD abt daak a aaaea aaaea A ALEEA EELEE EEEE EAA EEE EAA REEE EE EE EEEE REEERE
99. ion models associated with your design or sources in the design For IC Design projects to simulate your design you need to first associate a test file to either the top level source or recommended associate a test file to the device indicated by the device Li icon e For Verilog Simulation if you have this option you need at least one Verilog Test Fixture tf file For more information the Verilog Simulator Reference Manual e For VHDL Simulation if you have this option you need at least one VHDL Test Bench vhd file For more information refer to the Synario VHDL Simulation User Manual You can conduct Functional Simulation with a Virtual Device select Before you can conduct Post Route Timing Simulation however you need to select a specific device family and run the Place and Route or fitting processes for the design Synario ABEL Designer User Manual 4 19 ABEL HDL Compiling 4 20 Synario ABEL Designer User Manual D Synario ABEL HDL Design Considerations Overview of ABEL HDL Design Considerations This chapter discusses issues you need to consider when you create a design with ABEL HDL The topics covered are listed below e Hierarchy in ABEL HDL e Pin to Pin Architecture independent Language Features e Pin to Pin Vs Detailed Descriptions for Registered Designs e Using Active low Declarations e Polarity Control e Istypes and Attributes e Flip flop Equations e Feedback Considerations
100. ions hiercnt interface clk rst en gt q3 q2 ql q0 Submodule instances entl functional_block hiercnt cnt2 functional_block hiercnt Equations cntl cik clk cnt2 clk clk cntl rst rst cnt2 rst rst cntl en enl Each counter may be enabled independent of cnt2 en en2 the other This module may be used as a Sub module for a higher level design as these counters may be cascaded by feeding the ov outputs to the en inputs of the next stage ovl clk cik ov2 clk cik ovl e a3 a2 al la0 amp enl look ahead carry overflow ov2 b3 amp b2 amp bl b0 amp en2 indicator a3 cnt1 q3 a2 cnt1 q2 al cnt1 ql al D3 EH as b2 cnt2 q2 b1 cnt2 ql bO cnt2 q0 test vectors clk rst en1l en2 gt a3 a2 al a0 b 3 b2 b1 b0 ov1 ov2 cnt1 q0 L O a Uy E eee ep Sey E ep E X A Ry E RAS E og ky E ge Dos e AA Oe Ee Ee Og ie e Os Dl ae es Slee A Ue OG IG Sieg Da EE te Ek Els A Le Kn n Oe de gs EE lt ess bh te Oy he De Oly Oye 07 DS Oy Et Ts gt a ke 0 al es Ih igs ha e Sales EE 07 Oe TD it 00 eg Ka Ue gs e un ts Ls O al Se Og O Ole Ls EE he gee O O0 T Jhe E ge 0 ds E 0 A O Jy END 1 2 Synario ABEL Designer User Manual ABEL Design In ABEL a single IC is represented by a single project that is created and modified using the ABEL Project Navigator The project contains all the logical descriptions for the IC In addition
101. ions eliminates architectural ambiguities Specifying feedback paths also allows you to use architecture independent simulation The following rules should be kept in mind when you are using feedback No Dot Extension A feedback signal with no dot extension for example count count 1 results in pin feedback if it exists in the target device If there is no pin feedback register feedback is used with the value of the register contents complemented normalized if needed to match the value observed on the pin FB Extension A signal specified with the FB extension for example count count fb 1 results in register feedback normalized to the pin value if a register feedback path exists If no register feedback is available pin feedback is used and the fuse mapper checks that the output enable does not conflict with the pin feedback path If there is a conflict an error is generated if the output enable is not constantly enabled COM Extension A signal specified with the COM extension for example count count com 1 results in OR array pre register feedback normalized to the pin value if an OR array feedback path exists If no OR array feedback is available pin feedback is used and the fuse mapper checks that the output enable does not conflict with the pin feedback path If there is a conflict an error is generated if the output enable is not constantly enabled BIN Extension If a signal is specifie
102. ituations involving combinational logic The principle of the Truth Table is to build an exhaustive list of the input combinations referred to as the ON set for which the output s become s active The following list summarizes design considerations for Truth Tables Following the list are more detailed examples The OFF set lines in a Truth Table are necessary when more than one output is assigned in the Truth Table In this case not all Outputs are fired under the same conditions and therefore OFF set conditions do exist OFF set lines are ignored because they represent the default situation unless the output variable is declared dc In this case a third set is built the DC set and the Output inside it is assigned proper values to achieve the best logic reduction possible If output type dc or dcset is not used and multiple outputs are specified in a Truth table consider the outputs one by one and ignore the lines where the selected output is not set Don t Cares X used on the right side of a Truth Table have no optimization effect When dealing with multiple outputs of different kind avoid general settings like DCSET which will affect all your outputs Use istype SE DC on outputs for which this reduction may apply Beware of Outputs for which the ON set might be empty As a general guideline it is important not to rely on first impression or simple intuition to understand Truth tables The way they are under
103. ive you a module that can be reused Another advantage of hierarchical design is the way it lets you organize your design into useful levels of abstraction and detail Approaches to Hierarchical Design Creating a Hierarchical designs will consist of ONE top level The lower level modules can be of any supported source ABEL HDL sources and are represented in the top level module by a place holder You could create the top level module first or create it after creating the lower level modules new Hierarchical Design Hierarchical entry is a convenient way to enter a large design one piece at a time It is also a way of organizing and structuring your design and the design process The choice of the appropriate methodology can speed the design process and reduce the chance of design or implementation errors There are three basic approaches to creating a multi module hierarchical design e Top down e Bottom up e Inside out mixed Regardless of the approach you choose you start from those parts of the design that are clearly defined and move up or down to those parts of the design that need additional definition The following three sections explain the philosophy and techniques of each approach Top down Design In top down design you do not have to know all the details of your project when you start You can begin at the top with a general description of the circuit s functionality then break t
104. l polar esos darias 5 12 EXIN a E o E O 5 10 collapse CONaPpsINO DOES iii 5 5 SEI CCUVE COIODSING cms ropero rta 5 5 C EE EIERE EE Combinational NOES sans sos COMPlement Sra VS cnirnaeo ses EECHELEN Ee D D flip flop Unsatistiea Transition Beie ue le EE CEN Dangling nodes 5 3 iaa 5 24 dc dc and polarity control polarity NEE 5 16 D Ree ESE and edu Elte OP 5 24 decade BE 5 41 Declarations CUVE TEE 5 14 BEA Pon AFP o E EER A 1 7 Design Strategies Index 2 Synario ABEL Designer User Manual Bloc else golds goon en e ee ee ee and dot extensions COE EE example dot evtenslons nana nona nana nona nana nana nana nanananananas 5 22 15 21 example LAVO pad Sample NON AV intacta rata WINS TO US peas Detail descriptions and macrocells macro ae 1 e PEPPE PP o e O ee ee er we EA reis DOV te eene CS tardaron Devices device Hen KEE Proc rai ana PO EE Don t Care X On let side OF Truth Tala 5 45 on right side of Truth Jee Dot extensions and architecture independence archi and detail Oescriptionslgdetaill ENN ENN ENNEN EEN and feedback feedback EE example EIERE NS Editing EE SOUR CSS Eeer Emulation Ee gg ue OOS EE FU aOR POLI EE me Orchdtelam nA O eee et EE E E TEE E E a e E Equations for Elip Hopeftmge aaka a naana nana EEEE E EEEE REEERE EEEE 5 17 EE 5 26 Feedback and dot extensionsS COC aa 5 18 SKS Une EE 5 4 Flip flops le Wellen Te CR e EE EE detail CESCrIPtiONS
105. list box to associate an existing strategy with the selected source 4 8 Synario ABEL Designer User Manual ABEL HDL Compiling Simulating the PLD Design The following section briefly discusses Equation Simulation and Waveform Viewing For further information about simulation For Equation Simulation refer to Appendix A For JEDEC Simulation refer to Appendix B For Verilog Simulation refer to the Verilog Simulator Reference Manual For VHDL Simulation refer to the Synario VHDL Simulation User Manual To simulate this design la Highlight the test vector file andff abv in the Sources in Project window Double click on the Simulate Equations process in the Process window The Project Navigator builds all of the files needed to simulate the circuit and then runs the Equation Simulator To display the simulation results 1 Double click on the Equation Simulation Report process to display the simulation report file for tutor2 The simulation report file is shown below Simulate ABEL 6 00 Date Tue Jun 28 14 36 01 1994 Fuse file tutor2 bl2 Vector file andff tmv Part Pla AND gate and a El1p Elop VOOOL v0002 VO0O003 VO0O004 EE d Oa AR ER cA O E No E JG O Ge Se ee R N Q Ek EUR AO Ce EE E a E AO SO OD BE O LS LEE E AO O O Eo ek EE E E EH a e E 4 out of 4 vectors passed Synario ABEL Designer User Manual 4 9 ABEL HDL Compiling 2 In the Project Navigator Pr
106. ls when you first start the program All Synario examples are shipped with pre saved WAV files for your convenience Synario ABEL Designer User Manual ABEL HDL Compiling To zoom in the Waveform Viewer 1 Select Zoom in from the View menu 2 Place the zoom cursor at the beginning of the waveform hold down the left mouse button and select a zoom region of about 150 ns The Waveform Viewer zooms in on the selected waveform so you can see the circuit stimulus more clearly as shown in the following figure 3 Press the right mouse button to exit zoom mode when you have zoomed in the desired amount The waveform has the three inputs input_1 input_2 and Clk and the output output_q Waveform Viewer Timewave pla File Edit View Object Options Jump Help Waveform Viewer Timewave pla File Edit View Object Options Jump Help Zoom In Pick Center Point or Corner of foom Window Synario ABEL Designer User Manual 4 11 ABEL HDL Compiling ABEL HDL for CPLDs This section continues the same tutorial started in Chapter 3 in the section titled Creating a Hierarchical ABEL HDL Design for a CPLD You can either continue the tutorial or just read the text below to get a general idea of how to compile ABEL HDL for a Complex PLD This tutorial describes how to e Implement a hierarchical design in a complex PLD e Use test vectors to perform PLD device simulation ote This tutorial requires that you have a De
107. model of the design This method include macrocells sum terms and product terms Select the Report Type Macro cell property to display the model tmv Vectors The Equation simulator uses the tmv file vectors The vectors in the tmv file can have different values for input and output For example the tmv file allows you to apply a O to a bidirectional pin that is an input before the clock and test for an H after the clock A 2 Synario ABEL Designer User Manual Equation Simulation How to Use the Equation Simulator Test Vector Files To use the Equation simulator you will have to create test stimulus with ABEL HDL test vectors See the ABEL HDL Reference for more information about test vector syntax There are two ways to specify test vectors The most common method is to place test vectors in the ABEL HDL source file If you use this method the Project Navigator will detect the presence of test vectors in the source file and create a dummy test vector file This file indicates to the system that the actual test vectors are in the ABEL HDL source file The other way to specify test vectors is to create a real test vector file by selecting the New menu item in the Source menu and then choosing test vectors Note that test vector files have the ABV file extension and must have the same name as the top level module An example test vector file is shown on the following page Note that you must use the Module and En
108. mplifies the ABEL HDL source file Figure 3 4 shows a schematic of combinational logic Signals A B C D and E are inputs X and Y are outputs There are no intermediate Signals every declared signal is an input or an output to the subcircuit Figure 3 3 shows the ABEL HDL declarations and equations that would generate the logic shown in Figure 3 4 Figure 3 3 Declarations and Equations declarations Pop Dep Co y E E X Y pan equations X ASB8C BSC Y A amp D A amp E A amp BEC Figure 3 4 Schematic without Intermediate Signal FUNCTIONAL BLOCK COD 1 COD e AECH Synario ABEL Designer User Manual 3 17 Overview of ABEL HDL Sources Figure 3 6 shows the same logic using an intermediate signal M which is declared as a node and named but is used only inside the subcircuit as a component of other more complex signals Figure 3 5 shows the declarations and equations that would generate the logic shown in Figure 3 6 Figure 3 5 Declarations and Equations declarations Ay By Ca Dz Epa Xy Y GLN M node equations intermediate signal equations M A amp B amp C X M BSC Y A amp D A amp E M Figure 3 6 Schematic with Intermediate Signal M FUNCTIONAL BLOCK E C A A E C A E Y A E ra Both design descriptions are functionally the same Without the intermediate signal compilation generates the AND gate associated with A amp B amp C twice and the device fit
109. nage a large design containing many files the Project Navigator collects all of the files into a project When you open an existing design or create a new one you are opening or creating a project The tutorial in this example is tutorial number 1 1 To open the existing project for tutorial number 1 you must first start the Project Navigator For Windows 95 and Windows NT 4 0 start Synario or ABEL from the Start menus Refer to Chapter 1 of this manual for more information e When the Project Navigator initializes it loads the last used design If you have previously worked on a project the Project Navigator loads that project at startup e If you have not opened a project already or if you have disabled the Open Previous Project option you will see a blank project like the one shown in the following figure 3 2 Synario ABEL Designer User Manual Overview of ABEL HDL Sources 3ynario Project Navigator File Options Window Help strategy sources in Project No Project Open Processes for Current Source No Processes Available select New Project or Open Open a projectto make processes available Project in the File menu to opene project 2 To open tutorial number 1 select Open Example from the File menu Use the mouse to navigate through the example directories until you are in the synario4 examples tutorial tutor1 directory as shown in the following figure te Open Example Projec
110. nd the documentation for your simulator See Also For IC Design projects refer to the Vendor Kit manual for specific design information about a device family Tips for Creating a Top level Source Use the following guidelines when creating a top level source e It is best to create the lowest level sources first and then import or create the higher level sources Building a Top level ABEL HDL Module e Ina top level behavioral module in ABEL HDL you use the Interface and Functional block keywords to instantiate lower level files You can also use the Interface keyword in lower level files to link to upper level ABEL HDL modules not upper level schematics The ABEL HDL file pwmdac abl demonstrates the use of the Functional_block and Interface keywords in a top level file The file counter abl demonstrates the use of the Interface keyword in a lower level file 1 18 Synario ABEL Designer User Manual ABEL Design Import an Existing Source You can import a source into your project by doing the following 1 From the Source menu click on Import The Import File dialog box appears Find the source file you wish to import You can change the type of file that is displayed in the List files of type list box When you are done selecting the source click on OK Depending on the source type you are importing you may be asked to provide additional information in the Source Type dialog box Depending on the sou
111. nnnes 5 2 gang ul WEE Mixed design cccccccsscessccssessscssscsscsstecsusceaccsseecsuecuseusteceueceueenans PIC 2 4 PIC 2 4 MIDS CO pa AAPP o EE EE umm 3 2 neg neg and polarity control polarity ooocccccccccccccccnnncncnannnnnnnn nn 5 16 Node COLAPSO irreal COMINO A COMPETEN Silay Scars nit e DT Ksl E EMOVINO Beet ie En EE selective e Ee ne usted atar Notebook GINO ee DING eh en nt EE Siet e Te E EE me e Ee leia Ke A A e O EOI Optimization a a O DCSFTA o tasar en ne ne a prelados PA PPP e e o o o ee FOS OK oa reducing Product dan TEE Synario ABEL Designer User Manual Index 5 Index Other sources CGIUNG TTT 1 20 Alf gei Deg Ze EE D SL HE 5 19 Pin to pin descriptions and TUL Kgl elek de 8 GE gt e USO E A resolving amDigUITIES stare ee ane re ee ore PAGO PUSS Cl ege EE POLE eine el AA EE Ports declaring TOW GEFHIEV EE Post linked Optimization sois ia POWO PA A a EE EE EEE E E E Preset POLI EAN EE Product terms ceeds WEG Programmable 1C DESIGNIO voir aia Programmable polarity active levels for devices 00ccccccccnnncncccnccnnnnnnnnn raras Project Navigator ESCAP EE PROJeEL NODO Kiara ProJOCT SOURCES unreal bd dto tico tios Biet Wa lee Projects Maia P o Oil UE o e PO POP II Eeee Talgo o Lolo erer A A E A AB se e WEE SAVIN e RE a EE geleiert Redundant nodese ccc cee cee ceeeeeeeeeeeeeeeueeeueeueeeneeeeeaueeueeaueeeeeaneeueeaueeueea
112. ns are repeated This iterative process continues until no changes are detected or until 20 iterations have taken place If 20 iterations take place and there are still changes the design is determined to be unstable and an error is reported More detailed information on simulating devices with feedback and other advanced uses of the Simulation program are presented in the Equation and JEDEC Simulators Manual The Simulator Model The JEDEC simulator uses the JEDEC and device files to build a model of the design These methods include macrocells sum terms and product terms Select the Report Type Macro cell property to display the model B 2 Synario ABEL Designer User Manual JEDEC Simulation JEDEC and tmv Vectors The JEDEC simulator uses the JEDEC vectors but can optionally use the tmv vectors instead JEDEC vectors include only test conditions for pins the tmv file vectors allow testing of internal nodes Also the vectors in the tmv file can have different values for input and output For example the tmv file allows you to apply a O to a bidirectional pin that is an input before the clock and test for an H after the clock A JEDEC vector could only have the H In the JEDEC simulator select the Use tmv File test vectors property to use the tmv file for simulation in place of the JEDEC vectors JEDEC Vector Conversion Internally the JEDEC simulator uses the same test_vector format as the tmv file vectors The simulator
113. o correct the problem you must remove the DCSET directive so the implied dc set equations are folded into the off set for the resulting logic function Another option is to rewrite the module as shown below Figure 5 16 DCSET compatible State Machine Description module TRAFFIC1 title Traffic Signal Controller M McClure Data I O Corpo traffici device F167 Clk SenA SenB pin dun Sr Ts PR pin 16 Preset control GA YA RA pin 15 13 GB YB RB prn Iiag SOU node 31 34 istype reg_sr buffer Hye as Che Te E aes Count S3 S0 Define Set and Reset inputs to traffic light flip flops GreenA GA S GA R YellowA YA S YA R RedA RA S RA R GreenB GB S GB R YellowB YB S YB R RedB RB S RB R On Sri ba E a Ot Se E y aie ale test_vectors edited equations GB YB RB AP PR GA YA RA AP PR GB YB RB CLK Clk GA YA RA CLK Clk LS S 0 AP PR 0 CLK Clk QDCSET state_diagram Count State 0 if SenA amp SenB then 0 if SenA amp SenB then 4 if SenA SenB then 1 State 1 goto 2 State 2 goto 3 State 3 goto 4 State 4 GreenA Off YellowA On goto D State Ac YellowA Off RedA On RedB Off Synario ABEL Designer User Manual elo to Synario ABEL HDL Design Considerations end 5 36 State State State State State State State State State State 6 T 8 9
114. ocesses window double click on Equation Simulation Waveform to enter the Waveform Viewer and display the simulation waveforms The Waveform Viewer initially displays no signals so you must add the signals you wish to observe by selecting signals from the Waveform Viewer menus Select signals using Show from the Edit menu in the following manner a Select Show from the Waveform Viewer Edit menu b Select one or more signals to display in the waveform For our example select signals input_1 input_2 Clk and output_q You can select all four signals at once by holding the left mouse button down and dragging over the four names c Click on Add Wave to add the selected signals to the waveform display When you add the signals the Waveform Viewer displays a waveform like the one shown in the following figure File 3ynario Project Navigator TUTOR2 SYN cal File View Source Process Options Jools Window Help PET ee KH UL Strategy Bo fae sources in Project Processes for Current Source lt 3 Compile Test Vectors Compiler Listing lo 3 Simulate Equations e E Equation Simulation Report Mz Equation Simulation Yfaveform E Tutorial session 2 E Virtual Device ME andff vectors El andff andff abl Waveform Viewer Timewave pla Edit View Object Options Jump Help Note If there is a saved waveform file WAV the Waveform Viewer displays the saved signa
115. ohn When amp Sors 1973 coe 5 28 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations State Machines A state machine is a digital device that traverses a predetermined sequence of states State machines are typically used for sequential control logic In each state the circuit stores its past history and uses that history to determine what to do next This section provides some guidelines to help you make state diagrams easy to read and maintain and to help you avoid problems State machines often have many different states and complex state transitions that contribute to the most common problem which is too many product terms being created for the chosen device The topics discussed in the following subsections help you avoid this problem by reducing the number of required product terms e The following subsections provide state machine considerations e Use Identifiers Rather Than Numbers for States e Powerup Register States e Unsatisfied Transition Conditions D Type Flip Flops e Unsatisfied Transition Conditions Other Flip Flops e Number Adjacent States for a One bit Change e Use State Register Outputs to Identify States e Use Symbolic State Descriptions Use Identifiers Rather Than Numbers for States A state machine has different states that describe the outputs and transitions of the machine at any given point Typically each state is given a name and the state machine is described in terms o
116. oject el Mutiplier aus eae z ote you do not see d Virtual Device the filenames in multiply abw parentheses and would multioly multioly abl like to see them make 5 Py l Py sure that Filenames is F mcontrol mcontrol abl ec ite aw gi mshift mshift abl menu ei ripple ripple abl 1 16 Synario ABEL Designer User Manual ABEL Design Note You can change to a flat hierarchy view that shows only the top file by removing the check on View Hierarchy For additional information about building a hierarchical design refer to chapter 2 in this manual 2 Tips for Defining the Logic in the Project Use the following guidelines when saving and naming source files and projects e Itis best to create the lowest level sources first and then import or create the higher level sources In other words don t use topdown design Avoid using ABEL HDL keywords for module and signal names in any of your source files Do not use any Vendor Kit specific macro functions to name a source Avoid saving a project that has the same base file name as one of its sources If a source and project have the same base name you may have problems with the Project Navigator s automake feature For instance avoid calling your project myfile syn if it contains a source named myfile abl Each source must have a unique name in the project Do not have two different sources with the same name You can use the same s
117. on describing the example by double clicking on the documentation source located below the project title in the Project Navigator Sources Window Documentation is usually in Microsoft Write wri or online help hlp format Refer to the documentation for your Vendor Kit for information on available examples specific to a device family For a list of examples refer to the Synario website www synario com and search for the keyword examples Changing the Environment and Configuration You can set many environment variables and change settings for the Project Navigator and programs started from within the Project Navigator You can even add menus to access other Windows programs Changes to the environment may be made e By choosing Options Environment from the Project Navigator menus e Editing INI files used by the Project Navigator and other programs e By choosing other items in the Options menu to start the INI Editor The INI Editor program is used to modify the INI files used in the schematic tools such as the Schematic Editor Hierarchy Navigator and Symbol Editor Refer to the Project Navigator online help for information The help for these topics can be accessed from the Project Navigator Help by searching for the Environment and INI Editor keywords 1 24 Synario ABEL Designer User Manual 2 Hierarchical Design in ABEL Figure 2 1 Example of a Hierarchical Project in the Project Navigator sources in
118. on tests the JEDEC file that can be used to physically implement your design into a device Like Equation Simulation your design must have test stimulus ABEL HDL test vectors Simulation Flow Figure B 1 shows a flow diagram of simulation during evaluation of the inputs to the output This flow is the same for both Equation and JEDEC simulation The simulator applies the first test vector and performs any setup of internal registers that results from the vector applied to the inputs The simulator then calculates the product terms that result from the test vector the OR outputs that result from the product terms any macrocell outputs that result from the OR outputs and any feedback functions The results of the simulator calculations are written to the sim file Synario ABEL Designer User Manual B 1 JEDEC Simulation Figure B 1 Simulation Flow Diagram ae Set up internal registers Calculate product terms Calculate OR outputs Calculate macro cells Calculate feedback functions Trace detail or clock output 20 iterations yet Report error Trace brief level 0 output 0698 1 The outputs of designs with feedback may require several successive evaluations until the outputs stabilize After the feedback paths have been calculated the simulator checks to see if any changes have occurred in the design since the product terms were last calculated If changes have occurred due to feedback functions the calculatio
119. op level equations as shown in the source fragment below DECLARATIONS lowl FUNCTIONAL BLOCK lower zed0 zed7 pin upper level inputs atop pin istype reg buffer upper level output d3 d0 pin istype reg buffer upper level ouputs EQUATIONS atop lowl a wire this source s outputs d3 d0 owl basan 5 to lower level inputs lowl z0 z7 zed0 zed7 wire this source s inputs to lower level outputs See Functional block in the ABEL HDL Reference Manual for more information Synario ABEL Designer User Manual 5 3 Synario ABEL HDL Design Considerations Hierarchy and Retargeting and Fitting Redundant Nodes When you link multiple sources some unreferenced nodes may be generated These nodes usually originate from lower level outputs that are not being used in the top level source For example when you use a 4 bit counter as a 3 bit counter The most significant bit of the counter is unused and can be removed from the design to save device resources This step also removes trivial connections In the following example if outi is a pin and t1 is a node outi t1 tl a86 would be mapped to outi a86 t Merging Feedbacks Linking multiple modules can produce signals with one or more feedback types such as FB and Q You can tell the optimizer to combine these feedbacks to help the fitting process Post linked Optimization If your design has a constant tied to an input you can re optimize the des
120. or Modify the Logic in Your Project You define the logic in a design with the project sources These sources can be created from scratch using an available editor or you can import an existing source You have the following choices to define the logic of your project 1 Create new sources 2 Import existing sources 3 Remove sources 4 Modify sources Defining the logic of your design is probably one of the most difficult tasks because it can involve many steps design rules and design dependencies hierarchy The least complex design is a flat design in which there is only one source describing the design such as a single ABEL HDL file Witha flat design you can add a test file such as a ABEL HDL test vectors All processes such as JEDEC simulation in the flat design involve the entire design The complexity of the design increases as you add dependencies hierarchy A hierarchical or top down design consists of a top level source that contains interface statements that link to lower level modules to create the overall design The referencing of a lower level source is called instantiation ote A source can be referenced instantiated more than once Also a source can be both a lower level and top level source For example compare in the following figure could instantiate another file The following figure shows what a hierarchical design looks like in the Sources window Sources in Pr
121. ource many times in a design by instantiating the source but two different sources with the same name can cause problems with hierarchy For example do not have an top level source called Compare and a lower level source also called Compare Create a New Source You can create a new source and add it to your project by doing the following 1 From the Source menu click on New The New Source dialog box appears 2 In the New Source dialog box click on the type of source you would like to create and then click on the OK button The Project Navigator starts an editor that you can use to enter the information for your new source For HDL sources a text editor is started ute Do not name source files the same name as other source files in the same project Synario ABEL Designer User Manual 1 17 ABEL Design 3 In the editor create a source The following table lists the available source types and where to look for more information To Edit Look Here Behavioral Modules ABEL HDL entry section in the Synario ABEL HDL Programmable IC Designer User Manual and the ABEL HDL Reference Note that ABEL HDL sources are not supported in Board Design or System Simulation projects User Document The documentation for the editor you will be using By default the editor is either a text editor or Microsoft Write which edits wri files Waveform Stimulus Waveform Viewing section later in this manual used in simulation a
122. owerful feature in ABEL HDL where a logic function is converted for both non inverting and inverting devices A single logic function may be expressed with many different equations For example all three equations below for F1 are equivalent 1 Fl A B 2 AEL CAL Bo 3 1F1 lA IB In the example above equation 3 uses two product terms while equation 1 requires only one This logic function will use fewer product terms in a non inverting device such as the P10H8 than in an inverting device such as the P10L8 The logic function performed from input pins to output pins will be the same for both polarities Not all logic functions are best optimized to positive polarity For example the inverted form of F2 equation 3 uses fewer product terms than equation 2 1 F2 A B amp C D 2 E2 A C A D B Cy Ba Di 3 TED LA reo B EE amp D Programmable polarity devices are popular because they can provide a mix of non inverting and inverting outputs to achieve the best fit Polarity Control with Istype In ABEL HDL you control the polarity of the design equations and target device in the case of programmable polarity devices in two ways e Using Istype neg Dos and dc e Using Istype invert and buffer Using Istype neg Dos and dc to Control Equation and Device Polarity 5 16 The neg pos and OC attributes specify types of optimization for the
123. pa is Qout pin 19 istype reg_D equations Qout D Qout Q amp Toggle Qout CLK Clk Qout OE lEna test_vectors Clk Ena Toggle gt Qout Er Ers H dees 0 LaS Oi ge 2 gt de ange It oy 1 gt OF asas JO tae 1 T gt d Er Bis al i ee O beee Lg al PAS Lees O Or a Al gt des PI 2 a diua 0 0 al ee 0 end This version of the design will result in exactly the same fuse pattern as indicated in the figure at the top of page 5 29 Figure 5 5 Dot Extensions and Architecture independence Circuit 2 As written this design assumes the existence of an inverted output for the signal Qout This is why the Qout D and Qout Q signals are reversed from the architecture independent version of the design presented earlier Note The inversion operator applied to Qout D does not correspond directly to the inversion found on each output of a P16R8 The equation for Qout D actually refers to the D input of one of the P16R8 s flip flops the output inversion found in a P16R8 is located after the register and is assumed rather than specified Synario ABEL Designer User Manual 5 21 Synario ABEL HDL Design Considerations To implement this design in a device that does not feature inverted outputs the design description must be modified The following example shows how to write this detailed design for the E0320 device Figure 5 8 Detail One bit Synchronous Circuit with non inverted Qout 5 22 module detail2
124. pe reg Clock Preset DLN equations Olwelk Clock Q1 01 fb Preset test vectors Clock Preset gt Q01 bk Een oy t A ee E y 0 gt Ze eee gt QOS Ps LE lt 2 0 As 0 bk eee i T dn wesen NAS y 1 Jj gt 1 end Detailed Module Description module Q01 2 ol pin istype reg_D buffer Clock Preset Pan equations Q1 CLK Clock OLD 01 0 Preset test vectors Clock Preset gt Q01 E e 2 des E ce E Ei De 1 05 le y Ep J gt Te A ig a T gt ds E En d E E ae dr Ch Als end The first description can be targeted into virtually any device if register synthesis and device fitting features are available while the second description can be targeted only to devices featuring D type flip flops and non inverting outputs To implement the second detailed module in a device with inverting outputs the source file would need to be modified as shown in the following section 5 10 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Detailed Module with Inverted Outputs module Q01 3 Ql pin istype reg_D invert Clock Preset bain equations Q1 CLK Clock 101 D Q1 0 Preset test vectors Clock Pres t gt Qi DA DL 1 E wer a ch gt 03 LE 5 E AS E wee gt 0 gt 0 E 5 A ay ee Zen E oe L HA Tas end In this version of the module the existence of an inverter between the output of the D type flip flop and the output pin specified
125. project is a design Each project has its own directory in which all source files intermediate data files and resulting files are stored The picture shown below shows an example of what the Project Navigator might look like with a programmable IC project called multi syn opened The Sources in Project Window Sources The Processes for Current Source window shows all the design files Window Processes window shows associated with a project the available processes for the selected source Wf ABEL Project Navigator MULTLSYN OL x File View Source Process Options Tools Window Help DIS weg Bee Sources in Project Processes for Current Source three bit multiplier Link Design Linked Equations multiply vectors S Fit Design F multiply multiply abl Pre Fit Equations EE ei adder aslder abl Post Fit Equations Icon EB Fitter Report Signal Cross Reference G Create Fuse Map Double click the item in the list or selectthe Start button to startthe process Selectthe Properties Double click to choose a different device button to startthe property editor New Open Start View Properties Log Ready This picture shows the Project Navigator after a programmable IC project is opened If no project is open the Sources and Processes windows would be empty Synario ABEL Designer User Manual 1 9 ABEL Design The Sources Window The Sources window on the left side of the Project
126. put is forced high and low when the Toggle is low The circuit also contains a three state output enable that is controlled by the active low Enable input Figure 5 3 Dot Extensions and Architecture independence Circuit 1 Qout 0770 1 The following simple ABEL HDL design describes this simple one bit synchronous circuit The design description uses architecture independent dot extensions to describe the circuit in terms of its behavior as observed on the output pin of the target device Since this design is architecture independent it will operate the same disregarding initial powerup state irrespective of the device type Figure 5 4 Pin to pin One bit Synchronous Circuit module pin2pin Clk Pan Le Toggle Dan Ze Ena pam as Qout pin 19 istype reg equations Oout Qout FB amp Toggle OGUE CEK CTIE Qout OE lEna test_vectors C1k Ena Toggle gt Qout tap Oe a O gt O e ae ae ae ae ae C E Es Er oO A O QA A A A QAQA O e OF OO CH O V ON FN O A CH H D e se ae PPP PrP PrP PP PE end Synario ABEL Designer User Manual 5 19 Synario ABEL HDL Design Considerations If you implement this circuit in a simple P16R8 PAL device either by adding a device declaration statement or by specifying the P16R8 in the Fuseasm process the result will be a circuit like the one illustrated in the following figure Since the P16R8
127. r integrates many tools for design entry For example for ABEL HDL source files the Project Navigator connects to the ABEL Text Editor or an Editor of your choice Synario ABEL Designer User Manual 1 7 ABEL Design Why Use the Project Navigator There are many different tools for the many different tasks involved in making and testing your design The Project Navigator is a way of integrating the different tools The Project Navigator also keeps track of both the parts of your design and the states that each part is in so you can spend less time thinking about which steps and processes need to be run and more time developing your designs The Project Navigator also keeps track of preferences for you automatically setting the options that work for most systems until you want to tweak the options for yourself How to Start the Project Navigator After installing your ABEL products do the following to start the Project Navigator Refer to the Release Notes included with ABEL for instructions on how to install ABEL products For Windows 95 98 and Windows NT Installations 1 Click on the Start button and then select the following from the Start menus a Programs b ABEL X X where X X is the current version of ABEL c ABEL After the program loads the Project Navigator window appears 1 8 Synario ABEL Designer User Manual ABEL Design How the ABEL Project Navigator Works ABEL employs the concept of a project A
128. rammable IC Designing sssssssssrensnrsrnnnsrenrsrenns Simulating be e In CN Overview Of IC Design ee rra rr rr Sven e EE Boi gei le E Design Simulation and Testimg cece eeeeeeeeeeeeeeeeeeenees Device Independence E EEN EE EEN Vendor e De SIG Ui Te o eo E How to Use the Project Navigator What is the Project Navigator Why Use the Project Navigator ccccccceeeeeee ence eee eeeeeeeeeaaaaees How to Start the Project Navigator How the ABEL Project Navigator Works cccceecceeeeeeeeeeeeeeennees Create a New Project in the Project Navigator Open an Existing Project xa Ke KENNEN KENE KENNEN KENNEN rr ee nt e EE Tips for Saving and Naming Proiecte Change the Title of the broiect narran Define or Modify the Logic in Your broiect Tips for Defining the Logic in the broiect ees Tips for Creating a Top level Gource cece cece cece ee ee eens Import an EXIStind SOU CO EE REMOVE ge EE Modify OMS EE Synario ABEL Designer User Manual II Table of Contents Example IC Designs and Multi project Simulations Changing the Environment and Configuration cccccceeeeseeeeeees 2 Hierarchical Design in PU E 3 Overview of ABEL HDL Gources ENKEN EN ENNEN ENNEN ENNEN ENNEN ENNEN NV What Is a Hierarchical Design Why Use Hierarchical Design REENEN REENEN Approaches to Hierarchical Deeign rra Creating a new Hierarchical Design How To Specify a Lower level Module in an ABEL HDL Mo
129. ransition The preferred bit values produce fewer product terms Simple Preferred State Bit Values Bit Values A 00 00 B 01 01 C 10 11 D 11 10 If one of your state register bits uses too many product terms try reorganizing the bit values so that state register bit changes in value as few times as possible as the state machine moves from state to state Obviously the choice of optimum bit values for specific states can require some tradeoffs you may have to optimize for one bit and in the process increase the value changes for another The object should be to eliminate as many product terms as necessary to fit the design into the device Synario ABEL Designer User Manual 5 37 Synario ABEL HDL Design Considerations Use State Register Outputs to Identify States State Register Bit Values 5 38 Sometimes it is necessary to identify specific states of a state machine and signal an output that the machine is in one of these states Fewer equations and outputs are needed if you organize the state register bit values so one bit in the state register determines if the machine is ina state of interest Take for example the following sequence of states in which identification of the Cn states is required State Name A B C1 C2 C3 D Q3 0 1 0 Q2 0 0 0 1 1 1 Q1 0 0 0 This choice of state register bit values allows you to use Q3 as a flag to indicate when the machine is in any of the Cn states
130. rce you are importing you may be asked to associate the source with another source in the Associate dialog box For example if you import ABEL HDL test vectors abv file you are asked which source to associate the file to If you choose a behavior description such as an ABEL HDL file the test vector file will only apply to that source If you choose the device source the test vector file will apply to testing the entire design It is best to import the lower level sources before importing upper level sources You will get an error message if you import a source that has links to lower level sources and the lower level sources are not already part of your project Import test files that are to be associated with other sources after importing or creating the other source Where the source file is place in the Project Navigator The new source is entered into the Sources window Where the source appears in the window depends on the following If the imported source is documentation or of a file type not recognized as a logic desero or test file the source appears between the Project Icon LE and targeted design icon Eu If the source is a logic description the source is placed in alphabetical order for each level of hierarchy following the project notebook and the targeted device kit For example if the source is called multiplx and the top level source a schematic called myboard instantiates multiplx the source
131. roject When you begin a new project there won t be any sources except for the project notebook For most of the tools to work there needs to be only one top level source which must be the root source for all the other sources in the project This structure can usually be done with a single top level schematic that represents the entire system and that schematic then calls out all the parts Table 1 1 Types of Sources in the Project Navigator Source Type Icon File Extension Project notebook if at top of the syn Sources Window see linked project below Document File such as a wri doc hip or specification any extension not recognized by Project Navigator Targeted Device Family appears in 3 fdk all IC Design projects ABEL HDL logic description ei abl ABEL HDL test vectors abv or abl State Diagram optional dia Waveform stimulus wdl Undefined or incorrect source reference ABEL HDL source that failed ei abl Update Hierarchy process Synario ABEL Designer User Manual 1 11 ABEL Design The Processes Window The Processes window on the right side of the Project Navigator Shows all the processing tasks that apply to whatever object or file is highlighted in the Sources window on the left side A processing task includes netlisting compiling logic reduction logic synthesis place and routing simulation model building in other words any step along the way from design entry to implemented
132. rst go to 0 if reset do gib 21 carry out is carry in and q 1 END For detailed information about the ABEL HDL language refer to the ABEL HDL Reference Manual and the online help included with Synario or ABEL products An online version of the ABEL HDL Reference Manual is provided on your Synario CD accessible by selecting Manuals from online help Note This manual is intended to help you with design issues and does not discuss detailed language syntax For syntax refer to the ABEL HDL Reference Manual Mixed Design Entry ABEL HDL can be used to describe pieces of your design You can create an entire design consisting of ABEL HDL modules However you may find it easier to mix design entry methods For instance you can create a top level schematic with functional blocks Each functional block could be described by ABEL HDL modules Synario ABEL Designer User Manual 3 1 Overview of ABEL HDL Sources A First Look at a Design using ABEL HDL Sources This first look will help you become familiar with the Project Navigator and an ABEL HDL hierarchical design using a relatively large example that has already been entered The example is a hierarchical 3 bit multiplier Opening an Existing Design Designs that you enter using the Project Navigator can contain a number of ABEL HDL modules that describe and verify the design and any other files related to the design such as design specifications To help you ma
133. s for States module Sequence title State machine example D B Pellerin Data I O Corp sequence device plora gd a0 pin 14 15 istype reg clock enab start hold reset pin Te A IS a halt pin 17 istype reg in_B in_C pin 12 13 istype com sreg q1 q0 State Values A 0 B 1 C 2 equations q1 q0 halt clk clock q1 90 halt oe enab state_diagram sreg State A Hold in state A until start is active in_B 0 in_C 0 IF start amp reset THEN B WITH halt 0 ELSE A WITH halt halt fb State B Advance to state C unless reset is active in_B 1 or hold is active Turn on halt indicator in_C 0 if reset IF reset THEN A WITH halt 1 ELSE IF hold THEN B WITH halt 0 ELSE C WITH halt 0 State C Go back to A unless hold is active in_B 0 Reset overrides hold in_C 1 IF hold reset THEN C WITH halt 0 ELSE A WITH halt 0 test_vectors clock enab start reset hold gt sreg halt in_B in_C p 0 0 0 14 0 A 14 0 0 0 IK A O y a ae gl Bra 9O p Gey EA C 0 0 1 e a 0 0 O O gt is See FO tee Oe E Tess M 0 0 O EK r vie e Mer pe ea eee A e e Ae ig 5 30 Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations o Ge Be OP og AT op A A B we el aa pe 0 O 1 0 eel A 1 0 0j kene de Et e O ae Or a KR set be ab eier EE u Ae e es q
134. scouraged Instead you should use the J and K extensions for JK type flip flops or the S and R extensions for SR type flip flops and use a detailed description method including invert or buffer attributes to describe designs for these register types There is no provision in the language for directly writing pin to pin equations for registers other than D type State diagrams however may be used to describe pin to pin behavior for any register type Synario ABEL Designer User Manual 5 13 Synario ABEL HDL Design Considerations Using Active low Declarations In ABEL HDL you can write pin to pin design descriptions using implied active low signals Active low signals are declared with a operator as shown below 101 pin istype reg If a signal is declared active low it is automatically complemented when you use it in the subsequent design description This complementing is performed for any use of the signal itself including as an input as an output and in test vectors Complementing is also performed if you use the fb dot extension on an active low signal The following three designs for example operate identically Design 1 Implied Pin to Pin Active low module act_low2 ot lqgl pin istype reg CLOCK Dany reset OLEA equations q1 q0 ci1ik clock Lat q0 a100 PB Treset test_vectors clock reset gt ql ol k ae zm E hrs Tat pe HO a E bie e Ek SE es Es
135. ser Manual ABEL HDL Compiling To fit the design into the selected CPLD device 1 Double click on Fit Design in the Processes for Current Source window ote In general the Fit Design process is available for PLDs and CPLDs This process runs the optimization and fitting tasks that are necessary to prepare the design for device mapping Depending on the complexity of the design and the current Device Kit these tasks may include node collapsing Espresso logic reduction and fitting tasks such as pin and node assignments However depending on the Vendor Kit you are using the name of the process might be Launch place and route software instead of Fit design where Place And Route software is the name of a third party Place And Route software package that integrates with Synario 2 View the fitter report by double clicking on Fitter Report in the Processes for Current Source window This report tells you how much of the device was utilized and what pin numbers were assigned for each of the input and output signals To create a JEDEC format programming data file e Double click on Create Fuse Map in the Processes for Current Source window or e Double click on JEDEC File in the Processes for Current Source window This option displays the JEDEC file Mate JEDEC Simulation is not supported by all Device Kits Using Test Vectors for CPLD Simulation ote The following section briefly discusses Equation Simula
136. signer User Manual 3 5 Overview of ABEL HDL Sources To see the processes change Use the mouse to highlight each of the sources in the Sources in Project window and look at the processes defined for each type of source Online Help Use online help to guide you through the design entry process The help contains task oriented as well as reference information Browsing Online Help Click on the help icon and spend a few minutes browsing through the ABEL Help Map Getting Context sensitive Help k Click on the context help icon then move the help cursor to a part of the screen you d like more information about such as the Processes for Current Source window and click the left mouse button ABEL displays help about the area of the screen you select Examining the Project Sources Using the Source Editors The tutor1 project consists of ABEL HDL module sources To view or edit a source file double click on the source file name in the Sources in Project window The Project Navigator runs the associated editor with that source loaded To exit the editor window choose Exit from the File menu 3 6 Synario ABEL Designer User Manual Overview of ABEL HDL Sources Creating a PLD Design Consisting of ABEL HDL Sources This section is a tutorial that describes how to enter an ABEL HDL design description The circuit in this tutorial consists of a simple AND gate with a flip flop This tutorial demonstrates how to use ABE
137. ssignment operators when you write high level equations The operator specifies a combinational assignment where the design is written with only the circuit s inputs and outputs in mind The assignment operator specifies a registered assignment where you must consider the internal circuit elements such as output inverters presets and resets related to the memory elements typically flip flops The semantics of these two assignment operators are discussed below Using for Pin to pin Descriptions The implies that a memory element is associated with the output defined by the equation For example the equation Q1 Q1 Preset implies that Q1 will hold its current value until the memory element associated with that signal is clocked or unlatched depending on the register type This equation is a pin to pin description of the output signal Q1 The equation describes the signal s behavior in terms of desired output pin values for various input conditions Pin to pin descriptions are useful when describing a circuit that is completely architecture independent Language elements that are useful for pin to pin descriptions are the t assignment operator and the CLK OE ER CLR ACLR SET ASET and COM dot extensions described in the ABEL HDL Reference Manual These dot extensions help resolve circuit ambiguities when describing architecture independent circuits Resolving Ambiguities In the equation above Q1
138. stered Designs Using for Pin to pin Descriptions Detailed Circuit Descriptions ccccooccccncnnnnnncrnnnnn rra Synario ABEL Designer User Manual V Table of Contents Examples of Pin to pin and Detailed Descriptions Detailed Module with Inverted Outputs c cece cece eee ee ees When to Use Detailed DescriptiONS cece cece eee eeeeeeeeeeees Using for Alternative Flip flop Tvpes Using Active low Declarations ENNEN ENNEN POla rn SOMO EEN Polarity Control with Istype ae RFID HOP EGUACONS msn rios Feedback Considerations Dot ExtensSIOns ccccee cece eee eeeeees Dot Extensions and Architecture Independence es Dot Extensions and Detail Design Descriptions eee Using Don t Care Optimization cooccccccccnccccccnncccnnnnnnnnnnn nn n ranas Exclusive OR e EE e e LE Optimizing XOR Mel Le EEN Using XOR Operators in Eouations ns Using Implied XORs in Eouations rn Using XORs for Flip flop Emulation coocccccccccnnccncncncna nn State EE eegene Use Identifiers Rather Than Numbers for Gates Powerup getest AER EN Unsatisfied Transition Conditions Precautions for Using Don t Care Optimization 000eee Number Adjacent States for One bit Change Use State Register Outputs to Identify States 00occcccccccccconoos Using Symbolic State Descrpotions Using Complement ArrayS e ENNEN ENN ABEL HDL and Truth Tables Basic Syntax Simple Examples Influence of Signal polarity
139. stood by the compiler is the only possible interpretation This means that Truth Tables should be presented in a clear and understandable format should avoid side effects and should be properly documented commented Synario ABEL Designer User Manual 5 43 Synario ABEL HDL Design Considerations Basic Syntax Simple Examples 5 44 In this example the lines commented as L1 and L2 are the ON set Lines L3 and L4 are ignored because Out is type default meaning OU for unspecified combinations The resulting equation does confirm this MODULE DEMO1 TITLE Example 1 Inputs Ay Big Ce PA QOQutput Out pin istype com Truth Table A B c gt Out 0 1 0 O y El 1 1 da dG et LO 30 Li lt Es yA L3 1 0 0 gt Oe aff L4 END Resulting Reduced Equation Out 1A SBS IC AE A amp BEC Example 2 differs from example 1 because Out is now type COM DC optimizable don t care In this case the lines commented as L1 and L2 are the ON set L3 and L4 are the OFF set and other combinations become don t care DC set meaning O or 1 to produce the best logic reduction As a result in this example the equation is VERY simple DCSET instruction would have produced the same result as to declare Out of type dc But DCSET must be used with care when multiple outputs are defined they all become dc MODULE DEMO1 TITLE Example 2 Inputs Py De ES AA Output QUE pim ISC Po com de
140. t Look ir CN Tutor File name Tutor Sun Files of type Project Files suri sl Cancel Synario ABEL Designer User Manual 3 3 Overview of ABEL HDL Sources 3 Highlight the project tutor1 syn and click on OK or press Enter to exit the dialog box There will be a pause while the project loads When the project is open the display should look similar to the following figure Synario Project Navigator TUTOR1 SYN ala File View Source Process Options Tools Window Help atTutorial 1 No Processes Available ed Virtual Device multiply vectors ei multiply multiply abl A adder adder abl Selectthe New buttonto add No processes are available forthe project notebook Select source or Import inthe Source another item inthe Source listto get processes menu to add from a existing design 3 4 Synario ABEL Designer User Manual Overview of ABEL HDL Sources Project Sources A project design is composed of one or more source files e y Warning To ABEL the behavioral sources must all be ABEL HDL sources In Programmable IC however the sources can be a mix of different source types depending on which entry options you purchase and install In order to use ABEL HDL with Programmable IC Entry make sure that you purchased Synario ABEL Each type of source is identified by an icon and name in the Sources in Project window The Sources in Project window is the large scrollable w
141. t Note The Synario CD ROM includes the Acrobat PDF Viewer In order to use this viewer you must install it on a hard drive accessible by your PC If you wish to install the Acrobat PDF Viewer refer to your Synario Installation Instructions Do the following to view online manuals 1 If you chose the Synario Product Option Synario Online Manuals during installation go to the Start Menu and choose Online Manuals from the latest Synario program group OR Run setup exe from the root directory of the Synario CD 2 There manuals lists are organized by product Click on the manual from the list of manuals 3 optional In the PDF viewer press Ctrl F to bring up the Find window Enter text in the find text field then press Enter Tutorials Online Tutorials You can access online tutorial information by the same method as the manuals Synario ABEL Designer User Manual 1 23 ABEL Design Example IC Designs and Multi project Simulations Example IC Designs are included with ABEL Programmable IC design entry products TO open an example IC Design or Multi project Simulation project do the following 1 In the Project Navigator choose File Open Example 2 Navigate to the examples directory 3 Each subdirectory in the examples directory contains an example ABEL Design project 4 Click on the project SYN file you wish to open then click on OK 5 After the example loads you can view documentati
142. ter interface elk rst gt gq q0 Sub module instances ente Functional block counter Sets count cntr1 q7 q0 store r7 r0 Equations pwm count gt store Pulse width Modulated Output ds chow UnC count goes beyond data CHET sel clk de cntri rst clr Clear counter on clr load count 250 Time for next data byte Externally connect load e be EE To elk LAPUL store clk rclk Load data when count store arxa reaches appropriate point END Synario ABEL Designer User Manual Overview of ABEL HDL Sources ABEL HDL Source counter abl MODULE counter TITLE 8 bit preloadable up counter Constants Cys O Inputs Que ESE pun OQutputs q7 q0 pin istype reg buffer Sets count q q0 Equations count count fb 1 count cik clk count ar rst END Using ABEL HDL Hierarchy When you enter or import the two ABEL HDL files two entries will be listed in the Sources in Project window The Sources in Project window display is indented to indicate the hierarchy of the two files In this design the pwmdac module is a top level ABEL HDL file that references one instance of the lower level module counter Instantiating Lower level ABEL HDL Modules An instance of a lower level ABEL HDL module is referenced by using the INTERFACE and FUNCTIONAL_BLOCK statements as shown below counter interface clk rst gt q7 q0 entril Funct onal
143. ter must filter out the common term With the intermediate signal this sub signal is generated only once as the intermediate signal M and the fitter has less to do Using intermediate signals in a large design targeted for a complex PLD or FPGA can save fitter optimization effort and time It also makes the design description easier to interpret As another example compare the state machine descriptions in Figure 3 7 and Figure 3 8 Note that Figure 3 8 is easier to read 3 18 Synario ABEL Designer User Manual Overview of ABEL HDL Sources Figure 3 7 State machine Description without Intermediate Signals CASE which_code_enter from_disarmed_ready CASE sens_code sens_off amp key_code key_pound amp key_code key_star amp key_code key_none code_entry_ X WITH which code enter key_code sens_off amp code_entry_ Y WITH which code enter key_code key_pound error sens _ code sens_ off error ENDCASE which _code_enter from_armed CASE key_code key_pound amp key_code key_star key_code key_none code_entry_ X WITH which code enter key_code key_pound WITH which code enter armed key_code key_none code_entry_ Y WITH which code enter ENDCASE ENDCASE Synario ABEL Designer User Manual key_code whch code enters 3 key_code key_none which_code_enter key_code key_star which_code_enter
144. ters will show The title can contain spaces and any other keyboard character except tabs and returns Synario ABEL Designer User Manual 1 13 ABEL Design ote For some device kits the project directory and project name should be the same 6 In the Project Navigator s File menu click on Save to save your project Open an Existing Project 1 In the Project Navigator s File menu click on Open Project The Open Project dialog box appears Files of type Project Files sun sl Cancel 2 Find the project file syn you wish to open 3 Click on the file and then click on the OK button ote Tf you get an error Cannot create Hierarchy when trying to open a project make sure you have write privileges in the project directory and that the disk has free space for temporary files Save a project To save a project Select Save or Save As from the File menu If you select Save As ABEL asks for a filename to save the project to What is Saved Saving a project saves a project file syn extension with the following information e The title of the project e The sources in the project e The strategy associated with each source sty extension ABEL also tells the text editor to save when you save a project When you select Save As to save a project to another directory ABEL copies all of the project files to that directory 1 14 Synario ABEL Designer User Manual ABEL Design Tips for Saving
145. tion For further information about simulation e For Multi chip simulation refer to the Synario System and Board User Manual e For Equation Simulation refer to Appendix A e For JEDEC Simulation refer to Appendix B e For Verilog Simulation refer to the Verilog Simulator Reference Manual e For VHDL Simulation refer to the Synario VHDL Simulation User Manual Synario ABEL Designer User Manual 4 15 ABEL HDL Compiling For PLD and CPLD devices that are processed using test vectors the Project Navigator provides an Equation simulation process that allows you to simulate your programmed device The actual device can be tested after programming The Equation simulator uses the Equation file to build a model of the design and emulates the operation of a PLD device programmer by applying each test vector and checking the resulting outputs against your specified expected values The Equation simulator does not perform any timing verification because timing values are not part of the Equation file format Adding Test Vectors to the Design In this design we will add the test vectors directly to the source file The system will automatically create a dummy Test Vector file that points to the source file for the test vector stimulus To adequately test this design you will need a large number of test vectors Fortunately ABEL HDL provides language features that help make test vectors easy to describe and generate To create a l
146. to reflect the change in target device When this operation is finished the Processes for Current Source window is updated with processes that are specific to the devices supported by the current Device Kit Synario ABEL Designer User Manual ABEL HDL Compiling 5 Select highlight one of the ABEL HDL sources in the Sources in Project window and see how the processes for the ABEL HDL sources have also been changed to reflect these requirements Mapping the Design to the Selected Device How the Project Navigator maps this design to any PLD or CPLD depends on the Device Kit you are using In general though you must link all portions of the design into a single file in OPEN ABEL format and then map the file into a JEDEC format data file Stepping Manually through the PLD Design Flow The Project Navigator keeps track of all the required steps in the PLD fitting process and the files needed during these steps All you have to do is double click on the result you want such as Create JEDEC File in the Processes for Current Source window However to get a better understanding of all the processes involved in processing a design for a PLD device you may want to go through the following steps Manually To compile the ABEL HDL sources 1 Select one of the ABEL HDL sources in the Sources in Project window 2 Compile the source by double clicking on the Compile Logic process some Device Kits may have a different but similar pro
147. to store the counter values These nodes will appear in the design after the linking process Linking of ABEL HDL designs is required for many of the PLD device types When you are finished entering or importing source files you are ready to process your design The ABEL HDL Reference If you have questions about the ABEL HDL language refer to the ABEL HDL Reference manual Synario ABEL Designer User Manual Overview of ABEL HDL Sources Creating an FPGA Design using ABEL HDL This section discusses how to generate ABEL HDL source files with efficient logic for FPGAs such as Xilinx or Actel devices Entering the Design To start a new project and set up a new directory for this tutorial 1 2 3 4 SR 6 Start Synario or ABEL The Project Navigator window appears From the File menu click on New Project Select IC Design as the project type Click on the Create Directory button to add a new project directory In the Create New Project dialog box enter the Project Filename Click on the OK button to exit the New Project dialog box To change the name of the project design ie Double click on the project notebook icon or project name E Untitled that appears at the top of the Sources in Project window to change the project name From the File menu click on Save the changes to your new project Now you are ready to enter the design Create or Import ABEL HDL Sources Create your ABEL HDL source
148. ual Processing Your Design 1 22 When you click on each source in the Project Navigator a number of processes are brought up Each process list invokes the tools to do that stage of the process You can double click on any stage to generate it and see the results To run processes that affect the entire project such as place and route in the Processes window click on the project design icon and then double click on the process To run simulation on the entire project click on the test file that is associated with the project design icon this file should be located directly below the design icon To run processes that affect a single source and it s components in the Processes window click on the source and then double click on the process To run simulation on a source click on the test file that is associated with the source this file should be located directly below the source Synario ABEL Designer User Manual ABEL Design Help Online Documentation and Tutorials Help Context sensitive help is available in the Project Navigator by e Clicking on the Context Help button del and then clicking on the item you want information on e Clicking on an item such as a process and then pressing the F1 key e Clicking on the Help button in a dialog box General help is available by clicking on a menu item in the Help menu Manuals You can view an online manual using any installed PDF file viewer Importan
149. uded with the Vendor Kit you are using ote For more information about design considerations refer to Chapter 5 ABEL HDL Design Considerations Architecture Independent Compiling As mentioned above there is really no Architecture device independent compiling because all compiling is tied into which type of device you are designing for and which Device Kit you are currently using However with an IC Design project you can target your design to a Virtual Device The Virtual Device is tied in to a generic Device Kit that uses generic symbols and libraries Not all the processes will be available for instance Place And Route is not available but you can switch to a device specific Vendor Kit either a Device Kit or Interface Kit later if you wish Synario ABEL Designer User Manual 4 1 ABEL HDL Compiling For multi chip simulation you create a System Simulation project which can link to IC Design projects The System Simulation project is always a Virtual System which is architecture independent but the project can have project links to child IC Design projects that can be device specific ABEL HDL for PLDs This section continues the same tutorial started in Chapter 3 in the section titled Creating a PLD Design Consisting of ABEL HDL Sources You can either continue the tutorial or just read the text below to get a general idea of how to compile ABEL HDL for a generic PLD Keeping Track of Processes Auto
150. ueeuneanens Registered design descriptions cece cece scenes aran nnnn nr Registered MONOS terre ee Registers bit values in State machines cece eeeneeeeeeueeeeeeueeneeeueeueeuueeueeaueauennnsegs cleared state in state machines mirra DOWEIUD ER EE Reset Index 6 Synario ABEL Designer User Manual Index elei ge E leet RE CRTA example non inverted architecture ssserrsssrrrrsrrrrrrsrrrnrerrrrnnsrrrrneerernn 5 12 FESOIVINO AMPOULE eerren as 5 12 Selecting FPGA DEVICE EE selective CON CI SUING EE UENCE He Signals declaring in ABEL HDL for FPGAS ccccsccccessscecccsssceccessuceecensuscecensausecensanees 3 16 Simulating an FPGA e e EE 4 19 Simulation values alter Vatter Ei NEE C 9 Simulator required for Waveform Viewer EEN ii Sources adding and TEO EE cn EE EE E E TEE MADOC e ER MOCO C rei e EEN AB top level behavioral module EEN REENEN REENEN SR flip flop nie EE A PORO PO MI E E EERE State machine example rivera ODCEPE ino A cr o e o State machines a a a DCSE FACS luar as ci ared EE design consideracion Sist tata aa dentes EE POSTE Let EE Lets EI dE p werup Reie gg FEGUCING Product LENS EE USO State register OU e e ENOTE Eet o EE Symbollc State descriptos EE M 2 2 2 3 T flip flop and Cava AS EE IS e e CONVErsSION Ol JEU EE Iden EN TOP aAOWA Ke e Neira aan ge d Lee EE man e RE Transferring designs Synario ABEL Designer User Manual Index 7 Index Transit
151. ulator then calculates the product terms that result from the test vector the OR outputs that result from the product terms any macrocell outputs that result from the OR outputs and any feedback functions The results of the simulator calculations are written to the sim file Synario ABEL Designer User Manual A 1 Equation Simulation ae Set up internal registers Calculate product terms Calculate OR outputs Calculate macro cells Calculate feedback functions Figure A 1 Simulation Flow Diagram Trace detail or clock output 20 iterations yet Report error Trace brief level 0 output 0698 1 The outputs of designs with feedback may require several successive evaluations until the outputs stabilize After the feedback paths have been calculated the simulator checks to see if any changes have occurred in the design since the product terms were last calculated If changes have occurred due to feedback functions the calculations are repeated This iterative process continues until no changes are detected or until 20 iterations have taken place If 20 iterations take place and there are still changes the design is determined to be unstable and an error is reported More detailed information on simulating devices with feedback and other advanced uses of the Simulation program are presented in the Equation and JEDEC Simulators Manual The Simulator Model The Equation simulator uses the Equation file to build a
152. update The following figure shows the Processes for Current Source window for andff an ABEL HDL source file aynario Project Navigator TUTOR 2 SYN File View Source Process E Tutorial session 2 Compile Logic d Virtual Device Check Syntax E andff vectors Compiler Listing ME andff andff abl Compiled Equations G Reduce Logic Reduced Equations or selectthe Start button to startthe process Selectthe Properties button to start the property editor There are more processes required for an ABEL HDL source file than for a schematic because the ABEL HDL source file requires compilation and optimization before you can run a simulation But because the Project Navigator knows what processes are required to generate a simulation file from an ABEL HDL source you can double click on the end process you want The auto update feature automatically runs any processes required to complete the process you request Device related processes such as mapping the selected ABEL HDL source file to a JEDEC file will be available in the Processes for Current Source window after you select a device for this design Synario ABEL Designer User Manual ABEL HDL Compiling Compiling an ABEL HDL Source File The Project Navigator s auto updating reprocesses sources when they are needed to perform the process you request You do not need to worry about when to recompile ABEL HDL source files However you can compile
153. utput_q REG no equation La Eol O 23 RO 1 Rec Off No wrap DOS INS In this example the compiled equations are identical to the equations that you entered in the ABEL HDL source file This is because the equations were simple Boolean equations that did not require any advanced compiling in order to be processed 4 4 Synario ABEL Designer User Manual ABEL HDL Compiling Using Properties and Strategies for PLDs For many processes such as the compiling and optimizing steps shown above there are processing options you can specify These options include compiler options such as custom arguments or processing changes and optimization options such as node collapsing You can use properties to specify these options Properties The properties available at any given time depend on the following conditions e The selected type of source file in the Sources in Project window for example ABEL HDL e The selected process in the Processes for Current Source window e The selected device for the project for this example we have selected a Virtual Device which is considered to be a generic PLD To see how properties are set change the type of listing file that is generated for all ABEL HDL sources for the current project in the following manner 1 Highlight the ABEL HDL source file in the Sources in Project window by clicking on the andff ABEL HDL source 2 Highlight do not double click Compile Logic
154. vel module in a VHDL module For more detailed information about ABEL HDL refer to the ABEL HDL Reference Manual and Chapters 3 4 and 5 in this manual 1 In a Text Editor open your ABEL HDL file File Open or create a new ABEL HDL file File New 2 In the ABEL HDL file use the tnterface and functional_block keywords to instantiate lower level files You can also use the Interface keyword in lower level files to link to upper level ABEL HDL modules not upper level schematics You can place multiple instances of the same interface in the Same design by using the functional_block statement Refer to the ABEL HDL Reference Manual for more information 3 The interface must have same names as the pin names ABEL HDL in the lower level module The following figures show one upper level ABEL HDL module and different ways to implement the lower level modules Synario ABEL Designer User Manual 2 3 Hierarchical Design in ABEL Figure 2 2 Top level ABEL HDL Module for NAND1 MODULE nandl TITLE Hierarchical nand gate Instantiates an and gate and a not gate dee Za Os DLI The following code defines the interfaces components andl and notl Andl corresponds to the lower level module AND1 vhd AND L ABL or AND1 SCH For component AND1 the INI IN2 and OUT1 interface names correspond to IN1 IN2 and OUT1 in the lower level module andl INTERFACE IN1 IN2 gt QUTL notl INTERFACE IN1 gt OUT1
155. vice Kit that supports Complex PLDs installed and licensed In this design tutor3 the pwmdac module is a top level ABEL HDL file that references one instance of the lower level module counter Using Properties and Strategies For many processes such as the compiling and optimizing steps Shown above there are processing options you can specify These options include compiler options such as custom arguments or processing changes and optimization options such as node collapsing You can use properties to specify these options Properties and Strategies are set in the same manner as described in the previous section for PLDs For more information about properties refer to the Device Kit manual and online help for the device architecture you are using Selecting a Device 4 12 The primary goal of this tutorial is to learn about the design flow using complex PLDs Select a device in the following manner 1 Double click on the device icon GER to change the device 2 In the Choose Device dialog box select a Device Kit from the Device list box Select a Complex PLD from the Device list box Choose the OK button to exit the Choose Device dialog box When you exit the window the Project Navigator warns you that changing to a Device Kit has an impact on your project and prompts for confirmation Choose the Yes button There can be a noticeable pause while the Project Navigator reconfigures all the processes in the project
156. w sources or import existing sources into your project All sources are saved in the same directory as the project syn file For information on how to build a IC sources refer to the rest of this manual To edit a source in the project double click on the source in the Project Navigator Sources Window ote You can also import sources into your project by drag and dropping the files into the Project Navigator from the Windows File Manager or Explorer 8 Double click on the device icon Eu The Choose Device dialog box appears 9 In the Choose Device dialog box click on the Device Family Kit and device that you intend to target your design to and then click on OK You can change this later if you wish If asked if it is OK to change board kits click on OK You do not need to choose a specific device for functional simulation you can use Virtual Devices 10 After adding design source files you need to add test files to your project for simulation For instance import test vector abv files for Equation or JEDEC simulation 11 Click on sources to see the available processes for each source type Double click on a process to run that process Synario ABEL Designer User Manual 1 21 ABEL Design 12 To place and route or fit your design single click on the device icon ad and double click on the Fit Design or Place and Route process For more information on IC Designing refer to the rest of this man
157. way to set options in your project is to use strategies A strategy is a set of properties processing options that you have specified for some or all of the sources in your project Strategies can be useful as your processing requirements change depending on factors such as size and speed tradeoffs in synthesis or whether your design is being processed for simulation or final implementation With strategies you do not have to modify the properties for every source in the design if you want to change the processing options Strategies allow you to set up properties once then associate a strategy with a source to which you want to apply the properties You can create new strategies that reflect different properties for the entire project and then associate one or more custom strategies with the sources in your project 4 6 Synario ABEL Designer User Manual ABEL HDL Compiling To see how strategies work 1 From the Source menu click on Strategy 2 In the Define Strategies dialog box select the New button to create and name a new strategy This is shown in the following figure Synario Project Navigator TUTOR2 SYN e File View Source Process Options Tools Window Help A Tutorial sessiol Define Strategies ea Virtual ence atrategy m5 Associated Sources Elandff vectors 3 Enter a name for the strategy then click on the OK button The new strategy appears in the Strategy drop do
158. with the invert attribute has necessitated a change in the equation for Q1 D As this example shows device independence and pin to pin description methods are preferable since you can describe a circuit completely for any implementation Using pin to pin descriptions and generalized dot extensions such as ER CLK and OE as much as possible allows you to implement your ABEL HDL module into any one of a particular class of devices For example any device that features enough flip flops and appropriately configured I O resources However the need for particular types of device features such as register preset or reset might limit your ability to describe your design in a completely architecture independent way Synario ABEL Designer User Manual 5 11 Synario ABEL HDL Design Considerations If for example a built in register preset feature is used in a simple design the target architectures are limited Consider this version of the design module Q1 51 SN pin istype reg buffer Clock Preset pin equations Q1 CLK Clock OI Ab Preset Q1 AE Ee test_vectors Clock Preset gt Q01 L Ge y Eo oa Zb ieee y 0 gt 0 LO 43 Et gt 1 Kr tee O d ee 0 Li Ze 1 gt 1 L we de pk eg EE end The equation for Q1 still uses the assignment operator and FB for a pin to pin description of Q1 s behavior but the use of AP to describe the reset function requires consideration of different devi
159. wn list box Synario ABEL Designer User Manual 4 7 ABEL HDL Compiling To associate a source with a new strategy 1 Click on the Associate button in the Define Strategies dialog box 2 Highlight the ABEL HDL source andff in the Source to Associate with Strategy list box 3 Click on the Associate with Strategy button The andff source appears in the Sources Associated with Strategy list box Define Strategies Associated Sources tutorial 2 strategy D andit Cancel ASt SOc late gt gt _ _ _ _ _ QQ QQ J 22222222 Nr Source to Associate with Strate A _ _ A Associate With Strategy Synario Project Navigator TUTOR2 SYN vw 3ynario Project Navigator TUTOR2 SYN HE File View Source Process S Tools Window Help Sources in Project as for Current Ee El Tutorial session 2 C42 Compile Logic CO Virtual Device Check Syntax Elandff vectors Compiler Listing Toi andff andff abl i El Compiled Equations Reduce Logic Reduced Equations a click to open the selected Double click the item in the list or selectthe Stat button to Source statthe process selectthe Properties button to start the property editor Note There is a shortcut method to associate a source with a strategy from the Project Navigator Highlight a source and use the Strategy drop down
160. x Trig Indicates whether the current trigger conditions are True or False It appears on the prompt line only if triggers have been defined Synario ABEL Designer User Manual C 3 Waveform Viewing Selecting the Waveforms to View Show The most fundamental operation in the Waveform Viewer is adding waveforms to the display Once waveforms are displayed they can be moved deleted copied and converted to bus format using the commands described in the following sections Waveforms are added to the display with the Show command from the Edit menu The Hierarchical Name List dialog box Figure 2 that appears when you select this command lets you choose a signal from any level in the hierarchy and combine two or more signals into a bus display Figure 2 Hierarchical Name List Dialog Box Hierarchical Name List lei E eset Finding the Signal You Want The large list box at the left and the control button above it simplify navigating the hierarchy to find the signals you want The list box initially displays the top level of the hierarchy Clicking the Push button displays the hierarchical level if any below the top level To move to a lower hierarchical level highlight that level in the list box then click the Push button If you are already at the lowest level the button is relabeled Pop since you can only move upward in the hierarchy A display line below the list box shows the full hier
161. y a particular device when describing your design Attributes and dot extensions help you refine your design to work consistently when moving from one class of device architecture to another for example from devices having inverted outputs to those with a particular kind of reset preset circuitry However the more you refine your design using these language features the more restrictive your design becomes in terms of the number of device architectures for which it is appropriate Signal Attributes Signal attributes remove ambiguities that occur when no specific device architecture is declared If your design does not use device related attributes either implied by a DEVICE statement or expressed in an ISTYPE statement it may not operate the same way when targeted to different device architectures See Pin Declaration Node Declaration and Istype in the ABEL HDL Reference Manual for more information Signal Dot Extensions Signal dot extensions like attributes enable you to more precisely describe the behavior of a circuit that may be targeted to different architectures Dot extensions remove the ambiguities in equations Refer to Dot Extensions later in this chapter and in Language Structure or ext in the ABEL HDL Reference Manual for more information Synario ABEL Designer User Manual Synario ABEL HDL Design Considerations Pin to pin vs Detailed Descriptions for Registered Designs You can use ABEL HDL a

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