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Infineon SDA 555X TVText Pro User`s Manual

1. 2 6 Pin Configuration P MQFP100 ROMIless Version top view e e 9 Qoo 4 LO O O O L 11 lt N Q co 0 x O O o Q QO lt n L lt lt gt gt lt lt lt lt lt lt lt lt lt DiC 4 FL_RST D4c e 7 D2 o 3 A13 D A12 XROM 1 14 VDD 2 5 VDD 3 3 VSS vss VDD 3 3 VDD 2 5 P0 0 4 FL PGM P0 1 5 A15 2 1 A17 PO 3 16 0 4 18 TVTEXT PRO om SDA 55XX Poro P MQFP 100 Ee WR STOP E P1 7 EXTIF CVBS r3 BLANK COR VDDA 2 5 OB VSSA P2 0 OR P2 1 VDDA 2 5 P2 2 7 VSSA P2 3 XTAL1 HS SSC XTAL2 VS L3 ahaadraaaSQooHoooaoooAIL gt Figure 3 P MQFP100 ROMIess Version Semiconductor Group 25 User s Manual July 99 Infineon technologies Preliminary amp Confidential SDA 55xx Package and Pinning
2. 2 7 Pin Configuration P LCC 84 ROMIess Version top view e eo QN o O o o aa a a8 zaxzZ25 x2arxx2222 03 7 XROM e A13 VDD 2 5 A12 vss A14 VDD 3 3 VDD 3 3 P0 0 vss P0 1 VDD 2 5 P0 2 L3 A15 P0 3 L2 A17 P0 4 TVTEXT PRO 2 A16 P0 5 SDA 55XX A18 P0 6 P LCC 84 A19 P0 7 P1 7 CVBS BLANK COR VDDA 2 5 B VSSA G P2 0 R P2 1 VDDA 2 5 P2 2 VSSA P2 3 XTAL1 HS SSC XTAL2 c O i O Q N ME gt cj c e gt 00 0 0 u o agdadadtaaSsoooooaoaoaania a gt Figure 4 P LCC 84 ROMIess Version Semiconductor Group 26 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential SFR Overview 3 SFR Overview Add Long name Short Name Bit Reset Location Bit6 Bit5 Bit 4 Bit3 Bit2 Bitt Bito Add Value 80 Port 0 PO Yes FF Port P07 P0 6 P0 5 2 P0 1 P0 0 81 Stack pointer SP Miro SP_7 5 6 SP5 5 4 5 3 5 2 5 1 5 0 82 Data Pointer Low DPL No Miro DPL 7 DPL 6 DPL 5 DPL 4 DPL 3 DPL 2 DPL 1 DPL 0 83 Data Pointer
3. Figure 7 VBI Buffer General Structure Semiconductor Group 45 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition 5 5 Register Description The acquisition interface has only two SFR Registers The line and field parameters are stored in the RAM RAM Registers They have to be initialized by software before starting the acquisition Special Function Registers Default after reset 00 STRVBI SFR Address D9 MSB LSB ACQON reserved ACQSTA VBIADR VBIADR VBIADR VBIADR VBIADR Defines the 4 MSB s of the start address of the VBI buffer the ACQSTA ACQON Semiconductor Group LSB s are fixed to 0 by hardware The VBI buffer location can be aligned to any 1 KByte memory segment First Framing code after vertical sync 0 No framing code after vertical sync has been detected 1 Framing code after vertical sync has been detected Note The bit is set by hardware and cleared by software Enable Acquisition 0 The ACQ interface does not access memory immediately inactive 1 The ACQ interface is active and writes data to memory switching on is synchronous to V 46 User s Manual July 99 i SDA 55xx Infineon technologies Preliminary amp Confidential Slicer and Acquisition Default after reset 00 CISRO bit adressabl
4. BLANK COR B G R VDDA 2 5 VSSA XTAL1 XTAL2 RST P4 3 P4 2 VDD 3 3 VSS P3 7 P3 6 Figure 1 P SDIP 52 ROM Version of SDA 55xx Semiconductor Group 23 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Package and Pinning 2 5 Pin Configuration P MQFP 64 ROM Version top view 3 NE jg w p p p w s s s D n D D D D n D D a 22 N C N C N C P1 1 P0 7 P1 0 VDD 2 5 VDD 3 3 VSS vss VDD 3 3 VDD 2 5 CVBS TVTEXT PRO BLANK COR VDDA 2 5 SDA 55XX B VSSA P MQFP 64 G P2 0 R P2 1 VDDA 2 5 P2 2 VSSA P2 3 XTAL1 HS SSC XTAL2 VS N C N C N C OO 9 N c x 10 r 0 Q I 65 zzo eee VDD 3 3 Figure 2 P MQFP 64 ROM Version Semiconductor Group 24 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Package and Pinning
5. Infineon SDA 55xx tecnnologies Preliminary amp Confidential SFR Overview Default after reset 00 CSCR1 SFR Address DE MSB LSB IntSrc1 IntSrc0 ENARW 19 P4 4 A18 P4 1 A17 P4 0 IntSrcO 0 Port 3 3 is the source of the interrupt 1 SSU is the source of interrupt Application note Use with SEL 1 IntSrc1 0 Port 3 2 is the source of the interrupt 1 SSU is the source of interrupt Application note Use with SEL 0 Not used Not used ENARW 0 Port P4 2 and P4 3 function as port pins 1 Port P4 2 and P4 3 function as RD and WR signal outputs A19 P4 4 0 Pin functions as Address line 1 Pin function as port A18 P4 1 0 Pin functions as Address line 1 Pin function as port A17 P4 0 Pin functions as Address line Semiconductor Group Pin function as port 32 User s Manual July 99 e Qnin SDA 55xx technologies Preliminary amp Confidential Clock System 4 Clock System 4 1 General Function The on chip clock generator provides the TVTpro with its basic clock signals that controls all activities of the hardware Its oscillator runs with an external crystal and appropriate oscillator circuitry refer to Application Diagram For applications with low accuracy requirements RTC is not used the external oscillator circuit can also be a ceramic resonator Depending on the absolute tolerance of the resonator the slicer may not work correctly Moreover the disp
6. Preliminary amp Confidential Memory Organization Interrupt Source Vector Address Reserved 006B Reserved 0073 Reserved 007B PWM in timer mode 0083 Channel Change 008B Acq H Sync 0093 Display H Sync 009B Reserved 00A3 Reserved 00AB Reserved 00B3 Reserved 00BB Line 24 start 00C3 A to D wake up 00CB 10 2 Internal Data RAM Internal Data RAM is split into CPU RAM and XRAM 10 2 1 CPU RAM Address space The internal CPU RAM IRAM occupies address space 00 to This space is further split into two where lower 128 Bytes 00 7 can be accessed using both direct and indirect register addressing method Upper half 128 Bytes 80 be accessed using register indirect method only Register direct method for this address space 80 FF is reserved for Special function register access Registers Controller registers are also located in IRAM Four banks of eight registers each occupy locations 0 through 31 Only one of these banks may be enabled at a time through a two bit field in the PSW Bit addressable RAM area 128 bit locations of the on chip RAM are accessible through direct addressing These bits reside in internal data RAM at byte locations 32 through 47 Semiconductor Group 108 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Memory Organization Stack The stack can be located anywhere in the internal data RAM address space
7. 156 18 Display P 170 18 1 Display Features LR XR ESI P Eee vedere 170 18 2 Display Memory oc isses hk Red d SK nnii UPEER eee 171 18 3 Parallel Character Attributes 172 18 3 1 Access of Characters 173 18 3 2 Flash ede Sb EE px dew haw a Ds 176 18 3 3 Character Individual Double Height 176 18 3 4 Character Individual Double Width 178 18 4 Global OSD Attributes 179 18 4 1 Character Display Area Resolution 183 18 4 2 cog LITT 184 Semiconductor Group 6 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential 18 4 3 18 4 4 18 4 5 18 4 6 18 4 7 18 4 8 18 4 9 18 4 10 18 5 18 5 1 18 6 18 6 1 18 6 2 18 6 3 18 6 4 18 6 5 19 19 1 20 20 1 20 2 20 3 20 4 20 5 21 22 23 Border Color osc ke Rr EA he Re Yaga DR EE X wes 187 Full Screen Double Height 188 Flash Rate 190 Transparency of Boxes 191 CUT sucede Ree ERE xor Meee ee bas YD ae ee oe 194 Character Resolution 199 Shadowing 201
8. 104 8 4 Power save mode 104 8 5 Slow down mode 104 9 Reset oso UI RR D pee Qa q 105 9 1 Reset SOUICES MERE ERA Ru 105 9 2 Reset filtering b RE asul asas E PEE RIA 105 9 3 Reset duratlor cie E aqasha 105 9 4 aci RP 105 9 5 Functional blocks 2 2 usya uqyana Varus e gh us ER REED 105 9 6 RAMS 105 9 7 Analog blocks gt Hoek Gk dake bee RE teni 106 9 8 Processo niis b RR 106 9 9 PORS RR 106 9 10 Initialization phase 106 9 10 1 ACQUISITIOTI o dod IURE Db LER kusapas abis tied oe 106 9 10 2 DISDIAY AP 106 10 Memory Organization 107 10 1 Program 107 Semiconductor Group 4 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential 10 2 Internal Data RAM PUR DR Pep el 108 10 2 1 CPW RAM x ipd ug pa baypa cite aie ORE awa 108 10 2 2 Extended Data RAM XRAM 109 10 3 Memory Extension 2 chua IER xem m RUE RM RUE ROS 109 10 3 1 Memory extension registers 110 10
9. Input Fall Time Ti 200 ns 1096 9095 Input Hysteresis Vuyst 300 600 mV Input Pulse Width Tipwy 2 fh Output Pulse Width Tipwy Depends on Register HPR Output Rise Time T 100 ns 1096 9095 Output Fall Time T 100 ns 10 90 Load Capacitance C 50 pF Pin capacitance C 5 pF VCS Timing Master mode Pulse width of H Sync Tupves 4 59 us Distance between Tpep 31 98 us Equalizing Impulses Pulse Width of Equalizing Tep 2 31 us Impulses Pulse Width of Field Sync Trspe 27 39 us Impulses Horizontal Period Tupr us Depends on Register HPR P1 x P3 x 4 Output Rise Time T ns 1096 9095 Output Fall Time ns 1096 9095 Load Capacitance pF Pin capacitance pF Input Impedance Z 1 Analog Ports MO Input Sample Frequency F MHz General Purpose Ports Output Current I mA P3 10 P3 14 Semiconductor Group 220 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Electrical Characteristics Parameter Symbo Limit Values Unit Test Condition Hysteresis Voltage Uis mV PC Inputs P6 5 6 6 P6 7 P3 0 P3 1 A D Converter Characteristics Port 2 0 to P2 3 Input Voltage Range Vain
10. Type Additional reference Available vO SDIP52 MQFP64 MQFP100 PLCC84 Port 3 is an 8 bit bidirectional port with internal pull u resistors Port 3 pins that have 1 written to them are pulled hig by internal pull up resistors and in that state can be used as inputs To use the secondary functions of Port 3 the corresponding output latch must be programmed to a one 1 for that function to operate The secondary functions are as follows P3 0 ODD EVEN indicate output P3 1 external extra interrupt 0 INTXO UART T P3 2 interrupt 0 input timer 0 gate control input P3 3 interrupt 1 input timer 1 gate control input INT1 P3 4 counter 0 input TO P3 5 counter 1 input 1 or In master mode HS or VCS output P3 7 external extra interrupt 0 INTX1 UART RXD Semiconductor Group 17 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Package and Pinning Symbol P4 2 P4 3 P4 7 RST Vima Yma Vss CVBS HS SC XTAL1 Function Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 Port 4 is a bidirectional I O port with internal HR resistors Port 4 pins that have 1 written to them are pulled high by the interna pull up resistors and in that state can be used as inputs Secondary functions _ P4 2 RD Read line This signal is same as the to output of the pin RD available in some packages Type
11. PWM 8bit 2 comp8 2 00 PWM PC827 PC826 PC825 PCB24 PCH23 822 PC82 1 PC82 0 C4 PWM 8bit compare 3 comp8 3 No 00 PWM PC837 PC836 PC835 PCB34 PCB33 PCB32 PC83 1 PC83 0 C5 PWM 8bit compare 4 comp8 4 00 PWM PCB4 7 PCB46 PWCBA5 PCBA4 PCB43 PCBA2 PC84 1 PCB4 0 C6 PWM 8bit compare 5 PWM comp8 5 No 00 PWM PCB5 7 PCB56 855 PCB54 PCB53 PCB52 PC85 1 85 0 PWM I4bit compare 0 14 0 No 00 PWM PCi40 7 PC1400 6 140 5 PCi404 PCi40 3 PCi402 1401 140 0 C8 Centralintservice 1 CISR1 Yes 00 Interrupt CC ADW IEX1 IEX0 C9 PWM l4bit compare 1 PWM_comp14_1 No 0 PWM PCi4i 7 PCi4i 6 141 5 141 4 141 3 141 2 141 0 PWM 14bit comp ext 0 PWM compext 4 0 00 PWM PCX140 7 140 6 PCXi40 5 PCXi40 4 PCX140 3 PCX140 2 PCXi40 1 PCXi40 0 CB PWM 14bit comp ext 1 PWM compext 4 1 00 PWM PCXi41 7 PCXi4i 6 PCXi41 5 PCXi4i 4 141 3 PCX141_2 PCXi4i 1 PCXi4i 0 CC PWM counter low byte PWM cl No 00 PWM PWC 7 PWC 6 PWC 5 PWC 4 PWC3 PWC 2 PWC 1 PWC 0 CD PWM counter high byte PWM ch 00 PWM Tmr PWC 13 PWC i2 11 PWC 10 PWC 9 PWC 8 CE PWM channel enable PWM En No 00 PWM PEG PES 2 PE0 Semiconductor Group 28 User s Manual July 99 I
12. Source impedance 500 Q Overall CVBS amplitude Voves 0 5 2 V CVBS sync amplitude V 0 1 0 6 V TXT data amplitude J z 0 15 0 7 V De coupling Capacitors Cpe ce nF at Pins CVBSi RGB Outputs Load capacitance 20 pF Output voltage swing 05 12 available 0 5V 0 7V 1 0V 1 2V RGB offset 0 27 10 33 V Rise Fall Times 12 5 ns 12 5ns 32MHz output BW Semiconductor Group 217 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Electrical Characteristics Parameter Symbo Limit Values Unit Test Condition Diff non linearity 0 5 05 LSB Int non linearity 0 5 05 15 Output current tracking 3 96 Skew to COR Blank 5 5 ns Jitter to Horizontal Sync Tj 4 ns Reference Address Bits 0 to A15 ALE PSEN RD WR Output Rise Time T ns 1096 9095 Output Fall Time T ns 10 90 Load Capacitance C pF P4 0 4 Alternate address control lines Output Rise Time T ns 1096 9095 Output Fall Time ns 1096 9095 Load Capacitance C pF Data Bits DO to D7 Output Rise Time T ns 1096 9095 Output Fall Time Ti ns 1096 9095 Load Capacitance C pF Pin capacitance C pF Pin capacitance C pF BLANK CORBLA Output Rise Time T 8 1
13. Chiu SDA 55xx Preliminary amp Confidential Analog Digital Converter CADC Default after reset 00 CADC3 SFR Address D4 MSB LSB CADC3 7 CADC3 6 CADC3 5 CADC3 4 CADC3 3 CADC3 2 CADC3 1 CADC3 0 CADC3 7 0 ADC result of channel 4 After finishing the A to D conversion the processor is informed by means of an interrupt The interrupt service routine can now take the conversion result of channel 4 from CADC3 The result will be stable for about 50us after the interrupt Default after reset 00 CADCCO SFR Address D5 MSB LSB ADWULE AD3 AD2 AD1 ADO ADO AD1 AD2 AD3 Semiconductor Group Defines whether the port pin is used as analog input or as digital input 0 port pin is digital input the analog value has less precision 1 port pin is analog input the digital value is always 0 Defines whether the port pin is used as analog input or as digital input 0 port pin is digital input the analog value has less precision 1 port pin is analog input the digital value is always 0 Defines whether the port pin is used as analog input or as digital input 0 port pin is digital input the analog value has less precision 1 port pin is analog input the digital value is always 0 Defines whether the port pin is used as analog input or as digital input 0 port pin is digital input the analog value has less precision
14. Semiconductor Group 203 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display Example for a A displayed in shadow mode no shadow east shadow west shadow shadowed pixel C background pixel W foreground pixel Figure 21 Processing of Shadowing Within one character matrix shadowing is only processed for the pixels which are belonging to that character matrix Pixels of one character matrix can not generate a shadow inside a neighboured character matrix 18 4 10 Progressive Scan This feature is useful for TV devices in which a frame consists of 1 field with 625 lines instead of 2 fields with 312 5 lines each For this TV fields on RGB output lines are be repeated twice by enabling the progressive scan feature This repetition of lines in vertical direction is only processed for lines inside the character display area PROGRESS Description 0 progressive scan support is disabled 1 progressive scan support is enabled see also 1 4 Global Display Word GDW Semiconductor Group 204 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 5 DRCS characters DRCS characters are available in the
15. wakeup PWM CRT WDT DAC PLL and Display display pixel clock and D sync can be turned off Slow down mode In this mode the system frequency is reduced by one fourth All modes are entered by software Special function register is used to enter one of these modes 8 1 Power Save mode registers Default after reset 00 PSAVE bit addressable SFR Address D8 MSB LSB CADC WAKUP SLI ACQ DISP PERI Not used CADC Controller ADC 0 Power save Mode not started 1 Power save Mode started In Power save mode all 4 controller ADC channels are disabled WAKUP Wake up of CADC 0 Power save Mode not started 1 Power save Mode started In Power save mode ADC wake up unit of CADC is disabled Note that Power save mode of wake up unit is only useful in saving power when CADC bit is set Semiconductor Group 99 User s Manual July 99 Infineon SDA technologies Preliminary amp Confidential Power Saving modes SLI ACQ Slicer and Acquisition 0 Power save Mode not started 1 Power save Mode started In Power save mode Video A to D Slicer sync unit and acquisition are disabled All the pending bus requests are masked off DISP Display unit 0 Power save Mode not started 1 Power save Mode started In Power save mode display generator pixel clock unit display sync unit sandcastle decoder and COR BLA are disabled All the pending bus request are masked off DAC is also switched o
16. 12 11 10 9 8 PWM Tmr Start stop timer when all PWM channels are disabled If this bit is set the PWM timer will be reset and starts counting If this bit is cleared the PWM timer stops The PWM_Tmr bit could not be written set if one of the PWM channels is enabled PWM en not all zero PWM en register could not be written set if the bit is set OV Overflow bit for the timer mode Bit 5 Bit 0 These bits are the high order 6 Bits of the 14 Bit PWM Counter Semiconductor Group This register can only be read 140 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Watchdog Timer 15 Watchdog Timer Watch dog timer is 16 bit up counter which can be programed to clock by f 4 2 or fiygi 128 The current count value of the watchdog timer is contained in the watchdog timer register WDT High and WDT Low which are read only register Control and refresh function of the WDT is controlled by WDT Refresh and WDT Ctrl Additionally counter can be used as a general purpose timer in timer mode and the associated load register can be used either as load register or independent scratch register by the user 15 1 Input clock Input clock fwg is same as CPU clock f divided by 12 i e machine cycle is fed to the WDT either as divide by 2 or divide by 128 Divide factor is determined by WDT In WDT ctrl equal 0 and 1 respectively WDT I
17. Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Bit Function SND H 2 0 Slicing Level Horizontal Sync Pulses S ave mode Sanacastle input To fit the requirements of various applications the input circuit of the sandcastle decoder is free programmable The slicing levels for the horizontal pulses can be varied in a range from 1 33V up to 2 50V in steps of about 0 16 V 000 Horizontal Slicing Level set to 1 33V 001 Horizontal Slicing Level set to 1 50V 010 Horizontal Slicing Level set to 1 67V 011 Horizontal Slicing Level set to 1 83V 100 Horizontal Slicing Level set to 2 00V 101 Horizontal Slicing Level set to 2 17V 110 Horizontal Slicing Level set to 2 33V 111 Horizontal Slicing Level set to 2 50V These are nominal values They may also differ with supply voltage SND V 2 0 Slicing Level Vertical Sync Pulses S ave mode Sandcastle input To fit the requirements of various applications the input circuit of the sandcastle decoder is free programmable The slicing levels for the vertical pulses can be varied in a range from 0 67V up to 1 83V in steps of about 0 16 V 000 Horizontal Slicing Level set to 0 67V 001 Horizontal Slicing Level set to 0 83V 010 Horizontal Slicing Level set to 1 00V 011 Horizontal Slicing Level set to 1 17V 100 Horizontal Slicing Level set to 1 33V 101 Horizontal Slicing Level set to 1 50V 110 Horizontal Slicing Level set to 1 67V 111
18. ot Webs cee aes tele whale ahaa seated 135 14 5 Cycle time ee epe de yee Peay ei eb eee e ed eels 136 14 6 Power down idle and Power save mode 136 14 7 TIMER onion IMS P UMS deep reete edes 136 14 8 Control registers 137 15 Watchdog Timer 141 15 1 Input elock oe ele Q a EDEN 141 15 2 Starting WDT Geus RR wide had 141 15 3 Refresh P UTEM 141 15 4 WDT r6SBl insere ee Lege eee ecd een 142 15 5 Power down 142 15 6 Time period 2 ke nube 143 15 7 Block Diagram 2 144 15 8 WDT as general purpose 145 16 Analog Digital Converter 147 16 1 Power Down Wake 147 16 2 Register Description 147 17 Sync System 4 2 uuu 153 17 1 General Description 1 153 17 1 1 Screen Resolution 153 17 1 2 Synelnterr plS pb ux ER DER Reed eue i ag 155 17 2 Register Description
19. Single Double Width Height of Characters Variable Flash Rate Programmable Screen Size 25 Rows x 33 64 Columns Flexible Character Matrixes HxV 12 x 9 16 Up to 256 Dynamical Redefinable Characters in standard mode 1024 Dynamical Redefinable Characters in Enhanced Mode CLUT with up to 4096 color combinations Upto 16 Colors per DRCS Character One out of Eight Colors for Foreground and Background Colors for 1 bit DRCS and ROM Characters Shadowing Contrast Reduction Pixel by Pixel Shiftable Cursor With up to 4 Different Colors Support of Progressive Scan and 100 Hz 4Bits RGB DACs On Chip Free Programmable Pixel Clock from 10 MHZ to 32MHz Pixel Clock Independent from CPU Clock Multinorm H V Display Synchronization in Master or Slave Mode Semiconductor Group 13 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Overview Acquisition Features Multistandard Digital Data Slicer Parallel Multi norm Slicing TTX VPS WSS CC G Four Different Framing Codes Available Data Caption only Limited by available Memory Programmable VBl buffer Full Channel Data Slicing Supported Fully Digital Signal Processing Noise Measurement and Controlled Noise Compensation Attenuation Measurement and Compensation Group Delay Measurement and Compensation Exact Decoding of Echo Disturbed Signals Ports 8 bit l O po
20. Default after reset MSB Length of line MSB s Bit 3 MSB 00 ACQFP8 LSB 7 6 LEOFLI LEOFLI LEOFLI LEOFLI LEOFLI LEOFLI LEOFLI LEOFLI 5 4 3 2 1 0 LEOFLI 7 0 Length of line LSB s Bit 0 LSB Semiconductor Group 52 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Slicer and Acquisition Line Parameters Default after reset 00 ACQLPO MSB LSB DINCR 15 DINCR 14 DINCR 13 DINCR 12 DINCR 11 DINCR 10 DINCR 9 DINCR 8 DINCR 15 8 Data PLL Frequency Select High Byte Specifies the frequency of the D PLL of slicer 1 This parameter is used to configure the D PLL output frequency according to the Service used DINCR f 215 33 33MHz faata MHz DINCR 6 9375 54559 5 7273 45041 5 0 39321 1 006993 7920 Default after reset 00 ACQLP1 MSB LSB DINCR 7 DINCR 6 DINCR 5 DINCR 4 DINCR 3 DINCR 2 DINCR 1 DINCR 0 DINCR 7 0 Data PLL Frequency Select Low Byte refer to ACQLPO Semiconductor Group 53 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Slicer and Acquisition Default after reset 00 ACQLP2 MSB LSB NORM 2 NORM 1 NORM 0 FCSEL 1 FCSEL 0 FC1ER VCR MATCH MATCH
21. In sync master mode of TVTpro delivers separate horizontal and vertical signals with the same flexibility in the programming of there periods as in sync slave mode 17 1 1 Screen Resolution The number of displayable pixels on the screen is defined by the pixel frequency which is independent from horizontal frequency the line period and number of lines within a field The screen is divided in three different regions Semiconductor Group 153 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System EVCR BVCR Vertical Blacklevel Clamping 20 E E Character Display Area 2 VLR 9 5 N vY camp e EHCR n cip b gt 4 BHCR Ui period HPR gt H Sync Figure 16 TVTpro s Display Timing Blacklevel Clamping Area During horizontal and vertical blacklevel clamping the black value RGB 000 is delivered on output side of TVTpro Inside this area the BLANK pin and COR pin are set to the same values which are defined as transparency for subCLUTO see also 18 4 7 This area is programmable in vertical direction in terms of lines and in horizontal direction in terms of 33 33 MHz clock cycles Border Area The size of this area is defined by the sync delay registers SDH and SDV and the size of the character display area The color and transparency of this area is defined by a color look
22. Modes 2 and 3 of the serial interface of the controller have a special provision for multiprocessor communication In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor communications is as follows When the master processor wants to transmit a block of data to one of the several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t addressed leave their SM2s set and go on about their business ignoring the coming data bytes SM2 has no effect in mode 0 and in mode 1 can be used to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received Semiconductor Group 119 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confide
23. BVCR 1 BVCR 0 Bit Function BVCR 9 0 Beginning of Vertical Clamp Phase Master and slave mode This register defines the beginning of the vertical clamp phase from the positive edge of the vertical sync impulse at normal polarity in count of lines If EVCR is smaller than BVCR than the clamp phase will appear during Vsync Reset 00 EVCR1 SFR Address MSB LSB EVCR 9 EVCR 8 Reset 04 EVCRO SFR Address MSB LSB EVCR 7 EVCR 6 EVCR 5 EVCR 4 EVCR 3 EVCR 2 EVCR 1 EVCR 0 Bit Function EVCR 9 0 End of Vertical Clamp Phase Master and slave mode This register defines the end of the vertical clamp phase from the positive edge of the vertical sync impulse at normal polarity in count of lines If EVCR is set to a value smaller than BVCR than the vertical blanking phase will last over the vertical blanking interval If EVCR is smaller than BVCR than the clamp phase will appear during Vsync Semiconductor Group 169 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Reset 00 MSB Sync System SNDCSTL SFR Address LSB HYS SND_V SND_V SND_V SND_H SND_H SND_H 1 0 2 1 0 Semiconductor Group 170 User s Manual July 99
24. CHAR 1 DRCiPOINTh LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 00h PIXELO PIXEL 1 PIXEL2 PIXEL3 PIXEL4 PIXEL5 PIXEL6 PIXEL 7 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 DRCiPONNTh LINE 0 LINE 0 LINE 0 LINE 0 LINE 1 LINE 1 LINE 1 LINE 1 01 8 PIXEL9 PIXEL 10 PIXEL 11 PIXELO PIXEL 1 PIXEL2 PIXEL3 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 DRCIPOINTh LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 02h PIXEL4 PIXEL5 PIXEL6 PIXEL7 PIXEL8 PIXEL9 PIXEL 10 PIXEL 11 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 CHAR 1 CHAR 1 CHAR 1 CHAR 1 1 LINE 10 LINE 10 LINE 10 LINE 10 10h PIXEL8 PIXEL9 PIXEL 10 PIXEL 11 BIT 0 BIT 0 BIT 0 BIT 0 CHAR 2 CHAR2 CHAR2 CHAR2 CHAR2 2 CHAR2 CHAR 2 DRCiPOINTh LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 11h PIXELO PIXEL1 PIXEL2 PIXEL3 PIXEL4 PIXEL5 PIXEL6 PIXEL7 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 2 bit DRCS characters address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 DRC2POINTh LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 00h PIXELO PIXELO PIXEL 1 PIXEL 1 PIXEL2 PIXEL2 PIXEL3 PIXEL 3 BIT 0 BIT 1 BIT 0 BIT
25. DD Central Special ctrl0 CSCRO No 00 Reserved Reserved P47 Alt VS OE OEP30 Pol DE Central Special ctrl 1 CSCR 1 No 00 IntSrc1 IntSrc0 ENARW A19 P4 4 M8 PA 1 A17 P40 DF Sandcastle SNDCSTL No 00 DSYNC HYS SNDV2 SNDV1 SND V0 SNDH2 SNDHO E0 Accumulator Yes 00 Miro 5 4 A2 Ei DSync control 1 SCR1 No AO Dsync BWCON RGBG1 RGBGO CORBL vsU3 VSU 2 VSU 1 VSU 0 E2 DSync control 0 SCRO No 00 DSync RGB D i RGB DO HP INT SNC ves MAST DSync V delay 1 SDV1 No DSync SDV 9 SDV 8 E4 DSync V delay 0 SDV0 20 Dsync SDV7 SDV 6 SDV 5 SDV 4 SDV 3 2 SDV 1 SDV 0 ES DSync H delay 1 SDH1 No 00 DSync SDH 11 SDH10 spH 9 SDH 8 E6 DSync H delay 0 SDHO 48 Dsync SDH7 SDH 6 SDH 5 SDH 4 SDH 3 SDH 2 SDH 1 SDH 0 E7 DSyncHclamp begin HCR1 Dsync EHCR7 EHCR6 5 EHCR4 EHCR2 EHCR1 EHCRO EB Port 4 P4 Yes EC Port P4 7 P46 P45 P44 P43 P42 PA 1 P4 0 E9 DSyncHclampend HCRO No Dsync BHCR7 BHCR6 BHCRS BHCR4 BHCR3 BHCR2 BHCR1 BHCRO EA DSync V clamp begin 1 BVCR1 No DSync BVCR9 DSync V clamp begin 0 BVCRO No 00 DSync BVCR7 BVCR6 BVCR4 BVCR3 BVCR2 BVCR 1 BVCRO EC DSync V clamp end 1 EVCR1 No 00 DSync EVCR 9 EVCR 8 ED DSync clamp end0 EVCRO No DSync EVCR7 EVCR6 EVCRS EVCR4 EVCR3 EVCR2 EVCR1 EVCRO DSync Vetical lin
26. Preliminary amp Confidential Microcontroller XRLdirect data Exclusive OR immediate data to direct CLRA Clear Accumulator Figure 10 Logical Operations Mnemonic Description Byte ANLA Rn AND register to Accumulator 1 ANLA direct AND direct byte to Accumulator 2 ANLA Ri AND indirect RAM to Accumulator 1 ANLA data AND immediate data to Accumulator 2 ANLdirect A AND Accumulator to direct byte 2 ANLdirect data AND immediate data to direct byte 3 ORLA Rn OR register to Accumulator 1 ORLA direct OR direct byte to Accumulator 2 ORLA Ri OR indirect RAM to Accumulator 1 ORLA data OR immediate data to Accumulator 2 ORLdirect A OR Accumulator to direct byte 2 ORLdirect data OR immediate data to direct byte 3 XRLA Rn Exclusive OR register to Accumulator 1 XRLA direct Exclusive OR direct byte to Accumulator 2 XRLA Ri Exclusive OR indirect RAM to Accumulator 1 XRLA data Exclusive OR immediate data to Accumulator 2 XRLdirect A Exclusive OR Accumulator to direct byte 2 3 1 1 1 1 1 1 1 CPLA Complement Accumulator RLA Rotate Accumulator left RLCA Rotate A left through the Carry flag RRA Rotate Accumulator right RRCA Rotate A right through Carry flag SWAPA Swap nibbles within the Accumulator Semiconductor Group 70 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Micr
27. Reserved PR1 1 Divides input further by 8 0 Not divided by 8 First 1 Indicates first event 0 indicates not first event Start 1 Controller sets this bit enter the SSU mode and to indicate it is Semiconductor Group expecting a new telegram When an event occurs caputr unit sets First bit Upon next event hardware resets the first bit and interrupt is generated based on Min cap register 0 Not SSU mode 129 User s Manual July 99 Infineon Preliminary amp Confidential Capture reload timer Default after reset 00 CSCR1 SFR Address DE MSB LSB IntSrc1 IntSrcO ENARW A19 P4 4 A18 P4 1 A17 P4 0 IntSrcO 0 Port 3 3 is the source of the interrupt 1 SSU is the source of interrupt Application note Use with SEL 1 IntSrc1 0 Port 3 2 is the source of the interrupt 1 SSU is the source of interrupt Application note Use with SEL 0 Not used Not used ENARW See SFR Overview for description of this bit 19 P4 4 See SFR Overview for description of this bit A18 P4 1 See SFR Overview for description of this bit A17 P4 0 Semiconductor Group See SFR Overview for description of this bit 130 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Capture reload timer 13 6 Time resolution Max pulse F Fctr Fctr Time Res SD Mz PRE PR MHz nsec width msec 0 0 F 8 4 17 240 15 7
28. WDT timer low byte low No 00 WDT 7 WDTlow 6 WDTlow 5 WDTlow 4 3 WDTlow 2 WDTlow 1 WDTlow 0 B5 WDT timer high byte high No 00 WDT WDThi WDThi6 WDThi5 WDThi 4 WDThi3 WDThi2 WOThii B6 No 00 87 CRT reload low byte CRT rell No 00 CRT RelL 7 RelL 6 RelL 5 RelL 4 RelL 3 RelL 2 Rel 1 RelL 0 B8 Interrupt priority 0 IP0 Yes 00 Micro 65 1 G4P1 G3P1 G2P1 G0P1 B9 reload high byte CRT_relh 0 CRT RelH 7 RelH 6 RelH 5 RelH 4 RelH 3 RelH 2 RelH 1 0 BA capture low byte CRT No 00 CRT CapL7 CapLG CapL5 CapL3 Capl2 CapL 1 CapL 0 BB capture high byte caph No 00 CRT CapH 7 CapH 6 CapH 5 CapH4 CapH3 CapH2 CapHi CapH 0 BC mincapturelow CRT mincapl No 00 CRT MinL 7 MinL 6 MinL 5 MinL 4 MinL 3 MinL 2 MinL 1 MinL 0 BD CRT min capture high CRT mincaph 00 CRT MinH 7 MinH 6 MinH 5 MinH 4 MinH MinH 2 MinH 1 MinH 0 BE CRT control 0 CRTCONO 00 CRT ov PR PLG REL RUN RISE FALL SEL BF CRT control 1 CRTCON1 00 CRT PRI First Start co Central int service CISRO Yes 00 Interrupt L24 ADC WTmr AVS DVS PWimr AHS DHS PWM 8bit compare 0 comp8 0 No 00 PWM PC807 PCB06 PC805 PCB04 803 PCB02 80 1 PC80 0 C2 PWM 8bit compare 1 comp8 1 No 00 PWM PC8i 7 PC8i Pess PCBi4 PCBi3 PCBi2 PCBi1 PC81 0
29. XCHA Rn Exchange register with Accumulator XCHA direct Exchange direct byte with Accumulator XCHA Ri Exchange indirect RAM with Accumulator XCHDA Ri Exchange low order digital indirect RAM with A not applicable Semiconductor Group 71 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 12 Boolean Variable Manipulation Mnemonic Description Byte CLR C Clear Carry flag 1 CLR bit Clear direct bit 2 SETB C Set Carry flag 1 SETB bit Set direct bit 2 CPL C Complement Carry flag 1 CPL bit Complement direct bit 2 ANL bit AND direct bit to Carry flag 2 ANL C lbit AND complement of direct bit to Carry 2 ORL OR direct bit to Carry flag 2 ORL bit OR complement of direct bit to Carry 2 MOV bit Move direct bit to Carry flag 2 MOV bit C Move Carry flag to direct bit 2 Semiconductor Group 72 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Microcontroller Figure 13 Program and Machine Control Operations Mnemonic Description Byte ACALL addr 11 Absolute subroutine call 2 LCALL addr 16 Long subroutine call 3 RET Return from subroutine 1 RETI Return from interrupt 1 AJMP addr 11 Absolute jump 2 LJMP addr 16 Long jump 3 SJMP Short jump relative addr 2 JMP A DPTR Jump
30. 0Ous 122 8 us 480ns 4 8 us Of Horizontal Clamp Phase User has to take car for a setting of PFR and SDH so that SDH PFR is greater than 2us 17 1 2 Sync Interrupts The sync unit delivers interrupts Horizontal and vertical interrupt to the controller to support the recognition of the frequency of an external sync source These interrupts are related to the positive edge of the non delayed horizontal and vertical impulses which can be seen at pins HSYNC and VSYNC Semiconductor Group 155 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System 17 2 Register Description Reset 80 SCR1 SFR Address E1 MSB LSB BW _ RGB _ RGB_ VSU 3 VSU 2 VSU 1 VSU 0 CON G 1 Reset 00 SCRO SFR Address E2 MSB LSB RGB D RGB D HP VP INT SNC VCS MAST 1 0 Bit Function MAST Master Slave Mode This bit defines the configuration of the sync system master or slave mode and also the direction input output of the V H pins 0 Slave mode H V pins are configured as inputs 1 Master mode H V pins are configured as outputs Note Switching from slave to master mode resets the internal H V counters so that the phase shift during the switch can be minimized In slave mode registers VLR and HPR are without any use vcs Video Composite Sync VCS defines t
31. 1 port pin is analog input the digital value is always 0 149 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Analog Digital Converter CADC ADWULE 4 Defines threshold level for wake up A special wake up unit has been included to allow a system walk up as soon as the analog input signal on pin CINO drops below a predefined level ADWULE defines this level ADWULE 0 threshold level corresponds to fullscale 4LSB ADWULE 1 threshold level corresponds to fullscale 16LSB Default after reset 00 CISRO bit addressable SFR Address C0 MSB LSB L24 ADC WTmr AVS DVS PWtmr AHS DHS L24 refer to Interrupts ADC 1 Analog to digital conversion complete source bit set by hardware 0 Analog to digital conversion complete source bit must be reset by software WTmr refer to Interrupts AVS refer to Interrupts DVS refer to Interrupts PWtmr refer to Interrupts AHS refer to Interrupts DHS refer to Interrupts Semiconductor Group 150 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Analog Digital Converter CADC Default after reset 00 CISR1 bit addresseble SFR Address C8 MSB LSB CC ADW IEX1 IEX0 CC refer to Interrupts ADW 1 ADC wake up interrupt source bit set by hardware 0 ADC wake up interrupt source bit must be reset by software
32. AHS See Chpater interrupt DHS 1 Display horizental sync interrupt source bit set by hardware 0 Display horizental sync interrupt source bit must be reset by software DHS is used as a interface from H input pin to software interrupt routines These interrupt routines can be used for detection of the frequency of a external sync source Is set by the HW and must be resetted by the SW DVS is usedas a interface from V input pin to software interrupt routines These interrupt routines can be used for detection of the frequency of a external sync source Is set by the HW and must be resetted by the SW Semiconductor Group User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Sync System Reset 02 VLR1 SFR Address EE MSB LSB ODD VSU2 3 VSU2 2 VSU2 1 VSU2 0 VLR 9 VLR 8 Reset 71 VLRO SFR Address EF MSB LSB VLR 7 VLR 6 VLR 5 VLR 4 VLR 3 VLR 2 VLR 1 VLR 0 Semiconductor Group 160 User s Manual July 99 e DA Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Semiconductor Group 161 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Bit Function ODD EV ODD EVEN detection Slave mode only Used as a interface from the hardware odd even field detection to
33. CLKDIV 1 0 ALENGTH 2 0 Semiconductor Group The slicing level filter needs to find the DC value of the CVBS during CRI In order to do this it should suppress at least the CRI frequency As different services use different data frequencies the CRI frequency will be different as well Therefore the filter characteristic needs to be shifted This can be done by using different clocks for the filter The filter itself shows sufficient suppression for frequencies between 0 0757 SLc 0 13 SL oi SLcuk is the actual filter clock and corresponds to slicer 1 CLKDIV Slo 000 1 001 1 2 f 010 1 3 f 011 1 4 100 1 5 101 1 6 110 17 111 1 8 f Note f 33 33MHz If noise has been detected or if NOISEON 1 the output of the slicing level filter is further averaged by means of an accumulation arithmetic averaging ALENGTH specifies the number of slicing level filter output values used for averaging The accumulation clock depends on CLKDIV ALENGTH Number of Slicing Level Output Values used for Averaging 00 2 01 4 10 8 11 16 55 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition MLENGTH 2 0 For noise suppression reasons a median filter has been introduced after the actual data separation because of over sampling successive samples could be averaged Therefore an odd number of sliced successive samples is taken and if the majority ar
34. Horizontal Slicing Level set to 1 83V These are nominal values They may also differ with supply voltage HYS Definition of Hysteresis Slave mode Sanacastle input Defines the voltage range for the Hysteresis 0 Hysteresis set to 0 2V 1 Hysteresis set to 0 4V Semiconductor Group 171 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display 18 Display The display is based on the requirements for a Level 1 5 Teletext and powerful additional enhanced OSD features The display circuit reads the contents and attribute settings of the display memory and generates the RGB data for a TV backend signal processing unit The display can be synchronized to external H V sync signals slave mode or can generate the synchronisation signals by itself master mode The display can be synchronized to 50Hz as well as to 60 Hz systems Interlaced display is supported for interlaced sync sources and non interlaced ones 18 1 Display Features Teletext Level 1 5 feature set ROM Character Set to Support all European Languages in Parallel Mosaic Graphic Character Set Parallel Display Attributes Single Double Width Height of Characters Variable Flash Rate Programmable Screen Size 25 Rows x 33 64 Columns Flexible Character Matrixes HxV 12 x 9 16 Up to 256 Dynamical Redefinable Characters in standard mode 1024 Dynamical Redefinable Characters in Enhanced Mode
35. IDLS Idle Start Bit 0 14 Mode not started 1 ldle Mode started The instruction that sets this bit is the last instruction before entering idle mode Additionally this bit is protected by a delay cycle Idle mode is entered if and only if bit IDLE was set by the previous instruction Once set this bit is cleared by hardware and always reads out a 0 The CADC is switched off but the CADC Wake Up Unit is active GF1 refer to UART GFO refer to UART SD refer to power saving modes PDE refer to power saving modes IDLE refer to power saving modes Semiconductor Group 152 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System 17 Sync System 17 1 General Description The display sync system is completely independent from the acquisition sync system CVBS timing and can either work as a sync master or as a sync slave system Talking about H V Syncs in this chapter and in chapter display generator always refers to display related H V Syncs and never to CVBS related sync timing In sync slave mode TVTpro receives the synchronisation information from two independent pins which deliver separate horizontal and vertical signals or a sandcastle impulse from which the horizontal and vertical sync signals are seperated internally Due to the not line locked pixel clock generation refer to chapter Clock Processing it can process any possible horizontal and vertical sync frequency
36. IEX1 refer to Interrupts iEXO refer to Interrupts Default after reset 00 PSAVE bit addressable SFR Address D8 MSB LSB CADC WAKUP SLI ACQ DISP PERI Not used CADC CADC 0 Power save Mode not started 1 Power save Mode started In Power save mode CADC is disabled but the CADC Wake Up Unit is active WAKUP Wake up of CADC 0 Power save Mode not started 1 Power save Mode started In Power save mode ADC wake up unit of CADC is disabled Note that Power save mode of wake up unit is only useful in saving power when CADC bit is set SLI ACQ refer to power saving modes DISP refer to power saving modes Semiconductor Group 151 User s Manual July 99 Infineon technologies Preliminary amp Confidential SDA 55xx Analog Digital Converter CADC PERI refer to power saving modes Default after reset 00h PCON SFR Address 874 MSB LSB SMOD PDS IDLS SD GF1 GFO PDE IDLE SMOD refer to UART PDS Power Down Start Bit 0 Power Down Mode not started 1 Power Down Mode started The instruction that sets this bit is the last instruction before entering power down mode Additionally this bit is protected by a delay cycle Power down mode is entered if and only if bit PDE was set by the previous instruction Once set this bit is cleared by hardware and always reads out a 0 The CADC is completely switched off no wake up possible
37. RO SP Semiconductor Group 63 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Microcontroller Immediate Addressing Program Memory Base Register plus Index Register Indirect Addressing Program Memory DPTR A QPC A 6 1 31 Register Addressing Register addressing accesses the eight working registers RO R7 of the selected register bank The PSW register flags RS1 and RS0 determine which register bank is enabled The least significant three bits of the instruction opcode indicate which register is to be used ACC B DPTR and CY the Boolean processor accumulator can also be addressed as registers 6 1 3 2 Direct Addressing Direct byte addressing specifies an on chip RAM location only low part or a special function register Direct addressing is the only method of accessing the special function registers An additional byte is appended to the instruction opcode to provide the memory location address The highest order bit of this byte selects one of two groups of addresses values between 00 7 access internal RAM locations while values between 80 OFF access one of the special function registers 6 1 3 3 Register indirect Addressing Register indirect addressing uses the contents of either RO or R1 in the selected register bank as a pointer to locations in the 256 bytes of internal RAM Note that the special function registers are not accessible by th
38. Row No 0 Row No 0 E po Row No 13 Row No 11 Row No 14 Row No 12 Row No 23 R Row No 24 ow No 24 1 X X Full Screen Double Height Rows 12 23 are displayed in double height Row 0 is settled on top of display in normal height Memory organization Display Appearance Row No 0 Row No 0 ES p Row No 1 Row No 11 Row No 2 Row No 12 Row No 23 R Row No 24 ow No 12 see also 1 4 Global Display Word GDW Semiconductor Group 191 User s Manual July 99 Infineon technologies Preliminary amp Confidential 18 4 5 SDA 55xx Display Flash Rate Control This attribute is used to control the flash rate for the full screen All the characters on the screen for which flash is enabled are flashing with same frequency and in same phase FLRATE1 FLRATE0 Description 0 0 Slow flash rate The flash rate is derived from display V pulse For 50Hz systems Flash rate is approximately 0 5 Hz Duty cycle is approximately 50 Medium flash rate The flash rate is derived from the V pulse For 50Hz systems Flash rate is approximately 1 0 Hz Duty cycle is approximately 5096 Fast flash rate The flash rate is derived from the V pulse For 50Hz systems Flash rate is approximately 2 0 Hz Duty cycle is approximately 5096 see also 18 4 Global Display Word GDW Semiconductor Group 192 User s Manual July 99 Infineon SDA
39. The data start recognition matches the incoming data with a sequence of three data bits MATCH decides whether this matching sequence is alternating or steady 0 Alternating a 010 or 101 triggers data start 1 Steady 111 triggers data start VCR This bit is used to change the behavior of the D PLL corresponds to slicer 1 0 D PLL tuning is stopped after CRI 1 D PLL is tuned throughout the line If this bit is 1 the check is performed with one bit error tolerance 0 noerror tolerance for FC1 check 1 one bit error tolerance for FC1 check FCSEL 1 0 There are three different framing codes which can be used for each field The framing code used for the actual line is selected with FCSEL corresponds to slicer 1 FCSEL FC 00 FC1 01 FC2 10 11 FC check NORM 2 0 Most timing signals are closely related to the actual data service Semiconductor Group used Therefore 3 bits are reserved to specify the timing for the service used in the actual line corresponds to slicer 1 NORM Service 000 TXT 001 NABTS 010 VPS 011 WSS 100 CC 101 G 110 reserved 111 no data service 54 User s Manual July 99 e DA 55xx Infineon technologies Preliminary amp Confidential Slicer and Acquisition Default after reset 00 ACQLP3 MSB LSB MLENGTH MLENGTH MLENGTH ALENGTH ALENGTH CLKDIV CLKDIV CLKDIV 2 1 0 1 0 2 1 0
40. The stack depth is limited only by the available internal data RAM thanks to an 8 bit re locatable stack pointer The stack is used for storing the program counter during subroutine calls and may also be used for passing parameters Any byte of internal data RAM or special function registers accessible through direct addressing can be pushed popped By default Stack Pointer always has a reset value of 07 10 2 2 Extended Data RAM XRAM An additional on chip RAM space called XRAM extends the internal RAM capacity Up to 16 Kilobytes of XRAM are accessed by MOVX DPTR XRAM is located in the upper area of the 64K address space 1 Kbyte of the XRAM called VBI Buffer is reserved for storing teletext data 1KByte of address space can be allocated for CPU work space Three Kilobyte of RAM is reserved as Display RAM Rest of the RAM can be configured between Teletext page memory and DRCS Dynamically Redefinable Character Set memory Extended Data Memory address Mapping XRAM is mapped in the address space of C000 to FFFF 16 KBytes are implemented on Chip the address space of the 16K block is decoded starting from C000h Note that this decoding is done independent of the memory banking That means that in all 16 banks of 64K upper 16K address space is reserved for internal Extended data memory This decoding method has an advantage while copying data backand forth from on chip RAMand off chip RAM there is no need to switch the memory ba
41. 0 1 0 Vertical shift of 2 0 0 1 1 Vertical shift of 3 1 1 1 0 Vertical shift of 14 1 1 Vertical shift of 15 see also 18 4 Global Display Word GDW The character position of the cursor is determined by the following parameters POS POS POS POS POS POS Description HOR5 4 HOR3 HOR2 HOR1 HORO 0 0 0 0 0 Horizontal character column 0 0 0 0 0 0 Horizontal character column 1 1 1 1 1 1 Horizontal character column 62 1 1 1 1 1 Horizontal character column 63 see also 18 4 Global Display Word GDW POS POS POS POS POS Description VERA VER3 VER2 VER1 VERO 0 0 0 0 0 Vertical character row 0 0 0 0 0 Vertical character row 1 0 0 0 1 0 Vertical character row 2 0 0 0 1 1 Vertical character row 3 1 1 1 1 0 Vertical character row 30 Semiconductor Group 187 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display POS POS POS POS POS Description VER4 VER3 VER2 VER1 VER0 1 1 1 1 1 Vertical character row 31 see also 18 4 Global Display Word GDW Character position and pixel position have to be changed in parallel Otherwise it may appear that the character position already has been changed to a new position but the pixel position is still set to the former value This may cause a jumping cursor To avoid this jumping cursor there is a EN LD GDW enable
42. 0 2 5 V ADC Resolution RES 8 BIT binary Output by Underflow 0 Output by Overflow 255 Bandwidth 10 5 kHz Sampling Time ts 2 us Sampling Frequency p 21 kHz Maximum Input Source 100 Resistance Pin capacitance Gs 40 pF Analog Ports Reset Pin capacitance C pF Reset In Pull Up Resistor Ras KQ Input High Voltage V 20 4 Timings Vsync Ton gt Hsync Line i 1 Figure 24 H V Sync Timing Sync master mode Semiconductor Group 221 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Electrical Characteristics vcs Figure 25 VCS Timing Sync master mode Semiconductor Group 222 User s Manual July 99 ee _ DA 55xx Infineon technologies Preliminary amp Confidential Electrical Characteristics Figure 26 Application Diagram Semiconductor Group 223 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential 20 5 Package Outlines Electrical Characteristics P SDIP 52 P MQFP64 Plastic Metric Quad Flat Package GPM05247 Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Semiconductor Group 224 Dimensions in mm User s Manual July 99 e SDA 55xx Infineon technologies Preliminary amp Confidential Glos
43. 0 BIT 1 DI characters address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR1 CHAR 1 CHAR 1 CHAR 1 DRC4POINTh LINEO LINEO LINEO LINEO LINEO LINEO LINEO LINE 0 00h PIXELO PIXELO PIXELO PIXELO PIXEL 1 PIXEL 1 PIXEL 1 PIXEL 1 BIT 0 BIT 1 BIT2 BIT3 BIT 0 BIT 1 BIT 2 BIT CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 DRC4POINTh LINEO LINEO LINEO LINE 0 LINE 1 LINE 1 LINE 1 LINE 1 01h PIXEL 2 PIXEL2 PIXEL2 PIXEL2 PIXEL3 PIXEL3 PIXEL3 PIXEL3 BIT 0 BIT 1 BIT 2 BIT 3 BIT 0 BIT 1 BIT 2 BIT 3 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR1 CHAR 1 CHAR 1 CHAR 1 DRC4POINTh LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 LINE 1 02h PIXEL4 PIXEL4 PIXEL4 PIXEL4 5 5 PIXEL5 PIXEL 5 BIT 0 BIT 1 BIT2 BIT 3 BIT 0 BIT 1 BIT 2 BIT 3 CHAR 1 CHAR 1 HAR 1 CHAR 1 CHAR1 CHAR 1 CHAR 1 CHAR 1 preapointh LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 41h PIXEL 10 PIXEL 10 PIXEL 10 PIXEL 10 PIXEL 11 PIXEL 11 PIXEL 11 PIXEL 11 BIT 0 BIT 1 BIT2 BIT 3 BIT 0 BIT 1 BIT 2 BIT 3 CHAR 2 CHAR2 CHAR2 CHAR2 CHAR2 CHAR2 CHAR2 CHAR 2 prcapointh LINEO LINEO LINEO LINE 0 LINEO LINEO LINEO LINE 0 425 PIXELO PIXELO PIXELO PIXELO PIXEL1 PIXEL 1 PIXEL 1 PIXEL 1 BIT 0 BIT 1 BIT 2 BIT 3 BIT 0 BIT 1 BIT 2 BIT 3 Semiconductor Group 207 User s Manual July
44. 1 BIT 0 BIT 1 BIT 0 BIT 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 DRC2POINTh LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 LINE 0 01h PIXEL 4 PIXEL4 PIXEL5 PIXEL5 PIXEL6 PIXEL6 PIXEL7 PIXEL7 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 Semiconductor Group 206 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Display address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR1 CHAR 1 CHAR 1 CHAR 1 DRc2POINTh LINEO LINEO LINEO LINEO LINEO LINEO LINEO LINE 0 02h PIXEL8 PIXEL8 PIXEL9 PIXEL9 PIXEL 10 PIXEL 10 PIXEL 11 PIXEL 11 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 DRC2POINTh LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 LINE 10 20h PIXEL8 PIXEL8 PIXEL9 PIXEL9 PIXEL 10 PIXEL 10 PIXEL 11 PIXEL 11 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 CHAR2 CHAR2 CHAR2 CHAR2 CHAR2 CHAR2 CHAR2 CHAR 2 2 LINEO LINEO LINEO LINE 0 LINEO LINEO LINE 0 LINE 0 11h PIXELO PIXELO PIXEL1 PIXEL1 PIXEL2 PIXEL2 PIXEL3 PIXEL 3 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT
45. 12 1 4 Timer Counter Control Register Default after reset 00 TCON SFR Address 88 MSB LSB TF1 TR1 TFO TRO IE1 IT1 IEO ITO TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter on off TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TRO Timer 0 run control bit Set cleared by software to turn timer counter on off IE1 Interrupt 1 edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT1 Interrupt 1 type control bit Set cleared by software to specify edge low level triggered external interrupts IEO Interrupt 0 edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed ITO Interrupt 0 type control bit Set cleared by software to specify edge Semiconductor Group low level triggered external interrupts 124 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Capture reload timer 13 Capture reload timer Capture control timer is a 16 bit up counter with special features suited for easier infra red decoding by measuring the time interval between two successive trigger events Trigger events can be positive negative or both edges of a digital input signal Port
46. 13 3 6 Normal Capture mode Normal capture mode is started by setting the RUN bit 0 gt 1 and PLG 0 start 0 Setting RUN bit will reload the counter with reload value and reset the overflow bit and counter will start to count Upon event on the selected port pin contents of the counter are copied to the capture registers CRT caph and CRT capl Semiconductor Group 126 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Capture reload timer In capture mode if REL bit is set counter is automatically reloaded upon event with the reload value and starts to count If however REL bit is not set then counter continues to count from the current value OV bit is not effected by the capture event Note 1 Min cap register has no functionality in this mode Note 2 Interrupt would be generated from CRT however it will only be registered in the int source register if intsrc bits in the CSCR1are appropriately set It is not required to use the CRT generated interrupt in this mode Direct pin interrupt can be used 13 3 7 Polling mode Polling mode is started by setting the PLG bit PLG 1 START bit is in don t care for this mode Setting RUN bit will reload the counter with reload value and reset the overflow bit and start the counting In the timer polling mode capture register mirrors the current timer value note that in this mode any event at selected port pin is ignored Upon overflow
47. 2 Interrupt Sources 83 7 3 OVENVIEW Sc beady pret RR oe es ghee GG aee ek ate pee 84 7 4 Enabling intert pts gt Uu u y ass sansun iris ade eee ed eee ER 85 7 4 1 Interrupt Enable registers IEO IE1 IE2 1 85 7 5 Interrupt source 87 7 6 Interrupt REX oo vee ee 90 7 6 1 Interrupt Priority registers 91 7 7 Interrupt Vectors RR RR RR ed samasaa E Rund 92 7 8 Interrupt and memory extension 93 7 9 Interrupt Handling 1 1 93 7 10 Interrupt Latency ses casaria Rom A LR Rs 94 7 11 Interrupt Flag Clear 94 7 12 Interrupt returni 1i sigma 94 7 13 Interrupt Nestihg 94 7 14 External InterruptS dh eae siapa s dad x ror 95 7 15 Extension of Standard 8051 Interrupt Logic 95 7 16 Interrupt Task Function 22 2 tee 97 8 Power Saving modes 99 8 1 Power Save mode registers 99 8 2 m 103 8 3 Power down
48. 55xx technologies Preliminary amp Confidential Display 18 4 6 Transparency of Boxes For characters which are using subCLUTO the transparency which is defined for the whole CLUT see also 18 4 7 can be overruled for foreground or background pixels There are two different definitions for two box areas to define this overruling Which of these two box transparencies is used is selected character individual inside the bit BOX in CDW character display word see also 18 3 Transparency definition for characters for BOXO The cursor see also 18 4 2 is not affected by these bits GLBT2_BOX0 GLBT1 BOXO GLBTO BOXO Description X 0 0 Box transparency is disabled for BOXO For all pixels the global defined transparency of subCLUTO is used 0 0 1 Box transparency is enabled for BOXO for following pixels Foreground pixels of ROM characters 0 1 0 Box transparency is enabled for BOXO for following pixels Foreground pixels of 1 bit DRCS characters 0 1 1 Box transparency is enabled for BOXO for following pixels Foreground pixels of ROM characters Foreground pixels of 1 bit DRCS characters 1 0 1 Box transparency is enabled for BOXO for following pixels Background pixels of ROM characters 1 1 0 Box transparency is enabled for BOXO for following pixels Background pixels of 1 bit DRCS characters 1 1 1 Box transparency is enabled for BOXO for following pixels Background pixels of ROM characters Ba
49. 8 bit index register Sixteen bit jumps and calls permit branching to any location in the memory address space The processor has five methods for addressing source operands register direct register indirect immediate and base register plus index register indirect addressing The first three methods can be used for addressing destination operands Most instructions have a destination source field that specifies the data type addressing methods and operands involved For operations other than moves the destination operand is also a source operand Registers in the four 8 register banks can be accessed through register direct or register indirect addressing the lower 128 bytes of internal data RAM through direct or register indirect addressing the upper 128 bytes of internal data RAM through register indirect addressing and the special function registers through direct addressing Look up tables resident in program memory can be accessed through base register plus index register indirect addressing Semiconductor Group 59 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Microcontroller 6 1 1 CPU Hardware 6 1 1 1 Instruction Decoder Each program instruction is decoded by the instruction decoder This unit generates the internal signals that control the functions of each unit within the CPU section These signals control the sources and destination of data as well as the fu
50. 99 Infineon technologies SDA 55xx Preliminary amp Confidential 18 6 Memory Organization Display The memory organization concept of the OSD is based on a flexible pointer concept All display memory registers reside in the internal XRAM only Special Function Registers internal XRAM Display Memory Cursor matrix GDW CLUT GDWCURPOINTh CLUTPOINTh DISPOINTh 1 bit DRCS matrices 4 bit DRCS matrices 2 bit DRCS matrices DRC4POINTh DRC2POINTh DRC1POINTh POINTARRAYO User Data POINTARRAY1 VBI Figure 23 Semiconductor Group Memory Organization of On Screen Display 208 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display There are 4 bytes of SFR registers which are pointing to two pointer arrays inside the XRAM SFR address name function XXh POINTARRAYO Pointer to pointer array 0 XXh 02h POINTARRAY 1 Pointer to pointer array 1 These 2 SFR pointers are used to point to 2 x 3 other pointers These 6 pointers are pointing to the start address of the following memory areas Start address of character display area memory Start address of CLUT Start address of 1 bit DRCS characters matrixes Start address of 2 bit DRCS characters matrixes Start address of 4 bit DRCS characters mat
51. Driving a low level during the input phase freezes the real time relevant internal peripherals such as timers and interrupt controller Available MQFP100 Type Additional reference Opcode Fetch Emulation control line A high level driven by the controller phase indicates the beginning of a new instruction Available MQFP100 Type Additional reference l Enable Emulation Only if this pin is set to zero externally STOP and OCF are operational ENE has an internal pull up resistor which switches automatically to non emulation mode if ENE is not connected Semiconductor Group 20 User s Manual July 99 e SDA 55xx Infineon technologies Preliminary amp Confidential Package and Pinning Symbol Function RD Type Additional reference Available 100 PLCC84 Control output indicates a read access to the internal XRAM can be used for latching data from the data bus into an externa data RAM by a MOVX instruction This signal is also available as 4 2 WR Type Additional reference Available 100 PLCC84 Control output indicates a write access to the internal XRAM can be used as a write strobe for writing data into an external data RAM by a MOVX instruction This signal is also available as P4 3 ALE Type Additional reference Available MQFP100 Address Latch Enable PSEN Type Additional reference Available 100 PLCC
52. FC1 3 FC1 2 FC1 1 FC1 0 FC1 7 0 Framing code 1 Bit 7 First received bit of FC Bit 0 Last received bit of FC Default after reset 00 ACQFP5 MSB LSB AGDON AFRON ANOON GDPON GDNON FREON NOION FULL FULL 0 Full channel mode off 1 Full channel mode on Note Don t forget to reserve enough memory for the VBI buffer and to initialized the appropriate line parameters NOION 0 Noise compensation depends on ANOON 1 Noise compensation is always on FREON 0 Frequency depending attenuation compensation depends on AFRON 1 Frequency depending attenuation compensation is always on GDNON 0 Group delay compensation depends on AGDON 1 Negative group delay compensation is always on GDPON 0 Group delay compensation depends on AGDON 1 Positive group delay compensation is always on ANOON Automatic noise compensation Compensation Off Compensation On Automatic measurement depending compensation 0 1 Semiconductor Group 50 User s Manual July 99 i SDA 55xx Infineon technologies Preliminary amp Confidential Slicer and Acquisition AFRON Automatic frequency depending attenuation 0 Compensation Off 1 Compensation On Automatic measurement depending compensation AGDON Automatic group delay 0 Compensation Off 1 Compensation On Automatic Measurement Depending Compensation Default after reset 00 ACQFP6 MSB LSB CG
53. H V Synchronization 41 Acquisition Interface 42 FC Check sei io Rp Bede Rede deena Te Tea 42 Intertupts deo Roe anc oak Freed 43 VBI Buffer and Memory Organization 43 Register Description 46 RAM Registers 48 Recommended Parameter Settings 57 Microcontrolleir idiot nx RR RE 59 Arehitect re eee hid p Rode 59 CPU Hardware 60 CPU TIMING acsi eee 63 Addressing Modes 63 Ports l O Pins 1 65 Instruction Get egere eee ehe DARE ed Reate ins 68 Notes on Data Addressing Modes 68 Notes on Program Addressing Modes 68 Instruction Set Description 69 Semiconductor Group 3 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential 6 3 4 Instruction Opcodes in Hexadecimal Order 74 7 Interrupls uoo PEE EINE BP SURE 83 iA Interrupt System 2 83 7
54. High DPH No Micro DPH7 DPH 6 DPH 5 DPH 4 DPH 3 DPH 2 DPH 1 DPH 0 84 Data Pointer Select DPSEL No Micro DPSEL2 DPSEL1 DPSELO 85 No 00 86 No 00 87 Power control PCON No 00 Micro SMOD PDS IDLS SD GF0 PDE IDLE 88 Tmr Ctr control TCON Yes 00 Micro TF1 TRI TFO TRO IE1 m E0 89 Tmr Ctr Mode Ctr TMOD No 00 Micro GATE1 Mo 1 GATEO CINTO Mi Tmr Ctr Lowbyte TLO No 00 Miro TL07 6 TL05 TL04 2 TLO 1 0 Tmr Ctr1 Low byte TL1 No Miro 117 5 T4 2 Tu 1 TL10 sc Tmr Ctr 0 High byte THO No 00 Micro THO 7 THO 6 THOS 4 TH0 THO 2 THO 1 THO 0 80 Tmr Ctr 1 High byte TH1 No 00 Micro THI6 THi 5 THA 3 TH 2 TH 1 0 8E No 8F N 90 Port 1 P1 Yes FF Port P17 P16 P15 Pia P13 P12 Pit P10 91 No 92 No 93 No 9 Memory Ext Reg 1 MEX1 No 00 Micro CBI9 CB18 CB16 NB19 NB18 NB17 NB16 95 MemoryExtReg2 MEX2 No 00 Micro MM MB18 MB17 MB16 1819 1818 1817 1816 96 MemoryExtReg3 MEX3 No Micro MB19 UB3 19 MXM MX18 MX17 16 97 Memory Ext stack MEXSP No 00 Micro SP6 5 5 5 4 SP3 SP2 SP1 SP0 98 Serial control register SCON Yes 00 UART 5 5 1 5 2 TB8 RB8 n RI 99 Serial Data Buffer SBUF No 00 UART 07 06 05 03 02 Di 00 9 No 9B No No 00 9D No 00 9E No 00 oF No 00
55. INTO and INT1 are either level or edge triggered depending on bits in TCON and IRCON Other external interrupts are level sensitive and active high Any edge triggering will need to be taken care of by individual peripherals INTXO and INTX1 can be programed to be either negative or positive edge trigerred The analog digital converter interrupt is generated on completion of the analog digital conversion Semiconductor Group 83 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts 7 3 Overview A simple overview of the interrupt handling is shown in Figure below Highest Priority Interrrupt Request Priority Interrrupt Request Interrrupt Request Interrrupt Request IENO 7 Note x 0 to 5 Semiconductor Group 84 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Interrupts 7 4 Enabling interrupts Interrupts are enabled through a set of Interrupt Enable registers IEO IE1 IE2 and Bits 0 to 5 of the Interrupt Enable registers each individually enable disable a particular interrupt source Overall control is provided by bit 7 of IEO EAL When EAL is set to 0 all interrupts are disabled when EAL is set to 1 interrupts are individually enabled or disabled through the other bits of the Interrupt Enable Registers EAL may however be overridden by the DISINT signal which provides a gl
56. Manual July 99 e DA 55xx Infineon SDA 55 technologies Preliminary amp Confidential Watchdog Timer 15 6 The period between refreshing the watchdog timer and the next overflow can be determined by the following formula Time period Pwor 21109070 x x 216 WDT Rel X 2 Fworl Based on 33 33 Mhz system clock minimum time period and maximum time period are as defined below cem WDT In WDT Rel Pwor Min 33 33 MHz 0 FF 184 3 micro sec Max 33 33 Mhz 1 00 3 02 sec Semiconductor Group 143 User s Manual July 99 e _ SDA 55xx Infineon o o o c o o Watchdog Timer Preliminary amp Confidential 15 7 Block Diagram Lo o sm won rion miu asom 9 i3ulOM LOM Ju 10M ur 10M 5 10M 10M Jed LOM User s Manual July 99 144 Semiconductor Group Infineon SDA 55xx technologies Preliminary amp Confidential Watchdog Timer 15 8 WDT as general purpose timer WDT counter can be used as a general purpose timer in timer mode and the associated load register can be used either as load register or independent scratch register for the programmer This is achieved by setting Tmr bit WDT Tmr bit can only be set before starting the WDT timer Once watchdog
57. OV bit is set Note 1 Interrupts are not generated as events are not recognized 13 38 Capture mode with spike suppression at the start of a telegram This mode is specially been implemented to prevent false interrupt from being generated specially in idle mode while waiting for a new infra red telegram This mode is entered by setting the START bit PLG 20 Software sets Start bit to indicate it is expecting a new telegram Setting RUN bit will reload the counter with reload value and reset the overflow bit and start the counting 13 3 9 First event On occurrence of capture event counter value is captured and comparator then sets the First bit Interrupt is suppressed OV bit is reset and counter reloads the reload value regardless of the status of REL bit and starts counting again 13 3 10 Second event On occurrence of second capture event counter value is captured and interrupt is triggered if the capture value exceeds the value in the Min_Cap register and the OV bit is not set First bit is reset Counter will now continue in the normal capture mode Software may reset the START bit if the capture value is a valid pulse of a telegram If the pulse was invalid then software must stop the counter and start again Run bit first reset and then SET with start bit set to wait for a new telegram Semiconductor Group 127 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Capture reload t
58. Preliminary amp Confidential Microcontroller 6 Microcontroller 6 1 Architecture Every cpu machine cycle consists of 12 internal cpu clock period The CPU manipulates operands in two memory spaces the program memory space and the data memory space The program memory address space is provided to accommodate relocatable code The data memory address space is divided into the 256 byte internal data RAM XRAM extended data memory accessible with MOVX instructions and the 128 byte Special Function Register SFR address spaces Four register banks each bank has eight registers 128 addressable bits and the stack reside in the internal data RAM The stack depth is limited only by the available internal data RAM Its location is determined by the 8 bit stack pointer All registers except the program counter and the four 8 register banks reside in the special function register address space These memory mapped registers include arithmetic registers pointers l O ports registers for the interrupt system timers pulse width modulator capture control unit watchdog timer UART display acquisition control etc Many locations in the SFR address space are addressable as bits Note that reading from unused locations within data memory will yield undefined data Conditional branches are performed relative to the 16 bit program counter The register indirect jump permits branching relative to a 16 bit base register with an offset provided by an
59. Progressive 202 DRCS characters 203 Memory Organization of DRCS characters 203 Memory Organization 206 Character Display Area 208 of Mie 208 Global Display Word Cursor 208 1 bit 2 bit 4 bit DRCS 209 Overview on the SFR registers 210 DA Gonvetter ooi we Er end Geass 211 Register Description iwi Lig Db dee u aaa uqu 211 Electrical Characteristics 215 Absolute Maximum 5 215 Operating Range cles xk exe elk TR ESPERE YN 215 DC Characteristics 215 TIMINGS umum e sa IR BOR oe RT fe 221 Package 224 Glossaty eere DRE e A RV EOD ea ES 225 Index 222022 bre eR are RR ACER b Een a 226 List of changes since last edition 227 Semiconductor Group 7 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Semiconductor Group 8 User s Manual July 99 Infineon
60. VS P4 7 Type Additional reference Available Vo SDIP52 MQFP64 MQFP100 PLCC84 Vertical sync input output for display synchronization Can also be used as digital input P4 7 Furthermore this pin can be selected as an ODD EVEN indicator alternatively to P3 0 R G B Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 Red Green Blue COR BLA Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 Contrast reduction and blanking Semiconductor Group 19 User s Manual July 99 Infineon technologies Preliminary amp Confidential Package and Pinning 2 2 Additional Pins or Functions for ROMless Version Symbol Function 0 16 Additional reference Available 100 PLCC84 A17 A19 P4 0 P4 1 P4 4 00 07 STOP OCF ENE Address bus for external program memory or data RAM Type Additional reference Available 1 0 MQFP100 PLCC84 After power on P4 0 P4 1 P4 4 work as additional address lines A17 A19 NN In port mode these port lines act as bidirectional I O port with internal pull up resistors Port pins that have 1 written to them are pulled high by the internal pull up resistors and in that state can be used as inputs Type Additional reference Available 1 0 MQFP100 PLCC84 Data bus for external memory or data RAM Type Additional reference Available 100 STOP Emulation control line
61. XRAM There are three different DRCS color resolution formats available 1 bit per pixel DRCS characters 2 bit per pixel DRCS characters 4 bit per pixel DRCS characters In which way this 1 bit 2 bit or 4 bit color vector information is used to access the CLUT see 18 4 7 18 5 1 Memory Organization of DRCS characters The following examples are proceeded on the assumption that a height of 11 character lines is selected The memory organization behaves the same for any other count of lines AO l m m m m x 8 A LINEO LINEI LINE2 LINE3 LINEA LINES LINE6 LINE7 LINE8 LINE9 Figure 22 Allocation of pixels inside the character matrix Semiconductor Group 205 User s Manual July 99 e _ Infine technologies on SDA 55xx Preliminary amp Confidential Display Each character starts at a new byte address This causes that for odd heights nibbles may be left free 1 bit DRCS characters address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1 CHAR 1
62. alternative to using the TR1 bit in TCON register to start and stop timer counter 1 12 1 2 Configuring the Timer Counter Input The use of the timer counter is determined by two 8 bit registers TMOD timer mode and TCON timer control The input to the counter circuitry is from an external reference for use as a counter or from the on chip oscillator for use as a timer depending on whether TMOD s C T bit is set or cleared respectively When used as a time base the on chip oscillator frequency is divided by twelve or six before being used as the counter input When TMOD s GATE bit is set 1 the external reference input T1 TO or the oscillator input is gated to the counter conditional upon a second external input INTO INT1 being high When the GATE bit is zero 0 the external reference or oscillator input is unconditionally enabled In either case the normal interrupt function of INTO and Semiconductor Group 122 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential General Purpose Timers Counters INT1 is not affected by the counter s operation If enabled an interrupt will occur when the input at INTO or INT1 is low The counters are enabled for incrementing when TCON s TR1 and TRO bits are set When the counters overflow the TF1 and TFO bits in TCON get set and interrupt requests are generated The counter circuitry counts up to all 1 s and then overflows to either 05 or
63. and EX1 in edge triggered mode Now there is the possibility to trigger an interrupt on the falling and or rising edge at the dedicated Port3 Pin In order to use this feature respective ITO and IT1 bits in the TCON register must be set to activate edge triggering mode Table below shows combination for Interupt O however description is trueforinterupt 1 also ITO EXOR EXOF Interrupt 0 0 0 Disabled Semiconductor Group 95 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts 0 0 1 Low level 0 1 0 High level 0 1 1 Disabled 1 0 0 Disabled 1 0 1 Negative edge triggered 1 1 0 Positive edge triggered 1 1 I Positive and negative edge triggered Default after reset 054 IRCON SFR Address MSB LSB EXX1F EXXOR EXXOF EX1F EXOR EXOF EXX1R if set ExternalX 1 interrupt detection on rising edge at Pin P3 7 EXX1F if set ExternalX 1 interrupt detection on falling edge at Pin P3 7 EXXOR if set ExternalX O interrupt detection on rising edge at Pin P3 1 EXXOF if set ExternalX O interrupt detection on falling edge at Pin P3 1 EX1R if set External 1 interrupt detection on rising edge at Pin P3 3 1 if set External 1 interrupt detection on falling edge at Pin EXOR if set External 0 interrupt detection on rising edge at Pin P3 2 EXOF if set External 0 in
64. and the settings of DRCSB2_3 DRCSB2_0 Semiconductor Group 211 User s Manual July 99 e Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 6 5 Overview on the SFR registers Next to the settings in the XRAM SFR registers are used for OSD control bit name programma width purpose ble SFR address F8h EN LD GDW yes 1 bit Used to avoid the download of the parameter settings of the GDW from the RAM to the local display gene rator register bank See also 18 4 2 0 Download disabled 1 Download enabled Initial value 0 F8h EN DG OUT yes 1 bit Used to disable enable the output of the display generator If display generator is disabled the RGB outputs of the IC are set to black and the outputs BLANK and COR are set to COR ENABLECOR BLANK ENABLEBLA If display generator is enabled the display information RGB COR and BLANK is generated according to the parameter settings in the XRAM 0 Display generator is disabled 1 Display generator is enabled nitial value 0 F8h DIS COR no 1bit Defines the level of the COR output if display genera tor is disabled nitial value 0 F8h DIS BLA no 1bit Defines the level of the BLANK output if display generator is disabled nitial value 1 F3h POINTARRAY no 6 bit Defines a pointer to a pointer array 1_1 See also 18 6 nitial value 0 F4h POINTARRAY no 8bit Defines a pointer to a pointer array
65. bit characters the CLUT is divided 8 SubCLUTSs with 4 entries For 4 bit DRCS characters the CLUT is divided in 4 subCLUTs with 16 different entries Semiconductor Group 196 User s Manual July 99 DA 55xx Infineon technologies Preliminary amp Confidential Display subCLUTs can be selected for each character position individual For this three bits CLUT2 CLUT1 and CLUTO are reserved inside the character display word CDW see also 18 3 CLUT2 CLUT1 CLUTO Meaning for ROM Meaning for character and 4 bit DRCS 1 bit 2 bit DRCS characters characters 0 0 0 SUbCLUTO is selected subCLUTO is selected 0 0 1 subCLUT1 is selected subCLUT1 is selected 0 1 0 subCLUT2 is selected subCLUT2 is selected 0 1 1 SUbCLUTS is selected SubCLUTS is selected 1 0 0 SUbCLUTA is selected subCLUTO is selected 1 0 1 SUbCLUTS is selected subCLUT1 is selected 1 1 0 SUbCLUTS is selected subCLUT2 is selected 1 1 1 subCLUT7 is selected subCLUT3 is selected see also 18 3 Character Display Word CDW CLUT entries from 0 15 are hardwired and can not be changed by the user Each of the 48 RAM programmable CLUT locations have a width of 2 byte These 2 bytes are used to define a 3 x 4 bit RGB value plus the behaviour of the BLANK and COR output pins The following format is used 372 1 ys 2 d ps 2 15812 T2 TO e Omen CLU
66. indirect relative to the DPTR 1 JZ rel Jump if Accumulator is zero 2 JNZ rel Jump if Accumulator is not zero 2 JG rel Jump if Carry flag is set 2 JNC rel Jump if Carry flag is not set 2 JB bit rel Jump if direct bit set 3 JNB bit rel Jump if direct bit not set 3 JBC bit rel Jump if direct bit is set and clear bit 3 CJNE A direct rel Compare direct to A and jump if not equal 3 CJNE A data rel Compare immediate to A and jump if not equal 3 CJNE Rn data rel Compare immediate to register and jump if not equal 3 CJNE data rel Compare immediate to indirect and jump if not equal 3 DJNZ Rn rel Decrement register and jump if not zero 2 DJNZ direct rel Decrement direct and jump if not zero 3 NOP No operation 1 Semiconductor Group 73 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller 6 3 4 Instruction Opcodes in Hexadecimal Order Figure 14 Instruction Opcodes in Hexadecimal Order Hex Code Number of Bytes Mnemonic Operands 00 1 NOP 01 2 AJMP code addr 02 3 LJMP code addr 03 1 RR A 04 1 INC A 05 2 INC data addr 06 1 INC RO 07 1 INC RI1 08 1 INC RO 09 1 INC R1 0A 1 INC R2 0B 1 INC R3 oc 1 INC R4 00 1 INC R5 OE 1 INC R6 1 INC R7 10 3 JBC bit addr code addr 11 2 ACALL code addr 12 3 LCALL code addr 13 1 RRC A 14 1 DEC A 15 2 DEC data addr 1
67. is internally processed The following formula shows how to delay the external V sync before it is internally latched and processed ly delay 3 84 us VSU CORBL 3 Level Contrast Reduction Output There is one pin each for BLANK and COR Nevertheless by means of CORBL the user is able to switch the COR signal to a three level signal providing BLANK and contrast reduction information on Pin COR simultaneously 0 Two level signal for contrast reduction 1 Three level signal Level0 BLANK off COR off Level1 BLANK off COR on Level2 BLANK on COR off Note Please refer to chapter Electrical Specifications for the detailed specification of these Levels RGB G 0 Used for DAC setup purpose See also description of DAC RGB G 1 Used for DAC setup purpose See also description of DAC BW CON Used for DAC setup purpose See also description of DAC Semiconductor Group 158 User s Manual July 99 SDA 55xx e Infineon technologies Preliminary amp Confidential Default after reset 00 CISRO bit addresseble Sync System SFR Address CO MSB LSB L24 ADC WTmr AVS DVS PWtmr AHS DHS L24 See Chapter interrupt ADC See Chapter interrupt WTmr See Chapter interrupt AVS See Chpater interrupt DVS 1 Display Vertical sync interrupt source bit set by hardware 0 Display Vertical sync interrupt source bit must be reset by software PWtmr See Chpater interrupt
68. load GDW bit in the SFR bank If this bit is set to 0 the global display word can be changed without any effect on the screen and in consequence the cursor position can be changed without any effect on the screen To bring the effect to character display area the LOAD bit has to be set to 1 for at least one V period approximately 50ms The cursor ist handeled as a layer above the character display area Pixels of the 2 bit cursor bitplane which are set to 00 are transparent to the OSD Video layer below So the cursor can be transparent to the OSD in case of no transparency of OSD or to video in case of transparency of OSD Example DRCS character stored at 896d column 5 6d TOW 10d pixel shift gt horizontal 7d vertical 6d 119 character row column horizontal 54 vertical 10d Figure 19 Positioning of HW Cursor One out of 8 subCLUTs is used to display the cursor The parameters CURCLUT2 CURCLUTO are used to define the subCLUT to be used For detailed information of CLUT access see 18 4 7 Semiconductor Group 188 User s Manual July 99 oe SDA 55xx technologies Preliminary amp Confidential Display CUR CUR CUR Description CLUT CLUT CLUT 0 Used to select the subCLUT which is used for color look up of the 1 cursor 0 7 0 7 1 S O O O N 1 0 0 1 1 see also 18 4 Global Display Word GDW 18 4 3 Border Col
69. of the base cycle is 63 clock cycles In case all the comparator bits 7 0 including the stretching bits are set to 1 the high time of the full cycle 4 base cycles is 255 clock cycles The corrosponding PWCOMPSx register determines the duty cycle of the channel When the counter value is equal to or greater than the compare value then the output channel is set to zero The duty cycle can be adjusted in steps of fpwm as mentioned in the table In order to achieve the same resolution as 8 bit counter the high time is stretched periodically by one clock cycle Stretching cycle is determined based on the two least significant bits in the corresponding PWCOMPS8x register The relationship for streching cycle can be seen in the following table and the example below PWCOMP8X Cycle stretched Bit 1 1 3 Bit 0 2 stretched d Cycle 0 Cycle 1 Cycle 2 Cycle 3 Semiconductor Group 134 User s Manual July 99 Infineon SDA 55 technologies 14 4 2 14 bit PWM The base frequency of a 14 bit resolution channel is derived from the overflow of a eight bit counter On every counter overflow the enabled PWM lines would be set to 1 Execpt in the case when compare value is set to zero The corrosponding PWCOMP14x register determines the duty cycle of the channel When the counter value is equal to or greater than the compare value then the output channel is set t
70. see also 1 DRCSB1 1 for DRCS adressing 18 3 1 2 DRCSB1 2 7 3 DRCSB1 3 4 DRCSB2 0 Used to define the boundary pointer 2 see also 5 DRCSB 1 for DRCS adressing 18 3 1 6 DRCSB2 2 7 DRCSB2 3 0 SHEN Enables shadow see also 1 SHEAWE Defines if east or west shadow is 18 4 9 processed 8 2 SHCOLO Defines the shadow color vector 3 SHCOL1 4 SHCOL2 5 SHCOL3 6 SHCOL4 7 SHCOL5 Semiconductor Group 183 User s Manual July 99 DA 55xx Infineon SDA 55 technologies Preliminary amp Confidential Display Byte Bit Name function cross Pos reference 0 CURCLUTO Used to choose the foreground vector see also 1 CURCLUT1 for the cursor 0 63 18 4 2 2 CURCLUT2 9 3 FLRATEO Defines the flash rate for flashing see also 4 FLRATE1 characters 18 4 5 5 HDWCLUTCOR Defines the level of COR for the colors see also of the hardwired CLUT 18 4 7 6 HDWCLUTBLANK Defines the level of BLANK for the see also colors of the hardwired CLUT 18 4 7 7 Reserved Semiconductor Group 184 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 4 1 Character Display Area Resolution The count of rows of the character display area can be adjusted in a range from 33 to 64 columns in horizontal direction In vertical direction the character display area is fixed to 25 rows It depends on the settings for synchronisation mode pixel frequ
71. the reload value Upon overflow TF1 or TFO is set When an instruction changes the timer s mode or alters its control bits the actual change occurs at the end of the instruction s execution 12 1 3 Timer Counter Mode Register Default after reset 00 TMOD SFR Address 894 MSB LSB GATE C T M1 MO GATE C T M1 MO lt gt q 1 0 Gating control when set Timer counter x is enabled only while INTx pin is high and TRx control pin is set When cleared timer x is enabled whenever TRx control bit is set CIT Timer or counter selector Cleared for timer operation input from internal system clock Set for Counter operation input from Tx input pin Table 17 M1 M0 Operating Mode 0 0 SAB 8048 timer TLx serves as five bit prescaler 0 1 16 bit timer counter TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer O TLO is an eight bit timer counter controlled by the standard timer 0 control bits THO is an eight bit timer only controlled by timer 1 control bits Timer 1 timer counter 1 is stopped Semiconductor Group 123 User s Manual July 99 Infineon SDA SEE technologies Preliminary amp Confidential General Purpose Timers Counters
72. the system clock domain slow down mode Moreover the user is able to send the PLL into a power save mode SFR bit PLLS 1 Attention Before the PLL is switched to power save mode PLLS 1 the software has to switch the clock source from 200MHz PLL clock to the 3MHz oscillator clock SFR bit CLK_src 1 In this mode the Slicer Acquisition DAC and Display Generator are switched off To switch back the software has to end the PLL power save mode SFR bit PLLS 0 reset the PLL for 10us 3 machin cycles SFR bit PLL resz 1 then 0 again then wait 150us 38 machine cycles and switch back to the PLL clock SFR bit PLL_src 0 If Power Down Mode is activated PLL and Oscillator are send to sleep SFR bit PDS 1 refer to chapter Power Saving Modes Furthermore there are additional possibilities to disable the clocks for the peripherals Please refer to chapter Power Saving Modes The second clock system is the pixel clock fp which is programmable in a range from 10 32MHz It serves the output part of the display FIFO and the D A converters The pixel clock is derived from the high frequent output of the PLL and line by line phase shifted to the positive edge of the horizontal sync signal normal polarity Because the final display clock is derived from a DTO digital time oscillator it has no equidistant clock periods although the average frequency is exact The pixel clock can also be inserted by an external source which h
73. timer is started it is not possible to switch to general purpose timer mode If WDT Tmr bit is set then timer can be started using WTmr Strt bit When timer is started it a Resets the WTmr_OV overflow flag b Loads the preload value from WDT Rel and starts counting up Upon overflow WDT Rst bit is not set neither is internal watchdog reset initiated Overflow is indicated by the bit WTmr Ov r w Overflow also sets the interrupt source bit CISRO WTmr Both of these bits are set by hardware and must be cleared by software If corresponding watchdog timer interrupt enable IE1 EWT bit is set then upon overflow interrupt is initiated After overflow timer starts to count from WDT Rel It is possible for the processor to stop the timer by resetting the WTmr strt bit any time While timer is running Tmr bit cannot be toggled any write to this bit is ignored To reset the WDT_Tmr bit either timer is stopped WTmr Strt However it is possible to stop the timer WTmr_Strt and toggle Tmr with the same instruction Semiconductor Group 145 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Watchdog Timer Semiconductor Group 146 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Analog Digital Converter CADC 16 Analog Digital Converter CADC TVTpro includes a four channel 8 bit ADC for control purposes By means of these four in
74. to usethe port lines In power down mode PWMU is shut off 14 7 Timer PWM unit uses a signle 14 bit timer to generate signals for all 8 channels Timer is mapped into SFR address space and hence is readable by the controller Timer is enabled running if one of the PWM channels is enabled in PWME If all the channels are disabled counter is stopped Enabling one of the chnnels will reset the timer to 0 and start Not that this reset is done for the first enabled channel All other channels enabled later will drive the output from the current value of the counter Semiconductor Group 136 User s Manual July 99 Infineon SDA 55 technologies If all the channels are disabled then it can be used as a general purpose timer by enabling it with PWM Tmr bit in PWCH Setting PWM Tmr bit switches to timer mode and starts the timer Timer always starts from a reset value of 0 OV also reset to 0 Timer can be stoped any time by turning off the PWM Tmr bit When timer overflows it sets an over flow bit OV bit 6 PWCH and interupt bit CISRO PWtmr in the central interrupt register If the corresponding interrupt enable bit isEPW IEN2 is set the interrupt would be serviced OV bit and PWtmr bits must be reset by the software Note that before utilizing the timer for PWM channels PWM_Tmr bit must be reset Note that On reset CISRO PWtmr bit is intialized to 0 however if counter overflows this bit might be set along with OV bit H
75. up vector see also 18 4 3 Semiconductor Group 154 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Character Display Area Characters and there attributes which are displayed inside this area are free programmable according to the specifications of the display generator see also 18 2 The start position of that area can be shifted in horizontal and vertical direction by programming the horizontal and vertical sync delay registers SDH and SDV The size of that area is defined by the instruction FSR in the display generator Register which allow to set up the screen and sync parameters are given in the table below Table 18 Overview on Sync Register Settings Parameters Register Min Value Max Value Step Default Sync Control Register SCR see below VL Lines Field VLR 1 line 1024 lines 1 line 625 lines Th period Horizontal Period HPR 15 us 122 8 us 30ns 64 us Fpixai Pixel Frequency PFR 10 MHz 32MHz 1 73 25 12 01 KHz MHz T sync_delay Sync Delay SDV 4 lines 1024 lines 1 line 32 lines Thsyne_delay gt Sync Delay SDH 32 pixel 2048 pixel 1 pixel 72 pixel BVCR Beginning BVCR 1 line 1024 lines 1 line line 0 Of Vertical Clamp Phase EVCR End EVCR 1 line 1024 lines 1 line line 4 Of Vertical Clamp Phase Th amp Beginning BHCR 01 122 8 us 480ns 0 us Of Horizontal Clamp Phase Tn End EHCR
76. 10 See also 18 6 nitial value 0 F5h POINTARRAY no 6 bit Defines a pointer to a pointer array 0 1 See also 18 6 nitial value 0 F6h POINTARRAY no 8 bit Defines a pointer to a pointer array 0_0 See also 18 6 nitial value 0 Semiconductor Group 212 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential D A Converter 19 D A Converter TVTpro uses a 3 x 2 bit voltage D A converter to generate analog RGB output signals with a nominal amplitude of 0 7V also available 0 5V 1 0V and 1 2V peak to peak 19 1 Register Description Default after reset 0 SCR1 SFR Address E14 MSB LSB reserved RGB G1 RGB G0 CORBL VSU 3 VSU 2 VSU 1 VSU 0 reserved reserved Should always be set to 1 RGB 1 0 Gain Adjustment of RGB Converter The user can change the output gain of the DAC 00 0 5V 01 0 7V default 10 1 0 11 1 2V VSU 3 0 refer to Sync System Default after reset 00 PSAVE bit addressable SFR Address D8 MSB LSB CADC WAKUP SLI ACQ DISP PERI Not used CADC refer to power saving modes WAKUP refer to power saving modes Semiconductor Group 211 User s Manual July 99 Infineon SDA SAR technologies Preliminary amp Confidential D A Converter SLI_ACQ refer to power saving modes DISP Display unit 0 Power save Mode not started 1 Power sav
77. 2 5 ns 1096 9095 Output Fall Time T 8 12 5 ns 10 90 Load Capacitance C 20 pF Semiconductor Group 218 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Electrical Characteristics Parameter Symbo Limit Values min max Unit Test Condition BLANK CORBLA Control bit CORBL 0 BLANK only Output voltage no data Vin 0 0 5 JV insertion Video Output voltage for data Viy 0 9 V insertion BLANK CORBLA Control bit CORBL 1 BLANK and COR Output voltage no data Vic n 0 05 insertion no contrast reduction Output voltage for contrast Vc 0 9 1 2 V reduction and no data insertion Output voltage for data Viy 1 8 V insertion HSYNC Input Rise Time T 100 ns 10 90 Input Fall Time 100 ns 10 90 Input Hysteresis Vuyst 300 600 Input Pulse Width TipwH 100 ns Output Pulse Width 1 us Output Rise Time T 100 ns 1096 9096 Output Fall Time T 100 ns 1096 9096 Load Capacitance C 50 pF Pin capacitance C 5 pF VSYNC Input Rise Time T 200 5 1096 9096 Semiconductor Group 219 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Electrical Characteristics Parameter Symbo Limit Values Unit Test Condition
78. 2 P2 Yes FF Port P27 P26 P25 P24 P23 P22 P24 P20 M No A2 No No M No AS No Semiconductor Group 27 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential SFR Overview Add Longname Short Name Bit Reset Location Bit6 Bit 5 Bit 4 Bit3 Bit2 Biti Bito Add Value A6 No 00 AT No 00 A8 Interrupt enable Reg 0 IEO Yes 00 Interrupt EAL EAD EU EX1 EXO A9 Interrupt enable 1 IE1 No 0 Interrupt EDV EAV EXX1 EWT EXX0 Interrupt enable 2 IE2 No 00 Interrupt EDH EAH ECC EPW AB Interrupt enable 3 IE3 No 00 Interrupt E EADW E24 E AC Interrupt Priority 1 IP1 No 00 Interrupt G5P0 G4P0 G3P0 G2P0 G1P0 G0P0 AD Interrupt control reg IRCON 05 Interrupt EXXIF EXXOR EXXOF EXIR EXIF EXOR EXOF AE No 00 00 Port 3 P3 Yes FF P37 P3 6 P35 4 P33 P32 P31 P3 0 B1 Watchdog Reload WDT rel No 00 WDT WDTrel 7 WDTrel 6 WDTrel 5 WDTrel 4 WDTrel 3 WDTrel2 WDTrel1 WDTrel 0 B2 Watchdog control WDT No 00 WDT WDT in WDT start WDT nars WDT rst i t B3 Watchdog refresh WDT refersh No 00 WDT WDT ref tmr WTmr strt WTmr ov gt B4
79. 20 FG2 characters Foreground color is choosen if bit inside ROM mask RAM is set to 1 see also 18 4 7 21 BGO background color vector Used for ROM characters and 22 BG1 1 bit DRCS characters 23 BG2 For 2 bit and 4 bit DRCS characters only used in flash mode Background color is choosen if bit inside ROM mask RAM is set to 0 see also 18 4 7 18 3 2 Semiconductor Group 174 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 3 1 Access of Characters The DRCS characters and ROM characters are accessed by a 10 bit character address inside character display word CDW see also 18 3 18 3 1 1 Address Range from 0 to 767 This address range can either be used to access ROM characters or to access 1 bit DRCS characters CHAAC Description 0 Normal mode Address range Od 767d is used to access ROM characters 1 Enhanced mode Address range Od 767d is used to access 1 bit DRCS characters see also 18 4 Global Display Word GDW 18 3 1 2 Address Range from 768 to 1023 The address range from 768 to 1023 is reserved to address the DRCS characters This range is splitted in three parts for 1 bit DRCS 2 bit DRCS and 4 bit DRCS The boundary between 1 bit DRCS and 2 bit DRCS as well as the boundary between 2 bit DRCS and 4 bit DRCS are defined by two boundary pointers inside global display word see also 18 4 Boundary Poi
80. 3 0 1 F 16 2 083 480 31 46 0 33 33 1 0 F 64 5208 1920 125 83 1 1 F 128 2604 3840 251 66 0 F 8 447 240 15 73 0 1 F 16 2 083 480 31 46 1 8 33 Y 1 0 F 64 5208 1920 125 83 1 1 F 128 2604 3840 251 66 Semiconductor Group 131 User s Manual July 99 e _ Infineon SDA 55 technologies Preliminary amp Confidential Capture reload timer 13 7 Block diagram RELOAD 16 bit Ctr Spike Supression Unit Y Int Y Into Semiconductor Group 132 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Pulse Width Modulation Unit 14 Pulse Width Modulation Unit The Pulse Width Modulation unit consists of 6 quasi 8 bit and 2 quasi 14 bit PWM channels PWM channels are programmed by special function registers and each individual channel can be enabled and disabled inindividually 14 1 Reset Values Al the unit registers PWME PWCOMP8 0 5 PWCOMP14 0 1 PWMCOMPEXT14 0 1 PWML and PWMH are by default reseted to 00h 14 2 Input clock Input clock to PWMU fpwm is derived from fsys fsys is 33 33 Mhz in normal mode and in slowdown mode 8 33 Mhz In normal mode fsys is divided by 2 and in slow down mode it is directly fed to the PWMU Therefore PWM unit is counting at 16 5 Mhz in normal mode and 8 25 Mhz in slow down mode If PR bit 14 O bit 0 is set the then the counting frequency is half of
81. 3 6 2 6 3 6 3 1 6 3 2 6 3 3 u uen eer PEEL Lid o hay Kee EG RE Was ERE ERE 9 M Pr daa 9 Organization of this 9 Related Documentation 10 Introduction meme RR l u ease dx 11 ealutes teu ss ln ade vaut aul ste aa aa hectare tds 12 Logic Symbol 15 Block diagrami Euro ES REA wa aga lam usa 16 Package and 17 Pin Functions ROM and ROMless Version 17 Additional Pins or Functions for ROMless Version 20 Port Alternate functions 22 SFR e a gum era das PoP 27 Additional registers 30 Glock System ecc are tuendi EIER 33 General Function 33 Register Description cus I uywayuq rnb a 35 Slicer and Acquisition 39 General Function 39 Slicer Architecture 1 39 Distortion 0 40 Data Separation 41
82. 3 2 or 3 3 A built in Spike Suppression Unit SSU can be used for suppressing pulses with obviously too small or too long time duration at the beginning of an expected telegram thereby relieving the FW of processing corrupted telegrams This is especially useful in idle mode 13 1 Input clock Input clock is fcc is same as system clock frequency divided by two In normal mode system frequency is 33 33 Mhz fcc 16 66Mhz and in slow down mode SD mode 8 33 Mhz fcc 4 16Mhz PR prescaler bit when set divides the input clock further by 2 PR1 divides further by 8 Internal to the block change in SD mode is detected and frequency is adjusted accordingly so that maximum time resolution of 15 73 msec or 251 66 msec is achieved depending on Prescaler PR bits 13 2 Reset values All the eight 8 bit registers RELL RELH CAPL CAPH MINCAPL MINCAPH CRTCONO and 1 are reset to 00 13 3 Functional description 13 3 1 Port pin Either Port P3 3 or P3 2 can be selected as capture input via SEL bit Capture event can be programmed to occur on rising or falling edge or both using the bits RISE and FALL bits 13 3 2 Slow down mode SD bit when set reduces the system frequency to 8 33 Mhz However the clk to the counter has a fix frequency for a particular prescaler value This is achieved by a divide by 4 chain which divides the incoming frequency by 4 when SD 0 and feeds the incoming signal directly to the counter
83. 3 2 Reset value 2 2225 h Au EUR 112 10 3 3 Program memory Banking LUMP 112 10 3 4 CALLs and Interrupts 113 10 3 5 Stack E ll y ee PS eee D De s 113 10 3 6 Une 113 10 3 7 Interfacing Extended memory 114 10 3 8 Interfacing Extended stack 114 10 3 9 Application Examples 114 10 3 10 ROM ROMless version 116 11 UART bh ar EV Shedd 117 11 1 amp 2 DE 117 11 2 Multiprocessor Communication 119 12 General Purpose Timers Counters 121 12 1 Timer Counter 0 Mode Selection 121 12 1 1 Configuring the Timer Counter Input 122 12 1 2 Timer Counter Mode Register 123 12 1 3 Timer Counter Control Register 124 13 Capture reload timer 125 13 1 Input clock x Rose RE ER on pere S RUNE ok a ah T BER 125 13 2 Reset val es SERT 125 13 3 Functional description 125 13 3 1 POM PIN ERE 125 13 3 2 Slow down mode 125 13 3 3 QUIDEM 126 13 3 4 OVerTlO
84. 6 1 DEC RO 17 1 DEC R1 18 1 DEC RO 19 1 DEC R1 1A 1 DEC R2 1B 1 DEC 1C 1 DEC R4 Semiconductor Group 74 User s Manual July 99 oe nfineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands 1D 1 DEC R5 1E 1 DEC R6 1F 1 DEC R7 20 3 JB bit addr code addr 21 2 AJMP code addr 22 1 RET 23 1 RL A 24 2 ADD A data 25 2 ADD A data addr 26 1 ADD A RO 27 1 ADD A R1 28 1 ADD A RO 29 1 ADD A R1 2A 1 ADD A R2 2B 1 ADD A R3 2C 1 ADD A R4 2D 1 ADD A R5 2E 1 ADD A R6 2F 1 ADD A R7 30 3 JNB bit addr code addr 31 2 ACALL code addr 32 1 RETI 33 1 RLC A 34 2 ADDC A data 35 2 ADDC A data addr 36 1 ADDC A R0 37 1 ADDC A OR1 38 1 ADDC A RO 39 1 ADDC A R1 3A 1 ADDC A R2 Semiconductor Group 75 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands 3B 1 ADDC A R3 3C 1 ADDC A R4 3D 1 ADDC A R5 3E 1 ADDC A R6 3F 1 ADDC A R7 40 2 JC code addr 41 2 AJMP code addr 42 2 ORL data add
85. 84 Program Store Enable a is a control output signal which is usually connected to OE input line of the external program memory to enable the data output XROM Type Additional Reference Available MQFP100 PLCC84 This pin must be pulled low to access external ROM FL xx Type Additional Reference Available 100 All the pins prefix by FL are test pins which must be left open Semiconductor Group 21 User s Manual July 99 e _ Infineon SDA technologies Preliminary amp Confidential Package and Pinning 2 3 Port Alternate functions perou um Ene Toggle Function Toggle Function Control bit Function Control bit Function P0 0 7 0 Port pin P1 0 0 Portpin PWME EO PWM 8 bit channel 0 1 0 Portpin PWME E1 PWM 8 bitchannel 1 P1Q 0 Portpin PWME E2 PWM 8 bit channel 2 P1 3 0 Portpin PWME E3 PWM 8 bit channel 3 P1 4 0 Portpin PWME E4 PWM 8 bitchannel 4 P1 5 0 Portpin PWME E5 PWM 8 bit channel 5 P1 6 O Portpin PWME E6 PWM 14 bit channel 0 P17 O Portpin PWME E7 PWM 14 bit channel 1 P2 0 Port pin CADCCO ADO ADC channel 0 P2 1 Port pin CADCCO AD1 ADC channel 1 P2 2 Port pin CADCCO AD2 ADC channel 2 P2 3 Port pin CADCCO AD3 ADC channel 3 P3 0 0 Portpin CSCRO O E 0 ODD Even indicator P3 1 0 Portpin Port inp
86. A 55xx tecnnologies Preliminary amp Confidential Memory Organization 10 3 10 ROM and ROMless version XROM pin determines the onchip or off chip ROM access If no internal ROM is to be used then the XROM pin in ROMIess version should be driven low Controller then accesses the External ROM only In ROM version this pin is internally pulled high indicating no external ROM Semiconductor Group 116 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential UART 11 UART The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register however if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The frequencies and baud rates depend on the internal system clock used by the serial interface The serial port can operate in 4 modes 11 1 Modes Mode 0 Serial data enters and exits through RxD P3 7 TxD P3 1 outputs the shift clock Mode 1 10 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB f
87. AD1 ADC channel 1 P2 2 Port pin CADCCO AD2 ADC channel 2 P2 3 Port pin CADCCO AD3 ADC channel 3 P3 0 0 Portpin CSCRO O E 0 ODD Even indicator P3 1 0 Portpin Port input mode External extra Int 0 Port output mode TXD P3 2 0 Portpin Portinput mode External interrupt 0 P3 3 0 Portpin Portinput mode External interrupt 1 P3 4 0 Portpin Port input mode Timer counter 0 input 3 5 0 Portpin Port input mode Timer counter 0 input P3 6 0 Port pin P3 7 0 Portpin Port input mode External extra Int 1 Portinput mode RXD 40 10 17 CSCRI AI7 P4 0 Portpin p4 1 0 A18 CSCRI AI8 P4 1 Portpin P4 2 0 Portpin CSCRI ENARW Read signal P4 3 O Portpin CSCR1 ENARW Write signal p4 4 O0 19 1 19 P4 4 Portpin 4 7 JO PortWS CSCRO VS OE VS output CSCRO VS OE OddEven output P4 7 ALT P4 7 ALT 1 Not available in SDIP52 Semiconductor Group 66 User s Manual July 99 SDA 55xx e Infineon technologies Preliminary amp Confidential Microcontroller It is not allowed to drive Port 3 6 to logic low level while reset state changes from the active to inactive state otherwise a special test mode is activated Secondary functions can be selected individually and independently for the pins of port 1 and 3 Further information on port 1 s secondary functions is given in chapter Pulse Width Modulation Unit
88. B SDV 7 SDV 6 SDV 5 SDV 4 SDV 3 SDV 2 SDV 1 SDV 0 Bit Function SDV 9 0 Vertical Sync Delay Master and slave mode This register defines the delay in lines from the vertical sync to the first line of character display area on the screen Reset 00 SDH1 SFR Address E54 MSB LSB SDH 11 SDH 10 SDH 9 SDH 8 Reset 48 SDHO SFR Address MSB LSB SDH 7 SDH 6 SDH 5 SDH 4 SDH 3 SDH 2 SDH 1 SDH 0 Bit Function SDH 11 0 Horizontal Sync Delay Master and slave mode This register defines the delay in pixels from the horizontal sync to the first pixel character display area on the screen Semiconductor Group 166 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Reset 0A HCR1 SFR Address E74 MSB LSB EHCR 7 EHCR 6 EHCR 5 EHCR 4 EHCR 3 EHCR 2 EHCR 1 EHCR 0 Reset 00 HCRO SFR Address MSB LSB BHCR 7 BHCR 6 BHCR 5 BHCR 4 BHCR 3 BHCR 2 BHCR 1 BHCR 0 Bit Function BHCR 7 0 Beginning of Horizontal Clamp Phase Master and slave mode This register defines the delay of the horizontal clamp phase from the positive edge of the horizontal sync im
89. C CLR PX Y clear bit Y of Port X CLR P2 6 SET PX Y set bit Y of Port X SET P3 5 The instruction reads the port byte all 8 bits modifies the addressed bit the latch Semiconductor Group 67 then writes the new byte back to User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Microcontroller 6 3 Instruction Set The assembly language uses the same instruction set and the same instruction opcodes as the 8051 microcomputer family 6 3 1 Notes on Data Addressing Modes Hn Working register RO R7 direct 128 internal RAM locations any control or status register Ri Indirect internal RAM location addressed by register RO or R1 data 8 bit constant included in instruction data 16 16 bit constant included as bytes 2 amp 3 of instruction bit 128 software flags any l O pin control or status bit in special function registers Operations working on external data memory MOVX are used to access the extended internal data RAM XRAM 6 3 2 Notes on Program Addressing Modes addr 16 Destination address for LCALL amp LJMP may be anywhere within the program memory address space addr 11 Destination address for ACALL amp AJMP will be within the same 2 Kbyte of the following instruction rel SJMP and all conditional jumps include an 8 bit offset byte Range is 127 128 bytes relative to first byte of
90. C 1 MOV R4 FD 1 MOV R5 A FE 1 MOV R6 A FF 1 MOV 7 Semiconductor Group 82 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Interrupts 7 Interrupts 7 1 Interrupt System External events and the real time on chip peripherals require CPU service asynchronous to the execution of any particular section of code To couple the asynchronous activities of these functions to normal program execution a sophisticated multiple source four priority level nested interrupt system is provided 7 2 Interrupt Sources processor is capable of handling upto 24 interrupt sources In SDA55xx 17 interrupts are implemented rest are reserved for future use Processor acknowledges interrupt requests from 17 sources Two external sources via the INTO and INT1 pins and two additional external interrupts INTXO and INTX1 are provided Peripherals also use interrupts One from each of the two internal counters one from the analog digital converter and one from UART In addition there are four Acquisition related interrupts two display related interrupts and one interrupt indicating change of channel two interrupts are generated by WDT and PWM overflow in timer mode Timer 0 and Timer 1 interrupts are generated byTCON TFO and TCON TF1 following a rollover in their respective registers except in Mode 3 when TCON THO controls the Timer 1 interrupt The external interrupts
91. CADCO 2 CADCO 1 CADCO 0 CADCO 7 0 ADC result of channel 1 After finishing the A to D conversion the processor is informed by means of an interrupt The interrupt service routine can now take the conversion result of channel 1 from CADCO The result will be available for about 46 after the interrupt Semiconductor Group 147 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Analog Digital Converter CADC Default after reset 00 CADC1 SFR Address D2 MSB LSB CADC1 7 CADC1 6 CADC1 5 CADC1 4 CADC1 3 CADC1 2 CADC1 1 CADC1 0 CADC1 7 0 ADC result of channel 2 After finishing the A to D conversion the processor is informed by means of an interrupt The interrupt service routine can now take the conversion result of channel 2from CADC1 The result will be available for about 46 after the interrupt Default after reset 00 CADC2 SFR Address D3 MSB LSB 2 7 CADC2 6 CADC2 5 CADC2 4 CADC2 3 CADC2 2 CADC2 1 CADC2 0 CADC2 7 0 Semiconductor Group ADC result of channel 3 After finishing the A to D conversion the processor is informed by means of an interrupt The interrupt service routine can now take the conversion result of channel 3 from CADC2 The result will be available for about 46ys after the interrupt 148 User s Manual July 99
92. Confidential Watchdog Timer 15 4 WDT reset If software fails to refresh the WDT before the counter overflows after FFFF an internally generated watchdog reset is entered Watchdog timer reset differs only from the normal reset in that during normal reset all the WDT relevant bits in the three registers WDT Rel WDT Refresh WDT control are reset to 00 Counter gets initialized to 0000 In case of watchdog reset Statt and WDT nARST are not reset Bit WDT Rst read only is set to indicate the source of the reset In addition the WDT reset does not reset the PLL and clock generator If the nARSst bit is set then the values in the WDT Rel are retained after the WDT reset and counter starts with the same pre scaler WDT and reload configuration as before reset If WDT nARst is not set then upon watchdog reset WDT Rel is reset to 00h and WDT In to O After the WDT reset counter starts again and must be refreshed by the processor in order to avoid further WDT resets Duration of the WDT reset is sufficient to ensure proper reset sequence 15 5 Power down mode WDT is shut off during power down mode along with the rest of the peripherals In idle mode the WDT in watch dog mode is frozen in timer mode it continues it s operation In power save mode PSAVE PERI watchdog continues it s operation any write to this bit is ignored If in timer mode the timer can be frozen by setting this bit Semiconductor Group 142 User s
93. DRCS characters Example 2 Boundary Pointer1 set to 848d Boundary Pointer2 set to 848d Character Address Description From To 768 847 1 bit DRCS characters 848 1023 4 bit DRCS characters Example 3 Boundary Pointer 1 set to 768d Boundary Pointer 2 set to 928d Character address Description From To 768 9274 2 bit DRCS characters 928 1023 4 bit DRCS characters Semiconductor Group 177 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display 18 3 2 Flash Bit FLASH inside character display word CDW see also 18 3 is used to enable flash for a character FLASH Description 0 steady flash disabled 1 flash see also 18 3 Character Display Word CDW The meaning of the flash attribute is different for ROM characters and 1 bit DRCS characters in comparison to the meaning of flash for 2 bit and 4 bit DRCS characters For flash rate control see also the global attribute FLRATE1 FLRATEO in chapter 18 4 5 18 3 2 1 Flash for ROM Characters and 1 bit DRCS Characters For ROM characters and 1 bit DRCS characters enabled flash causes the foreground pixels to alternate between the foreground and background color vector 18 3 2 2 Flash for 2 bit and 4 bit DRCS Characters For these characters enabled flash causes the DRCS pixels to alternate between the 2 bit 4 bit color vector and the background
94. H V synchronization for the slicer The acquisition interface Semiconductor Group 39 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition i Sync Slicer y HS1 IR VS1 IR gt HN 2 m gt HPLL 5453 IR bs Timing CC IR Data seperation Acquisition Interface Y to amp S P ress CVBS A Darr p Converter Decoder Compen Noise Paramete Attenua Butter Group D Measur A Figure 6 Block Diagram of Digital Slicer and Acquisition Interface 5 2 1 Distortion Processing After A D conversion the digital CVBS bit stream is applied to a circuitry which corrects for transmission distortion In order to apply the right algorithm for correcting a signal measurement is done in parallel This measurement device can detect the following distortions Noise The value of the back porch is called black level and known to the system Therefore the back porch can be used to measure the noise distortion by just measuring the differences between the black value and the actual sampled value at the back porch A flag is set as soon as this differences over several TV lines are greater than a specified value This flag is used to switch on the noise suppression algorithm i
95. HADRC is used to characterize the organization of DRCS characters and the vertical count of lines for a character row on output side If the count of lines of ROM characters is smaller than the count of DRCS Semiconductor Group 201 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display characters the lines of ROM characters are filled up with background colored pixels Semiconductor Group 202 User s Manual July 99 e Chinar SDA 55xx technologies Preliminary amp Confidential Display 18 49 Shadowing If shadowing is enabled the ROM characters and 1 bit DRCS characters of the characters are displayed by west shadow or east shadow The color vector of the shadow is defined by software The shadow color vector has a width of 6 bit The shadow feature is enabled by the bit SHEN SHEN Description 0 shadow disabled shadow for ROM characters and 1 bit DRCS characters see also 1 4 Global Display Word GDW There are two options for shadowing SHEAWE Description 0 east shadowing 1 west shadowing see also 1 4 Global Display Word GDW CLUT entries from 0 63 can be used as a shadow color vector SHCOL5 SHCOL4 SHCOL3 SHCOL2 SHCOL1 SHCOLO Description 0 0 0 0 0 0 Defines a color vector 0 0 0 0 0 1 for shadowing See also 18 4 7 1 1 1 1 1 0 1 1 1 1 1 1 see also 1 4 Global Display Word GDW
96. Hz Attention Register values greater then 874 generate pixel frequencies which are outside of the specified boundaries Semiconductor Group 35 User s Manual July 99 Infineon SDA DIR technologies Preliminary amp Confidential Clock System Default after reset 00h PCON SFR Address 874 MSB LSB SMOD PDS IDLS SD GF1 IDLE SMOD refer to power saving modes PDS Power Down Start Bit 0 Power Down Mode not started 1 Power Down Mode started The instruction that sets this bit is the last instruction before entering power down mode Additionally this bit is protected by a delay cycle Power down mode is entered if and only if bit PDE was set by the previous instruction Once set this bit is cleared by hardware and always reads out a 0 PLL and Oscillator are switched off during Power Down IDLS refer to power saving modes SD refer to power saving modes GFx refer to power saving modes PDE refer to power saving modes IDLE refer to power saving modes Semiconductor Group 36 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Clock System Default after reset 00 PSAVEX SFR Address D7 MSB LSB CLK_src PLL_res PLLS PLLS 0 PLL is running 1 PLL is disabled The system clock is switched to the 6MHz oscillator clock The slicer acquisition and the display ge
97. IEN1 EWT 0043 WTmr CISRO 5 External X Interrupt 1 IEN1 EXX1 004B CISR1 IEX1 Acquisition V Sync IEN1 EAV 0053 AVS CISRO 4 Display V Sync IEN1 EDV 005B DVS CISRO 3 PWM in timer mode IEN2 EPW 0083 PWtmr CISRO 2 Channel Change IEN2 ECC 008B CC CISR1 7 Acquisition H Sync IEN2 EAH 0093 AHS CISRO 1 Display H Sync IEN2 EDH 009B DHS CISRO 0 Line 24 Start 1 E24 00C3 L24 CISRO 7 A to D Wake up IEN3 EADW 00CB ADW CISR1 6 Semiconductor Group 92 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Interrupts 7 8 Interrupt and memory extension When an interrupt occurs the Memory Management Unit MMU carries out the following sequence of actions 1 The MEX1 register bits are made available on SDATAO 7 0 2 The MEXSP register bits are made available on SADD 7 0 3 The Stack read and write signals are set for a write operation 4 A write is performed to External memory 5 The MEXSP Stack Pointer is incremented 6 The Interrupt Bank bits IB19 IB16 MEX2 3 MEX2 0 are copied to both the NB19 NB16 and the CB19 CB16 bits in the MEX1 Then on return from the interrupt service routine 1 The MEXSP Stack Pointer is decremented 2 The MEXSP register bits are made available on SADD 7 0 3 The Stack read and write signals are set for a read operation 4 A read is performed on External memory 5 SDATAI 7 0 is copied to the MEX1 register Th
98. JMP code addr A2 2 MOV C bit addr A3 1 INC DPTR 4 1 MUL AB A5 reserved A6 2 MOV RO data addr 2 R1 data addr A8 2 MOV RO data addr A9 2 MOV R1 data addr AA 2 MOV R2 data addr AB 2 MOV data addr AC 2 MOV R4 data addr AD 2 MOV R5 data addr AE 2 MOV R6 data addr AF 2 MOV R7 data addr BO 2 ANL C bit addr B1 2 ACALL code addr B2 2 CPL bit addr Semiconductor Group 79 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands B3 1 CPL B4 3 CJNE A data code addr B5 3 CJNE A data addr code addr B6 3 CJNE R0 data code addr B7 3 CJNE R1 data code addr B8 3 CJNE RO data code addr B9 3 CJNE R1 data code addr BA 3 CJNE R2 data code addr BB 3 CJNE R3 data code addr BC 3 CJNE R4 data code addr BD 3 CJNE R5 data code addr BE 3 CJNE R6 data code addr BF 3 CJNE R7 data code addr CO 2 PUSH data addr C1 2 AJMP code addr C2 2 CLR bit addr C3 1 CLR C C4 1 SWAP A C5 2 XCH A data addr C6 1 XCH A RO C7 1 XCH A R1 C8 1 XCH A RO C9 1 XCH A R1 CA 1 XCH A R2 CB 1 XCH A R3 CC 1 XCH A R4 CD 1 XCH A R5 CE 1 XCH A R6 CF 1 XCH A R7 DO 2 POP data addr Semiconductor Group 80
99. Microcontroller 6 1 2 CPU Timing Timing generation is completely self contained except for the frequency reference which can be a crystal or external clock source The on board oscillator is a parallel anti resonant circuit The XTAL2 pin is the output of a high gain amplifier while XTAL1 is its input A crystal connected between XTAL1 and XTAL2 provides the feedback and phase shift required for oscillation In slowdown mode processor runs at one fourth the normal frequency This mode is useful when power consumption needs to be reduced Slow down mode is entered by setting the bit SD in PCON register Note Any Slow down mode should only be used if teletext reception and the display are disabled Otherwise processing of the incoming text data might be incomplete and the display structure will be corrupted For disabling acquisiton and display generator refer to chapter Power saving modes 6 1 3 Addressing Modes There are five general addressing modes operating on bytes One of these five addressing modes however operates on both bytes and bits Register Direct both bytes and bits e Register indirect Immediate Base register plus index register indirect The following table summarizes which memory spaces may be accessed by each of the addressing modes Register Addressing RO R7 ACC B CY bit DPTR Direct Addressing RAM low part Special Function Registers Register indirect Addressing RAM QR1
100. O EX6 Reserved Default after reset 00 IE2 SFR Address MSB LSB EDH EAH ECC EPW EX13 EX12 Not implemented Return 0 when read EDH Enable or disable Display H Snc EAH Enable or disable Acquisition H Snc ECC Enable or disable channel change interrupt EPW Enable or disable PWM in timer mode EX13 Reserved EX12 Reserved Semiconductor Group User s Manual July 99 Chiu SDA 55xx technologies Preliminary amp Confidential Interrupts Default after reset 004 IE3 SFR Address MSB LSB i 5 EADW E24 EX21 EX20 EX19 EX18 Not implemented Return 0 when read EADW Enable or disable Analog to digital wake up unit E24 Enable or disable line 24 interrupt 21 Reserved EX20 Reserved EX19 Reserved EX18 Reserved 7 5 Interrupt source registers All the interupts except for timer 0 timer1 external interrupt O external interrupt external extra interrupt 0 and external extra interrupt 1 are generated by the respective blocks and are positive edge trigered They are sampled in a central interrupt source register corresponding bit must be cleared by the software after entering the interrupt service routine Semiconductor Group 87 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts Default after reset 004 CISRO bit addresseble SFR Address MSB LSB L24 ADC WTmr AVS DVS PWtm
101. POSHOR 1 3 POSHOR2 4 POSHORS3 5 POSHOR4 6 POSHOR5 7 POSVERO Vertical character position of cursor 0 POSVER1 1 POSVER2 2 POSVER3 3 3 POSVER4 4 GLBTO BOX1 Used to enable transparency of Box1 see also 5 GLBT1 BOX1 CLUT transparency of subCLUTO can 18 4 6 be overruled for destined pixels inside 6 GLBT2 BOX1 Box 7 Reserved 0 BRDCOLO Color vector of border See also 1 BRDCOL1 18 4 3 2 BRDCOL2 4 3 BRDCOL3 4 BRDCOL4 5 BRDCOL5 6 BLA_BOX1 Used to define the overruling see also 7 COR 1 transparency levels for Box1 18 4 6 0 GDDH0 Double height of the full screen see also 1 18 44 2 GDDH2 5 3 GLBTO BOXO Used to enable transparency of see also 4 GLBT1 BOXO CLUT transparency of subCLUTO can 18 4 6 be overruled for destined pixels inside 5 GLBT2 BOXO 0 6 BLA BOXO Used to define the overruling See also 7 COR BOXO transparency levels for BoxO 18 4 6 Semiconductor Group 182 User s Manual July 99 e Qnin SDA 55xx technologies Preliminary amp Confidential Display Byte Bit Name function cross Pos reference 0 CHADRCO Defines vertical resolution of DRCS see also 1 CHADRC1 characters 18 4 8 2 CHADRC2 6 3 Defines vertical resolution of ROM 4 1 characters 5 CHAROM2 6 CHAAC Defines character access mode see also 18 3 1 7 Reserved 0 DRCSB1 0 Used to define the boundary pointer 1
102. Reserved No 80 FE No 00 FF Reserved No Red addresses are controller fix addresses These registers are for internal use of the device Do not write in these locations All the bits marked with and Reserved are reserved As a general rule Software should always only write to the bits which it wants to change all other bits implemented or not should be masked in order to avoid problems with future versions 3 1 Additional registers Default after reset 00 CSCRO SFR Address DD MSB LSB ENERCLK P4 7 VS OE OEP30 OE Pol Not used 7 Alt Selects the output function of the port 0 Port function is selected 1 Port 4 7 alternate function is selected see vs OE For inut port mode or slave mode VS input mode port must be switched to input mode by writing 1 to the port latch VS OE 0 4 7 alternate output mode Odd Even selected 1 4 7 alternate output mode Vertical Sync selected Refer to display chapter register SCRO for Vertical Sync details Semiconductor Group 30 User s Manual July 99 e DA Infineon SDA 55 technologies Preliminary amp Confidential SFR Overview 0 0 Port 3 0 port mode selected 1 Port 3 0 works as a Odd even output P E POL 0 Odd 1 Even 0 1 Odd 0 Even 1 Note polarity is true for both P3 0 and P4 7 Semiconductor Group 31 User s Manual July 99
103. S 6 cx m ss c o gt EEP PAE 9 xn Bojeuy 59529 5 E 2 8 See E 8 9 M aor User s Manual July 99 16 Semiconductor Group e DA 55xx Infineon inpia technologies Preliminary amp Confidential Package and Pinning 2 Package and Pinning 2 1 Pin Functions ROM and ROMless Version Symbol Function 0 0 0 7 Type Additional reference Available yo SDIP52 MQFP64 MQFP100 PLCC84 P1 0 P1 7 PWM P2 0 P2 3 ADC P3 0 P3 7 Alternate function Port 0 is 8 bit open drain bidirectional l O port Port 0 pins that have 1 written to them float in this state they can be used as high M eene inputs e g for software driven I C Bus support Type Additional reference Vo Available SDIP52 MQFP64 MQFP100 PLCC84 Port 1 is a 8 bit bidirectional multifunction I O port with internal pull up resistors Port 1 pins that have 1 written to them are ulled high by the internal pull up resistors and in that state can used as inputs The secondary functions of port 1 pins are Port bits P1 0 P1 5 contain the 6 output channels of the 8 bit ulse width modulation unit ort bits P1 6 P1 7 contain the two output channels of the 14 bit pulse width modulation unit Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 Port 2 is a 4 bit input port without pull up resistors Port 2 also works as analog input for the 4 channel ADC
104. S characters are stored in the RAM Within a 4 bit DRCS character a 4 bit color vector information is available for each pixel By this 1 out of 16 color vectors is selected from a subCLUT 1 out of 4 subCLUTSs are selected by character display word CDW see also 1 3 Please notice the table in chapter 18 4 7 1 Semiconductor Group 200 User s Manual July 99 oe 4 nfineon SDA 55xx technologies Preliminary amp Confidential Display 18 4 8 Character Resolution The character matrix of DRCS characters can be adjusted in vertical direction from 9 lines up to 16 lines In horizontal direction the character matrix is fixed to 12 pixels CHADRC2 CHADRC1 CHADRCO Description 0 0 9 lines 10 lines 11 lines 1 0 1 12 lines 0 13 lines 1 0 0 0 0 0 1 14 lines 15 lines 1 16 lines see also 18 4 Global Display Word GDW 0 1 1 0 0 1 1 The character matrix of the ROM characters can also be adjusted in vertical direction from 9 lines up to 16 lines In horizontal direction the ROM character matrix is fixed to 12 pixels CHAROM2 CHAROM1 CHAROMO Description 0 0 0 9 lines 0 0 1 10 lines 0 1 0 11 lines 0 1 1 12 lines 1 0 0 13 lines 1 0 1 14 lines 1 1 0 15 lines 1 1 1 16 lines see also 18 4 Global Display Word GDW The parameter CHAROM is used to characterize the organization of ROM characters The parameter C
105. SDA 55 technologies Preliminary amp Confidential Overview 1 Overview 1 1 Preface TVText Pro is a 8 bit controller based on SIEMENS Enhanced 8051 core with embedded teletext On screen Display and TV controller functions TVText Pro can be used for a wide range of TV and OSD applications This document provides complete reference information of the TVText Pro system 1 2 Organization of this document Chapter 1 Overview Gives a general description of the product and lists the key features Chapter 2 Package and Pinning Lists pin locations with associated signals categorizes signals according to function and describes signals Chapter 3 SFR Overview List of the registers Chapter 4 Clock System Describes Clock system and it s distribution Chapter 5 Slicer and Acquisition Describes slicer and acquisiton interface Chapter 6 Microcontroller Describes microcontroller instruction set ports Chapter 7 Interrupts Describes interrupts priorities sources enhancements to standard 8051 interrupt logic Chapter 8 Power Saving modes Describes the four power saving modes of the device Chapter 9 Reset Describes reset requirements and behavior of the device Chapter 10 Memory Organization Describes internal external RAM ROM and Memory extension Chapter 11 UART Describes peripheral UART Chapter 12 General Purpose Timers Counters Describes peripherals TimerO and timer 1 Semiconduct
106. SDataO 7 0 SRd and SWr are available at the core boundary which are sued to interface a 64 Byte SRAM 10 3 9 Application Examples MOVC Figure 15 PC and DPTR on Different Banks DPTR PC UECO4717 1 17 73 64 72 Semiconductor Group 114 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Memory Organization Sample Code Figure shows an assembler program run performing the following actions 1 Start at bank 0 at 00000 2 Set ISR page to bank 2 3 Jump to bank 1 at address 25 4 Being interrupted to bank 2 ISR 5 Call a subprogram at bank 2 address 43 6 After return read data from bank 2 ORG 25 ORG 40 0025 PRGM1 MOV sset ISR Bank Bank 2 Prepare Interrupt PRGMO Calling PRGM2 MOV MEX2 02 on Bank 2 Prepare jumping 0040 MOV 1 2 from Bank 0 to Bank 1 RETI ORG 43 PRGM2 0080 LCALL 43 MEXt 4 Fetch Data from Bank 2 update ISR Bank pointer PRGM2 0060 RET LJMP 25 ORG 100 225 is a substitution 0100 BYTE 444 of Primary Labels 0150 MEX2 0A2 4 transformed to an 0153 MOV DPTR 100 Absolute Address at 0156 MOVC A DPTR Bank 2 to AKKU UECO4719 Fig Program code Semiconductor Group 115 User s Manual July 99 Infineon SD
107. STAB VDOK FIELD NOISE GRDON GRDSIGN GRDSIGN Group delay detector 0 If group delay distortion has been detected it was positive 1 If group delay distortion has been detected it was negative Written to memory by ACQ interface GRDON Group delay detector 0 No group delay distortion detected 1 Group delay distortion detected Written to memory by ACQ interface NOISE Noise detector 0 No noise detected 1 Noise detected Written to memory by ACQ interface FIELD Field detector Semiconductor Group 0 Actual field is field 1 1 Actual field is field 2 Written to memory by ACQ interface 51 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Slicer and Acquisition VDOK STAB CC Default after reset MSB Vertical sync watchdog 0 There was no vertical sync during stable horizontal synchronization 1 There was atleast one vertical sync during stable horizontal synchronization Written to memory by ACQ interface Horizontal sync watchdog 0 H PLL of not locked 1 H PLL of locked Written to memory by ACQ interface Vertical sync watchdog of slicer 1 0 The number of lines between two vertical syncs is stable 1 number of lines between two vertical syncs changed suddenly Written to memory by ACQ interface 00 ACQFP7 LSB LEOFLI LEOFLI LEOFLI LEOFLI 11 10 9 8 LEOFLI 11 8
108. Semiconductor Group 110 User s Manual July 99 Chia SDA 55xx technologies Preliminary amp Confidential Memory Organization Memory Extension Register 2 Default after reset 00 MEX2 SFR Address 95 MSB LSB MM MB18 MB17 MB16 IB19 IB18 IB17 IB16 IB Interrupt Bank R W MB Memory Bank R W MM Memory Mode R W 1 use MB Comments None Memory Extension Register 3 Default after reset 00 SFR Address 964 MSB LSB MB19 UBS3 UB4 MX19 MXM MX18 MX17 MX16 MB19 Memory Bank bit RAWbit See MEX2 MXM 1 During external Data Memory accesses the bits MX19 16 are used as address lines A19 16 instead of the current bank CB MX19 16 MOVX Bank R W If MXM is set these bits will be used during external data moves into or from an externally connected Data RAM UB3 UB4 User bits available to the user for MMU they are don t Semiconductor Group care 111 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Memory Organization 0 0 1 Memory Extension stack pointer Default after reset 004 MEXSP SFR Address 974 MSB LSB 5 6 5 5 5 4 SP3 SP2 SP1 SPO SP Stack Pointer Maximum allowable value 7F Bit7 Reserved bit for future Comments None 10 3 2 Reset value In order to insure proper 8051 functionality all the bits in SFR MEX1 MEX2 MEX3 and MEXSP are ini
109. Tadress 0 CLUTadress 1 1 0 Figure 20 Bit 3 0 Semiconductor Group RGB Transparency Memory Format of CLUT 4 bit representation of Blue value 197 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display Bit 7 4 Bit 11 8 4 bit representation of Green value 4 bit representation of Red value Bit 12 Directly fed to BLANK pin Bit 13 Directly fed to COR pin Bit 14 reserved Bit 15 reserved Semiconductor Group 198 User s Manual July 99 oe Infineon technologies SDA 55xx Preliminary amp Confidential 18 4 7 1 Organization of CLUT Display cnu RON CLUT No for CLUT No for 2 bit CLUT No for 4 bit RAM address Race 1 bit DRCS Cursor DRCS character DRCS character hardy ined CLUE character No entry No entry No entry No entry 0 0 0 0 0 R G B 00 00 00 not available 1 1 not 1 not 1 1 R GB 15 00 00 availa availa not available 2 2 bie 2 ble 2 2 R G B 00 15 00 not available 3 0 3 3 3 3 RGB 15 15 00 not available 4 4 0 0 4 R G B 00 00 15 not available 5 5 not 1 not 1 5 RGB 15 00 15 availa availa n
110. Th 4Ch 54 6 ble 2 ble 2 6 software programmable CLUTPOINTh 4Eh 55 7 3 3 7 software programmable CLUTPOINTh 50h 56 0 0 0 8 software programmable CLUTPOINTh 52h 57 1 not 1 not 1 9 software programmable availa availa CLUTPOINTh 454h 58 7 2 ble 2 ble 2 10 software programmable CLUTPOINTh 56h 59 3 3 3 11 software programmable CLUTPOINTh 58h 60 4 0 0 12 software programmable CLUTPOINTH 5Ah 61 5 not 1 not 1 13 software programmable availa availa CLUTPOINTh 5Ch 62 6 ble 2 ble 2 14 software programmable CLUTPOINTh 5Eh 63 7 3 3 15 software programmable 18 4 7 2 CLUT Access for ROM characters 1 bit DRCS characters For each pixel of a character a 1 bit background foreground information is available 1 out of 8 subCLUTs can be selected by character display word CDW see also 18 3 1 out of 8 color vectors can be selected as a foreground and background color vector by the character display word CDW see also 18 3 Please notice the table in chapter 18 4 7 1 18 4 7 3 CLUT Access for 2 bit DRCS Characters 2 bit DRCS characters are stored in the RAM Within a 2 bit DRCS character a 2 bit color vector information is available for each pixel By this 2 bit information 1 out of 4 color vectors is selected from a subCLUT 1 out of 8 SubCLUTSs is selected by character display word CDW see also 1 3 Please notice the table in chapter 18 4 7 1 18 4 7 4 CLUT Access for 4 bit DRCS Characters 4 bit DRC
111. Tpro Following formula helps to calculate a memory address of a character position You depending on the count of characters in horizontal direction defined in the binary parameters DISALH4 DISALHO and a display start address DISPOINT CHARADRESS DISPOINT Y oy x DISALH4 DISALHO 21 Xcq x 3p Semiconductor Group 173 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential 18 3 Parallel Character Attributes The character display area content of each character position is defined by a 3 byte character display word CDW see also 18 3 in display memory CHARACTER DISPLAY WORD RAM location display memory Display Byte Bit Name Function Remark Pos 0 CHAR0 1 CHAR1 2 CHAR2 DRCS characters are defined 3 CHAR3 Used to choose a ROM or by the user Up to 16 different 0 4 CHAR4 DRCS character colors can be used within one 5 CHARS DRCS see also 18 3 1 6 CHAR6 7 CHAR7 8 CHAR8 9 CHAR9 10 FLASH Control of flash modes See also 18 3 2 11 UH Upper half double height See also 18 3 3 BET DH Double height See also 18 3 3 13 DW Double width See also 18 3 4 14 BOX Control for Boxes See also 18 4 6 15 CLUTO Bit0 CLUT select See also 18 4 7 16 CLUT1 Bit1 CLUT select See also 18 4 7 17 CLUT2 Bit2 CLUT select See also 18 4 7 18 FGO foreground color vector Only used for ROM 19 FG1 characters and 1 bit DRCS 2
112. Up to 16 Colors for DRCS Character One out of Eight Colors for Foreground and Background Colors for 1 bit DRCS and ROM Characters Shadowing Contrast Reduction Pixel by Pixel Shiftable Cursor With up to 4 Different Colors Support of Progressive Scan Semiconductor Group 172 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 2 Display Memory The display memory is located inside the internal XRAM The start address of the display memory is at memory address DISPOINT This memory address is defined by the user due to a pointer For each character position three bytes in the display memory are reserved These three bytes are stored in a serial incremental order for each character and used to define the display attributes of each single character position The complete amount of allocated display memory depends on the display resolution In vertical direction the character display area is fixed to 25 rows In horizontal direction the character display area can be adjusted from 33 up to 64 columns The following figure is an example for a character display area resolution of 25 rows and 40 columns row address i 0 i 39d No Od fo a DISPOINT 0 0 DISPOINT 1 78 ixX3 DISPOINT Character Display Area 2 F0 ix 3 DISPOINT 23 AC8 ix 3 DISPOINT 24 40 i X 3 Figure 18 Display Memory Organization of TV
113. User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands D1 2 ACALL code addr D2 2 SETB bit addr D3 1 SETB C D4 1 DA A D5 3 DJNZ data addr code addr D6 not applicable D7 not applicable D8 2 DJNZ R0 code addr D9 2 DJNZ R1 code addr DA 2 DJNZ R2 code addr DB 2 DJNZ R3 code addr DC 2 DJNZ R4 code addr DD 2 DJNZ R5 code addr DE 2 DJNZ R6 code addr DF 2 DJNZ R7 code addr E0 1 MOVX A DPTR E1 2 AJMP code addr E2 not applicable ES not applicable E4 1 CLR A E5 2 MOV A data addr E6 1 MOV A R0 E7 1 MOV A R1 E8 1 MOV A RO E9 1 MOV A R1 EA 1 MOV A R2 EB 1 MOV A R3 EC 1 MOV A R4 ED 1 MOV A R5 EE 1 MOV A R6 Semiconductor Group 81 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands EF 1 MOV A R7 FO 1 MOVX DPTR A F1 2 ACALL code addr F2 not applicable F3 not applicable F4 1 CPL A F5 2 MOV data addr A F6 1 MOV RO A F7 1 MOV 1 F8 1 MOV RO F9 1 MOV R1 A FA 1 MOV R2 FB 1 MOV R3 A F
114. W xix Ree manaa 126 13 3 5 MOdeS cto pi a e u ans D 126 13 3 6 Normal Capture mode 126 13 3 7 Polling Modene ene ED e x RR UR prr pus 127 13 3 8 Capture mode with spike suppression at the start of a telegram 127 13 3 9 Firstevent 2 Rx re ER RR RERBA RE ER E ERE 127 13 3 10 Second 127 13 3 11 CRT Interrupts meas sigen aa an Ret 128 13 3 12 Counter Stop 128 13 4 Idle and power down 128 13 5 ReglslerS oes bur Re PEN Ede een See 128 13 6 Time resolution ed PEL hukaq 131 Semiconductor Group 5 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential 13 7 Block diagram wer en RE RE Br 132 14 Pulse Width Modulation Unit 133 14 1 Reset Valu6 us bah hein panne pe aed pean Wea fan RES Een ala 133 14 2 Input clock iore hate HIM shapi s 133 14 3 POM DIMS cua y eatem Yong ain r E 133 14 4 Functional description 134 14 4 1 B DIEPWM aest hee ee DERE bh RI sg ie eee 134 14 4 2 14 bit PWM 4230
115. a 0 0 0 Full Screen Normal Height Memory organization Display Appearance Row No 0 Row No 0 Row No 1 Row No 1 Row No 11 Row No 11 Row No 12 Row No 12 Row No 23 Row No 23 Row No 24 Row No 24 0 0 1 Full Screen Double Height Rows 0 11 are displayed in double height Row 24 is settled on bottom of display in normal height Memory organization Display Appearance Row No 0 Row No 1 lt Row No 0 Row No 11 Row No 1 Row No 12 E nom Row No 23 Row No 11 Row No 24 Row No 24 Semiconductor Group 190 User s Manual July 99 i SDA 55xx Infineon technologies Preliminary amp Confidential Display 0 1 0 Full Screen Double Height Rows 12 23 are displayed in double height Row 24 is settled on bottom of display in normal height Memory organization Display Appearance Row No 0 Row No 12 Row No 11 Row No 13 Row No 12 ER RES 23 Row No 23 Row No 24 Row No 24 0 1 1 Full Screen Double Height Rows 12 23 are displayed in double height Row 0 is settled on top of display in normal height Memory organization Display Appearance
116. a These three bytes are used to store the character display word as it is described in chapter 18 3 The array is sorted in a incremental serial order coming from the top left character throughout the bottom right character of the character display area For further information see chapter 18 2 The length of this display memory area depends on the parameter settings of DISALHO DISALH4 18 6 2 CLUT Area The CLUT area consist of 48 x 2 Byte CLUT contents The CLUT contents are stored in a serial incremental order For further information see chapter 18 4 7 The length of the CLUT is fixed to 96 bytes 18 6 3 Global Display Word Cursor The area of the global display word is fixed to 10 byte All the global display relevant informations are stored inside global display word GDW see also 18 4 See also 18 2 The cursor matrix for cursor display is stored after the global display word The length of the memory area of global display word is fixed to 10 byte The length of the memory area of cursor matrix depends on the settings of CHADRC2 CHADRCO Semiconductor Group 210 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 6 4 1 bit 2 bit 4 bit DRCS character In this area the pixel information of the dynamic reconfigurable characters is stored For further information on the memory format refer to 18 5 The length of these areas depends on the settings of DRCSB1_3 DRCSB1_0
117. able CLUTPOINTh 26h 35 3 3 3 3 software programmable CLUTPOINTh 28h 36 4 0 0 4 software programmable CLUTPOINTh 2Ah 37 5 5 1 1 5 software programmable CLUTPOINTh 2Ch 38 6 2 2 6 software programmable CLUTPOINTh 2Eh 39 7 3 3 5 T software programmable CLUTPOINTh 30h 40 0 0 0 8 software programmable CLUTPOINTh 32h 41 1 1 1 9 software programmable CLUTPOINTh 434h 42 5 2 6 2 6 2 10 software programmable CLUTPOINTh 36h 43 3 3 3 11 software programmable CLUTPOINTh 438h 44 4 0 0 12 software programmable CLUTPOINTh 3Ah 45 5 7 1 7 1 13 software programmable CLUTPOINTh 3Ch 46 6 2 2 14 software programmable CLUTPOINTh 3Eh 47 7 3 3 15 software programmable Semiconductor Group 199 User s Manual July 99 e _ Infineon SDA 55xx technologies Preliminary amp Confidential Display CLU CLUT No for ROM and CLUT No for CLUT No for2 bit CLUT No for 4 bit EAM address 1 bit DRCS Cursor DRCS character DRCS character hardwired character No entry No entry No entry No entry CLUTPOINTh 40h 48 0 0 0 0 software programmable CLUTPOINTh 42h 49 1 not 1 not 1 1 software programmable availa availa CLUTPOINTh 44h 50 6 2 ble 2 ble 2 2 software programmable CLUTPOINTh 46h 51 3 3 3 3 software programmable CLUTPOINTh 48h 52 4 0 0 4 software programmable CLUTPOINTh 4Ah 53 5 not 1 not 1 5 software programmable availa availa CLUTPOIN
118. an perform the bit operation of logical AND or logical OR with the result returned to the carry flag 6 1 1 6 Program Status Word Register PSW The PSW flags record processor status information and control the operation of the processor The carry CY auxiliary carry AC two user flags FO and F1 register bank select RSO and RS1 overflow OV and parity P flags reside in the program status word register These flags are bit memory mapped within the byte memory mapped PSW The CY AC and OV flags generally reflect the status of the latest arithmetic operations The CY flag is also the Boolean accumulator for bit operations The P flag always reflects the parity of the A register FO and F1 are general purpose flags which are pushed onto the stack as part of a PSW save The two register bank select bits RS1 and 50 determine which one of the four register banks is selected as follows Table 16 RS1 RSO Register Bank Register Location 0 0 0 00 07 0 1 1 08 OF 1 0 2 10 17 1 1 3 18 1 Reset 00 Program Status Word PSW SFR Address DO MSB LSB CY AC FO RS1 RSO OV F1 P 6 1 1 7 Stack Pointer SP The 8 bit stack pointer contains the address at which the last byte was pushed onto the stack This is also the address of the next byte that will be popped The SP is Semiconductor Group 61 User s Manual July 99 Infineon SDA 55xx tecnnolog
119. are same as discussed above 7 10 Interrupt Latency The response time in a single interrupt system is between 3 and 9 machine cycles 7 11 Interrupt Flag Clear In case of external interrupt 0 and external interrupt 1 If the external interrupts are edge triggered the interrupt flag is cleared on vectoring to the service routine but if they are level triggered the flag is controlled by the external signal Timer counter flags are cleared on vectoring to the interrupt service routine All other interrupt flag including external extra interrupt O and 1 are not cleared by hardware They must be cleared by software 7 12 Interrupt return For the proper operation of the interrupt controller It is necessary that all interrupt routines end with a RETI instruction 7 13 Interrupt Nesting The process whereby a higher level interrupt request interrupts a lower level interrupt service program is called nesting In this case the address of the next instruction in the lower priority service program is pushed onto the stack the stack pointer is incremented by two and processor control is transferred to the program memory location of the first instruction of the higher level service program The last instruction of the higher priority interrupt service program must be a RETI instruction This instruction clears the higher priority level active flip flop RETI also returns processor control to the next instruction of the lower level interrupt
120. are structured as follows Default after reset 00 IPO bit addresseble Interrupts SFR Address B8 MSB LSB G5P0 G4P0 G3P0 G2P0 G1P0 G0P0 Default after reset 00 IP1 SFR Address MSB LSB G5P1 G4P1 G3P1 G2P1 G1P1 G0P1 IP1 7 IP1 6 Not implemented Return 0 when read IP0 7 IP0 6 GxP1 GxP0 Interrupt Group Priority Level as follows x 0 to 5 0 0 Interrupt Group x is set to priority level 0 lowest 0 1 Interrupt Group x is set to priority level 1 1 0 Interrupt Group x is set to priority level 2 1 1 Interrupt Group x is set to priority level 3 highest Semiconductor Group 91 User s Manual July 99 e _ Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts 7 7 Interrupt Vectors When an interrupt is serviced a long call instruction is executedto one of the locations listed in the following table Interrupt Sources Interrupt Enable Vector Interrupt Request Flag Address Register Bit hex External Interrupt 0 IEN0 EX0 0003 IE0 TCON 1 Timer 0 Overflow IEN0 ETO 000B TF0 TCON 5 External Interrupt 1 IENO EX1 0013 IE1 TCON 3 Timer 1 Overflow IENO ET1 001B TF1 TCON 7 UART IENO EU 0023 R1 SCON 0 and T1 SCON 1 Ato D IENO EAD 002B ADC CISRO 6 ExternalX Interrupt 0 IEN1 EXXO 003 CISR1 IEXO Watchdog in timer
121. as a fixed and stable phase to an external horizontal sync This pixel clock generation system has several advantages The frequency of the pixel clock can be programmed independently from the horizontal line period Because the input of the PLL is already a signal with a relative high frequency the resulting pixel frequency has an extremely low jitter Theresulting pixel clock follows the edge of the H sync impulse without any delay and has always the same quality than the sync timing of the deflection controller Semiconductor Group 34 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Clock System 4 2 Register Description Default after reset 01 PCLK1 SFR Address DA MSB LSB PF 10 PF 9 PF 8 PF 10 8 Pixel Frequency factor MSBs for detailed information refer to PCLK0 Default after reset 484 PCLKO SFR Address DB MSB LSB PF 7 PF 6 PF 5 PF 4 PF 3 PF 2 PF 1 PF 0 PF T 0 Pixel Frequency factor LSBs This register defines the relation between the output pixel frequency and the frequency of the crystal The pixel frequency does not depend on the line frequency It can be calculated by the following formula fa PF 300MHz 8192 The pixel frequency can be adjusted in steps of 36 6 KHz After power on this register is set to 328p So the default pixel frequency is set to 12 01 M
122. assified as Program Memory Internal Data Memory 256 Bytes CPU RAM Internal Extended Data Memory XRAM A 16 bit program counter and a dedicated banking logic provide the processor with 1 MByte addressing capability for ROM less versions up to 20 address lines are available The program counter allows the user to execute calls and branches to any location within the program memory space Data pointers allows to move data to and from Extended Data RAM There are no instructions that permit program execution to move from the program memory space to any of the data memory space 10 1 Program Memory Program ROM consists of 128KByte on chip ROM Certain locations in program memory are reserved for specific programs Locations 0000 through 0002 are reserved for the initialization program Following reset the CPU always begins execution at location 0000 Locations 0003 through OOCB are reserved for the interrupt request service programs Interrupt Source Vector Address External Interrupt 0 0003 Timer 0 Overflow 000B External Interrupt 1 0013 Timer 1 Overflow 001B UART 0023 ADC 002B Reserved 0033 ExternalX Interrupt 0 003B Watchdog timer 0043 External X Interrupt 1 004B Acquisition V Sync 0053 Display V sync 005B Reserved 0063 Semiconductor Group 107 User s Manual July 99 Infineon SDA 55xx tecnnologies
123. ckground pixels of 1 bit DRCS characters see also 18 4 Global Display Word GDW Semiconductor Group 193 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display To decide the levels of COR and BLANK for BOXO two global parameters are used COR BOXO BLA BOXO Description 0 0 Box transparency levels of COR and BLANK are overruled by COR 0 BLANK 0 0 1 Box transparency levels of COR and BLANK are overruled by COR 0 BLANK 1 1 0 Box transparency levels of COR and BLANK are overruled by COR 1 BLANK 0 1 1 Box transparency levels of COR and BLANK are overruled by COR 1 BLANK 1 see also 18 4 Global Display Word GDW For characters which are using subCLUTO there are two types of transparencys which can be defined Which of these two box transparencys is used is defined character individual inside the bit BOX in CDW character display word see also 18 3 Transparency definition for characters for which BOX is set to 1 and which are using subCLUTO GLBT2 BOX1 GLBT1_BOX1 GLBTO BOX1 Description X 0 0 Box transparency is disabled for BOX1 0 0 1 Box transparency is enabled for BOX1 for following pixels Foreground pixels of ROM characters 0 1 0 Box transparency is enabled for BOX1 for following pixels Foreground pixels of 1 bit DRCS characters 0 1 1 Box transparency is enabled for BOX1 for following pix
124. coder The ALU performs the arithmetic operations of add subtract multiply divide increment decrement BCD decimal add adjust and compare and the logic operations of and or exclusive or complement and rotate right left or nibble swap The A register is the accumulator the B register is dedicated during multiply and divide and serves as both a source and a destination During all other operations the B register is simply another location of the special function register space and may be used for any purpose Semiconductor Group 60 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Microcontroller 6 1 1 5 Boolean Processor The Boolean processor is an integral part of the processor architecture It is an independent bit processor with its own instruction set its own accumulator the carry flag and its own bit addressable RAM and The bit manipulation instructions allow the direct addressing of 128 bits within the internal data RAM and several bits within the special function registers The special function registers which have addresses exactly divisible by eight contain directly addressable bits The Boolean processor can perform on any addressable bit the bit operations of set clear complement jump if set jump if not set jump if set then clear and move to from carry Between any addressable bit or its complement and the carry flag it c
125. color vector which is defined by the parameters BG2 BGO inside character display word CDW see also 18 3 18 3 3 Character Individual Double Height Bit UH Upper half double height marks the upper part of a double height character It is only active if the DH bit Double Height is set to 717 Semiconductor Group 178 User s Manual July 99 T Infineon SDA 55xx technologies Preliminary amp Confidential Display The following table shows the influence of the DH bit and the UH bit on the character DH UH Display see also 18 3 Character Display Word CDW Semiconductor Group 179 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 3 4 Character Individual Double Width Bit DW double width marks the left half of a character with double width The character to its right will be overwritten by the right half If the DW bit of the following character here the X is also set to 1 the right half of the A is overwritten by the left half of the X If a character is displayed in double width mode the attribute settings of the left character position are used to display the whole character DW bit Display Left Right character character A A see also 18 3 Character Display Word CDW Semiconducto
126. cquisition horizental sync interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred Semiconductor Group 88 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Interrupts DHS 1 Display horizental sync interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred Default after reset 00 CISR1 bit addresseble SFR Address C8 MSB LSB CC ADW IEX1 IEX0 CC 1 Chanel change interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt 0 Interrupt has not occurred ADW 1 ADC wake up interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt 0 Interrupt has not occurred IEX1 External Extra Interrupt 1 edge flag Setby hardware when external interrupt edge detected Must be cleared by software Note that port P3 7 must be in input mode to use this interupt IEX0 External Extra Interrupt 0 edge flag Setby hardware when external interrupt edge detected Must be cleared by software Note that port P3 1 must be in input mode to use this interupt Semiconductor Group 89 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts 7 6 Interrupt priority For the purposes of assi
127. e Infineon technologies ICs for Consumer Electronics Confidential Preliminary User s Manual TVTEXT PRO SDA 55xx Version 1 21 July 99 TVTEXT PRO Revision History User s Manual Version 1 21 July 99 Previous Releases Version 1 1 Dec 98 Version 1 2 April 99 ae ses See Chapter List of Changes Edition July 99 Published by Infineon Technologies Bereich Halbleiter Marketing Kommunikation Balanstrafie 73 D 81541 M nchen Infneon Technologies 1999 All Rights Reserved As far as patents or other rights of third parties are concerned liability is only assumed for components per se not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Offices of Infineon Technologies in Germany or Infineon Technologies Companies and Representatives worldwide Due to technical requirements components may contain dangerous substances For information on the type in question please contact your nearest Infineon Technolgies Office Infineon SDA 55xx technologies Preliminary amp Confidential und um k O Q N 5 2 5 2 1 5 2 2 5 3 5 4 5 4 1 5 4 2 5 4 3 5 5 5 5 1 5 5 2 6 6 1 6 1 1 6 1 2 6 1
128. e 1 VLR1 02 DSync OddEv VsU3 VSU 2 1 VSU 0 VL 9 VL B EF DSync Veticalline 0 VLRO No 71 Dsync VL7 VL 5 VLA VL 3 v2 VLA FO B register B Yes 00 Micro B7 B6 B5 B4 B3 B2 B1 1 DSync Horiz period 1 HPR1 No 08 DSync HPR 11 10 HPR9 HPR 8 F2 DSync Horiz period 0 HPRO 55 Dsync HPR7 HPR_6 HPR 5 HPR 4 HPR 3 HPR 2 HPR 1 HPR 0 F3 Display Ptr 1 high byte PointArrayt 1 No Display Pointi 13 Pointi 12 Pointt 11 Pointi 10 Point 9 Pointi 8 F4 Display Ptr 1 low byte PointArrayt 0 No 00 Display Pointi_7 6 Pointi_s Point 4 Pointt_2 Pointti Pointt_o F5 Display Ptr 0 high byte PointArrayO 1 No 00 Display Point 13 Pointo 12 Pointo 11 Pointo 10 Point 9 Point 8 F6 Display Ptr 0 low byte PointArrayO 0 No 00 Display Point 7 Point 6 Point 5 Pointo 4 Point 3 02 Point 1 Pointo_o F7 No 00 Semiconductor Group 29 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential SFR Overview Add Long name Short Name Bit Reset Location Bit6 Bit5 Bit4 Bit3 Bit2 Bitt Bito Add Value F8 Display OSD control OSD Yes 00 Display En ld Cu En DGOut Dis Cor Dis Blank r F9 Reserved No 00 FA Reserved No 00 FB No 00 FC No 00 FD
129. e 1 a 1 is sliced otherwise a 0 MLENGTH specifies how many samples are taken Corresponds to slicer 1 MLENGTH Number of samples 000 1 001 3 010 5 011 7 100 9 101 11 110 13 111 15 Default after reset 00 ACQLP4 MSB LSB FCOK FCOK Framing Code Received 0 No framing code has been detected no new data has been written to memory 1 The selected framing code has been detected new data has been written to memory Semiconductor Group 56 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Slicer and Acquisition 5 5 2 Recommended Parameter Settings TTX VPS WSS CC G AGDON 1 0 0 0 0 AFRON 1 0 0 0 0 ANOON 1 1 1 1 1 GDPON 0 0 0 0 0 GDNON 0 0 0 0 0 FREON 0 0 0 0 0 NOION 0 0 0 0 0 DINCR 54559 39321 39321 7920 7920 1 0 0 0 0 0 MLENGTH 1 2 7 7 7 ALENGTH 2 2 2 2 2 CLKDIV 0 0 2 5 5 NORM 0 2 3 4 5 FCSEL 0 1 2 2 2 VCR 0 0 0 0 0 MATCH 0 0 0 0 0 FC1 228 don t care don tcare don tcare FC3 don t don tcare 3 1261 FC3MASK don tcare don tcare 63 2047 Semiconductor Group 57 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition Semiconductor Group 58 User s Manual July 99 Infineon SDA 55 technologies
130. e 8 33 Mhz Microcontroller Features 8bit 8051 instruction set compatible CPU 33 33 MHz internal clock max 0 360 us min instruction cycle Two 16 bit timers Watchdog timer Overview CMOS P SDIP 52 28 s 64 Capture compare timer for infrared remote control decoding Pulse width modulation unit 2 channels 14 bit 6 channels 8 bit ADC 4 channels 8 bit UART Type Package TVTEXT PRO ROM P SDIP 52 P MQFP 64 TVTEXT PRO ROMless P MQFP 100 P LCC 84 Semiconductor Group 12 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Overview Memory Non multiplexed 8 bit data and 16 20 bit address bus ROMless Version Memory banking up to 1Mbyte Romless version Upto 128 Kilobyte on Chip Program ROM Eight 16 bit data pointer registers DPTR 256 bytes on chip Processor Internal RAM IRAM 128bytes extended stack memory e Display RAM and TXT VPS PDC WSS Acquisition Buffer directly accessible via MOVX UP to 16KByte on Chip Extended RAM XRAM consisting of 1 Kilobyte on chip ACQ buffer RAM access via MOVX 1 Kilobyte on chip extended RAM XRAM access via MOVX for user software 8 Kilobyte Display Memory Display Features ROM Character Set Supports all East and West European Languages in single device Mosaic Graphic Character Set Parallel Display Attributes
131. e Mode started In Power save mode display generator pixel clock unit display sync unit sandcastle decoder and COR BLA are disabled All the pending bus request are masked off DAC is also switched off and it outputs the values defined for DAC off BLA output their reset value PERI refer to power saving modes Semiconductor Group 212 User s Manual July 99 i SDA 55xx Infineon technologies Preliminary amp Confidential D A Converter Default after reset 000xxx00 PCON SFR Address 874 MSB LSB SMOD PDS IDLS SD GF1 GFO PDE IDLE SMOD refer to UART PDS Power Down Start Bit 0 Power Down Mode not started 1 Power Down Mode started The DAC is switched off during Power Down Mode IDLS Idle Start Bit 0 Idle Mode not started 1 ldle Mode started The DAC is switched off during Idle Mode SD Slow Down Bit 0 Slow down mode is disabled 1 Slow down mode is enabled The DAC is switched off during Slow Down Mode GF1 refer to Power saving modes GFO refer to Power saving modes PDE refer to Power Save Modes IDLE refer to Power Save Modes Semiconductor Group 213 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential D A Converter Semiconductor Group 214 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Electrical Characteristics 20 Electrical Characteristics 20 1 Absolute Maximum Ratings The maximum
132. e SFR Address C0 MSB LSB L24 ADC WTmr AVS DVS PWtmr AHS DHS L24 1 Line 24 start interrupt occurred source bit set by hardware source bit must be reset by software after entering the interrupt service routine 0 No Line 24 start interrupt has occurred ADC refer to chapter Interrupt WTmr refer to chapter Interrupt AVS 1 Acquisition vertical sync interrupt source bit set by hardware 0 Acquisition vertical sync interrupt source bit must be reset by software DVS refer to chapter Interrupt PWtmr refer to chapter Interrupt AHS 1 Acquisition horizontal sync interrupt source bit set by hardware 0 Acquisition horizontal sync interrupt source bit must be reset by software DHS refer to chapter Interrupt Semiconductor Group 47 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition Default after reset 00 CISR1 bit adressable SFR Address C8 MSB LSB CC ADW IEX1 IEX0 CC 1 Channel change interrupt source bit set by hardware 0 Chanel change interrupt source bit must be reset by software ADW refer to chapter Interrupt IEX1 refer to chapter Interrupt IEX0 refer to chapter Interrupt Note The interrupt request flags of the ACQ interrupt subnode have to be cleared by software inside the interrupt service routine 5 5 1 RAM Registers Field Parameters All field parameters are updated once in a field That means the status informatio
133. eloads with the RELOAD value and reset the OV bit 13 4 Idle and power down mode In idle mode CRT continues to function normally unless it has been explicitly shut off by PSAVEX PERI bit In power down mode CRT is shut off 13 5 Registers The RELL and RELH are the reload registers SFR address B7H and B9H CAPH and CAPL are corresponding capture registers SFR address BAH and BBH MIN_CAPL and MIN_CAPH BC BB are Minimum capture registers CRTCONO E5H and CRTCON1 are the control registers Semiconductor Group 128 User s Manual July 99 Chiu SDA 55xx technologies Preliminary amp Confidential Capture reload timer Default after reset 00 CRTCONO SFR Address BE MSB LSB OV PR PLG REL RUN RISE FALL SEL OV will be set by hardware if counter overflow has occured must be cleared by software PR if cleared 2 bit prescaler if set 3 bit prescaler PLG if set Timer polling mode selected capture function is automatically disabled reading capture registers will now show current timer value REL if set counter will be reloaded simultanously with capture event RUN run stop the CRT counter RISE capture and if REL 1 reload on rising edge FALL capture and if REL 1 reload on falling edge SEL if set P3 3 is selected for capture input otherwise P3 2 Default after reset 00 CRTCON1 SFR AddressBF MSB LSB PR1 First Start
134. els Foreground pixels of ROM characters Foreground pixels of 1 bit DRCS characters Semiconductor Group 194 User s Manual July 99 eo DA 55xx Infineon technologies Preliminary amp Confidential Display 1 0 1 Box transparency is enabled for BOX1 for following pixels Background pixels of ROM characters 0 Box transparency is enabled for BOX1 for following pixels Background pixels of 1 bit DRCS characters 1 Box transparency is enabled for BOX1 for following pixels Background pixels of ROM characters Background pixels of 1 bit DRCS characters see also 18 4 Global Display Word GDW To decide the levels of COR and BLANK for BOX1 two global parameters are used COR BOX1 BLA BOX1 Description 0 0 Box transparency levels of COR and BLANK for BOX1 are overruled by COR 0 BLANK 0 Box transparency levels of COR and BLANK coming from CLUTO inside BOX1 are overruled by COR 0 BLANK 1 Box transparency levels of COR and BLANK coming from CLUTO inside BOX1 are overruled by COR 1 BLANK 0 Box transparency levels of COR and BLANK coming from CLUTO inside BOX1 are overruled by COR 1 BLANK 1 see also 18 4 Global Display Word GDW Semiconductor Group 195 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 4 The CLUT has a maximum width of 64 en
135. en RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 REN Enables serial reception Set by software to enable reception Cleared by software to disable reception TB8 Is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB8 In modes 2 and 3 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TI Is the transmit interrupt flag Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software RI Is the receive interrupt flag Set by hardware at the end of the 8th bit time in mode 0 or halfway through stop bit time in the other modes in any serial reception Must be cleared by software SMO SM1 Mode Description Baud Rate CDC 0 0 0 0 Shift Reg Jasna 0 1 1 8 bit UART Variable 1 0 2 9 bit UART yasa 1 1 3 9 bit UART Variable In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 Semiconductor Group 118 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential UART 11 2 Multiprocessor Communication
136. ency and character matrix if all these columns are visible on the tube The programmable parameters DISALH4 to DISALHO are the binary representation of a offset value This offset value plus 33 gives the count of columns Examples for the settings DISALHA DISALH3 DISALH2 DISALH1 DISALHO Description 0 0 0 0 0 33 columns 0 0 0 0 1 34 columns 0 0 0 1 0 35 columns 0 1 1 1 1 48 columns 0 0 0 0 49 columns 1 1 1 1 0 63 columns 1 1 1 1 1 64 columns see also 18 4 Global Display Word GDW Semiconductor Group 185 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Display 18 4 2 Cursor The 2 bit color vector matrix of the cursor is stored in the XRAM A programmable pointer is used so that the matrix can be stored at any location inside the XRAM see also 18 6 3 The cursor matrix has the same resolution as the character matrix see also 18 4 8 If Global Display Double Height see also 19 is set to double height the rows which are displayed in double height the cursor is also displayed in double height For rows which are displayed in normal height the cursor is also displayed in normal height If cursor is displayed over two rows and one of these rows is displayed in double height and the other is displayed in normal height cursor is also partly displayed in double height and partly in normal height Cursor Pixels which a
137. er and slave mode 0 Normal polarity active high 1 Negative polarity RGB D 1 0 RGB COR Delay Circuitry In some applications of our customers the blanking is fed through other devices before it is used as a signal to control the multiplexing of video RGB mix These other devices may create a delay of the blank signal If no special effort is taken this delay would create a vertical band at the beginning and the end of the active blanking zone To compensate this the generated RGB and the COR signals can be delayed by TVTpro in reference to the generated blank signal This delay is always a multiple of the pixel frequency from zero delay up to 3 times pixel delay 00 zero delay of RGB COR output in reference to BLANK output 01 one pixel delay of RGB COR output in reference to BLANK output 10 two pixel delay of RGB COR output in reference to BLANK output 11 three pixel delay of RGB COR output in reference to BLANK output Semiconductor Group 157 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Bit Function VSU 3 0 Vertical Set Up Time Slave mode only The vertical sync signal is internally sampled with the next edge of the horizontal sync edge The phase relation between V and H differs from application to application To guarantee vertical jitter free processing of external sync signals the vertical sync impulse can be delayed before it
138. errupt enable and interrupt priority registers The processor acknowledges the interrupt by setting one of the four internal priority level active flip flops and performing a hardware subroutine call This call pushes the PC but not the PSW onto the stack and for some sources clears the interrupt request flag The service program is executed Control is returned to the main program when the RETI instruction is executed The RETI instruction also clears one of the internal priority level active flip flops The interrupt request flags IEO IE1 TFO and TF1 are cleared when the processor transfers control to the first instruction of the interrupt service program Semiconductor Group 97 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts Semiconductor Group 98 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Power Saving modes 8 Power Saving modes The controller provides four modes in which power consumption can be significantly reduced Idle mode The CPU is gated off from the oscillator All peripherals except WDT in watch dog mode are still provided with the clock and are able to work Power down mode Operation of the controller is turned off This mode is used to save the contents of internal RAM with a very low standby current e Power save mode In this mode display generator Slicer acq sync VADC CADO
139. ess C1 C6 MSB LSB PC8X 7 PC8X 6 PC8X 5 PC8X 4 PC8X 3 PC8X 2 PC8X 1 PC8X 0 Bit 7 Bit 2 These bits define the high time of the output If all bits are 0 the high time is 0 internal clocks If all bits are 1 the high time of a base cycle is 63 internal clocks Bit 1 If this bit is set every second PWM Cycle is stretched by one internal clock regardless of the settings of Bit7 Bit2 Bit 0 If this bit is set every fourth PWM Cycle is stretched by one internal clock regardless of the settings of Bit7 Bit2 Default after reset 004 PWM COMP14 0 1 SFR Address C7 C9 MSB LSB PC14X 7 PC14X 6 PC14X 5 PC14X 4 PC14X 3 PC14X 2 PC14X 1 PC14X 0 Bit 7 Bit 0 This bits define the high time of the output If all bits are 0 the high time is 0 internal clocks If all bits are 1 the high time of a base cycle is 255 internal clocks Semiconductor Group 138 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Pulse Width Modulation Unit Default after reset 00 PWCOMPEXT14Y 0 1 SFR Address MSB LSB PCX14Y 7 PCX14Y 6 14 5 PCX14Y 4 PCX14Y_3 PCX14Y_2 PCX14Y_1 PCX14Y_0 Bit 7 If this bit is set every second PWM Cycle is stretched by one internal clock Bit 6 If this bit is set every fourth PWM Cycle is stretched by one internal clock Bit 5 If this bitis set
140. every eighth PWM Cycle is stretched by one internal clock Bit 4 If this bit is set every 16th PWM Cycle is stretched by one internal clock Bit 3 If this bit is set every 32th PWM Cycle is stretched by one internal clock Bit 2 If this bit is set every 64th PWM Cycle is stretched by one internal clock Bit 1 PWCOMEXT14_1 this bit is reseved for future use PWM_direct PWCOMEXT14_0 PWM_ direct If set the counting rate of the PWM and the timer is direct the incoming clock 33 33 MHz or 8 33 MHz in Slow Down Mode then the Bit PWM_PR is ignored This bit effects all PWM channels and the timer mode Bit 0 PWCOMEXT14_1 this bit is reseved for future use PWM_PR PWCOMEXT14_0 PWM_PR when this bit is set input counting frequency is divided by 2 PR bit Note The described operation is independent of the setting of PI COMP14 x Note The stretch operation is interleaved between PWM Cycles Semiconductor Group 139 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Default after reset 00 PWCL MSB Pulse Width Modulation Unit SFR Address LSB PWC7 6 5 4 PWC 3 PWC 2 PWC 1 PWC O Bit 7 Bit 0 This bits are the low order 8 Bits of the 14 Bit PWM Counter This register can only be read Default after reset 00 PWCH SFR Address CD MSB LSB PWM Tmr OV PWC 13
141. example a normal PAL timing should be generated set this register to 625d and set the interlace bit to 0 The hardware will generate a vertical impulse periodically after 312 5 lines If a non interlace picture with 312 lines should be generated set this register to 312 and set the interlace bit to 1 The hardware will generate a vertical impulse every 312 lines A progressive timing can be generated by setting VLR to 625 and interlace to 07 Semiconductor Group 164 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Sync System Reset 08 HPR1 SFR Address F1 MSB LSB HPR 11 HPR 10 HPR 9 HPR 8 Reset 55 HPRO SFR Address F2 MSB LSB HPR 7 HPR 6 HPR 5 HPR 4 HPR 3 HPR 2 HPR 1 HPR 0 Bit Function HPR 11 0 Horizontal Period factor Master mode only This register allows to adjust the period of the horizontal sync signal The horizontal period is independent from the pixel frequency and can be adjusted with the following resolution HP 30 ns Semiconductor Group 165 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Sync System Reset 00 SDV1 SFR Address E34 MSB LSB SDV 9 SDV 8 Reset 20 SDVO SFR Address E4 MSB LS
142. ff and it outputs the values defined for DAC off COR BLA output their reset value PERI Peripherals Watchdog timer in timer mode PWM and CRT Default after reset MSB 0 Power save Mode not started 1 Power save Mode started In Power save mode WDT in timer mode PWM and CRT are disabled It is only possible to enterthis power save mode if watchdog is not started in a watchdog mode 00 PSAVEX bit addressable SFR Address D7 LSB Src PLL rst PLLS CLK Src Not used CLock Source 0 200 Mhz PLL 33 33Mhz system clock selected 1 PLL is bypassed oscillator clock 6 MHz 3Mhz system clock selected In this mode slicer acquisition DAC and display generator are disabled Semiconductor Group 100 User s Manual July 99 e SDA 55xx Infineon technologies Preliminary amp Confidential Power Saving modes PLL rst PLL reset 0 PLL not reset 1 PLL reset PLL reset sequence requires that PLL rst 1 for 10 micro second then PLL rst 0 after that 150 microsecond are required till PLL is locked PLLS PLL Sleep Semiconductor Group 0 Power save Mode not started 1 Power save Mode started Before the PLL is switched to power save mode PLLS 1 the SW has to switch the clock source from 200 Mhz PLL clock to the 6 MHZ oscillator clock CLK Src 1 To switch back to the normal mode software has to end the PLL power save mode PLLS 0 reset the PLL for 10 micro sec
143. generates the secondary control signals automatically as long as the pin corresponding to the appropriate signal is programmed as an input i e if the corresponding bit latch in the special function register contains a one Read Modify Write Feature Read modify write commands are instructions that read a value possibly change it and then rewrite it to the latch When the destination operand is a port or a port bit these instructions read the latch rather than the pin The read modify write instructions are listed in table 8 The read modify write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a one is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a 0 Reading the latch rather than the pin will return the correct value of one Fig Read Modify Write Instructions Mnemonic Description Example ANL logical AND ANL P1 A ORL logical OR ORL P2 A XRL logical EX OR XRL P3 JBC jump if bit 2 1 and clear bit JBC P1 1 LABEL CPL complement bit CPL P3 0 INC increment INC P1 DEC decrement DEC P1 DJNZ decrement and jump if not zero DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of Port X MOV P1 7
144. gnalling WSS data used for PAL plus transmissions line 23 The device provides an integrated general purpose fully 8051 compatible Microcontroller with television specific hardware features Microcontroller has been enhanced to provide powerful features such as memory banking data pointers and additional interrupts etc The on chip display unit for displaying Level 1 5 teletext data can also be used for customer defined on screen displays Internal XRAM consists of up to 16 KBytes Device has an internal ROM of up to 128 KBytes ROMless versions can access up to 1MByte of external RAM and ROM The SDA 55xx supports a wide range of standards including PAL NTSC and contains a digital slicer for VPS WSS PDC and TTX an accelerating acquisition hardware module a display generator for Level 1 5 TTX data and powerful On screen Display capabilities based on parallel attributes and Pixel oriented characters DRCS The 8 bit Microcontroller runs at 360 ns cycle time min Controller with dedicated hardware does most of the internal TTX acquisition processing transfers data to from the external memory interface and receives transmits data via I C firmware user interface The slicer combined with dedicated hardware stores data in a VBI buffer of 1 Kilobyte The Microcontroller firmware performs all the acquisition tasks hamming and parity checks page search and evaluation of header control bits once per field Additionally t
145. gning priority the 24 possible interrupt sources are divided into groups determined by their bit position in the Interrupt Enable Registers and their respective requests are scanned in the order shown below Interrupt Interrupts in Group Group Group gt Priority High Priority 0 External High Priority Interrupt 0 1 Timer 0 ExternalX Interrupt O 2 External WT PW Interrupt 1 Timer Timer 3 Timer 1 ExternalX Channel Interrupt 1 Change 4 UART Acquisition Acquisition Line 24 V Sync H Sync Start Y 5 AtoD Display Display Ato D V Sync H Sync Wake up Not implemented Each interrupt group may individually be assigned to one of four priority levels by writing to the IPO and IP1 Interrupt Priority registers at the corresponding bit position An interrupt service routine may only be interrupted by an interrupt of higher priority level and if two interrupts of different priority occur at the same time the higher level interrupt will be serviced first An interrupt cannot be interrupted by another interrupt of the same or a lower priority level If two interrupts of the same priority level occur simultaneously the order in which the interrupts are serviced is determined by the scan order shown above Semiconductor Group 90 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential 7 6 1 Interrupt Priority registers IP0 IP1 The Interrupt Priority registers
146. he firmware can provide high end Teletext features like Packet 26 handling FLOF TOP and list pages The interface to the user software is optimized for minimal overhead SDA 55 is realized 0 25 micron technology with 2 5V supply voltage and 3 3V TTL compatible The software and hardware development environment TEAM is available to simplify and speed up the development of the software and On Screen Display TEAM stands for TVT Expert Application Maker It improves the TV controller software quality in following aspects Shorter time to market Re usability Target independent development Verification and validation before targeting General test concept Graphical interface design requiring minimum programming and controller know how Modular and open tool chain configurable by customer Semiconductor Group 11 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential 1 5 Features General Feature selection via special function register Simultaneous reception of TTX VPS PDC and WSS line 23 Supply Voltage 2 5 and 3 3 V ROM version package P SDIP 52 P MQFP64 e Romless version package P MQFP100 P L CC84 External Crystal and Programmable clock speed Single external 6MHz crystal all necessary clocks are generated internally CPU clock speed selectable via special function registers Normal Mode 33 33 Mhz CPU clock Power Save mod
147. he sync output at pin V Master mode only 0 V the vertical sync appears 1 Atpin V a composite sync signal including equalizing pulses H Sync and V Syncs is generated VCS The length of the equalizing pulses have fixed values as described in the timing specifications Note Don t forget to set registers VLR and HPR 64us according to your requirements Semiconductor Group 156 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Bit Function SNC Sandcastle Sync Slave mode only Two input pins are reserved for synchronisation These input pins can be used as two seperated sync inputs or as one single sync input If two Seperated sync inputs is selected horizontal syncs are fed in at H pin and vertical syncs are fed in at V pin If one single input pin is selected H pin is used as a sandcastle input pin 0 H V sync input at H V pins 1 Sandcastle input H pin INT Interlace Non interlace TVTpro can either generate an interlaced or a non interlaced timing Master mode only Interlaced timing can only be created if VLR is an odd number 0 Interlaced timing is generated 1 Non nterlaced timing is generated VP V Pin Polarity This bit defines the polarity of the V pin master and slave mode 0 Normal polarity active high 1 Negative polarity HP H Pin Polarity This bit defines the polarity of the H pin Mast
148. ial Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands 77 2 MOV R1 data 78 2 MOV RO data 79 2 MOV R1 data 7A 2 MOV R2 data 7B 2 MOV data 7C 2 MOV R4 data 7D 2 MOV R5 data 7E 2 MOV R6 data 7F 2 MOV R7 data 80 2 SJMP code addr 81 2 AJMP code addr 82 2 ANL C bit addr 83 1 MOVC A QA PC 84 1 DIV AB 85 3 MOV data addr data addr 86 2 data addr ORO 87 2 MOV data addr R1 88 2 MOV data addr R0 89 2 MOV data addr R1 8A 2 MOV data addr R2 8B 2 MOV data addr R3 8 2 MOV data addr R4 8D 2 MOV data addr R5 8E 2 MOV data addr R6 8F 2 MOV data addr R7 90 3 MOV DPTR data 16 91 2 ACALL code addr 92 2 MOV bit addr C 93 1 MOVC A A DPTR 94 2 SUBB A data Semiconductor Group 78 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands 95 2 SUBB A data addr 96 1 SUBB A ORO 97 1 SUBB A OR1 98 1 SUBB A RO 99 1 SUBB A R1 9A 1 SUBB A R2 9B 1 SUBB A R3 9C 1 SUBB A R4 9D 1 SUBB A R5 9E 1 SUBB A R6 9F 1 SUBB A R7 0 2 ORL C bit addr A1 2 A
149. ies Preliminary amp Confidential Microcontroller incremented during a push SP can be read or written to under software control The stack may be located anywhere within the internal data RAM address space and may be as large as 256 bytes Note that for memory above 64K mmeory extension stack is used refer to Chapter Memory Extension 6 1 1 8 Data Pointer Register DPTR The 16 bit Data Pointer Register DPTR is the concatenation of registers DPH high order byte and DPL low order byte The DPTR is used in register indirect addressing to move program memory constants and to access the extended data memory DPTR may be manipulated as one 16 bit register or as two independent 8 bit registers DPL and DPH Eight data pointer registers are available the active one is selected by a special function register DPSEL Default after reset 00 DPL SFR Address 844 MSB LSB DPL 7 DPL 6 DPL 5 DPL 4 DPL 3 DPL 2 DPL 1 DPL 0 DPL X Data Pointer low byte Default after reset 00 DPH SFR Address 844 MSB LSB DPH 7 DPH 6 DPH 5 DPH 4 DPh 3 DPH 2 DPH 1 DPH 0 DPH X Data Pointer high byte Default after reset 00 DPSEL SFR Address 844 MSB LSB DPSEL 2 DPSEL 1 DPSEL 0 DPSEL X Selects one of the eight Data Pointers Semiconductor Group 62 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential
150. imer If Capture value is less then or equal to min cap value or OV bit has been set that is spike has been detected and Interrupt is suppreessed OV bit would be reset counter would be reloaded with reload value regarless of REL bit In this case If either RISE or FALL bit were set then counter will wait for the second event FIRST 21 if RISE and FALL both were set then counter will wait for the Flrst event FIRST 20 13 3 11 CRT Interrupt CRT can generate interupt when SSU is employed CRT unit uses the same interrupt line as INT1 and INTO The interrupt line is selected by the SEL bit Note that when using CRT to generate interrupt the direct interrupt source from Port 3 2 or 3 3 which ever is selected should be switched to CRT CSCR1 IntSrc0 CSCR1 IntSrc1 If application uses port pins directly to generate interrupt then these bits should be reset Note that by default INT1 and INTO are mapped to P3 3 and P3 2 SSU generates interrupt signal as a pulse which is captured in the int source register TCON IE1 or IEO While using this mode TCON ITO or IT1 must be set to 1 edge triggered and PCON EX1R or EXOR must be set to 1 and PCON EX1F or EXOF must be set to O For further information on interrupts please refer to the interrupt section of this document 13 3 12 Counter Stop Counter can be stopped any time by resetting the RUN bit If counter is stopped and started again reset and set the RUN bit counter r
151. irst and a stop bit 1 On reception the stop bit goes into RB8 in special function register SCON The baud rate is variable Mode 2 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmission the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On reception the 9th data bit goes into RB8 in the special function register SCON while the stop bit is ignored The baud rate is programmable via SFR Bit SMOD Mode 3 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable Semiconductor Group 117 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential UART Serial Port Control RegisterSCON SFR Address 98 Default after reset 004 MSB LSB SM0 SM1 SM2 REN TB8 RB8 TI RI SM0 Serial Port Mode Selection see table below SM1 Serial Port Mode Selection see table below SM2 Enables the multiprocessor communication feature in modes 2 and 3 In mode 2or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit 8 is 0 In mode 1 if SM2 1 th
152. is action allows the user to place interrupt service routines on specific banks 7 9 Interrupt Handling Exteranl interrupt 0 external interrupt 1 timer 0 timer 1 abd UART interrupt are handled as following Interrupts are sampled at S5P2 in each machine cycle and the sampled interrupts polled during the following machine cycle If an interrupt is set when it is sampled it will be serviced provided An interrupt of an equal or higher priority is not currently being serviced The polling cycle is not the final cycle of a multi cycle instruction and The current instruction is neither a RETI nor a write either to one of Interrupt Enable registers or to one of the Interrupt Priority registers Semiconductor Group 93 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Interrupts Note Active interrupts are only stored for one machine cycle As a result if an interrupt was active for one or more polling cycles but not serviced for one of the reasons given above the interrupt will not be serviced For all other interupts interrupt request is stored as an interrupt flag in CISR0 and CISR1 These request bits must be cleared by software while servicing the interrupt These interrupts always gets serviced once raised regardless of number of polling cycles required to service them The rest of the functionality with regards to sampling from controller and requirements to start the service
153. is method Execution of PUSH and POP instructions also use register indirect addressing The stack pointer may reside anywhere in internal RAM 6 1 3 4 Immediate Addressing Immediate addressing allows constants to be part of the opcode instruction in program memory An additional byte is appended to the instruction to hold the source variable In the assembly language and instruction set a number sign precedes the value to be used which may refer to a constant an expression or a symbolic name 6 1 3 5 Base Register plus Index Register indirect Addressing Base register plus index register indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a Semiconductor Group 64 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Microcontroller base register DPTR or PC and index register ACC This mode facilitates accessing to look up table resident in program memory 6 2 Ports and There 34 Port pins available out of which are 24 l O pins are configured as three 8 bit ports PO P1 and Port 4 consists of 6 I O bits out of which are available in SDIP52 all 6 bits are available in rest of the packages Each pin can be individually and independently programmed as input or output and each can be configured dynamically One 4 bit port P2 is input only An instruction that uses a
154. l but can be loaded with the field parameters If the third one is used the user can specify not only the FC but also a don t care mask The fourth FC is reserved for WSS The actual FC can be changed line by line FC1 This FC should be used for all services with 8 bit framing codes e g for TTX The actual framing code is loaded down each field The check can be done without any error tolerance or with a one bit error tolerance FCVPS This FC is fixed to that of VPS Only an error free signal will enable the reception of the VPS data line Note If VPS should be sliced in field 1 and TTX in field 2 the appropriate line parameters for line 16 have to be changed dynamically from field to field Semiconductor Group 42 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Slicer and Acquisition FC3 This 16 bit framing code is loaded with the field parameters as well as a don t care mask The incoming signal is compared with both framing code and don t care mask Further reception is enabled if all bits which are not don t care match the incoming data stream FCWSS This FC is fixed to that of WSS Only an error free signal will enable the reception of the WSS data line FC Check Select There is a two bit line parameter called FCSEL By means of this parameter the user will be able to select which FC Check is used for the actual line If NORM is set to WSS the WSS FCcheck is used i
155. latch leaves the output transistor off so the pin floats In that condition it can be used as a high impedance input Port 0 is considered true bidirectional because when configured as an input it floats Ports 1 3 and 4 have quasi bidirectional output drivers In ports P1 P3 and P4 the output drivers provide source current for one system clock period if and only if software updates the bit in the output latch from a zero to an one Sourcing current only on zero to one transition prevents a pin programmed as an input from sourcing current into the external device that is driving the input pin Semiconductor Group 65 User s Manual July 99 e _ Infineon SDA DRR technologies Preliminary amp Confidential Microcontroller pon vo pateu um med Toggle Function Toggle Function Control bit Function Control bit Function P0 0 7 0 Port pin P1 0 0 Portpin PWME EO PWM 8 bit channel 0 1 0 Portpin PWME E1 PWM 8 bitchannel 1 P1Q 0 Portpin PWME E2 PWM 8 bit channel 2 P1 3 0 Portpin PWME E3 PWM 8 bit channel 3 P1 4 0 Portpin PWME E4 PWM 8 bitchannel 4 P1 5 0 Portpin PWME E5 PWM 8 bit channel 5 P1 6 O Portpin PWME E6 PWM 14 bit channel 0 P17 O Portpin PWME E7 PWM 14 bit channel 1 P2 0 Port pin CADCCO ADO ADC channel 0 P2 1 Port pin CADCCO
156. lay timings and baudrate prescaler have to be adapted in appropriate way In some applications the timing reference given by the horizontal frequency of the CVBS signal can be used to measure the timing tolerance and to adjust the programming 66 67 33 33 uc E 6MHz 3MHz t 9 5 uC Periph 2 e Ports B Ze XTPADIN Y D or 8 33 or jus 2007 833 3MHzor T 1 i OSC PLL MHz ext clk Slicer lt 6 MH 1 gt DG XTPADOUT OSCCL CLK src CLUTs gt F o oo ME e y Display FIFO o Q DTO DAC Ext pixel clock 10 32MHz Hin CLKE PF Figure 5 Clock System of TVTpro The on chip phase locked loop PLL which is internally running at 300 MHz is fed by the oscillator or can be bypassed to reduce the power consumption If it is not required to wake up immediately the PLL can also be switched off Semiconductor Group 33 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Clock System From the output frequency of the PLL two clock systems are derived The 33 33 MHz system clock provides the processor all processor related peripherals the sync timing logic the A D converters the slicer the DG and the CLUTs It will be possible to use 8 33MHz 1 4 of 33 33MHZz for
157. logies Preliminary amp Confidential Reset 9 Reset 9 1 Reset sources TVText Pro can be reset by two sources 1 Externally by pulling down the reset pin RST 2 Internally by Watch dog timer reset Note that both the reset signals use the same path however Watchdog reset doesnot reset the PLL 9 2 Reset filtering RST pin uses a filterwith delay element which suppresses the jitter and spikes in the range of 25 nsec to 75 nsec 9 3 Reset duration With the active edge of the RST an internal signal resets all the flip flops asynchrounsly The internal signal is released synchronusly to the internal clock when it is stable as described below Duration of the external reset depends on the time required for crystal oscilator to stablize and is dependend on the crystal used During the period when the RST pin is held low the PLL is initialized and it gets locked The high going reset pulse then initiates a sequence which requires one machine cycle 12 clock cycles to initialize the processor and all other registers and peripherals 9 4 Registers Upon reset all the registers are initialized to the values as defined in Register overview chapter 9 5 Functional blocks All the blocks to a known a known state Processor Acquisiton and display will not have any pending bus requests after reset 9 6 RAMs Reset hardware does not intialize any RAMs Semiconductor Group 105 User s Manual July 99 Infineon SDA 55xx
158. n written from the acquisition interface to the memory represent only a snapshot of the status Default after reset 00 ACQFPO MSB LSB FC3 15 FC3 14 FC3 13 FC3 12 FC3 11 10 FC3 9 FC3 8 FC3 15 8 Framing code 3 High Byte Bit 15 First received bit of FC Semiconductor Group 48 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Slicer and Acquisition Default after reset 00 ACQFP1 MSB LSB FC3 7 FC3 6 FC3 5 FC3 4 FC3 3 FC3 2 FC3 1 FC3 0 FC3 7 0 Framing code 3 Low Byte Bit 0 Last received bit of FC Default after reset 004 ACQFP2 MSB LSB FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK 15 14 13 12 11 10 9 8 FC3MASK 15 8 Mask for Framing code 3 High Byte Bit 15 Mask for first received bit of FC Default after reset 004 ACQFP3 MSB LSB FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK FC3MASK 7 6 5 4 3 2 1 0 FC3MASK 7 0 Mask for Framing code 3 Low Byte Bit 0 Mask for last received bit of FC Semiconductor Group 49 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition Default after reset 004 ACQFP4 MSB LSB FC1 7 FC1 6 FC1 5 FC1 4
159. n has the same functionality in both watch dog mode and timer mode 15 2 Starting WDT WDT can be started if the WDT unit is in the Watch dog mode WDT Tmr 0 WDT is started by setting the bit WDT Start in the WDT Ctrl register Immediately after the start 1 clock cycle the reload value from WDT Rel register is copied to the WDT High WDT Low is always reset to 0 upon start Value can be written to WDT Rel any time during normal controller operation Value is only loaded to the counter upon start refresh or watchdogreset if WDT nARST is set Note that Counter registers are read only and cannot be directly written by the controller 15 3 Refresh Once WDT is started it cannot be stopped by software Note that while WDT is running any change to WDT tmr bit would be ignored A refresh to the WDT is required before the counter overflows Refreshing WDT requires two instruction sequence whereby first instruction sets Ref bit and the next instruction sets the WDT Start bit For exmaple if there is NOP between these two instructions refresh would be ignored This double instruction refresh minimize the chances of unintentional reset of the watchdog timer Once set WDT Ref bit is reset by the hardware after three machine cycles Refresh causes WDT low to reset to 00h and loads the reload value to from WDT Rel to WDT High Semiconductor Group 141 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp
160. n the data correcting circuit Semiconductor Group 40 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Slicer and Acquisition Frequency Attenuation During signal transmission the CVBS is attenuated severely This attenuation normally is frequency depending That means that the higher the frequency the stronger the attenuation As the clock run in from now on CRI for teletext represents the highest possible frequency 3 5MHz it can be used to measure the attenuation As only strong negative attenuation causes problems during data slicing a flag is needed to notify highly negative attenuation If this flag is set a special peaking filter is switched on in the correcting circuit part Group Delay Quite often the data stream is corrupted because of group delay distortion introduced by the transmission channel The teletext framing code E4 is used as a reference for measurement The delay of the edges inside this code can be used to measure the group delay distortion The measurement is done every teletext line and filtered over several lines It can be detected whether the signal has positive negative or no group delay distortions Two flags are set accordingly By means of this two flags an allpass contained in the correcting circuit is configured to compensate the positive or negative group delays 5 2 2 Data Separation Parallel to the signal analyses and distortion compensation a fil
161. nction of the Arithmetic Logic Unit ALU 6 1 1 2 Program Control Section The program control section controls the sequence in which the instructions stored in program memory are executed The conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution The 16 bit program counter holds the address of the instruction to be executed It is manipulated with the control transfer instructions listed in chapter Instruction Set 6 1 1 3 Internal Data RAM The internal data RAM provides a 256 byte scratch pad memory which includes four register banks and 128 direct addressable software flags Each register bank contains registers RO R7 The addressable flags are located in the 16 byte locations starting at byte address 20 and ending with byte location 2F of the RAM address space In addition to this standard internal data RAM the processor contains an extended internal RAM It can be considered as a part of an external data memory It is referenced by MOVX instructions MOVX A DPTR the memory organization is explained in the chapter Memory 6 1 1 4 Arithmetic Logic Unit ALU The arithmetic section of the processor performs many data manipulation functions and includes the Arithmetic Logic Unit ALU and the A B and PSW registers The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction de
162. ndependently of FCSEL 5 4 2 Interrupts Some events which occur inside the slicer sync separation or acquisition interface should cause an interrupt They are summarized in register CISRO and CISR1 The hardware sets the associated interrupt flag which must be manually reset by software before the next interrupt can be accepted 5 4 3 VBI Buffer and Memory Organization Slicer and acquisition interface need parameters for configuration and produce status information for the CPU Some of these parameters and status bits are constant for a field Those parameters are called field parameters They are downloaded after the vertical sync Other parameters and status bits may change from line to line e g data service depending values Those parameters are called line parameters They are downloaded after each horizontal sync impulse The start address of the VBI buffer can be configured with a special function register STRVBI 9 bytes are needed for the field parameter 47 byte should be reserved for every sliced data line If 18 lines of data in full channel mode 314 have been send to memory no further acquisition takes place until the next vertical pulse appears and the H PLL is still locked That means if at least 855 Bytes 14767 Bytes in full channel mode are reserved for the VBI buffer VBI overflow is possible The acquisition can be started and stopped by the controller using bit ACQON of register STRVBI The acquisition is st
163. nerator are switched off Note Bit PLLS can only be set if bit CLK_src 1 PLL_rst 0 no PLL reset 1 PLL hold in reset CLK_src 0 System clock 33 3MHz derived from 200MHz PLL clock 1 System clock 3MHz derived from 6MHz oscillator clock Note Before the PLL is switched to power save mode PLLS 1 the SW has to switch the clock source from 200MHz PLL clock to the 2 oscillator clock CLK_src 1 In this mode the Slicer Acquisition DAC and Display Generator are switched off To switch back the SW has to end the PLL power save mode PLLS 0 reset the PLL for 10us 3 machin cycles PLL_res 1 then 0 again then wait 150 5 38 machine cycles and switch back to the PLL clock CLK_src 0 Semiconductor Group 37 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Clock System Semiconductor Group 38 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Slicer and Acquisition 5 Slicer and Acquisition 5 1 General Function TVTpro provides a full digital slicer including digital H and V sync separation and digital sync processing The acquisition interface is capable to process on all known data services starting from line 6 to line 23 for TV Teletext VPS CC G WSS Four different framing codes two of them programmable from field to field are available for each field Digital signal processing algorithms are applied to c
164. nfineon technologies SDA 55xx Preliminary amp Confidential SFR Overview Add Long name Short Name Bit Reset Location Bit6 Bit Bit4 Bit2 Bitt Bito Add Value CF 00 Program Status Word PSW Yes 00 Miro CY AC Fo RS1 850 ov Fi P 01 ADC channel 0 result CADCO No ADC CADCO CADCO cancos CADCOU cancos CADCO CADCO i CADCO 0 02 ADC channel 1 result CADC1 No 00 ADC CADCI 1 6 capcis CADC1 4 capcis canci CADC i CADCi 0 03 ADC channel 2 result CADC2 No 00 ADC 2 26 2 5 24 2 3 CADC2 CADC2 20 04 ADCchannel3result CADC3 No ADC CADC3 7 CADC3 6 CADC3 5 CADC3 4 CADC3 3 canca CADC3 i cancao 05 ADC Configuration CADCCO No 00 ADC ADWULE AD3 AD2 ADI ADO D6 No 00 07 Power save Extra Reg PSAVEX No 00 PSave SRC PLLRST PLLS 08 PowerSaveRegister PSAVE Yes 00 PSave CADC su aca DISP PERI D9 Config ACQ amp Slicer STRVBI 0 Acq ACQON Reserved ACQSTA VBIADR 3 VBIADR 2 VBIADR 1 VBIADR 0 DA DTO pixel freq factor 0 PCLKO No 01 DTO E E E H PF 10 PF 9 PF 8 DB pixel freq factor 1 PCLK1 No 48 PF 7 PF 6 PF 5 PF 4 PF 3 PF 2 PF 1 PF 0 DC No
165. nks 10 3 Memory Extension The controller provides four additional address lines A16 A17 A18 and A19 These additional address lines are used to access program and data memory space up to 1MByte The extended memory space is split into 16 banks of 64Kbyte each A16 is available as a dedicated pin however A17 A18 and A19 work as alternate func tion to port pins P4 0 P4 1 and P4 4 respectively Refer to register CSCR 1 A19 P4 4 A18 P4 1 A17 4 0 Semiconductor Group 109 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Memory Organization The operations to the extended memory space are controlled by four special function registers called MEX1 MEX2 and MEXSP The functionality for memory extension is provided by a module Memory management unit MMU which includes the four SFR registers MEX1 MEX2 MEX3 and MEXSP 10 3 1 Memory extension registers The following registers are present in the Memory management unit These registers can be read and written through MOV instructions like any other SFR registers Except for CB bits in MEX1 which are read only they can only be written by MMU During normal operation user must not write in the MEXSP Memory Extension Register 1 Default after reset 00 MEX1 SFR Address 944 MSB LSB CB19 CB18 CB17 CB16 NB19 NB18 NB17 NB16 NB Next Bank R W CB Current Bank Read Only Comments None
166. nter 1 DRCS DRCS DRCS DRCS Description B13 12 B1_1 10 Boundary1 set to 768d Boundary1 set to 784d Boundary1 set to 800d Boundary1 set to 816d 0 0 0 1 1 0 1 1 0 Boundary1 set to 992d 1 1 1 1 Boundary1 set to 1008d see also 18 4 Global Display Word GDW Boundary Pointer 2 Please notice DRCSB2_3 DRCSB2_0 must be set to a greater or a equal value than DRCSB1_3 DRCSB1_0 Semiconductor Group 175 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display DRCS DRCS DRCS DRCS Description B23 22 21 B20 Boundary1 set to 768d Boundary1 set to 784d Boundary1 set to 800d Boundary1 set to 816d 1 1 1 Boundary1 set to 992d 1 1 1 1 Boundary1 set to 1008d see also 18 4 Global Display Word GDW m E E Below some examples can be found to show which way the character addressing depends on the boundary definitions Semiconductor Group 176 User s Manual July 99 oe nfineon technologies SDA 55xx Preliminary amp Confidential Example 1 Boundary Pointer 1 set to 848d Boundary Pointer 2 set to 928d Display Character Address Description From To 768 847 1 bit DRCS characters 848 991 2 bit DRCS characters 928 1023 4 bit
167. ntial UART Semiconductor Group 120 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential General Purpose Timers Counters 12 General Purpose Timers Counters Two independent general purpose 16 bit timers counters are integrated for use in measuring time intervals measuring pulse widths counting events and causing periodic repetitive interrupts Either can be configured to operate as timer or event counter In the function the registers TLx and or THx x 0 1 are incremented once every machine cycle Thus one can think of it as counting machine cycles A machine cycle consists of 12 oscillator periods In the counter function the registers TLx and or THx x 0 1 incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled during every machine cycle When the samples show a high one cycle and a low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes 2 machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for a
168. o zero The duty cycle can be adjusted in steps of f pwm as mentioned in the table In order to achieve the same resolution as 14bit counter the high time is stretched periodically by one clock cycle Stretching cycle is determined based on the bit 7 1 in the corresponding PI COMPEXT 14x register PWCOMPEXTI4X Cycle streched Bit 7 1 3 5 7 59 61 63 Bit 6 2 6 10 54 58 62 Bit 5 4 12 20 52 60 Bit 4 8 24 40 56 Bit 3 16 48 Bit 2 32 Semiconductor Group 135 User s Manual July 99 Infineon SDA 55xx tecnnologies 14 5 Cycle time Counting Base Full PWM Slow PWM_ Fsys Resolutio Down PR direct MHz Rate cycletime cycletir n SD L l MHz us us 0 0 0 33 33 16 66 3 84 15 37 8Bit 1 0 0 8 33 833 7 68 30 7 0 1 0 33 33 8 33 7 68 30 7 1 1 0 8 33 4 16 15 37 61 46 0 X 1 33 33 33 33 1 92 7 68 1 X 1 8 33 8 33 7 68 30 7 0 0 0 33 33 16 66 15 37 983 4 14 Bit 1 0 0 8 33 8 33 30 7 1967 0 1 0 33 33 8 33 30 7 1967 1 1 0 8 33 4 16 61 4 3934 0 x 1 33 33 33 33 7 68 492 1 X 1 8 33 8 33 30 7 1967 14 6 Power down idle and Power save mode In idle mode PWMU continues to function normally unless it has been explicitly shut off by PSAVE PERI Note that in In Psave mode all channels are frozen and pins are switch to port output mode making it possible
169. oad as shown in figure 12 1 3 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged Mode Timer counter 0 in mode 3 establishes TLO and THO as two separate counters TLO uses the timer 0 control bits C T GATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter With timer 0 in mode 3 the processor can operate as if it has three timers counters When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used in any application not requiring an interrupt 12 1 1 Timer Counter 1 Mode Selection Timer counter 1 can also be configured in one of four modes which are selected by its own bitpairs M1 MO in TMOD register The serial port receives a pulse each time that timer counter 1 overflows This pulse rate is divided to generate the transmission rate of the serial port Modes 0 and 1 are the same as for counter 0 Mode2 The reload mode is reserved to determine the frequency of the serial clock signal not implemented Mode 3 When counter 1 s mode is reprogrammed to mode 3 from mode 0 1 or 2 it disables the increment counter This mode is provided as an
170. obal disable signal for the interrupt controller 7 4 1 Interrupt Enable registers IEO IE1 IE2 IE3 The processor has 4 Interrupt Enable registers The details of the registers are as follows For each bit in these registers a 1 enables the corresponding interrupt and a 0 disables it Default after reset 00 IEO bit addresseble SFR Address A84 MSB LSB EAL EAD EU EX1 ETO EXO EAL Enable All Interrupts When set to 0 all interrupts are disabled When set to 1 interrupts are individually enabled disabled according to their respective bit selection Reserved EAD Enable or disable Analog to digital convertor Interrupt EU Enable or disable UART nterrupt ET1 Enable or disable Timer 1 Overflow Interrupt EX1 Enable or disable External Interrupt 1 ETO Enable or disable Timer 0 Overflow Interrupt EXO Enable or disable External Interrupt 0 Semiconductor Group 85 User s Manual July 99 Infineon SIXX technologies Preliminary amp Confidential Interrupts Default after reset 004 SFR Address A94 MSB LSB EDV EAV EXX1 EWT EXX0 EX6 Not implemented Return 0 when read EDV Enable or disable Display V Snc EAV Enable or disable Acquisition V Snc EXX1 Enable or disable extra external interrupt 1 EWT Enable or disable Watchdog in timer mode EXXO Enable or disable extra External Interrupt
171. ocontroller Figure 11 Data Transfer Operations Mnemonic Description Byte MOVA Rn Move register to Accumulator MOVA direct Move direct byte to Accumulator MOVA Ri Move indirect RAM to Accumulator MOVA data Move immediate data to Accumulator MOVRn A Move Accumulator to register MOVRn direct Move direct byte to register MOVRn data Move immediate data to register MOVdirect A Move Accumulator to direct byte MOVdirect Rn Move register to direct byte MOVdirect direct Move direct byte to direct MOVdirect Ri Move indirect RAM to direct byte MOVdirect data Move immediate data to direct byte MOV Ri A Move Accumulator to indirect RAM MOV Ri direct Move direct byte to indirect RAM MOV Ri data Move immediate data to indirect RAM MOVDPTR data 16 Load Data Pointer with a 16 bit constant MOVCA A DPTR Move Code byte relative to DPTR to Accumulator MOVCAQGA PC Move Code byte relative to PC to Accumulator MOVXA Ri Move External 8 bit addr to Accumulator MOVXA DPTR Move External RAM 16 bit addr to Accumulator MOVX Ri Move A to External RAM 8 bit addr MOVX DPTR A Move A to External RAM 16 bit addr PUSHdirect Push direct byte onto stack POPdirect Pop direct byte from stack
172. oes not set the device into the respective power saving mode The idle mode can be terminated by activation of any enabled interrupt or a hardware reset The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after RETI instruction will be the one following the instruction that set the bit IDLS The port state and the contents of SFRs are held during idle mode Entering Idle mode disables VADC Acquisition Slicer Display CADC and DAC However note that CADC Wake up unit is still operational Leaving idle mode brings them to thier orginal power save configuration See Power save mode Semiconductor Group 103 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Power Saving modes 8 3 Power down mode Entering the power down mode is done by two consecutive instructions immediately following each other The first instruction has to set bit PDE PCON 1 and must not set bit PDS PCON 6 The following instruction has to set bit PDS PCON 6 and must not set bit PDE PCON 1 Bits PDE and PDS will automatically be cleared after having been set This double instruction sequence is implemented to minimize the chance of unintentionally entering the power down mode The following instruction sequence may serve as an example ORLPCON 00000010 Set bit PDE bit PDS must be set ORLPCON 01000000 Set bit PDS bit PDE must be set The in
173. ompensate various disturbance mechanisms These are Noise measurement and compensation Attenuation measurement and compensation Group delay measurement and compensation Note Thus TVTpro is optimized for precise data clock recovery and error free reception of data widely unaffected from noise and the currently valid channel characteristics The CVBS input contains an on chip clamping circuit The integrated A D converter is a 7 bit video converter running at the internal frequency of 33 33 MHz The sliced data is synchronized to the clock frequency given by the clock run in and to the framing code of the data stream framing code checked and written to a programmable VBI buffer After line 23 is received an interrupt can be given to the microcontroller The microcontroller starts to process the data of this buffer That means the data is error checked by software and stored in the memory To improve the signal quality the slicer control logic generates horizontal and vertical windows in which the reception of the framing code is allowed The framing code can be programmed for each line individually so that in each line a different service can be received For VPS and WSS the framing code is hardwired All follow up acquisition tasks are performed by the internal controller so in principal the data of every data service can be acquired 5 2 Slicer Architecture The slicer is composed of three main blocks The slicer The
174. ond 3 machine cycles PLL rst 1 the back to 0 wait for 150 micro seconds 38 machine cycles and then switch back to the PLL clock 101 User s Manual July 99 Infineon SDA SONR technologies Preliminary amp Confidential Power Saving modes Default after reset 00h PCON SFR Address 874 MSB LSB SMOD PDS IDLS SD GF1 IDLE SMOD USRT baud rate 0 Normal baudrate 1 Double baud rate PDS Power Down Start Bit 0 Power Down Mode not started 1 Power Down Mode started The instruction that sets this bit is the last instruction before entering power down mode Additionally this bit is protected by a delay cycle Power down mode is entered if and only if bit PDE was set by the previous instruction Once set this bit is cleared by hardware and always reads out a 0 IDLS Idle Start Bit 0 Idle Mode not started 1 ldle Mode started The instruction that sets this bit is the last instruction before entering idle mode Additionally this bit is protected by a delay cycle Idle mode is entered if and only if bit IDLE was set by the previous instruction Once set this bit is cleared by hardware and always reads out a 0 SD Slow Down Bit 0 Slow down mode is disabled 1 Slow down mode is enabled This bit is set to indicate the external clock generating circuitry to slow down the frequency This bit is not protected by a delay cycle GFx General purpose flag bits Semiconductor Group For
175. opped as soon as this bit changed to 0 If the bit is changed back to 1 the acquisition starts again with the next V pulse only 1 The start address Bit Semiconductor Group 43 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Slicer and Acquisition 3 0 of register STRVBI of the VBI buffer should only be changed if the acquisition is switched off Semiconductor Group 44 User s Manual July 99 T Infineon technologies SDA 55 Preliminary amp Confidential Slicer and Acquisition STRVBI BP9SACQFPO Field Parameters ACQFP1 Field Parameters ACQFP2 Field Parameters send to slicer after V pulse ACQFP3 Field Parameters 4 Field Parameters ACQFP5 Field Parameters ACQFP6 Field Status Information write to memory JACQFP7 Field Status Information after V pulse ACQFP8 Field Status Information VBI start line 6 gt ACQLPO Line Parameters 1 Line Parameters send to slicer after H pulse ACQLP2 Line Parameters ACQLP3 Line Parameters ACQLP4 Line tatus Data pre 0 Data Byte 1 Data Byte 2 send to memory lt Data Byte 41 ACQLPO Line Parameters Sandita libet ACQLP1 Line Parameters after H pulse ACQLP2 Line Parameters ACQLP3 Line Parameters We ms Data Byte 0 send to memory 2 Data Byte 41
176. or Next to the character display area in which the characters are displayed there is a area which is surrounding the character display area The visibility of this border area depends on the width and height ofthe character display area The user is free to define the color vector of this border BRDCO BRDCO BRDCO BRDCO BRDCO BRDCO Description L5 14 L2 L1 10 0 0 0 0 0 0 Defines a color vector for 0 0 0 0 0 1 the border see also 18 4 7 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 see also 18 4 Global Display Word GDW Semiconductor Group 189 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display 18 4 4 Full Screen Double Height If double height is enabled for the full screen each line of the OSD is repeated twice at the RGB output As a result characters which are normally displayed in normal height are now displayed in double height and characters which are normally displayed in double height are now displayed in quadruple height Row 0 and 24 are handled in a special way If double height is selected for the full screen these two rows can be fixed to normal display each line of these rows is repeated only once In double height mode user may want to start the processing of the display at row 12 and not at row 0 To decide this three bits are used as a global attribute GDDH2 GDDH1 GDDHO display are
177. or Group 9 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Overview Chapter 13 Capture reload timer Describes peripheral CRT Chapter 14 Pulse Width Modulation Unit Describes peripheral PWM Chapter 15 Watchdog Timer Describes peripheral Watchdog timer Chapter 16 Analog to Digital converter Describes ADC functionality Chapter 17 Sync System Screen resolution sync mechanism Chapter 18 Display Display features modes and their usage Chapter 19 Digital to Anaog converter Describes DAC operation Chapter 20 Electrical Characteristics Lists all important AC and DC Values and the maximum operating conditions of SDA55xx Chapter 21 22 amp 23 Glossary Index and List of changes since last edition Provides a list of used terms and abbreviations their explanation and where to find them in that document and changes since last edition 1 3 Related Documentation For easier understanding of this specification it is recommended to read the documentation listed in the following table Document Name Document Purpose Semiconductor Group 10 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Overview 1 4 Introduction The SDA 55xx is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System VPS Program Delivery Control PDC and Wide Screen Si
178. ot available 6 6 ble 2 ble 2 6 RG B 00 15 15 not available 7 7 3 3 7 RGB 15 15 15 not available 8 0 0 0 g 8 R G B 00 00 00 not available 9 1 not 1 not 1 9 R G B 07 00 00 availa availa not available 10 2 ble 2 ble 2 10 R G B 00 07 00 not available 11 1 3 3 3 11 R GB 07 07 004 not available 12 4 0 0 12 R G B 00 00 074 not available 13 5 not 1 not 1 13 R G B 07d 00 07 availa availa not available 14 6 ble 2 ble 2 14 R GB 00 07 074 not available 15 7 3 3 15 R GB 07 07 074 CLUTPOINTh 00h 16 0 0 0 0 software programmable CLUTPOINTh 02h 17 1 1 1 1 software programmable CLUTPOINTh 04h 18 2 2 2 2 software programmable CLUTPOINTh 06h 19 2 3 3 3 3 software programmable CLUTPOINTh 08h 20 4 0 0 4 software programmable CLUTPOINTh 0Ah 21 5 i 1 i 1 5 software programmable CLUTPOINTh 0Ch 22 6 2 2 6 software programmable CLUTPOINTh 0Eh 23 7 3 3 software programmable CLUTPOINTh 10h 24 0 0 0 T 8 software programmable CLUTPOINTh 12h 25 1 1 9 software programmable CLUTPOINTh 14h 26 2 2 2 2 2 10 software programmable CLUTPOINTh 16h 27 3 3 3 3 11 software programmable CLUTPOINTh 18h 28 4 0 0 12 software programmable CLUTPOINTh 1Ah 29 5 1 3 1 13 software programmable CLUTPOINTh ICh 30 6 2 2 14 software programmable CLUTPOINTh 1Eh 31 3 3 15 software programmable CLUTPOINTh 420h 32 0 0 0 0 software programmable CLUTPOINTh 22h 33 1 4 1 4 1 1 software programmable CLUTPOINTh 24h 34 4 2 2 2 2 software programm
179. oweverclearing OV bit does not clear the CISRO PWtmr bit Therefore software must clear this bit before enabling the corresponding interrupt 14 8 Control registers All control register for PWM are mapped in the SFR address space Their address and bit discription is given below Note that controller can write any time into these registers However registers PWM COMPS8 X CPMP14 X CPMPEXT14 X including the bits PWM direct and PWM PR are double buffered and values from shadow registers are only loaded into the main register in case timer overflows or timer is stopped PWME 00h of8 bit counter Overflow for 8 bit PWM occurs at the overflow of 6 bit counter and overflow for 14 bit counter occurs at the overflow When any of the PWM channels is not used associated compare register can be used as general purpose registers except En and 14 0 bit 0 and 1 Semiconductor Group 137 User s Manual July 99 Infineon SDA 55xx tecnnologies Default after reset 00 PWM En SFR Address CE MSB LSB PE7 4 PE1 PEO E7 E0 0 The corresponding PWM channel is disabled P1 i functions as normal bidirectional l O port E7 E0 1 The corresponding PWM channel is enabled PEO PE5 channels with 8 bit resolution while PE6 and PE7 are channels with 14 bit resolution Default after reset 004 PWM_COMP8_X 0 to 5 SFR Addr
180. port s bit byte as a source operand reads a value that is the logical AND of the last value written to the bit byte and the polarity being applied to the pin pins by an external device this assumes that none of the processor s electrical specifications are being violated An instruction that reads a bit byte operates on the content and writes the result back to the bit byte reads the last value written to the bit byte instead of the logic level at the pin pins Pins comprising a single port can be made a mixed collection of inputs and outputs by writing a one to each pin that is to be an input Each time an instruction uses a port as the destination the operation must write ones to those bits that correspond to the input pins An input to a port pin needs not to be synchronized to the oscillator All the port latches have one s written to them by the reset function If a zero is subsequently written to a port latch it can be reconfigured as an input by writing a to it The instructions that perform a read of operation on and write to a port s bit byte are INC DEC CPL JBC SETB CLR MOV P X CJNE DJNZ ANL ORL and XRL The source read by these operations is the last value that was written to the port without regard to the levels being applied at the pins This insures that bits written to a one for use as inputs are not inadvertently cleared Port 0 has an open drain output Writing a one to the bit
181. pulse normal polarity is assumed The beginning of clamp phase can be calculated by the following formula p 480 ns BHCR If EHCR is smaller than BHCR the clamp phase will appear during Hsync EHCR 7 0 End of Horizontal Clamp Phase Master and slave mode This register defines the end of the horizontal clamp phase from the positive edge of the horizontal sync impulse at normal polarity The end of clamp phase can be calculated by the following formula ty omp 480 ns EHCR If EHCR is smaller than BHCR the clamp phase will appear during Hsync Semiconductor Group 167 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Sync System The clamp phase area has higher priority than the screen background area or the character display area and can be shifted independent from any other register Clamp Phase Area mum Screen Background Area Pixel Layer Area V VN V V Video H period frame n H pulse Figure 17 Priority of Clamp Phase Screen Background and Pixel Layer Area Semiconductor Group 168 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Reset 00 BVCR1 SFR Address EA MSB LSB 2 5 BVCR 9 BVCR 8 Reset 00 BVCR0 SFR Address MSB LSB BVCR 7 BVCR 6 BVCR 5 BVCR 4 BVCR 3 BVCR 2
182. put signals the controller is able to supervise the status of up to four analog signals and take actions if necessary This analog signals can be connected to the port4 inputs without a special configuration If the port pins of port 4 are used as digital input make sure that the input high level never exceeds VDDA The input range of the ADC is fixed to the analog supply voltage range 2 5V nominal The conversion is done continuously on all four channels the results are stored in the SFRs CADCO CADC3 and updated automatically every 46us A interrupt be used to inform the processor about new available results 16 1 Power Down and Wake Up During idle mode it is required to reduce the power consummation dramatically In order to do this for the controller ADC a special wake up unit has been included During this mode only the signal on input channel 0 is observed As soon as the input signal has fallen below a predefined level an interrupt is triggered and the system wakes up Two different levels are available The first one corresponds to fullscale 4 LSB the second one to fullscale 16 LSB The actual level can be selected by a control bit ADWULE Nevertheless it is possible to send even this wake up unit into power down for detailed description refer to power down chapter 16 2 Register Description Default after reset 00 CADCO SFR Address D1 MSB LSB CADCO 7 CADCO 6 CADCO 5 CADCO 4 CADCO 3
183. r 43 3 ORL data addr data 44 2 ORL A data 45 2 ORL A data addr 46 1 ORL A ORO 47 1 ORL A R1 48 1 ORL A RO 49 1 ORL A R1 4A 1 ORL A R2 4B 1 ORL A R3 4C 1 ORL A R4 4D 1 ORL A R5 4E 1 ORL A R6 4F 1 ORL A R7 50 2 JNC code addr 51 2 ACALL code addr 52 2 ANL data addr 53 3 ANL data addr data 54 2 ANL A data 55 2 ANL A data addr 56 1 ANL A RO 57 1 ANL A R1 58 1 ANL A RO Semiconductor Group 76 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller Figure 14 Instruction Opcodes in Hexadecimal Order cont d Hex Code Number of Bytes Mnemonic Operands 59 1 ANL A R1 5A 1 ANL A R2 5B 1 ANL A R3 5C 1 ANL A R4 5D 1 ANL A R5 5E 1 ANL A R6 5F 1 ANL A R7 60 2 JZ code addr 61 2 AJMP code addr 62 2 XRL data addr 63 3 XRL data addr data 64 2 XRL A data 65 2 XRL A data addr 66 1 XRL A RO 67 1 XRL A R1 68 1 XRL A RO 69 1 XRL A R1 6A 1 XRL A R2 6B 1 XRL A R3 6C 1 XRL A R4 6D 1 XRL A R5 6E 1 XRL A R6 6F 1 XRL A R7 70 2 JNZ code addr 71 2 ACALL code addr 72 2 ORL C bit addr 73 1 JMP A DPTR 74 2 MOV A data 75 3 MOV data addr data 76 2 MOV RO data Semiconductor Group 77 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confident
184. r AHS DHS L24 1 Line 24 start interrupt occured source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred ADC 1 Analog to digital conversion complete source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred WTmr 1 Watchdog in timer mode overflow source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred On reset this bit is intialized to 0 however if timer mode is selected and timer is running every over flow of timer will set this bit Therefore software must clear this bit before enabling the corresponding interrupt AVS 1 Acquisition vertical sync interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred DVS 1 Display Vertical sync interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred PWtmr 1 PWM in timer mode overflow interrupt source bit set by hardware Source bit must be reset by software after servicing the interupt O Interrupt has not occurred On reset this bit is intialized to 0 however if timer mode is selected and timer is running every over flow of timer will set this bit Therefore software must clear this bit before enabling the corresponding interrupt AHS 1 A
185. r Group 180 User s Manual July 99 e Infineon technologies Preliminary amp Confidential SDA 55xx 18 4 Global OSD Attributes Next to the parallel attributes stored inside character display word there are global attributes The settings of the global attributes affect the full screen The settings of the global OSD attributes are stored in the global display word GDW see also 18 4 within 10 Bytes in the XRAM The location of the GDW is defined by a programmable pointer see also 18 6 Display Byte Bit Name function cross Pos reference 0 DISALHO see also 1 DISALH1 ro Count of display columns in horizontal 2 DISALH2 direction 0 3 DISALH3 4 DISALH4 5 PROGRESS Used to enable progressive scan see also mode 18 4 10 6 Reserved 7 Reserved 0 CURSEN Enables cursor function see also 1 CURHORO Horizontal pixel shift of cursor to 18 4 2 2 CURHOR1 character position 1 3 CURHOR2 4 CURHOR3 5 CURVERO Vertical pixel shift of cursor to 6 CURVER1 character position 7 CURVER2 Semiconductor Group 181 User s Manual July 99 DA 55xx Infineon pres technologies Preliminary amp Confidential Display Byte Bit Name function cross Pos reference 0 CURVERS3 Vertical pixel shift of cursor to see also character position 18 4 2 1 POSHORO Horizontal character position of cursor 2 2
186. ratings may not be exceeded under any circumstances not even momentarily and individually as permanent damage to the IC will result Ambient temperature 0 70 Parameter Symbol Limit Values Unit Test Condition min max Supply voltage 3 3V VDD33 4 0 V Supply voltage 2 5V VDD25 3 0 V Analog supply voltage VDDA 3 0 V Storage temperature T 20 125 eC Electrostatic discharge 2000 V 100 pF 1 5 HBM 20 2 Operating Range Parameter Symbol Limit Values Unit Test Condition min max Ambient temperature 0 70 Supply voltage 3 3V VDD33 3 0 3 6 V Supply voltage 2 5V VDD25 2 25 2 75 V Analog supply voltage VDDA 2 25 2 75 V Total Power Dou 1 5 W Consumption Note In the operating range the functions given in the circuit description are fulfilled 20 3 DC Characteristics Semiconductor Group 215 User s Manual July 99 Infineon technologies SDA 55xx Preliminary amp Confidential Electrical Characteristics Parameter Symbo Limit Values Unit Test Condition Supply Currents Digital supply current for Ls mA all ports as inputs 3 3V domain MHz Digital supply current for Ls mA MHz 2 5V domain Analog Power Supply Luo mA Current Idle mode supply current Ius mA with A D wake up RTC and Ex
187. re shifted to a non visible row are also not displayed on the screen The cursor can be shifted in horizontal and vertical direction pixel by pixel all over the character display area CURSEN Description 0 Cursor mode disabled 1 Cursor mode enabled see also 18 4 Global Display Word GDW The display position of the cursor is determined by a display column value a display row value and on pixel level by a pixel shift in horizontal and vertical direction Cursor can not be shifted more than one character height and one character width on pixel level Cursor is clipped at border In full screen double height mode see also 18 4 4 cursor is also displayed in double height The pixel shift value is always related to a south east shift The pixel shift is determined by the following parameters CURHOR3 CURHOR2 CURHOR1 CURHORO Description 0 0 0 0 Horizontal shift of 0 0 0 0 1 Horizontal shift of 1 0 0 1 0 Horizontal shift of 2 0 0 1 1 Horizontal shift of 3 Semiconductor Group 186 User s Manual July 99 oe SDA 55xx nfineon technologies Preliminary amp Confidential Display CURHOR3 CURHOR2 CURHOR1 CURHORO Description 1 0 1 1 Horizontal shift of 11 1 X X not allowed see also 18 4 Global Display Word GDW CURVER3 2 CURVER1 CURVERO Description 0 0 0 0 Vertical shift of 0 0 0 0 1 Vertical shift of 1 0
188. rixes Start address of global display word cursor matrix User has to take care for a pointer definition so that memory areas do not overlapp each other on the one hand and that the definition is optimized in a way so that no memory is wasted on the other hand The length of the global display word is fixed to 10 byte and the length of the CLUT is fixed to 2 x 48 byte The length of all the other areas depend on the OSD recquirements see also 18 6 1 to 18 6 4 Each of the six pointers to the memory areas is stored in an array of pointers Each pointer in this array has got a width of 16 bits and uses 2 bytes inside the RAM Pointer Array Startaddress name function in array Oh LByte DISPOINTh Pointer to display memory POINTFIELD 1h HByte 0 2h LByte CLUTPOINT Pointer to CLUT 3h HByte 4h LByte GDWCURPOINTh Pointer to GDW and cursor matrix 5h HByte Semiconductor Group 209 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Display Pointer Array S name function LByte DRC1POINTh Pointer 1 bit DRCS matrices HByte Oh th 2h LByte 3h HByte Ah 5h POINTFIELD 1 DRC2POINTh Pointer 2 bit DRCS matrices LByte DRC4POINTh Pointer 4 bit DRCS matrices HByte 18 6 1 Character Display Area The character display area consists of 3 bytes for each character position of the character display are
189. rt with open drain output and optional C Bus emulation suport PortO e Two 8 bit multifunction l O ports Port1 Port3 One 4 bit port working as digital or analog inputs for the ADC Port2 One 2 bit I O port with secondary functions P4 2 4 3 4 7 One 4 bit l O port with secondary function P4 0 4 1 4 4 Not available in P SDIP 52 Semiconductor Group 14 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential 1 6 Logic Symbol XTAL1 gt XTAL2 STOP ENE OCF CVBS gt lt PSEN4 R G4 4 B COR BLA 4 4 HSYNC SSC VSYNC gt RD WR RST Semiconductor Group Vcc 2 5 3 3 V TVTEXT PRO SS Overview Address 20 bit Data 8 bit Port 0 8 bit Port 1 8 bit Port 2 4 bit Port 3 8 bit Port 4 6 bit User s Manual July 99 e x gt I gt lt TT gt pul ndis a o 0 13 ee _ Kejdsiq 18 H00 ino 1 Aejdsiq MEM ms e gt wow 49joE1eu 3 apay lt e P EE n aloo lt sng 3qgxyor E 5 9080 013u09 eJn3de5 Wax odv 54 2 142 WOW WeiBolg S 6 Md DAT i uols uoisueya o m o
190. s Preliminary amp Confidential Slicer and Acquisition is used to synchronize the line counter which is used to generate the vertical control signals The synchronization block includes a watchdog which keeps control of the actual lock condition of the H PLL The watchdog can produce an interrupt CC IR if synchronization has been lost It could therefore be an indication for a channel change or missing input signal 5 4 Acquisition Interface The acquisition interface manages the data transfer between both slicers and memory First of all a bit synchronization is performed FC check Following this the data is paralleled and as 8bit words shifted into memory In the other direction parameters are loaded from memory to the slicer This parameter down loading takes place after the vertical sync and after horizontal sync The parameters are used for slicer configuration The data acquisition supports several features The FC check is able to handle four different framing codes for one field Two of this framing codes are programmable and could therefore be changed from field to field The acquisition can be switched from normal mode line 6 to 23 to full channel mode line 6 to end of field 5 4 1 FC Check There are four FC s which are compared to the incoming signal The first one is 8 bit wide and is loaded down with the field parameters The second one is 16 bit wide and fixed to the FC of VPS The third one is 16 bit wide as wel
191. sary 21 Glossary Semiconductor Group 225 User s Manual July 99 Infineon TVTEXT PRO technologies Confidential Index 22 Index Semiconductor Group 226 User s Manual July 99 e DA Infineon SDA 55 technologies Preliminary amp Confidential 23 List of changes since last edition List of changes since last edition Pinning in the chapter Package and Pinning has been updated Semiconductor Group 227 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential List of changes since last edition Semiconductor Group 228 User s Manual July 99
192. service program Since the lower priority level active flip flop Semiconductor Group 94 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Interrupts has remained set higher priority interrupts are re enabled while further lower priority interrupts remain disabled 7 14 External Interrupts The external interrupt request inputs NINTO and NINT1 can be programmed for either transition activated or level activated operation Control of the external interrupts is provided in the TCON register Default after reset 00 TCON SFR Address 884 MSB LSB TF1 TR1 TFO TRO IE1 IT1 IEO ITO IE1 Interrupt 1 edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT1 Interrupt 1 type control bit Set cleared by software to specify falling edge low level triggered external interrupts IT1 1 selects transition activated external interrupts IEO Interrupt 0 edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed ITO Interrupt 0 type control bit Set cleared by software to specify falling edge low level triggered external interrupts ITO 1 selects transition activated external interrupts TCON 7 4 See chapter General Purpose Timers Counters 7 15 Extension of Standard 8051 Interrupt Logic For more flexibility the SDA545x family provides a new feature in detection EXO
193. software Set to 1 for odd fields and to 0 for even fields Semiconductor Group 162 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Sync System Bit Function VSU2 3 0 Vertical Set Up Time 2 Slave mode only To realize the odd even detection of a field next to VSU a second vertical setup time VSU2 is defined by the VSU2 register bits This horizontal delay is used to recognize the Vsync to another time than it is recognized at VSU The field detection is realized by detecting if in between these two latching points the VSync is rising or stable ly 3 84 us VSU2 If VSYNC became active for both VSU and VSU2 an odd field is detected If VSYNC became active only for VSU an even field is detected H A MEER S Su E V A DM E 13 f VSU2 VSU VSU2 VSU Generated field signal bei utilization of VSU and VSU2 field A with inverted VSU and VSU2 H A ly V A MEE tw f VSU VSU2 VSU VSU2 VSU VSU2 Generated field signal bei utilization of VSU and VSU2 field Semiconductor Group 163 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Sync System Bit Function VLR 9 0 Amount of Vertical Lines a Frame Master mode only TVTpro generates in sync master mode vertical sync impulses If for
194. struction that sets bit PDS is the last instruction executed before going into power down mode Concurrent setting of the enable and the start bits does not set the device into the respective power saving mode If idle mode and power down mode are invoked simultaneously the power down mode takes precedence The only exit from power down mode is a hardware reset The reset will redefine all SFRs but will not change the contents of internal RAM 8 4 Power save mode Bits in the PSave register individually enable and disable different major blocks in the IC Note that Power save mode is independent of Idle and power down mode In case of idle mode blocks which are in power save mode remains in power save mode Entering the power down mode with Power save mode is possible However leaving the power down mode reset would intialize all the power save register bits Note that Power save mode has a higher priority then idle mode 8 5 Slow down mode SD bit in PCON register when sets divides the system frequency by 4 During the normal operation TVT Pro is running with 33 33Mhz and in SD mode TVT Pro runs with 8 33MHZ In slow down mode the slicer Acquisiton and display are disabled regardless of Power save mode or other modes All the pending request to the bus by these blocks are masked off Leaving slow down mode restores the original status of these blocks Semiconductor Group 104 User s Manual July 99 Infineon SDA 55xx techno
195. t least one full machine cycle 12 1 Timer Counter 0 Mode Selection Timer counter 0 can be configured in one of four operating modes which are selected by bit pairs M1 MO in TMOD register figure Mode 0 Putting timer counter 0 into mode 0 makes it look like an 8048 timer which is an 8 bit counter with a divide by 32 prescaler Figure shows the mode 0 operation as it applies to timer 0 In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all 0 s it sets the timer interrupt flag TFO The counted input is enabled to the timer when TRO 1 and either GATE 0 or INTO 1 Setting GATE 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON figure GATE is contained in register TMOD figure The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 1 Mode 1 is the same as mode 0 except that the timer counter 0 register is being run with all 16 bits Semiconductor Group 121 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential General Purpose Timers Counters Mode2 Mode 2 configures the timer counter 0 register as an 8 bit counter TLO with automatic rel
196. tecnnologies Preliminary amp Confidential Reset 9 7 Analog blocks After the power up reset DAC will output a fix value ADC and ADC wake up unit does not generate any interrupts till the 12 cycle reset sequence is completed 9 8 Processor After the reset sequence program counter intializes to 0000h and starts execution from this location in the ROM Location 0000h to 0002h is reserved for intialization routine 9 9 Ports With the reset all the ports are set in to the input mode Except Port 4 0 4 1 and 4 4 which by default are reset tooutput address lines A17 A18 A19 9 10 Initialization phase 9 10 1 Acquisition After the reset Acquisition will not generate any memory accesses to the RAM as bit is initialized to 0 Processor should then initialize the VBI buffer and set the start bit software Acquisiton will also not generate any accesses to the RAM if the synchonisation is not achieved 9 10 2 Display After the reset DAC will output a fix value as defined by DGOut which is reset to 0 COR BLA is reset to a level indicating COR 0 and BLank 1 Processor should initialize the display memoryand set the En DGOUut OCD Ctrl bit Semiconductor Group 106 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Memory Organization 10 Memory Organization The processor has separate Program and Data memory space Memory spaces can be further cl
197. ter is calculating the slicing level The slicing level is the mean value of the CRI As the teletext is coded using the NRZ format the slicing level can not be calculated outside the CRI and is therefore frozen after CRI Using this slicing level the data is separated from the digital CVBS signal The result is a stream of zeros and ones In order to find the logical zeros and ones which have been transmitted the data clock needs to be recovered Therefore a digital data PLL D PLL is synchronized to the data clock during CRI using the transitions in the sliced data stream This D PLL is also frozen after CRI Timing informations for freezing the slicing level stopping the D PLL and other actions are generated by the timing circuit It generates all control signals which are synchronized to the data start 5 3 H V Synchronization Slicer and acquisition interface need a lot of signals which have to be synchronized to the incoming CVBS e g line number field or line start Therefore a sync slicing level is calculated and the sync signal is sliced from the filtered digital CVBS signal Using digital integration vertical and horizontal sync pulses are separated The horizontal pulses are fed into a digital H PLL which has flywheel functionality The H PLL includes a counter which is used to generate all the necessary horizontal control signals The vertical sync Semiconductor Group 41 User s Manual July 99 Infineon SDA 55xx tecnnologie
198. ternal Interrupts Power Down mode supply 7 uA current Slow Down mode supply 1 mA current Voltages valid for any pin unless otherwise stated Input low voltage Va 0 4 0 8 V Input high voltage 2 0 3 6 V Output low voltage V 04 V lut 3 2 mA Output high voltage Vy 2 4 V 1 6 mA Leakage current 0 2 uA 0 lt Vin lt VDD Crystal Oscillator XIN XOUT Amplifier Transconductance 4 2 mS Oscillation Frequency Cu 6 0 6 0 2 50 50 ppm Duty Cycle 45 55 High time 50 5 Pin capacitance XTAL1 G 3 5 pF CVBS Input CVBS ADC_DIFF 0 differential CVBS Input Semiconductor Group 216 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Electrical Characteristics Parameter Symbo Limit Values Unit Test Condition Pin capacitance pF Input impedance 2 1 Ext coupling capacitance 10 100 nF Source impedance 500 Q Overall CVBS amplitude Vas 0 5 2 V CVBS sync amplitude 0 1 0 6 V TXT data amplitude Vx 0 15 0 7 V De coupling Capacitors to C ct nF at Pins CVBSi CVBS Input CVBS ADC DIFF 1 non differential CVBS Input Pin capacitance C pF Input impedance 7 1 Ext coupling capacitance 10 100
199. terrupt detection on falling edge at Pin P3 2 Development Note In order to implement the edge triggering functionality ITO and IT1 are mirrore outside the core Note if both EXxR and EXxF set both rising and falling edges would generate interrupt Minimmum delay between the interrupts should be ensured by the software If both the EXxR and EXxF are reset to 0 Interrupt is disabled Note External extra interupts EX1 and 2 edge triggered interrupts only Note When intO or int1 is used together with capture reload timer it is possible to generate interupt through CRT For further details refer to the chapter CRT Semiconductor Group 96 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Interrupts Please refer to the chapter Additional registers register bits IntsrcO and Intsrc1 for further description of external interrupt O and 1 source selection 7 16 Interrupt Task Function The processor records the active priority level s by setting internal flip flop s Each interrupt level has its own flip flop The flip flop corresponding to the interrupt level being serviced is reset when the processor executes a RETI instruction The sequence of events for an interrupt is Asource provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred Theinterrupt request is conditioned by bits in the int
200. that In addition PWM direct bit makes it possible to run PWMcounter at system frequency ignoring PR bit and the built in divide by 2 prescaler To reduce electromagnetic radiation the different PWM channels are not switched on simultaneously with the same counter value but delayed each with one clock cycle to the next channel Channel 0 0 clock cycles delayed Channel 1 1 clock cycle delayed Channel 5 5 clock cycles PWM14 0 6 clock cycles PWM14 1 7 clock cycles delayed 14 3 Port pins Port 1 is a dual function port Under normal mode it works as standard port 1 under alternate function mode it outputs the PWM channels P1 0 P1 5 corresponds to the six 8 bit resolution PWM channels PWM8_0 PWM8_5 P1 6 and P1 7 coressponds to the two 14 bit resolution PWM channels PWM14 0 and PWM14 1 PWM channels can be indivdually enabled by corresponding bits in the PWME register provided PWM bit is not set timer mode start bit Semiconductor Group 133 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Pulse Width Modulation Unit 14 4 Functional description 14 4 1 8 bit PWM The base frequency of a 8 bit resolution channel is derived from the overflow of a six bit counter On every counter overflow the enabled PWM lines would be set to 1 Execpt in the case when compare value is set to zero In case the comparator bits 7 2 are to 1 the high time
201. the following instruction Semiconductor Group 68 User s Manual July 99 e Infineon technologies SDA 55xx Preliminary amp Confidential Microcontroller 6 3 3 Instruction Set Description Figure 9 Arithmetic Operations Mnemonic Description Byte ADDA Rn Add register to Accumulator ADDA direct Add direct byte to Accumulator ADDA Ri Add indirect RAM to Accumulator ADDA data Add immediate data to Accumulator ADDCA Rn Add register to Accumulator with Carry flag ADDCA direct Add direct byte to A with Carry flag ADDCA Ri Add indirect RAM to A with Carry flag ADDCA data Add immediate data to A with Carry flag SUBBA Rn Subtract register from A with Borrow SUBBA direct Subtract direct byte from A with Borrow SUBBA Ri Subtract indirect RAM from A with Borrow SUBBA data Subtract immediate data from A with Borrow INCA Increment Accumulator INCRn Increment register INCdirect Increment direct byte INC Ri Increment indirect RAM DECA Decrement Accumulator DECRn Decrement register DECdirect Decrement direct byte DEC Ri Decrement indirect RAM INCDPTR Increment Data Pointer MULAB Multiply A amp DIVAB Divide A amp B DAA Decimal Adjust Accumulator p po pl pl pl Hf pm Ht aH nmi Semiconductor Group 69 User s Manual July 99 Infineon technologies SDA 55xx
202. tialized to 0 0 0 2 Instructions on which memory extension would act LJMP MOVC MOVX LCALL ACALL RET RETI 10 3 3 Program memory Banking LJMP After reset the bits for current bank CB and next bank NB are set to zero This insures that processor starts the same as standard 8051 controller at address 00000 When a jump to another bank is required software changes the bits NB16 19 to the appropriate bank address before LJMP instruction When LJMP is encountered in the code MMU copies the NB16 19 next bank bits to CB16 19 current bank Note that the NB bits are not destroyed Extended address bits would appear at A16 A19 This address line has same timing requirement as normal address lines AO A15 and both must be stable at the same time Only with LUMP above mentioned action is performed other jmp instructions have no effect CB bits are read only Semiconductor Group 112 User s Manual July 99 Infineon SDA 55 technologies Preliminary amp Confidential Memory Organization 0 0 3 MOVC handling There are two modes for MOVC instructions The mode is selected by MM bit in MEX2 MOVC with Current Bank When MM bit 0 MOVC will access the current bank The CB16 CB19 bits would appear as address A16 A19 during MOVC instructions MOVC with Memory Bank When MM bit 1 MOVC will access the Memory bank The MB16 MB19 bits would appear as address A16 A19 during MOVC ins
203. tries The RGB values of the CLUT entries from 0 15 are hardwired and can not be changed by software The transparency for the hardwired CLUT values are set by a global attribute inside the global display word GDW see also 18 4 This global setting can be overruled inside of boxes see also 18 4 6 HDWCLUTCOR HDWCLUTBLANK _ Description 0 0 Decides the polarity for COR and BLANK output for the hardwired CLUT entries 0 15 and the polarity of COR and BLANK during black clamp phase see also 17 1 COR 0 BLANK 0 0 1 Decides the polarity for COR and BLANK output for the hardwired CLUT entries 0 15 and the polarity of COR and BLANK during black clamp phase see also 17 1 0 BLANK 1 1 0 Decides the polarity for COR and BLANK output for the hardwired CLUT entries 0 15 and the polarity of COR and BLANK during black clamp phase see also 17 1 COR 1 BLANK 0 1 1 Decides the polarity for COR and BLANK output for the hardwired CLUT entries 0 15 and the polarity of COR and BLANK during black clamp phase see also 17 1 COR 1 BLANK 1 The RGB values of the CLUT entries from 16 to 63 are free programmable The RGB values of the CLUT are organized in the TVTpro XRAM in a incremental serial order CLUT locations inside XRAM which are not used for OSD can be used for any other storage purposes The CLUT is divided 8 subCLUTs with 8 entries for 1 bit DRCS and ROM characters For 2
204. tructions Note MEX1 is not destroyed MOVX handling There are two modes for MOVX instructions The mode is selected by MXM bit in MEX3 MOVX with Current Bank When MXM bit 0 MOVX will access the current bank The CB16 CB19 bits would appear as address A16 A19 during MOVX instructions MOVX with Data Memory Bank When bit 1 MOVX will access the Data memory bank The MX16 MX19 bits would appear as address 16 19 during MOVX instructions Note MEX1 is not destroyed 10 34 CALLs and Interrupts Memory extension Stack For Interrupts and Calls Memory extension Stack is required Stack pointer MEXSP provides the stack depth of up to 128bytes Stack width is 1 byte In TVT Pro 128 Bytes stack is implemented 10 3 5 Stack Full No indication for stack full is provided User is responsible to read MEXSP SFR to determine the status of the MEXSP stack 10 3 6 Timing MMU outputs address bits A19 A16 at the same time as normal addresses A15 A0 Semiconductor Group 113 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Memory Organization Stack operation signals SAdd 6 0 SDatal 7 0 SDataO 7 0 SRd and SWr have the same timing as internal RAM signals 10 3 7 Interfacing Extended memory Signals A19 A18 A17 A16 are used to decode extended memory 10 3 8 Interfacing Extended stack Device provides 128 Byte extended Stack SAdd 6 0 SDatal 7 0
205. user 102 User s Manual July 99 Infineon SDA 55xx technologies Preliminary amp Confidential Power Saving modes PDE Power Down Mode Enable Bit When set a delay cycle is started The following instruction can then set the device into power down mode Once set this bit is cleared by hardware and always reads out a 0 IDLE Idle Mode Enable Bit When set a delay cycle is started The following instruction can then set the device into idle mode Once set this bit is cleared by hardware and always reads out a 0 Default after reset 00h PCON SFR Address 87 MSB LSB PDS IDLS SD _ PDE IDLE 8 2 Idle mode Entering the idle mode is done by two consecutive instructions immediately following each other The first instruction has to set bit IDLE PCON 0 and must not set bit IDLS PCON 5 The following instruction has to set bit IDLS PCON 5 and must not set bit IDLE 0 Bits IDLE and IDLS will automatically be cleared after having been set This double instruction sequence is implemented to minimize the chance of unintentionally entering the idle mode The following instruction sequence may serve as an example ORLPCON 4000000015 Set bit IDLE bit IDLS must not be set ORLPCON 001000005 Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode Concurrent setting of the enable and the start bits d
206. ut mode External extra Int 0 Port output mode TXD P3 2 0 Portpin Portinput mode External interrupt 0 P3 3 0 Portpin Portinput mode External interrupt 1 P3 4 0 Portpin Port input mode Timer counter 0 input 3 5 0 Portpin Port input mode Timer counter 0 input P3 6 0 Port pin P3 7 0 Portpin Port input mode External extra Int 1 Portinput mode RXD 40 10 17 CSCRI AI7 P4 0 Portpin HO 18 CSCRI AI8 P4 1 Portpin P4 2 0 Portpin CSCRI ENARW Read signal P4 3 O Portpin CSCR1 ENARW Write signal 4 4 0 19 1 19 P4 4 Portpin 4 7 0 PortWS CSCRO VS OE VS output CSCRO VS OE OddEven output P4 7 ALT P4 7 ALT 1 Not available in SDIP52 Semiconductor Group 22 User s Manual July 99 SDA 55 e Infineon technologies Preliminary amp Confidential 2 4 Pin Configuration P SDIP 52 ROM Version top view Package and Pinning P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 VDD 2 5 VSS VDD 3 3 CVBS VDDA 2 5 VSSA P2 0 P2 1 P2 2 P2 3 HS SSG VS 0 P3 1 P3 2 P3 3 P3 4 P3 5 TVTEXT PRO SDA 55XX P SDIP 52
207. when SD 1 Semiconductor Group 125 User s Manual July 99 Infineon SDA 55xx tecnnologies Preliminary amp Confidential Capture reload timer 13 3 3 Run When counter is started RUN 16 bit reload value is automatically loaded in the 16 bit counter Note REL bit is irrelevant in case of RUN function Setting run bit resets the FIRST and OV bit All the control bits PR PLG REL RUN RISE FALL SEL Start Int Src SD can be changed anytime during the operation these changes take immediate effect there is no protected mode when counter is running 13 3 4 Overflow In case no capture event occurs counter keeps on counting till it overflows from FFFF to 0000 at this transition OV bit is set After the overflow counter keeps on counting Overflow does not reload the reload value Note that OV bit is set by counter and can be reset by software 13 3 5 Modes There are three different modes in which counter can be used Normal Capture mode Polling mode Capture mode with spike suppression at the start of a telegram Mode START PLG Normal capture mode 0 0 Capture mode with spike suprression 1 0 Polling mode X 1 For each mode selection it is recomended to reset the RUN bit if it is not already at 0 set the appropriate mode bit and then start the counter by setting the RUN bit For each of the capture mode the event is captured based on the CRTCONO RIiISE and CRTCONO FALL
208. yo P4 3 WR write line This signal is same as the output of the pin WR which is only available in some package P4 7 VS Vertical sync ODD Even Odd even field indicator Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 A low level on this pin resets the device An internal pull up resistor permits power on reset using only one external capacitor connected to Vss Type Additional reference Available PS SDIP52 MQFP64 MQFP100 PLCC84 Vops 3 Input output 3 3V Supply voltage 2 5V V Ground 0 V Type Additional reference Available PS SDIP52 MQFP64 MQFP100 PLCC84 Supply voltage for analog components Ground for analog components Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 CVBS input for the acquisition circuit Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 In slave mode Horizontal sync input or sandcastle input for display synchronization In master mode HS or VCS output Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 Input of the inverting oscillator amplifier Semiconductor Group 18 User s Manual July 99 SDA 55xx Infineon technologies Preliminary amp Confidential Package and Pinning Symbol Function XTAL2 Type Additional reference Available SDIP52 MQFP64 MQFP100 PLCC84 Output of the inverting oscillator amplifier

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