D:\Research\Projects\Organic - OPDK Project\OPDK Tutorial\OPDK
Contents
1. 46 Chapter 5 Applying Cross Overs for Interconnections 49 Introducing Cross Over 50 Layout of Cross Over 51 Chapter 6 Using P Cells 53 Purpose of P Cell 54 Supported Devices 55 Using P Cell for Ion Gel Top Gated P3HT Channel 56 OPDK User Manual Release 2014 3 Table of Contents Using P Cell for Ion Gel Top Gated CNT Channel 58 Using P Cell for Capacitor 60 Chapter 7 Simulating Circuits 62 Introducing Device Models 63 Simulating with HSPICE 64 Chapter 8 Brief Guidelines to Modify OPDK 71 Basic Background Knowledge Regarding Design Kit 72 Modifying OPDK When You Do Not Need New Layers Devices 72. Status Ready T 27 C Simulator spectre Design Variables Analyses Type Arguments Enable Low Outputs Name signalExpr Value Plot Save Save Options XE T __ 45 Piloting mode Replace gt 14 Environment Fig 7 2 1 Virtuoso ADE interface 2 2 Set up Simulator Click Setup gt Simulator Directory Host OPDK User Manual Release 2014 3 65 Chapter 7 Simulating Circuits Vinuoso Analog Design Environment 2 TEST inverter schematic Analyses VYanables Outputs Simulation Hesvits Tools Help cadence Design 58581071 Simul Design Va Libraries Name Temperature Igi L Stimuli Simulation Files we LA L gt ai 73 Environment 25 4 gt z EN Plotting moce Repace D e 14 SimalatorDirectorysHost Fig 7 2 2 Set up simulator Select hspiceD in Simulator Click OK to return 2 3 Generate Circuit Netlist File Click Simulation gt Netlist gt Create Virtuoso Analog Design Environment 2 TEST inverter schematic Session Setup Analyses Variables Outputs Results Tools Help cadence Netlist and Run Run Read l ca imulator hspice Design Variables Stop 1 Analog Options umen Netlist Create oe Display M Convergence Aids m Re
3. 00 orsi e 3 Draw the gate electrode On the left side of the drawn Fig 2 3 2 Layers window choose 1 Draw the source drain electrodes Assume we are going to and draw another one under the first rectangle with 50um 2 Draw the source drain connections to other nets On the right electrodes draw a rectangle of 100um x 200um in METALI OPDK User Manual Release 2014 3 21 Chapter 2Getting Started with 100um distance away from the source drain electrodes The final pattern should look like this Fig 2 3 3 Metal pattern of a PSHT OTFT B P3HT Channel Select PSHT TFT drw from LSW window and draw a rectangle of 500um x 120um covering the entire two source drain electrodes and filling the entire 50um gap to form a channel C Ion Gel Dielectric Select IONGEL_TFT drw from LSW window and draw a rectangle of 700um x 120um completely enclosing the P3HT channel with 25um extension on the length direction and 50um extension on the width side onto METALI D PEDOT Conductive Layer Select PEDOT_TFT drw from LSW window and draw a rectangle of 675um x 25um placed roughly in the middle of the channel Locate the rectangle so that it extends onto OPDK User Manual Release 2014 3 22 Chapter 2Getting Started METALI over Iongel layer on the gate side by 50um Iongel layer should also enclose this PEDOT layer by 25um on the right side E Contact For LVS purpose dummy contacts are requ
4. Design cell name inverter Design view name schematic TEMP 25 Simulation Temperature OPTION Simulation Options ARTIST 2 INGOLD 2 PARHIER LOCAL PSF 2 POST 2 inc OPDK organic_basekit models model_P3HT Jncluded Model File Library name TEST Circuit Description Cell name inverter View name schematic m0 out in vdd sub PTFT P3HT TG L 50e 6 W 500e 6 r0 out gnd 10e3 VDD vdd 0 1 2 Power Supply VGND gnd 0 0 OPDK User Manual Release 2014 3 68 Chapter 7 Simulating Circuits VSUB sub 0 1 2 VIN in 0 Input dc VIN 0 1 2 0 01 Analysis Type DC Sweep END 2 6 Run Simulation At the directory where you save your test sp run hspice hspice test sp You should be able to see job concluded near the bottom of the simulation log printed on screen In case of job aborted check your test sp file 2 7 Examine Waveform Now you can observe your waveforms generated by the simulation For example you can launch cscope and open the test sw0 file Select v out and the waveform should look like this OPDK User Manual Release 2014 3 69 Chapter 7 Simulating Circuits A Grapho V VOLTS y out 05 0 75 Te BE UE Fig 7 2 5 HSPICE simulation waveform OPDK User Manual Release 2014 3 Chapter 8 Brief Guidelines to Modify Chapter 8 Brief Guidelines to Modify OPDK This chapter introduces brief guidelines to modify the Organic Proce
5. Ab sideways upside Down Width in uM 100 Length in uM 50 Cancel Fig 6 4 2 Specify channel length and width for CNT OTFT Note usually the default parameters are the minimum values If an invalid value is specified it will restore its previous value To make sure click on another input textbox and check if the input value is restored 4 3 Place the instance Place the new instance at appropriate position in your layout view OPDK User Manual Release 2014 3 60 Chapter 6 Using P Cells 5 Using P Cell for Capacitor 5 1 Create an Instance with P Cell Create a new instance in your layout Create gt Instance Select layout view in OPDK_Pcells CAP_P3HT_TG layout Library Browser Create Instance Show Categories Library Cell View OPDK_PCells CAP_P3HT_TG layout OPDK_Devices OPDK_Examples PTFT_P3HT_TG OPDK_PCells TFT CNT TG TechLib TEST Us 8ths analogLib basic k tdsDefTechLib Close j Filters J Display Help Fig 6 5 1 Utilizing capacitor P Cell to create device layout 5 2 Specify key parameters Assume we are creating a CAP_P3HT_TG device with area of W L 200um 500um In the bottom of the Create Instance window specify Length_in_uM as 500 and Width_in_uM as 200 OPDK User Manual Release 2014 3 61 Chapter 6 Using P Cells Create Instance Library OPDK PCells Browse Cell P3HT TG V
6. Fig 6 3 2 Specify channel length and width for PSHT OTFT Note usually the default parameters are the minimum values If an invalid value is specified it will restore its previous value To make sure click on another input textbox and check if the input value is restored 3 3 Place the instance Place the new instance at appropriate position in your layout view OPDK User Manual Release 2014 3 58 Chapter 6 Using P Cells 4 Using P Cell for Ion Gel Top Gated CNT Channel OTFT 4 1 Create an Instance with P Cell Create a new instance in your layout Create gt Instance Select layout view in OPDK_Pcells TFT_CNT_TG layout j Library Browser Create Instance Show Categories Library Cell View OPDK_PCells TFT_CNT_TG layout OPDK_Devices CAP PSHT TG 1 OPDK Examples PTFT P3HT TG x OPDK TechLib TEST US 8ths analogLib basic cdsDefTechLib Close Filters Display Help 9 Fig 6 4 1 Utilizing CNT OTFT P Cell to create device layout 4 2 Specify key parameters Assume we are creating a TFT_CNT_TG device with W L 100um 50um In the bottom of the Create Instance window specify Length_in_uM as 50 and Width_in_uM as 100 OPDK User Manual Release 2014 3 59 Chapter 6 Using P Cells gt Create Instance x Library Pells Browse j Cell TFT CNT T6 View layout Names Ti Mosaic Rows 1 Columns 1 Delta Y 425 Delta X 500 Halo x Define Halo Sh Rotate
7. Introducing OPDK 3 Introducing Organic Thin Film Transistor 4 The Organic Process Design Kit Definition and Purpose 7 The Organic Process Design Kit Features 8 Chapter 2 Getting Started 9 System Requirements 10 Setup OPDK 11 Example Design of an Inverter with Top Gated P3HT Channel TFT 13 Example Layout of an Inverter with Top Gated P3HT Channel TFT 20 Chapter 3 Designing Layout of OTFT 33 Supported OTFT Devices 34 Layout of the Ion Gel Top Gated P3HT Channel 35 Layout of the Ion Gel Top Gated CNT Channel 38 Chapter 4 Designing Layout of Passive Devices 42 Supported Passive Devices 43 Layout of Resistor 44 Layout of Capacitor
8. OEDK provides three types of resistor layers PEDOT_R2K PEDOT RIOK and PEDOT_RIOOK The resistor value is calculated by L W R Unit where R_Unit value is the suffix of each type of layer Assume we are going to draw a 10 resistor with PEDOT R2K L W ratio should be 5 according to the calculation So here we can go with L W 500um 100um Select METAL from LSW window and draw two rectangles of 300um x 100um being 500um away from each other in Y direction B Resistor Select PEDOT R2K drw from LSW window and draw a rectangle of 100um x 700um extending onto METALI layers by 100um each C Substrate Select SUB drw from LSW window and draw a rectangle to enclose everything OPDK User Manual Release 2014 3 45 Chapter 4Designing Layout of Passive Devices The final layout should look like this lt gt Resistor Width Resiston Length Fig 4 2 1 Final layout of a resistor OPDK User Manual Release 2014 3 46 Chapter 4Designing Layout of Passive Devices 3 Layout of Capacitor Note The capacitor supported in this design kit is formed in the way of a PTFT with P3HT channel Therefore it has positive drain and source and negative gate ends METAL1 In the LSW window choose METAL drw From the Layout window choose Create gt Shape gt Rectangle 1 Draw the positive end Assume we are going to draw a TFTCAP of 2uF Since the unit capacitance is 10pF sq um we can use W L 500um 400um Draw a
9. Before starting with the design example there are a couple things worth mentioning e Most of the commands in Cadence can be accessed in multiple ways pull down menus shortcut keys buttons in toolbars etc In the described example all the commands are referenced by their position in the pull down menus The shortcut keys can be found from the pull down menus as well e most frequently used key in Cadence is ESC It is used to cancel on going commands The following picture shows the schematic of an inverter which is ready for netlist extraction The following section explains how to draw it in Cadence OPDK User Manual Release 2014 3 13 Chapter 2Getting Started ch Options Migle Wincow Hey cadence Fig 2 2 1 Schematic of an inverter 2 1 Create a library for your new design From the library manager window File gt New gt Library Type a new name such as TEST click OK In the pop up window choose Attach to an existing tech library Then choose OPDK TechLib Click OK 2 2 Create a new cell In the Library Manager highlight your new library TEST if that is what you chose File gt New gt Cellview Choose library TEST cell name inverter view name schematic and Open with Schematic L Click OK Click Always if Upgrade License warning message shows up A schematic window will open OPDK User Manual Release 2014 3 14 Chapter 2Getting Started 2 3 Design your circ
10. File Manager Mentor Calibre techfile calibre calibreDRC rul DRC rule file techfile calibre calibreLVS rul LVS rule file techfile calibre layer inc DRC LVS layer mapping file Spice models Spice transistor models OPDK User Manual Release 2014 3 74 Chapter 8 Brief Guidelines to Modify Modifying OPDK When You Do Not Need New Layers Devices In many cases you are only looking for a quick way to do a p type only or CNT only design You usually do not need to create new layers or devices even if it is not using P3HT material as long as you are okay with the name inconsistency This will save your a lot of effort in modifying the OPDK The only thing you need to do is to use the existing CNT symbols to do your design ignoring the names as if they are the devices you have access to Update the DRC LVS rules where necessary and create your own Spice models In this way you can have the same layout verification with DRC LVS and also same functionality verification with your own Spice models The only issue is the transistors will be displayed as P3HT or CNT devices Hint even if you are doing a complementary logic design i e with both p type and n type available you can still use the and CNT devices as a workaround You can assume the P3HT as p type and CNT as n type and update your device models to match what you actually have The CNT device is modeled a
11. following system requirement 1 Cadence Virtuoso version 6 1 1 or higher 2 Mentor Calibre 2006 4 OA 2 2 5 or higher Running OPDK with a lower version of Cadence or Mentor is not tested and may require changes in configuration If you are not sure about your system environment please contact your IT support OPDK User Manual Release 2014 3 10 Chapter 2Getting Started 1 Setup OPDK 1 1 Make a new directory called OPDK under your home directory mkdir OPDK 1 2 Go to OPDK cd OPDK 1 3 Copy the file OPDK 1 5 tar to directory OPDK by using the command from this directory cp OPDK 1 5 tar gz 1 4 Extract the archive using the command tar zxvf OPDK 1 5 tar gz 1 5 You should now be able to see the extracted files under OPDK at your home directory This contains an open source open access based OPDK for organic electronic applications based on ion gel technology from the Department of Chemical Engineering and Materials Science CEMS at the University of Minnesota Twin Cities 1 6 Go to organic_basekit cdssetup under OPDK directory cd organic_basekit cdssetup Here you will have to modify setup csh using vi nano or any of your favorite editors as follows 1 6 1 Comment out the line which defines the environment variable OPDK_DIR it starts with setenv Lines can be commented out by adding a at the beginning OPDK User Manual Release 2014 3 11 Chapter 2Getting Started 1 6 2 Set the OPDK_DIR variab
12. this inverter you will need five pins ground GND negative power VDDN input IN output OUT and substrate SUB From Schematic window Create gt Pin Add Pin window will open Type in the pin names and place the pins in the appropriate locations Pay attention to the red box shown below and make sure you choose the right I O direction for each pin For example IN should be Input OUT should be Output and all the rest should be InputOutput Pin Names GND VDDN IN OUT SUB Direction inputOutput B Bus Expansion off w on Usage schematic D Placement amp single multiple Attach Net Expression amp No wv Yes Property Name Default Net Name Fant Heicht Font style S Rotate Sideways Upside Down Show Sensitivity gt gt GUES Cancel Defaults Help Fig 2 2 3 Specify pin names and types OPDK User Manual Release 2014 3 16 Chapter 2Getting Started 2 3 3 Connect components Connect the component terminals as shown in the figure above using Create gt Wire narrow 2 4 Generate netlist files In the Schematic Window Design gt Check and Save There should be no errors Then go Launch gt ADE L The window of Cadence Analog Design Environment will show up Make sure the current simulator is set to hspiceD Setup gt Simulator Directory Host Set the simulator to hspiceD Simulation Netlist Create se Virtuoso Analog Design Environment 1 TEST inverter schematic Session Setu
13. those files with the new name OPDK User Manual Release 2014 3 80 Chapter 8 Brief Guidelines to Modify 2 New Device If you need a new device it is not that straightforward and has a lot of details that can easily be missed However here are the useful guidelines which can help you out in most Cases To create a new device e g NMOS go to the common analoglib library and copy a similar device over For example pmos4 for p transistors res for resistors Start CIW CDF Edit browse and select the new cell you just copied Make sure CDF Type is set to base otherwise the change won t be saved Go through all the parameters and make necessary changes The key parameters include gt model in Component Parameters gt componentName amp modelName in auCdl and componentName in auLvs in Simulation Parameters important for LVS gt componentName in hspiceD in Simulation Parameters note all transistors must use nmos even if it is a pmos device important for netlist extraction Save the CDF changes If necessary modify the symbol OPDK User Manual Release 2014 3 81 Chapter 8 Brief Guidelines to Modify 3 Extra Modifications After you have the new layer and or device in place you need to also update the models too OPDK User Manual Release 2014 3 82
14. 2 3 9 Calibre LVS check results If there are errors the message will contain statistics about what kind of errors are found To see why and where you get an error double click on the error messages and the corresponding layers or boundaries will be highlighted in the layout Note Sometimes you may have multiple labels with the same name e g GND on a few separated GND rails If they are eventually going to be connected while you want to leave them separated at the moment you should go to Setup gt LVS Options and enable LVS Options menu and check Connect gt Connect all nets by name This will automatically recognize all nets with the same name to be connected even if they are not physically connected in your layout So you need to be careful when using this option Or OPDK User Manual Release 2014 3 32 Chapter 2Getting Started you can check Connect gt Connect nets named and specify the net names to be connected during LVS OPDK User Manual Release 2014 3 33 Chapter 3Designing Layout of Chapter 3 Designing Layout of OTFT This chapter provides details about designing layouts for the supported OTFT devices Supported OTFT Devices Layout of Ion Gel Top Gated P3HT Channel OTFT Layout of Ion Gel Top Gated CNT Channel OTFT OPDK User Manual Release 2014 3 34 Chapter 3Designing Layout of 1 Supported OTFT Devices The supported OTFT devices in this OPDK are based on ion gel technique wit
15. 5 Modifying When You Need New Layers Devices 79 OPDK User Manual Release 2014 3 Chapter 1Introducing Chapter 1 Introducing OPDK This chapter introduces basic background of the Organic Process Design Kit OPDK Introducing Organic Thin Film Transistor OTFT The Organic Process Design Kit Definition and Purpose The Organic Process Design Kit Features OPDK User Manual Release 2014 3 3 Chapter 1Introducing Introducing Organic Thin Film Transistor OTFT The integration of electronics onto the flexible substrate including plastic and metal foils will greatly expand the application area of microelectronics However difficulties have been encountered with the traditional silicon transistors mainly due to their rigid lattice structure and the high temperature during fabrication Organic thin film transistors 1 which are composed of polymers have been demonstrated to be a potential solution Furthermore the feasibility of printing organic transistors also indicates the perspective of low cost fabrication Organic transistors however usually suffer from low carrier mobility resulting in a high operation voltage Few attempts have been made on printable low voltage organic transistors Here we demonstrate a printable gel OTFT technique which provides sufficient current under a low operation voltage 1V A gel OTFT is an organic thin f
16. Engineering and Material Science Department at the University of Minnesota Corresponding OTFT device symbols OPDK_Devices PTFT_P3HT_TG symbol OPDK_Devices CHT_TFT_TG symbol Corresponding capacitor symbols OPDK_Devices cap symbol OPDK User Manual Release 2014 3 56 Chapter 6 Using P Cells 3 Using P Cell for Ion Gel Top Gated P3HT Channel 3 1 Create an Instance with P Cell Create a new instance in your layout Create gt Instance Select layout view in OPDK Pcells PTFT P3HT TG layout Library Browser Create Instance Show Categories Library Cell View OPDK_PCells PTFT_P3HT_TG layout OPDK_Devices CAP P3HT TG OPDK Examples TechLib TEST US 8ths analogLib basic cdsDefTechLib R TFT_CNT_TG Close Filters Display Help Fig 6 3 1 Utilizing PSHT OTFT P Cell to create device layout 3 2 Specify key parameters Assume we are creating a PTFT_P3HT_TG device with W L 100um 50um In the bottom of the Create Instance window specify Length_in_uM as 50 and Width_in_uM as 100 OPDK User Manual Release 2014 3 57 Chapter 6 Using P Cells v Create Instance x Library OPDK_PCells Browse Cell PTFT P3HT TG View layout Names 11 Mosaic Rows 1 Columns 1 DeltaY 450 Delta X 500 Halo Define Halo nk Rotate n Sideways 2 Upside Down Length in uM 50 Width in uM 100 Cancel Defauits _ Help
17. T drw from LSW window and draw a rectangle of 500um x 120um covering the entire two source drain electrodes and filling the entire 50um gap to form a channel C Ion Gel Dielectric Select IONGEL TFT drw from LSW window and draw a rectangle of 700um x 120um completely enclosing the P3HT channel with 25um extension on the length direction and 50um extension on the width side onto METALI D PEDOT Conductive Layer Select PEDOT TFT drw from LSW window and draw a rectangle of 675um x 25um placed roughly in the middle of the channel Locate the rectangle so that it extends onto METAL over Iongel layer on the gate side by 50um Iongel layer should also enclose this PEDOT layer by 25um on the right side OPDK User Manual Release 2014 3 37 Chapter 3Designing Layout of E Contact For LVS purpose dummy contacts are required in layout Select COTFT drw from LSW window draw rectangles at source P3HT overlapping METAL1 and drain P3HT overlapping METALI Select CONTACT drw from LSW window for rectangles at gate PEDOT overlapping METALL but not interacting with IONGEL F Substrate For LVS purpose substrate layer is required in layout Select SUB drw from LSW window and draw a rectangle to enclose everything The final layout should be like this Fig 3 2 2 Final layout of a PSHT OTFT OPDK User Manual Release 2014 3 38 Chapter 3Designing Layout of 3 Layout of the Ion Gel Top Gate
18. UNIVERSITY OF MINNESOTA OPDK User Manual Release 2014 3 Wei Zhang March 2014 User Manual Release 2014 3 March 2014 Copyright 2014 University of Minnesota All rights reserved Unpublished rights reserved under the copyright laws of the United States Use of copyright notices is precautionary and does not imply publication or disclosure Contact VLSI Group University of Minnesota Contact VLSI Group University of Minnesota by Telephone 612 626 0834 Fax 612 626 4583 VLSI Group ECE Department University of Minnesota Keller Hall EECS Building 4 168 200 Union Street SE Minneapolis MN 55455 Questions amp Comments Contact author Wei Zhang by Email zhang758 umn edu OPDK User Manual Release 2014 3 Il Using This Manual This manual describes the Organic Process Design Kit OPDK and how to use it Audience This manual is intended for designers who use OPDK to develop test analyze and modify organic circuit designs in ion gel gated OTFT technique and designers who develop device descriptions as an extension for other specific organic transistor structures Related Documents The following documents pertain to this manual Features Release Notes OPDK User Manual Release 2014 3 111 Conventions OPDK User Manual uses the following conventions unless otherwise specified Convention Description Indicates the name of the menu and the co
19. ce sizes It is a very useful tool since it helps us identify wrong connections or shorts or open circuits that may be difficult to be discovered by naked eyes To perform LVS verification click on Calibre gt Run LVS The LVS dialog window opens up Again set the LVS Rules File to OPDK_DIR organic_basekit techfile calibre calibreLVS rul and LVS Run Directory to OPDK_DIR runcalibre Go to Inputs and make sure for both Layout and Netlist Export from layout or schematic viewer is checked Click on Run LVS and the LVS will now run Hierarchical __ Flat Calibre CB Inputs Layout vs Netlist _ Netlist vs Netlist Netlist Extraction Outputs Layout Netlist H Cells Run Control Transcript Files inverter src net bd m View L rema srce Start RVE Top Cel inverter M Fig 2 3 8 Calibre LVS interface OPDK User Manual Release 2014 3 31 Chapter 2Getting Started If everything is okay it should finish with this popped out window 3 Calibre LVS RVE inverter project chriskim03 wei OPDK OPDK runcalibre svdb File View Layout Source Setup Hep ios k z B input Files 3 BI LVS Results Designs Match 9 Rules File gt BB inverter inverter 9 Source Netlist Output Files 9 Layout Netlist Extraction Report LVS Report Discrepancy Information Guery Cell Inverter Fig
20. create zu Plotting mode Replace Y i 14 Create Fig 7 2 3 Create netlist OPDK User Manual Release 2014 3 66 Chapter 7 Simulating Circuits The following window will pop out displaying the generated netlist home 03 zhang758 simulation inverter hspiceD schematic netlist in EIENEN File Help cadence Generated for hspiceD Generated cn Dec 14 22 21 00 2010 Design library name TEST Design cell name inverter Design view name schematic TEMP 25 OPTION ARTIST 2 INGOLD 2 PARHIER LOCAL PSF 2 Library name TEST Cell nane inverter View name schenatic L3 out in vdd sub P3HY T6 L 50e 6 W S00e 6 out gnd 10e3 END Fig 7 2 4 Generated netlist Click File gt Save As and save the netlist file as your HSPICE netlist e g test sp 2 4 Include Model File Open the netlist file saved in 2 3 e g test sp Add the model path before the circuit descriptions PSF 2 inc models model P3HT Library name TEST Make sure your model file path is correct OPDK User Manual Release 2014 3 67 Chapter 7 Simulating Circuits 2 5 Modify Simulation File Make necessary modifications to your simulation file including simulation options power supply inputs analysis type etc The following is an example to simulate the inverter for its transfer curve Generated for hspiceD Generated on Dec 14 22 21 00 2010 Design library name TEST
21. d CNT Channel Note CNT TFTs are neither P type nor N type The corresponding device is modeled as a PTFT_CNT_TG and a NTFT_CNT_TG connected in parallel Gate Gate Substrate Fig 3 3 1 Modeling illustration of a CNT OTFT A METALI In the LSW window choose METAL drw From the Layout window choose Create Shape Rectangle 1 Draw the source drain electrodes Assume we are going to draw a TFT with W L 500um 50um with a source drain electrode width of 10um Draw a rectangle of 500um x 10um and draw another under the first rectangle with 50um distance in between 2 Draw the source drain connections to other nets On the right side of the drawn electrodes draw two rectangles in METALI each being 100um 200um 3 Draw the gate electrode On the left side of the drawn electrodes draw a rectangle of 200um x 100um in METALI with 100um distance away from the source drain electrodes OPDK User Manual Release 2014 3 39 Chapter 3Designing Layout of The final pattern should look like this Source Channel Width Channel Length Fig 3 3 2 Metal pattern of a CNT OTFT B CNT Channel Select CNT TFT drw from LSW window and draw a rectangle of 500um x 120um covering the entire two source drain electrodes and filling the entire 50um gap to form a channel C CNT Dummy Channel Layer Since CNT TFTs are modeled as a P type and a N type TFT connected in parallel a dummy channel
22. e DRC will now run Fig 2 3 7 Calibre DRC interface OPDK User Manual Release 2014 3 29 Chapter 2Getting Started If everything is okay it should finish with this popped out window v Calibre DRC RVE inverter drc results projectchriskim03 wei OPDK OPDK runcalibr File View Highlight Tools Setup Help gt Go AHPC Z Topcell inverter No Results in 143 Checks Bl Check 1 1 Bl Check 1 2 Bl Check METAL2 1 Bl Check METAL2 2 o B Check P3HT TFT 1 o B Check P3HT TFT 2 Bl Check CNT TFT 1 o Bl Check TFT 2 o Bl Check TFT DUM 1 Bl Check CNT TFT DUM 2 Bl Check NT1 TFT 1 Bl Check NT1 TFT 2 Bl Check NT2 TFT 1 hori TET Cell inverter 0 Results Fig 2 3 7 Calibre DRC check results If there are errors the message will contain statistics about which rules were violated To see why and where you violate the DRC rule double click on the error messages and the corresponding layers or boundaries will be highlighted in the layout To understand the details of the DRC rules please visit the website of OPDK 3 5 Perform LVS Verification The LVS tool is used to compare the layout with the schematic identifying any circuit related differences that might exist between these two views It reports circuit nodes and OPDK User Manual Release 2014 3 30 Chapter 2Getting Started devi
23. e environment Supports layout design in Cadence environment Supports major built in tools in Cadence environment Supports circuit file generation through Cadence Virtuoso Analog Design Environment Supports design rule checks DRC for layouts Supports layout versus schematic LVS checks for layouts Supports all layers currently used in the OTFT platform with other layers for future extension Supports two kinds of OTFT devices ion gel top gated OTFTs with P3HT or CNT channel layer Supports resistor with three unit resistance options Supports capacitor based on ion gel top gated OTFT with P3HT channel layer Provides P Cells for the two kinds of OTFT devices and for capacitor Provides HSPICE device models to perform functionality verification Provides examples of inverter NAND DFF DRAM etc Extensible for other types of organic devices including N type devices OPDK User Manual Release 2014 3 8 Chapter 2Getting Started Chapter 2 Getting Started This chapter provides the basic steps of using OPDK For details you may refer to Chapter 3 6 System Requirement Setup OPDK Example Design of an Inverter with Top Gated P3HT Channel TFT Example Layout of an Inverter with Top Gated P3HT Channel TFT OPDK User Manual Release 2014 3 9 Chapter 2Getting Started Before You Start System Requirements To run all features Organic Process Design Kit OPDK in Cadence please first make sure you have met the
24. e transistor to generate a considerable current under a low operation voltage 1E 3 e PEDOT PSS oc 0 ef o A 1 4 1 5 Substrate L 1 6 Neutral State Transistor Off amp B 1E 7 ETEEEEEEI E PINAR Hel ccce cee c 1E 9 Vps 1 0V 1E 10 Vps 0 1V Polarized lons Transistor On 1E 11 Gate capacitance gt 100 pF cm 1 0 0 5 0 0 0 5 1 0 Gate capacitance in 65nm CMOS 1 4 pF cm Ves V Fig 1 1 a Operation of ion gel electrolyte transistor in off mode and on mode The polarized ions enable an unusually high gate capacitance inducing large channel current b Ips Ves curve shows a 0 4mA drive current at a 1 V supply voltage W 500pm L 25ym The detailed current voltage characteristic curve is shown in Figure 1 1 b Under a low voltage 1V a transistor with W L 500um 25um achieves 0 4mA drain current which is sufficient in most applications Another important aspect is the on off ratio of the transistor which is the ratio between drain currents under Vas 1V and Vos OV It can be noted that the on off ratio is as high as 1000 which is good enough for digital applications These data illustrate the feasibility of fabricating high performance and stable low voltage digital circuits with gel OTFTs The gel OTFT demonstrated above is a p type transistor with P3HT channel layer N type transistor is also possible in this technique if suitable N type channel material is ava
25. equired in layout Select SUB drw from LSW window and draw a rectangle to enclose everything The final layout should be like this Fig 4 3 2 Final layout of a capacitor OPDK User Manual Release 2014 3 49 Chapter 5 Applying Cross Overs for Interconnection Chapter 5 Applying Cross Overs for Interconnection This chapter provides details about designing layouts for cross over Introducing Cross Over Layout of Cross Over OPDK User Manual Release 2014 3 50 Chapter 5 Applying Cross Overs for Interconnection 1 Introducing Cross Over In circuit designs it is rare that a single layer of interconnection would be enough Circuits usually require interconnections to cross each other without being connected e g inputs in a 3 input NAND gate In modern silicon technology multiple metal layers are used to provide more routing flexibility which are connected through vias In the OTFT platform however it is difficult to generate vias during printing Therefore cross overs are used instead A cross over is mainly composed of an insulation layer PMMA and a conducting layer PEDOT When a metal line A is to cross over another line B without getting connected we first break A at the position it meets B We then place a patch of insulation layer PMMA over B at the crossing position and build a bridge over this patch with the conducting layer PEDOT The conducting layer will connect the endpoints of broken A and ach
26. h a top gated structure provided by Dr Frisbie s group in Chemical Engineering and Material Science Department at the University of Minnesota Two devices are supported OTFT with P3HT channel layer p type and OTFT with CNT channel layer modeled as a p type and a n type device in parallel Corresponding device symbols OPDK_Devices PTFT_P3HT_TG symbol OPDK_Devices TFT_CNT_TG symbol OPDK User Manual Release 2014 3 35 Chapter 3Designing Layout of 2 Layout of the Ion Gel Top Gated P3HT Channel OTFT A METALI In the LSW window choose METAL drw From the Layout window choose Create Shape Rectangle 1 Draw the source drain electrodes Assume we are going to draw a PTFT with W L 500um 50um with a source drain electrode width of 10um Draw a rectangle of 500um x 10um and draw another one under the first rectangle with 50um distance in between 2 Draw the source drain connections to other nets On the right side of the drawn electrodes draw two rectangles in METALL each being 100um x 200um 3 Draw the gate electrode On the left side of the drawn electrodes draw a rectangle of 200um x 100um in METAL with 100um distance away from the source drain electrodes The final pattern should look like this OPDK User Manual Release 2014 3 36 Chapter 3Designing Layout of Source Channel Width Channel Length Fig 3 2 1 Metal pattern of a PSHT OTFT B P3HT Channel Select PSHT TF
27. iangle and put a small circle at the output To do this you will want to delete the green rectangle draw the new shape and move the terminals to new positions Use Create gt Shape to draw a triangle and place a circle There are several shapes available line rectangle circle etc You will also need to change the Selection box the red rectangle which defines the limits of the symbol This can be done by stretching the Selection box Figure below shows an example of the inverter symbol OPDK User Manual Release 2014 3 18 Chapter 2Getting Started FS of mx Q RIS E 2 6k gt Fig 2 2 5 Create symbol from schematic view Don t forget to check and save 2 5 2 Use the symbol in other schematics Create a new schematic using the instructions described in Create a new cell Give a name such as test inverter You place this symbol in the new schematic in the same way that you placed any other components with Create Instance This time change the Library to your library TEST and click on inverter Your symbol should be here To move in the hierarchy select the inverter and then Edit gt Hierarchy gt Descend Edit You can choose the schematic or the symbol for editing To return to the previous schematic use Edit gt Hierarchy gt Return OPDK User Manual Release 2014 3 19 Chapter 2Getting Started 3 Example Layout of an Inverter with Top Gated P3HT Channel TFT This example will help y
28. ieve the target This cross over solution can handle any interconnection situations Sometimes you may combine single cross overs to save space or to minimize printing effort OPDK User Manual Release 2014 3 51 Chapter 5 Applying Cross Overs for Interconnection 2 Layout of Cross Over A METALI Crossover connects two METAL pieces together jumping over another METAL piece between them Assume we are going to connect two METALL pieces 300um away from each other B PMMA Insulation Layer Select PMMA drw from LSW window and draw a rectangle of 200um x 300um completely enclosing the METAL piece in the middle by 50um on four edges C PEDOT Conductive Layer Select PEDOT_CRV drw from LSW window and draw a rectangle of 100um x 400um placed over the METAL piece in the middle and extending onto the two METALI pieces to connect by 50um D CONTACT For LVS purpose dummy contacts are required in layout Select CONTACT drw from LSW window and draw rectangles on two sides where PEDOT overlaps METAL E Substrate For LVS purpose substrate is required in layout Select SUB drw from LSW window and draw a rectangle to enclose everything OPDK User Manual Release 2014 3 52 Chapter 5 Applying Cross Overs for Interconnection The final layout should look like this Fig 5 2 1 Final layout of a cross over OPDK User Manual Release 2014 3 53 Chapter 6 Using P Cells Chapter 6 Using P Cells This chapter in
29. iew layout Names 11 Mosaic Rows 1 Columns 1 Delta Y 400 Delta X 300 Halo Define Halo Sk Rotate Sideways f upside Down Length in uM 500 Width in uM 200 UB Cance Defaults Fig 6 5 2 Specify channel length and width for capacitor Note usually the default parameters are the minimum values If an invalid value is specified it will restore its previous value To make sure click on another input textbox and check if the input value is restored 5 3 Place the instance Place the new instance at appropriate position in your layout view OPDK User Manual Release 2014 3 62 Chapter 7 Simulating Circuits Chapter 7 Simulating Circuits This chapter provides the basic steps of simulating circuits with device models Introducing Device Models Simulating with HSPICE OPDK User Manual Release 2014 3 63 Chapter 7 Simulating Circuits 1 Introducing Device Models Device models include detailed characteristics of the device which are utilized in simulation In OPDK we focus on HSPICE models Due to the similarity in I V characteristics of OTFT and silicon transistors compact models are feasible by modeling OTFTs with traditional silicon transistors In OPDK OTFT with P3HT channel is modeled as a PMOS transistor and OTFT with CNT channel is modeled as a PMOS transistor and a NMOS transistor connected in parallel Resistor and capacitor are modeled as ideal resistor and capacit
30. ilable OPDK User Manual Release 2014 3 5 Chapter 1Introducing However the introduction of a viable n type material has been delayed due to unstable characteristics no good contact and significantly lower mobility than their p type counterpart Therefore n type device is not the focus of Organic Process Design Kit OPDK at the current stage In conclusion we have demonstrated our printable gel OTFT technique where the high gate capacitance caused by polarized ions is the key to generating significant current under a low operation voltage The current voltage characteristics have shown the great potential of gel OTFTS in achieving stable digital applications References 1 Y Xia W Zhang M Ha et al Printed Sub 2 V Gel Electrolyte Gated Polymer Transistors and Circuits Applied Functional Materials Volume 20 Issue 4 pages 587 594 February 22 2010 2 W Zhang M Ha D Braga M Renn C D Frisbie C H Kim A 1V Printed Organic DRAM Cell Based on Ion Gel Gated Transistors with a Sub 10nW per Cell Refresh Power International Solid State Circuits Conference ISSCC February 2011 OPDK User Manual Release 2014 3 6 Chapter 1Introducing The Organic Process Design Kit OPDK Definition and Purpose The main purpose of OPDK is to facilitate the entire OTFT circuit system design The earlier OTFT designs rely on examinations by naked eyes and lack effective verification in either fu
31. ilm transistor which is fabricated based on ion gel wherein ion gel refers to an electrolyte formed by gelation of a triblock copolymer in an ionic liquid acting as the gate dielectric Figure 1 1 shows the basic structure and mechanism of a gel OTFT and its current voltage characteristics 1 Poly 3 hexylthiophene P3HT is printed between the two gold electrodes source and drain as the channel layer An ion gel layer covers the entire channel layer and a conducting polymer poly 3 4 ethylenedioxythiophene poly styrenesulfonate PEDOT PSS is printed on the top as the gate electrode When the gate is floating the ions in the ion gel are randomly distributed and the entire gel displays a neutral state When the gate is biased with a negative voltage the ions are polarized by the electrical field and interfaces are formed near both surfaces of ion gel creating two capacitors in serial If a voltage difference is also applied between the source and the drain carriers in the channel layer will start to flow leading to a drain OPDK User Manual Release 2014 3 4 Chapter 1Introducing current Since the distance between charges at each interface is quite small at the order of nm the equivalent gate capacitance is significantly high 100 uF cm which is around 70 times larger than that in the silicon transistors 1 4 uF cm 2 Therefore in spite of the relatively low carrier mobility the large gate capacitance enables th
32. ing Started The final layout should look like this Fig 2 3 5 Final layout of an inverter w o pins 3 2 3 Add pins For LVS purpose pins are required in layout Create gt Pin A Create Pin window will open OPDK User Manual Release 2014 3 26 Chapter 2Getting Started Create Shape Pin Terminal Names GND VDDN IN OUT SUB Keep First Name X Pitch 0 Y Pitch 0 Display Pin Name As ROD Object I Display Pin Name Option Pin Name Display Height 50 Font stick Text Options x Drafing Mode VO Type Overbar Snap Mode Bic s Access Direction Layer e w Pin Layer Justification centerCenter Sk Rotate Ab Sideways Upside Down Cancel _ Help Fig 2 3 6 Add pins Type in the pin names and check Display Pin Name Click Display Pin Name Option and a Pin Name Display window opens Set the text height to 50 and set appropriate layer for the pins In this example SUB should be of SUB drawing layer while all the rest should be of METALI drawing layer Do not close the windows before you finish your drawing Go back to the layout view and select the appropriate layer METALI drawing in the LSW window for the first pin you will place GND Draw a rectangle on the metal plate of ground and place the text on or near it You can do the rest in the same way OPDK User Manual Release 2014 3 27 Cha
33. ired in layout Select COTFT drw from LSW window and draw rectangles at source P3HT overlapping METAL and drain P3HT overlapping METALI Select CONTACT drw from LSW window for rectangles at gate PEDOT overlapping METALL but not interacting with IONGEL F Substrate For LVS purpose substrate layer is required in layout Select SUB drw from LSW window and draw a rectangle to enclose everything The final layout should look like this Fig 2 3 4 Final layout of a PSHT OTFT OPDK User Manual Release 2014 3 23 Chapter 2Getting Started OPDK User Manual Release 2014 3 24 Chapter 2Getting Started 3 2 2 Layout a resistor A METALI provides three types of resistor layers PEDOT R2K PEDOT RIOK and PEDOT R100K The resistor value is calculated by L W R Unit where R_Unit value 15 the suffix of each type of layer Assume we are going to draw a 10 resistor with PEDOT R2K L W ratio should be 5 according to the calculation So here we can go with width 100um and length 500um Select METALI from LSW window and draw two rectangles of 300um x 100um being 500um away from each other in Y direction B Resistor Select PEDOT_R2K drw from LSW window and draw a rectangle of 100um x 700um extending onto METALI layers by 100um each C Substrate Select SUB drw from LSW window and draw a rectangle to enclose everything or simply stretch the previous SUB OPDK User Manual Release 2014 3 25 Chapter 2Gett
34. ke this Fig 3 3 3 Final layout of a CNT OTFT OPDK User Manual Release 2014 3 42 Chapter 4Designing Layout of Passive Devices Chapter 4 Designing Layout of Passive Devices This chapter provides details about designing layouts for the supported Passive devices Supported Passive Devices Layout of Resistor Layout of Capacitor OPDK User Manual Release 2014 3 43 Chapter 4Designing Layout of Passive Devices 1 Supported Passive Devices The supported passive devices in this OPDK include resistor and TFT based capacitor provided by Dr Frisbie s group in Chemical Engineering and Material Science Department at the University of Minnesota Three resistor types are supported Resistor with unit resistance of 2k Ohm and Resistor with unit resistance of 10k Ohm and Resistor with unit resistance of 100k Ohm Corresponding device symbols OPDK_Devices res symbol Resistor value Unit Resistance L W length units um One capacitor type is supported TFT based capacitor with unit capacitance of 100pF Corresponding device symbols OPDK PDevices cap symbol Capacitance value Unit capacitance W L length units um OPDK User Manual Release 2014 3 44 Chapter 4Designing Layout of Passive Devices 2 Layout of Resistor Note There are three types of resistor layers with different unit resistance Please choose the appropriate one according to the resistor value you are going to use A METAL1
35. layer is required to represent the N type device model the CNT channel layer in Step B represents the P type device Select CNT TFT DUM from LSW window and draw a rectangle of 500um x 120um exactly overlapping with the TFT layer in Step B OPDK User Manual Release 2014 3 40 Chapter 3Designing Layout of D Ion Gel Dielectric Select IONGEL_TFT drw from LSW window and draw a rectangle of 700um x 120um completely enclosing the CNT channel with 25um extension on the length direction and 50um extension on the width side onto METALI E PEDOT Conductive Layer Select PEDOT_TFT drw from LSW window and draw a rectangle of 675um x 25um placed roughly in the middle of the channel Locate the rectangle so that it extends onto METALI over Iongel layer on the gate side 50um Iongel layer should also enclose this PEDOT layer by 25um on the right side F Contact For LVS purpose dummy contacts are required in layout Select COTFT drw from LSW window and draw rectangles at source CNT overlapping METAL1 drain CNT overlapping METAL1 Select CONTACT drw from LSW window for rectangles at gate PEDOT overlapping METAL but not interacting with IONGEL G Substrate For LVS purpose substrate layer is required in layout Select SUB drw from LSW window and draw a rectangle to enclose everything OPDK User Manual Release 2014 3 41 Chapter 3Designing Layout of The final layout should be li
36. le to the root directory of the OPDK distribution setenv OPDK_DIR lt your_absolute_local_path gt OPDK 1 6 3 Comment out the line which defines the environment variable CDSHOME 1 6 4 Set the CDSHOME variable to the root directory the Cadence installation For example setenv CDSHOME home apps common cadence Linux ic_611 tools Inx86 1 6 5 Save and exit the file Your OPDK is setup and ready to be used now 1 7 Create your temporary Cadence work directory at OPDK cd OPDK mkdir cds cd cds Always run Cadence from this directory to avoid cluttering up your workspace 1 8 Copy setup csh the file you modified in step 1 6 into this directory cp organic_basekit cdssetup setup csh Source this script using the following command source setup csh This script copies the files needed by Cadence and initializes the environment 1 9 Invoke Cadence by typing virtuoso amp This should bring up the command interface window and library manager You are now ready to design circuits in Cadence OPDK User Manual Release 2014 3 12 Chapter 2Getting Started 2 Example Design of an Inverter with Top Gated P3HT Channel TFT This example will help you familiarize yourself with OPDK in Cadence This will show the most important commands and steps used when working with schematics in Cadence As an example you will design a simple inverter with resistor load For details of the various components please refer to the next few chapters
37. mmand name For menuName gt commandName example File gt Save as refers to the Save as command in the File menu times italic Indicates commands functions arguments file names and variables with a line of text When a variable is included in italicized text the variable is lt gt enclosed by angle brackets lt gt For example setenv OPDK DIR your absolute local path gt OPDK where your absolute local path is your absolute local path of your OPDK directory Other Sources of Information The OPDK external website provides information for OPDK updates downloads and documentation The website can be accessed at http opdk umn edu Acknowledgment The author would like to thank 1 NCSU FreePDK45 Developer Team North Carolina State University and Oklahoma State c niversity for providing software framework for OPDK development NCSU FreePDK45 Website http www eda ncsu edu wiki FreePDK 2 National Science Foundation for funding support 3 Dr C Daniel Frisbie s group in Chemical Engineering and Materials Science Department at the University of Minnesota for technical support in organic electronics information 4 Dr Chris H Kim s group in Electrical and Computer Engineering Department at the University of Minnesota for technical support in software development and website design OPDK User Manual Release 2014 3 IV Table of Contents TABLE OF CONTENTS Chapter 1
38. nctionality or layout To ensure reasonable yield for complex circuit systems it is required to improve the design tools and introduce verification steps Fortunately sharing a lot in common with silicon transistors especially in the structure OTFTs are able to adapt similar techniques widely used in silicon industry For example among the mainstream computer aided design CAD software Cadence VirtuosoO design environment is feasible to be utilized for OTFTs both for designing circuits and drawing layouts Circuit simulation software such as HSPICEO is also an excellent candidate to verify the design functionality The existing tools however cannot be directly utilized since the major characteristics and materials are totally different Therefore the design kit specifically developed for OTFTs targets at building a software package based on silicon transistors while following the real properties of OTFT With the help of Cadence Virtuoso and HSPICE it enables computer based verifications on circuit and layout designs and significantly reduces design load for large scale systems OPDK User Manual Release 2014 3 7 Chapter 1Introducing The Organic Process Design Kit OPDK Features is a design kit developed for platform under the software environment of Cadence Virtuoso It has the following major features T 2 10 11 12 13 14 Supports circuit design in Cadenc
39. or respectively The model parameters are selected to fit the real I V curves obtained from measurements Another approach is to utilize behavior modeling It is basically a look up table Once the raw I V curve is obtained users can directly use the measurement data to build the look up table or say behavior device model This way is more straightforward and requires little curve fitting effort however errors in measurement could introduce potential risks as convergence failures and the simulation cannot exceed the voltage range of the table The models included in OPDK do not involve this approach TFT capacitance can be estimated by data fitting with measurements of ring oscillator frequency To simulate timing parameters the estimated capacitance should be added to the model either by assigning the unit capacitance values in the compact model e g Cgdo or by adding an explicit capacitor to the device OPDK User Manual Release 2014 3 64 Chapter 7 Simulating Circuits 2 Simulating with HSPICE To simulate the circuit in HSPICE you need to first generate the circuit file netlist and prepare the model files needed 2 1 Launch Analog Design Environment ADE In your schematic window launch Analog Design Environment ADE Launch gt ADE L A window will pop out Virtuoso Analog Design Environment 2 TEST inverter schematic Session Setup Aralyses Variables Outputs Simulation Results Tools Help cadence
40. ou to create a layout for the inverter you designed in the first example The following picture shows a layout for the inverter The following sections explain how to make each of the separate components in Virtuoso See Fig 2 3 1 Layout of an inverter 3 1 Create a layout view of your cell In the Library Manager Highlight your inverter schematic library TEST if that is what you chose OPDK User Manual Release 2014 3 20 Chapter 2Getting Started File gt New gt Cellview Change the view type to layout and open with layout L Click OK Click Always if there is any license upgrade message A layout editing and an LSW window will open up 3 2 Layout the components for your circuit For this inverter we will need to layout a Top gated P3HT channel PTFT and a resistor 3 2 1 Layout a PTFT For better illustration it is recommended to draw different layers in the order of how it is actually fabricated OE 1217 A METALI Son Edit Help In the LSW window choose METAL drw From the Layout METALI OPDK_TechLib Layer Object Grid av Nv as NS Create gt Shape gt Rectangle draw with W L 500um 50um with a source drain MAcorrT electrode width of 10um Draw a rectangle of 500um x 10um Micorr net METAL 1 VI Jore distance in between VIAL net Mera _ side of the drawn electrodes draw two rectangles METALI each being 100um x 200um
41. p Analyses Variables Outputs amp Results Tools Help Netlist and Run Run Stop Status Ready T 27 C Simulator spectre Design Variables Analyses Name Value Device Checking Optians AL Netlist ETC TERES c 2 Trans Display Recreate 25 4 E u d Q 2 Plotting mode Replace B gt 7 Create Fig 2 2 4 Create netlist from schematic view A new window will pop up showing the generated HSPICE netlist You may save this file by clicking the menu bar File gt Save As OPDK User Manual Release 2014 3 17 Chapter 2Getting Started Specify the full path name and file name in the Save As window If you have models ready you can use this netlist file to run simulations with the model You may need to modify some of the netlist which we will not discuss in details 2 5 Working with symbols If you want to use your design in other schematics you need to create a symbol for it This is equivalent to the use of sub circuits in HSPICE Using hierarchy in your project makes it easier to organize 2 5 1 Create a new symbol Save the schematic before you create its symbol File gt Check and Save Create gt Cellview gt From Cellview click OK A new window will open with the symbol view By default the symbol shape is a rectangle but you can change it Since this design is an inverter we will draw a tr
42. pter 2Getting Started Note Do not use Create Rectangle to draw the pins The Create Pin command automatically provides rectangle drawings Note Be sure to change the layer for SUB The final layout should be look like the one shown in the beginning of this section 3 3 Route If in the future you need to route between different instances or cells simply use METAL for connection 3 4 Grid control for layout In the layout view the mouse pointer only snaps to a certain spacing of location The spacing can be set by Options gt Display In the Grid Control panel the X Snap Spacing and Y Snap Spacing control the resolution of mouse snap in layout In default X Snap Spacing and Y Snap Spacing are set to lum You should either keep the default setting or change them to multiples of lum in your layout because in this design kit DRC rule requires the edge of the drawing e g rectangle wire lies on grid which is a multiple of 1pm 3 4 Perform DRC Verification It s always a good practice to stop and do a DRC check from time to time before placing more components to your diagram To do so clicking on Calibre DRC A window that looks like the one below opens up Set the DRC Rules File to OPDK_DIR organic_basekit techfile calibre calibreDRC rul and DRC Run Directory to OPDK_DIR runcalibre OPDK User Manual Release 2014 3 28 Chapter 2Getting Started Click on Run DRC and th
43. rectangle of 500um x 500um and draw another of 550um x 100um placed on top of the first one overlapping 100um in Y direction Thus only 500um x 400um is going to be used as the capacitor plate 2 Draw the negative end Draw a rectangle of 550um x 100um placed under the 500um x 500um one with 100um distance away in Y direction OPDK User Manual Release 2014 3 47 Chapter 4Designing Layout of Passive Devices The final pattern should look like this Source amp Drain POS Channel Length Channel Width Gate NEG Fig 4 3 1 Metal pattern of a capacitor B P3HT Channel Select PSHT CAP drw from LSW window and draw a rectangle of 500um x 400um covering the entire 500um x 400um METALL plate This is the dielectric layer of the TFTCAP C Ion Gel Dielectric Select IONGEL CAP drw from LSW window and draw a rectangle of 600um x 500um completely enclosing the P3HT plate with 50um extension on four edges D PEDOT Conductive Layer Select PEDOT CAP drw from LSW window and draw a rectangle of 500um x 600um completely enclosing the P3HT plate and overlapping with the negative end with 100um OPDK User Manual Release 2014 3 48 Chapter 4Designing Layout of Passive Devices E Contact For LVS purpose dummy contacts are required in layout Select CONTACT drw from LSW window and draw a rectangle at negative end PEDOT overlapping METAL 1 F Substrate For LVS purpose substrate layer is r
44. s a sub circuit in OPDK but you can always post process the netlist after it is created We may in the future release an OPDK update to include a valid n type device so that it can better serve those using complimentary logic however since that is not urgent there OPDK User Manual Release 2014 3 75 Chapter 8 Brief Guidelines to Modify is a workaround like using CNT devices temporarily and users can also create their own n type devices see next section we do not guarantee a release date OPDK User Manual Release 2014 3 76 Chapter 8 Brief Guidelines to Modify 1 DRC LVS Rule Modification DRC rule file techfile calibre calibreDRC rul LVS rule file techfile calibre calibreL V S rul The rule files are written in Standard Verification Rule Format SVRF whose reference manual can be found in Calibre s document You can update the details according to your actual fabrication process OPDK User Manual Release 2014 3 77 Chapter 8 Brief Guidelines to Modify 2 Spice Model Modification Spice model directory models In many cases you have a different transistor characteristic compared to what is provided in OPDK OPDK uses conventional HSpice supported device models e g Level 61 TFT model to write the model files Therefore the only thing you need to work on is the various model parameters so that it fits your device I V characteristics better You can of course complete re
45. ss Design Kit OPDK so that it can best fit your needs Basic Background Knowledge Regarding Design Kit Modifying OPDK When You Do Not Need New Layers Devices Modifying OPDK When You Need New Layers Devices OPDK User Manual Release 2014 3 71 Chapter 8 Brief Guidelines to Modify Basic Background Knowledge Regarding Design Kit The Organic Process Design Kit OPDK is created based on the framework of the open source NCSU FreePDK45 Therefore it shares most basic structures with NCSU FreePDK45 A Design Kit is a set of configuration files that are recognizable by Cadence Virtuoso Environment for the visual aided design part Mentor Calibre for DRC LVS part and Spice for simulation part As a result all files are written following these commercial products guidelines OPDK User Manual Release 2014 3 72 Chapter 8 Brief Guidelines to Modify 1 Major Resources Cadence Virtuoso Cadence Virtuoso Official Manual Cadence Virtuoso Skill Language Reference Manual Mentor Calibre Standard Verification Rule Format SVRF Manual svrf_ur pdf Spice Hspice User Manual OPDK User Manual Release 2014 3 73 Chapter 8 Brief Guidelines to Modify 2 Major Related Files Cadence Virtuoso Most il files however they do not need to be modified in most scenarios tech db files they can only be modified by Virtuoso s built in functions like Technology
46. troduces how to use P Cells to facilitate layout design Purpose of P Cell Supported Devices Using P Cell for Ion Gel Top Gated P3HT Channel Using P Cell for Ion Gel Top Gated CNT Channel Using P Cell for Capacitor OPDK User Manual Release 2014 3 54 Chapter 6 Using P Cells 1 Purpose of P Cell P Cell stands for parameterized cell Cells that only vary in parameters can be grouped with the concept of P Cell and thus significantly reduce work load The single OTFT device symbols that we use in Chapter 2 can also be viewed as a P Cell since by specifying parameters various devices can be obtained P Cells can be very useful in layout design If two devices are different only in parameters it would be much more efficient to generate the second device based on the first one instead of designing from scratch So the basic concept of P Cell is first create a reference layout for a single type of device then specify parameters and the software will stretch the reference layout according to the parameter difference Thus devices with various parameters can be generated with little effort which significantly improve design efficiency OPDK User Manual Release 2014 3 55 Chapter 6 Using P Cells 2 Supported Devices The supported devices in this OPDK with P Cell setup include ion gel top gated OTFTs with P3HT or CNT channel layer and TFT based capacitor provided by Dr Frisbie s group in Chemical
47. uit 2 3 1 Place components For this inverter you will need a top gated P3HT channel TFT and a resistor From Schematic window Create gt Instance Add Instance and Library Browser windows will open If the Library Browser window does not open automatically simply click Browse on the Add Instance window Make sure the Library in the Library Browser is set to OPDK_Devices Use the Library Browser window and click on PTFT_P3HT_TG then select symbol and close the window In the Add Instance window type in the appropriate width and length values Here we use width 500um and length 50um Place the PTFT in the schematic window Virtuoso Schematic Editor L Editing TEST inverter schematic Launrh Fila Edit View Creata Chack Antins Minate Window Help cadence Add Instance a Library CPDK Devices Browse j P3HT TO zyabol Sideways d Model name TG width 500u M Length 5 u N Source diffusion area Drain diffusion area Source diffusion periphery Fig 2 2 2 Add a P3HT OTFT device symbol into schematic Similarly place a resistor of 10K Ohm with the res symbol If you make any mistake you can always use OPDK User Manual Release 2014 3 15 Chapter 2Getting Started Edit gt Delete or Edit gt Rotate or Edit gt Move or Edit gt Stretch To change the properties of some of the components Edit gt Properties gt Objects 2 3 2 Place pins For
48. write the model if you want There is no restriction on file names either The model files are no more than an included file in your Spice simulation see Chapter 7 on how to run simulations OPDK User Manual Release 2014 3 78 Chapter 8 Brief Guidelines to Modify Modifying OPDK When You Need New Layers Devices In certain cases you may want to build a more dedicated design kit with new layers or devices It could be due to a new device that is introduced or maybe you simply do not want the naming inconsistency in your design In this scenario you will need to spend some effort to edit a layer add a new layer or add a new device Here we will only cover the basics and the most critical tips on how to do it OPDK User Manual Release 2014 3 79 Chapter 8 Brief Guidelines to Modify 1 Layer Modification Layer modification is straightforward by utilizing the built in Technology Library Manager in Cadence Virtuoso CIW Tools Technology Library Manager Edit Layers Add new layers by clicking Add in Layer Purpose Pairs and set appropriate properties Make sure you have appropriate display configured for the new layers Note once you have a new layer you usually also need to update the layer mapping files e g Layers inc as well as DRC LVS rule files to include the rules for those new layers If you only have edited the layer s name then probably you only need to update
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