SMT350_User_Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. 245 76 MHz Single ended Signals 5 External Clock In ADCs DAC External Clock Out ADCs DAC LVTTL Figure 6 Clock Structure Version 1 9 Page 15 of 45 SMT350 User Manual ADCs can both receive the same clock or the fraction of the CDCM7005 input clock 2 3 4 6 8 or 16 the maximum being 125MHz for each ADC This input clock can be coming from the on board fixed VCXO or from an external source Here is a list of possible sampling frequencies for the ADCs ADC Sampling CDCM7005 Setting Clock source Frequency Not Allowed On board VCXO fixed 245 bir 122 88 MHz On board VCXO fixed 245 76MHz 81 92 MHz 13 On board VCXO fixed 245 76MHz 61 44 MHz 14 On board VCXO fixed 245 76MHz 40 96 MHz 6 On board VCXO fixed 245 76MHz 30 72 MHz l On board VCXO fixed 245 76MHz 15 36 MHz 16 On board VCXO fixed 245 76MHz Anything between 10 1 12 13 14 6 8 or and 125 MHz 116 External Clock The same applies to the DAC with a maximum sampling frequency for clk1 of 160MHz and for clk2 of 500Mhz Below is shown how the external clock is fed to the system By default it is single ended and AC coupled before being converted into LVPECL format The option of having a differential external clock is still possible on the hardware by the way of fitting or not some of the components Version 1 9 Page 16 of 45 SMT350 User Manual Pra 5 IL wilt c E m o i e E cc 2 CC DC m CONNECTO2. 0x1D 36 DDS Register 0 Start Phase Increment LSB Ov20 37 DDS Register 1 Start Phase Increment MSB 0X21 37 DDS Register 2 Stop Phase Increment LSB 0x22 38 DDS Register 3 Stop Increment MSB vin 38 DDS Register 0 Step Phase Increment LSB 0x24 ee eek Ee ee ee 38 DDS Register 5 Step Increment MSB 0X25 i 39 FPEA DESIGNED e ue nL Ee le 40 SOM ial CSE AC EEN 40 Version 1 9 Page 5 of 45 SMT350 User Manual BIOCK Ol FOOISIONS NETTE LEM 41 Space avallable MF POA ge 41 Pepoli 42 Bel eie EA Een 44 PICS gl len SE 44 LOCATION on IE BOAAN EE Ge ee eg eate sa een ER Ee Ge 45 Table of Figures Figure 1 Fan across PEL si ESE LIL eee 7 FigUre 2 BIO6K RI Le EE 10 Figure EE NR 12 Figure AD CAMPUS le AO N OE OE EO EE 12 Elgure 5 DAC OUMPUT STAJE ni AAA 14 Figure 6 Clock Structure ees ee see ee ee ee EE ee nennen nnne ee ee nnne nnne nnns nnne nnne ee ee 14 wie i ac O ebe 16 Figure 8 Clock Architecture Main Characteristics es ee ee ee EE ee ee ee ee ee ee ee Ee 17 Figure 9 Mezzanine module Connector Interface SLB data and power connectors 18 Figure 10 Mezzanine Module Interface Power Connector and Pinout 20 Figure 11 Daughter Module Interface Data Signals Connector and Pinout Bank A 21 Figure
3. Bye Biz Bte Bis ml eta Bt2 em Bto DDS Start Phase Increment 31 24 ity DDS Start Phase Increment 23 16 The Start Phase Increment value is coded on 32 bits DDS Data registers 0x20 and 0x21 Each value corresponds to a frequency generated worked out as follows Fout Start Phase Increment Fpac sampling MHz 2 When the DDS is used in sweep mode Start Phase Increment should be lower than Stop Phase Increment and Step Phase Increment should be greater than 0 When used to generate a fixed frequency Start Phase Increment should be equal to Stop Phase Increment and Step Phase Increment should be equal to 1 For Registers 0x20 and 0x21 to take effect Bit 4 of register 0x1D must be set to 1 DAC Channel A is the Sine output of the DDS and DAC Channel B is the Cosine output of the DDS Both outputs are therefore is quadrature The Maximum Phase increment value supported by the design is 0x40000000 which corresponds to a frequency of 30 2MHz when sampling at 122 88MHz with no interpolation Version 1 9 Page 38 of 45 SMT350 User Manual DDS Register 2 Stop Phase Increment LSB 0x22 DDS Register 2 0x22 Bye Bi7 Bite Bits Bia Bra era Bii Bito Im DDS Stop Phase Increment 15 8 eo DDS Stop Phase Increment 7 0 DDS Register 3 Stop Increment MSB 0x23 Ly DDS Register 3 0x23 Bye Biz Bite Bis Bia Bt3 ito Biti Bito DDS Stop Phase Incre
4. CDCM7005 Register 6 0x16 Bye ear Bte Bts Bia Bes Bitz Bii Reserved Hold Reserved Hold Function 1 Default 0000 MEA EE ae AK i O Reserved Cycle Slip Lock Cycles Lock Window Register Selection 1 0 CDCM7005 Register 7 0x17 For more details refer to CDCM7005 datasheet CDCM7005 Register 7 0x17 ODOMTOOB Register 7 017 00000 Bye Bi 7 Bte Bis Bta Bis eno Bii Bito mar Reserved Ummd wp Eg Rem DEN mmi wwe Main Module Temperature not implemented 0x18 Main Module Temperature 0x18 Bye Biz Bte ets Bt4 Bts sto siti mn IE Temperature in Celcius Degrees Main Module FPGA Temperature not implemented 0x19 Main Module FPGA Temperature 0x19 Bye Bt7 m Bits Bia Gita Bt2 Bii Bito o Temperature in Celcius Degrees Mezzanine Module Temperature not implemented 0x1A Mezzanine Module Temperature 0x1A Bye en7 ene ens Ba Bus ena eni Bro o Temperature in Celcius Degrees Version 1 9 Page 35 of 45 SMT350 User Manual Mezzanine Module Converters Temperature not implemented 0x1B NEM Mezzanine Module Converters Temperature 0x1B Bye sar Bte bts am Bea Brz bti mg INN Temperature in Celcius Degrees Miscellaneous Register Ox1C Miscellaneous Register 0x1C Bye Bn Bte ms Bia ea a bri
5. SmeYOGCENTS s enon oeta roor Out Carnero 3 DORn_ suwsRscocuro C IE meme memes um ses ASS raps Figure 11 Daughter Module Interface Data Signals Connector and Pinout Bank A Version 1 9 Page 22 of 45 SMT350 User Manual Bank A Bank B Bank C 13 57 41 43 8183 24 68 Bank B Pinno Pmtame gufen Pinno PinName SGniDesrpon o augher careto Man Mode pn ngem rat suso Temperature Sensor lock 42 Tags Temperature Sensor Daa fe Senior O Sotto swe og Cad o em Mode reses ooo Ls wea rasi ECT r 7 LEEN qu Joen rer Main Module to Daughter Card Dir Main Module to Daughter Card Ls oven renea Yn vane Resi 31 Leen noc Soares Se Adcom ment __ Man gu to Deuger Gar O Reed O oOoOoOO o tana aca NE aa R008 SG E Le sp 5 EE Main Mogu Davgher Ced TOR Main Module to paura Ls aca as Fama ra 20 s meeue cs Rest m Lang Tessepe OE Dauger Cad o lm Module or ager cardio Man Mede DEE Les Pons COCWTOOSCicckSelston 64 MONS DACPH _ EELER es Lummen acre so ETT OACPHLeck fer Jegen Testen os mecrowen EMO Main Module to Daughter Gard py Main Module to Daughter Card eo mtcnowres DIC Soa OI 70 Fave wee LL Tee re roger rese Daughter Card to Main Module DEC mensi n meme mess Jean Teen CC Iren Reseved S Daughter Card to Main Module Reserved Version 1 9 Page 23 of 45 SMT350 User Manual Figure 12 Daughter Module Interf
6. 9 Page 18 of 45 SMT350 User Manual The figure underneath illustrates this configuration The bottom view of the daughter card is shown on the right This view must the mirrored to understand how it connects to the main module Data cannartnre nuni SMIT 350 Power connectors Figure 9 Mezzanine module Connector Interface SLB data and power connectors The female differential connector is located on the base module The Samtec Part Number for this connector is QTH 060 01 F D DP A The female power connector is located on the base module The Samtec Part Number for this connector is BKS 133 03 F V A The male differential connector is located on the mezzanine card The Samtec Part Number for this connector is QSH 060 01 F D DP A The male power connector is located on the mezzanine card The Samtec Part Number for this connector is BKT 133 03 F V A The mated height between the main module and the daughter card is 5 mm Version 1 9 Page 19 of 45 SMT350 User Manual Some JTAG Lines are also mapped onto this connector to be used in case the Daughter module would have a TI Processor They would allow debugging and programming via JTAG The following table shows the pin assignment on the power connector 2 1 pepe Du iil ail E EL Epp 33 Pm number Pmneme DescntomorSigni OOS DREES DREES s ese mm Version 1 9 Page 20 of 45 SMT350 User Manual Fig
7. Bio Reserved ADC Trigger ADC Trigger ADC Trigger ADCs Clock Reference PX FEM NK A NE EN BL E Trigger m Trigger NEM Trigger EM EN NN e CH CS EMEN 0x1C C ets 6019 mes O o o memaDAC roger trom register ato DI Mei OOOO OOOO O Tener DR age trom comedor 28 see o Miscellaneous Register feig mum op SSS o Peery DAC Trapesignalselectes Nowtnvering OOOO a REESEN Miscellaneous Register feig sei mn Besoin o o memes niggersetoo OOS TT il rera __ IMiscellaneows Register XI zum enoe Dem SSS e oo AG Chane Aand B 1 sample of each ADO chanel packed onto one 3238 wor OMB CA EE o ADC Channel A only 2 samples packed onto one 32 bit word word t 1 word t EE o ADC Channel B only 2 samples packed onto one 32 bit word word t 1 word t BI 11 A06 Crame and B sample o ch ADC channel packed onto one 32 bit word ICNS ChAT o Miscellaneous Register XI stig Gs oes o o mere AOC Teer tom restr 0x bt 3 sees OOOO E Eea oC Treger from comes 28 lets O O O 7 7 O EN Miscellaneous Register 0x1C sus Ba seems OO o o rely AOC Trager see sled Nonivenn M O o RT eat ao ger signal sled wete EN Miscellaneous Register 0x1C Version 1 9 Page 36 of 45 SMT350 User Manual semg eno nm O O o o memecon OOOO O A reeeo OOOO O SS ewe BE lesse OOOO O oo lem OOOO EUN so EF INN TN zo D osmon OOOO o o CE EREECHEN NN ve zum emo
8. ET eouspunS Spaz 3 i i m a JOBGGIOJ INN NN p q ABO AU Figure 22 Daughter Module Solder Side Version 1 9 Page 44 of 45 SMT350 User Manual Connectors Description The following table gathers all connectors on the board and describes their function Connector name Description Location on the board silkscreen schematics Version 1 9 Page 45 of 45 SMT350 User Manual Location on the board sf JE IT stagno AIDA id N TEE ss RAN IE sl T zt J24 Figure 23 Connectors Location
9. FPGA Regis DOS Regier o2 005 Register 2 Sep Phase Increment LSB Reetbeck FPGA Roge DDS Regiter2 0x23 DDS Register 3 Stop Phase Increment MSB Read back FPGA Register DDS Register 3 Version 1 9 Page 27 of 45 SMT350 User Manual 0x24 DDS Register 4 Step Phase Increment LSB Read back FPGA Register DDS Register 4 MOS DDS Register 5 Step Phase Increment MSB Read back FPGA Register DDS Register 5 Figure 16 Register Memory Map Register Descriptions Reset Register 0x0 Reset G Um E 0x0 BR7 7 EN E nu RUM E ad Km Reset ees T Reset Reset Tg zo mmo mge DC CN Frese ADG deves as elas e coresondra Sora mereces O ewe Bei Dmm OOO y yO Ug o CC rento DAG desa watas a Sarli ewe ms ower E RER PE 1 EE tn CLK aove a watas ts Sra cas sewing Bus Descepton o o Narra opeaton OAC PHSTRIS sees 0 UR n EST UR m omemwesmemm OOOO O O EC BEER zm ens esempio OOOOO o o 00 nt na SH paran ol T ens DOS core she samp arde DAS Note 1 What is mentioned as DAC PHSTR line is the physical net on the board that connects together the FPGA to the PHSTR pin DAC5686 as well as to J5 In a multiple board system one board can be used as a master and its PHSTR pin can be driven high or low and an other one as slave in which case its DAC PHSTR pin must be tri stated Note 2 The Reset bits don t get cleared automatically so a device can remain
10. FPGA Register ADCA Register 0 0x0 ADCARegister1 Read back FPGA Register ADCA Register 1 0x04 ADCARegister2 sid Read back FPGA Register ADCA Register 2 0x0 ADCBRegister0 sd Read back FPGA Register ADCB Register 0 Gros aoesRegseri Rec FPA Regia ADOS Reger oes pcne L ps ooa ono egsera Rec FPGA Register DAC Register Read back FPGA Register DAC Register 3 Read back FPGA Register DAC Register 4 0x0 DACRegister5 Read back FPGA Register DAC Register 5 L meg pac registro Reabbeck FPOARegs DACRegser mor nc Reger Reesibak FPGA Register DAC Regetert orto coowmesRegser EE oe cocurosRegswri Reese FPGA Register CDCM7005 Regeer orta cocuroosegster2 Rees beet FPGA Register CDCM7005 Register gem CDCM7005 Register 3 sd Read back FPGA Register CDCM7005 Register 3 0xid CDCM7005 Register 4 sd Read back FPGA Register CDCM7005 Register 4 geg CDCM7005 Register 5 Read back FPGA Register CDCM7005 Register 5 geg CDCM7005 Register 6 0 Read back FPGA Register CDCM7005 Register 6 Read back FPGA Register CDCM7005 Register 7 Pte Reeve mac empero OOOO ode reserves ManMieFPOTempegum OOOO UGG Reen MezeweMleTomemus OOOO ode resenei MezanneMedueCoweterTempemum L BB upiseaniRestbackconmmendRagser Oo FimwaeVesonan Ssusbis oo posnegser SaPhesemeemenlS8 Ross ack FPGA Register DDS Regero oe 005 Register 1 San Phase eremeni MSB Reaaack
11. lese OOOO O Se ded O OO O O O O OOOO OR Eemere OOOO Updates Read back and Firmware Version Registers 0x1D The Update bit activates the corresponding Serial Interface to pass registers previously written in the FPGA into the corresponding device ADCA ADCB DAC or CLK devices The Read back bit activates the corresponding Serial Interface to read back register values from the corresponding device and to pass them to the FPGA This operation must be followed by Read back register operations Note that only the DAC allows proper read back operation Other devices read back commands would only perform a read back of the FPGA register a and Read ie N a 0x1D Bi7 7 im DDS um DDS MTM LN I Start LO NOE MOE Lm HEC AM Em lt a N A HE S GE LONE NM Read a Reading back this register returns the Firmware version as well as some Status signals coming from the CDCM7005 Version 1 9 Page 37 of 45 SMT350 User Manual DN Firmware Version 0x1D ore per me sno eng i eng eno ac mu Firmware Version 00000000 CDCM7005 CDCM7005 CDCM7005 Status Status Ref Status Lock lt a DDS Register 0 Start Phase Increment LSB 0x20 DDS Register 0 0x20 Bye Biz Bite Bits Bita Bt3 Bt2 Biti Bito DDS Start Phase Increment 15 8 00000000 DDS Start Phase Increment 7 0 00000000 DDS Register 1 Start Phase Increment MSB 0x21 EE DDS Register 1 0x21
12. more details refer to CDCM7005 datasheet CDCM7005 Register 1 0x11 sz ere Bes ena era enz Bit Bno x Freq Detect Manual or Auto Programmable Delay N 2 0 Programmable Delay M 2 0 Ref VCXO divider 11 4 Version 1 9 Page 33 of 45 SMT350 User Manual CDCM7005 Register 2 0x12 For more details refer to CDCM7005 datasheet CDCM7005 Register 2 0x12 Bye Bar Bte Bts pra Bis Bra Bii Bito dmm OUT2A0 OUT1B1 OUT1BO OUT1A1 OUT1A0 OUTOB1 OUTOBO OUTOA1 pe OUTOAO Output Signaling Selcetion 5 0 Register Selection 1 0 CDCM7005 Register 3 0x13 For more details refer to CDCM7005 datasheet CDCM7005 Register 3 0x13 Bye mr ms Bis era pits Bitz a Bio ia 90Div8 90Div4 ADClock Status Ref OUT4B1 OUTABO OUT4A1 VCXO a OUT4A0 OUT3B1 OUT3BO OUT3A1 OUT3A0 OUT2B1 OUT2B0 OUT2A1 CDCM7005 Register 4 0x14 For more details refer to CDCM7005 datasheet CDCM7005 Register 4 0x14 Bye Bar Bio bts am bro ene bri mg YO MUX Width FB MUX PDF Pulse CA CP Current PRECP CP DIR Register Selection 1 0 CDCM7005 Register 5 0x15 For more details refer to CDCM7005 datasheet CDCM7005 Register 5 0x15 BR7 Bee Bis Bia bis ene eni Bio E Reset ResHold Power Y4 MUX Y3 MUX Down Version 1 9 Page 34 of 45 SMT350 User Manual CDCM7005 Register 6 0x16 For more details refer to CDCM7005 datasheet
13. pe ea 17 Control Register Selde ad aca e is 25 Control Packet SIT ctlfe ee EG DS tdt d tota o ge due 25 Reading anad Writing Registe Siei E 25 MeMO Map NEE ie EG a a P 26 Register DeseripiONE eene ee 21 RESCUE EE saa T 2f Test Register OE TT 28 ADEA Register Ds Lc e 28 ADEA REOSE OS sleale 28 ADCA ee EE 29 Version 1 9 Page 4 of 45 SMT350 User Manual ADGB REGISTER Oi EE 29 ADEB RedlisiEl EE si EE ille 29 ADEB REGISTE EE 30 DAG Register Da OB ii destra ED Air 30 DAG Redlister 1 OKO dieci e 30 DAE REJSIE 2 0A do 31 DAE e o e OB reed 31 DAC Register 4 E 31 DAG Redster iD 31 DAC el ER do 32 DAE Register 7 OX sas EO aaa 32 CDGM7 00S Register 0 DX TO SE Re ee 32 CDCM7005 Register 1 Oil 32 CDCM7005 Register 2 0X2 0000 az 33 CDCM7005 Register 3 OE E 33 CDCM7005 Register 4 Ox14 ee ee ee EE ee Ee ee EE ee Ee ee EE ee ee nennen 33 CDCMZO005 Register D ak SE idein uu OE ee Ee bue 33 CDCM7005 Register 6 0x16 ee ee iii 34 CDEMT7OOS Register 7 OT iudei EE GE anello 34 Main Module Temperature not implemented 0x18 34 Main Module FPGA Temperature not implemented 0X19 34 Mezzanine Module Temperature not implemented Ox1A 34 Mezzanine Module Converters Temperature not implemented Ox1B 35 Miscellaneous Register UNI 35 Updates Read back and Firmware Version Registers
14. reset while not used to reduce the global power consumption Version 1 9 Page 28 of 45 SMT350 User Manual Test Register 0x1 Any 8 bit value written in this register can be read back to check that the Comport used works properly Test Register 0x1 Bye Biz Bic Bis Bra Bis Bio bii Bto ADCA Register 0 0x2 For more details refer to ADS5500 datasheet ADCA Register 0 0x2 ZIA ge am mu s ons mes ono ora en am we NN et eme Rae OR Rees et mm a b 00000000 ETA O EEN meter eem 00 Ron sergegreuerees beween GO o 26 ME ADCA Register 1 0x3 For more details refer to ADS5500 datasheet ADCA Register 1 0x3 ge MA 000000 ene my ene ons ome oro mz em mo E eee o eran et mn v 9 Eg Rem Tee mme oo o ADCAReieri OR Y Semng Tei TRO Description L o o Normai ode ot operation GE o 0 At outputs are zeroes OOO pe c o0 ue ENSEM Ju Lesmasgesngg IO Version 1 9 Page 29 of 45 SMT350 User Manual ADCA Register 2 0x4 For more details refer to ADS5500 datasheet ADCA Register 2 0x4 a mu mno ons ema ono ora env ono Eg Re mune setting Pon msn OOS O Lp remise A o dec Poner Don Mode OOOO ADCB Register 0 0x5 For more details refer to ADS5500 datasheet A gie 000 ome mu ono ons mna ono ee sur ono ww gees NN Rae OR ee Umm
15. 00 Datasheet Texas Instrument http focus ti com docs prod folders print ads5500 htm DAC5686 Datasheet Texas Instrument http focus ti com docs prod folders print dac5686 htm CDCM7005 Datasheet Texas Instrument http focus ti com docs prod folders print cdcm7005 html Sundance High speed Bus SHB specifications Sundance ftp ftp2 sundance com Pub documentation pdf files SHB Technical Specification pdf Sundance LVDS Bus SLB specifications Sundance http www sundance com docs SLB 20 20Technical 20Specifications pdf TIM specifications ftp ftp2 sundance com Pub documentation pdf files tim_spec v1 01 pdf Xilinx Virtex 4 FPGA http direct xilinx com bvdocs publications ds031 pdf MMCX Connectors Hubert Suhner MMCX Connectors Surface Mount MMCX connector Sundance Multiprocessor Technology Ltd SMT368 Version 1 9 Page 10 of 45 SMT350 User Manual Functional Description In this part we will see the general block diagram and some comments on some the SMT350 entities Block Diagram The following diagram describes the architecture of the SMT350 coupled as an example with an SMT368 to show how mezzanine and base modules are connected together Power Temb ratur External ADC ROWEL Supplies 1 8 peratu Supplies 1 25 Trigger and 3 3 Volts Sensors 1 5 2 5 and 3 3 Volts ADC Input Channel A ADS5500 ChA Data 14 Ch A MMCX Signal ADC ChA Clo
16. 12 Daughter Module Interface Data Signals Connector and Pinout Bank B 23 Figure 13 Daughter Module Interface Data Signals Connector and Pinout Bank C 24 Figure 14 Setup Packet Structure i 25 Figure 15 Control Register Read Sequence ii 25 Figure 16 Register Memory Map 2f Figure 17 Firmware Block Dagram se ee ee ee Ee ee Ee ee ee Ee ee memes 40 Figure 18 Space available mo 41 Figure 19 Main Module Component Side esse i 42 Figure 20 Main Module SMT368 Solder Side occccocccccoccccccoccncconcncnoocnnononnnonocnnnonons 42 Figure 21 Daughter Module Component Gudde 43 Figure 22 Daughter Module Solder Side ooocccoccccocncoccnconcncnocononcnonncononcnnnnnnconnnnnnnnnnnons 43 Figure 23 Connectors Location i 45 Version 1 9 Page 6 of 45 SMT350 User Manual Physical Properties Dimension ism mx Am wem rose SuppyVotages ooo S Sworn AIN 1 2 Amps reset converters active 1 4 Amps max 0 14 Amp reset converters active 0 4 Amps max Ordering Information SMT350 Standard Product ADC inputs and DAC outputs are AC coupled SMT350 DC ADCs inputs are DC coupled and DAC outputs are AC coupled Version 1 9 Page 7 of 45 SMT350 User Manual Precautions In order to guarantee that Sundance s boards function correctly and to protect the module from damage the fol
17. 4 on the base module is responsible for handling data going coming to from one of the following destination source TI converters Comport TIM 40 standard Sundance High speed Bus SHB These interfaces are compatible with a wide range of Sundance s modules The memory on base module can be divided into two 16 bit wide independent blocks for storing incoming and or outgoing samples Converter configuration sampling and transferring modes are set via internal control registers stored inside the FPGA and accessible via Comport Module features The main features of the SMT 350 are listed below e Dual 14 bit 125MSPS ADC ADS5500 e Dual channel 16 bit 510 MSPS DAC DAC5686 e On board low jitter clock generation CDCM7005 e One external clocks two external triggers and one reference clock via MMCX connector e One SLB connector to link SMT 350 and SMT 368 e Synchronisation signals e All Analogue inputs to be connected to 50 Ohm sources e All Analogue outputs to be connected to 50 Ohm loads e Temperature sensors Version 1 9 Page 9 of 45 SMT350 User Manual Possible applications The SMT350 can be used for the following application this non exhaustive list should be taken as an example e High Intermediate Frequency IF sampling architecture e Cellular base station such as CDMA and TDMA e Baseband l amp Q systems e Wireless communication systems e Communication instrumentation Related Documents ADS55
18. R MMB DD CAP a ru E 2 Int et IO et GE a ENI Ch MCI L VEPIB ndn d na NC vec D OI EEN nD no Po 2 Vbb Veel R73 AEBI RES i w MLIBAL VEFIG RIF o IE HA r r 11120 m r4 Di bio es Figure 7 External Clock The main characteristics of the SMT350 Clocks are gathered into the following table External Reference Input Input Voltage Level 0 5 3 3 Volts peak to peak AC coupled Input Impedance 50 Ohm Termination implemented at the connector Frequency Range 0 100 MHz External Reference Output Output Voltage Level 1 6 Volts peak to peak AC coupled Output Impedance 50 Ohm Termination implemented at the connector External Sampling Clock Input Input Voltage Level 0 5 3 3 Volts peak to peak AC coupled Single ended or differential on option 3 3V Input Format LVPECL Frequency range 10 500 MHz Output Voltage Level Input Voltage Level 1 5 3 3 Volts peak to peak DC coupled and Single ended Termination Format implemented at the connector Differential Version 1 9 Page 17 of 45 SMT350 User Manual on option 3 3 V PECL Frequency range 62 5 MHz maximum External Clk Input to Ext Clk Out Ons between J29 and J4 Figure 8 Clock Architecture Main Characteristics Power Supply and Reset Structure The SMT350 gets two power sources from the base module 3 3 and 5 Volts Linear regulators are used to provide a clean and stable voltage supply to the analog co
19. SMT 350 User Manual Certificate Number FM 55022 Version 1 9 Page 2 of 45 SMT350 User Manual Revision History 11 10 05 18 01 06 25 01 06 31 10 06 11 12 06 25 01 2007 05 02 2007 21 02 2007 23 03 2007 18 12 2007 Changes Made ai Original Document Updates on ADC inputs and DAC EE impedances Added details on PHSTR synch Dac Trigger was missing Corrected 0x0 and 0x1C ES register descriptions LED description added as well as J1 description 14 PSR Connector list added Control structure corrected 15 PSR Figure 6 corrected EIE Scratch Test register description corrected ADC pe PLL register 0x2 corrected Details added to the clock circuitry 18 Pen Ordering Information added 19 PSR Version 1 9 Page 3 of 45 SMT350 User Manual Table of Contents mec Properties t ILLE 6 Ordering Informationen A lito o TTC 6 os Vida q rarae A ee See T NTFOdUC doe DEE 8 ON OE EER ER OMM AA OE EE EN 8 ModileiEalifes oe 8 Possible ADDICION S ER Ee pildoras 9 REldiEADOEUMERE nl 9 FUNCIONal DES e ss ES Ee UD DUET 10 Block Diagramma 10 VOodule Description 10 ADC CHINNE S EE EE EE iii lei erre 12 ADC Ma araeleils tl ee Se de Ge UR Ee 12 ADC MPU Slade retata 12 BBW Fe greg ace DAE emm 13 B SSEN 13 BAG e E Le LEE 13 CIOCK ea UIC MUS aaa 14 Power Supply and Reset Gtruchure ener 17 JUMPE AE EA AE IE N EE 17 GIGS Sulle 17 Mezzanine module Interface 2 b De Oe Nr E
20. a mme Gee regie ewe onr oem OOOO O o o Pu or tor sampinarequencis eb E a Ierseng ADCB Register 1 0x6 For more details refer to ADS5500 datasheet ADCB Register 1 0x6 CB Reitero OO S O Bye mi Bite Bes Bra Bes sita Biti Bto Ases eo es EA Rec Reserved N ADCB Register 1 0x6 Setting mm mm Description S Version 1 9 Page 30 of 45 SMT350 User Manual Eck o 1 Atoutouts are zeroes DAA fo Altoutputs are ones ADCB Register 2 0x7 For more details refer to ADS5500 datasheet TA gite am my sio ss ma ms sie sur mo HE Reserved Reserved Bad 00 ln LE Reed O Bait N S sg Pon oem OOS O o remise a 7 oomen SSS DAC Register 0 0x8 For more details refer to DAC5686 datasheet DAC Register 0 0x8 aC Register O BO Bye mi Bite Bis Bite Bas Bt2 Biti Bto EM 1 EM lt lt Low Freq int 7 0 EM _ DAC Register 1 0x9 For more details refer to DAC5686 datasheet DAC Register 1 0x9 Bye mi Bite sits Bits Bits Bt2 Bii Bito imm Freq int 15 8 P3 Freq int 23 16 Version 1 9 Page 31 of 45 SMT350 User Manual DAC Register 2 OxA For more details refer to DAC5686 datasheet DAC Register 2 OxA Bye Biz ete Bis Bia ets sie Bii Bto E Freq int 31 24 pa Phase int 7 0 DAC R
21. ace Data Signals Connector and Pinout Bank B Version 1 9 Page 24 of 45 SMT350 User Manual Bank A Bank B Bank C 13 57 41 43 81 83 24 68 Bank C DAC e Pinteme Sues Pinno Pin name Signal ossipion or Oaugher canto an moce or Der Casto van mame res ooo oaio cremea Je Les Been Geek zem open ee oen creman osea nen JL Dauomer Cardio men mae ee oet gege CA CT dawns cana m oram engen e posam paint Gesk osse Cad io mannose or ome Cardio men Moe e now omane crama oo Tess omamo creman tomum _ nei to owns e2 e onami omma osse Ge nien In ome Cardio mensa ss oona Dasinra ona m 00805 vanti cana e ponam orent Cerin o poson onan ommen Omugner Gio man moae or Omer Casto men mese s Teen omamo cremas loose Daan teraman so oos az cremers 100 DOM mama cremas ENE A AT EE NE N Er or ente NR m Le Jee r va CEC Dauger Cara to am mose In Dauomer Casto men mae m penea Let ne mme e Figure 13 Daughter Module Interface Data Signals Connector and Pinout Bank C Version 1 9 Page 25 of 45 SMT350 User Manual Control Register Settings The Control Registers control the complete functionality of the SMT350 They are setup via the Comport3 standard firmware provided The settings of the ADC triggers clocks and the configuration of the SHB interfaces and the internal FPGA data path settings can be configured via the Con
22. acturer Minimum Sampling Clock 10 MHz ADC DLL off Maximum Sampling Frequency 125 MHz ADC DLL on Figure 3 Main features ADC Input Stage Each ADC Analogue input is AC coupled via and RF transformer The 50 Ohm resistor between the connector and the first RF transformer is not fitted because the source impedance match is implemented between the second RF transformer and the ADC by the way of two 25 Ohm resistors AF Transformer hor AE BP ia CONNECTOR MMCX i l Second Dit gt rim De P Prim Dot 1 Second Doi e e ut 2 Sacond ET gt i a gt NG Ls 2 Secand CT D LL n 0 gt tr 3 Second A 4 Prim c SAT 4 Prim d d 3 Second E m D E ig ds N ol a TR 7 2345 1 G XX du SC DE J a em GI O Eeer CES bm 1402 CAP gt ND Figure 4 ADC Input Stage Version 1 9 Page 13 of 45 SMT350 User Manual Dual Channel DAC DAC Main characteristics The main characteristics of the SMT350 DAC are gathered into the following table Analogue Outputs Input voltage range 1 Vp p Full scale AC coupled DAC single ended outputs are to be connected to a 500 load which impedance matching implemented between DAC and RF transformers DAC Input 2 s Compliment or offset binary Data Format l l Changeable via control register SFDR 89dBs maximum manufacturer SNR 80dBs maximum manufacturer Maximum input data rate 160 MSPS CIkI DAC5686 Maximum Sampli
23. ch can be either on board generated or from an external reference or an external clock common to ADCs and DAC MMCX connector Digital samples travel to the FPGA on the base module via Version 1 9 Page 11 of 45 SMT350 User Manual the inter module connector SLB Sundance LVDS Bus used in this case as single ended DAC Digital samples are routed from the FPGA to the DAC via the inter module connector Internal interpolation scheme allows reaching 500 Mega Samples per second The DAC shows other modes such as Dual DAC Single side band Quadrature or up conversion Both outputs are AC coupled By default they are single ended but can optionally be differential The DAC mode is selected via Jumper J1 that enables or disables the DAC Internal PLL see DAC5686 datasheet for more details Clock generator and distribution All samplings clocks are generated by the same chip It allows having them all synchronized to a single reference clock Multi module Synchronization There are two types of synchronization available on the SMT350 The first one is frequency synchronization by passing the external reference clock to an other module It first goes through a 0 delay buffer and is then output Note that the synchronization is in frequency and not in phase The second type is register synchronization between DACs It is achieved by the way of an extra link between several modules to synchronize DAC internal registers DAC signal PHSTR pass
24. ck and Control 50 Ohm Conditioning 14 bit 125MSPS ChA amp ChB Data Clock and Control 60 SHBB ADC Channel A and Channel B ADC Input Channel B ADS5500 Ch B MMCX Signal ADC ChB ChB Data 14 50 Ohm Conditioning 14 bit 125MSPS lock and Control x is A e E Spare SHB connector ock In SHBA PECL Clock ADCs and DAC External Generation and Clock Out MMCX Distribution S based on DAC Clock CDCM7005 and Daughter Card Virtex 4 XCV4SX35 External Reference SN65LVPC23 interface 2xComports and Top and Bottom TIM Clock Out MMCX connector FF668 Package Control 24 Connectors SLB External Reference 448 IOs Clock In MMCX DAC Output Channel A Ch A MMCX Signal 16 Spare SHB connector 50 Ohm Conditioning DAC5686 and Gorrel SHBO Dual Channel DAC 16 bit 500MSPS Interpolation ChB Data 16 and Control DAC Output Channel B Ch B MMCX Signal 50 Ohm Conditioning SHBD DAC Channel A and External ADC Power ChA amp ChB Data Clock Channel B Trigger Daughter Card and Control 60 connector SLB SMT350 SMT368 Figure 2 Block Diagram Module Description The module is built around two TI ADS5500 14 bit sampling analog to digital converters and one TI DAC5686 dual 16 bit digital to analog converter ADCs Analog data enters the module via two MMCX connectors one for each channel Both signals are then conditioned AC coupling DC optional before being digitized Both ADCs gets their own sampling clock whi
25. crement value is coded on 32 bits It corresponds to the increment in phase on each sampling clock cycle Sweep Mode When used to generate a fixed frequency Start Phase Increment should be equal to Stop Phase Increment and Step Phase Increment should be equal to 1 For Registers 0x24 and 0x25 to take effect Bit 6 of register Ox1D must be set to 1 DAC Channel A is the Sine output of the DDS and DAC Channel B is the Cosine output of the DDS Both outputs are therefore is quadrature Version 1 9 FPGA Design Page 40 of 45 SMT350 User Manual The following block diagram shows how the default FPGA design is structured Other SMT module Serial Interfaces Comport Interface SHBB Interface SHBD Interface DDS Core Trigger Block Registers Route and Format 1024x32 Route and DI Format FIFO Ext Trigger ADC and DAC ADCA Serial bcd ADCB Serial HS DAC Serial ud Clock Serial SMT350 SLB ri Interface ra ei Connector ae 2x14 bits ADCs ChA and ChB 2x16 bits si and ChB SMT368 Virtex 4 FPGA Figure 17 Firmware Block Diagram All serial interfaces have been designed in accordance with manufacturers datasheets and validated by probing and checking against timing provided Version 1 9 Page 41 of 45 SMT350 User Manual Block of registers This implements what has previously been described in this document Space available in FPGA This is the summary provi
26. ded by Xilinx ISE 7 1 04i regarding the amount of resources required by the default FPGA design this is targeting a Virtex4 XC4VSX35 Logic Utilization Used Available Utilization Hotels Number of Slice Flip Flops Seth 30 720 Drs Number of 4 input LUT s d i 30 720 Drs Logic Distribution Number of occupied Slices zl 15360 142 Number of Slices contaming only related logic zl zl 100 Number of Slices containing unrelated logic zl LESS Total Number 4 input LUT s 2391 30 720 7 Number used as logic fede mm Number used as a route thru Ja Number used as Shift registers 4 Number of bonded IUE s 194 445 132 Number of BUFGABUFGCTALS d chs Number used as BUF Os Number used as BUFGCT ALS Number of FIFOTBAAME 1 bs Number used as FIFOT bs Number used as HAMBTbs Figure 18 Space available in FPGA 132 qe LO Coy Oo Cay A Version 1 9 Page 42 of 45 SMT350 User Manual PCB Layout The following figures show the top and bottom view of the main module the top view of the daughter card and the module composition viewed from the side gd AAA E i Pie TT ML Ga Figure 20 Main Module SMT368 Solder Side Version 1 9 Page 43 of 45 SMT350 User Manual 2xADS55008 TT dd idad KKK L jj e Ze mee ii TE ra xui D a n Er CDCM7005 Figure 21 Daughter Module Component Side DEA di Shahi
27. ed from one module to the other and driven by the master FPGA it resets the internal VCO Inter module Connector it is made of a power 33 pins and data connectors 120 pins It is called Sundance LVDS Bus Please refer to the SLB specifications for more details In the case of the SMT350 the SLB is used as single ended A global reset signal is mapped to the FPGA from the bottom TIM connector External Clock signals used to generate Sampling clocks There is one external clock common to ADCs and DAC When used the CDCM7005 is used as a clock multiplexer Also available an external reference clock that can be passed to an other SMT350 module with O delay External Trigger passed directly to base module There are two one for the ADCs and one for the DAC Temperature Sensor available for constant monitoring Not part of default firmware provided Version 1 9 Page 12 of 45 SMT350 User Manual ADC Channels ADC Main Characteristics The main characteristics of the SMT350 ADCs are gathered into the following table Analogue Inputs 2 4 Vp p 11 5 dbm 50 Ohm Full scale AC coupled ADC single ended inputs are to be connected to a 506 source Source impedance matching implemented between RF transformers and ADC Bandwidth ADC bandwidth 750 MHz ADCs Output Impedance Output Data Width 14 Bits 2 s Compliment or offset binary Data Format Changeable via control register SFDR 82dBs maximum manuf
28. egister 3 OxB For more details refer to DAC5686 datasheet DAC Register 3 OxB aC Register Bye Biz Bite Bits Bite Bt3 Bt2 Biti Bito a Phase _int 15 8 Pee ee EUR em CI mm cone rm BM 0 0 20 0 9 DAC Register 4 OxC For more details refer to DAC5686 datasheet DAC Register 4 0xC Bye mi Bite Bits Bits Bits Bt2 Bii Bito IE Dual_clk DSS gain 1 0 Qflag PII rng 1 0 DAC Register 5 OxD For more details refer to DAC5686 datasheet DAC Register 5 0xD Bye Bt7 Bte Bts eta eis Bt2 Biti Bto oa Daca_offset 7 0 L3 Daca gain 7 0 Version 1 9 Page 32 of 45 SMT350 User Manual DAC Register 6 OxE For more details refer to DAC5686 datasheet DAC Register 6 OxE Bye Biz Bre Bts Bta ml Brz Bei Bio Daca_offset 10 8 Daca_gain 11 8 feet lf 0000 par Dacb_offset 7 0 DAC Register 7 OxF For more details refer to DAC5686 datasheet DAC Register 7 OxF Te Renee a m s s ema ona eno ein ono Ha KM NN omm mmm A pei eci Emma ml we CDCM7005 Register 0 0x10 For more details refer to CDCM7005 datasheet CDCM7005 Register 0 0x10 Bye mi Bio Bis Bia Bis Bez Bii a VCXO divider 3 0 Reference Divider 9 6 mo Reference Divider 5 0 Register Selection 1 0 000000 CDCM7005 Register 1 0x11 For
29. lowing precautions should be taken They are static sensitive products and should be handled accordingly Always place the modules in a static protective bag during storage and transition When operated in a closed environment make sure that the heat generated by the system is extracted e g a fan extracting heat or blowing cool air Sundance recommends and uses PAPST 12 Volt fans Series 8300 producing an air flow of 54 cubic meters per hour equivalent to 31 8 CFM Fans are placed so they blow across the PCI bus as show on the following picture Figure 1 Fan across PCI Version 1 9 Page 8 of 45 SMT350 User Manual Introduction Overview The SMT350 is a single width expansion TIM that plugs onto the SLB base module SMT368 Virtex 4 FPGA and incorporates 2 Texas Instrument Analog to Digital Converters ADS5500 and a Texas Instrument dual channel Digital to Analog Converter DAC5686 The SMT350 implements a comprehensive clock circuitry based on a CDCM 005 chip that allows synchronisation among the converters and cascading modules for multiple receiver or transmitter systems as well as the use of an external reference clock It provides a complete conversion solution and stands as a platform that can be part of a transmit receive base station ADCs are 14 bit and can sample at up to 125 MHz The DAC has a resolution of 16 bits and is able to update outputs at up to 500MHz All converters are 3 3 Volt The Xilinx FPGA Virtex
30. ment 31 24 WES DDS Stop Phase Increment 23 16 The Stop Phase Increment value is coded on 32 bits DDS Data registers 0x22 and 0x23 Each value corresponds to a frequency generated worked out as follows Fout Stop Phase Increment Fpac sampling MHz 2 When the DDS is used in sweep mode Start Phase Increment should be lower than Stop Phase Increment and Step Phase Increment should be greater than 0 When used to generate a fixed frequency Start Phase Increment should be equal to Stop Phase Increment and Step Phase Increment should be equal to 1 For Registers 0x22 and 0x23 to take effect Bit 5 of register 0x1D must be set to 1 DAC Channel A is the Sine output of the DDS and DAC Channel B is the Cosine output of the DDS Both outputs are therefore is quadrature The Maximum Phase increment value supported by the design is 0x40000000 which corresponds to a frequency of 30 72MHz when sampling at 122 88MHz with no interpolation DDS Register 0 Step Phase Increment LSB 0x24 DDS Register 4 0x24 Bye Bi7 Bite Bits Bra Bts Bt2 Bii Bito re DDS Step Phase Increment 15 8 IE DDS Step Phase Increment 7 0 Version 1 9 Page 39 of 45 SMT350 User Manual DDS Register 5 Step Increment MSB 0x25 D DDS Register 5 0x25 Bye Biz Bt6 Bis Bt4 ets Bitz Biti Bito IEEE DDS Step Phase Increment 31 24 lao DDS Step Phase Increment 23 16 The Step Phase In
31. ng rate 500 MSPS CIk2 DAC5686 Jumper J1 disables position 1 2 also called External Clock Mode or enables position2 3 also called Internal Clock Mode the DAC internal PLL Impedance DAC output stage The following piece of schematics shows how the DAC outputs are coupled The DAC5686 generates differential output signals that are fed into an RF transformer Ohm ratio 4 that makes both DAC channels AC coupled 100 Ohm resistors to Vcc on the primary stage of the transformer allow balancing the secondary stage to 50 Ohm single ended Note that R153 is not mounted Version 1 9 Page 14 of 45 SMT350 User Manual n n n LL LL LU oc r i x A E Kc S OS YS u a a mei Git CONNECTOR MMBX 1 Jas Figure 5 DAC Output Stage Clock Structure There is one integrated clock generator on the module CDCM7005 Texas instrument The user can either use this clock on board or provide the module with an external clock input via MMCAX connector YO ADC Channel A ADC ChA ADS5500 TI 14 bit 125MSPS Y1 ADC Channel B ADC ChB ADS5500 TI Clock Synthesizer 14 bit 125MSPS Y3 DAC CLK1 External Reference Clock 50 Ohm and Jitter Cleaner Texas Instrument DAC DAC5686 TI Y4 DAC CLK2 500MSPS Y2 Feddback FPGA Multi module Synch Ref Clock 50 ohm Dual clock Mux 2 to 1 SN65LVPC23 doo7 OXOA On board LVPECL Clock Signals VCXO gt
32. nverters JumperJ1 There is one jumper 3 pin header on the board It is to control the power supply of the DAC internal PLL When fitted on positions 2 and 3 the PLL is enabled whereas on positions 1 and 2 it is disabled Please refer to the DAC5686 datasheet for more details Green LEDs There are 7 LEDs on the SMT350 Daughter Module Five are dedicated for power supplies monitoring LED1 1 8V DAC LED2 3 3V Clock LED3 3 3V DAC LED4 3 3V ADCA LED6 3 3V ADCB should be all ON when the board is under power They state that power supplies all work fine LEDS ADCs should be flashing once the ADC Clocks are set up It is actually a divided version of ADCA sampling clock LED7 DAC is a divided version of PLLLOCK coming from the Dac DAC5686 Mezzanine module Interface The daughter module interface is made up of two connectors data and power The first one is a 0 5mm pitch differential Samtec connector This connector is for transferring data such as ADC or DAC samples to and from the FPGA on the main module The second one is a 1mm pitch Samtec header type connector This connector is for providing power to the daughter card Sundance defines these two connectors as the Sundance LVDS Bus SLB It has originally been made for data transfers using LVDS format but can also be used with single ended lines which is the case for the SMT350 To know more about the SLB please refer to the SLB specifications Version 1
33. trol Registers Control Packet Structure The data passed on to the SMT350 over the Comport must conform to a certain packet structure Only valid packets will be accepted and only after acceptance of a packet will the appropriate settings be implemented Each packet will start with a command 4 bits 0x1 for a write operation 0x2 for a read operation information followed by a register address 12 bits see table Memory Map followed by a 16 bit data This structure is illustrated in the following figure Byte Content enz ene ers ena bs ea em nm 3 2 1 0 E Ed Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 ia Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 O baar pass Deas bass Daas pi Figure 14 Setup Packet Structure Reading and Writing Registers Control packets are sent to the SMT350 over Comport3 This is a bi directional interface The format of a Read Packet is the same as that of a write packet 1 Write Packet ComPort 3 SMT350 Figure 15 Control Register Read Sequence Version 1 9 Page 26 of 45 SMT350 User Manual Memory Map The write packets must contain the address where the data must be written to and the read packets must contain the address where the required data must be read The following figure shows the memory map for the writable and readable Control Registers on the SMT350 Address Readable Registers Read back
34. ure 10 Mezzanine Module Interface Power Connector and Pinout The following few pages describes the signals on the data connector between the main module and the daughter card Bank A on the connector is used for the ADC Channels A and B Bank C is used for the DAC channels A and B Bank B is used for system clock and trigger signals ADC DAC Clock control signal Version 1 9 Page 21 of 45 SMT350 User Manual Bank A Bank B Bank C 13 57 41 43 81 83 24 68 Bank A ADCs ce Pinteme Sues Pinno Pane Signal esco Or Oaugher canto an oss or Der cardo Mao 1 oomp L ntgen 2 popop Oma Outs crema 3 ponm mon gan a posen bas Ons omman NN Omer cao an moade or ome roto men mae s oos oa oua choweta s oom baw ous Chala z ponm Dmc e poste enee EE DON ous Ou Gansta Tu Tess sn m ponn paoui croman 8 esoe MN osse Ca nien In Dagar Cardio men mae o onse oaa ow12 cremara In mm Oma Ou Chanel CATE 0 Omer Casto Wain Mose Lio oonan sa oz cromelo 20 ooeur Oma Outs creme or outer cato Man ogue Oaigher Casto Wan moaue a cows oats ots crams nop Oma ou crm ENE NN ONEWE NI Onugner Gato am Mosse 0 onge Casto men mae Lm nos ous Ou cui A ECN 2r oomen a ou1s crameis 28 mge Sangen ENE TIEN IE Casto me ose e oo oaa ow 13 cremers 20 mm _ Over Range Cramers leem Je f CET ousie Ge ro man moae or Dauomer Cardio van mae loop mmo oat Game a Sos
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