HMC900lP5e
Contents
1. Table 16 Reg 04h Calibration RC BIST Strobe Calibration strobe register is used only to initialize a calibration cycle Writing any value to this register serves to request a new calibration cycle Note that this register is also used to start the Built In Self Test RC BIST mode and this is used to test the fault coverage of the RC calibration engine Bit Name Width Default Description 23 0 Request calibration 1 0 Writing to any bit in this register starts a calibration cycle Table 17 Reg 05h Clk Period Bit Name Width Default Description Sets the clock period for the RC calibration circuit Clock period entered is in 14 0 clock_period 14 0 15 0000h pico seconds i e 1 40 MHz clock 25000ps 110000110101000b 61A8h 23 15 unused Table 18 Reg 06h Measure Adjust Correction value used to adjust RC Calibration result Value is in 1 024ns increments Bit Name Width Default Description Correction value to ADD to counter output before counter is decoded for calibration setting Number is in 2 s complement format Note this applies to all settings universally 8 0 meas_adj 8 0 9 000h 23 9 unused Table 19 Reg 07h Unused For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On lin2. z QD A um lt 2 a 2 lt co TT N lt c LL SHMittile MICROWAVE CORPORATION yo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 10 Calibration Code Look up Table fine_tune_ratio fine_bandwidth_code 3 0 min typ max MHz MHz MHz MHz MHz MHz 0000 0 790 0 803 0 818 0001 0 818 0 832 0 846 0010 0 846 0 862 0 878 0011 0 878 0 893 0 909 0100 0 909 0 926 0 943 0101 0 943 0 959 0 976 0110 0 976 0 994 1 012 0111 1 012 1 030 1 048 1000 10 48 1 068 1 087 1001 1 087 1 107 1 128 1010 1 128 1 148 1 169 1011 1 169 1 189 1 210 3 Program the SPI for the given device with the coarse and fine bandwidth code and instruct the device to use the provided instructions a Write coarse bandwidth code 3 0 to Reg 02h bits 9 6 b Write fine bandwidth code 3 0 to Reg 03h bits 3 0 Instruct HMC900LP5E to use provided codes by setting Reg Oth bit 4 Filter Bandwidth Setting After Calibration After the initial filter calibration is completed as above the filter bandwidth can be changed to an arbitrary bandwidth by recalculating coarse bandwidth code 3 0 and fine bandwidth code 3 0 from the previously determined ctune This results in the same coarse bandwidth code 3 0 and fine bandwidth code 3 0 as if the HMC900LP5E was recalibrated as described above If ctune is unknown but
3. lt co TT N lt c LL MICROWAVE CORPORATION vo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY HMC900LP5E Application Information The HMC900LP5E provides an attractive alternative to other discrete filter solutions due to it s unmatched flexibility in supporting a wide range of bandwidths in today s complex multi carrier systems and multi standard systems Typical architectures supporting multiple bandwidths have required either large board real estate or compromised filter selection which come at the expense of price or performance The HMC900LP5E overcomes this limitation by allowing the system designer to optimize the bandwidth for the required signal The HMC900LP5E overcomes the matching problem that discrete filters present with respect to baseband signal processing The matched dual filter paths provide excellent gain and phase balance between the two channels eliminating the image problem which results from poor matching The HMC900LP5E provides selectable gain and a flexible output driver further increase system integration and reduce board area OH HMC822 HMC794 HMC821 HMC597 HMC960 HMC900 SPI CONTROL Figure 19 Typical Receive Path Block Diagram showing HMC900LP5E PHO HMC794 HMC822 V HMC900 HMC795 SPI CONTROL Fig
4. OTP_Coarse_Bandwidth 3 Non volatile version of SPI values found in Reg 02h Settings 15 reserved reserved 23 16 unused Table 23 Reg OBh OTP Write Enable Bit Name Width Default Description 0 EFR_Write_enable 1 0 Enables OTP Programming 23 1 unused Table 24 Reg OCh OTP Write OTP address register is used in programming of OTP Bit Name Width Default Description 3 0 OTP Address 4 0 Address of OTP bit to be set z QD D A um lt 2 2 lt co TT N lt c LL 23 4 unused For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com eeriitite mwcoooresE MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 25 Reg 0Dh OTP Write Pulse OTP strobe register is used in programming of OTP Bit Name Width Default Description 23 0 reserved 1 0 reserved Table 26 Reg OEh RC BIST Enable Bit Name Width Default Description 0 enable RCBIST mode 1 0 RC BIST mode enable 23 1 unused Table 27 Reg OFh RC BIST Out Bit Name Width Default Description 15 0 crc BIST 15 0 16 0 RC BIST CRC check r
5. Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Z Qn U or o lt 2 5 n lt Qn lt z QD A um lt 2 a 2 lt co TT N lt c LL MICROWAVE CORPORATION vo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Theory of Operation The HMC900LP5E consists of the following functional blocks 1 Input Gain Stage 2 6th Order LPF 3 Output Driver 4 RC Calibration Circuit 5 Bias Circuit 6 One Time Programmable Memory 7 Serial Port interface 8 Built in Self Test RC BIST Input Gain Stage The HMC900LPBSE input stage consists of a programmable 0 or 10 dB gain stage which in turn drives the 6th order LPF A block diagram showing input impedance of the channel is presented below Q channel is similar VDDI ESD 5000 5000 1 5kQ IP Z ESD PADDLE GND 1 4 VJ esp IN A 5000 5000 1 5kQ ESD Figure 21 Input Stage Block Diagram 6 Order Low Pass Filter LPF The LPF allows for coarse bandwidth tuning by varying the capacitive elements in the filter while the fine bandwidth tuning is accomplished by varying the resistors Note that all opamps in the LPF are class AB for minimum power consumption in the filter while maintaining excellent distortion characteristi
6. Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHIUIC HmcoooLPse MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 5 Pin Descriptions Pin Number Function Description Interface Schematic 1 3 8 10 The pins are not connected internally however all data eV N C shown herein was measured with these pins connected to 17 24 25 32 RF DC ground externally Quadrature Q Channel 5V Supply 9 Must be locally decoupled GND CMQ L 8 5 CMQ Quadrature Q channel output common mode level VDD 6 7 OQN Quadrature Q channel positive and negative differential 4 Laava outputs p D VDD z 11 CALCK Calibration clock input CALCK O u VDD CC SDI 12 14 15 SCLK SDI SEN SPI Data clock data input and enable respectively TOTI T aem VDD 13 SDO SPI Data Output joo Q 16 DVDD Digital 5V Supply Must be locally decoupled to GND VDD dp 18 19 OIN OIP Inphase I channel negative and positive differential cot Ano RE outputs respectively N For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com z
7. Matched filter paths provide excellent quadrature balance making the HMCO9OOLPSE ideal for I Q communications applications The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJ Hittite MICROWAVE CORPORATION RoHS v EARTH FRIENDLY Table 1 Electrical Specifications HMC900LP5E 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER T 25 C VDDI VDDQ VDDCAL VDDBG DVDD 5V 5 GND OV 400 load unless otherwise stated Parameter Conditions Min Typ Max Units Analog Performance p 1 min gain setting 0 dB Passband max gain setting 10 dB 3dB corner frequency fc 1 passband group delay variation group delay 3dB frequency fc e g for 1 0 dB BW of 40 MHz fc 44 9 MHz max group delay variation 2 0 400 44 9 MHz 8 9 ns Programmable to any frequency in this range Bypass mode 75 100 MHz aoe uncalibrated 20 3dB corner frequency variation calibrated 2 5 3 5 3dB corner frequency variation vs temperature over 40 C to 85 0 03 Max passband gain error vs ideal 6th order LPF H s 0 5 dB at 0 1dB BW 0 73 fc 0 250 at
8. a 3 5 MHz corner frequency 3 2 G represents the gain setting of either 0 dB G 0 or 10 dB G 1 3 3 L represents the linearity setting of either standard L 0 or high linearity L 1 Note that the high linearity setting is recommended only for bandwidth settings above 30 MHz For example to order the HMC9OOLP5E pre programmed for 50 MHz dB frequency 10 dB gain and standard linearity setting please specify part number HMC900LP5E 50010 Table 8 Custom Part Frequency Options BBB frequency for custom part actual frequency is BBB x 0 1 MHz 035 048 066 088 121 163 218 292 400 036 049 068 091 124 167 224 300 401 037 050 069 093 128 171 229 307 411 038 052 070 095 131 175 235 315 422 039 053 071 098 134 179 240 322 432 040 054 073 100 137 180 246 330 443 041 056 075 102 140 184 253 338 454 042 057 076 105 141 188 259 347 465 043 058 078 108 144 193 265 355 476 044 060 080 110 148 198 272 364 488 045 061 082 118 151 203 278 3738 500 046 063 084 116 155 208 280 382 047 064 086 119 159 213 285 392 1 The Output IP2 and Output IP3 for the two linearity settings are shown in Figure 8 and Figure 9 High linearity setting improves linearity for bandwidths greater than 30 MHz at the cost of increased current consumption additional 25 mA For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive
9. or can drive up to 2000 in parallel with 50 pF to AC ground per differential output Note that the output common mode of the driver is controlled directly via the CMI CMQ pin and can be set as per Table 1 Electrical Specifications Also note that driver loading does not impact filter transfer responses The output common mode of the driver is controlled directly via the CMI CMQ pin and can be set as per the Table 1 Electrical Specifications A block diagram showing output connections is presented below PADDLE GND CMI ESD NO EXTERNAL ADC DRIVER VDDI REQUIRED esp 100 esp N PADDLE GND ADC esp V7 100 OIN esp O VDDI Figure 22 Output Driver Block Diagram RC Calibration Circuit The RC Calibration block uses a known user supplied clock to measure an on chip RC time constant This measurement is representative of the uncorrected corner frequency error for a given bandwidth for the LPF Calibration is normally done at room temperature Refer to Table 1 Electrical Specifications for further details on the variation of the 3dB cutoff point with temperature With this information the HMC900LPBSE can correctly fine tune the LPF by adjusting the resistors in the LPF to center the corner frequency to the desired bandwidth The calibration for the HMC900LPS5SE proceeds as follows 1 the clock used for calibration is programmed between 20 MHz and 1
10. the current desired frequency is known then the value of ctune needs to be estimated based on the values of coarse bandwidth code 3 0 and fine bandwidth code 3 0 and the corresponding nominal frequencies in Table 9 and Table 10 For example if the dB bandwidth for the HMC900LPB5E was factory pre programmed to a customer defined requirement of 34 MHz and coarse bandwidth code 3 0 and fine bandwidth code 3 0 are 0111 and 1001 respectively as determined from Reg OAh for a pre programmed part or from Reg 02h for a non programmed part then ctune can be estimated as follows 1 Lookup the nominal coarse bandwidth and fine bandwidth frequencies a From Table 9 the nominal coarse frequency is 35 0 MHz b From Table 10 the nominal fine normalized frequency is 1 107 MHz MHz or simply 1 107 2 Estimate ctune as ctune 35 MHz 1 107 34 MHz 1 13956 This value of ctune can now be used to calculate any arbritary filter frequency as described above For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHIUIC nwcooresE MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Output Driver The 9 5 output driver consists of a differential class AB driver which is designed to drive typical ADC loads directly
11. 0 5dB BW 0 83 fc at 1 0dB BW 0 89 fc at 3 0dB BW at fc 0 400 min gain fc 3 5 MHz 22 nV rtHz min gain fc 28 MHz 22 nV rtHz Output Noise f 1 MHz max gain fc 2 3 5 MHz 25 nV rtHz max gain fc 28 MHz 25 nV rtHz min gain fc 2 3 5 MHz 8 nV rtHz max gain fc 3 5 MHz 8 nV rtHz Output noise f gt 10 fc min gain fc 28 MHz 8 nV rtHz max gain fc 28 MHz 8 nV rtHz Noise Figure 100 source min gain dB Input referred Out of Band IM3 half scale tones at 2fc and 3fc IMS product at 0 5fc max gain min gain 19 dB Noise Figure 1 KO source max gain 12 dB half scale tones at 0 8fc and 0 6fc Input referred Passband IM3 fc 20 MHz 60 dBc fc 50 MHz 50 dBc half scale tones at 1 2fc and 1 6fc IM3 product at 0 8fc Input referred Out of Band IMS fo 20 MHz 60 dBc fc 50 MHz P fc 20 MHz 50 dBc fc 50 MHz 21 45 dBc half scale tones at 0 8fc and Output IP3 inband fc i 25 30 dBm fc 50 MHz 17 20 dBm half scale tones at 1 2fc and Output IP3 out of band Te pice REB 25 30 dBm fc 50 MHz P 17 20 dBm half scale tones at 2fc and 3fc Output IP3 out of band M deis s m 5 fc 50 MHz 17 20 dBm half scale tones at 0 8fc and Output IP2 inband RE un 28 m fc 50 MHz P 55 60 dBm For price delivery and to place orders please contact Hittite Microwave Corporati
12. 00 MHz via Reg 05h Also note that for clocks between 20 MHz and 40 MHz the doubler must be enabled via Reg Oth the RC calibration circuit is enabled via Reg 01h a calibration cycle is initialized by writing to Reg 04h For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com 2 xX A lt A e Z lt lt o LL z QD A lt 2 a 2 lt co TT N lt c LL BBHittite MICROWAVE CORPORATION y04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY When complete the calibration value can be retrieved from Reg 08h and if desired the calibration results can be overridden via Reg O3h Bias Circuit A band gap reference circuit generates the reference currents used by the different sections The bias circuit is enabled or disabled as required with the or Q channel as appropriate One Time Programmable Memory OTP The HMC900LP5E features one time programmable memory which can be programmed by the end user or ordered from the factory precalibrated The OTP memory is programmed via the standard 4 wire serial port SPI as follows 1 enable OTP write mode see Reg OBh bit 0 enables OTP programming 2 read the status of the OTP a
13. 900LP5E registers the data bits in the next 23 rising edges of SCLK total of 24 data bits The LSBs of the data bits represent the address of the register that is intended to be read 4 Host places the 5 register address bits on the next 5 falling edges of SCLK MSB to LSB while the HMC900LPSE reads the address bits on the corresponding rising edge of SCK For a read operation this is 00000 5 Host places the 3 chip address bits 101 on the next 3 falling edges of SCK MSB to LSB Note the HMC900LPBSE chip address is fixed as 5d or 101b 6 SEN goes from low to high after the 32 rising edge of SCK This completes the first portion of the READ cycle 7 The host asserts SEN active low Serial Port Enable followed by a rising edge SCLK 8 HMC900LP5E places the 24 data bits 5 address bits and 3 chip id bits on the SDO on each rising edge of the SCK commencing with the first rising edge beginning with MSB 9 The host deasserts SEN i e sets SEN high after reading the 32 bits from the SDO output The 32 bits consists of 24 data bits 5 address bits and the 3 chip id bits Note that the data sent to the SPI during this portion of the READ operation is stored in the SPI when SEN is deasserted This can potentially change the state of the HMC900LPBSE If this is undesired it is recommended that during the second phase of the READ operation that Reg Oh is addressed with either the same address or the address of anoth
14. A um lt 2 a 2 lt co TT N lt c LL For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Hittite MICROWAVE CORPORATION 040811 RoHSv HMC900LP5E 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY HMC900LP5E Usage Information The HMC900LP5E addresses different filter applications such as fixed frequency or variable bandwidth implementations dependent on the part selected see HMC900LPSE Ordering Information and the control provided to the HMC900LP5E These modes provide the user with different filter options depending on the system implementation An overview of these trade offs are shown below Table 7 HMC900LP5E Modes of Operation Function Unprogrammed Pre programmed SPI CALCK Comments HMC900LPS5E 00000 HMC900LPS5E BBBGL Req d Req d bur Fixed Bandwidth Filter Yes Yes Default Bandwidth and Gain Bandwidth and Pre programmed gain and bandwidth and Gain as defined Gain as defined by setting after Power On Reset by register defaults pre programming at No No are defined when ordering the part See POR 3 5 MHz OdB gain factory HMC900LP5E Ordering Information Typical Corner Frequency Ac Ln Accuracy is with respect to ba
15. ANALOG HittiLc DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK jac A l lt Z e Z lt t o LL EJ Hittite MICROWAVE CORPORATION v04 0811 RoHS v EARTH FRIENDLY Typical Applications The HMC900LP5E is ideal for various modulation systems e Baseband filtering before A D or after D A converters for point to point fixed wireless or base station transceivers GSM GPRS WCDMA amp TD SCDMA Integrated direct conversion receiver DCR when mated with mixer and VGA Software defined radio applications Anti aliasing and reconstruction filters Test and measurement equipment Functional Diagram c See8822 e e e R ER KN s D 24 N C vDDQ 2 23 VDDI N C 3 22 VDDCAL vDDQ 4 DX yom 27 2i VDDI CMQ 5 20 CMI OQP 6 19 OIP 7 SERON 18 OIN 87 D N C e B EE EI B GND HMC900LP5E 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Features Low Noise Figure 12 dB High linear
16. Characteristics DVDD 5V 5 GND OV Parameter Conditions Min Typ Max Units ty SDI to SCK Setup Time 8 nsec to SDI to SCK Hold Time 8 nsec tg SCK High Duration 18 10 nsec t4 SCK Low Duration 10 nsec t5 SEN Low Duration 20 nsec te SEN High Duration 20 nsec t7 SCK to SEN Ibl 8 nsec tg SCK to SDO Out 8 nsec a The SPI is relative insensitive to the duty cycle of SCK b SEN must rise after the 32nd falling edge of SCK but before the next rising SCK edge If SCK is shared amongst several devices this timing must be respected c Typical load to SDO 10pF max 20pF For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHIUIC HmcoooLPse MICROWAVE CORPORATION y04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Built In Self Test RC BIST The HMC900LP5E RC Calibration state machine features built in self test RC BIST to facilitate improved device testing The RC BIST can be exercised as follows 1 apply reset to the chip via a power cycle hard reset or via the SPI soft reset Soft reset is accomplished by writing 20h to Reg Oh followed by writing OOh to Reg Oh 2 setup the RCCAL input parameters if desired Note that the RC BIST will work with the default settings from power up however test c
17. Duty Cycle 40 50 60 SCLK Frequency 20 30 MHz Digital Input Low Level VIL 0 4 V Digital Input High Level VIH 1 5 V Digital Output Low Level VOL 0 4 V Digital Output High Level VOH Vdd 0 4 Power Supply Analog amp Digital Supplies 4 75 5 5 25 V Supply Current 130 mA Power on Reset 250 us 1 The attenuation of the filter transfer function can be calculated directly at any frequency f as attenuation 10 log o 1 f f9 68 where f is the bandwidth or corner frequency for the filter Similarly for a given maximum attenuation and bandwidth fp the frequency at which the attenuation is achieved can be calculated as f 10 attenuation 10 4 A 1 2 6 t Note that for a 6th order Butterworth filter the 1dB bandwidth is at 89 of the filter bandwidth and 0 5dB bandwidth is at 84 of the filter bandwidth 2 Specified distortion is measured with in high linearity mode with opamp_bias 1 2 2 and drvr_bias 1 0 2 See Reg 02h Table 2 Test Conditions Unless otherwise specified the following test conditions were used Parameter Condition Temperature 25 C Filter Bandwidth Setting 20 MHz Gain Setting 0dB bias settings opamp bias 1 0 drvr bias 1 0 01 10 Input Signal Level 2 Vppd Input Output Common Mode Level 2 5V Output Load 2000 Output Supply Analog 5V Digital 5V For price delivery and to place orders please contact H
18. FILTER BANDWIDTH MHz 1 OIP3 and OIP2 measured into 400 O differential load OIP3 and OIP2 can be translated from dBm into dBVrms as follows IPx dBVrms IPx dBm 4 dB For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHIUIC nwcooresE MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Figure 13 3 5 MHz Filter Magnitude and Figure 14 50 MHz Filter Magnitude and Group Delay Group Delay 5 su AV140 dNOYD Q3ZI1IVINHON su Av14d dNOYD Q3zrviWHON rou Dela gt ii a acra Group Delay 15 E E 1 91 1 10 1 10 100 FREQUENCY MHz FREQUENCY MHz Figure 15 HMC900LP5E OIP2 at 10 MHz amp Figure 16 HMC900LP5E OIP3 at 10 MHz amp 10 1 MHz n 10 1 MHz 11 40 20 0 a a E E 20 2 2 E 40 5 extrapolated OIP2 94 5 o i 1 o ss D cile 60 80 100 120 20 0 20 40 60 80 100 Vin dBVrms tone Vin dBVrms tone Figure 17 Filter I Q Channel Isolation 0 m o A o I Q FILTER ISOLATION dBc o do o z CD U A lt 2 a 2 lt co lt c LL 100 1 10 FREQUENCY MHz 1 14 MHz Coarse BW Op Amp bias 01 F
19. On Reset by register defaults respr dremmind at are defined when ordering the part See dp POR y reg S PEE PhO g HMC900LPSE Ordering Information 3 5 MHz OdB gain factory e Typical Corner Frequency Accuracy after POR before 20 2 5 S WIN TERPECO Z after POR User Calibration lt Accuracy is with respect to calibrated eoa Typical Corner Frequency Ac 155 Yes A User Calibration requires access to the curacy after User Calibration 2 5 H 2 5 9n dp at calibrated bandwidth HMC900LP5E via the digital serial port SPI and requires a valid calibration clock lt via CALCK pin Accuracy is with respect to the desired bandwidth LL User Calibration requires access to the HMC900LP5E via the digital serial port Typical Corner Frequency Ac SPI and requires a valid calibration clock curacy after User Calibration 5 0 5 0 ee at non calibrated bandwidths Wie pi CALCK See Filter Bandwidth Setting for informa tion regarding changing the bandwidth after calibration when further calibration is not possible For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com z QD A um lt 2 a 2
20. QD A um lt 2 a 2 lt co TT N lt c LL EJ Hittite MICROWAVE CORPORATION yo4 0811 HMC900LP5E RoHS v EARTH FRIENDLY 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 5 Pin Descriptions Continued Pin Number Function Description Interface Schematic ov E 20 CMI Inphase 1 channel output common mode level 21 23 VDDi Inphase 1 Channel 5V Supply Must be locally decoupled to GND 22 VDDCAL Calibration 5V Supply Must be locally decoupled to GND IN 26 27 IIP IIN Inphase I channel positive and negative differential inputs respectively 28 VDDBG Bias 5V Supply Must be locally decoupled to GND VBG 29 VBG 1 2V Bandgap output testing only 1QP IQN 30 31 ION IQP Quadrature Q channel negative and positive differential inputs respectively For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHIUIC HmcoooLPsE MICROWAVE CORPORATION 04 0811 a 50 MHz DUAL PROGRAMMABLE E LOW PASS FILTER with DRIVER Evaluation PCB JA J2 23 4 J4 J3 2 11 The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be c
21. Reg 09h 23 0 23396981 For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Z D U or o lt 2 5 n lt Qn lt HmcoooLPsE MICROWAVE CORPORATION yo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Register Map Table 13 Reg 01h Enable Bit Name Width Default Description 0 OTP DontUse 1 0 Default use stored OTP values only if OTP is programmed 1 cal enable 1 0 Enable RC Calibration circuit 2 filter enable 1 1 Enable channel gain stage filter and driver 3 filter Q enable 1 1 Enable Q channel gain stage filter and driver 4 force_cal_code 1 0 Force calibration setting to use SPI values Reg 03h Calibration 0 Doubler Disabled RC Calibration clock 40 MHz lt RC calibration clock lt 80 MHz 5 doubler_enable 1 0 1 Doubler Enabled RC Calibration clock 20 MHz RC calibration clock lt 40 MHz Note calibration clock duty cycle must be within 5096 10 9 6 reserved 4 0000 23 10 unused Table 14 Reg 02h Settings Bit Name Width Default Description Opamp bias setting 00 min bias 1 0 opamp bias 1 0 2 01 11 max bias opamp_bias 1 0 01 standard
22. bias characterized value opamp_bias 1 0 10 high linearity bias Driver bias setting 00 min bias 11 max bias drvr_bias 1 0 10 standard bias characterized value 3 2 drvr bias 1 0 2 10 VGA gain setting 4 gain_10dB 1 0 0 OdB VGA gain 1 10dB VGA gain Filter bypass setting 5 bypass filter 1 0 0 Filter bypass disabled 1 Filter bypass enabled Sets filter coarse tuning range 0000 3 5 MHz 0001 5 MHz 0010 7 MHz 0011 10 MHz 0100 14 MHz 0101 20 MHz 0110 28 MHz 0111 35 MHz 1000 50 MHz 9 6 coarse_bandwidth_code 3 0 4 0000 10 reserved 1 0 z QD D A um lt 2 a 2 lt co TT N lt c LL 23 11 unused For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHIUIC HmcoooLPse MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 15 Reg 03h Calibration Bit Name Width Default Description fine bandwidth setting override bits register 01 bit 4 force_cal_code must be set 0000 Minimum frequency 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Maximum frequency 3 0 fine_bandwidth_code 3 0 4 0000 23 4 unused
23. cs even in large signal swing conditions The attenuation due to the LPF can be calculated for any frequency f from the standard Butterworth transfer function for a 6th order filter Specifically the attenuation of the filter in dB can be calculated as attenuation 10 log o 1 f f 9 where f is the 3 dB bandwidth or corner frequency for the filter Note that for a 6th order Butterworth filter the 1 dB bandwidth is 90 of f and the 0 3 dB bandwidth is 80 of f For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHHIUIC nwcooresE MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Filter Bandwidth Setting The 3 dB bandwidth of the HMC900LP5E is programmable anywhere within the range from 3 5 to 50 MHz This is accomplished via a two step process which involves 1 running calibration and 2 programming the appropriate coarse and fine bandwidth codes Once the settings for a given device are found they can be stored permanently in the non volatile memory See One Time Programmable Memory OTP To program the bandwidth of the HMC9OOLP5E to a desired bandwidth 1 Run a calibration routine the procedure is as follows Run filter calibration cycle to determine the particular calibratio
24. ctive flag see Reg 08h bit 5 is the OTP active flag The Write Pulse Status OTP active flag must be 0 to allow the OTP to be programmed 3 write the OTP bit address to be set Reg OCh This address is a 4 bit number representing the address of the bit to be programmed Note that when programming a bit we change its state from 0 to 1 and this operation cannot be reversed OTP bit addresses can be found in Reg 08h 4 start the OTP Write operation Write any data to the OTP strobe register Reg ODh 5 read the status of the OTP active flag Reg 08h bit 5 is the OTP active flag If bit 5 is set then the Write pulse is still high Repeat until bit 5 is O which indicates that the write pulse is finished 6 Repeat steps 3 to 5 to program the remaining desired bits Note that bit 13 OTP prg flag must be set by the user to use OTP values 7 When completed disable OTP write mode Reg OBh Serial Port Interface The HMC900LP5E features a four wire serial port for simple communication with the host controller Typical serial port operation can be run with SCK at speeds up to 30MHz The details of SPI access for the HMC900LP5E is provided in the following sections Note that the READ operation below is always preceded by a WRITE operation to Reg Oh to define the register to be queried Also note that every READ cycle is also a WRITE cycle in that data sent to the SPI while reading the data will also be stored by the HMC900LP5E when SEN goes hi
25. d paddle OMM 5 Outline Drawing Z TOP VIEW BOTTOM VIEW op 007 638 201 5 10 ad 016 0 40 7 193 4 90 008 0 20 MIN E JUUUUUUD O 1 24 i b ES PIN 1 T 1 r 3 A H900 ee Cj XXXX 22 m 5 022 0 56 ST LI 07 935 8 17 L2 SUE 3 16 LOT NUMBER O 43 88 souar 039 1 00 Z 031 5 NOTES 002 0 05 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC lt 000 0 00 SILICA AND SILICON IMPREGNATED ca ony T inno 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY HH H SEATING 8 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN PLANE 4 DIMENSIONS ARE IN INCHES MILLIMETERS 003 0 08 b LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD BURR LENGTH SHALL BE 0 15mm MAX PAD BURR HEIGHT SHALL lt 0 25 7 PACKAGE WARP SHALL NOT EXCEED 0 05mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GOUND m 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND LL PATTERN Table 4 Package Information Part Number Package Body Material Lead Finish MSL Rating 0 Package Marking P HMC900LP5E RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 1 Max peak reflow temperature of 260 2 4 Digit lot number XXXX For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive
26. e at www hittite com z QD a A lt 2 a Z lt co TT N lt c LL SHMittile MICROWAVE CORPORATION yo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 20 Reg 08h Calibration Status read only Bit Name Width Default Description i A fine bandwidth setting must run a calibration cycle to get valid data 8 fine bandwidth 4 0000 Valid states are 0000 to 1011 see Table 3 Reg 03h Calibration 4 cal busy 1 Calibration active flag 5 OPT write busy 1 OTP write active flag 23 6 unused Table 21 Reg 09h Calibration Count read only Bit Name Width Default Description 23 0 count read 23 0 24 Output of calibration counter in pico seconds unadjusted Table 22 Reg 0Ah OTP Values read only Bit l Name Width Default Description 3 0 OTP_fine_bandwidth_ 4 Non fine bandwidth code 3 0 Definition is same as per Reg code 3 0 Calibration 6 4 Rr Ma 3 7 OTP Gain 10dB 1 8 bypass filter 1 Non volatile version of SPI values found in Reg 02h Settings 10 9 OTP opamp bias 1 0 2 12 11 drvr bias 1 0 2 This flag must be set if the OTP values are to be used and must be set by the 13 OTP prg flag 1 user If not set this flag overrides bit 0 of Reg Oth 14
27. er register to be read during the next cycle 10 This completes the READ cycle For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Z xX A lt A e Z lt lt o LL z QD A um lt 2 2 lt co N lt co LL MICROWAVE CORPORATION vo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Serial Port Bus Operation with Multiple Devices The SPI bus architecture supports multiple HMC devices on the same SPI bus Each HMC900LP5E on the bus requires a dedicated SEN line to enable the appropriate device The SDO pin is normally driven by the HMC900LPS5E during and after an SPI read write which is addressed directly to the HMC900LP5E chip address 5d 101 b A write to the HMC900LP5E where chip address is set to any value other than 5d or 101 b is required in order to ensure that the SDO pin remains tri stated after accessing the HMC900LP5E Such a write will not result in any change the HMC900LP5E configuration because of the incorrect chip address SEN from Master SCK from Master SDI from Master SDO from Master Figure 23 SPI Timing Diagram Table 11 Main SPI Timing
28. esult 16 crc RC BIST busy flag 1 0 RC BIST busy flag Indicates that BIST cycle is not completed and data crc BIST 15 0 is invalid 23 17 unused Table 28 Reg 10h to Reg1A Window Threshold OTP strobe register is used in programming of OTP Bit Name Width Default Description 23 0 reserved reserved z 0 A lt 2 77 a 2 lt co lt c LL For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com
29. gh If this is not desired then it is suggested to write to Reg Oh during the READ operation as the status of the device will be unaffected Power on Reset and Soft Reset The HMC900LP5E has built in Power On Reset POR and also a serial port accessible Soft Reset SR POR is accomplished when power is cycled for the HMC900LPSE while SR is accomplished via the SPI by writing 20h to Reg Oh followed by writing 00h to Reg Oh All chip registers will be reset to default states approximately 250us after power up Serial Port WRITE Operation The host changes the data on the falling edge of SCK and the HMC900LPBSE reads the data on the rising edge A typical WRITE cycle is shown in Figure 23 It is 32 clock cycles long 1 The host both asserts SEN active low Serial Port Enable and places the MSB of the data on SDI followed by a rising edge on SCLK For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com eeriitite HmcoooLPsE MICROWAVE CORPORATION y04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY 2 HMC9OOLP5E reads SDI the MSB on the 1st rising edge of SCK after SEN 3 HMC900LP5E registers the data bits D23 DO in the next 23 rising edges of total of 24 data bits 4 Host places the 5 register address bits A4 A0 on the next 5 falling edges
30. ittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com E Hittite MICROWAVE CORPORATION vo4 0811 RoHS v EARTH FRIENDLY Figure 1 Filter Attenuation all Bandwidths 0 20 40 Bypass 3 5MHz 60 FILTER GAIN dB 80 FREQUENCY MHz Figure 3 Filter Passband Gain Response 0 3 0 2 0 1 0 0 1 oaL FILTER GAIN dB 0 3 0 4 0 5 E 1 10 100 FREQUENCY MHz Figure 5 Filter 3 dB Cutoff vs Temperature 10 MHz Bandwidth 5 FILTER GAIN dB 5 6 7 8 9 10 FREQUENCY MHz 1 Measured with 100 source impedance HMC900LP5E 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Figure 2 Filter Noise Figure vs Bandwidth 11 NOISE FIGURE dB FILTER BANDWIDTH MHz Figure 4 Filter Output Noise OUTPUT NOISE nV rtHz 0 001 0 01 0 1 1 10 100 FREQUENCY MHz Figure 6 Filter Side Band Rejection vs Bandwidth SIDEBAND REJECTION dBc 3 5 5 7 10 14 20 28 35 50 FILTER BANDWIDTH MHz For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Z xX A lt A e Z lt lt o LL BBHi
31. ity Output IP3 30 dBm Pre programmed and or Programmable Bandwidth 3 5 MHz to 50 MHz Please see HMC900LP5E Ordering Information Integrated ADC Driver Amplifier Exceptional 3 dB Bandwidth Accuracy 2 5 6th order Butterworth Magnitude amp Phase Response Automatic Filter Calibration Externally Controlled Common Mode Output Level Simplifies Interface Filter Bypass Option 100 MHz Bandwidth Read Write Serial Port Interface SPI 32 Lead 5x5 mm SMT Package 25 mm General Description The 9 5 is a 6th order programmable bandwidth fully calibrated dual low pass filter It features O or 10 dB input gain setting and supports arbitrary bandwidths from 3 5 MHz to 50 MHz and when calibrated is accurate to 2 5 of the desired bandwidth It includes a 100 MHz bandwidth filter bypass option while retaining gain setting and common mode control Housed in a compact 5x5 mm SMT QFN package the 9 requires minimal exter nal components and provides a low cost alternative to more complicated switched discrete filter architectures The integrated ADC driver and externally controlled common mode output level further simplify system implementations Filter calibration for the HMC900LP5E is accomp lished with any reference clock rate from 20 to 80 MHz One time programmable OTP memory offers unsurpassed flexibility allowing the user set and forget parameters like gain and bandwidth setting
32. n code for the device under test See RC Calibration Circuit Once complete the actual calibration measurement must be read from the SPI See Reg 09h 2 Calculate the desired coarse bandwidth and fine bandwidth codes a From the calibration result we define a coarse tune factor ctune as ctune Cal count 10370000 b Normalize the desired frequency norm coarse fwanted ctune c Lookup the coarse tune code based on few norm_coarse from Table 9 Table 9 Normalized Bandwidth Look up Table nw nom coarse coarse bandwidth code 3 0 min typ max MHz MHz MHz 0000 2 764 3 500 4 235 0001 3 948 5 000 6 050 0010 5 527 7 000 8 470 0011 7 896 10 000 12 100 0100 11 055 14 000 16 940 0101 15 792 20 000 24 200 0110 22 109 28 000 33 880 0111 27 637 35 000 42 351 1000 39 480 50 000 60 500 d Calculate the fine tuning factor fine_tune_ratio for bandwidth based on the typical value of the coarse bandwidth center frequency fsw nor coarse typ fine tune ratio few_norm_coarse few_norm_coarse_typ e Lookup the fine tune code based on fine_tune_ratio from Table 10 For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Z xX A lt A e Z lt lt o LL
33. ndwidth curacy at Default Bandwidth 0 after POR Variable Bandwidth Filter Yes Yes Full GORGE over HMOSUOEPSE requires access via the digital serial port SPI Default Bandwidth and Gain Dalaul Bandwidth Bandwidth ang Pre programmed gain and bandwidth and Gain as defined Gain as defined by 3 setting after Power On Reset by register defaults re prearammind at are defined when ordering the part See pd POR y reg ee 9 5 Ordering Information 3 5 MHz OdB gain factory 70 Typical Corner Frequency Ac h 20 4259 Yes No Accuracy is with respect to bandwidth dp curacy at Default Bandwidth after POR Accuracy is with respect to the desired Typical Corner Frequency bandwidth Accuracy at all other Band 20 5 0 See Filter Bandwidth Setting for informa Q widths tion regarding changing the bandwidth C after when calibration is not possible z Full control over HMC900LP5E requires A Variable Bandwidth Filter E Ku access via the digital serial port SPI aem with ability to execute User i MAU 4 Yes Yes Filter calibration requires valid calibration Calibration to calibrate filter f lt bandwidth clock via CALCK pin See RC Calibra tion Circuit z Default Bandwidth and Gain Bandwiath pandwioth and Pre programmed gain and bandwidth and Gain as defined Gain as defined by setting after Power
34. of SCLK MSB to LSB while the HMCS900LP5E reads the address bits on the corresponding rising edge of SCK 5 Host places the chip address bits CA2 CAO0 101 on the next falling edges of SCK MSB to LSB Note the HMC900LPSE chip address is fixed as 5d or 101b 6 SEN goes from low to high after the 32th rising edge of SCK This completes the WRITE cycle 7 HMC900LPBSE also exports data back on the SDO line For details see the section on READ operation Serial Port READ Operation The SPI can read from the internal registers in the chip The data is available on SDO line This line itself is tri stated when the device is not being addressed However when the device is active and has been addressed by the SPI master the HMC900LP5E controls the SDO line and exports data on this line during the next SPI cycle HMCS900LP5E changes the data to the host on the rising edge of SCLK and the host reads the data from HMC900LP5E on the falling edge A typical READ cycle is shown in Figure 23 Read cycle is 32 clock cycles long To specifically read a register the address of that register must be written to dedicated Reg Oh This requires two full cycles one to write the required address and a 2nd to retrieve the data A read cycle can then be initiated as follows 1 The host asserts SEN active low Serial Port Enable followed by a rising edge SCLK 2 HMC900LPSE reads SDI the MSB on the 1 rising edge of SCK after SEN 3 HMC
35. on 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com z CD U A lt 2 2 lt co TT N lt c z QD A um lt 2 a 2 lt co TT N lt c LL nwcoonesE MICROWAVE CORPORATION y04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 1 Electrical Specifications TA 25 C Continued Parameter Conditions Min Typ Max Units half scale tones at 1 2fc and 2 Output 1 2 out of band 1 6fc IM2 product at 0 4fc 60 65 dBm complex signal measured at Sideband Suppression Uncalibrated 0 8fc vs 0 8fc 40 45 dB Channel Balance magnitude 0 04 dB phase 0 5 o Channel Isolation 60 80 dB Analog I O Differential Input Impedance 1000 Q Full Scale Differential Input min gain 2 Vppd 400 Q Differential Load max gain 0 613 Vppd Full Scale Differential Input min gain 0 5 Vppd 100 Q Differential Load max gain 0 156 Vppd Input Common Mode Voltage Range 1 4 V Full Scale Differential Output 400 O Differential Load 2 Vppd Full Scale Differential Output 100 Differential Load 0 5 Vppd Output Voltage Range 0 5 Vdd 0 5 V Output Common Mode Voltage Range Vdd 2 1 Vdd 2 Vdd 2 1 V Digital I O CALCK Frequency E naan ae 20 40 80 MHz CALCK
36. onnected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request Table 6 Evaluation Order Information Item Contents Part Number Evaluation PCB Only HMC900LP5E Evaluation PCB 131200 HMC900LP5E HMCS900LP5E Evaluation PCB A USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable 130521 HMC900LP5E CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software Z A lt A m Z lt t o For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com MICROWAVE CORPORATION o4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Evaluation PCB Schematic To view Evaluation PCB Schematic please visit www hittite com and choose HMC9OOLP5E from the Search by Part Number pull down menu to view the product splash page Evaluation Setup Agilent E3630A Power Supply S 5 Agilent 2 S Agilent BBQ HMC900LPSE BB Eval Board S Interface Board PC Control Figure 18 Characterization Setup Block Diagram z QD
37. or price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com nwcoonesE MICROWAVE CORPORATION yo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Table 3 Absolute Maximum Ratings Nominal 5V Supply to GND Reflow Soldering VDDCAL VDDI VDDQ VDDBG 0 3 to 5 5V Peak Temperature 260 C DVDD Time at Peak Temperature 40 us Common Mode Inputs Pins _ ESD Sensitivity HBM 1kV Class 1C CMI CMQ 0 3 to 5 5V Input and Output Pins Stresses above those listed under Absolute Maximum Ratings may IIP IIN IQP ION OIP OIN 0 3 to 5 5V cause permanent damage to the device This is a stress rating only OQN functional operation of the device at these or any other conditions Digital Pins above those indicated in the operational section of this specification SEN SDI SCK SDO CALCK 0 3 to 5 5V is not implied Exposure to absolute maximum rating conditions for SDO min load impedance 1kO extended periods may affect device reliability Operating Temperature Range 40 to 85 C Sia eee Beane ee ELECTROSTATIC SENSITIVE DEVICE Maximum Junction Temperature 125 C A OBSERVE HANDLING PRECAUTIONS Thermal Resistance junction to groun
38. overage will improve if the following SPI registers are also accessed a program the RC clock period Reg 05h b program the measurement adjustment setting Reg 06h c program the threshold adjustment settings 3 enable BIST mode Reg OEh 4 start the BIST by writing any data to the BIST strobe register Reg 04h Note that the BIST will take 2 8 260k clock cycles to complete 5 read the result of the BIST test Read the value in the BIST Out register Reg OF Bit 16 is the busy flag and will be set when the BIST is still running When this bit is reset then the BIST output value in bits 15 0 are valid Note that the value of the BIST output must be compared to the expected result depending on values programmed into the registers in step 2 The BIST procedure can be repeated as desired to ensure adequate test coverage for the RC Calibration engine The suggested register settings to maximize test coverage with BIST is provided below Table 12 Test Conditions Register Settings Expected Result Reg 05h 14 0 65 Reg 06h 8 0 255 Reg10h 4 0 to egtAh 4 0 0d or Oh Reg OFh 15 0 36092 Reg 09h 23 0 14942167 Reg 05h 14 0 232702 Reg 06h 8 0 36 Reg10h 4 0 to Reg1Ah 4 0 231d or 1Fh Reg OFh 15 0 55027 Reg 09h 23 0 14143649 Reg 05h 14 0 10922 Reg O6h 8 0 170 Reg10h 4 0 to Reg1Ah 4 0 10d or Ah Reg OFh 15 0 28618 Reg 09h 23 0 8907563 Reg 05h 14 0 221845 RegO6h 8 0 853 Reg10h 4 0 to Reg1Ah 4 0 21d or 15h Reg oFg 15 0 16368
39. ttite MICROWAVE CORPORATION vo4 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY Figure 7 In band OIP3 1 amp OIP2 nvs Figure 8 In band OIP3 and OIP2 11 vs Temperature 0 dB Gain standard bias Temperature 0 dB Gain high linearity 45 i 75 45 T T T 75 1 2 Hoseok oeoo oee Ajeet 70 g 2 g E 60 5 60 3 5 3 E 5 55 3 55 3 s 2 1 e 85 45 45 3 5 5 7 10 14 20 28 35 50 3 5 5 7 10 14 20 28 35 50 FILTER BANDWIDTH MHz FILTER BANDWIDTH MHz Figure 9 In band OIP3 OIP2 1 vs Figure 10 In band land OIP2 vs 5 Bandwidth standard bias Bandwidth high linearity 2 OUTPUT IP2 _y OUTPUT 2 gt gt i E ian QD MS E 8 qi q E q E 3 E E E 3 E 3 oc i am lt 85 5 7 10 14 20 28 35 50 85 5 14 20 28 35 50 Z FILTER BANDWIDTH MHz FILTER BANDWIDTH MHz Figure 11 Out of band Figure 12 Out of band and Q OIP2 vs Bandwidth standard bias OIP2 vs Bandwidth high linearity Pd 50 2 i 55 85 lt 45 iaa 40 Li e i e qu ge lt gt 30 2 ki o 8 E 8 3 25 2 3 LL 20 15 0 0 1 0 0 3 5 5 7 10 14 20 28 35 50 3 5 5 7 10 14 20 28 35 50 FILTER BANDWIDTH MHz
40. ure 20 Typical Transmit Path Block Diagram For price delivery and to place orders please contact Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com EJHHEUIC nwcoooresE MICROWAVE CORPORATION 04 0811 RoHS 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER EARTH FRIENDLY HMC900LP5E Ordering Information The HMC900LP5E is available as product that is either un programmed or pre programmed Programming is available to a variety of filter bandwidths defined in this context as the 3dB bandwidth Other options available for pre programmed product include the single path gain and bias state as described below Gain and bias settings are described in Reg 02h When placing an order for the HMC900LPB5SE please observe the following guidelines 1 Toorder the un programmed standard part please place order using the part number HMC900LP5E 00000 2 To order a pre programmed HMC9OOLP5E please determine the part number as described below and then contact Hittite Sales at sales hittite com or call 978 250 3343 2 1 Minimum quantity order for the pre programmed HMC900LP5E BBBGL is 500 pieces 3 Pre Programmed part number description HMC900LP5E BBBGL 34 BBB represents a three digit number from the following table that represents the desired bandwidth setting 3 dB bandwidth from 3 5 MHz to 50 MHz for example BBB 035 specifies
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