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User Manual DNPCIe_10G_K7_LL (_QSFP)

1. E Mail You may direct questions and feedback to Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page may contain a document called DNPCIe_10G_K7_LL _QSFP Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 7 GETTING STARTED Getting Started Congratulations on your purchase of the DINPCIe_10G_K7_LL _OSFP Ethernet Packet Analysis Engine The remainder of this chapter describes how to start using the DNPClIe_10G_K7_LL _OSFP Ethernet Packet Analysis Engine 1 Before You Begin 1 1 Configuring the Programmable Components The DNPCIe 10G K7 LL _QSFP has been factory tested and pre programmed to ensure correct operation The user does not need to alter any jumpers or program anything to see the board work 1 2 Warnings e Mechanical Stress Inserting and removing VLP MINIUDIMM and the board from the motherboard can add additional stress that may cause board failures e ESD Warning The board is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the
2. HARDWARE DESCRIPTION e The RESET and CKE signals are not terminated These signals should be pulled down during memory initialization with a 4 7 kQ resistor connected to GND e ODT which terminates a signal at the memory and DCI which terminates a signal at the FPGA are required The MIG tool should be used to specify the configuration of the memory system for setting the mode register properly Refer to Micron technical note TN 47 01 for additional details on ODT e ODT applies to the DQ DQS and DM signals only If ODT is used the mode register must be set appropriately to enable ODT at the memory 2 4 3 Design Guidelines DDR3 IO Standards These rules apply to the I O standard selection for DDR3 SDRAMs e Designs generated by the MIG tool use the SSTL15_T_DCI and DIFF SSTL15 T DCI standards for all bidirectional I O DQ DQS e The SSTL15 and DIFF_SSTL15 standards are used for unidirectional outputs such as control address and forward memory clocks The MIG tool creates the UCF using the appropriate standard based on input from the GUI 2 4 4 Serial Presence Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence detect The SPD data is stored in a 256 byte EEPROM The first 128 bytes are programmed by Micron to comply with JEDEC Standard JC 45 Appendix X Serial Presence Detect SPD for DDR3 SDRAM Modules These bytes identify module specific timing parameters configuration information and p
3. 12V LED DS16 is ON indicating the presence of 12V located on the back side of the board near the top left 4 3 Configuring the FPGA To configure the Xilinx FPGA perform the following steps Note Non Xilinx devices in the JTAG chain will report IR Length errors 1 Open ChipScope Pro gt Analyzer and identify the devices in the JTAG chain ET ChipScope Pro Analyzer new proj Sry Eile View JTAG Chain D Window Help New Project H JTAG Chain ChipScope Pro Analyzer z JTAG Chain Device Order Index Name Device Name IR Length Device IDCODE USERCODE O MyDeviced IXC7K410T 6 13656093 1 MyDevice1 XC2C64A Ja 0665093 2 MyDevice2 a 12454069 1 oK Cancel Read USERCODEs RY NA ChipScope Pro INFO ChipScope Pro Analyzer Version 14 2 P 28xd Build 14200 12 202 1250 COMMAND open cable INFO Started ChipScope host localhost50001 INFO Successfully opened connection to server localhost 50004 localhost 127 0 0 1 INFO Successfully opened Digilent USB JTAG Cable INFO Cable DNPCle_10G_K7_LL Port 0 Speed 10000000 Hz Note In order for the JTAG offsets to be set correctly set the IR Length for the QDR SRAMSs to 3 2 Proceed as normal see UG029 ChipsCope Pro Software and Cores User Guide DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 20 HARDWARE DESCRIPTION Ci Hardware Description This chapter desribes the harcore f
4. 2 3 QDR Il SRAM Memory The CY7C25632KV18 500BZC is a 1 8 V synchronous pipelined SRAM equipped with QDR H architecture Similar to QDR II architecture QDR I architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that exists with common I O devices Each port is accessed through a common address bus Addresses for read and write addresses are latched on alternate rising edges of the input K clock Accesses to the QDR H read and write ports are completely independent of one another To maximize data throughput both read and write ports are equipped with DDR interfaces Each address location is associated with four 18 bit words that burst sequentially into or out of the device Because data is DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 25 HARDWARE DESCRIPTION transferred into and out of the device on every rising edge of both input clocks K and Kn memory bandwidth is maximized while simplifying system design by eliminating bus turn arounds These devices have an on die termination feature supported for D x 0 BWS x 0 and K K inputs which helps eliminate external termination resistors reduce cost
5. Before powering up the board prepare the board as follows 1 If the kit contains a Memory VLP MINIUDIMM module populate the VLP MINIUDIMM socket J7 DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 9 GETTING STARTED 2 Plug board into x4 x8 or x16 PCIE slot 3 Connect the USB 2 0 Cable to the USB B connector on the bracket Note The DNPCIe 10G K7 LL QSFP Ethernet Packet Analysis Engine is shipped with a passive heat sink for operation in a server or PC with forced cooling If the board is used in standalone mode please provide an external fan to prevent the FPGA from overheating 3 2 Powering Up the Board 1 Power up the board by turning ON the power to the motherboard verify the 12V LED DS16 is ON indicating the presence of 12V located on the back side of the board near the top left 2 USB drivers should automatically install when the board turns on If this doesn t happen then install the USB driver from the FIDI website for driver installation please refer to http www ftdichip com Support Documents InstallGuides htm 3 Once drivers are finished installing open a Terminal Emulator and configure the session as follows Baud rate Data Parity Stop Flow control Transmit delay 0 msecjchar msecjline DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 10 GETTING STARTED 4 Using the Reference Design Main This section lists detailed in
6. and thus requires a single slot DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 49 HARDWARE DESCRIPTION The mounting holes are connected to the ground plane and can be used to ground test equipment DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 50 APPENDIX Appendix 7 Appendix A UCF File See the Customer Support Package USB Flash Drive for the Xilinx User Constraint Files UCF 8 Ordering Information Request quotes by emailing sales dinigroup com For technical questions email support dinigroup com DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 51
7. can be bypassed There are no interrupts No operating system Not a single clock cycle is wasted here enabling a near theoretical minimum in to out response time For algorithms requiring processing FPGA resources can be hard coded to perform the task This includes real time Monte Carlo analysis and floating point all operating 1000 s of times faster than possible in a processor based approach DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 3 INTRODUCTION 2 DNPCle_10G K7 LL _QSFP Ethernet Packet Analysis Engine Features Eora Figure 1 DNPCIe_10G_K7_LL QSFP Ethernet Packet Analysis Engine upper picture is the DNPCIe_10G_K7_LL and lower picture is the DNPCIe_10G_K7_LL_QSFP DNPCIe_10G_K7_LL _QSFP Kintex 7 Board features the following e Hosted in a 4 lane 16 lane mechanical with notches to allow to be plugged into x4 x8 x16 PCI Express Slot GEN2 or Stand alone e Xilinx Kintex 7 FPGA FFG676 o XC7K325T 3 2 1 fastest to slowest o XC7K410T 3 2 1 fastest to slowest e GTX Transceivers 10Gb s o PCI Express x4 o Two SFP modules x1 each o QSFP module x4 only with _QSFP version DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 4 INTRODUCTION e Flexible Clock Resources o PCI Express Clock Jitter Attenuator 250MHz o Oscillators for GTX Transceivers e Memory o Bulk Memory DDR3 VLP MINIUDIMM 244 pin 72 bit data width 64 bit with 8 bit ECC PC3 1
8. reduce board area and simplify board routing 2 3 1 QDRII SRAM Memory Architecture One QDR I SRAM memory U4 is connected in a 4M x18 memory architecture see Figure 5 The Memory Interface Generator MIG is a self explanatory wizard tool that can be invoked under the CORE Generator software Xilinx published a memory application note please refer to UG 586 7 Series FPGAs Memory Interface Solutions User Guide control FPGA Xilinx Kintex 7 7K325T 7K410T FFG 676 Figure 5 QDR I Memory Architecture The memory is also mapped into the JTAG chain and is fully compliant with IEEE Standard 1149 1 2001 2 3 2 Design Guidelines QDR II SRAM IO Standards The MIG tool generates the appropriate UCF file for the core with select I O standards based on the type of input or output to the Kintex 7 FPGA These standards should not be changed Table 4 contains a list of the ports together with the I O standard used Table 4 QDR II SRAM IO Standards Signal Name Direction IO Standard qdriip_bw_n OUTPUT HSTL_I qdriip_cq_p qdriip cq n INPUT HSTL I qdriip_d OUTPUT HSTL I qdriip_k_p qdriip_k_n OUTPUT DIFF_HSTL_I qdriip_q INPUT HSTL I DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 26 HARDWARE DESCRIPTIO Direction IO Standard OUTPUT HSTL I OUTPUT HSTL I OUTPUT HSTL I 2 3 3 Connections between FPGA and QDR II SRAM Devices 4M x 18 Table 5
9. 0 4uF 16V tev 16V 10V 16V tev _ 10 10 _ 10 10 10 10 SFPO_VCCT_DAMP R339 0 25R SFPO VCCR DAMP R367 0 25R 25V 3 3V REG Note Place the 0 1uF decoupling Kg Note Place the 0 1uF decoupling ae capacitors between pins 16617 of capacitors between pins 16617 of the SFP connector the SFP connector Silkscreen SFPO Dst LED SFPO_TXFAUCT 13mA _LED_SFFO_TXFAULTa LED RED LED SFPO_RX LOS AR ama LED GREEN SFP Connector MGT116 Green host good module good Red host bad module bad al Orange host good module ne Mo light host bad module R388 bad p 2 SFPO_TXFAULT amp 22 SFPOLTXDISABLE p2 SFPO_MOD_ABS p2 SFPO_RSO p2 SFPOLRX LOS 43 3V SFPO VOGT 3 3V SFPO VCCR p2 SFPOLRST x z uz 5 Note Add SPP Cage St vce CAGE Kis P N 2007199 1 LED SFFO RX LOSS 4 on 2 a CAGE PID 2644 Lor Hono ne Hx the 16v 10 INT4LVC1GOTDEVR SOT 22 5 3x3 Sane we a rope Silkscreen SFPO Figure 7 SFP Channel 0 Interface Fixed frequency 156 25 MHz LVPECL oscillator X5 is used to clock the GTX transceivers see Figure 8 These parts are available from Silicon Laboratories P N 534SC000390DG The oscillator power supply is filtered to reduce power supply noise and jitter Ta 8 156 25MHz for SFP 1Gb 10Gb 98mA MAX x5 CLK SFP Fsi lt CLK_SFP_REFCLKp p 13 GA Sr Fs
10. 1 0 b Pin Address Bits Lx 6 Right Click on the FLASH icon and select Program Uncheck the Verify checkbox followed by OK A Process Dialog box will indicate programming progress Note This process takes minutes to complete Device Programming Propenies Device 1 Programming Propet M Category B Boundary Scan Device 1 FPGA xc7k410t Property Name Device 1 Attached FLASH 28F00 Verify Device 2 CPLD2 xc2c64a Device 3 Unknown Type GENERAT Design Specific Erase Before Programming V After programming Flash automatically load FPGA with l Configuration Bank Voltage Based on CFGBVS pin m r Cox ca sv J _te 7 Verify that iMPACT successfully programmed the BPI Flash DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 18 PROGRAMMING CONFIGURING THE HARDWARE B File Edit View Operations Output Debug Window Help e DAR BBa ST FR IMPACT Flows D amp X Right click device to select operations E 9 Boundary Scan 2 Systemace pir E create PROM File PROM File Formatter f E WebTalk Data m xc7k410t xc2c84a unknown_2_3 fpga_a bt bypass unknown_2_3 bsd T00 IMPACT Processes 08x amp Boundary Scan Console 08x Using x16 mode Set Data Width J INFO Cse Using Buffered Programming 71 Programming Flash done 71 Flash
11. CLK_SFP_REFCLKn p 13 1 CLK SFP NC R13 pn 2 5V_OSC CLK SFP OEn 400MA DNI 00 mOhm Max DC 1K Ohm 100MHz S S 0 0984 VDD min 2 35408 PID 2768 2 5V FS 1 0 00 100 MHz FS 1 0 01 125 MHz FS 1 0 10 150 MHz FS 1 0 11 156 25MHz Figure 8 SFP GTX Oscillator 2 7 2 LED indicators SFPO and SFP1 have separate LED indicators that indicate the state to the light pipes that display on the bracket On the bracket 0 indicated SFPO and 1 indicates SFP1 The color of the lights indicates the following Green host good module good Red host bad module bad Orange host good module bad No light host bad module good DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 40 HARDWARE DESCRIPTION 2 7 3 SFP Pin Assignments The SFP pin assignments are listed in Table 11 Table 11 SFP Pin Assignments Symbol Description VeeT Transmitter Ground TX Fault Transmitter Fault Indication TX Disable Transmitter Disable SDA 2 wire Serial Interface Data Line Same as MOD DEF2 in INF 80741 SCL 2 wire Serial Interface Clock Game as MOD DEF1 in INF 80741 Mod ABS Module Absent connected to VeeT or VeeR in the module RSO Rate Select 0 optionally controls SFP module receiver Rx LOS 3rd Receiver Loss of Signal Indication In FC designated as Rx_LOS and in Ethernet designated as Signal Detect Rate Select 1 opt
12. E11 U4 E3 U4 F2 U4 G3 U4 P6 U4 A8 U4 A4 4 B8 4 C5 U4 C7 U U U U www dinigroup com 28 HARDWARE DESCRIPTION Signal Name QDRIIP_SA7 QDRIIP_SA8 QDRIIP_SA9 QDRIIP_SA10 QDRIIP_SA11 QDRIIP_SA12 QDRIIP_SA13 QDRIIP_SA14 QDRIIP_SA15 QDRIIP_SA16 QDRIIP_SA17 QDRIIP_SA18 QDRIIP_SA19 CICI CICI SISIS gt N QIQ gt w Re CG D gt ssl N N QDRUP SA2 U 2 4 DDR3 Memory VLP MINIUDIMM With a 244 pin VLP MINIUDIMM module connected to the Kintex 7 FPGA the following transfer speeds can be expected e Speed Grade 3 1866Mb s e Speed Grade 2 1866Mb s e Speed Grade 1 1600Mb s The VLP MINIUDIMM interface is connected to IO Banks on the Kintex 7 FPGAs and uses a 1 5V switching power supply for Vpp and Veco Verr and Var ate powered from a separate linear power supply set at 0 75V DDR3 SDRAM modules are available from Micron example part number for a 2GB 256Mbx72 244 pin VLP MINIUDIMM SDRAM module is MT9JBG25672AKZ 1G4 2 4 1 DDR3 SDRAM Memory Interface Solution The Kintex 7 FPGA memory interface solutions core is a pre engineered controller and physical layer PHY for interfacing Kintex 7 FPGA user designs to DDR3 SDRAM devices The Memory Interface Generator MIG is a self explanatory wizard tool that can be invoked under the CORE Generator software Xilinx published a memory application note please refer to UG 586 7 Series FPGAs Memory Interface Solu
13. Fundamentals of ESD for those of you who are new to ESD sensitive products http en wikipedia org wiki Electrostatic_discharge 2 Installing the Software No Software installation required DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 8 GETTING STARTED 2 1 Exploring the Customer Support Package The USB Flash Drive contains the following items see Figure 2 l Documentation FPGA Reference Designs Host Software Figure 2 USB Flash Drive Directory Structure A description of the USB Flash Drive directory contents is listed in Table 1 Please visit the Dini Group website for the most recent revision of these documents Table 1 USB Flash Drive Directory Contents USB Flash Drive Directory Contents Directory Name Description of Contents Documentation Contains the Datasheets Schematics and User Manual for the board FPGA Reference Designs Contains the source and compiled programming files for the DNPClIe_10G_K7_LL _QSFP reference designs Host Software Provides the Host Software for the Windows and Linux platforms 3 Board Setup The instructions in this section explain how to install the DNPCle_10G_K7_LL _QSFP Ethernet Packet Analysis Engine For the purpose of this demonstration the DNPCIe 10G K7 LL _QSFP will be configured using a motherboard s PCIE connectors for power and the USB interface 3 1 Before Powering Up the Board
14. Inverted Data Output CML O 1 2 3 4 5 6 7 8 9 m oO f a me DD F Q F K DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 44 HARDWARE DESCRIPTION Symbol Description Logic Family Rx3n Receiver Inverted Data Output CML O GND Ground Rxlp Receiver Non Inverted Data Output CML O Rxln Receiver Inverted Data Output CML O GND Ground GND Ground Rx2n Receiver Inverted Data Output Rx2p Receiver Non Inverted Data Output GND Ground Rx4n Receiver Inverted Data Output Rx4p Receiver Non Inverted Data Output GND Ground ModPrsL Module Present IntL Interrupt Vcc Tx 3 3V Power supply transmitter Vccl 3 3V Power supply LPMode Low Power Mode GND Ground Tx3p Transmitter Non Inverted Data Input Tx3n Transmitter Inverted Data Input GND Ground Txip Transmitter Non Inverted Data Input Txin Transmitter Inverted Data Input GND Ground 2 8 4 Connections between FPGA and the QSFP Connectors Table 14 lists the connections between the FPGA and the QSFP connectors Signal Name Table 14 Connections between FPGA and the QSFP Connectors QSFP Connector QSFP QSFP_RX1p pia QSFP_RX1n DNPCle_10G_K7_LL _QSFP User Manual J11 18
15. NER TE AS DERES SEES quote odavaovaacesradeatestausunessiteuseredvoutesesteudapesauneseate 8 1 1 Configuring the Programmable Component scccccccceeeseeseesesseesceeseeseeseeseesecsccuseeseeseesecsecseeseeseesecsecsecseesseeseesecsecseceaseaeeseeaeeaecseceeeeaeeaeeaeeaeeaeenes 8 1 2 WAIN Rae oe EDER REE TEER CERT RM CER TERE E REDIESS NERE 8 2 INSTALLING THE SOFTWARE 8 21 Exploring the Customer Support Package 9 3 BOARD SETUP 00 9 3 1 Before ROW Erin SUP MBO soci sxe covisscssencusesesniucsss EAE EN AASE EEAS ENS REEERE CASES ESEA OANSET AS E EESE AE 9 3 2 Powering Up the Board 10 4 USING THE REFERENCE DESIGN MAIN c sscccssssscccsnssccenesyacedaxesncesuntoscedevecedsenstanchsusasestcouescseduvedosedubeeceudevecedensvvacesaeseacsvuesvacesatevdedssdavedcse 11 PROGRAMMING CONFIGURING THE HARDWARE cccccssssssssssssssssssscssssssssssssssssesssssesssssssesssessesssseassssessassesessesesscssssessssossasessessessseessssassesonees 13 1 INTRODUCTION israelere es vente GSE GV re cease GAUL A ouald MAR AS Een ea TAY 13 CONFIGURING THE FPGA USING JTAG 2 1 Setup Configuring the FPGA using JTAG 2 2 Powering Up the Board 14 2 3 Configuring the FPGA 14 3 CONFIGURING THE FPGA USING MASTER BPI 16 3 1 Setup Configuring the FPGA using Master BPI 517 3 2 Powering Up the Board ss TZ 33 Configuring the FPGA 17 4 USING CHIPSCOPE PRO VIA JTAG 19 4 1 Setup Using Chip
16. Power up the board by turning ON the ATX power supply to the motherboard and verify the 12V LED DS16 is ON indicating the presence of 12V located on the back side of the board near the top left 3 3 Configuring the FPGA To configure the Xilinx FPGA perform the following steps 1 Open iMPACT and create a new default project Select Configure devices using Boundary Scan JTAG from the iMPACT welcome menu Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain YW Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Cancel 2 iMPACT will identify the components in the JTAG chain A pop up window will display ERROR iMPACT Bsdl reader is not available for device 3 Click OK to proceed Reason QDR2 devices are also in the JTAG chain 3 A pop up window will display Device Programming Properties Device 1 Programming Properties Click OK to select default options DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 17 PROGRAMMING CONFIGURING THE HARDWARE 4 Right click on FPGA and select Add BPI SPI Flash Specify the location for the PROM file based on the type of FPGA populated e g XC7K325T 5 Select the 28F00AG18F device in the Select Attached SPI BPY window BPI PROM Data Width Select RS
17. Programming completed successfully PROGRESS END End Operation Elapsed time 783 sec Match _cycl LCK_cyc LCK cycle 4 INFO iMPACT ecking done pin done 1 Programmed successfully El console rors Warnings 8 Power cycle the board and verify that the FPGA_DONE blue LED DS15 is enabled indicating successful configuration of the FPGA from BPI PROM 4 Using ChipScope Pro via JTAG The Xilinx ChipScope Pro tool inserts logic analyzer system analyzer and virtual I O low profile software cores directly into the design allowing the user to view any internal signal or node including embedded hard or soft processors Signals are captured in the system at the speed of operation and brought out through the programming interface freeing up pins for your design Captured signals are then displayed and analyzed using the ChipScope Pro Analyzer tool Note This User Manual will not be updated for every revision of the Xilinx ISE tools so please be aware of minor differences 4 1 Setup Using ChipScope Pro via JTAG Before configuring the FPGA ensure the following steps have been completed 1 Connect the USB 2 0 Cable to the bracket mounted USB 2 0 B connector DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 19 PROGRAMMING CONFIGURING THE HARDWARE 4 2 Powering Up the Board 1 Power up the board by turning ON the ATX power supply to the motherboard and verify the
18. can be optimized in any way you choose Dini Group provides several Verilog examples All functions of the QDR I SSRAM can be exploited including concurrent read and write operations and four tick bursts The only real limitation is the amount of time and effort spent in customizing the individual memory controllers 1 5 DDR3 DRAM Bulk Memory A single 244 pin PC3 10600 DDR3 VLP MINIUDIMM socket enables up to 4GB of memory for bulk storage and lookup Using a 2 or 3 speed grade FPGA this interface is tested at the maximum FPGA I O frequency 666 5Hz 1333Mb s with DDR The user can use this memory as 64 bits with 8 bits of error correction ECC or as a 72 bit byte memory without correction To minimize data synchronization across clock boundaries it probably makes sense to clock the DDR3 interface at a 3x multiple of the base Ethernet frequency of 156 25 MHz which is 468 75MHz A 3x phase synchronous clock can be easily generated internal to the FPGA allowing zero latency synchronous data transfers between the Ethernet packet receiving logic and the DDR3 memory controller The DDR3 controller can be optimized in any way you choose We of course provide several Verilog examples All functions of the DDR3 DRAM can be exploited and optimized Timing variables such as CAS latency and precharge can be tailored to the minimum given your operating frequency and the timing specification of the exact DDR3 memory DNPCle_10G_K7_LL _QSFP User M
19. gt gt ai Q RR gt O 00 T gt DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 32 HARDWARE DESCRIPTION cic CIG SIN ae co V M5 M6 M7 M8 CIC T gt a pare DD C CIG pE G DIDIDID KICGI lt SITALEIO DIK wW DIMM DI DIMM DI DIMM DI DIMM_D CIG a ec gt gt tH J N T gt z on DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 33 HARDWARE DESCRIPTION cic cic dild Pi gt gt AIO e N 00 eagle DID lt 4 JS C IC DID lt i lt Nn T zZ O DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 34 HARDWARE DESCRIPTION cic C C G GG DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 35 HARDWARE DESCRIPTION C GCIS CIS SS E Ee T Cc DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 36 HARDWARE DESCRIPTION 2 5 EEPROM The AT24C256C U26 provides 262 144 bits of serial electrically erasable and programmable read only memory EEPROM organized as 32 768 words of eight bits each The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential 2 5 1 EEPROM Circuit Diagram Figure 6 shows the implementation of the EEPROM memory circuit 1 8V Rem 2 261 EEPROM 256K U2
20. 0600 666 5MHz Addressing power to support 4GB ECC DDR3 Verilog VHDL reference design provided o QDRII SSRAM 1 channels 4M x 18 72Mb 500 MHz bus operation DDR double data rate Fast enough to be clocked at 312 50 MHz Eliminates clock synchronization delays between memory and Ethernet clock e User LED s e Time Synchronization o 2 5mm jack that accepts PPS and IRIG B000 RS232 RS485 RS422 TTL time code e Onboard Distributed Power Supplies e Full support for Embedded Logic Analyzers and Debug o ChipScope Logic Analyzer o InPA Veridae SpringSoft e USB B 2 0 Port o RS232 o JTAG e The FIX board support package DN FBSP for the DNPCIe 10G K7 LL _QSFP is a functioning reference design with the following components o 10 Gigabit Ethernet MAC o TCP IP Offload Engine TOE o FIX protocol parser DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 5 INTRODUCTION o PCIe Interface 4 lane GEN2 o Memory o QDRII Controller o DDR3 Controller 3 Package Contents Before using the kit or installing the software be sure to check the contents of the kit and inspect the board to verify that you received all of the items If any of these items are missing contact Dini Group before you proceed The DNPCIe_10G_K7_LL QSFP Ethernet Packet Analysis Engine includes the following e USB Flash Drive 4GB USB007 P N UFDCR 4096 e USB 2 0 Cable NewEgg P N N82E16812119030 e VLP MI
21. 3 U3 A5 DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 47 HARDWARE DESCRIPTION 3 Clock Generation 3 1 System Clock IDELAYCTRL Hither X3 or X2 can be used as the IDELAYCTRL system clock The IDELAYCTRL module must be instantiated when using the tap delay line The oscillator power supply is filtered to reduce power supply noise and jitter 3 1 1 Connection between FPGA and the System Clock Oscillator The connections between the FPGA and the System Clock Oscillator are shown in Table 15 These signals are routed as differential pairs LVDS Table 15 Connection between the FPGA and the System Clock Oscillator Signal Name Oscillator CLK_DIMM_SYSp X3 4 CLK_DIMM_SYSp X35 or CLK_QDRIIP_SYSp X2 4 CLK_QDRIIP_SYSn X25 3 2 High Speed GTX Clocks Refer to the relevant sub section of this User Manual for a detailed description of the clocking resoutces 4 LED Indicators The DNPCIe 10G K7 LL _QSFP Ethernet Packet Analysis Engine provides various LED s to indicate that status of the board 4 1 FPGA Status LEDs Numerous LEDs Green Yellow Red are provided to the user as a design aid during debugging The LEDs can be turned ON by driving the corresponding pin LOW Table 16 describes the Status LEDs and their associated pin assignments on the FPGA Table 16 FPGA Status LEDs DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 48 HARDWARE DESCR
22. 56 25MHz for QSFP 40Gb 98mA MAX x5 ork GSR ST Z ps1 NOLK H KeLK ASFP_REFCLKP p 11 Fso gt cLK S CLK QSFPIREFCLKN p 11 CLK _QSFP_OEn L 2l J wl CLK_QSFP_NC R13 DNI CLK QSFP OEn 2 5V_OSC 3 2 25 2 75 6 2 5V CLK QSFP VDD FB1 R7 R126 lt R141 GND VOD ton ci2 400mA 1 DNI DNI DNI 5345C000390DG 0 1uF 10uF 500 mOhm Max DC al i 8SMD 16V 6 3V 1K Ohm 100MHz PID 2768 10 20 i i e 00982 VDD min 2 35408 PID 2768 2 5V FS 2 0 00 100 Miz FS 1 0 01 125 MHz FS 1 0 10 150 Miz FS 1 SOF 11 156 25Miz Figure 10 QSFP GTX Oscillator 2 8 2 LED indicators There are two separate LEDs that connect to the light pipes that display on the bracket These LEDs are directly connected to the FPGA so the color of the lights can be used to indicate status of the QSFP interface 2 8 3 QSFP Pin Assignments The QSFP pin assignments are listed in Table 13 Table 13 QSFP Pin Assignments Pin Number Symbol Description Logic Family GND Ground Tx2n Transmitter Inverted Data Input CML I Tx2p Transmitter Non Inverted Data Input CML I GND Ground Tx4n Transmitter Inverted Data Input CML I Tx4p Transmitter Non Inverted Data Input CML I GND Ground ModSelL Module Select LVTIL I ResetL Module Reset LVTIL I Vcc Rx 3 3V Power Supply Receiver SCL 2 wire serial interface clock LVCMOS I O SDA 2 wire serial interface data LVCMOS I O GND Ground Rx3p Receiver Non
23. 6 EEPROM SCL 6 1 SCL AO EEPROM SDA ji Su fr 2 R251 1 PHY P2 PROM WP ae A2 747K 8 4 VCC GND eee ae 1 8V AT24C256C SSHL B 8 SOIC 5x6 2 C297 1uF l Figure 6 FPGA Serial Port Device address A2 A1 and AO is set up by connecting to ground and is mapped to 0000000x where x is the R W bit The eighth bit of the device address is the read write operation select bit A read operation is initiated if this bit is HIGH and a write operation is initiated if this bit is LOW 2 5 2 Connections between FPGA and the EEPROM The connections between the FPGA and the EEPROM ate shown in Table 9 Table 9 Connections between FPGA and the EEPROM Signal Name FPGA EEPROM EEPROM_SCL U6 D18 U26 6 EEPROM_SDA U6 H17 U26 5 2 6 PCI Express Interface x4 The Kintex 7 FPGA Integrated Block for PCI Express contains full support for 2 5Gb s and 5 0Gb s PCI Express Endpoint and Root Port configurations The LogiCORE IP Kintex 7 FPGA Integrated Block for PCI Express core internally instantiates the Kintex 7 FPGA Integrated Block for PCI Express PCIE_2_0 The DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 37 HARDWARE DESCRIPTION integrated block follows the PCI Express Base Specification layering model which consists of the Physical Data Link and Transaction layers The integrated block is compliant with the PCI Express Base Specification Rev 2 0 2 6 1 System Requirements e Windows o Wind
24. ARE DESCRIPTION Signal Name PCIE_TX_1p PCIE_TX_1n PCIE_TX_2p PCIE_TX_2n PCIE TX 3p PCIE_TX_3n f CICI P1 B28 U U PCIE_RX_0p PCIE_RX_0n PCIE_RX_1p P1 A16 P1 A17 P1 A21 PCIE_RX_1n PCIE_RX_2p PCIE_RX_2n PCIE_RX_3p PCIE_RX_3n C 2 7 SFP Interface only for DNPCle 10G K7 LL The 10GBASE SFP modules offer customers a wide variety of 10 Gigabit Ethernet connectivity options for data center enterprise wiring closet and service provider transport applications SFP is defined as Small Form Factor Pluggable standard by the SFP MSA and is most commonly used for 10 Gigabit Ethernet or 10 Gigabit Fiber Channel applications C f C The SFP modules are hot pluggable Hot pluggable refers to plugging in or unplugging a module while the host board is powered Due to routing losses in the printed circuit board utilizing 10GSFP Cu over copper is limited recommend SFP Direct Cable 10GbE Copper 1 6ft Amphenol P N SE SFPP2EPASS 000 5 2 7 1 SFP Circuit Diagram Two Small factor Pluggable SFP connectors are connected to the high speed GTX Transceivers on the FPGA DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 39 HARDWARE DESCRIPTION SFP Connector Decoupling Note Place these components close to the connector 2 3V REG 3 3Y REG I L4 AIH 4 3 3V_SFPO_VCCT I 13 ATH 3 3V SFFO VCCR TE 135A co C383 CAB 1 354 Cf Lea 0 1uF uF Our ANG 2uF
25. CONFIGURING THE HARDWARE 2 Configuring the FPGA using JTAG This section lists detailed instructions for programming the Xilinx Kintex 7 FPGA using iMPACT Version 14 2 tools The JTAG Boundary Scan configuration interface is always available regardless of the Mode pin settings The JTAG Boundary Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces Note This User Manual will not be updated for every revision of the Xilinx ISE tools so please be aware of minor differences 2 1 Setup Configuring the FPGA using JTAG Before configuring the FPGA ensure the following steps have been completed 1 Connect the USB 2 0 Cable to the bracket mounted USB 2 0 B connector 2 2 Powering Up the Board 1 Power up the board by turning ON the ATX power supply to the motherboard and verify the 12V LED DS16 is ON indicating the presence of 12V located on the back side of the board near the top left 2 3 Configuring the FPGA To configure the Xilinx FPGA perform the following steps 2 Open iMPACT and create a new default project Select Configure devices using Boundary Scan JTAG from the iMPACT welcome menu DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 14 PROGRAMMING CONFIGURING THE HARDWARE Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and id
26. DINI GROUP LOGIC Emulation Source User Manual DNPCle_10G_K 7_LL QSFP LOGIC EMULATION SOURCE DNPCle 10G K7_LL _QSFP User Manual Version 1 0 Date of Print December 12 2012 Dini Group 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Copyright Notice and Proprietary Information Copyright 2012 Dini Group All rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of the Dini Group Right to Copy Documentation Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However the Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents INTRODUCTION N E AES E sesconsaneutsessenscvasesecssenteadecssavaunonsdeaseosessssasusuacecdesveasoasduasucdoasbacessouaducseseoaceussnasasscasedeossvessnssosssevetse 1 1 DNPCIE_10G_K7_LL _QSFP ETHERNET PACKET ANAL
27. F gt One Step XSVF Console LICK cycle NoWait LCK cycle NoWait 08x 0011 1111 0101 1110 0000 1000 0100 0000 jownloading bit file to device completed successfully PROGRESS END End Operation Nol 1 Checking done pin done 1 Programmed successfully 4 m El console Errors MY Warnings 7 Verify that the FPGA_DONE blue LED DS15 is enabled indicating successful configuration of the FPGA 3 Configuring the FPGA using Master BPI In Master Byte wide Peripheral Interface BPI Mode the Kintex 7 FPGA configures itself from an attached industry standard parallel NOR flash PROM The board is populated with a Micron PC28F00AG18F 1 Gbit Flash PROM Table 2 shows the uncompressed configuration file size for the supported Kintex 7 devices Table 2 Kintex 7 Uncompressed Bitstream Length Device Data Size Bits PROM Flash XC7K325T 91 548 896 28FOOAG18F XC7K410T 127 023 328 28FOOAG18F Note This User Manual will not be updated for every revision of the Xilinx ISE tools so please be aware of minor differences DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 16 PROGRAMMING CONFIGURING THE HARDWARE 3 1 Setup Configuring the FPGA using Master BPI Before configuring the FPGA ensure the following steps have been completed 1 Connect the USB 2 0 Cable to the bracket mounted USB 2 0 B connector 3 2 Powering Up the Board 1
28. IPTION 4 2 Configuration DONE LEDs After the FPGA has received all the configuration data successfully it releases the DONE pin which is pulled high by a pull up resistor A low to high transition on the DONE indicates configuration is complete and initialization of the device can begin DONE pin drives an N MOSFET and turns ON a blue LED when the DONE pin goes high Table 17 describes the DONE LED and its associated pin assignment on the FPGA Table 17 FPGA DONE LED Signal Name FPGA LED FPGA_DONE U6 J7 DS15 5 Power Distribution The DNPClIe_10G_K7_LL _QSFP Ethernet Packet Analysis Engine supports a wide range of technologies from legacy devices like serial ports to DDR3 SDRAM Ethernet Transceivers and GTX Transceivers on the Xilinx FPGA This wide range of technologies including the various FPGA power supplies requires a variety of power supplies These are provided on the DNPCIe 10G K7 LL _QSFP Ethernet Packet Analysis Engine using a combination of switching and linear power regulators 5 1 In System Operation The primary source of power for the DNPCIe_10G_K7_LL _QSFP is from the PCI Express Edge Connector P1 All other voltages on the board are generated from this supply 6 Mechanical 6 1 Board Dimensions The board conforms to the PCI Express Card Electromechanical Specification 2 1 for a Low Profile Half Length Card The maximum component height is the specified height 14 47mm
29. L _QSFP is a PCI Express based FPGA board designed to minimize input to output processing latency on 10Gb Ethernet packets The primary application is for ultra low latency high throughput trading without CPU intervention Every possible variable that affects input to output latency has been analyzed and minimized Raw 10 GbE packets can be analyzed and acted upon without interrupts or an operating system adding delay to the process This configurable hardware computing platform has the ability to achieve the theoretical minimum Ethernet packet processing latency This board also has a time code input to allow for precise message time stamping and tracking 1 2 FPGA Xilinx Kintex 7 The Xilinx Kintex 7 in the FFG676 package is utilized for this product This package supports 400 IOs with the majority utilized Most are dedicated to a variety of off chip memory peripherals including QDR II for low latency high speed look up and DDR3 for performance oriented bulk storage The Kintex 7 FPGAs contain high speed transceiver PHYs The GTX transceivers are capable of handling data rates of 500 Mb s to 12 5 Gb s making these applicable to 10 Gigabit Ethernet 10 GbE and GEN1 GEN2 PCI Express applications Four of the GTX transceivers are used for GEN2 capable PCIe For the DNPCIe 10G K7 LL version two of the GTX transceivers are connected to 10 GbE SFP sockets or the DNPCle_10G_K7_LL_QSFP version four of the GTX transceivers are connected
30. NIUDIMM DDR3 2GB PC3 10600 244 Pin Micron P N MT9JBG25672AKZ 1G4 e DB9 to 2 5mm cable P N BC20223 6 e Customer Support Package on USB Flash Drive o Documentation Datasheets User Manual and Schematics o FPGA Reference Designs Verilog o Host Software AETest Optional Items e SFP Direct Cable 10GbE Copper 1 6ft Amphenol P N SF SFPP2EPASS 000 5 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 6 INTRODUCTION 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Demonstration MEG Array Daughter Card header insertion and removal video Videos Dini Group The web page will contain the latest user manual application notes Web Site FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from 7 Series Databook which contains device specific information on Xilinx device characteristics
31. RAM Memory Architecture 26 2 3 2 Design Guidelines QDR H SRAM IO Standards cesses 26 233 Connections between FPGA and QDR II SRAM Devices 4M x 18 PPA 24 DDR3 Memory VLPMINIUDIMM tise itteni sain oiie bleer ween AAE A EET OREO EVER EA E EAEE D EE EE a 29 2 4 1 DDR3 SDRAM Memory Interface Solution is ceccccasccccessevvecicoresaceescsevsncevcuscoevevavaussvtuscoesduasusteveseneesuassedusvetevesvenaiadeveusevetvcassaseveutevevsceusete 29 24 2 Design Guidelines DDR3 Termination ae 2 4 3 Design Guidelines DDR3 JO Standards s ciscisscisossseccsccassvascnsscarsctavearssesscatsstaseustccsnsasecsaaavatevanseneseansaacevasssascoanbabdenssssausvansoadensansanevansiaezs 244 Serial Presence Det ct EEPROM Opeta onic swvcsecasasecsscuviesscesevecesavsvavesunsexessdveveveseaseuedsdoscevasessvecdadessuucsdhovededeovevecadasvasscasevvecahasuesecdbevetecss 2 4 5 Clocking Connections between FPGA and MINIUDIMM se 2 4 6 Connections between FPGA and MINIUDIMM c eee tiii itseasissa ii sE DE ETE AEAEE ENEKE EE E 2 5 2 5 1 2 5 2 2 6 PCI Express Interface x4 2 6 1 System Requirements z 2 6 2 Clocking Jitter Attemu ators oriee a ra an AKEE EEEE EE ATA USERS ES OE EEEIEE EEAS AEEA EE A EEE ERES EAS 2 6 3 PEFEXpress Circuit aonais oa O tices Tese EE SES SISSE REDER EREA AONNE AARRE ENAERE ERNE ANETA AESA NEEE AEAEE ENEE 2 6 4 Connections between FPGA and PCI Express Edge Connector i 2 7 SFP Int rface onl
32. Scope Pro via JTAG 19 4 2 Powering Up the Board sccceccvsvasivsavsessvesacatcvssinecioasdaasevaaabiciousdascesavessiossasaoasnasataicesenevavagassavausssasesedasasaseatoaseseadesscssesaseseddoisseabsoasescadsasiensanatessdsea 20 4 3 Configuring the FPGA genron e eCa EEA EER SE IR NENS ASEN SEGA EREE OAE EE EE EAE RES Era 20 HARDWARE DESCRIPTION cscscsssssssssssssssssssssssssssssessssssscsssssssssesscssesesssssssesssessscssseasessesenssssessssasscssseassssesssssssesssssssessseasessesenssesessessssesssesesseseaseesess 21 1 DESCRIPTION sss pcan ac snr abscess loncome ESS TRE RES case EE EAEE ERE SETE Mico aa bse Nn vg Nel LA NASR AO RUS Rp sonar va lh 1 1 ONA n TAEAE E E E E A E E A A EE 1 2 PGA X hini KIMEN Ahern ORERE TEAT ET O REEE ENEA ANOS VEREV EES VAE AAS EEA AE RES 1 3 Two Channels of 10 GbE or Four Channels of 10 GbE for the QSFP version 14 QDR II SSRAM Memory with the Lowest Latency LS gt DDR DRAM Bulk MeMo rye asvccccascacatacaiseaseuissen ess EE se nese ate A Ea EEE RASENDE USHA AUGER Cal SEES SAU aa Oud Ua hse A CaN Sao SaaS 23 1 6 PCI Express Customizable 4 lane GEN2 PCI Express 14 23 1 7 Time Synchronization oee 524 2 FPGA KINTEX 7 24 2 1 FPGA Configuration 24 2 2 USB Port RS232 JTAG ig 24 2 2 1 RS232 JTAG Circuit Diagram SEE HE SEER STER 24 22 2 Connections between FPGA and the RS232 Port 25 2 3 QDR II SRAM Memory osos edd 2 3 1 QDRII S
33. YSIS ENGINE e cecceseeseeseeseeseeseeseesseeseeseeseceeesceeseeaecaecaeeeeneeeaeeseeaeeaeeeeeeeeaeeaees 1 1 1 Overview es 1 2 FPGA Xilinx KINESERE EE ESEE EE EEEE RE TE ENE TE NEKE OA ENNER 1 1 3 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version c ccccceccscssesessesessesesseseesesessesscseceessesessessesesesacesseeeesessseesaseeeagegs 2 14 QDR II SSRAM Memory with the Lowest Latency 1 5 DDR3 DRAM Bulk Memory 1 6 PCI Express Customizable 4 lane GEN2 PCI Express cccccscsscessessesssessensceseeseeseesecsecuseneeseesecseesecseeseeeseeseesecaecseceeseceeseeseesecaeceseseeaeeaeeaeeeeneenae 3 1 7 Time Synchronization is L8 How Everything WOKS oreore aroge see vente aaa as aa Ea e AA E le kat stn Peak EE EAE as Ans sb EE a ed she DR EESE 3 2 DNPCIE_10G_K7_LL _QSFP ETHERNET PACKET ANALYSIS ENGINE FEATURES sccecceseeseeseeseeeeseeeseeseeseeaecaeeseceeeaeeseeseeaeeeeeeeeaeeaees 4 3 PACKAGE CONTENTS iiae eaae rN AEE REESE SNE docs EA AETA EEEE e 4 INSPECT THE BOARD asagn ANER Be a Ena asm aR E ESSEN RESEN ESSENS ER ENEDES ESS SEER NERE TEGN GSAT EEEREN EE 5 ADDITIONAL INFORMATION tuoi esd ainiensen ieee as ae Aiea eo ee ne ec doe a alae GETTING STARTED ccccsssssssssssscssssssscscsscssasssssssscsssnsesecsessessssessassscesssseseasossessnsssessasscseseseassssesenssssessnsssscsoseassssosenssssassssassaseseassseseassssessssacessoseeseesess 8 1 BEFORE YOU BEGIN orenean ree anaa E aise E
34. anual www dinigroup com 2 INTRODUCTION utilized As with the QDRII SRAM the only real limitation is the amount of time and effort spent customizing the DDR3 memory controller to your needs 1 6 PCI Express Customizable 4 lane GEN2 PCI Express PCI Express is connected directly to the FPGA via 4 lanes of GTX transceivers The interfaces are GEN2 capable and the board is shipped with PCIe IP that is a full function fixed 4 lane master target To gain access to the PCIe interface this IP must be integrated with the user application Dini Group provides support with the IP including BAR sizes Additionally we can optionally add or subtract DMA engines scratchpad memories interrupts and other host related functions to maximize the performance while utilizing the minimum FPGA resources C source for drivers for several operating systems are included no charge Partial reconfiguration of the FPGA is supported via the PCle interface 1 7 Time Synchronization The time code input allows for precise message time stamping and tracking This input can receiver PPS or IRIG B000 RS232 RS485 RS422 TLL 1 8 How Everything Works With direct data feeds such as NASDAQ ITCH OUCH or Financial Information Exchange FIX the DNPCIe_10G_K7_LL _QSFP contains all of the basic functions required to minimize the amount of time it takes to recetve Ethernet packets process them and respond deterministically The MAC operating system et al
35. describes configuring and programming the hardware in detail DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 12 PROGRAMMING CONFIGURING THE HARDWARE Ci Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DNPCle 10G K7 ILL _OSFP Ethernet Packet Analysis Engine 1 Introduction This section of the User Manual presents different methods to configure the Xilinx Kintex 7 FPGA e Configuring the FPGA using JTAG using the USB 2 0 Cable e Configuring the FPGA using Master BPI using the BPI serial Flash PROM Kintex 7 FPGAs are configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes are supported e Master Byte Peripheral Interface BPI configuration mode x16 e JTAG Boundary Scan configuration mode The configuration modes are explained in detail in the UG470 7 Series FPGAs Configuration User Guide The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 13 PROGRAMMING
36. eatures of the DNPCIe 10G K7 IL OSFP Ethernet Packet Analysis Engine 1 Description 1 1 Overview The DNPCIe_10G_K7_LL _QSFP is a PCI Expressed based FPGA board designed to minimize input to output processing latency on 10Gb s Ethernet packets The primary application is for ultra low latency high throughput trading without CPU intervention Every possible variable that affects input to output latency has been analyzed and minimized Raw 10 GbE Ethernet packets can be analyzed and acted upon without interrupts or an operating system adding delay to the process This configurable hardware computing platform has the ability to achieve the theoretical minimum Ethernet packet processing latency A high level block diagram of the DNPClIe_10G_K7_LL QSFP Ethernet Packet Analysis Engine is shown in Figure 3 followed by a brief description of each section DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 21 HARDWARE DESCRIPTION PC3 10600 DDR3 DIMM 512M x 72 QDRII lt i Hom FPGA sme B23 Th C7 3 4Mx18 jia Kintex 7 5 7K325T 7K410T 1Gbit Time Sync 4 Lane PCle GENI GEN2 4 lane electrical 16 lane mechanical DNPCle_10G_K7_LL Son of Godzillas Bad Hair Day Block Diagram v1 01 Figure 3 DNPCIe_10G_K7_LL _QSFP Block Diagram Note the two SFP modules are replaced with one QSFP module in the _QSFP version 1 2 FPGA Xilinx Kintex 7 The Xilinx Kintex 7 in the FFG676 pac
37. entify Boundary Scan chain y Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File 3 iMPACT will identify the components in the JTAG chain A pop up window will display ERROR iMPACT Bsdl reader is not available for device 3 Click OK to proceed Reason QDR2 devices are also in the JTAG chain 4 A pop up window will display Device Programming Properties Device 1 Programming Properties Click OK to select default options 5 Right click on FPGA and select Assign New Configuration File Specify the location for the FPGA bit file based on the type of FPGA populated e g XC7K325T a pop up window will display Attach SPI or BPI PROM Click NO to proceed 6 Right click on the FPGA and select the Program option Click OK in the Device Programming Properties window A Configuration Operation Status box will appear indicating programming progress DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 15 PROGRAMMING CONFIGURING THE HARDWARE EP e r i File Edit View Oper Dae xa IMPACT Flows 88 Boundary Scan SPREE E SystemACE oe E Create PROM File PROM File Formatter E WebTalk Data To TRAE xc2o84a unknown 2 3 fpga_a bit bypass unknown_2_3 bsd iMPACT Processes 08 x Available m Prog gt m Get Device Signature Usercode Read Device Status One Step SV
38. hysical attributes User specific information can be written into the remaining 128 bytes of storage READ WRITE operations between the system master and the EEPROM slave device occur via a standard I2C bus using the DIMMs SCL clock and SDA data signals together with SA 1 0 which provide four unique DIMM EEPROM addresses Write protect WP is connected to Vss internal to the Temp Sensor EEPROM permanently disabling hardware write protection Please note that VDDSPD is connected to 3 3V Table 6 Serial Presence Detect EEPROM Connections Signal Name FPGA MINIUDIMM DIMM SA0 J7 119 pull down 4 7K R256 DIMM SA1 J7 241 pull down 4 7K R323 DIMM SA2 J7 121 pull down 4 7K R255 U6 E12 J7 120 pull up 4 7K R285 DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 31 HARDWARE DESCRIPTION DIMM_SDA U6 C14 J7 242 pull up 4 7K R324 2 4 5 Clocking Connections between FPGA and MINIUDIMM The clocking connections between the FPGA and the MINIUDIMM connector are shown in Table 7 Table 7 Clocking Connections between FPGA and the UDIMM Connector Signal Name FPGA MINIUDIMM DIMM CKO0P U6 AE12 J7 186 DIMM CKON U6 AF12 J7 187 DIMM_CK1P U6 AB12 J7 64 DIMM CKIN U6 AC12 J7 65 2 4 6 Connections between FPGA and MINIUDIMM Table 8 shows the connections between the FPGA and the MINIUDIMM connector pins Table 8 Connections between FPGA and the UDIMM Connector G G clic eal bre
39. ionally controls SFP module transmitter Receiver Ground Receiver Ground Inverse Received Data Out Received Data Out Receiver Ground Receiver Power Transmitter Power Transmitter Ground Transmitter Data In Inverse Transmitter Data In Transmitter Ground 2 7 4 Connections between FPGA and the SFP Connectors Table 12 lists the connections between the FPGA and the SFP connectors DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 41 HARDWARE DESCRIPTION Table 12 Connections between FPGA and the SFP Connectors Signal Name FPGA SFP Connector SFP Clocks SFPO_REFCLKP U6 D6 X5 4 SFPO_REFCLKN U6 D5 X5 5 SFP Channel 0 SFPO_TXP U6 A3 J8 18 SFPO_TXN U6 A4 J8 19 SFPO_RXN U6 C4 J8 12 SFPO_RXP U6 C3 J8 13 SFPO_SCL U6 G10 J8 5 SFPO_SDA U6 H8 J8 4 SFPO_TXDISABLE U6 H9 J8 3 SFPO_TXFAULT U6 J8 J8 2 SFPO MOD ABS U6 G9 J8 6 SFPO_RSO U6 J13 J8 7 SFPO_RS1 U6 J11 J8 9 SFPO_RX_LOS U6 H13 J8 8 SFP Channel 1 SFP1_TXP U6 B1 J5 18 SFP1_TXN U6 B2 J5 19 SFP1_RXP U6 B6 J5 13 SFP1_RXN U6 B5 J5 12 SFP1_SCL U6 H12 J5 5 SFP1_SDA U6 G14 J5 4 SFP1_TXDISABLE U6 H14 J5 3 SFP1_TXFAULT U6 J10 J5 2 SFP1_MOD_ABS U6 H11 J5 6 SFP1_RSO U6 F9 J5 7 SFP1_RS1 U6 D9 J5 9 SFP1_RX_LOS U6 F8 J5 8 Note SFPO_TXp n pair is swapped and SFP1_TXp n pair is swapped This must be add
40. it Setup Control Window Help Main Menu lt gt DDR 3 Test requir ECC module gt RocketIO Test Restart and Check status Rocket IO st Check status only QDR2 Test I2C Test Clock Frequencies Check Misc Pins Test DC Display RS232 connections isables RS232 Enables RS485 loops back USB RS232 to RS485 loops back USB RS232 to RS232 Disables RS232 Enables RS485 lt RX only loops back USB RS232 to RS485 Enter Option CAND ENTER gt waiting for init done pd init done f 3 Select test option 3 QDR2 Test in the Terminal window and verify that the test PASS periods will be displayed as the memory locations are being tested if no QDR2 Memory fails the test will display read write errors W COM53 19200baud Tera Term anra File Edit Setup Control Window Help Main Menu lt requires ECC module est Restart and Check status est Check status only Check ay RS232 connectio lt lt nS les RS232 Ena 32 to RS485 ick USB RS232 t S232 KO Dis s RS232 Enables R8485 lt RX only loops back USB RS232 to RS485 Enter Option AND ENTER gt for QDR2 init done QDR2 Complete The remainder of the reference design functional tests requires various loop back test boards modules to make them PASS and is not covered in this User Manual Please reference the Customer Support Package on USB Flash Drive for code examples The next section
41. ith the Lowest Latency One quad data rate static RAMs QDR II SSRAM is used in the 4M x 18 size This style of memory has separate input and output data paths enabling maximum read write data bandwidth with minimum latency Using 3 speed grade FPGA this interface is capable of running at the maximum I O frequency of 500MHz To minimize processing latency we suspect it will be best to clock these QDRII SSRAMs at 312 50 MHz exactly twice the internal Ethernet controller frequency of 156 25MHz The Kintex 7 FPGAs are capable of generating internal 2x clocks that are phase synchronous eliminating the latencies associated with the tricky re synchronization of data moving between different clock frequencies The internal controller can be optimized in any way you choose Dini Group provides several Verilog examples All functions of the QDR I SSRAM can be exploited including concurrent read and write operations and four tick bursts The only real limitation is the amount of time and effort spent in customizing the individual memory controllers 1 5 DDR3 DRAM Bulk Memory A single 244 pin PC3 10600 DDR3 VLP MINIUDIMM socket enables up to 4GB of memory for bulk storage and lookup Using a 2 or 3 speed grade FPGA this interface is tested at the maximum FPGA I O frequency 666 5MHz 1333Mb s with DDR The user can use this memory as 64 bits with 8 bits of error correction ECC or as a 72 bit byte memory without correction To minimize data
42. kage is utilized for this product This package supports 400 IOs with the majority utilized Most are dedicated to a variety of off chip memory peripherals including QDR II for low latency high speed look up and DDR3 for performance oriented bulk storage The Kintex 7 FPGAs contain high speed transceiver PHYs The GTX transceivers are capable of handling data rates of 500 MB s to 12 5 Gb s making these applicable to 10 Gigabit Ethernet 10 GbE and GEN1 GEN2 PCI Express applications Four of the GTX transceivers are used for GEN2 capable PCIe For the DNPCIe 10G K7 LL version two of the GTX transceivers are connected to 10 GbE SFP sockets For the DNPCle_10G_K7_LL_QSFP version four of the GTX transceivers are connected to the 40 GbE QSFP socket Either the XC7K325T or the XC7K410T FPGAs can be populated Both come in three speeds grades with 3 being the fastest 1 3 Two Channels of 10 GbE or Four Channels of 10 GbE for the QSFP version The Kintex 7 FPGAs have transceivers capable of 10 GbE The physical interface is handled using SFP modules or a single QSFP module for the _QSFP verison This allows you to bypass a MAC if necessary and process raw Ethernet packets The DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 22 HARDWARE DESCRIPTION DNPCIe_10G_K7_ LL has two 10 GbE channels and the DNPCIe 10G K7 LL QSFP has four 10 GbE channel and can support 10GBASET ER 10GBASET SR 10GBASET KR 1 4 QDR Il SSRAM Memory w
43. m 23 HARDWARE DESCRIPTION performance while utilizing the minimum FPGA resources C source for drivers for several operating systems are included no charge Partial reconfiguration of the FPGA is supported via the PCle interface 1 7 Time Synchronization The time code input allows for precise message time stamping and tracking This input can receiver PPS or IRIG B000 RS232 RS485 RS422 TLL 2 FPGA Kintex 7 2 1 FPGA Configuration Kintex 7 FPGAs are configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes are supported e Master BPI x16 e JTAG Boundary Scan The FPGA drives up to 26 address lines to access the attached parallel flash For configuration from industry standard parallel NOR flash only asynchronous read mode is used In asynchronous read mode the FPGA drives the address bus and the flash PROM drives back the bitstream data Using the JTAG interface the Kintex 7 FPGA can be configured using Xilinx software G MPACT or ChipScope software and USB 2 0 Cable 2 2 USB Port RS232 JTAG A RS232 JTAG ports U15 are provided for low speed communication
44. ows XP Professional 32 bit 64 bit o Windows Vista Business 32 bit 64 bit e Linux o Red Hat Enterprise Linux WS v4 0 32 bit 64 bit o Red Hat Enterprise Desktop v5 0 32 bit 64 bit with Workstation Option o SUSE Linux Enterprise SLE v10 1 32 bit 64 bit e Software o ISE v14 2software O Check the release notes for the required Service Pack ISE software Service Packs can be downloaded from http www xilinx com support download index htm For more information regarding the Kintex 7 FPGA Integrated Block for PCI Express reference the PG054 7 Series FPGAs Integrated Block for PCI Express Product Guide 2 6 2 Clocking Jitter Attenuator The ICS874001AGI 02LF U9 is a high performance Differential to LVDS Jitter Attenuator designed for use in PCI Express systems 2 6 3 PCI Express Circuit High speed LVDS traces connect the PCI Express Edge Connector P1 directly to the GTX Transceivers on the FPGA U6 AC Coupling Capacitors in the transmit direction ensures blocking of DC currents and specified by the PCI Express Card Electromechanical Specification Rev 2 0 2 6 4 Connections between FPGA and PCI Express Edge Connector Table 10 shows the connections between the FPGA GTX Transceivers and the PCI Express Edge connector pins Table 10 Connections between FPGA and the PCI Express Edge Connector Signal Name FPGA PCI Express PCIE_TX_0Op U9 R4 P1 B14 DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 38 HARDW
45. programming and debugging with the Kintex 7 FPGA The FT2232H is a USB to JTAG UART interface device which simplifies USB to serial designs and reduces external component count by fully integrating an external EEPROM and USB termination resistors It has been designed to operate efficiently with a USB host controller by using as little as possible of the total USB bandwidth available 2 2 1 RS232 JTAG Circuit Diagram Figure 4 shows the implementation of the USB port DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 24 HARDWARE DESCRIPTION Figure 4 FPGA Serial Port There are two signals attached to the FPGA for RS232 communication e Transmit Data USB B TXD e Receive Data USB B RXD The USB Transceiver Cell provides the USB 1 1 USB 2 0 full speed physical interface to the USB cable 2 2 2 Connections between FPGA and the RS232 Port The connections between the FPGA and the RS232 Port are shown in Table 3 Table 3 Connections between RS232 Port and the FPGA Signal Name FPGA RS232 USB_B_TXD U6 G11 U15 38 USB_B_RXD U6 F10 U15 39
46. ressed in your FPGA design DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 42 HARDWARE DESCRIPTION 2 8 QSFP Interface only for the DNPCle_10G K7 LL QSFP The 40GBASE QSFP modules offer customers a wide variety of 40 Gigabit Ethernet connectivity options for data center enterprise wiring closet and service provider transport applications QSFP is defined as Quad Small Form Factor Pluggable standard by the QSFP MSA and is most commonly used for 40 Gigabit Fiber Channel applications The QSFP modules are hot pluggable Hot pluggable refers to plugging in or unplugging a module while the host board is powered Due to routing losses in the printed circuit board utilizing 40GSFP Cu over copper is limited 2 8 1 QSFP Circuit Diagram A single Quad Small factor Pluggable QSFP connectors are connected to the high speed GTX Transceivers on the FPGA QSFP Connector Decoupling Figure 9 QSFP Channel 0 Interface Fixed frequency 156 25 MHz LVPECL oscillator X5 is used to clock the GTX transceivers see Figure 10 These parts ate available from Silicon Laboratories P N 534SC000390DG The oscillator power supply is filtered to reduce power supply noise and jitter DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 43 HARDWARE DESCRIPTION pa LVDS R6 127 lt R161 AK Al IK 1
47. s wd 4 2 Configuration DONE LEDS isssssessssseeisistasscsasatasivasiaaccnasatavevasdsacinvsansaveveisasasagassacseaieaseensassesseasesseeeaasasascassseesadeasaessabasesea ietsdecssbateseasazedsvaspageseaseas 49 5 POWER DISTRIBUTION giri eet aO NEEE OEE AEE SEERE DESK ENS EEEE E SKE ere SSR DE berg teed 49 5 1 In System Operation a 6 MECHANICAL iesscveccassvccessssvscxcebuvetenstosdvconuvcnds voto ENERE EEEE AEREE EE ATEREA ERREKETEEK REE AEK REGEER 6 1 Boar DIMENSIONS ni a aE E EERE Goa Eta er IEE EEE E AEE EAEN OEA N E EAEEREN 49 APPENDIX 51 7 ARPENDIX A UCR FILE Seese yaoa a A n Ea E E AEA EEN rE OEE TECEN OE oE EE O PERETE APERE EG ORENG 51 8 ORDERING INFORMATION vertie okrepite NEn E A VEEE KEA A EEE E EAEE E EE E EE EEE N E EE EEE OS 51 List of Figures Figure 1 DNPClIe_10G_K7_LL _QSFP Ethernet Packet Analysis Engine upper picture is the DNPCIe_10G_K7_LL and lower picture is the DNPCIe 10G K7 LL QSFP Figure 2 USB Flash Drive Directory Structute 7 Figure 3 DNPCle_10G_K7_LL _QSFP Block Diagram Note the two SFP modules are replaced with one QSFP module in the _QSFP version 22 Figure 4 FPGA Serial Port Figure 5 QDR H Memory Architecture Figure 6 FPGA Serial Port Figure 7 SFP Channel 0 Interface Figure 8 SFP GTX Oscillator Figure 9 QSFP Channel 0 Interface Figure 10 QSFP GTX Oscillator List of Tables Table T USB Flash Drive Directory Comtent3 ss ccssesscccc
48. sessossssesiscssseseccavscssesviesccsv eesscsssestedssosohessvavolesevosolessvasglessvnsghessverglessvbsolessvosglessvasolessvasglessvosolesavavelessvasghesvivelesepeeones Table 2 Kintex 7 Uncompressed Bitstream Length Table 3 Connections between RS232 Port and the FPGA Table 4 QDR II SRAM IO Standards Table 5 Connections between FPGA and the QDR H SRAM Devices Table 6 Serial Presence Detect EEPROM Connections ccceeeeseseereeeeees Table 7 Clocking Connections between FPGA and the UDIMM Connector Table 8 Connections between FPGA and the UDIMM Connector Table 9 Connections between FPGA and the EEPROM Table 10 Connections between FPGA and the PCI Express Edge Connector Fable 11 SEP Pin Assigtiments 22 0 20 c5i5cisecnascneessedssesetiedteecbedecerstieee Table 12 Connections between FPGA and the SFP Connectors Table 13 QSFP Pin ASSISNMENtS irssi tisasari ensien Table 14 Connections between FPGA and the QSFP Connectors Table 15 Connection between the FPGA and the System Clock Oscillator Table 16 FPGA Status LEDs Table 17 FPGA DONE LED INTRODUCTION Introduction This User Manual accompanies the DINPCle_10G_K7_LL QSFP Ethernet Packet Analysis Engine For specific information regarding the Xilinx Kintex 7 parts please reference the datasheet on the Xilinx website 1 DNPCle_10G K7_LL _QSFP Ethernet Packet Analysis Engine 1 1 Overview The DNPCIe_10G_K7_L
49. shows the connections between the FPGA and the QDR H SRAM device U4 Table 5 Connections between FPGA and the QDR II SRAM Devices Signal Name QDRIIP_BWS0n QDRIIP_BWS1n QDRIIP_CQ QDRIIP_CQn QDRIIP_DO QDRIP D1 QDRIP_D2 QDRIIP_D3 QDRIIP_D4 QDRIIP_D5 QDRIIP_D6 QDRIIP_D7 QDRIIP_D8 QDRIIP_D9 QDRIIP_D10 QDRIIP_D11 QDRIP D12 QDRIP D13 QDRIP D14 QDRIP D15 QDRIP D16 QDRIIP D17 DNPCle_10G_K7_LL _QSFP User Manual FPGA 6 AA25 6 AB25 6 N21 6 R21 6 V21 6 V22 6 U22 6 U24 6 U25 6 W25 6 V26 6 W26 6 U26 6 AC26 6 AB26 6 Y26 6 Y25 6 AB24 6 AA23 6 Y23 6 W24 6 W23 CIS CICI GIG G WWW QRD II SRAM U4 B7 dinigroup com 27 HARDWARE DESCRIPTION Signal Name QDRIIP_DOFFn QDRIP K QDRIP Kn QDRIP Q0 QDRIP Q1 QDRIP Q2 QDRIP Q3 QDRIIP_Q4 QDRIIP_Q5 QDRIP Q6 QDRIP_Q7 QDRIIP_Q8 QDRIIP_Q9 QDRIIP_Q10 QDRIP Q11 QDRIP Q12 QDRIIP_Q13 QDRIP Q14 QDRIP Q15 QDRIP Q16 QDRIIP_Q17 QDRIP_QVLD QDRIIP_RPSn QDRIIP_WPSn QDRIIP_SAO QDRIIP_SA1 QDRIIP_SA2 QDRIIP_SA3 QDRIIP_SA4 QDRIIP_SA5 QDRIIP_SA6 DNPCle_10G_K7_LL _QSFP User Manual FPGA 6 K25 6 V23 6 V24 6 P19 6 N19 6 P20 M20 M21 N22 6 M22 6 M24 6 L24 6 T24 6 T25 6 T23 6 R23 6 T22 6 R22 6 U19 6 T20 6 R20 6 P21 6 AE22 6 AE25 6 AD25 6 AD26 6 AE26 6 AC24 6 AD24 6 AE23 6 AF23 amp IGIG oN nN I Sp I C S amp N GCE CICI CICI C SRAM U4 H1 U4 B6 U4 A6 4 F11 4
50. structions for executing the reference design Ensure the DNPCle_10G_K7_LL _QSFP Ethernet Packet Analysis Engine is powered ON and a Terminal Window is open to exercise the reference design options 1 Select test option 6 Clock Frequencies Check in the Terminal window and verify that the test displays VALID frequencies cz W COM53 19200baud Tera Term VT arma File Edit Setup Control Window Help Main Menu DDR3 Test lt requires ECC module RocketIO Test Restart and Check status RocketIO Test Check status only QDR2 Test I2C Test Clock Frequencies Check gt Misc Pins Test XADC Display test RS232 connect ions Disables RS232 Enables RS485 loops back USB RS232 to RS485 loops back USB RS232 to RS232 Disables RS 232 Enables RS485 lt R amp X only loops back USB RS232 to RS485 Enter Option CAND ENTER gt 49 744898 Mhz 99 981633 Mh 9 591837 Mh 6 666606 Mh 66 147959 24 413265 B B BB Mh 57 423469 57 551028 MGT T 115 249 872449 Mhz 2 Select test option 0 DDR3 Test requires ECC module in the Terminal window and verify that the test PASS periods will be displayed as the memory locations are being tested if no DDR3 Module is present the test will display read write errors DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 11 GETTING STARTED E l COM53 19200baud Tera Term VT l come File Ed
51. synchronization across clock boundaries it probably makes sense to clock the DDR3 interface at a 3x multiple of the base Ethernet frequency of 156 25 MHz which is 468 75MHz A 3x phase synchronous clock can be easily generated internal to the FPGA allowing zero latency synchronous data transfers between the Ethernet packet receiving logic and the DDR3 memory controller The DDR3 controller can be optimized in any way you choose We of course provide several Verilog examples All functions of the DDR3 DRAM can be exploited and optimized Timing variables such as CAS latency and precharge can be tailored to the minimum given your operating frequency and the timing specification of the exact DDR3 memory utilized As with the QDRII SRAM the only real limitation is the amount of time and effort spent customizing the DDR3 memory controller to your needs 1 6 PCI Express Customizable 4 lane GEN2 PCI Express PCI Express is connected directly to the FPGA via 4 lanes of GTX transceivers The interfaces are GEN2 capable and the board is shipped with PCIe IP that is a full function fixed 4 lane master target To gain access to the PCIe interface this IP must be integrated with the user application Dini Group provides support with the IP including BAR sizes Additionally we can optionally add or subtract DMA engines scratchpad memories interrupts and other host related functions to maximize the DNPCle_10G_K7_LL _QSFP User Manual www dinigroup co
52. tions User Guide DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 29 HARDWARE DESCRIPTION 2 4 2 Design Guidelines DDR3 Termination These rules apply to termination for DDR3 SDRAM e Unidirectional signals are to be terminated with the memory device s internal termination or a pull up of 402 to VTT at the load A split 80Q termination to VCCO and an 8022 termination to GND can be used but takes more power For bidirectional signals the termination is needed at both ends of the signal DCI ODT ot external termination Vit gt Rr 402 ZQ UGsae c 7 0011 Figure 1 70 409 Termination to Vyr Veco L 2xZQ 3800 Za Source sA EH Load lt 2xZQ bd 802 UCase c1 71 com e Differential signals should be terminated with the memory device s internal termination or a 80Q differential termination at the load For bidirectional signals termination is needed at both ends of the signal DCI ODT or external termination ZQ Source_P Ja Load_P 2xZQ gt 800 ZQ Source_N a ae Load_N UGens_ 1_72_051011 e All termination must be placed as close to the load as possible The termination can be placed before or after the load provided that the termination is placed within a small distance of the load pin The allowable distance can be determined by simulation e DCI can be used at the FPGA as long as the DCI rules such as VRN VRP are followed DNPCle 10G K7 LL _QSFP User Manual www dinigroup com 30
53. to the 40 GbE QSFP socket DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 1 INTRODUCTION Hither the XC7K325T or the XC7K410T FPGAs can be populated Both come in three speeds grades with 3 being the fastest 1 3 Two Channels of 10 GbE or Four Channels of 10 GbE for the _QSFP version The Kintex 7 FPGAs have transceivers capable of 10 GbE The physical interface is handled using SFP modules or a single QSFP module for the _QSFP verison This allows you to bypass a MAC if necessary and process raw Ethernet packets The DNPClIe 10G K7 LL has two 10 GbE channels and the DNPCIe 10G K7 LL QSFP has four 10 GbE channel and can support 10GBASET ER 10GBASET SR 10GBASET KR 1 4 QDR Il SSRAM Memory with the Lowest Latency One quad data rate static RAMs QDR II SSRAM is used in the 4M x 18 size This style of memory has separate input and output data paths enabling maximum read write data bandwidth with minimum latency Using 3 speed grade FPGA this interface is capable of running at the maximum I O frequency of 500MHz To minimize processing latency we suspect it will be best to clock these QDRII SSRAMs at 312 50 MHz exactly twice the internal Ethernet controller frequency of 156 25MHz The Kintex 7 FPGAs are capable of generating internal 2x clocks that are phase synchronous eliminating the latencies associated with the tricky re synchronization of data moving between different clock frequencies The internal controller
54. www dinigroup com 45 HARDWARE DESCRIPTION Signal Name QSFP Connector QSFP_TX1p J11 36 QSFP_TX1n J11 37 QSFP_RX2p J11 22 QSFP RX2n J11 21 QSFP_TX2p J11 3 QSFP_TX2n J11 2 QSFP_RX3p J11 14 QSFP_RX3n J11 15 QSFP_TX3p J11 33 QSFP_TX3n J11 34 QSFP_RX4p J11 25 QSFP_RX4n J11 24 QSFP_TX4p J11 6 QSFP_TX4n J11 5 QSFP_MODSELn J11 8 QSFP_RESETn J11 9 QSFP_LPMODE J11 31 QSFP_INTn J11 28 QSFP_MODPRSn J11 27 QSFP_SCL_FET J11 11 QSFP_SDA_FET J11 12 Note QSFP_TXp n pair is swapped This must be addressed in your FPGA design 2 9 Time Synchronization Gare ee ea are SELE ES EL 6 e ere te bene Cc DNPCle_10G_K7_LL _QSFP User Manual www dinigroup com 46 HARDWARE DESCRIPTION 2 9 1 Time Synchronization Circuit Diagram Half Duplex RS422 485 170mA MAX i He n H de rs Depending on the time code input U2 U3 can be configured to accept signals including PPS and IRIG B000 RS232 RS485 RS422 TTL 2 9 2 Connections between the FPGA and Time Synchronization Circuitry Signal Name FPGA U2 U3 RS485_RO U6 D23 U2 A6 RS485_DI U6 D24 U2 A3 RS485_ON U6 F22 U2 A8 RS485_TE U6 E23 U2 A2 RS485_REn U6 G22 U2 A5 RS485_DE U6 F23 U2 A4 RS232_T1IN U6 F12 U3 A4 RS232_R10UT U6 D14 U3 A3 RS232_ON U6 D13 U3 A6 RS232_DIN U6 E1
55. y for DNPCIe 10G K7 LL sisicissasesvevesasseisinsaacevadessevcsscasssvadeasecesscassenaiesavsessessdoasansavavsdeasduesanaauaeacedsdossanaansea cesadossanasnscaeds 2 7 1 SEP Citcvit Diagrami aoe ei oiee ia EE EOS NEE ATE EE E EEE E EN NENE E AE EEEE 2 7 2 LED indicators 27 3 SFP Pin Assignment cscsscceeeseeceeteeseeteeneeeeeeee 2 74 Connections between FPGA and the SFP Connectors 2 8 QSFP Interface only for the DNPCIe 10G K7 LL QSFP 2 8 1 QSFP Circuit Diagram 2 8 2 LED indicators 2 8 3 QSFP Pin Assignment ccceseseeseeeeeeeeeeeeeeeneeeeaes 2 8 4 Connections between FPGA and the QSFP Connectors 2 9 Time Synchronization 2 9 1 Time Synchronization Circuit Diagram 219 2 Connections between the FPGA and Time Synchronization Circuitry in 3 CLOCK GENERATION wesc atnese EEEL ANEETA NAVO EE ANEKA AEGEE E iytuned E ANE VEEE EA EAEE 3 1 System Clock IDELAYCTR iss sisvasevssiavesssssvavevesssvesacsabetevassevecssasaa teva sansevesscssdeva tes svscsasessena tubavecssesseenaanaavavedeaseueaanaasavaceusbessdeauaeasevseosaanansdezsess 3 1 1 Connection between FPGA and the System Clock Oscillator ee 3 2 t High Speed CIX CLOCKS cccacasceseta ee EEE satus EAE EEA ERR ott vee eA EG AAW ERIE REE ERE Ene REDE EET aE EEa avs DaR a OAE aes 48 4 FED INDICATORS es EET ES EEEE SE TREENER cece ssictaaeesusdueuvegceuzeveuseensttec sturstotaeesedcaseuscdetovues ccesesteactscuweletede 4 1 FPGA Status LED

User Manual DNPCIe_10G_K7_LL (_QSFP)

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