SuperHTM Family E10A-USB Emulator Additional
Contents
1. AUD pin 4 bits The trace data is acquired from the 4 bit AUDATA pin 8 bits The trace data is acquired from the 8 bit AUDATA pin This mode is not available when the SH7663 is used Note When the AUD trace is enabled the emulator forcibly changes the pin functions of the specified port as the AUD functions 29 RENESAS To set the AUD trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the Trace model Trace mode2 or AUD mode group box in the Trace mode page of the Acquisition dialog box Acquisition Trace Mode Trace type e y C Internal trace C User Memory trace r Trace Mode 1 Realtime trace Non realtime trace Trace Mode 2 Trace continue Trace stop AUD Mode Abit Capt AUD trace display range Start pointer 255 End pointer Do User memory area Trace Extend Mode Trace data with PPC Figure 2 6 Trace Mode Page When the AUD trace function is used select the AUD function radio button in the Trace type group box of the Trace mode page 30 RENESAS Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics operands or source is not displayed The AUD branch trace function outputs the differences betwe2. 12 13 14 Memory Access during Break In the enabled MMU when a memory is accessed and a TLB error occurs during break it can be selected whether the TLB exception is controlled or the program jumps to the user exception handler in TLB Mode in the Configuration dialog box When TLB miss exception is enable is selected a Communication Timeout error will occur if the TLB exception handler does not operate correctly When TLB miss exception is disable is selected the program does not jump to the TLB exception handler even if a TLB exception occurs Therefore if the TLB exception handler does not operate correctly a Communication Timeout error will not occur but the memory contents may not be correctly displayed Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 5 MHz IO Window e Display and modification Do not change values of the User Break Controller because it is used by the emulator For each watchdog timer register there are two registers to be separately used for write and read operations Table 2 3 Watchdog Timer Register Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter e The watchdog timer operates only when the user program is execu
3. 18th 191 2 ka Hangang ro Yongsan ku Seoul 140 702 Korea Tel 82 2 796 3115 Fax 82 2 796 2145 Renesas Technology Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jalan Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 603 7955 9390 Fax 603 7955 9510 Colophon 4 0 SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7763 2 NE S AS RenesasTechnology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
4. ASID Status address Bus Break Count Trace Trace Action Event X X X X X X X X Condition B T 9 dialog and P box Event X X X X X X X Condition B and 10 dialog P box Event o X X X X X Condition B and 11 dialog P box Event X X X X X X X X X Condition B T 12 dialog and P box Software X X X X X X X X X trace fixed dialog box Notes 1 Can be set in the dialog box X Cannot be set in the dialog box 2 For the Action item B Setting a break is enabled T Setting a trace is enabled P Setting a performance start or end condition is enabled 18 RENESAS Sequential Setting In the emulator sequential setting of an Event Condition is enabled Table 2 6 Sequential Event Conditions CPU Sequential Event Page Type 2 Channel Sequential Event Condition Ch2 gt 1 Description Halts a program when a condition is satisfied in the order of Event Condition 2 1 An event condition must be set for Ch2 and Ch1 Ch4 gt Halts program when condition is satisfied in the order of Event Condition 4 3 An event condition must be set for Ch4 and Ch3 Ch6 gt 5 Halts a program when a condition is satisfied in the order of Event Condition 6 5 An event condition must be set for Ch6 and Ch5 Ch11 gt 10 Halts a program when a condition is satisfied in the order of Event Condition 11 10 An event conditi
5. do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector Figures 1 1 and 1 2 show the pin assignments of the 36 pin and 14 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer RENESAS SH7763 Input SH7763 Pin No Note No Output No AE18 19 Input AC21 20 21 Input 22 23 Input 24 25 Output 26 27 Input output 28 29 Output 30 GN 31 Output User reset 32 GND N C 33 Output GND 34 GND TCK Input AE19 35 NC GND 36 GND Notes 1 Input to or output from the user system 2 The symbol means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 When the user system interface cable is connected to this pin and the MPMD pin is set to 0 do not connect to GND but to the MPMD pin directly Edge of the board H UDI port connector top view connected to the connector Fi is Pin 1 mark 1 27 M2 6 x 0 45 I4 21 59 37 61 43 51 Pattern inhibited area H UDI port connector top view H UDI port connector front view Figure 1 1 Pin Assignments of the H UDI Port Connec
6. Acquisition dialog box The AUD trace acquisition mode can be set in the Trace model or Trace mode2 group box in the Trace mode page of the Acquisition dialog box Acquisition Trace Mode Trace type C AUD trace C Internal trace User Trace Mode 1 Realtime trace Non realtime trace Trace Mode 2 Trace continue Trace stop AUD Mode Abit C hit AUD trace display range start pointer D 255 End pointer nio o User memory area Start H3000 End Address H33FF Trace Extend Mode Trace data with PPC me Figure 2 7 Trace Mode Page 33 RENESAS Notes 1 The memory range for which trace is output is the address on the system bus and not supported for the MMU or cache 2 In the memory range for output do not specify the ranges that the user program has been downloaded or the user program accesses 3 The range for trace output must be 1 MB or less 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK Set the JTAG clock frequency to lower than the frequency of the SH7763 peripheral module clock CKP Set the AUD clock AUDCK frequency to 50 MHz or lower If the frequency is higher than 50 MEZ the emulator will not operate normally The set value of the JTAG clock TCK is initialized by executing Reset CPU or Reset Go 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address
7. Eventpoint window Remove the check mark of the Don t care check box in the Window address page and enter the memory range to be set Event condition 5 Window address ASID Bus State Action Window address Start address H 00000000 End address H 00000000 Ges Figure 2 4 Window address Page 26 RENESAS i Open the ASID page remove the check mark of the Don t care check box and enter the ASID value to be set When the ASID value is not set as a condition do not remove the check mark of the Don t care check box i Open the Bus state page and specify the bus type and bus cycle that are to be set Event condition 5 Window address ASID Bus State Action Bus state Read Write Read Write Bead C Write Figure 2 5 Bus State Page Selecting the Acquire trace check box in the Action page enables acquiring memory access within the range Note To cancel settings select the popup menu that is opened by clicking on the Ch5 OA or Ch6 OA column with the right mouse button 27 RENESAS Software Trace Function Note This function can be supported with SHC C compiler manufactured by Renesas Technology Corp including OEM and bundle products V6 0 or later However SHC C compiler including OEM and bundle products V8 0 or later is needed when instructions other than those compatible with SH4 are output Wh
8. IA OA R and Ch11 of Event Condition cannot be used 2 2 7 Note on Setting the PPC MODE Command In the Configuration dialog box if User is set while the PPC mode list box has been set Ch1 and Ch2 of the performance analysis function and options 1 and 2 of the profile function cannot be used 2 2 8 Performance Measurement Function The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE SET command When a channel line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the Performance Analysis dialog box is displayed by selecting Setting 36 RENESAS Performance Analysis Condition Cycle D Selection of a count item GPU performance Cycle Count C Instruction C Branch Exception interruption C Stalled Cycle C TLB performance C Instruction bus performance r Operand bus performance Access count Access miss count Waited cycle SY SCT pert m Extend counter Enable EN Figure 2 8 Performance Analysis Dialog Box Note For the command line syntax refer to the online help a Specifying the measurement start end conditions Set the performance measurement conditions in the Action page after conditions
9. a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 3 Trace information cannot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset 28 RENESAS AUD Trace Functions This function is operational when the AUD pin of the device is connected to the emulator It is activated by selecting the AUD trace radio button in the Trace type group box of the Trace mode page Set the trace condition to be used Table 2 9 shows the AUD trace acquisition mode that can be set in each trace function Table 2 9 AUD Trace Acquisition Mode Type Mode Continuous Realtime trace trace occurs Description When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer Trace continue full This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed
10. bus clock Waited cycles for WRQ request The cycles for an issued request req that no acceptance signal gnt is issued to are counted by the system bus clock Even if the waits are issued simultaneously for multiple requests they are counted as 1 Waited cycles for WRS response RENESAS The cycles for an issued response r_req that no acceptance signal r_gnt is issued to are counted by the system bus clock Even if the waits are issued simultaneously for multiple requests they are counted as 1 45 Table 2 13 shows the measurement items and methods that are mainly used Table 2 13 Main Measurement Items Main Measurement Item Elapsed time Measurement Method Number of elapsed cycles x CPU clock cycles Number of execution instructions Number of valid instructions issued number of cases of simultaneous execution of two instructions Number of interrupts accepted Number of exceptions accepted Number of instruction fetches for both cache and non cache Number of memory accesses in an opcode Instruction cache hit ratio Number of instruction cache accesses instruction cache miss counts instruction cache access counts Number of operand accesses for both cache and non cache Number of memory accesses in an operand read number of memory accesses in an operand write Operand cache hit ratio read Number of operand cache accesses read
11. control registers as shown in table 2 1 The initial values of the actual SH7763 registers are undefined When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H A0000000 RO BANK to R7 BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 DBR H 00000000 SGR H 00000000 SPC H 00000000 SSR 000000 0 FPUL H 00000000 FPSCR H 00040001 FRO to FR15 H 00000000 XFO to XF15 H 00000000 2 The emulator uses the H UDI do not access the H UDI RENESAS 3 Low Power States Sleep Software Standby and Module Standby For low power consumption the SH7763 has sleep software standby and module standby states The sleep software standby and module standby states are switched using the SLEEP instruction When the emulator is used the sleep state can be cleared with either the normal clearing function or with the STOP button and a break will occur Note The memory must not be accessed or modified in sleep state 4 Reset Signals The SH7763 reset signals are only valid during emulation started with clicking the GO or STEP type button If these signals are enabled on the user system in command input wait state they are not sent to the SH7763 Note Do not
12. have been set in the Event Condition dialog box that is opened by double clicking Ch1 to Ch6 and Ch8 to Ch12 on the Event Condition sheet of the Eventpoint window 37 RENESAS Notes 1 When no measurement start end conditions are specified measurement is started by executing a program and ended when an event condition is satisfied When only the measurement start or end condition is specified performance cannot be measured Be sure to specify both of the measurement start and end conditions When the measurement start end conditions are specified step operation cannot be performed Table 2 11 Conditions Specified in the Action Page Item Description PA1 pal1 start point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 1 1 end point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 1 PA2 2 start point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 2 pa2 end point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 2 PA3 pa3_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 3 pa3_end_point Specifies the conditions of Event Condition that has been s
13. instruction fetch exceptions generated by an instruction fetch number of EXPEVT sets Number of UTLB miss UMO The number of TLB miss for operand fetch exceptions generated by an operand access number of EXPEVT sets Number of ITLB miss IM The number of ITLB misses for valid accesses does not include UTLB hits or misses Instruction bus Instruction Number of memory MIF The number of memory performance accesses for accesses by an instruction instruction fetch fetch Accesses canceled by an instruction fetch bus are not counted Instruction fetches which have been fetched in anticipation of a branch but not actually executed are counted Accesses by the PREFI instruction are included Number of instruction The number of accesses for cache access an instruction cache during memory access of the opcode 42 RENESAS Table 2 12 Measurement Items cont Classification Type Measurement Item Option Note Instruction bus Instruction Number of ICM The number of cache misses performance cont instruction cache by an instruction cache access cont miss the number of accesses to the outside of the CPU core due to a cache miss Number of internal XL The number of accesses for RAM access for the XY or L memory in the instruction fetch XY SH7763 during memory RAM or L memory accesses of the opcode Operand bus Access Number of memory MR The number of memory performance count access for operand accesses by an operan
14. is set the next lowest even address is used 34 A BREAKPOINT is accomplished by replacing instructions of the specified address Accordingly it can be set only to the RAM areas in CSO to CS6 However a BREAKPOINT cannot be set to the following addresses e ROM areas in CSO to CS6 e Areas other than CSO to CS6 e Areas other than the internal RAM e A slot instruction of a delayed branch instruction e An area that can be only read by MMU During step operation BREAKPOINTs are disabled When execution resumes from the address where a BREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction When the Normal option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address or a virtual address according to the SH7763 MMU status during command input when the VPMAP_SET command setting is disabled The ASID value of the SH7763 PTEH register during command input is used When VPMAP_SET command setting is enabled a BREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table However for addresses out of the ran
15. number of operand cache misses read number of operand cache accesses read Operand cache hit ratio write Number of operand cache accesses write number of operand cache misses write number of operand cache accesses write Operand cache hit ratio Number of operand cache accesses read number of operand cache accesses write number of operand cache misses read number of operand cache misses write number of operand cache accesses read number of operand cache accesses write System bus occupied rate of request bus The equivalent CPU clock value of the number of requests number of elapsed cycles System bus occupied rate of response bus 46 The equivalent CPU clock value of the number of responses number of elapsed cycles RENESAS Each measurement condition is also counted when conditions in table 2 14 are generated Table 2 14 Performance Measurement Conditions to be Counted Measurement Condition Notes No caching due to the Counted for accessing the cacheable area settings of TLB cacheable bit Cache on counting Accessing the non cacheable area is counted less than the actual number of cycles and counts Accessing the cacheable X Y RAM and U RAM areas is counted more than the actual number of cycles and counts Branch count The counter value is incremented by 2 This means that two cycles are valid for one branch Notes 1 In the non realtime
16. 2H 36 pin connector Available HS0005KCUO1H HS0005KCUO02H 14 pin connector Not available The H UDI port connector has the 36 pin and 14 pin types as described below Use them according to the purpose of the usage 1 36 pin type with AUD function The AUD trace function is supported A large amount of trace information can be acquired in realtime The window trace function is also supported for acquiring memory access in the specified range memory access address or memory access data by tracing 2 14 pin type without AUD function The AUD trace function cannot be used because only the H UDI function is supported For tracing only the internal trace function is supported Since the 14 pin type connector is smaller than the 36 pin type 1 2 5 the area where the connector is installed on the user system can be reduced RENESAS 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 36 pin connector DX10M 36S Hirose Electric Co Ltd Screw type DX10M 36SE Lock pin type DX10G1M 36SE 14 pin connector 2514 6002 Minnesota Mining amp 14 pin straight type Manufacturing Ltd Note When designing the 36 pin connector layout on the user board do not connect any components under the H UDI connector When designing the 14 pin connector layout on the user board
17. 4 7 or more VecQ VccQ H UDI port connector 36 pin type SH7763 AUDCK 1 AUDATAO AUDATAO AUDATA1 AUDATA1 AUDATA2 AUDATA3 AUDSYNC TDO _ASEBRK M BRKACK ASEBRK BRKACK UVCC _RESET PRESET MPMD User system Figure 1 3 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type RENESAS Note This emulator does not support backup of the RTC power supply in the low power consumption mode When using the emulator the RTCSTB pin must be fixed at high level RENESAS 1 5 2 Recommended Circuit 14 Pin Type Figure 1 4 shows a recommended circuit for connection between the H UDI and AUD port connectors 14 pins and the MPU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used MPMD 0 2 When the emulator is not used MPMD 1 Figure 1 4 shows an example of circuits that allow the MPMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the MPMD pin is changed by switches etc ground pin 9 Do not connect this pin to the MPMD pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU m
18. Circuit between the H UDI Port Connector and the MPU 6 1 5 1 Recommended Circuit 36 Pin 6 1 5 2 Recommended Circuit 14 Pin 9 Section 2 Software Specifications when Using the SH7763 11 2 1 Differences between the SH7763 and the 11 2 2 Specific Functions for the Emulator when Using the 5 7763 16 2 2 1 Event Condition Functions 16 2 4 2 Puncttonss s sees sees cots iem rye ie epo rene vr ERE teen 24 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK 34 2 2 4 Notes on Setting the Breakpoint Dialog Box se 34 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION SET Command eee 35 2 2 6 Note on Setting the MODE 36 2 2 Note on Setting MODE 36 2 2 8 Performance Measurement Function essen 36 13 NC SAS 13 NE SAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box HS0005KCUO1H ware Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCUO2H De
19. OINT is set is determined when the BREAKPOINT is set Accordingly even if the VP_MAP table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a BREAKPOINT is satisfied with the modified address in the VP_MAP table the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT 10 If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the event condition the mark disappears 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION SET Command 1 When Go to cursor Step In Step Over or Step Out is selected the settings of Event Condition 3 are disabled 2 When an Event Condition is satisfied emulation may stop after two or more instructions have been executed 3 If a PC break address condition is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destination instruction 35 RENESAS 2 2 6 Note on Setting the UBC MODE Command In the Configuration dialog box if User is set while the UBC mode list box has been set Ch10
20. REJ10J1148 0100 Everywhere you imagine g 2 NESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7763 Renesas Microcomputer Development Environment System SuperH Family E10A USB for SH7763 HS7763KCUO1HE Rev 1 00 R Technol Revision Date Nov 02 2005 wwwreneses oom Keep safety first in your circuit designs Renesas Technology Corp puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corp or a third party Renesas Technology Corp assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algori
21. Sequential Extend page Sequential The sequential setting is enabled with any Event Page combination cont For details refer to section 2 2 1 Sequential Break Extension Setting in this manual SystemBus SystemBus Ch9 gt 8 Halts a program when a condition is satisfied for Sequential Sequential Event Condition 9 8 Event Page Event An event condition must be set for Ch9 and Ch8 Ch8 gt 9 Halts a program when a condition is satisfied for Event Condition 8 9 An event condition must be set for Ch8 and Ch9 SystemBus Expands the SystemBus Sequential Extend page Extend The sequential setting is enabled with any combination For details refer to section 2 2 1 Sequential Break Extension Setting in this manual 20 RENESAS Sequential Break Extension Setting Sequential setting CPU Sequential Event SystemBus Sequential Event CPU Sequential Extend Chi A OA PreHit Channel Ch2XIA OA DT CT CPU Match flag Match flag set gt 1 OCh2 IA OA PreHit Channel Select CPU Match flag Se Ch31A PreHit Channel Select hi CPU Match flag No Se PreHit Channel Match flag z CPU Match flag Match flag set gt 0 7 Ch5COA PreHit Channel Select CPU Match flag Se CH6COA PreHit Channel Select CPU Match flag PreHit Channel Ch4 1A CPU Match flag Ch11 A OA DT CT R PreHit Channel No Se CPU Match flag Chl 2 Branch Pr
22. ation when a condition such as setting a break trace or performance start or end is matched Table 2 5 lists the combinations of conditions that can be set under Ch1 to Ch12 and the software trace 16 RENESAS Table 2 5 Dialog Boxes for Setting Event Conditions Function Bus Window Address Data State Address Branch Bus Bus ASID Condition Condition LDTLB Count Condition Dialog Condition Condition Condition Bus Window System Instruction Condition Branch Software Box Address Data ASID Status address Bus Break Count Trace Trace Action Event X X X X X X X Condition B and 1 dialog P box Event X X X X X Condition B and 2 dialog P box Event X X X X X X X X Condition B and 3 dialog P box Event X X X X X X X X Condition B and 4 dialog P box Event X X X X X X X Condition B T 5 dialog and P box Event X X X X X X X Condition B T 6 dialog and P box Event X X X X X X X X X Break Condition fixed 7 dialog box Event X X X X X X X X Condition B T 8 dialog and P box 17 RENESAS Table 2 5 Dialog Boxes for Setting Event Conditions cont Function Bus Window Address Data State Address Branch Bus Bus ASID Condition Condition LDTLB Count Condition Dialog Condition Condition Condition Bus Window System Instruction Condition Branch Software Box Address Data
23. break the user program when the RESET or BREQ signal is being low and the 5 WAIT control signal is being active A TIMEOUT error will occur If the WAIT control signal and the BREQ signal are fixed to active and low during break respectively a TIMEOUT error will occur at memory access Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer Memory Access during User Program Execution When a memory is accessed from the memory window etc during user program execution the user program is resumed after it has stopped in the E10A USB emulator to access the memory Therefore realtime emulation cannot be performed The stopping time of the user program is as follows Environment Host computer 800 MHz Pentium SH7763 400 MHz CPU clock JTAG clock 10 MHz TCK clock When a one byte memory is read from the command line window the stopping time will be about 38 ms Memory Access during User Program Break The emulator can download the program for the flash memory area for details refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family E10A USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area RENESAS 8 Cache Operation during User Program Break When ca
24. che is enabled the emulator accesses the memory by the following methods e Atmemory write Writes through the cache then issues a single write to outside The LRU is not updated e Atmemory read Reads memory from the cache The LRU is not updated Therefore when memory read or write is performed during user program break the cache state does not change e At breakpoint set Disables the instruction cache Port The AUD pin is multiplexed as shown in table 2 2 Table 2 2 Multiplexd Functions Function 1 Function 2 PortO PTO5 DREQ1M SSI3_SDATAIO AUDCK PTO4 _EX_INT SSI3_WS AUDATAS PTOS RMIIOM1 MDIO SSI2 SCK AUDATA2 PTO2 RMIIOM1 MDC SSI2 SDATAI AUDATA1 PTO1 RMIIM MDIO SSI2 SDATAIO AUDATAO PTOO RMIHM MDC SSI2 WS AUDSYNC Note Function 1 can be used when the AUD pins of the device are not connected to the emulator When the AUD trace is enabled the emulator changes settings so that function 2 is forcibly used 10 Backup of the RTC Power Supply 11 This emulator does not support backup of the RTC power supply in the low power consumption mode When using the emulator the RTCSTB pin must be fixed at high level UBC When User is specified in the UBC mode list box in the Configuration dialog box the UBC can be used in the user program Do not use the UBC in the user program as it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box RENESAS
25. d by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2005 Renesas Technology Corp All rights reserved Printed in Japan Renesas Tech nology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan 2CENESAS RENESAS SALES OFFICES Refer to http www renesas com en network for the latest and detailed information http www renesas com Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel 1 408 382 7500 Fax 1 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH United Kingdom Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Technology Shanghai Co Ltd Unit2607 Ruijing Building No 205 Maoming Road S Shanghai 200020 China Tel 86 21 6472 1001 Fax 86 21 6415 2952 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Technology Korea Co Ltd Kukje Center Bldg
26. d read fetch READ equal to loading on the operand bus Accesses by the PREF instruction or canceled accesses are not included Number of memory MW access for operand fetch WRITE The number of memory accesses by an operand write equal to storing memory on the operand bus Canceled accesses are not included Number of operand CR cache access READ The number of operand cache reads during memory access read of an operand Number of operand CW cache access WRITE The number of operand cache reads during memory access write of an operand Number of internal XLR RAM access for operand fetch READ XY RAM or L memory RENESAS The number of accesses to XY or L memory in the SH7763 during memory access read of an operand Accesses via the XY bus and the operand bus are included When MOVX and MOVY are executed simultaneously it increments one count regardless of the read or write 43 Table 2 12 Measurement Items cont Classification Operand bus performance cont 44 Type Measurement Item Option Note Access Number of internal XLW The number of accesses to XY count cont RAM access for or L memory in the SH7763 operand fetch during memory access write WRITE XY RAM of an operand or L memory Accesses via the XY bus and the operand bus are included When MOVX and MOVY are executed simultaneously it increments one count regardl
27. e not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corp is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corp for further details on these materials or the products contained therein Contents Section 1 Connecting the Emulator with the User System 1 11 Components of the Emulator sese 1 1 2 Connecting the Emulator with the User System seen 2 1 3 Installing the H UDI Port Connector on the User System 2 2 421 3 1 4 Pin Assignments of H UDI Port eene 3 1 5 Recommended
28. eHit Channel Se Figure 2 1 CPU Sequential Extend Page a Indicates the channel name for setting conditions b Selects a condition that is satisfied before the channel which sets up conditions When a channel name is selected it is required that the condition of the channel selected here must have already been satisfied When CPU Match flag is selected the CPU match flag must be set When a condition is selected by the channel selected here no break will occur c When a condition is satisfied the CPU match flag is set or cleared When a program breaks the CPU match flag is initialized Set the event condition for each channel in the Event Condition dialog box this also applies to the System Bus Sequential Extend page 21 RENESAS Usage Example of Sequential Break Extension Setting A tutorial program provided for the product is used as an example For the tutorial program refer to section 6 Tutorial in the SuperH Family EIOA USB Emulator User s Manual The conditions of Event Condition are set as follows 1 5 Chl Breaks address H 00001068 when the condition Prefetch address break after executing is satisfied Ch2 Breaks address H 00001058 when the condition Prefetch address break after executing is satisfied Ch4 Breaks address H 0000107a when the condition Prefetch address break after executing is satisfied Ch10 Breaks address H 00001086 when the condition Prefetch addres
29. en a specific instruction is executed the PC value at execution and the contents of one general register are acquired by trace Describe the Trace x function x is a variable name to be compiled and linked beforehand For details refer to the SuperH RISC engine C C Compiler Assembler Optimizing Linkage Editor User s Manual When the load module is downloaded on the emulator and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed To activate the software trace function select the Acquire Software trace radio button in the Software trace dialog box that is opened by double clicking on the software Trace column of the Eventpoint window Note To cancel settings select the Don t care radio button in the Software trace dialog box or select Delete from the popup menu that is opened by clicking on the software Trace column with the right mouse button Internal Trace Function This function is activated by selecting the Internal trace radio button in the Trace type group box of the Trace mode page Set the trace condition to be used Notes 1 If an interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displayed Ignore this address because it is not a user program address 2 If
30. en newly output branch source addresses and previously output branch source addresses The window trace function outputs the differences between newly output addresses and previously output addresses If the previously output address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address If the 32 bit address cannot be displayed the source line is not displayed In the emulator when multiple loops are performed to reduce the number of AUD trace displays only the IP counts up In the emulator the maximum number of trace displays is 65534 lines 32767 branches However the maximum number of trace displays differs according to the AUD trace information to be output Therefore the above pointers cannot be always acquired The AUD trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 31 ENESAS Memory Output Trace Functions This funct
31. ess of the read or write Access Number of operand CMR The number of cache misses miss count cache miss READ by an operand cache access read number of accesses to the outside of the CPU core due to a cache miss Cache misses are not counted by the PREF instruction Number of operand CMW The number of cache misses cache miss WRITE by an operand cache access write number of accesses to the outside of the CPU core due to a cache miss Write through accesses are not counted Cache misses are not counted by the PREF instruction Waited Waited cycles for WOR The number of wait cycles by a cycle operand fetch memory access read of an READ operand Waited cycles for WOW The number of wait cycles by a operand fetch memory access write of an WRITE operand Waited cycles for WCMR The number of wait cycles by operand cache miss an operand cache miss read READ however the number of wait cycles of cache is included due to contention Waited cycles for WCMW The number of wait cycles by operand cache miss WRITE RENESAS an operand cache miss write Table 2 12 Measurement Items cont Classification Type System bus System bus performance only available for Ch3 and Ch4 Measurement Item Option Number of requests RQ Note The number of valid bus cycles cells is counted by the system bus clock Number of RS responses The number of valid bus cycles cells is counted by the system
32. et as the measurement end condition of performance channel 3 PA4 pa4_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 4 pa4_end_point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 4 38 RENESAS Event condition 1 Address ASID Bus State Action 6 pal start point C pal end point 25 3 Figure 2 9 Action Page Note or PA2 cannot be set for Ch8 and Ch9 39 RENESAS b Measurement tolerance e The measured value includes tolerance e Tolerance will be generated before or after a break For details see table 2 14 c Measurement items 40 Items are measured in the Performance Analysis dialog box for each channel from Chl to Ch4 A maximum of four conditions can be specified at the same time Table 2 12 shows the measurement items Options in table 2 12 are parameters for mode of the PERFORMANCE SET command They are displayed in CONDITION of the Performance Analysis window RENESAS Table 2 12 Measurement Items Classification Type Measurement Item Option Note Disabled None Not measured CPU Cycle Elapsed cycles AC Except for power on period performance counted by the CPU clock Cycles executed in PM The number of privileged privileged mode mode cycles among the number of elapsed cycles Cycles for asserting T
33. ge of the VP_MAP table the address to which a RENESAS BREAKPOINT is set depends on the SH7763 MMU status during command input Even when the VP_MAP table is modified after BREAKPOINT setting the address translated when the BREAKPOINT is set valid 7 When the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address A BREAKPOINT is set after disabling the SH7763 MMU upon program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT 8 When the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the SH7763 MMU upon program execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input 9 An address physical address to which a BREAKP
34. hat allow the MPMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the MPMD pin is changed by switches etc ground pin 22 Do not connect this pin to the MPMD pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board The AUD signals AUDCK AUDATA3 to AUDATAO and AUDSYNC operate in high speed Isometric connection is needed if possible Do not separate connection nor connect other signal lines adjacently Supply only the VccQ voltage to the UVCC pin because the H UDI and AUD of the MPU operate at the VccQ voltage I O power supply Make the emulator s switch settings so that the user power will be supplied SW2 1 and SW3 1 The resistance values shown in figure 1 3 are preliminary For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU For the AUDCK pin guard the pattern between the H UDI port connector and the MPU at GND level RENESAS When the circuit is connected as shown in figure 1 3 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family E10A USB Emulator User s Manual VccQ I O power supply All pulled up at
35. he number of cycles when the SR BL bit the SR BL bit 1 among the number of elapsed cycles Instruction Number of effective The number of execution instructions issued instructions number of valid instructions issued number of cases of simultaneous execution of two instructions The number of valid instructions means the number of completed instructions Number of 2 21 number of times that two instruction executed instructions are executed simultaneously simultaneously among the valid instructions issued Branch Number of BT The number of unconditional unconditional branch branches other than branches occurring after an exception However RTE is counted Exception Number of EA Interrupts are included interruption exceptions accepted Number of interrupts accepted NMI is included Number of UBC channel hit UBC RENESAS Performs OR to count the number of channel hits in the CPU 41 Table 2 12 Measurement Items cont Classification Type Measurement Item Option Note CPU Stalled Cycles stalled in full SFM All items are counted performance cycle trace mode with independently cont multi counts Cycles stalled in full SF This item is not counted if the trace mode without stall cycle is generated multi counts simultaneously with a stall cycle that has occurred due to instruction execution TLB TLB Number of UTLB miss UMI The number of TLB miss performance for
36. ion is activated by selecting the Use Memory trace radio button in the Trace type group box of the Trace mode page In this function write the trace data in the specified user memory range Specify the start address to output a trace for the Start edit box in the User memory area group box and the end address for the End Address edit box Set the trace condition to be used Table 2 10 shows the memory output trace acquisition mode that can be set in each trace function Table 2 10 Memory Output Trace Acquisition Mode Type Continuous trace occurs Mode Realtime trace Description When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer full 32 Trace continue This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed RENESAS To set the memory output trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the
37. le 2 8 shows the type numbers that the AUD function can be used Table 2 8 Type Number and AUD Function Type Number AUD Function HS0005KCUO1H Not supported HS0005KCUO2H Supported 24 RENESAS Branch Trace Functions The branch source and destination addresses their source lines branch types and types of accessed bus masters are displayed Setting Method Select the check box in the Branch group box in the Branch trace page of the Branch trace dialog box that opens by double clicking on the Ch12 Branch column of the Eventpoint window The branch condition to be acquired can be set Branch trace Branch trace Action Branch Dont care Acquire subroutine branch instruction trace Acquire exception branch instruction trace Figure 2 3 Branch trace Dialog Box A branch trace can be acquired by selecting the Acquire trace check box of the Action page Note To cancel settings select Delete from the popup menu that is opened by clicking on the Ch12 Branch column with the right mouse button 25 RENESAS Range Memory Access Trace Functions The memory access within the specified range is acquired by a trace The read cycle write cycle or read write cycle can be selected as the bus type ASID value or bus cycle for trace acquisition Setting Method To open the Event condition 5 or Event condition 6 dialog box double click on the Ch5 OA or Ch6 OA column of the
38. on must be set for Ch11 and Ch10 Many Channel Sequential Ch3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 3 2 1 An event condition must be set for Ch3 Ch2 and Ch1 Ch4 gt 3 2 2 gt 1 Halts program when condition is satisfied in the order of Event Condition 4 3 2 1 An event condition must be set for Ch4 Ch3 Ch2 and Ch1 Ch5 gt 4 gt 3 gt 2 gt 1 Halts program when condition is satisfied in the order of Event Condition 5 4 3 2 1 An event condition must be set for Ch5 Ch4 Ch3 Ch2 and Ch1 Ch6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts program when a condition is satisfied in the order of Event Condition 6 5 4 3 2 1 An event condition must be set for Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 Ch10 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 10 6 5 4 3 2 1 An event condition must be set for Ch10 Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 Ch11 gt 10 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 11 10 6 5 4 3 2 1 An event condition must be set for Ch11 Ch10 Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 19 RENESAS Table 2 6 Sequential Event Conditions cont Type Event Condition Description CPU CPU Extend Expands the CPU
39. pth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g User system interface 1 14 pin type cable Length 20 cm Mass 33 1 g User system interface 1 36 pin type cable 4 Length 20 cm Mass 49 2 g only for HS0005KCUO2H USB cable 1 Length 150 cm Mass 50 6 g Soft E10A USB emulator setup 1 HS0005KCUO18SR ware program C e SuperH Family E10A HS0005KCUO1HJ USB Emulator User s HS0005KCUO1HE Manual Supplementary HS7763KCUO01HJ Information on Using the HS7763KCU01HE SH7763 and Test program manual for HS0005KCUO1H and HS0005KCUO2H 50005 01 and HS0005TMO1HE provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the target MPU and refer to its additional document RENESAS 1 2 Connecting the Emulator with the User System To connect the E10A USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to an example of recommended connection between the connector and the MPU shown in this manual In addition read the E10A USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCUO
40. s break after executing is satisfied Note Do not set other channels Set the CPU Sequential Extend page as shown in figure 2 1 Then set the program counter and stack pointer PC H 00000800 R15 H 00010000 in the Registers window and click the Go button If this does not execute normally issue a reset and execute the above procedures The program is executed up to the condition of Ch10 and halted Here the condition is satisfied in the order of Ch2 gt 1 gt 4 gt 10 22 RENESAS 1 0 00001058 alil 0 00001068 p_sam gt sort a 0 00001070 p_sam gt change a 0 00001076 _ gt 0 01 0 0000107 p_sam gt sl aL1 0 0000107 _ gt 2 2 1 0 00001082 _ gt 2 3 1 0 00001086 _ gt 4 4 1 0x0000108a p_sam gt s5 aL5 0 0000108 _ gt 6 6 0 00001092 _ gt 7 7 1 0 00001096 p_sam gt s8 aL8 0x0000109a p_sam gt s9 aL9 0 0000109 delete p sam Figure 2 2 Source Window at Execution Halted Sequential Break 23 RENESAS 2 2 2 Trace Functions The emulator supports the trace functions listed in table 2 7 Table 2 7 Trace Functions Memory Output Function Internal Trace AUD Trace Trace Branch trace Supported eight branches Supported Supported Range memory access trace Supported eight events Supported Supported Software trace Supported eight events Supported Supported Tab
41. ted Do not change the value of the frequency change register in the IO window or Memory window e The internal I O registers can be accessed from the IO window However note the following when accessing the SDMR register of the bus state controller Before accessing the SDMR register specify addresses to be accessed in the I O register definition file SH7763 IO and then activate the High performance Embedded Workshop After the I O register definition file is created the MPU s specifications may be changed If each I O register in the I O register definition file differs from addresses described in the hardware manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format Note that however the emulator does not support the bit field function RENESAS e Verify In the IO window the verify function of the input value is disabled 15 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter 16 Reset CPU and Reset Go in the Debug Menu When a reset is issued from Reset CPU or Reset Go in the Debug menu the clock pulse generator or watchdog timer is not initialized RENESAS 2 2 Specific Functions for the Emulator when Using the SH7763 2 2 1 Event Condition Functions The emulator is used to set 12 event conditions Ch1
42. thms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corp without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corp semiconductors ar
43. to Ch12 and the software trace Table 2 4 lists the conditions of Event Condition Table 2 4 Types of Event Conditions Event Condition Type Address bus condition Address Description Breaks when the SH7763 address bus value or the program counter value matches the specified value Data bus condition Data Breaks when the SH7763 data bus value matches the specified value Byte word or longword can be specified as the access data size Bus state condition Bus State There are two bus state condition settings Bus state condition Breaks or acquires a trace when the data bus or the X Bus or Y Bus address bus of the SH7763 is matched Read Write condition Breaks or acquires a trace when the specified read write condition is matched Window address condition Breaks or acquires a trace when the data in the specified memory range is accessed System bus Breaks or acquires a trace when the address or data on the system bus is matched LDTLB instruction event condition Breaks when the SH7763 executes the LDTLB instruction Count Breaks when the conditions set are satisfied the specified number of times Branch trace condition Branch trace Breaks or acquires a trace when a branch occurs with the condition specified by the SH7763 By default trace acquisition is enabled Software trace Selects whether or not the software trace is acquired Action Selects the oper
44. tor 36 Pins RENESAS Input SH7763 Pin No Signal Output PinNo Note TCK nput AE19 _TRST nput AC19 TDO Output AB20 _ASEBRK nput AD19 BRKACK output TMS nput AC21 TDI nput AC20 _RESET Output AE16 User reset N C GND UVCC Output GND m GND 8 Output Input to or output from the user system The symbol means that the signal is active low The emulator monitors the GND signal of the user System and detects whether or not the user system is connected When the user system interface cable is connected to this pin and the MPMD pin is set to 0 do not connect to GND but to the MPMD pin directly Pin 1 mark H UDI port connector top view TIERE id H UDI port connector 23 0 6x 2 54 15 24 top view Pin 1 mark Figure 1 2 Pin Assignments of the H UDI Port Connector 14 Pins RENESAS 1 5 1 5 1 Recommended Circuit between the H UDI Port Connector and the MPU Recommended Circuit 36 Pin Type Figure 1 3 shows a recommended circuit for connection between the H UDI and AUD port connectors 36 pins and the MPU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used MPMD 0 2 When the emulator is not used MPMD 1 Figure 1 3 shows an example of circuits t
45. trace mode of the AUD trace and memory output trace normal counting cannot be performed because the generation state of the stall or the execution cycle is changed 2 Since the clock source of the counter is the CPU clock counting also stops when the clock halts in the sleep mode d Extension setting of the performance result storing counter The 32 bit counter stores the result of performance and two counters can be used as a 64 bit counter To set a 64 bit counter check the Enable check box in the Extend counter group box of the Performance Analysis dialog box for Ch and Ch3 2 Displaying the result of performance The result of performance is displayed in the Performance Analysis window or the PERFORMANCE ANALYSIS command in hexadecimal 32 bits However when the extension counter is enabled it is displayed in hexadecimal 64 bits Note Ifa performance counter overflows as a result of measurement will be displayed for upper bits 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE ANALYSIS command 47 RENESAS 48 RENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7763 Publication Date Rev 1 00 November 2 2005 Published by Sales Strategic Planning Div Renesas Technology Corp Edite
46. ust be as short as possible Do not connect the signal lines to other components on the board Supply only the VccQ voltage to the UVCC pin because the H UDI of the MPU operates at the VccQ voltage I O power supply Make the emulator s switch settings so that the user power will be supplied SW2 1 and SW3 1 The resistance values shown in figure 1 4 are preliminary For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU RENESAS When the circuit is connected as shown in figure 1 4 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family E10A USB Emulator User s Manual VccQ I O power supply All pulled up at 4 7 kQ or more VccQ VccQ VccQ VccQ H UDI port connector 14 pin type SH7763 _TRST TDO _ASEBRK BRKACK TMS Reset signal User system Figure 1 4 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type Note This emulator does not support backup of the RTC power supply in the low power consumption mode When using the emulator the RTCSTB pin must be fixed at high level 10 RENESAS Section 2 Software Specifications when Using the SH7763 2 1 Differences between the SH7763 and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the
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