48-bit Channel Link Serializer Deserializer
Contents
1. On board transmitter LVCMOS LVTTL input termination resistors R1 R25 onnector ermination CU RT Pe 3 Re RS R Re Re Oy OF U U U U U U U U O af S rol pol N N ol Al al op si ol ol ol a po wl Zz g 2 Ol in 36 in 46 81 84 88 8 3j 93 o2 58 54 a Nl ol Ala I 25 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Receiver LVDS Input Termination The DS90CR486 Receiver has nine total LVDS input pairs eight pairs of data and one pair of clock Impedance and lengths are matched on all nine pairs and between each pair to reduce reflection and board skew See MDR Connector under Connector Mapping Tables on page 22 for detail on receiver s inputs signal mapping A 100 Ohm differential termination resistor is provided on each input pair R92 R100 near the receiver s device pins to generate proper differential voltage and minimize stub length See below figure for simply circuit schematic and mapping for resistor and its corresponding signal LVDS termination is required in all applications Parallel Output Load NS90CR486 7 NAME Resistor RINM RxINP 9 PRN RxINM 9 RxCL 9 nn R rips r RxINM 9 RxIN 9 Rane Fes RxIN R100 Device Pin A TENN Ui DO DM od oO B amp B BI w OD I om rms A L3 Z T x2. T iU Js ose ENABLED Eg 8 ENABLED uw o 66 Mhz 133 MHz OPEN Externol Clock 9 1 CLKIN 023 022 INPUT VOLTAGE ed 2C 33v 485 TX PART CLINK3V488T 133 i 498222222222222222222223233 33232333988 38052003 2 Semiconductor The Sight amp Sound of Information GLINK 3V 485 486 PCB REV I WIRED COMMUNICATIONS 9982 9298823322223383 Spi HEBHHO HE H SIE WAV N VEE 486 RX L3 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2222222222222222222222222 gt gt LA 10 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Overview The CLINK3V48BT 133 evaluation kit is configured using switches SW1 SW3 and jumpers J6 J12 The DS90CR485 Transmitter and DS90CR485 Receiver parallel LVCMOS LVTTL data buses and clocks are accessed through the 50 pin IDC connectors J1 J3 The transmitter clock can be applied through the 50 pin IDC connector or one of the two on board oscillators can be selected The high speed serialized LVDS data plus the LVDS clock is transmitted and received through 3M D26 1 MDR connectors J4 and J5 The evaluation board has two power planes 2 5V for the Transmitter and 3 3V for the Receiver Power and ground are supplied through connectors J13 J16 The Transmitter inputs can be made 3V input tolera
3. O z I 5 DEVICE ENABLED SW2 National Semiconductor The Sight amp Sound of Information Receiver Configuration Control NA in BOARD LABEL NAME RE START DESKEW DESKEW DEFAULT in3 DC BAL OFF BAL ac in4 JCON1 HIGH TU I v 2 a VU VU I 5 a I 5 o I 5 zj PWR DOWN DEVICE ENABLED SW3 I 5 DS_OPT RE c3v TURN OFF 133MH Oscillator Control OSCILLATOR Tran nfigurati TSEN LVDS Clock Termination Receiver s Configuration Detec Output Tran nfigurati Cable Deskew Option smitter Co TURN OFF 66MH Oscillator Control OSCILLATOR on Selection of CLKIN source Transmitter s Clock Select Pre Emphasis Selec smitter o on S Input ter s Input Ve Transmitter s Input Tolerant Transmitter s Power Pin Select 23 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information On Board Termination Resistors 24 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Transmitter LVCMOS LVTTL Data Input Termination Resistors An on board 50 Ohm termination resistor to ground is provided at each transmitter LVCMOS LVTTL clock and data input to match standard 50 Ohm test environments In a real application these series termination resistors are optional fX E Parallel Data DS90CR485 Clock source RM
4. PCB Bill of Material Document number CLINK3V485 486 BOM Rev 1 02 PCB Layouts Rev 1 Cable amp Connector Info Crystal Oscillator Info 31 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Other Resources For more information on Channel Link devices refer to the National s LVDS website at LVDS national com Interface Application Hotline 1 408 721 8500 California USA National Semiconductor 2003 National Semiconductor and the N logo are registered trademarks of National Semiconductor Corporation All other brand or product names are trademarks of their respective owners All rights reserved 32 of 32 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent T
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6. Sight amp Sound of Information Pin amp Signal Assignments 20 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information The following tables show signal mapping for IDC connectors MDR connectors switches and jumpers IDC Connector Note All odd number pins in the IDC connectors are grounded GND Transmitter Parallel Inputs Receiver Parallel Outputs Receiver Parallel Outputs 7 n2 in 4 2 in 6 2 ind in 10 2 12 nid inte nie i20 in 22 1 in 24 1 m 25 n in 30 1 n3 v9 ne 08 36 ns 5e mo 55 na 04 ma 23 na 9 ne no 0 J1 in NAM RxCLKOU RXOUT4 RXOUT4 RXOUT4 RXOUT4 RXOUT4 RXOUT4 RXOUT4 RXOUT4 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT3 RXOUT2 RXOUT2 RXOUT2 RXOUT2 RXOUT2 RXOUT2 in in2 in4 in6 in 8 in 10 in 12 in 14 in 16 in 18 in 20 in 22 in 24 in 26 in 28 in 30 in 32 in 34 in 36 in 38 in 40 in 42 in 44 in 46 in 48 in 50 NAM RXOUT2 RXOUT2 RXOUT2 RXOUT2 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT1 RXOUT RXOUT RXOUT RXOUT RXOUT RXOUT RXOUT RXOUT RXOUT RXOUT in 4 in 6 in 8 in 10 in 12 in 14 in 16 in 18 in 20 in 22 in 24 in 26 in 28 in 30 in 32 in 34 in 36 in 38 in 40 in 42 in 44 in 46 in 48 in 50 pnr BS O z 21 of 32 DS90CR485 486 E
7. a 2K Ohm potentiometer R42 can be adjusted using a jeweler s screwdriver to increase or decrease pre emphasis Turning clockwise increases pre emphasis turning counterclockwise decreases pre emphasis 18 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Transmitter PRBS Generator Mode The DS90CR485 transmitter is equipped with an internal test pattern generator that can be used to check signal quality eye patterns on the link To enable this test mode select PRBS ENABLE from the switch block SW2 and choose either the PRBS 15 or the PRBS 23 pattern Designator Settings SW2 LVDS Cable Sense TSEN Status Flag The TSEN pin reports the presence of a remote termination resistor on the LVDS clock line The user may monitor the status of the TSEN pin through jumper J9 When TSEN is HIGH a termination resistor of approximately 100 Ohms has been detected When TSEN is LOW no termination has been detected The TSEN status flag provides a gross detect function meaning it is meant check whether a cable or other interconnect is present between the transmitter and receiver A high signal on the TSEN line does not guarantee the termination is correct or the link is capable of carrying data without bit errors See the DS90CR485 datasheet for more detail on the TSEN pin 19 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The
8. s best to start with one data bit to the Tx Switches and Jumpers are set correctly or to default settings The 2 meter cable is connecting the Tx portion and Rx portion Make sure all of the connections are good Start with a low clock frequency 66 MHz and work from there Problem Solution There is only the output clock There is no output data Make sure the data scramble mapping is correct Make sure there is data input No output data and clock Make sure Power is on Input data and clock are active and connected correctly Make sure that the 2 meter cable is secured to both demo boards Power ground input data and input clock are connected correctly but no outputs Check the Power Down pins of both boards and make sure the devices are enabled PD ON for operation The devices are pulling more than 1A of current Check for shorts on the demo boards After powering up the demo boards the power supply reads less than 3V when it is set to 2 3 V Use a larger power supply that will provide enough current for the demo boards 29 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Additional Information 30 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information PCB Schematic Document number CLINK3V485 486 PCB Rev 1 01
9. 26 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Optional Receiver LVCMOS LVTTL Output Termination Resistors Unpopulated 0402 size resistor pads are provided on each receiver output trace R43 R91 These pads are unpopulated from the factory Note The user must cut the metal trace between the pads before mounting a series termination resistor Connector pin number device pin and name number and resistor placement are mapped below ermination i i NAME Resistor 42 RxCLKOU R43 RxOUTA4 RxOUT4 RxOUT4 RxOUT4 RxOUT4 RxOUT3 RxOUT3 RxOUT3 RxOUT RxOUT3 RxOUT3 RxOUT3 onnector Pin Pin 2 onnector ar in 6 in 8 in 12 NAME Resistor RxOUT2 RxOUT2 RxOUT2 RxOUT2 RxOUT RxOUT1 RxOUT1 RxOUT1 RxOUT1 RxOUT1 RxOUT1 RxOUT1 RxOUT1 RxOUT RxOUT RxOUT RxOUT RxOU RxOU RxOUT RxOUT RxOUT Q2 iw lt o o I 5 wj w C If 3t QLN D I ALS oj wo A i wo N i O A g 0 lt O ol I 2 DH HD OI Biola xt C i Ri BR SLD wo Qo A A Q O N Q2 a A Qo in 16 in 20 co I Par I NO A Q N Qo e gt A A e 2 a S e oO i I g I D gt c I OT N Q A A i I 92 Qo O a Ol N i gi Co a e T NLA NLY d A 3 co co I z Q A in 26 in 30 in 34 in 38 i
10. DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information DS90CR485 486 48 bit 66 133 MHz Channel Link SerDes Chipset Evaluation Kit User Manual Part Number CLINK3V48BT 133 January 2005 PC and Networking Group National Semiconductor Corporation Document Revision 1 01 1 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Table of Contents MT 3 Mor 4 Evaluation Board Features ccccccccsssssseceeeceeeeeeeeeesesseeeeesseeeses 4 Contents of the Evaluation Kit arrrrrnnnnnnrrronnnnnnnrrerrrrnnrrrrrnnnnnnnnnn 4 Applications RT E E 5 Getting Started Lua T7 SEIU D EEE EE E E E A T 8 Board Configuration saadan 9 CLINK3V48BT 133 Evaluation Board Layout Silkscreen 10 Per 11 Transmitter CLKIN Input Clock rrrrrnnnnrrvonnnnnnrrrrnrrnnnnrrrrnrnnnnreenn 12 Default Switch amp Jumper Configuration rrvrrrnnnrrrrrrrrnnrrvrnnnnnn 13 Alternative Switch amp Jumper Configurations 15 Power Down Mode rr 15 ENE 16 DS ORT RR 17 Transmitter PRBS Generator Mode rrrnnnnnnnnvrvvnrrnnnrrennnnnnnerernnnn 19 LVDS Cable Sense TSEN Status Flag rrrrrrrrrnrrrvrrnrnnrrrrrnnnnnnnr 19 Pin amp Signal Assignments rrrnnnnnnnnrvrrnnnnnrrrennnnnnrrrrnnrnnnnereennnnnssnnene 20 DE COMET he r
11. OS LVTTL double edge inputs 48 bits data latched in per clock cycle onto 8 Low Voltage Differential Signaling LVDS streams A phase locked clock is also transmitted in parallel with the data streams over a 9 LVDS pair The receiver converts the 8 LVDS data streams plus clock back to 48 LVCMOS LVTTL data bits plus clock This evaluation kit can be used to test and verify the following Data serialization and deserialization over backplanes or cable Bit error rate testing BERT Eye pattern signal quality Transmitter adjustable LVDS output pre emphasis DC balance mode Transmitter cable detector Cable deskew function Interoperability with National s 112 MHz DS90CR481 482 482 484 chips 112 MHz CLINK3V48BT 112 evaluation kit required Evaluation Board Features National Semiconductor s 48 bit 66 133 MHz DS90CR485 486 Channel Link serializer deserializer On board selectable 66MHz and 133MHz oscillators Provision for external clock source Configuration controls for pre emphasis DC balance cable deskew power down internal pattern generator and pattern select 3M MDR cable and connectors Contents of the Evaluation Kit CLINK3V485 486 PCB with the DS90CR485VS Transmitter and the DS90CR486VS Receiver One 2 meter 3M MDR LVDS cable interface Evaluation Kit Documentation this manual DS90CR485 486 Datasheet 4 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconducto
12. a 21 MDR S ere ig cielo ER tennere rent 22 Probing LVDS SIOIalsosced acsi ates eae qus equ suis eS apDO RED dco RUD EE dE 22 SEERE RE 23 PEER 23 On Board Termination Resistors rrrrrnnrrrvrnrnnnnrrrrvrrrnnrrrrrnnnnnsrnnene 24 Transmitter LVCMOS LVTTL Data Input Termination Resistors 25 Receiver LVDS Input Termination cccccccsseeeeeeeeeeseeeeeeeeenes 26 Optional Receiver LVCMOS LVTTL Output Termination Resistors Unpopulated RR EE NE 27 Troubleshooting METER 28 Troubleshooting Wee TEETER 29 Trouble shooting CHAM ex cess etes prar EE n E rix i Rt ER Enel 29 Additional Inrortfiallolioseccci er ree eumd Rad rabbi x iex Ca E Pv PEE RAM o E MERE 30 Other Resources NR om EM 32 2 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Introduction 3 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Introduction The National Semiconductor CLINK3V48BT 133 evaluation kit demonstrates the performance of the DS90CR485 485 48 bit 66 133 MHz Channel Link SerDes chipset The printed circuit board PCB is optimized for the high speed operation The LVCMOS LVTTL parallel bus trace impedance is 50 Ohms and LVDS differential impedance is 100 Ohms Both LVCMOS LVTTL and LVDS buses have matched trace lengths for low signal to signal skew The transmitter serializes 24 LVCM
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14. ector J4 and the other end to the receiver input connector J5 If a longer cable is desired please contact 3M for more information 3M contacts are included at the end of this document Cables from other manufacturers e g Amphenol SKEWCLEAR can be used and or the board can be modified to interface to custom cable or backplane interconnect Jumpers and switches have been configured at the factory for default operation Please refer to Default Configuration on page 13 amp 14 of this manual for more detail For alternative configurations please refer to Alternative Switch amp Jumper Configurations on page 15 to 19 of this manual for information Connect the appropriate IDC cable from the incoming data and clock to the transmitter input section J1 and connect two 50 pin IDC cables from the receiver output section J2 amp J3 to the receiver load Power and ground for the board must be supplied externally through J13 2 5V Vcc J15 3 3V Vcc J14 and J16 GND See Power Connections on page 11 of this manual for details 8 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Board Configuration 9 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information CLINK3V48BT 133 Evaluation Board Layout Silkscreen 25v GND amp 3 oop G CLOCK SELECT p 66 MHz 133 Hz OPEN pm OPEN 036
15. itch amp Jumper Configurations Power Down mode Both the transmitter and receiver have power down control pins Power down mode shuts down the internal PLL and other circuitry to minimize power consumption Power down control is accessed using switches SW2 and SW3 on the evaluation board as shown on below figure Please see datasheet for detail on power down operation and timing Designator Settings Note PLLSE DC BAL OFF PRBS DISABLE SW2 p Transmitter powered down RE START DESKEW DEFAULT HIGH DC BAL ON HIGH i SW3 Receiver powered down 15 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information DC Balance mode DC balance mode helps minimize the short and long term DC bias on the LVDS lines to facilitate driving long cables To use this function both transmitter and receiver DC balance BAL pins must be switched ON Designator Settings Note SW2 Transmit DC balance ON RE START DESKEW DEFAULT IG SW3 Receive DC balance ON lm _ DEVICE ENABLE Cable Deskew The receiver DESKEW function removes fixed pair to pair skew between the LVDS clock and data The receiver performs deskew calibration automatically on power up provided that sufficient transitions appear on its LVDS data inputs during this time 4096 clock cycles Automatic deskew on power up is enabled by setting pin CON1 SW3 to HIGH and the DESKEW pi
16. l deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such a
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18. n SW3 to DEFAULT In addition deskew calibration can be initiated any time by toggling the DESKEW pin SW3 for more than one clock cycle Once deskew is initiated the LVDS data inputs must have edge transitions for the receiver to perform the deskew operation Unlike older chipsets the DS90CR486 receiver deskew operates in either DC balance or non DC balance mode transmitter and receiver must be in the same DC balance mode NOTE DESKEW pin must set to DEFAULT for normal operation Setting the pin to RE START DESKEW will continuously recalibrate the sampling strobes Data outputs are LOW during this period 16 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Designator Settings RE START DESKEW DEFAULT SW3 DS OPT The DS90CR485 transmitter DS OPT pin J6 automatically generates an LVDS switching pattern at the LVDS outputs This pattern instructs DS90CR482 484 receivers to initiate deskew calibration This switching pattern is also suitable for DS90CR486 deskew however the DS90CR486 deskew operation is not initiated by this DS OPT pattern but instead is initiated automatically on power up or on command by toggling its DESKEW pin For optimal deskew calibration it is recommended the DS OPT pin be pulled HIGH for at least 4096 clock cycles plus 20 ms if the transmitter and receiver are not yet powered up and synchronized Please see data
19. n 40 in 44 in 48 N I Q o1 Ie Q ye Oo a NO i 1 oa D e e i Co CO O p Oo N ao A z ol I i O QJ I Cc Qo Qo Oo Q I I Zz A A co NO ps oa i lt e ALO oil j 0o DL li Sul co a x o c m e I r z co amp A D RxOUT2 RxOUT2 RxOUT2 RxOUT2 RxOUT2 e Q2 i i o 49 I i Q2 co Qo e N A Oo ie A I ps o R O lo e Q O zZ g 55 UES 61 o o I 1 Co Qo A 27 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Troubleshooting 28 of 32 DS90CR485 486 Evaluation Kit User Manual Rev 1 01 Troubleshooting National Semiconductor The Sight amp Sound of Information If the demo boards are not performing properly use the following as a guide for quick solutions to common problems If the problem persists contact the hotline number listed under Additional Information section of this document Check the following 1 Power and Ground are connected to both power connections of the board 2 Supply voltage 2 5V and 3 3V and current It s around 130mA for the 2 5V supply and 90mA for the 3 3V supply with clock and one data bit at 66MHz are correct m input connector Dg Em s Trouble shooting chart Input clock and input data It
20. nt using jumper J12 Power Connection The CLINK348BT 133 evaluation board has two power plane layers one for the transmitter s 2 5V supply and the other layer for the receiver s 3 3V supply The power and ground connections for the evaluation board must be applied through power spade connectors J13 2 5V Voc J15 3 3V Voc J14 and J16 GND See datasheets for recommended operating conditions 2 5V Vcc GND 3 3V Vcc GND J13 J14 J15 J16 Tantalum 10uF capacitors C38 and C39 placed near each power connection provide bulk energy storage In addition to excellent bypassing provided by the closely sandwiched power and ground planes a network of 0 1uF C1 C19 0 01uF C26 C31 and 10uF C32 C37 bypass capacitors is placed between each Vcc and ground group to provide additional bypassing near each device When using any high speed SerDes it is recommended that power supply noise measured at device power and ground pins especially PLL Vcc and PLL GND be less than 100 mV peak to peak 11 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Transmitter CLKIN Input Clock An external low jitter clock may be supplied at pin 2 of jumper J1 or alternatively one of two convenient on board oscillators 66 MHz or 133 MHz may be selected instead Jumper J10 selects the clock source while jumpers J7 and J8 enable either the 66 MHz or 133 MHz on board oscillat
21. ors respectively Designator Settings OOO Use external clock source 66MHz 133MHz Default setting No Jumper 66 MHz oscillator disabled default setting 133 MHz oscillator disabled default setting Use on board 66 MHz oscillator 66MHz 133MHz 66 MHz oscillator ENABLED no jumper 133 MHz oscillator disabled default setting Use on board 133 MHz oscillator 66MHz 133MHz 66 MHz oscillator disabled default setting 133 MHz oscillator ENABLED no jumper Pletronics 2 5V CMOS crystal oscillators See Appendix for information 12 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Default Switch amp Jumper Configuration The following default settings are for normal data transmission operation CON6 CON7 CONS Designator Settings Note con BE CON CON3 CON4 SW1 CONS SW2 WT tt ttt SW3 HF stes DEVICE ENABLE J8 133MHz Oscillator disabled J7 66MHz Oscillator disabled 13 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information J10 O O External clock used J11 0 pre emphasis R42 potentiometer is ignored Manual 0 Adjust J12 O Transmitter inputs are 3V tolerant 2 5V Vcc 3 3V Vcc 14 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Alternative Sw
22. r The Sight amp Sound of Information Applications 5 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information LVDS DS90CR485 DATA DS90CR486 8 396 798 8 L gt Mbps gt 5 8 E a per channel p w z 8 2 E 3 E HE 3 DS 8 o 2 gt og te 8 O g 2 u amp J i 9 4 Jaja 1 I e JE o E 9 51 6 384Gbps 5 45 5 6 EF O E gt d V o E V Oo E g3 8 2 t7 e O a CLOCK IN LVDS CLOCK CLOCK OUT 66 133MHz PLL 2 66 133MHz _ P gt PLL 66 133MHz POWERDOWN L POWERDOWN Channel Link Application The diagram above illustrates the use of the Chipset Tx Rx This chipset is able to transmit 48 bits of TTL CMOS data using eight LVDS channels at the speed of 6 384Gbps Please refer to datasheet for information on Chipsets 6 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Getting Started 7 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Setup The CLINK3V48BT 133 evaluation board is delivered ready to run with configuration switches and jumpers set to their default positions To start using the evaluation kit follow these steps 1 Connect one end of the D26 1 MDR cable to the transmitter output 2 4 conn
23. sheet for deskew more details regarding DS OPT and deskew operation NOTE DC BAL pin of SW2 must set to DC BAL ON for the transmitter to output switching pattern DS OPT will be ignored if DC BAL pin of SW2 set to DC BAL OFF Designator Settings Note Vesignator settings Note SW2 Transmit DC balance ON J6 LVDS clock 1111100 1100000 LVDS data 1111000 1110000 Vcc GND DS OPT J6 LVDS clock 1111000 1110000 LVDS data 1111111 0000000 Vcc GND 17 of 32 DS90CR485 486 Evaluation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information Transmitter Input Voltage Tolerance Setting The DS90CRA85 transmitter inputs are configurable as either 2 5V or 3 3V tolerant This can be achieved by connecting input voltage jumper J12 to 2 5V or 3 3V Typically the inputs should be set for 3V tolerance J12 J12 2 5V input tolerance 3 3V input tolerance 2 5V 3 3V 2 5V 3 3V Transmitter Pre Emphasis Transmitter pre emphasis boosts LVDS drive current during each LVDS logic transition to reduce cable loading effects The jumper J11 either disables pre emphasis or allows the manual adjustment of pre emphasis level using potentiometer R42 Designator Settings Note Vesignator settings Note J11 Pre emphasis disabled i e 0 Default setting R42 is ignored Manual 0 Adjust J11 R42 adjusts pre emphasis level Manual 096 Adjust When the jumper J11 is set to MANUAL ADJUST
24. valuation Kit User Manual National Rev 1 01 Semiconductor The Sight amp Sound of Information MDR Connector Transmitter LVDS Output Receiver LVDS Input NAME GN RxOUT1 RxOUT2 RxCLK1 GN GN GN zZ gt z Q m O Zz Q TxOUTO TxOUT1 TxOUT2 CLK1 A O c eo ULU TI VU I g l Zz g O Zz g g TxOUT3 TxOUT4 TxOUT5 TxOUT6 TxOUT7 Of Ul U Ul U U TxOUTOM TxOUT1M TxOUT2M CLK1M Of Ul Ul U Ul U O Zz g Zz g LAM LN O Zz J4 Probing LVDS Signals LVDS signals are high speed low swing signals Improper probing can result in deceiving results since the probe and or scope can filter high speed components of the signal Using a gt 1 GHz bandwidth scope such as the Agilent 86100 or Tektronix 694C and a high speed differential probe such as the Tektronix P6247 8 or P6330 is highly recommended LVDS drivers are not compatible with 50 Ohm probes 22 of 32 DS90CR485 486 Evaluation Kit User Manual Rev 1 01 Switches Transmitter Configuration Control NIA BOARD LABEL NAME ONS HIGH ON6 HIGH in7 ON7 HIGH in8 ONG HIGH SW1 Transmitter Configuration Control NIA NAME C_BAL OFF PLL_SEL BAL C_BAL ON in3 RBS DISABLED PRBS_EN RBS ENABLED RBS 15 PRBS PAT SEL EST1 HIGH TEST EST2 HIGH in in 1 BOARD LABEL PLLSEL HIGH in 2 OO I I 5 A N i 1 3S 5 OT o 4 I 2 T 5 g
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