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HMC832LP6GE

1. DIVIDER CTRL DT DO POWER DOW 0 A WE BY TU The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request Changing Evaluation Board Reference Frequency amp CP Current Configuration The evaluation board is provided with a 50 MHz on board reference oscillator and Type 1 loop filter configuration shown in Table 1 127 kHz bandwidth The default register configuration file included in the Hittite PLL Evaluation software sets the comparison frequency to 50 MHz R 1 ie Reg 02h 1 As with all PLLs and PLL with Integrated VCOs modifying the comparison frequency or Charge Pump CP current will result in changes to the loop dynamics and ultimately phase noise performance When making these changes there are several items to keep in mind e CP Offset Current setting Refer to Section 1 5 1 e LD Configuration Refer to Section 1 5 5 To redesi
2. V gt QO m t a LLI lt L z V uM e A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz fvco fyco2 Integer Integer Boundary Boundary fy fco coz fvcos fvco4 fvcoZ 2 fvco241 fvco2 fi fcr fi e Figure 47 Exact Frequency Tuning Some fractional PLLs are able to achieve this by adjusting shortening the length of the Phase Accumulator the denominator or the modulus of the Delta Sigma modulator so that the Delta Sigma modulator phase accumulator repeats at an exact period related to the interval frequency fycok fycoyk 1 in Figure 47 Consequently the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period or at harmonic frequencies of fycok fvcoyk 1 For example in some applications these intervals might represent the spacing between radio channels and the spurious would occur at multiples of the channel spacing The Hittite method on the other hand is able to generate exact frequencies between adjacent integer N boundaries while still using the full 24 bit phase accumulator modulus thus achieving exact frequency steps with a high phase detector comparison rate which allows Hittite PLLs to maintain excellent phase noise and spurious performance in the Exact Frequency Mode 1 5 7 6 6 Usin
3. gt QO m t a LLI z L V uM A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz HMC832LP6GE HMC832LP6GE Figure 38 HWC832LP6GE used as a tunable reference for HMC832LP6GE Tunable Reference 25 MHz to 100 MHz Crystal Oscillator Using the HMC832LP6GE with a tunable reference as shown in Figure 38 it is possible to drastically improve spurious emissions performance across all frequencies Example shown in Figure 16 shows that it is possible to achieve spurious emissions as low as 108 dBc Hz at 2 GHz Please contact Hittite s application support to obtain detailed tunable reference configuration Power Supply The HMC832LP6GE is a high performance low noise device In some cases phase noise and spurious performance may be degraded by noisy power supplies To achieve maximum performance and ensure that power supply noise does not degrade the performance of the HMC832LP6GE it is highly recommended to use Hittite s low noise high PSRR Power Supply Rejection Ratio regulator the HMC1060LPSE Using the HMC1060LP3E lowers the design risk and cost and ensures that the performance shown in Typical Performance Characteristics can be achieved Power supply noise contribution to the PLL output phase noise can easily be modelled in the Hittite PLL Design tool To download Hittite s PLL Design software tool click o
4. For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz NDLY Tpd Reg02 CALIBRATION WINDOW I Tt RT x2 RegA 14 13 Start Stop eg m 0 2 4 5 RegA 2 0 n 0 1 2 3 5 6 7 8 50 MHz Max for FSM VSPI Clocks Figure 43 VCO Calibration A 5 bit step tuned VCO for example nominally requires 5 measurements for calibration worst case 6 measurements and hence 7 VSPI data transfers of 20 clock cycles each Total calibration time worst case is given by Tay k128T poy 6T py 2 7 20T poy EQ 7 cal or equivalently y cal Taa OR 2 140 3 128 2 EQ 8 For guaranteed hold of lock across temperature extremes the resolution should be better than 1 84 the frequency step caused by a VCO sub band switch change Better resolution settings will show no improvement 1 4 1 5 1 1 VCO AutoCal Example The VCO subsystem must satisfy the maximum f limited by the two following conditions a N gt 16 fin N gt 20 0 frac where N fvco fod b fsa lt 100 MHz Suppose the VCO subsystem output frequency is to operate at 2 01 GHz Our example crystal frequency is fta 50 MHz
5. 00000 wanes O S e mowo ooo 0 e o ewwa O O a e VCO Open Loop Phase Noise at fo 2 GHz 5 owo OOOO o f e Cd wwo e e Comos OO 5 sew owo O O O ow y ee 2500 800 MHz Low Current Mode VCO_Reg 03h 1 0 23d 41 2500 L E L L L N N N N N gt gt UA A 5 m 4 For detailed current consumption information please refer to Figure 31 and Figure 32 5 Gain setting 6 VCO Reg 07h 3 0 6d in High Performance mode VCO Reg 03h 1 0 3d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com lI V gt QO m t a D LLI Z L z V EM qn A V gt C m t a LLI Z L V un A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY Electrical Specifications Continued Parameter VCO Open Loop Phase Noise at fo 2 GHz 2 1 GHz P5 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset VCO Open Loop Phase Noise at fo 3 GHz 30 100 MHz 5 10 kHz Offset 110 dBc Hz 100 kHz Offset a EE 139 dBc Hz L7wmoma o www om sete w 3 sene ure at tert
6. to wo resena 9 wo Resena OOOO 3 7 Miu Reg06h MSB Cal s pam m Beraun e es 3 8 VCO 07h Power Control Output stage gain control in 1 dB steps Od 0 dB Gain 1d 1 dB Gain 3 0 Output Stage Gain Control 2d 2 dB Gain 10d 10 dB Gain 11d 11 dB Gain w wo inaizaton 3 9 Programs SSS For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo01 0812 FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz RoHS vV E NOTES V gt QO m t a D LLI Z L z V A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com
7. 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI a Z L z V a A V gt QO m t a LLI Z L z V uM uM A eal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS vV E 1 4 1 6 1 4 2 FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Table 2 AutoCal mampi with F 50 MHz R 1 m 0 2 a s ae sm suse ie Ce 2 mw sem 35 s se e seem Manual VCO Calibration for Fast Frequency Hopping If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating the VCO in advance and storing the switch number vs frequency information in the host This can be done by initially locking the HMC832LP6GE on each desired frequency using AutoCal then reading and storing the selected VCO switch settings The VCO switch settings are available in Reg 10h 7 0 after every AutoCal operation The host must then program the VCO switch settings directly when changing frequencies Manual writes to the VCO switches are executed immediately as are writes to the integer and fractional registers when AutoCal is disabled Hence frequency changes with manual control and AutoCal disabled requires a minimum of two serial port transfers to the PLL once to set the VCO switches and once to set the
8. LLI tk Z L z V a A I V O O gt QO m t a LLI Z L z QU un un A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY PD Force UP Reg OBh 9 1 and PD Force DN Reg OBh 10 1 allows the charge pump to be forced up or down respectively This will force the VCO to the ends to the tuning range which can be useful in test of the VCO 1 5 2 Reference Input Stage RVDD AC couple 100 Figure 46 Reference Path Input Stage The reference buffer provides the path from an external reference source generally crystal based to the R divider and eventually to the phase detector The buffer has two modes of operation controlled by Heg 08h 21 High Gain Reg 08h 21 0 recommended below 200 MHz and High frequency Reg 08h 21 1 for 200 to 350 MHz operation The buffer is internally DC biased with 100 O internal termination For 50 O match an external 100 O resistor to ground should be added followed by an AC coupling capacitor impedance lt 1 Q then to the XREFP pin of the part At low frequencies a relatively square reference is recommended to keep the input slew rate high At higher frequencies a square or sinusoid can be used The following table shows the recommended operating regions for different reference frequencies If operating outside these regions the part will norma
9. from the serial port register Reg Olth 1 It is also possible to leave various blocks on when in Power Down see Reg 01h including a Internal Bias Reference Sources Heg 01h 2 b PD Block Reg O1h 3 c CP Block Heg 01h 4 d Reference Path Buffer Reg 01h 5 e VCO Path buffer Heg O1h 6 f Digital I O Test pads Reg O1h 7 To mute the output but leave the PLL and VCO locked please refer to 1 4 4 section 1 8 General Purpose Output GPO Pin The PLL shares the LD_SDO Lock Detect Serial Data Out pin to perform various functions While the pin is most commonly used to read back registers from chip via the SPI it is also capable of exporting a variety of signals and real time test waveforms including Lock Detect It is driven by a tri state CMOS driver with 200 O Rout It has logic associated with it to dynamically select whether the driver is enabled and to decide which data to export from the chip In its default configuration after power on reset the output driver is disabled and only drives during appropriately addressed SPI reads This allows it to share the output with other devices on the same bus The pin driver is enabled if the chip is addressed ie The last 3 bits of SPI cycle 000 b before the rising edge of SEN If SEN rises before SCK has clocked in an invalid non zero chip address the HMC832LP6GE will start to drive the bus To monitor any of the GPO signals including Lock Detect set Reg OFh 7 1 to
10. 0 which also sets VCO sub band setting Reg 05h 15 7 20 to zero effectively programming incorrect VCO sub band settings and causing the HMC832LPGGE to lose lock e Immediately followed by a write to Reg 03h if in Integer Mode e or Reg 04h if in Fractional Mode Which effectively re triggers the AutoCal state machine forcing the HMC832LP6GE to re lock This procedure will cause the HMC832LP6GE to lose lock and re lock after every VCO subsystem change Typical output frequency and lock time can be observed in Figure 25 and Figure 26 and is typically in the order of 100 us for a phase settling of 10 and is also dependent on loop filter design loop filter bandwidth and loop filter phase margin 1 4 VCO Subsystem The HMC832LP6GE contains a VCO subsystem that can be configured to operate in e Fundamental frequency fo mode 1500 MHz to 3000 MHz e Divide by N mode where N 2 4 6 8 58 60 62 25 MHz to 1500 MHz All modes are VCO register programmable as shown in Figure 40 One loop filter design can be used for the entire frequency of operation of the HMC832LPGGE For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI kt Z L V uM x A esrittite HMC832LP6GE MICROWAVE CO
11. 00000 i TE 4 T i s Gain Setting O_ _ _ _ EP GN ae VCO Reg07h 3 0 Od 10 E t 1 Low Current Mode ere ies ce 3 VCO RegO3h 1 0 1d High Performance Mode ee por ded As aM EST m EERTE 100 1000 3000 100 1000 3000 FRQUENCY MHz FRQUENCY MHz Figure 23 Typical RF Output Power at Figure 24 RF Output Return Loss 2 GHz Single Ended vs Temperature 10 E S S m D Z g 2 5 gt E Lu gt iam o 100 1000 GAIN SETTING OUTPUT FREQUENCY MHz 13 Loop Filter Type 2 from Table 1 used 14 Using High Performance Mode VCO Reg 03h 1 0 3d 15 The HMC832LP6GE features programmable RF Output Return loss VCO Reg O3h 5 and 12 dB of programmable gain VCO Reg 07h 3 0 Maximum output power is achieved with high Return Loss setting VCO Reg O3h 5 0 as shown in Figure 21 Setting VCO Reg O3h 5 1 improves Return Loss for applications that require it Figure 21 at the cost of reduced RF Output Power Figure 24 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3348 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite MICROWAVE CORPORATION v01 0812 RoHS v Figure 25 Frequency Settling After Frequency Change AutoCal Enabled re __ Settling Time to lt 10 Degree
12. 120 140 PHASE NOISE dBc Hz High Performance Mode VCO Rego3h 10 3d 160 SSB Integrated Phase Noise 56 dBc AP Integration Bandwidth 1 kHz to 100 MHz 4 ii SNR 53 dB EVM 0 224 Phase Noise ias rs am panawa 1 kHz to 100 Ri 10 10 10 10 107 10 OFFSET Hz HMC832LP6GE FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Figure 8 Fractional Spurious Performance at 1804 MHz Exact Frequency Mode ON Low Current Mode Dot eenid id Pei SSB Integrated Phase Noise 58 7 dBc bobo aay Integration Bandwidth 1 kHz to 100 MHz 5 100 Ae n roid SNA 55 7 EVM 0 164 Phase Noise 120 140 PHASE NOISE dBc Hz High Pa RN Mode VCO Rego3h 10 3d 160 SSB Integrated Phase Noise 59 dBc_ Integration Bandwidth 1 kHz to 100 MHz SNR 56 dB EVM 0 158 Phase Noise Integration Bandwidth 1 kHz to 100 MHz 180 OFFSET kHz Figure 10 Fractional Spurious Performance at 2118 i MES mAN ew Mode OFF 1 60 m pe Current Mode RE ene 1d SSB Integrated Phase Noise 57 dBc bi Integration Bandwidth 1 kHz to 100 MHz m PU SNR 54 EVM 0 199 Phase Noise un cd Integration Bandwidth 1 kHz to 100 MHz PHASE NOISE dBc Hz High Performance Mode VCO Rego3h 10 3d SSB Integrated Phase Noise 57 45 dBc_ Integration Bandwidth 1 kHz to 100 MHz SNR 54 45 dB EVM 0 189 Phase Noise Integration Bandwidth 1
13. 3 Hz cannot be tolerated Fractional PLLs are able to generate exact frequencies with zero frequency error if N can be exactly represented in binary eg N 50 0 50 5 50 25 50 75 etc Unfortunately some common frequencies cannot be exactly represented For example Nia 0 1 1 10 must be approximated as round 0 1 x 224 224 0 100000024 At fpp 50 MHz this translates to 1 2 Hz error Hittite s exact frequency mode addresses this issue and can eliminate quantization error by programming the channel step size to Fpp 10 in Reg OCh to 10 in this example More generally this feature can be used whenever the desired frequency fyco can be exactly represented on a step plan where there are an integer number of steps lt 2 4 across integer N boundaries Mathematically this situation is satisfied if f icok Mod fea 0 where fgcd gcd f corfpp and fgcd gt EJ EQ 16 Where gcd stands for Greatest Common Divisor fy maximum integer boundary frequency lt fyco fpp frequency of the Phase Detector and fyco are the channel step frequencies where 0 lt k lt 224 1 As shown in Figure 47 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI a Z L V uM ae A
14. PLL frequency If AutoCal is disabled Reg OAh 11 1 the VCO will update its registers with the value written via Reg 05h immediately The VCO internal transfer requires 16 VSCK clock cycles after the completion of a write to Heg 05h VSCK and the AutoCal controller clock are equal to the input reference divided by O 4 16 or 32 as controlled by Reg 0Ah 14 13 Registers required for Frequency Changes in Fractional Mode A large change of frequency in fractional mode Reg O6h 11 1 may require Main Serial Port writes to 1 The integer register intg Reg 03h only required if the integer part changes 2 The VCO SPI register Reg 05h e only required for manual control of VCO if Reg OAh 11 1 AutoCal disabled e required to change the VCO Output Divider value if needed VCO_Reg 02h please see Figure 40 for more information 3 The fractional register Reg 04h The fractional register write triggers AutoCal if Reg OAh 11 0 and is loaded into the modulator automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the fractional frequency change is loaded into the modulator immediately when the register is written with no adjustment to the VCO Small steps in frequency in fractional mode with AutoCal enabled Reg OAh 11 0 usually only require a single write to the fractional register Worst case 3 Main Serial Port transfers to the HMC832LP6GE could be required to change frequencies in fractional mode If the frequency s
15. RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz e Drive SDO during reads Lock Detect otherwise e Set GPO Select Reg OFh 4 0 00001 b which is default e Set Prevent GPO driver disable Reg OFh 7 1 e Always drive Lock Detect e Set Prevent AutoMux of SDO Reg OFh 6 1 e Set GPO Select Reg OFh 4 0 00001 which is default e Set Prevent GPO driver disable Reg OFh 7 1 The signals available on the GPO are selected by changing GPO Select Reg OFh 4 0 1 9 Chip Identification PLL subsystem version information may be read by reading the content of read only register chip_ID in Reg OOh It is not possible to read the VCO subsystem version 1 10 SERIAL PORT The SPI protocol has the following general features a 3 bit chip address can address up to 8 devices connected to the serial bus b Wide compatibility with multiple protocols from multiple vendors c Simultaneous Write Read during the SPI cycle d 5 bit address space e 3 wire for Write Only capability 4 wire for Read Write capability Typical serial port operation can be run with SCLK at speeds up to 50 MHz 1 10 1 Serial Port Initialization at Power Up At power up it is required that both SEN and SCK lines are initially held low and that the first rising edge occurs on the SCK line before any rising edges occur on the SEN line If the first rising edge occurs on the SEN line before it does on the SCK line the HMC
16. RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz 1 5 PLL Subsystem 1 5 1 Charge Pump CP amp Phase Detector PD The Phase detector PD has two inputs one from the reference path divider and one from the RF path divider When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each other We refer to the frequency of operation of the PD as fpa Most formulae related to step size delta sigma modulation timers etc are functions of the operating frequency of the PD foa foa is also referred to as the comparison frequency of the PD The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals The output current varies linearly over a full 27 radians X360 of input phase difference 1 5 1 1 Charge Pump A simplified diagram of the charge pump is shown in Figure 44 The CP consists of 4 programmable current sources two controlling the CP Gain Up Gain Reg O9h 13 7 and Down Gain Reg O9h 6 0 and two controlling the CP Offset where the magnitude of the offset is set by Reg 09h 20 14 and the direction is selected by Reg 09h 21 1 for up and Reg 09h 22 1 for down offset CP Gain is used at all times while CP Offset is only recommended for fractional mode of operation Typically the CP Up and Down gain
17. disabling the LD output m Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock Detect on LD_SDO Lal Read Timing Characteristics Parameter imi te E l Units ts NN e seges oi ts sckmengEwewSDOime sensoa w O e Recovering OOO 3 l w scememE amp eosENReENe 0 s For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz FIRST CYCLE SCK i PUUN AU UUU E tg SDI X d5 do r4 r3 rO a2 al a0 X READ Address Register Address 00000 Chip Address 000 LD SDO d m CELE SEE TRI STATE ul ts t4 SECOND CYCLE 28 29 30 31 32 1 18 19 20 23 24 25 H t7 ONO te SDI x d23 d5 do r4 r3 rO a2 al aO X seeped Koad od Od eae SEN LD GPO Figure 49 Serial Port Timing Diagram READ For more information on using the GPO pin while in SPI Open Mode please see section 1 10 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps
18. example 2800 2 x109 fy fop xfloor 45x61 44x108 2764 8 MHz Then 61 44x106 fico1 2 Reg 04h ceil PD f for channel 1 where fjco 2800 2 MHz 924 2800 2x10 2764 8 x108 61 44 x106 4 To change from channel 1 fuco 2800 2 MHz to channel 2 fuco 2800 3 MHz only Heg 04h needs to be programmed as long as all of the desired exact frequencies fyco Figure 47 fall between the same integer N boundaries f lt fyco lt fy 4 In that case ceil 9666560d 938000h 924 2800 3x10 2764 8x10 6144x109 9693867d 93EAABh and so on x Reg 04h ceil 1 5 8 Seed Register The start phase of the fractional modulator digital phase accumulator DPA may be set to one of four possible default values via the seed register Reg O6h 1 0 The HMC832LP6GE will automatically reload the start phase seed value into the DPA every time a new fractional frequency is selected Certain zero or binary seed values may cause spurious energy correlation at specific frequencies For most cases a random or non zero non binary start seed is recommended Reg O6h 1 0 2 1 6 Soft Reset amp Power On Reset The HMC832LP6GE features a hardware Power on Reset POR All chip registers will be reset to default states approximately 250 us after power up The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg OOh Note that the soft reset does not clear th
19. for Exact Frequency Channel Mode initially and only at the beginning integer Reg 03h and exact frequency Reg OCh registers need to be programmed for the smallest fyco frequency fyco in Figure 47 as follows 1 Calculate and program the integer register setting Reg 03h Nyyrz floor fyco fpp where fyco is shown in Figure 47 and corresponds to minimum channel VCO frequency Then the lower integer boundary frequency is given by fy Niwr fpp 2 Calculate and program the exact frequency register value Reg OCh fpp fgcg where fgca gcd fycok 1 fycox fpp greatest common divisor of the desired equidistant channel spacing and the PD frequency fycoks7 fycox and fpp Then to switch between various equally spaced intervals channels only the fractional register Reg 04h needs to be programmed to the desired VCO channel frequency fyco in the following manner 24 f _f Reg 04h Nerac ca en wherefy floor fyco fpp andfyco as shownin Figure 47 represents the smallest channel VCO frequency that is greater than fy Example To configure the HMC832LP6GE for Exact Frequency Mode for equally spaced intervals of 100 kHz where first channel Channel 1 fyco 2800 200 MHz and Phase Detector PD rate fpp 61 44 MHz proceed as follows First check that the exact frequency mode for this fyco 2800 2 MHz Channel 1 and fyoo2 2800 2 MHz 100 kHz 2800 3 MHz Channel 2 is possible For price delivery and to p
20. hittite com V gt QO m t a D LLI Z L z V A V gt QO m t a LLI z L z QU EN e A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz 2 0 PLL Register Map 2 1 Reg 00h ID Register Read Only Lug mo jaw BT a 2 2 2 00h Mode Read Address RST Strobe M Write Only WRITE ONLY Read Address for next cycle Open Mode Soft Reset both SPI modes reset set to O for proper KNEE Sor Reset ESES operation esea wo Notdetined 16 NotDefneatsetto Oforproperoperation 2 3 Reg 01h RST Register Default 000002h 1 take PLL enable via CEN pin see Power Down Mode description 9 0 R W rst chipen pin select 0 take PLL enable via SPI rst chipen from spi RegO1 1 2 4 Reg 02h REFDIV Register Default 000001h Reference Divider R Value EQ 12 Divider use also requires refBufEn Reg08 3 1and Divider min 1d max 16383d 2 5 Reg 03h Frequency Register Integer Part Default 000019h VCO Divider Integer part used in all modes see EQ 12 Fractional Mode min 20d max 21 4 7FFFCh 524 284d Integer Mode min 16d max 219 1 7FFFFh 524 287d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Or
21. kHz to 100 MHz Lad ppt 3o oe eed OFFSET Hz Figure 12 Fractional Spurious Performance at 2646 96 MHz Exact Frequency Mode OFF 1 Til 1 1 Low Current Mode VCO RegO3h 10 1d ji 80 cocco a a SSB Integrated Phase Noise 55 6 dBc Ra 2 1 Integration Bandwidth 1 kHz to 100 MHz oie SNR 52 6 EVM 0 234 Phase Noise 356 bora Integration Bandwidth 1 kHz to 100 MHz mud 120 140 PHASE NOISE dBc Hz High Performance Mode coL RegO3h 10 3d 160 _ SSB Integrated Phase Noise 56dBc fi Integration Bandwidth 1 kHz to 100 MHz 4 trig SNR 53 dB EVM 0 224 Phase Noise Ao 16b Integration Pandwidii 1 kHz to 100 mE 10 10 10 10 10 10 OFFSET Hz 3 122 88 MHz Xtal PFD 61 44 MHz Channel Spacing 200 KHz Loop Filter Type 2 from Table 1 4 122 88 MHz Xtal PFD 61 44 MHz Channel Spacing 200 KHz Loop Filter Type 2 from Table 1 5 122 88 MHz Xtal PFD 61 44 MHz Channel Spacing 240 KHz Loop Filter Type 2 from Table 1 6 Identical configuration to 5 with Exact Frequency Mode turned Off 7 122 88 MHz Xtal PFD 61 44 MHz Channel Spacing 240 KHz Loop Filter Type 2 from Table 1 8 Identical configuration to 7 with Exact Frequency Mode turned Off For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com A
22. or cr Wmamein me ete VCO Characteristics VCO Characteristies S a e e eae je ects je mois jet Deme i For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite MICROWAVE CORPORATION v01 0812 RoHS v EART NDLY Typical Performance Characteristics Figure 1 Typical Closed Loop Integer Phase Noise 111 100 Ato eet VEN a reir Loop i BW 75 KHz 120 PT ano Sein 140 PHASE NOISE dBc Hz 150 OFFSET Hz Figure 3 Open Loop VCO Phase Noise at 1800 MHz d p ae Low Current Mode e cn VCO RegO3h 1 0 19 PHASE NOISE dBc Hz High curse Mode k vea Pe ania an OFFSET Hz Figure 5 Free Running VCO Phase Noise at 3000 MHz Low Current Mode VCO_RegO3h 10 1d PHASE NOISE dBc Hz xr s n High A A Mode jet ie lia lal belie arr NM age d ht OFFSET Hz 1 Measured with 50 MHz PD frequency output gain of 6 VCO Reg 07h 3 0 HMC832LP6GE FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Figure 2 Typical Closed Loop Fractional Phase Noise n PHASE NOISE dBc Hz 880 MHz EVM 61 3 dB or 0 086 1605 MHz EVM 57 5 dB or 0 133 2505 MHz EVM 52 dB or 0 251 880 MHz EVM 61 8 dB o
23. 0 170 30 100 300 1000 OFFSET Hz FREQUENCY MHz 9 100 MHz Xtal PD Frequency 50 MHz loop filter bandwidth 75 kHz Type 2 from Table 1 Fractional Mode 50 MHz Low Pass Filter used at the output of the HMC832LP6GE only for the 25 MHz curve Charge Pump is set to Maximum value 10 50 MHz fixed reference 50 MHz PD frequency The plot shows an integer boundary spur inside the loop filter bandwidth All PLLs with Integrated VCOs exhibit integer boundary spurs at harmonics of the reference frequency The plot shows the worst case spurious scenario where harmonic of the reference frequency 50 MHz is within the loop filter bandwidth of the fundamental frequency of the HMC832LPG6GE 11 Loop Filter Type 2 from Table 1 The tunable reference is used to change the reference frequency from 50 MHz in Figure 14 to 47 5 MHz in figure Figure 15 in order to distance the harmonic of the reference frequency spurious emissions away from the fundamental output frequency of the HMC832LP6GE so that it is filtered by the loop filter The internal HMC832LP6GE setup and divide ratios are changed in the opposite direction accordingly so that the HMC832LP6GE generates identical output frequency as in Figure 14 without the spurious emissions inside the loop bandwidth 12 The graph is generated by observing and plotting the magnitude of only the largest spur at any offset at each output frequency while using a fixed 50 MHz reference and a tunable 47 5 MHz refere
24. 00 MHz 3d Reserved S O For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY 2 11 Reg 09h Charge Pump Register Default 403264h Name h ED It Description Charge Pump DN Gain Control 20 p A4step Affects fractional phase noise and lock detect settings Od 0 pA CP DN Gain 7 Pr 1d 20 pA 2d 40 pA 127d 2 54mA Charge Pump UP Gain Control 20 pA per step Affects fractional phase noise and lock detect settings Od 0 pA CP UP Gain Y Po 1d 20 pA 2d 40 pA 127d 2 54mA Charge Pump Offset Control 5 pA step Affects fractional phase noise and lock detect settings Od 0 pA 20 14 Offset Magnitude 7 1d 2 5 pA 2d 10 pA 127d 635 pA 21 Offset UP enable Pot o Recommended setting 1 in Fractional Mode 0 otherwise 22 Offset DN enable Recommended setting 0 py mw aese 3 9 Red S 2 12 Reg 0Ah VCO AutoCal Configuration Register Default 002205h R Divider Cycles 0 1 V Resoluti 1 2 tune Resolution 2 4 7 256 ss ow em 7 a Rem 000000000000 11 EE AutoCal Disable 1 o 1 AutoCal disabled 12 qa RW No VSPI Trigger 01 0 Don t trigger a transfer o
25. 00 MHz Output gain settings VCO_Reg 07h 3 0 Output Return Loss setting VCO_Reg O3h 5 See Figure 24 for more information Single ended or differential output operation VCO_Reg O3h 3 2 Mute VCO Reg 03h 8 7 1 3 SPI Serial Port Interface Configuration of PLL amp VCO Subsystems The two subsystems PLL subsystem amp VCO subsystem have their own register maps as shown in PLL Register Map and VCO Subsystem Register Map sections Typically writes to both register maps are required for initialization and frequency tuning operations As shown in Figure 39 the PLL subsystem is connected directly to the SPI of the HMC832LP6GE while the VCO subsystem is connected indirectly through the PLL subsystem to the HMC832LP6GE SPI As a result writes to the PLL Register Map are written directly and immediately while the writes to the VCO Subsystem Register Map are written to the PLL subsystem Reg 05h and forwarded via the internal VCO SPI VSPI to the VCO subsystem This is a form of indirect addressing Note that VCO subsystem registers are write only and cannot be read More information is available in 1 3 1 VCO Serial Port Interface VSPI section 1 3 1 VCO Serial Port Interface VSPI The HMC832LP6GE communicates with the internal VCO subsystem via an internal 16 bit VCO SPI The internal serial port is used to control the step tuned VCO and other VCO subsystem functions Note that the internal VCO subsy
26. 30 32 g Master asserts SEN after the 32nd rising edge of SCLK h Slave registers the SDI data on the rising edge of SEN 1 2 5 22 23 24 25 26 30 31 Figure 48 Serial Port Timing Diagram WRITE 1 10 3 Serial Port READ Operation A typical READ cycle is shown in Figure 49 In general the LD_SDO line is always active during the WRITE cycle During any SPI cycle LD_SDO will contain the data from the current address written in RegOh 7 3 If RegOh 7 3 is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in progress If it is desired to READ from a specific address it is necessary in the first SPI cycle to write the desired address to RegOh 7 3 then in the next SPI cycle the desired data will be available on LD_SDO An example of the two cycle procedure to read from any random address is as follows a The Master host on the first 24 falling edges of SCLK places 24 bit data d23 d0 MSB first on SDI as shown in Figure 49 d23 d5 should be set to zero d4 dO address of the register to be READ on the next cycle b the slave HMC832LP6GE shifts in data on SDI on the first 24 rising edges of SCK c Master places 5 bit register address r4 r0 the READ ADDRESS register MSB first on the next 5 falling edges of SCK 25 29 r4 r0200000 d Slave shifts the register bits on the next 5 rising edges of SCK 25 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 fall
27. 6 Frequency hop of 5 MHz is shown in Figure 27 and Figure 28 however the settling time is independent of the size of the frequency change Any size frequency size hop will have a similar settling time with AutoCal disabled Reg OAh 11 1 Loop filter BW 127 kHz Type 1 in Table 1 18 The HMC832LP6GE features an internal AutoCal process that seamlessly calibrates the HMC832LP6GE when a frequency change is executed Once calibrated at any temperature the calibration setting holds across the entire operating range of the HMC832LP6GE 40 C to 85 C Figure 30 shows that the tuning voltage of the HMC832LP6GE is maintained within a narrow operating range for worst case scenarios where calibration was executed at one temperature extreme and the HMC832LP6GE is operating at the other extreme For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO t a LLI kt Z L z V A V gt QO m t a LLI Z L z V uM uM A edl TIttItE MICROWAVE CORPORATION v01 0812 RoHS v EART NDLY Figure 31 Current Consumption in Single Ended Output Configuration 1191 pt Output Gain 0 dB ME Output Gain 6 dB High Performance Mode
28. 8 250 3343 or apps hittite com V gt QO m t a D LLI a Z L z V ae A V gt QO m t a LLI Z L z V uM un A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Electrical Specifications Continued PLL RF Divider Characteristics 19 Bit N Divider Range Integer Max 219 1 524 287 19 Bit N Divider Range Fractional Menem Dene ion 524 283 REF Input Characteristics Max Ref Input Frequency Ref Input Level Ref Input Capacitance 14 Bit R Divider Range Phase Detector PD 2 PD Frequency Fractional Mode PD Frequency Integer Mode Charge Pump Output Current Charge Pump Gain Step Size BEEN mA UA PD Charge Pump SSB Phase Noise 1 kHz dBc Hz 10 kt rad 2 dB tor Fractional 459 Bor 100 kHz Add dB tor Fractional 45 ao Logic Inputs Logic Outputs momoe O O 9 CSV aowa O 9 C CMS owmamemws O O 9 OO wemmuwonn 1 C I Power Supply Voltages AVDD VCCHF VCCPS 3 3 V Supplies VCCPD RVDD DVDD VPPCP 3 1 3 3 3 5 V VDDLS VCC1 VCC2 1 Measured with 100 O external termination See Reference Input Stage section for more details 2 Slew rate of gt 0 5 ns V is recommended see Reference Input Stage section for more details Frequency is guaranteed across process voltage and temperature fro
29. 80 Pe ee ee ee eee Low Current Mode VCO_Reg03h 10 1d Daun SSB Integrated Phase Noise 64 3 dBc rM 9o a png 1 Integration Bandwidth 1 kHz to 100 MHz rida amara t SNR 61 3 EVM 0 086 95 Phase Noise 2 1 moi i reHon Bandwidth 1 kHz to 100 He PHASE NOISE dBc Hz Bio a Made Woo RegO3h 10 o z SSB Integrated Phase Noise 65 5 dBc Integration Bandwidth 1 kHz to 100 MHz SNR 62 5 dB EVM 0 075 Phase Noise Integration Bandwidth 1 kHz to 100 MHz OFFSET Hz Figure 9 Fractional Spurious Performance at 2118 24 MHz Exact Mode ON s 60 ON Current Mode UBL PEA 1d SSB Integrated Phase Noise 57 dBc Integration Bandwidth 1 kHz to 100 MHz SNR 54 EVM 0 199 Phase Noise Integration Bandwidth 1 kHz to 100 MHz PHASE NOISE dBc Hz High Performance Mode vco Reg03h 10 30 SSB Integrated Phase Noise 57 45 dBc Integration Bandwidth 1 kHz to 100 MHz SNR 54 45 dB EVM 0 189 Phase Noise Integration Bandwidth 1 kHz to 100 MHz LEETE 1 loot E 10 10 10 10 10 10 OFFSET Hz Figure 11 Fractional Spurious Performance at 2646 96 MHz Exact Frequency Mode ON r pdt 1 1 Low Current Mode VCO_Reg03h 10 1d 80 22t eau cac 2 22 SSB Integrated Phase Noise 55 6 dBc VO E GE rou Integration Bandwidth 1 kHz to 100 MHz raga 1 a 1 SNR 52 6 EVM 0 234 Phase Noise pu arg Integration Bandwidth 1 kHz to 100 MHz ayni 100
30. 832LP6GE SPI interface will not function In that case it is necessary to cycle the power to the OFF and ON and repeat the recommended sequence above hold both signals low at power up and ensure that the first rising edge occurs on the SCK line 1 10 2 Serial Port WRITE Operation AVDD DVDD 3V AGND DGND OV Table 5 SPI Timing Characteristics SE n eter C ns 2 PRecoveryTime E A typical WRITE cycle is shown in Figure 48 a The Master host places 24 bit data d23 d0 MSB first on SDI on the first 24 falling edges of SCLK b the slave HMC832LP6GE shifts in data on SDI on the first 24 rising edges of SCLK For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz c Master places 5 bit register address to be written to r4 r0 MSB first on the next 5 falling edges of SCLK 25 29 d Slave shifts the register bits on the next 5 rising edges of SCLK 25 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 30 32 Hittite reserves chip address a2 a0 000 for all RF PLL with Integrated VCOs f Slave shifts the chip address bits on the next 3 rising edges of SCLK
31. ART NDLY 2 9 Reg 07h Lock Detect Register Default 00014Dh Name Bit Type Width l Enable Internal Lock Detect see section 1 10 SERIAL PORT sa RW Reed 2 o Remd SSCS Lock Detection Window Timer Selection Lock Detect Window type 1 Digital programmable timer It lock detect window sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0 5 1 32 2 96 3 4 5 6 7 5d 0 Analog one shot nominal 10 ns window 0 Lock Detection Digital Window Duration 0 1 2 cycle 1 cycle 2 cycles 4 cycles 8 cycles 16 cycles 32 cycles 64 cycles LD Digital Timer Freauenc Lock Detect Digital Timer Frequency Control 00 fastest 11 10 R W cua q y 11 slowest See section 1 5 5 Lock Detect for more information my RW feens a o Reewd O 13 R W Auto Relock One Try 1 1 Attempts to relock if Lock Detect fails for any reason Only tries once 2 10 Reg 08h Analog EN Register Default C1BEFFh L 1 1 5 Name Width Description Reserved VCO Buffer and Prescaler Bias Enable 1d s 3d aor 0 Pin LD_SDO disabled 1 and RegFh 7 1 Pin LD SDO is always driven this is required for use of GPO port 1 and RegFh 7 0 SPI LDO SPl is off if unmatched chip address is seen on the SPI allowing a shared SPI with other compatible parts 00 Program to 1 for XTAL 2
32. ED VCO 25 3000 MHz EART NDLY f fcd 9Cd fyco fep and hca 2 E foa 9Cd 2800 2 x 108 61 44 x 10 120x10 gt 61 44 x108 m 3750 Since EQ 16 is satisfied the HMC832LP6GE can be configured for exact frequency mode at fyco 2800 2 MHZ as follows f 2800 2 x106 1 Nyyr Reg 03h floor C9 floor 45d 2Dh INT feo 61 44 108 6 6 2 Reg OCh o SM _ 81 010 512d 200h ged fcosfop god 2800 2x10 61 44x108 3 To program Reg 04h the closest integer N boundary frequency f that is less than the desired VCO frequency fyco must be calculated fy fpp N nz Using the current example fy fop X Nr 45x 61 44 10 2764 8 MHz fos f 2 4 9800 2 x 10 2764 8 x 10 Heo UN ceil c led 9666560d 938000h 2 Then Reg04h cei 5 top 61 44x10 1 5 7 7 7 Hittite Exact Frequency Channel Mode If it is desirable to have multiple equally spaced exact frequency channels that fall within the same interval ie fy lt fycok lt fy where fyco is shown in Figure 47 and 1 lt k x 21 it is possible to maintain the same integer N Reg 03h and exact frequency register Reg OCh settings and only update the fractional register Reg 04h setting The Exact Frequency Channel Mode is possible if EQ 16 is satisfied for at least two equally spaced adjacent frequency channels i e the channel step Size To configure the HMC832LP6GE
33. LI Z L z V a A QU O O gt C m t a LLI Z L z QU EN ur A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz 3 4 VCO Reg 03h Config Selects output noise floor performance level at a cost of increased current consumption Programmable Performance Mode 01 Low Current Consumption Mode 11 High Performance Mode Other states 00 and 10 not supported Enables the output on RF P pin HF P output enable Required for differential operation or single ended output on RF P pin Enables the output on RF N pin RF N output enable Required for differential operation or single ended output on RF N pin 0 Return Loss 5 dB Typical Highest output power Defines when the Mute Function is enabled the output is muted see section 1 4 4 and Figure 35 for more information 00 Mute enabled when divide ratio VCO Reg 02h 5 0 0 This enables the HMC832LPGGE to 8 7 Mute Mode be backwards compatible to HAC830LP6GE mute function 01 During VCO Calibration See 1 4 1 VCO Calibration section for more details e 10 Not supported e 11 Mute all RF outputs unconditional 3 9 VCO Reg 04h Cal Bias Specified performance is only guaranteed with the required settings in this table Other settings are not audiuit E Name Wieth Detau Lm owe muse s mu mememu 00 3 6 VCO RegO05h CF Cal
34. R 1 and m O Figure 43 hence Tgs 20 ns 50 MHz Note when using AutoCal the maximum AutoCal Finite State Machine FSM clock cannot exceed 50 MHz see Reg OAh 14 13 The FSM clock does not affect the accuracy of the measurement it only affects the time to produce the result This same clock is used to clock the 16 bit VCO serial port If time to change frequencies is not a concern then one may set the calibration time for maximum accuracy and therefore not be concerned with measurement resolution Using an input crystal of 50 MHz R21 and fpd 50 MHz the times and accuracies for calibration using EQ 6 and EQ 8 are shown in Table 2 Where minimal tuning time is 1 8 of the VCO band spacing Across all VCOs a measurement resolution better than 800 kHz will produce correct results Setting m 0 n 5 provides 781 kHz of resolution and adds 8 6 us of AutoCal time to a normal frequency hop Once the AutoCal sets the final switch value 8 64 us after the frequency change command the fractional register will be loaded and the loop will lock with a normal transient predicted by the loop dynamics Hence as shown in this example that AutoCal typically adds about 8 6 us to the normal time to achieve frequency lock Hence AutoCal should be used for all but the most extreme frequency hopping requirements For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax
35. RPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY sn LD SDU vo sme VCO SUBSYSTEM VCO RegOt1h 0 Performance Tuning Master Enable VCO Subsystem VCO RegO h 5 vco VCO _RegO03h 2 VSPI CONTROL 1 2 4 6 62 VCO RegO1h 3 EN a VCO Reg02h 5 0 VCO_RegO3h 3 L CONTROL CAL VCO RegO7h 3 0 MODULATOR VCO RegO1h 2 i VTUNE VCO_RegOth 1 EN VCO CAL VCO_RegOOh 8 1 VOLTAGE vco RegOOh 0 CHARGE CP LOOP PUMP FILTER XREFP Mm R DIVIDER V gt QO m t a LLI Z L z QU uM A Figure 40 PLL and VCO Subsystems 1 4 1 VCO Calibration 1 4 1 1 VCO Auto Calibration AutoCal The HMC832LP6GE uses a step tuned type VCO A simplified step tuned VCO is shown in Figure 41 A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center frequency of the VCO to be adjusted or stepped by switching in out VCO tank capacitors A step tuned VCO
36. VCO with a fundamental frequency of 1500 MHz 3000 MHz and an integrated VCO Output Divider divide by 1 2 4 6 60 62 that enables the HMC832LP6GE to generate continuous frequencies from 25 MHz to 3000 MHz The integrated Phase Detector PD and delta sigma modulator capable of operating at up to 100 MHz permit wider loop bandwidths and faster frequency tuning with excellent spectral performance Industry leading phase noise and spurious performance across all frequencies enable the HMC832LP6GE to minimize blocker effects improve receiver sensitivity and transmitter spectral purity Low noise floor 160 dBc Hz eliminates any contribution to modulator mixer noise floor in transmitter applications The HMC832LP6GE is footprint compatible to the market leading HMC830LP6GE PLL with Integrated VCO It features all 3 3 V supply and an innovative Programmable Performance technology that enables the HMUC832LP6GE to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for an improved noise floor performance Additional features of the HMC832LP6GE include 12 dB of RF output gain control in 1 dB steps Output Mute function to automatically mute the output during frequency changes when the device is not locked Selectable output return loss Programmable differential or single ended outputs with the ability to select either output i
37. VCO_Reg03h 1 0 3d Li l I LI I LI L l LI l l I 1 I l Li I I 1 E IL L I Il m m m I LI i LI i LI I I l I LI I I l L 1 l 1 1 7 l Li L 1 Low Current i Consumption Mode VCO_Reg03h 1 0 1d CURRENT CONSUMPTION mA 500 1000 1500 2000 2500 3000 OUTPUT FREQUENCY MHz Figure 33 Reference Input Sensitivity Square Wave i 234 232 230 FOM dBc Hz 224 L X 14 MHz Square Wave 25 MHz Square Wave 50 MHz Square Wave 100 MHz Square Wave 15 12 9 6 3 0 3 REFERENCE POWER dBm Figure 35 Mute Mode Isolation 211 10 Signal on RF N pin when RF N pin Off RF P pin On VCO Reg3h 3 2 1d Mute Off On only during VCO Calibration VCO RegO03h 8 7 1d Both RF N amp RF P pins Off VCO Reg3h 3 2 0d Mute Off On only during VCO K Calibration VIN Shain ns 10 ISOLATION dB 3000 100 1000 FRQUENCY MHz HMC832LP6GE FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Figure 32 Current Consumption in Differential Output Configuration s 260 K Fo 62 p e Output Gain 0 dB M Output Gain 6 dB High Performance Mode m VCO_Reg03h 1 0 3d Low Current Consumption Mode voo_ Reg03h 1 0 1d CURRENT CONSUMPTION mA 500 1000 1500 2000 2500 3000 OUTPUT FREQUENCY MHz Figure 34 Reference Input Sensitivity Sinusoidal Wave 201 235 230 225 N 220 T o co 2 215 210 rol
38. Y EART NDLY solu D RV te Maximum Ratings CPD 0 3 V to 3 6 V 0 3 V to 3 6 V 0 3 V to 3 6 V 40 C to 85 C 65 C to 150 C Ab HMC832LP6GE FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 150 C 260 C Class 1B Recommended Operating Conditions Temperature Supply Voltage AVDD RVDD DVDD VCCPD VCCHF T T VCCPS VPPCP VDDLS VCC1 VCC2 i 1 Layout design guidlines set out in Qualification Test Report are strongly recommended For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Outline Drawing TOP VIEW BOTTOM VIEW 240 530 Dus 5 90 40 31 LOT NUMBER 387 475 lt ouane 008 0 20 MIN 035 0 90 ME aL 012 0 30 REF 031 0 80 ee
39. a 14 MHz sin A 25 MHz sin Pod 50 MHz sq 205 100 MHz sq REFERENCE POWER dBm 19 Output Gain is configured in VCO_Reg 07h 3 0 Differential or single ended mode programmed in VCO_Reg O3h 3 2 20 Measured from a 50 O source with a 100 external resistor termination 21 The HMC832LP6GE features a configurable mute mode along with the ability to independently turn off outputs on both RF N and RF P output pins Figure 35 shows isolation measured at the output when the mute mode is on VCO Reg 03h 8 7 3d and when the mute mode is off VCO_ Reg 03h 8 7 1d with either both outputs disabled VCO Reg O03h 3 2 0 or one output enabled and the other disabled VCO Reg 03h 3 2 1d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz NDLY Table 1 Loop Filter Designs Used in Typical Performance Characteristics Graphs 22 Loop Filter Type 1 is suggested to use for best integrated phase noise It is designed for 50 MHz PD frequency CP 2 mA in Fractional Mode 23 Loop Filter Type 2 is suggested to use for best far out phase noise It is designed for 50 MHz PD frequenc
40. allows the user to center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near the mid voltage tuning point of the HMC832LP6GE s charge pump This enables the PLL charge pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning sensitivity kvco The VCO switches are normally controlled automatically by the HMC832LP6GE using the Auto Calibration feature The Auto Calibration feature is implemented in the internal state machine It manages the selection of the VCO sub band capacitor selection when a new frequency is programmed The VCO switches may also be controlled directly via register Reg 05h for testing or for other special purpose operation Other control bits specific to the VCO are also sent via Reg O5h For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 EART RoHS vV NDLY FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Figure 41 Simplified Step Tuned VCO To use a step tuned VCO in a closed loop the VCO must be calibrated such that the HMC832LP6GE knows which switch position on the VCO is optimum for the desired output frequency The HMC832LP6GE supports Auto Calibration A
41. by the Correction Rate Must be an integer Frequencies at exactly the correction rate will have zero frequency error 0 Disabled 1 Disabled 2 16383d SFFFh For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY 2 15 Reg OFh GPO SPI RDIV Register Default 000001h lsignal selected here is output to SDO pin when enabled Data from RegOF 5 Lock Detect Output Lock Detect Trigger Lock Detect Window Output Ring Osc Test Pullup Hard from CSP PullDN hard from CSP Reserved Reference Buffer Output Ref Divider Output VCO divider Output Modulator Clock from VCO divider Auxiliary Clock R W gpo select Aux SPI Clock Aux SPI Enable Aux SPI Data Out PD DN PD UP SD3 Clock Delay SD3 Core Clock AutoStrobe Integer Write Autostrobe Frac Write Autostrobe Aux SPI SPI Latch Enable VCO Divider Sync Reset Seed Load Strobe 26 29 Not Used 30 SPI Output Buffer En 31 Soft RSTB GPO Test Data a 1 GPO Test Data 1 Outputs GPO data only guo pe 0 Automuxes between SDO and GPO data 1 LD SDO Pin Driver always on ii ER Driver AWAS N 0 LD_SDO Pin driver only on during SPI
42. der setting divide by 2 4 6 60 62 in VCO Reg O2h 5 0 The HMC832LP6GE automatically controls frequency tuning in the fundamental band of operation for more information see 1 4 1 1 VCO Auto Calibration AutoCal To tune to frequencies below the fundamental frequency range lt 1500 MHz it is required to tune the HMC832LP6GE to the appropriate fundamental frequency then select the appropriate output divider setting divide by 2 4 6 60 62 in VCO Reg O2h 5 0 1 5 7 1 Integer Mode The HMC832LP6GE is capable of operating in integer mode For Integer mode set the following registers a Disable the Fractional Modulator Reg 06h 11 20 b Bypass the Modulator circuit Reg O6h 7 7 In integer mode the VCO step size is fixed to that of the PD frequency Integer mode typically has 3 dB lower phase noise than fractional mode for a given PD operating frequency Integer mode however often requires a lower PD frequency to meet step size requirements The fractional mode advantage is that higher PD frequencies can be used hence lower phase noise can often be realized in fractional mode Charge Pump offset should be disabled in integer mode 1 5 7 2 2 Integer Frequency Tuning In integer mode the digital A gt modulator is shut off and the N divider Reg 03h may be programmed to any integer value in the range 16 to 219 1 To run in integer mode configure Reg O6h as described then program the integer portion of the frequency as explained b
43. der On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY 2 6 Reg 04h Frequency Register Fractional Part Default 000000h VCO Divider Fractional part 24 bit unsigned see Fractional Frequency Tuning Used in Fractional Mode only Nfrac Reg 04h 2 4 min Od max 274 1 2 7 Reg 05h VCO SPI Register Default 000000h 2 0 0 e VCO TER ID Internal VCO Subsystem 1D 6 3 RW VCO Subsystem register address 4 0 For interfacing with the VCO please see section 1 3 1 15 7 VCO Subsystem data 9 o Data to be written to the VCO Subsystem Note RegO5h is a special register used for indirect addressing of the VCO subsystem Writes to Reg O5h are automatically forwarded to the VCO subsystem by the VCO SPI state machine controller HegObh is a Read Write register However RegO5h only holds the contents of the last transfer to the VCO subsystem Hence it is not possible to read the full contents of the VCO subsystem Only the content of the last transfer to the VCO subsystem can be read Please take note special considerations for AutoCal related to Reg 05h 2 8 Reg 06h Delta Sigma Configuration Register Der 200B4Ah Selects the Seed in Fractional Mode 00 0 seed 01 Isb seed 02 B29D08h seed 03 5OF1CDh seed Note Writes to this regi
44. e PLL subsystem divides down the VCO output to the desired comparison frequency via the N divider integer value set in Reg O3h fractional value set in Reg 04h compares the divided VCO signal to the divided reference signal reference divider set in Reg 02h in the Phase Detector PD and drives the VCO tuning voltage via the Charge Pump CP configured in Reg 09h to the VCO subsystem Some of the additional PLL subsystem functions include e Delta Sigma configuration Reg 06h e Exact Frequency Mode Configured in Reg OCh Reg 03h and Reg 04h e Lock Detect LD Configuration Reg 07h to configure LD and Reg OFh to configure LD_SDO output pin e External CEN pin used as hardware PLL enable pin CEN pin does not affect the VCO subsystem Typically only writes to the divider registers integer part Reg O3h fractional part Reg 04h of the PLL subsystem are required for HMC832LP6GE output frequency changes Divider registers of the PLL subsystem Reg O3h and Reg 04h set the fundamental frequency 1500 MHz to 3000 MHz of the VCO subsystem Output frequencies ranging from 25 MHz to 1500 MHz are generated by tuning to the appropriate fundamental VCO frequency 1500 MHz to 3000 MHz by programming N divider Reg O3h and Reg 04h and programming the output divider divide by 1 2 4 6 60 62 programmed in VCO_Reg 02h in the VCO subsystem For detailed frequency tuning information and example please see 1 5 7 Frequency Tuning secti
45. e SPI mode of operation referred to in section 1 10 It should be noted that the VCO subsystem is not affected by the PLL soft reset the VCO subsystem registers can only be reset by removing the power supply For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz NOTE if external power supplies or regulators have rise times slower than 250 ys then it is advised to write to the SPI reset register Reg OOh 5 1 immediately after power up before any other SPI activity This will ensure starting from a known state 1 7 Power Down Mode Note that the VCO subsystem is not affected by the CEN or soft reset Hence device power down is a two step process First power down the VCO by writing O to VCO register 1 via Reg 05h and then power down the PLL by pulling CEN pin pin 17 low assuming no SPI overrides Reg O1h 0 1 This will result in all analog functions and internal clocks disabled Current consumption will typically drop below 10 pA in Power Down state The serial port will still respond to normal communication in Power Down mode It is possible to ignore the CEN pin by setting Reg 01h 0 0 Control of Power Down Mode then comes
46. e switching charge pump Reg O9h 6 0 or Reg O9h 13 7 If the result provided by EQ 10 is equal to 10 ns Analog LD can be used Reg 0O7h 6 0 Otherwise Digital LD is necessary Reg 07h 6 1 Table 4 provides the required Reg 07h settings to appropriately program the Digital LD window size From Table 4 simply select the closest value in the Digital LD Window Size columns to the one calculated in EQ 10 and program Reg 07h 11 10 and Reg 07h 9 7 accordingly a 4 Typical Digital Lock eee IPIDGOW P fam es pss pes m ses 5 ELI l N S i Lie d 1 5 5 2 Digital Window Configuration Example Assuming fractional mode with a 50 MHz PD and e Charge Pump gain of 2 mA Reg 09h 13 7 64h Reg O9h 6 0 64h e Up Offset Reg 09h 22 21 01 b e and Offset current magnitude of 400 pA Reg 09h 20 14 50h Applying EQ 10 the required LD window size is 0 4x10 A 1 7 2 66x10 R 50x10 Hz x 2x10 A fessi doses 50 x10 Hz LD Window seconds uo EE 591999 tin EQ 11 Locating the Table 4 value that is closest to the EQ 11 result in this case 13 3 13 33 To set the Digital LD window size simply program Reg 07h 11 10 10 b and Reg 07h 9 7 010 b according to Table 4 There is always a good solution for the lock detect window for a given operating point The user should understand however that one solution does not fit all operati
47. ee 002 0 05 eT ae Pe ee ee SEATING PLANE 003 0 08 c C o03 0 08 C ES dones PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY LEAD AND GROUND PADDLE PLATING 100 MATTE TIN DIMENSIONS ARE IN INCHES MILLIMETERS LEAD SPACING TOLERANCE IS NON CUMULATIVE PAD BURR LENGTH SHALL BE 0 15mm MAX PAD BURR HEIGHT SHALL BE 0 25mm MAX PACKAGE WARP SHALL NOT EXCEED 0 05mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN DM 2 D N o it ic F art Numbi MSL Rating In atinc MSL HMC832LP6GE RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 Um 1 4 Digit lot number XXXX For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI Z L z V A V gt QO m t a LLI Z L z V uM A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY Evaluation PCB
48. ency changes If AutoCal is disabled Reg OAh 11 1 a priori knowledge of the correct VCO switch setting and the corresponding adjustment to the VCO is required before executing the integer frequency change 1 4 4 VCO Output Mute Function The HMC832LP6GE features an intelligent output mute function with the capability to disable the VCO output while maintaining the PLL and VCO subsystems fully functional The mute function is automatically controlled by the HUC832LP6GE and provides a number of mute control options including 1 Automatically mute the outputs during VCO calibration that occurs during output frequency changes This mode can be useful in eliminating any out of band emissions during frequency changes and ensuring that the system emits only desired frequencies It is enabled by writing VCO Reg OSh 8 7 1d 2 Always mute VCO Heg 03h 8 7 3d This mode is used for manual mute control Typical isolation when the HMC832LP6GE is muted is always better than 50 dB and is 40 dB better than disabling the individual outputs of the HUC832LP6GE via VCO Heg 03h 3 2 as shown in Figure 35 Please refer to Figure 40 for more information Also note that the VCO subsystem registers are not directly accessible They are written to the VCO subsystem via PLL Reg 05h More information about VCO subsystem SPI in section 1 3 1 1 4 5 VCO Built in Test with AutoCal The frequency limits of the VCO can be measured using the BIST features of
49. es rapidly over a range much greater than 2m radians Since the gain of the PD varies linearly with phase up to 27 the gain of a conventional PD will cycle from high gain when the phase difference approaches a multiple of 2rr to low gain when the phase difference is slightly larger than a multiple of O radians The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle This can make the VCO frequency actually reverse temporarily during locking This phenomena is known as cycle slipping Cycle slipping causes the pull in rate during the locking phase to vary cyclically Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal Laplace analysis The HMC832LP6GE PD features an ability to reduce cycle slipping during acquisition The Cycle Slip Prevention CSP feature increases the PD gain during large phase errors The specific phase error that triggers the momentary increase in PD gain is set via Reg OBh 8 7 1 5 7 Frequency Tuning HMC832LP6GE VCO subsystem always operates in fundamental frequency of operation 1500 MHz to 3000 MHz The HMC832LP6GE generates frequencies below its fundamental frequency 25 MHz to 1500 MHz by tuning to the appropriate fundamental frequency and selecting the appropriate Output Divi
50. esrittite MICROWAVE CORPORATION v01 0812 HMC832LP6GE RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Features e HF Bandwidth e Fractional Figure of Merit FOM 226 dBc Hz 25 3000 MHz e 24 bit Step Size Resolution 3 Hz typical e 3 3 V Supply P Exact Frequency Mode with 0 Hz frequency error e Maximum Phase Detector Rate 100 MHz Fast Frequency Hopping 40 Lead 6x6 mm SMT Package 36 mm e Ultra Low Phase Noise 110 dBc Hz in Band Typ Typical Applications e Cellular Infrastructure CATV Equipment e Microwave Radio e WiMax WiFi DDS Replacement Military e Communications Test Equipment Tunable Reference Source for Spurious Free Performance Functional Diagram V gt QO m t a LLI Z EE z V uM un A AVDD SEN NC RF_P VPPCP RF_N CP VCC1 NC NC NC VCC2 VDDLS NC NC VTUNE NC NC RVDD NC GND For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY General Description The HMC832LP6GE is a 3 3 V high performance wide band Fractional N Phase Locked Loop PLL that features an integrated Voltage Controlled Oscillator
51. g Hittite Exact Frequency Mode If the constraint in EQ 16 is satisfied HMC832LPGGE is able to generate signals with zero frequency error at the desired VCO frequency Exact Frequency Mode may be re configured for each target frequency or be set up for a fixed f 4 which applies to all channels 1 5 7 6 1 1 Configuring Exact Frequency Mode For a Particular Frequency 1 Calculate and program the integer register setting Reg 03h Ny floor fyco fpp where the floor function is the rounding down to the nearest integer Then the integer boundary frequency fy Nint fpp 2 Calculate and program the exact frequency register value Reg OCh fpp fgcg where faca gcd fyco f ged 9CQ fyco fpp 224 too fy pp 3 Calculate and program the fractional register setting Reg 04h Neprac ceil where ceil is the ceiling function meaning round up to the nearest integer Example To configure the HMC832LP6GE for exact frequency mode at fyco 2800 2 MHz where Phase Detector PD rate fpp 61 44 MHz Proceed as follows Check EQ 16 to confirm that the exact frequency mode for this fyco is possible For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRAT
52. gn the loop filter for a particular application download Hittite s PLL Design software tool by clicking on the Software Download link on the HMC832LPG6GE product page at www hittite com Hittite PLL Design enables users to accurately model and analyze performance of all Hittite PLLs PLLs with Integrated VCOs and Clock Generators It supports various loop filter topologies and enables users to design custom loop filters and accurately simulate resulting performance For evaluation purposes the HUC832LP6GE evaluation board is shipped with an on board low cost low noise 100 ppm 50 MHz VCXO enabling evaluation of most parameters including phase noise without any external references Exact phase or frequency measurements require the HMC832LP6GE to use the same reference as the measuring instrument To accommodate this requirement the HMC8S32LPGGE evaluation board includes the HMC1031MS8E a simple low current integer N PLL that can lock the on board VCXO to an external 10 MHz reference input commonly provided by most test equipment To lock the HMC832LP6GE to external 10 MHz reference simply connect the external reference output to J5 input of the HUC832LP6GE evaluation board and change the HMC1031MS8E integer divider value to 5 by changing the switch settings D1 1 SW1 4 closed and DO O SW2 3 open for more information please see the HMC1031MS8E data sheet For price delivery and to place orders Hittite Microwave Corporation 2 Elizabe
53. ing edges of SCK 30 32 Chip address is always 000 b Slave shifts the chip address bits on the next 3 rising edges of SCK 30 32 Master asserts SEN after the 32nd rising edge of SCK gt ao gt Slave registers the SDI data on the rising edge of SEN i Master clears SEN to complete the the address transfer of the two part READ cycle j If one does not wish to write data to the chip at the same time as we do the second cycle then it is For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI Z L z V A I V gt C m t a LLI Z L z V uM uM A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle k Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK l Slave HMC832LP6GE shifts the SDI data on the next 32 rising edges of SCK m Slave places the desired read data ie data from the address specified in Reg OOh 7 3 of the first cycle on LD SDO which automatically switches to SDO mode from LD mode
54. ite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY Offset current When operating in Integer Mode simply disable CP offset in both directions Up and down by writing Reg 09h 22 21 00 b and set the CP Offset magnitude to zero by writing Reg O9h 20 14 O In Fractional Mode CP linearity is of paramount importance Any non linearity degrades phase noise and spurious performance In fractional mode these non linearities are eliminated by operating the PD with an average phase offset either positive or negative either the reference or the VCO edge always arrives first at the PD ie leads A programmable CP offset current source is used to add DC current to the loop filter and create the desired phase offset Positive current causes the VCO to lead negative current causes the reference to lead The CP offset is controlled via Reg 09h The phase offset is scaled from O degrees that is the reference and the VCO path arrive in phase to 360 degrees where they arrive a full cycle late The specific level of charge pump offset current Reg 09h 20 14 is provided in EQ 9 It is also plotted in Figure 45 vs PD frequency for typical CP Gain currents Required CP Offset min 4 310 x Fpp X lop 0 25 x lor EQ 9 where Fpp Comparison frequency of the Phase Detector Hz lcp is the full scale current setting A of the switching charge pu
55. keep the SDO driver always on This stops the LDO driver from tri stating and means that the SDO line cannot be shared with other devices The HMC832LP6GE will naturally switch away from the GPO data and export the SDO during an SPI read To prevent this automatic data selection and always select the GPO signal set Prevent AutoMux of SDO Reg OFh 6 1 The phase noise performance at this output is poor and uncharacterized Also the GPO output should not be toggling during normal operation because it may degrade the spectral performance Note that there are additional controls available which may be helpful if sharing the bus with other devices e To disable the driver completely set Reg O8h 5 O it takes precedence over all else e To disable either the pull up or pull down sections of the driver Reg OFh 8 1 or Reg OFh 9 1 respectively Example Scenarios e Drive SDO during reads tri state otherwise to allow bus sharing e No action required For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI I Z L V uM ae A V gt QO m t aH D LLI z L V uM A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812
56. lace orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI I Z L V uM ae A I V gt QO m t a LLI Z L z QU uM A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY f f locat ICA ycor fep and ooa 2 a Jena fgcd2 9Cd fycoo fep and hoaz 2 t 61 44 x108 fedi ged 2800 2x108 61 44x108 1205109 77757 9750 6 fyoaa god 2800 35109 61 44 5109 20510 gt SUC S750 If EQ 16 is satisfied for at least two of the equally spaced interval channel frequencies fyco7 fycoa fyvco3 fycow aS it is above Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies and can be configured as follows 2800 2 x 10 1 R h floor YES floor 5 45d 2Dh Reg 03h A 61 44 x 106 6 fop _ 61 44x10 _ 61 44x10 3072d COOh Bee x REN ged 100x108 61 44x108 20000 where fycok 1 fycoy is the desired channel spacing 100 kHz in this example 3 To program Reg 04h the closest integer N boundary frequency fy that is less than the smallest channel VCO frequency fyco must be calculated fy floor fyco fpp Using the current
57. led allowing manual VCO tuning Refer to section 1 4 1 6 for a description of manual tuning For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI a Z L V a A I V gt QO m t a LLI Z L z V uM A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz 1 4 1 2 2 AutoCal Use of Reg05h AutoCal transfers switch control data to the VCO subsystem via Reg 05h The address of the VCO subsystem in Reg 05h is not altered by the AutoCal routine The address and ID of the VCO subsystem in Reg 05h must be set to the correct value before AutoCal is executed For more information see section 1 3 1 1 4 1 3 3 Auto reLock on Lock Detect Failure It is possible by setting Reg O7h 13 to have the VCO subsystem automatically re run the calibration routine and re lock itself if Lock Detect indicates an unlocked condition for any reason With this option the system will attempt to re Lock only once 1 4 1 4 4 VCO AutoCal on Frequency Change Assuming Reg OAh 771 0 the VCO calibration starts automatically whenever a frequency change is requested If it is desired to rerun the Au
58. lly still operate but with degraded reference path phase noise performance Table 3 Reference ill A Table Input referred phase noise of the PLL when operating at 50 MHz is between 148 and 150 dBc Hz at 10 kHz offset depending upon the mode of operation The input reference signal should be 10 dB better than this floor to avoid degradation of the PLL noise contribution It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required for the system goals For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz 1 5 3 Reference Path R Divider The reference path R divider is based on a 14 bit counter and can divide input signals by values from 1 to 16 383 and is controlled via Reg O2h 1 5 4 RF Path N Divider The main RF path divider is capable of average divide ratios between 219 5 524 283 and 20 in fractional mode and 219 1 524 287 to 16 in integer mode The VCO frequency range divided by the minimum N divider value will place practical restrictions on the maximum usable PD frequency For example a VCO operating at 1 5 GHz in fractio
59. loop filter bandwidth and higher phase margin 0 20 40 60 80 100 120 140 160 TIME us Figure 30 Typical Tuning Voltage After Calibration 151 Calibrated at 85C measured at 85C Calibrated at 85 measured at 40C Calibrated at 40C measured at 40C Calibrated at 40C measured at 85C Calibrated at 27C measured at 27C l l i ATT T M du M j e AM n TUNE VOLTAGE AFTER CALIBRATION V 0 1 1 1 1 1 1 1 1 1 1 L y L LI I L 1 1330 1520 1710 1900 2090 2280 2470 2660 2850 3040 VCO FREQUENCY MHz 16 The HMC832LP6GE features an internal AutoCal process that seamlessly calibrates the HMC832LP6GE when a frequency change is executed Typical frequency settling time that can be expected after any frequency change Reg 03h or Reg 04h writes is shown in Figure 25 with AutoCal enabled Reg OAh 11 0 Frequency hop of 5 MHz is shown in Figure 25 however the settling time is independent of the size of the frequency change Any size frequency size hop will have a similar settling time with AutoCal enabled Loop filter BW 127 kHz Type 1 in Table 1 17 For applications that require fast frequency changes the HMC832LP6GE supports manual calibration that enables faster settling times Manual calibration needs to be executed only once for each individual HMC832LP6GE at any temperature and is valid across all temperature operating range of the HMC832LP6GE More information about manual calibration is available in section 1 4 1
60. m 40 C to 85 C 3 This maximum PD frequency can only be achieved if the minimum N value is respected eg In the case of fractional mode the maximum PD frequency fvco 20 or 100 MHz whichever is less For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY Electrical Specifications Continued Units r A Da QO Power Supply Currents Gain 11 VCO Reg 07h 3 0 110 Single Ended Output VCO Reg 03h 3 2 2d 2500 800 MHz Gain 6 VCO Reg 2500 07h 3 0 6d Differential Output VCO Reg 03h 3 2 3d Gain 1 VCO_Reg 07h 3 0 1d High Performance Mode VCO_Reg 03h 1 0 23d 41 800 MHz aE Pfs NEN NNNM 210 NEN Ll EEJ E Differential Output VCO_Reg 03h 3 2 3d 800 MHz Gain 6 VCO_Reg 07h 3 0 6d Differential Output VCO Reg 03h 3 2 3d Gain 1 VCO Reg 07h 3 0 1d Differential Output VCO_Reg 03h 3 2 800 MHz JE 3d Heg 01h20 Power Down Crystal Off Crystal Not Clocked 10 Reg 01hz0 Power Down Crystal On 100 MHz Crystal Clocked 100 MHz Power on Reset Power on Reset
61. mp set in Reg 09h 6 0 Reg O9h 13 7 N Q O CP Current 2 5 mA o e eo o1 e eo CP Current 2 mA A O O 09 Q O N Q O RECOMMENDED OFFSET CURRENT uA o e o 0 20 40 60 80 100 PHASE DETECTOR FREQUENCY MHz Figure 45 Recommended CP offset current vs PD frequency for typical CP gain currents Calculated using EQ 9 The required CP offset current should never exceed 25 of the programmed CP current It is recommended to enable the Up Offset and disable the Down Offset by writing Reg 09h 22 21 01 b Operation with CP offset influences the required configuration of the Lock Detect function Refer to the description of Lock Detect function in section 1 5 5 1 5 1 4 Phase Detector Functions Phase detector register Reg OBh allows manual access to control special phase detector features Setting Reg OBh 5 0 masks the PD up output which prevents the charge pump from pumping up Setting Reg OBh 6 2 0 masks the PD down output which prevents the charge pump from pumping down Clearing both Reg OBh 5 and Reg OBh 6 tri states the charge pump while leaving all other functions operating internally For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D
62. n single ended mode and a delta sigma modulator Exact Frequency Mode which enables users to generate output frequencies with O Hz frequency error Electrical Specifications VPPCP VDDLS VCC1 VCC2 3 3 V RVDD AVDD DVDD VCCPD VCCHF VCCPS 3 3 V Min and Max Specified across Temp 40 C to 85 C DUEEAMMLLLLHLHULLLHULLL L M E IRE E A O ne n 7 y Wagn ee i gd Dew re Em pd n oS ID ATA Cy nn Ny vr Fat 1Cle r UC OII VIHTI yP pan EN EE FRONS _ E EN D RF Output Characteristics pE Output Frequency VCO Frequency at PLL Input RF Output Frequency at fyco Output Power Max Gain Setting VCO_Reg 07h 3 0 11d RF Output Power at fundmental frequency Single Ended 2000 MHz Across all Frequencies see Figure 22 Gain setting 6 VCO_Reg 07h 3 0 6d Differential Output Power Control range 1 dB Steps Harmonics for Fundamental Mode fo Mode at 2 GHz 2nd 3rd 4th fo 2 Mode at 2GHz 2 1 GHz 2nd 3rd 4th fo 30 Mode at 3 GHz 30 100 MHz 2nd 3rd 4th fo 62 Mode at 1550 MHz 62 25 MHz VCO Output Divider VCO RF Divider Range 1 2 4 6 8 62 2nd 3rd 4th For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 97
63. n the Software Download link on the HUC832LP6GE product page at www hittite com Programmable Performance Technology For low power applications that don t require maximum noise floor performance the HMC8S32LPGGE features the ability to reduce current consumption by 50 mA power consumption by 165 mW at the cost of decreasing phase noise floor performance by 5 dB High performance is enabled by writing VCO Reg O3h 1 0 3d and disabled Low Current Consumption Mode enabled by writing VCO Reg O3h 1 0 1d High performance mode improves noise floor performance at the cost of increased current consumption Resulting current consumption and phase noise floor performance are shown in Figure 31 and Figure 32 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz 1 0 Theory of Operation The HMC832LP6GE PLL with Integrated VCO is comprised of two sub systems PLL subsystem and VCO subsystem as shown in Figure 39 CONTROL CHARGE MODULATOR VSPI PUMP DETECTOR R PLL Buff DIVIDER PLL Only PLL Buff EN PHASE FREQUENCY Figure 39 HMC832LP6GE PLL and VCO Subsystems 1 1 PLL Subsystem Overview Th
64. n writes to Reg 05h Set the AutoCal FSM and VSPI Clock 50 MHz maximum 0 Input Crystal Reference 14 13 FSM VSPI Clock Select 2 1 1 Input Crystal Reference 4 2 Input Crystal Reference 16 3 Input Crystal Reference 32 mus Ww mmm 2 9 Reme For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com I 2 V gt QO m t a D LLI Z L z QU l ae A QU O gt QO m t a LLI Z L z QU uM e A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz 2 13 Reg OBh PD Register Default OF8061h E SIRE 7 zT XS vviatn Default Vescription Name Type ss E R W 5 a aw mum 3 Cycle Slip Prevention Mode Extra current is driven into the loop filter when the phase error is larger than 0 Disabled 8 7 R W CSP Mode 2 1 5 4ns 2 14 4ns 3 24 1ns This delay varies by 10 with temperature and 12 with process Force CP UP oa o Forces CP UP output on Use for Test only 10 Force CP DN Oaa 0 Forces CP DN output on Use for Test only 2 14 Reg OCh Exact Frequency Mode Register Default 000000h 2 0 Comparison Frequency divided
65. nal mode with a minimum N divider value of 20 will have a maximum PD frequency of 75 MHz 1 5 5 Lock Detect The Lock Detect LD function indicates that the HMC832LP6GE is indeed generating the desired frequency It is enabled by writing Reg 07h 3 1 The HMC832LP6GE provides LD indicator in one of two ways e As an output available on the LD_SDO pin of the HUC832LP6GE Configuration is required to use the LD_SDO pin for LD purpose for more information please see 1 10 SERIAL PORT and 1 5 5 3 Configuring LD_SDO Pin for LD Output section e Or reading from Reg 12h 1 where Reg 12h 1 1 indicates locked and Reg 12h 1 0 indicates an unlocked condition The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a user specified time period window repeatedly Either signal may arrive first only the difference in arrival times is significant The arrival of the two edges within the designated window increments an internal counter Once the count reaches and exceeds a user specified value Reg 07h 2 0 the HUC832LP6GE declares lock Failure in registering the two edges in any one window resets the counter and immediately declares an un locked condition Lock is deemed to be reestablished once the counter reaches the user specified value Reg 07h 2 0 again The HMC832LP6GE supports two lock detect modes e Analog LD that only supports a fixed window size of 10 ns Analog LD mode is
66. nce and following procedure discussed in 11 See HMC832LP6GE Application Information section for more details Contact Hittite Apps Support to obtain the required configuration to achieve similar spurious performance throughout the operating range of the HMC832LP6GE For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO t a LLI Z L V uM x A V gt QO m t a LLI Z L z V uM uM A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY Figure 19 Single Sideband Integrated Figure 20 Figure of Merit Phase Noise High Performance Mode 31 50 So 0 446 i 7 0 141 T s Typ FOM vs Offset 0 0447 E 2 FOM Floor m FOM 1 f folie E 0 0141 3 0 0045 OUTPUT FREQUENCY MHz OFFSET Hz Figure 21 Typical Single Ended Output Figure 22 Typical Output Power vs Power vs Frequency Mid Gain Setting 6 Frequency and Gain Single Ended 15 T 20 7 a 7 10 Shes eo Jo toe td M PEU N E E ce to at me Sh ce E E E EE go E O O a T E 0 n Gain Setting 5 ee 5 E VCO RegO7h 30 2 5d Y 1 i a E E o 5 Return Loss VCO_RegO3h 5 1
67. ncy of 1402 5 MHz is achieved by programming the 19 bit binary value of 56d 38h into intg_reg in Reg O3h and the 24 bit binary value of 1677722d 19999Ah into frac reg in Reg 04h The 0 596 Hz quantization error can be eliminated using the exact frequency mode if required In this example the output fundamental is divided by 2 Specific control of the output divider is required See section 3 0 and description for more details 1 5 7 5 5 Exact Frequency Tuning Due to quantization effects the absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fractional modulator For example a 24 bit fractional modulator has frequency resolution set by the phase detector PD comparison rate divided by 224 The value 224 in the denominator is sometimes referred to as the modulus Hittite PLLs use a fixed modulus which is a binary number In some types of fractional PLLs the modulus is variable which allows exact frequency steps to be achieved with decimal step sizes Unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period channel step size For this reason Hittite PLLs use a large fixed modulus Normally the step size is set by the size of the fixed modulus In the case of a 50 MHz PD rate a modulus of 224 would result in a 2 98 Hz step resolution or 0 0596 ppm In some applications it is necessary to have exact frequency steps and even an error of
68. ndant upon the reference in use The HMC832LP6GE in fractional mode can achieve frequencies at fractional multiples of the reference The frequency of the HMC832LP6GE fvco is given by tal fico Nint Nirac fint frac EQ 12 Lures K EQ 13 Where Lond is the output frequency after any potential dividers k is 1 for fundamental or k 2 2 4 6 58 60 62 depending on the selected output divider value Reg O5h 5 0 indirectly to VEO Reg O2h 5 0 Nint is the integer division ratio Reg O3h an integer number between 20 and 524 284 sac is the fractional part from 0 0 to 0 99999 N 4 Reg 04h 224 R is the reference path division ratio Reg 02h Lai is the frequency of the reference oscillator input fod is the PD operating frequency f 4 R As an example fout 1402 5 MHz k 2 fen 2 805 MHz Pos 50 MHz R fod 50 MHz Nint 56 Nise z0 1 Heg 04h round 0 1 x 224 round 1677721 6 1677722 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY 50e6 1677722 fyco EJ 56 2805 MHz 1 192 Hz error EQ 14 fyco iG E 1402 5 MHz 0 596 Hz error EQ 15 In this example the output freque
69. ng points As observed from EQ 10 If charge pump offset or PD frequency are changed significantly then the lock detect window may need to be adjusted 1 5 5 3 Configuring LD SDO Pin for LD Output Setting Reg OFh 7 7 and Reg OFh 4 0 7 will display the Lock Detect Flag on LD SDO pin of the HMC832LP6GE If locked LD SDO will be high As the name suggests LD SDO pin is multiplexed between LD and SDO Serial Data Out signals Hence LD is available on the LD_SDO pin at all times For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz except when a serial port read is requested in which case the pin reverts temporarily to the Serial Data Out pin and returns to the Lock Detect Flag after the read is completed LD can be made available on LD SDO pin at all times by writing Reg OFh 6 1 In that case the HMC832LP6GE will not provide any read back functionality because the SDO signal is not available 1 5 6 Cycle Slip Prevention CSP When changing VCO frequency and the VCO is not yet locked to the reference the instantaneous frequencies of the two PD inputs are different and the phase difference of the two inputs at the PD vari
70. on 1 2 VCO Subsystem Overview The VCO subsystem consists of a capacitor switched step tuned VCO and an output stage In typical operation the VCO subsystem is programmed with the appropriate capacitor switch setting which is executed automatically by the PLL subsystem AutoCal state machine if AutoCal is enabled Reg OAh 11 0 see section 1 4 1 VCO Calibration for more information The VCO tunes to the fundamental frequency 1500 MHz to 3000 MHz and is locked by the CP output from the PLL subsystem The VCO subsystem controls the output stage of the HMC8S2LPG6GE enabling configuration of e User defined performance settings Programmable Performance Technology configured via VCO_ Heg O3h 1 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI Z L V uM ae A I V gt QO m T a LLI Z L z V uM e A edl TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz e VCO Output divider settings configured in VCO Heg 02h divide by 2 4 6 60 62 to generate frequencies from 25 MHz to 1500 MHz or divide by 1 to generate fundamental frequencies between 1500 MHz and 30
71. pplication Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Figure 14 Typical Spurious Emissions at 2000 1 MHz Fixed Reference n T E ee of ome GUT EART NDLY Figure 13 Low Frequency Performance 1 120 x S a pu WT MEE T a u Mu iii OMMzOUBdm cillum iiis 7 O bdu O 2 Z LLI LLI 6 P ep i i OFFSET Hz OFFSET Hz Figure 15 Typical Spurious Emissions at Figure 16 Typical Spurious vs Offset from 2000 1 MHz Tunable Reference n 2 GHz Fixed vs Tunable Reference n21 80 70 2 100 Je s Da a i unm m E g n AMNEM i 80 Typical Spurios VS Offset ewe d bO Wht cole XI m Fixed Reference 50 MHz ui Eu ui Ce O AGG coa Gasca OQ 90 z aa O Z Z D 3t a a ee eee i 140 E xul E Typical Spurious vs Offset from 2 GHz a a Tunable Reference 47 5 MHz i 160 110 a 180 120 Aw WES A 2000 010 2000 100 2001 OFFSET Hz OUTPUT FREQUENCY kHz Figure 17 Open Loop Phase Noise Figure 18 Open Loop Phase Noise vs Temp 40 M rr 100 High Performance Mode On ti Ceci 2 oe WL VCO_Reg 3h 1 0 Sd i533 410 i NNNM T ae oe MiModos E 2854 MHz ind l c 2453 MHz i L ub X oa 3p A 1 MHz Offset 2013 MHz S aL cor wet 1 a a All Modes D 1587 MHz T dune ue ee 2 S 140 0 o i I 150 16
72. ps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz Reg 05h 6 3 0001 VCO subsystem register address Heg O5h 7 1 Master enable Heg O5h 8 1 VCO enable Heg O5h 9 1 PLL Buffer enable Heg O5h 10 1 IO Master enable Reg O5h t1 1 Reserved Heg 05h 12 0 Disable the output stage Reg 05h 14 13 01 b Reg 05h 15 1 don t care 3 3 VCO_Reg 02h VCO Output Divider BY Ty f JT Mute the Output when VCO Reg OS3h 8 7 Od s FO Fo 2 invalid defaults to 2 Fo 4 invalid defaults to 4 HF Divide ratio Fo 6 60 Fo 60 61 invalid defaults to 60 62 Fo 62 gt 62 invalid defaults to 62 L Gs wo resa 3 o Reewd For example to write O 1111 1110 into VCO Heg 02h VCO subsystem VCO ID 000 b and set the VCO output divider to divide by 62 the following needs to be written to Reg 05h O 1111 1110 0010 000 b Reg 05h 2 0 000 subsystem ID O Heg 05h 6 3 2 0010 VCO register address 2d Heg 05h 16 7 O 1111 1110 Divide by 62 max output RF gain For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t aH L
73. r 0 081 1605MHz EVM 57 2 dB or 0 138 2505 MHz EVM 53 9 dB or 0 204 OFFSET Hz Figure 4 Closed Loop Phase Noise at 1800 Miz ones iis 1 to 62 2 100 PHASE NOISE dBc Hz OFFSET Hz Figure 6 Closed Loop Phase Noise at 3000 MHz Divided by 1 to 62 iz 100 110 x 120 130 140 PHASE NOISE dBc Hz 150 e LHUR 170 aranan iii 1 Larga 1 Horry 1 AMEN 10 10 10 10 10 10 OFFSET Hz 6d and in High Performance Mode VCO_Reg 03h 1 0 3d Loop Filter designs are provided in Table 1 Phase Noise integrated from 1 kHz to 100 MHz 2 PD frequency loop filter bandwidth 75 kHz Type 2 from Table 1 Only a subset of available output divide ratios is shown Full range of output divide values includes 1 2 4 6 8 58 60 62 High Performance Mode selected VCO Reg 0O3h 1 0 3d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO t a D LLI Z L z V A I V gt QO m t or LLI Z L z V uM al A edl TIttItE MICROWAVE CORPORATION v01 0812 RoHS v EART NDLY Figure 7 Fractional Spurious Performance at 904 MHz Exact Frequency Mode ON n 60
74. read cycle 2 16 Reg 10h VCO Tune Register eo mou Ie f Read Only Register Indicates the VCO switch setting selected by the AutoCal state machine to yield the nearest free running VCO frequency to the desired operating frequency Not valid when Reg10h 8 1 AutoCal Busy Note if a manual change is done to the VCO switch settings this register will not indicate the VCO Switch Setting current VCO switch position 0 highest frequency 1 2 2nd highest 256 lowest frequency Note VCO subsystems may not use all the MSBs in which case the unused bits are don t care Busy when AutoCal state machine is searching for the 8 AutoCal Busy 1 nearest switch setting to the requested frequency For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com I V gt QO m t a D LLI Z L z QU EM A QU O O gt QO m t a LLI z L z QU EN e A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz EART NDLY 2 17 Reg 11h SAR Register I orem 8 0 0 m SAR Error Mag ag Counts aa me SAR Error Magnitude gt Counts 19 RO SAR Error Sign at 6 7 SAR Error Sign 0 ve 1
75. s Phase Error i FREQUENCY ERROR GHz 0 20 40 60 80 100 120 140 160 TIME us Figure 27 Frequency Settling After erequency ange Manual Calibration 71 2 51 Settling Time to lt ET Degrees eo a oe CRM Phase Error i l 2 505 FREQUENCY ERROR GHz Note Loop Filter Bandwidth 127 kHz Loop Filter Phase Margin 61 degrees This result is directly affected by loop filter design Faster settling time is possilbe with wider loop filter bandwidth and higher phase margin 2 495 g 1 1 1 1 1 1 1 1 1 1 0 20 40 60 80 100 120 140 160 TIME us Figure 29 Typical VCO Sensitivity 2854 MHz Tuning Cap 15 2453 MHz Tuning Cap 15 2013 MHz Tuning Cap 15 1587 MHz Tuning Cap 15 kVCO MHz V 0 0 66 1 3 2 2 6 3 3 TUNING VOLTAGE V HMC832LP6GE FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz Figure 26 Phase Settling After Frequency ee autocar Enabled 16 200 NS Settling Time to lt 40 draai Phase EE 50 F PHASE ERROR DEGREES 100 F 150 200 l L l I LI I i i 1 i 1 1 1 1 0 20 40 60 80 100 120 140 160 TIME uS Figure 28 Phase Settling After Frequency gii oe Manual Calibration 7 200 aa Time to lt 10 Phase Error PHASE ERROR DEGREES Note Loop Filter Bandwidth 127 kHz Loop Filter Phase Margin 61 degrees This result is directly affected by loop filter design Faster settling time 4 is possilbe with wider
76. selected by writing Heg O7h 6 O e Digital LD that supports a user configurable window size programmed in Reg 07h 11 7 Digital LD is selected by writing Reg O7h 6 1 1 5 5 1 Lock Detect Configuration Optimal spectral performance in fractional mode requires CP current and CP offset current configuration discussed in detail in section 1 5 1 Charge Pump CP amp Phase Detector PD These settings in Reg 09h impact the required LD window size in fractional mode of operation To function the required lock detect window size is provided by EQ 10 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com I V gt QO m t a LLI a Z L V uM ae A V O O gt QO m t or D LLI Z L z QU uM al A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz I CP Offset A Fpp Hz x lop A Fpp H LD Window seconds LT in Fractional Mode EQ 10 2 66 x10 sec LD Window seconds in Integer Mode x FPD where Fpp is the comparison frequency of the Phase Detector lop offset S the Charge Pump Offset Current Reg O9h 20 14 lcp is the full scale current setting of th
77. settings are set to the same value Reg 09h 13 7 Reg O9h 6 0 UP Offset Reg09 21 0 6355uA SuA Step Reg09 20 14 UP Gain RegO9 1 53 7 0 2 54mA 20uA Step REF PATH Loop Filter VCO PATH DN Offset Reg09 22 0 6355uA SuA Step Reg09 20 14 DN Gain Reg09 6 0 0 2 54mA 20uA Step Figure 44 Charge Pump Gain amp Offset Control 1 5 1 2 2 Charge Pump Gain Charge pump Up and Down gains are set by Reg O9h 6 0 and Reg 09h 13 7 respectively The current gain of the pump in Amps radian is equal to the gain setting of this register divided by 2rr Typical CP gain setting is set to 2 to 2 5 mA however lower values can also be used Values 1 mA may result in degraded Phase Noise performance For example if both Reg 09h 13 7 and Reg O9h 6 0 are set to 50d the output current of each pump will be 1 mA and the phase frequency detector gain k 1 mA 2r radians or 159 pA rad See section 1 5 1 for more information 1 5 1 3 3 Charge Pump Phase Offset In Integer Mode the phase detector operates with zero offset The divided reference signal and the divided VCO signal arrive at the phase detector inputs at the same time Integer mode does not require any CP For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hitt
78. stem SPI VSPI runs at the rate of the AutoCal FSM clock Tes section 1 4 1 1 where the FSM clock frequency cannot be greater than 50 MHz The VSPI clock rate is set by Reg 0Ah 14 13 Writes to the VCO s control registers are handled indirectly via writes to Reg 05h of the HMC832LP6GE A write to HUC832LP6GE Reg 05h causes the internal PLL subsystem to forward the packet MSB first across its internal serial link to the VCO subsystem where it is interpreted 1 3 1 1 VSPI Use of Reg05h The packet data written into Reg 05h is sub parsed by logic at the VCO subsystem into the following 3 fields 1 2 0 3 bits VCO ID target subsystem address 000b 2 6 3 4 bits VCO REGADDR the internal register address inside the VCO subsystem 3 157 9 bits VCO DATA data field to write into the VCO register For example to write O 1111 1110 into register 2 of the VCO subsystem VCO D 000 b and set the VCO output divider to divide by 62 the following needs to be written to Reg 05h O 1111 1110 0010 000 b or equivalently Reg 05h ZOFE20h During AutoCal the AutoCal controller writes into the VCO register address specified by the VCO ID and VCO REGADDR as stored in Reg 05h 2 0 and Reg 05h 6 3 respectively AutoCal expects these values to be zero Reg O5h 6 0 0 If they are not zero Reg O5h 6 0 0 AutoCal will not function To ensure AutoCal functions it is critical to write Reg O5h 6 0 0 after the last VCO subsy
79. stem write prior to an output frequency change triggered by a write to Reg O3h or Reg O4h However it is impossible to write only Reg O5h 6 0 20 VCO_REGADDR without writing Reg O5h 15 7 VCO DATA Therefore to ensure that the VCO DATA Reg 05h 15 7 in VCO_REGADDR 0 is not changed it is required to read the switch settings provided in Reg 10h 7 0 and then rewrite them to Reg 05h 15 7 Please see an example below For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz First read Reg 10h then write to Reg O5h as follows e Read Reg 10h to obtain VCO sub band settings e Write Reg O5h 6 0 0 to set the VCO address to O for following writes e Write the following to set the VCO sub band settings e Reg 05h 15 14 Reg 10h 7 6 e Reg 05h 13 1 Reserved bit e Reg 05h 12 7 Reg 10h 5 0 Changing the VCO subsystem configuration 3 0 VCO Subsystem Register Map without following the procedure above will result in failure to lock to the desired frequency For applications not using the read functionality of the HMC832LP6GE SPI in which Reg 10h cannot be read it is possible to write e Reg 05h Oh to set Reg O5h 6 0
80. ster are stored in the HMC832LP6GE and are only loaded into the modulator when a frequency change is executed and if AutoSeed RegO6h 8 1 Gg Ww Reed s WM Remmd 0 Use Modulator Required for Fractional Mode 1 Bypass Modulator Required for Integer Mode frac bypass Note In bypass fractional modulator output is ignored but fractional modulator continues to be clocked if frac rstb 21 Can be used to test the isolation of the digital fractional modulator from the VCO output in integer mode 10 8 R W hialzation Initialization 83 34 Program to 7d 0 disable frac core use for Integer Mode or Integer Mode with CSP 11 SD Enable 1 Enable Frac Core required for Fractional Mode or Integer isolation testing This register controls whether AutoCal starts on an HRU 9 or a Fractional write 20 12 SS Reserved Resemed cy mw mwms E 0 meme For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com I V O gt QO m t a D LLI Z L z QU ae A V O O gt QO m t a LLI Z L z QU un A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo01 0812 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 25 3000 MHz E
81. tep is small and the integer part of the frequency does not change then the integer register is not changed In all cases in fractional mode it is necessary to write to the fractional register Reg 04h for frequency changes For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com estittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz 1 4 8 Registers Required for Frequency Changes in Integer Mode A change of frequency in integer mode Reg 06h 11 20 requires Main Serial Port writes to 1 VCO SPI register Reg 05h e only required for manual control of VCO if Reg OAh 11 1 AutoCal disabled e required to change the VCO Output Divider value if needed VCO_Reg 02h 2 The integer register Reg O3h e n integer mode an integer register write triggers AutoCal if Reg OAh 11 0 and is loaded into the prescaler automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the VCO Normally changes to the integer register cause large steps in the VCO frequency hence the VCO switch settings must be adjusted AutoCal enabled is the recommended method for integer mode frequ
82. th Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com esrittite HMC832LP6GE MICROWAVE CORPORATION v01 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz Evaluation PCB Schematic To view this Evaluation PCB Schematic please visit www hittite com and choose HMC832LP6GE from the Search by Part Number pull down menu to view the product splash page Contents Part Number HMC832LP6GE Evaluation PCB USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable EKIT01 HMC832LP6G CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software Hittite PLL Design Software HMC832LP6GE Application Information Large bandwidth 25 MHz to 3000 MHz industry leading phase noise and spurious performance excellent noise floor 160 dBc Hz coupled with a high level of integration make the HMC832LP6GE ideal for a variety of applications as an RF or IF stage LO HMC960LP4E HMCS9OOLPSE Figure 37 HMC832LP6GE in a typical receive chain For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com I 2 V gt QO m t a D LLI I Z L z V a A I V
83. the AutoCal machine This is done by setting Reg OAh 10 1 which freezes the VCO switches in one position VCO switches may then be written manually with the varactor biased at the nominal mid rail voltage used for AutoCal For example to measure the VCO maximum frequency use switch 0 written to the VCO subsystem via Reg 05h 000000001 0000 VCOID Where VCOID 000 b If AutoCal is enabled Reg OAh 11 0 and a new frequency is written AutoCal will run The VCO frequency error relative to the command frequency will be measured and results written to Reg 11h 19 0 where Reg 11h 19 is the sign bit The result will be written in terms of VCO count error EQ 4 For example if the expected VCO is 2 GHz reference is 50 MHz and n is 6 we expect to measure 2000 50 29 22560 counts If we measure a difference of 5 counts in Reg 11h then it means we actually measured 2555 counts Hence the actual frequency of the VCO is 5 2560 low or 1 99609375 GHz 1 Count 781 kHz For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m lt a D LLI kt Z L V uM x A V gt QO m t a LLI Z L z V uM uM A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812
84. toCal routine for any reason at the same frequency simply rewrite the frequency change with the same value and the AutoCal routine will execute again without changing final frequency 1 4 1 5 5 VCO AutoCal Time amp Accuracy The VCO frequency is counted for Tmm the period of a single AutoCal measurement cycle a T el Ll EQ 1 n is set by Reg OAh 2 0 and results in measurement periods which are multiples of the PD period 7 4jR R is the reference path division ratio currently in use Reg 02h Tua is the period of the external reference crystal oscillator The VCO AutoCal counter will on average expect to register N counts rounded down floor to the nearest integer every PD cycle N is the ratio of the target VCO frequency f to the frequency of the PD foa where N can be any rational number supported by the N divider N is set by the integer N Reg 03h and fractional N44 Reg 04h register contents 24 N N N 2 EQ 2 The AutoCal state machine and the data transfers to the internal VCO subsystem SPI VSPI run at the rate of the FSM clock Tgs where the FSM clock frequency cannot be greater than 50 MHz m Teu rat 2 EQ 3 m is 0 2 4 or 5 as determined by Reg 0Ah 14 13 The expected number of VCO counts V is given by V floor N 2 EQ 4 The nominal VCO frequency measured fycom is given by n f on V f 2 R EQ 5 where the worst case measurement error ferr is n 1 NE tf 2 EQ 6
85. utoCal of the step tuned VCO The AutoCal fixes the VCO tuning voltage at the optimum mid point of the charge pump output then measures the free running VCO frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency This procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor A typical tuning curve for a step tuned VCO is shown in Figure 42 Note how the tuning voltage stays in a narrow range over a wide range of output frequencies 3 5 N c1 N c1 Co TUNE VOLTAGE AFTER CALIBRATION V o e 1500 3000 VCO FREQUENCY MHz Figure 42 Typical VCO Tuning Voltage After Calibration The calibration is normally run automatically once for every change of frequency This ensures optimum selection of VCO switch settings vs time and temperature The user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the AutoCal routine The accuracy required in the calibration affects the amount of time required to tune the VCO The calibration routine searches for the best step setting that locks the VCO at the current programmed frequency and ensures that the VCO will stay locked and perform well over it s full temperature range without additional calibration regardless of the temperature that the VCO was calibrated at Auto Calibration can also be disab
86. ve 2 18 Reg 12h GPO2 Register Default 000000h ee NNN Lock Detect Status Lock Detect 1 Locked 0 Unlocked 2 19 Reg 13h BIST Register Default 000000h TU a ASS 3 0 VCO Subsystem Register Map Please note that the VCO subsystem uses indirect addressing via Reg 05h For more detailed information on how to write to the VCO subsystem please see section 1 3 1 VCO Serial Port Interface VSPI 3 1 VCO_Reg 00h Tuning L tune voltage is redirected to a to a temperature compensated calibration voltage VCO sub band selection 0 max frequency 1111 1111 min frequency Master Enable VCO Subsystem 1 To All VCO subsystem blocks m blocks Off VCO Enable Enables VCOs PLL Buffer Enable Enables PLL Buffer to N Divider Enables output stage and the Output Divider It does not IO Master Enable enable disable the VCO Output Stage Enable For T to T the output stage of the VCO EET of the HMC832LP6GE bit 5 in VCO_Reg 01h needs to be cleared If the other bits are left unchanged then 1 1101 1111 needs to be written into VCO_Reg 01h The VCO subsystem register is accessed via a write to PLL subsystem Reg 05h 1 1101 1111 0001 000 EF88h Reg 05h 2 0 000 VCO subsystem ID 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or ap
87. y CP 2 mA in Fractional Mode Pin Descriptions Pin Number Function Description AVDD DC Power Supply for analog circuitry 2 5 6 8 9 11 14 18 22 24 26 34 37 38 The pins are not connected internally however It is recommended to connect these pins to RF DC ground externally Power Supply for charge pump analog section Charge Pump Output Power Supply for the charge pump digital section XREFP Reference Oscillator Input DVDD DC Power Supply for Digital CMOS Circuitry PLL Subsystem Enable No effect on the VCO Subsystem Connect to logic high for normal operation VTUNE VCO Varactor Tuning Port Input CEN a Lock Detect or Serial Data or General Purpose CMOS Logic Output GPO External bypass decoupling for precision bias circuits 40 BIAS Note 1 920V 20mV reference voltage BIAS is generated internally and cannot drive an external load Must be measured with 10GO meter such as Agilent 34410A normal 10MQ DVM will read erroneously For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V O gt QO m t a D LLI Z L V un a A QU O gt QO m t or D LLI Z L z QU EN e A eal TIttItE MICROWAVE CORPORATION vo1 0812 RoHS
88. y EQ 12 ignoring the fractional part a Disable the Fractional Modulator Reg O6h 11 O For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com V gt QO m t a D LLI a Z L V uM ae A V gt QO m t a LLI Z L z V un A tal TIttItE HMC832LP6GE MICROWAVE CORPORATION vo1 0812 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 25 3000 MHz b Bypass the delta sigma modulator Reg O6h 7 1 c To tune to frequencies 1500 MHz select the appropriate output divider value VCO Reg O2h 5 0 Writing to VCO subsystem registers VCO Reg 02h 5 0 and VCO_Reg 03h 0 in this case is accomplished indirectly through PLL register 5 Reg 05h More information on communicating with the VCO subsystem through PLL Reg O5h is available in 1 3 1 VCO Serial Port Interface VSPI section 1 5 7 3 Fractional Mode The HMC832LP6GE is placed in fractional mode by setting the following registers a Enable the Fractional Modulator Reg 06h 11 1 b Connect the delta sigma modulator in circuit Reg 06h 7 20 1 5 7 4 4 Fractional Frequency Tuning This is a generic example with the goal of explaining how to program the output frequency Actual variables are depe

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