Digital module requirement specification
Contents
1. osease 5 Jo ERR e 6 3 1 SIGNAL INTERFACE fe 6 3 21 Gcr ERAT DRE USA 9 4 REGISTER INTEREACE IEEE eR PANE 10 5 FUNCTIONAL 1 61 sesta set en s tetas tes toas 17 5 1 FUNCTIONAL OVERVIEW eed au E ial A esset Rena di UMP 17 5 2 MAIN FUNCTIONAL CHANGES FROM PCM v2 0 HUST 17 5 3 PROJECT 5 aon lena Ute e idus 17 5 3 1 19 94 seins 20 5 4 1 Main Output Signals Lula a 20 5 4 2 TO BIC 20 5 4 3 ALTRO Switch Mask I 20 5 4 4 ALTRO i tree FE PRU eret EDU 20 5 4 5 Event length Manager uie Goode etd esee ned deese eh ge eR ER ieee 21 5 4 6 Slow Control Slave Interface eus orden eter ee Rae 22 5 4 7 Interface Decoder siii deco LEE ERU ats La ca 23 5 4 8 Registers eria era ERE I 23 5 4 9 ene A R a2. PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 9 31 led_yellow Output to diode connected high Output to diode connected high u u aux 3 0 in in in USB interface Not Used uso sc USB interface Not Used USB interface Not Used uso w Jin USB interface Not Used uso cs USB interface Not Used usb fd 1 5 0 inout USB interface Not Used USB interface Not Used USB interface Not Used USB interface Not Used Table 3 1 Signal interface 3 2 Timing diagrams TBA PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 10 31 4 Register interface Brcast UNLOCK 0x0 RW Yes One bit unlock register for writing to read only regs for testing 0 Locked 1 Unlocked L2CNT 15 0 0x0C R W Yes Number of L2a triggers received SCLKCNT 15 0 R W Sampling clock counter SLOWCTR_ERR OxOE R No Number of timeout situations in Slow 7 0 Control CSRO 1 1 0 0x11 RW Yes Interrupt Mask Register Default value 0x1FF 11 HV Update Mode 0 The BC updates DAC with update hv command 1 The BC continuously updates DACs Conversion Mode 0 The BC reads the content of the monitor ADC with the STCNV command 1B 1 monitor ADC converts continuously Error Mask These two bits mask the assertion of the Error line This line is asserted with the flags registered in CSR1
3. tb_pkg_phosBC vhd tb txt util vhd vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl slave vhdl slave vhdl slave vhdl slave vhdl slave vhdl slave vhdl slave vhdl testbench vhdl testbench vhdl testbench vhdl testbench vhdl testbench vhdl testbench vhdl testbench Table 5 1 Files checked in in the CVS repository 5 3 1 Software Editor Simulation Synthesis and Place and Route for test See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 obsolete See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 obsolete obsolete See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 6 See chapter 5 4 6 See chapter 5 4 6 See chapter 5 4 6 See chapter 5 4 6 See chapter 5 4 6 not updated See chapter 5 4 6 See chapter 6 4 See chapter 6 4 not updated See chapter 6 4 See chapter 6 4 See chapter 6 4 See chapter 6 4 See chapter 6 4 ConTEXT v0 98 5 Questasim 6 1d Quartus II Version 6 0 Build 178 PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 20 31 5 4 Functional Details 5 4 1 Main Output Signals Signal Name Explanation rdoclk_en Enables the distribution of the system clock to all the ALTROs adcclk_en Enables distribution of the sampling clock
4. Digital module requirement specification 1 31 PHOS Board Controller Specification Document name PHOS BC specification_v3 4 doc Revision 0 6 fw version 3 4 Date Created on 5 23 2007 9 38 00 AM Last saved 10 31 2007 11 12 00 AM Author Created by Johan Alme Last saved by Johan Alme Module PHOS BC Block diagram RCU ALTRO bus I2C bus FEC Drivers GTL driver CTRL EventLength Manager ALTRO Switch Mask In ADCs lt 2 busy 1 27 ALTRO Interface Slow Control I2C Slave Interface decoder 13 SCLK cnt VTC Status Low Thr Mem Hamming High Thr Mem decoder Register Block Power Supply Errors ADC val mem DAC Memory Power Supply Enables ADC Interface Hamming decoder Serial bus DACs DAC interface PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 2 31 Features Two command interfaces o ALTRO bus interface o Special I2C interface I2C interface is robust with timeout counters and masking of bus input when active transaction to other card Setting of DACS for bias voltage for High Voltage region Interface to 3 ADCS
5. 8 A6pVO over th 9 A6pVOC over th 10 TEMPS over th 11 A3V3 over th 12 over th 13 A13VO over th 14 1 over th Voltage Temperature Status register 0 TEMP1 under th 1 D4VO under th 2 D4VOC under th 3 D3V3 under th 4 D3V3C under th 5 TEMP2 under th 6 A6nVO under th 7 AenVOC under th 8 A6pVO under th 9 A6pVOC under th 10 under th 11 under th 12 under th 13 A13VO under th 14 A13VOC under th H 14 0 high threshold memory 14 t 0 threshold memory TT HV_HVHMGERR1 0x27 R W Yes 15 0 0 28 Yes Lua 0 mE m Compared outputs from DAC for CSP 7 0 16 CSP 23 15 8 CSP7 CSP0 0 DAC not set Wrong 1 DAC set Correct Compared outputs from DAC for CSP 7 0 CSP 15 CSP 8 15 8 CSP 24 CSP 31 0 DAC not set Wrong 1 DAC set Correct Double hamming errors for the following 7 0 16 CSP 23 15 8 CSP7 CSP0 Double hamming errors for the following 7 0 15 CSP 8 15 8 CSP 24 31 Sets which ADC values that should be treated as currents in the ADC value and ADC threshold memory In practice this is a diff between Vprev and Vourrent Default Value 0x5294 PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 13 31 Register name Addr Type Allow Description Brcast ADC DIFF DIR 2 Yes Set
6. the ALTRO IF On the given test setup given here more that 1000000 transaction on the ALTRO bus went without error and more than 250000 complete transmissions 4xbytes on the Slow Control bus did the same On the complete module it has been functionally verified that Slow Control communication works with more than one FEC attached and powered Concerning the ALTRO bus protocol certain timeout situation happens at a approximate rate of 1 per mill of all transactions The reason for these timeout situations is that the Board Controller does not see a valid address when it occurs and then does not ack This has been tested with all FECs powered and with only one FEC powered and the result is the same Since this problem has not been seen at all on the test setup in the lab only at the module the conclusion is that the Board Controller is performing as it should but the error is somewhere externally http ep ed alice tpc web cern ch ep ed alice tpc PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 30 31 7 Physical implementation 7 1 Technology Device Altera ACEX1K EP1K100QC208 3 7 2 Logic Synthesis 7 2 1 Static timing analysis Required Time Ealey Paths Clock Setup 40 00 MHz 41 32 MHz period rdoclk period 25 000 24 200 ns ns Clock Hold 40 00 MHz N A rdoclk period 25 000 ns Recovery 26 200 ns 11 300 ns rdoclk Removal 2 800
7. 2007 and pin 2 is GND and pin4 is VCC All 4 RCUS has been verified in the sense that the version number has been read back from all FECs with success One RCU has been more extensively tested to debug the problem with the ALTRO bus timeouts see chapter 6 4 3 8 2 Soflware There are a couple of things that are interesting for the software developer and this chapter is an attempt to summarize them shortly 1 The software must handle different mapping of various registers since there is one board that still have the old version 2 When doing writes and reads over the ALTRO interface always check that the transaction didn t timeout This will be easier with the new RCU firmware version to handle in a fault proof manner 3 Remember to verify certain status registers after doing various actions An example can be the setting of the DAC values Then there are 4 registers that should be checked the High Voltage Feedback Registers giving which channels has been set and the Hamming error registers in case hamming encoding is included 4 If Hamming encoding is enabled all values written the DAC memories and the ADC Threshold Memories must be written with correct hamming code The calculation for the hamming code is included in this document 5 Continuously readback of ADC values is not turned on by default and must be done if this is wanted 6 Same accounts for continuously updating the DACs from the values stored in the memory 7 E
8. Over temperature indicator Not used oi 3 In 12 Overtemperature indicator Not Used en 10 DAQ serial clock enable Active high i17 DACseralClck 7 dac ldac out Load DAC LDAC is asynchronous active low that updates the DAC outputs simultaneously dac sel 3 0 out If LDAC is driven low the DAC registers are transparent Chip Select output active low daq sel 0 HVB 1 8 sel 1 HVA 1 8 sel 2 HVA 9 16 sel 3 HVB 9 16 Pu Serial Data Input for the 4 dacs Data Output from the 4 dags DOUT is updated on the falling edge of SCLK 1 le 2 21 dac din 3 0 dac dout 3 0 ut 30 29 28 27 n 36 31 15 14 in test_m_sclk_dn o LVDS_n Test mode sampling clock generated by the Board Controller Can only be used of external SCLK is missing by the Board Controller and RCLK for BC Active low tms altro2 Test mode Altro 2 active low Not Used tms altro3 out Test mode Altro 3 active low Not Used adc adq 1 0 out 116 Output addressing lines for testmode Used to 115 address which of the 4 4 channels in the ALTROS should be readout during testmode execution QO chO0 8 01 4 7 10 ch 8 11 11 ch 12 15 Not Used led red Jout 62 Output to diode connected high test m sclk dn test m g e tms altroO tms altro1 0
9. Ox3D Minimum 13 0V Analog Voltage Threshold Default Value 0x1D6 12 6 V 13 0 MIN TH Ox3E Minimum 13 0V Analog Current Threshold Default Value 0 0 disabled Alternatively Voltage level used for current calc Table 4 2 ADC Minimum Threshold Value Memory The conversion factors are given in Table 4 4 PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 15 31 Memory location name Addr Description Default Data Value 0 0 40 Default Value 0x0 disabled Maximum 4 0V Digital Current Threshold Default Value 0 00 0 36 Alternatively Voltage level used for current calc Default Value 0x0 disabled D3V3C_MAX_TH 0x44 Maximum 3 3V Digital Current Threshold Alternatively Voltage level used for current calc Default Data Value OxA0 40 A6nVO MAX TH Maximum 6 0V Analog Voltage Threshold Default Value 0 0 disabled Maximum 6 0V Analog Current Threshold Default Value OxOOF 0 44 A Alternatively Voltage level used for current calc Default Value 0x0 disabled A6pVOC_MAX_TH Maximum 6 0V Analog Current Threshold Default Value 0 016 0 764 Alternatively Voltage level used for current calc TEMP3 MAX_TH Maximum Temperature Threshold for ADC IC14 Default Data Value OxAO0 40 C A3V3_MAX_TH Maximum 3 3V Analog Voltage Threshold Default Value 0x0 disabled 0 4 Maximum 3 3V Analog Curre
10. d 10 h 2 d 1 d 2 d 3 d 7 d 8 d 9 d 10 h 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 h 4 h 0 h 1 h 2 h 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 Where h is the 5 bit hamming vector and d is the 11 bit data vector Please note that when hamming decoding is enabled the threshold registers and the DAC value registers must be filled in with hamming code and data for the firmware to act as expected If hamming decoding is disabled only the last 1O bits in these register PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 27 31 matters the other bits are don t care The formats of these registers are given in Table 4 1 5 4 12 Optional Functionality If it should be of any interest to store board specific data for instance the serialnumber of the board on the 241 256 External Flash Memory 2 master can be made in the BC firmware that gives access to this device The I2C bus is shared between the USB chip the Flash Device and the Board Controller of which the latter is us originally thought to be used as a slave Since I2C master device on the USB chip has open drain outputs it should not be any electrical constraints preventing the BC from being the master but investigations must be done to verify that the BC and the USB will not access the I2C bus at the same time f
11. decoded for the ALTRO sampling clock Reset from RCU command decoded active low Global reset signal from power up Bidirectional ALTRO bus 39 Parity bit 38 Bcast bit 37 Boardcontroller ALTRO 36 25 Channel Address BC register address 24 20 ALTRO Instruction Code 19 0 Data The write read signal is driven by the master RCU and defines whether the access to the addressed unit is in write read mode The master RCU drives the command strobe CSTB signal When asserted it indicates that a valid word has been placed in the AD bus The signal also qualifies the WRITE signal On a WRITE or COMMAND cycle the addressed unit asserts the ACKN signal to indicate that is has successfully latched the bus content and executed the requested instruction On a READ cycle the addressed unit asserts the ACKN to indicate that it has placed the requested data on the bus The ERROR line is asserted by the slave units to signal the occurrence of an error condition If the error condition has occurred in an instruction cycle parity error or clock name gt lasync Assumed synchronous with the given clock name or asynchronous Ouputs clock name glitch free lcomb Output generated from the given clock name or combinatorial PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 7 31 instruction code error the slave does not acknowledge the instruction cycle an
12. for verifying voltage and current levels as well as temperatures Programmable min and max thresholds for flagging errors in ADC values Possible to set how to treat the voltages read back for current calculations o Store them as is o diff with previous adc value o Control the order of diff after the expected direction of the current Unlock register for write to read only registers Monitoring error inputs from Power Regulators Interrupt line to RCU for errors of a severity level craving urgent measures Configurable number of threshold violations from 1 to 3 before interrupt is flagged Possible to set the FEC in standby mode by turning off voltage regulators and not reporting any warnings errors Radiation precautions o Hamming coded ADC threshold settings o Hamming coded DAC values o of configuration status registers and threshold config registers Configurable automatic update of DACs Event length Manager module that generates a hitmap of all ALTRO channels and clocks this out to RCU by controlling dstb for Sparse Readout Mode Debug registers to test ALTRO bus integrity PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 3 31 1 DOCUMENT CONTROL 4 1 1 REVISION HISTORY de enue 4 24 IRE NCES EN 4 2 MOTIVATION Pec
13. ns 5 700 ns rdoclk Clock Setup 20 00 MHz 151 52 MHz period adcclk period 50 000 6 600 ns ns Clock Hold 20 00 MHz N A adcclk period 50 000 ns Recovery 5 55 000 ns 5 700 ns adcclk Removal 7 600 ns 11 600 ns adcclk Total number of failed paths Table 7 1 Worst path timing information 7 2 2 Area estimates A altro sw mask in mask laltrobusinterface bus interface drivers driv levi man eventlength manager interface interface adc ADC interface linterfacedec decoder registers regs slave slow_control_if Table 7 2 Area estimates giving total usage of resources and how much is used by the sub modules PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 31 31 8 Installation Log This chapter gives a short overview on the installation of the Board Controller of 1 PHOS module 8 1 Installation Status The installation was done on the 29 30 of October 2007 on the complete module The only board that was not upgraded is FEC B 12 on dcs0281 due to a problem with the JTAG chain This board has still version 1 2 of PCM as made by HUST It also is worth noticing that FEC A 12 on dcs0280 needs to have 3 3V externally fed to the JTAG chain because of a problem most probably related to a broken wire This very cable has two connectors on it as of 31 October
14. 24 34d0 DAC hne 25 5 4 11 Hamming Code Hamming Decoder Module esses 26 5 4 12 CMTC ALF VPC ONLI ae as sisi leech Dae 27 6 555255 ri aea ehe open e tee 28 6 1 CLOCK STRATEGY aea Lo det mu ect eee 28 6 2 RESET STRATEGY rnrn o hue Viae ioo ossa Fue Parks boo 28 6 3 POWER STRATEGY C esee data adu E E cd 28 EBST STRATEONCG NUM BA M Ee Ree MAL peius 28 6 4 1 Functional and Post Place and Route 28 6 4 2 Functional CoVeldge irr enlace 29 6 4 3 Hardware Verification Ue dioe e I eaa Us 29 7 555540 30 Jul TECHNOLOGY o e ie theca pie tot Gea ain ante UNES 30 7 2 LOGIC SYNTHESIS r E EAER ES 30 7 2 1 Statie timing 30 7 2 2 red estimates i ecd a ous 30 INSTALLATION 31 8 1 INSTALLATION STATUS 31 8 2 dera 31 PHOS specification_v3 4 doc Created by Johan Alme Digital module requirement specificati
15. 9 8 0 the error is masked 1 the error asserts the line Interrupt Mask These bits mask the bits of CSR1 7 0 for the assertion of the Interrupt line CSR1 13 0 0x12 N A Error Status Register Default value 0 0000 13 X Value of Slow Control Interrupt line Value of ALTRO bus Error line Slow Control Instruction Error ALTRO error Registered value of ALTRO bus error line ALTRO bus Instruction Error to BC Parity error of ALTRO bus 20 MSB Missing Sampling Clock ALTRO Power Digital 4 2V amp 3 3V and Bias Supply Error Shaper 6 0V Power Supply Error 4 2 V or 3 3 V digital current is higher than thresholds 4 2 V or 3 3 V digital voltage is lower than thresholds Legend W write R read T write trigger not physical registers PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 11 31 Register name Addr Allow Description F Brcast 2 4 0 V 6 0 V 6 0 V 13 5 V analog current higher than threshold 1 4 0 V 6 0 V 6 0 V 13 5 V analog voltage lower than threshold Temp1 Temp2 or Temp3 higher than threshold CSR2 15 0 0x13 RW Yes Status and Configuration Default value 0x013F 15 11 Hardware Address read only 10 Card Isolated 9 8 Number of times a ADC threshold violation must occur before it is reported 7 Not Used 6 Enables Hamming correction on HVDAC values and Thresholds 5 Enables DAC cl
16. arallel input is register values from the BC The parallel output is used by all state machines to get the needed data The serial output is used by the transmitter to serialize the parallel input to the master of the I2C bus Slave RX Receives 1 byte and compares the lower 7 bit to valid instructions If the instruction is correct then the state machine acknowledges the request and reads 2 more bytes The instruction code and 16bit data is output for handling by the BC Slave TX Receives one 1 byte and compares the lower 7 bit to valid instructions If the instruction is correct then the state machine acknowledges the request The instruction code is sent off to the BC and valid data should be returned The transmitter then transfers the data in 2 l byte blocks to the master of the I2C bus Select Signals A multiplexer Depending on the state of the various state machines this mux chooses the control inputs to the serializer and the address returned to the BC In version 3 2 this module has been upgraded Now this module will decode all that is received on the slow control bus no matter if the card address is correct or not This is done to ensure that a fake start condition can not be detected when a different board is addressed and busy with a transaction If the card address is not correct a mask bit has been set to mask both the sda_out data line and the internal write enable In addition the RX and TX module have now timeout c
17. d asserts the ERROR signal trsf inout 39 The ALTRO chip takes the control of the bus by asserting the TRANSFER signal acknowledges this instruction cycle TRANSFER is kept asserted till the data block has been completely transferred The data transfer is not necessarily continuous and for this reason each single word being transferred is validated by the signal DSTB Data Strobe The 11 signal is broadcasted by the RCU to all the FECs It is used for the distribution of the trigger information The 11 signal is synchronous with the SCLK signal and lasts for at least two clock cycles I2 signal is broadcasted by the RCU to all the FECs It is used for the distribution of the trigger information The 12 signal is synchronous with the RCLK and lasts for two clock cycles ack_en ack_en frames ackn enabling the intrinsic capacitor in the transceiver dolo_en In 186 dolo_en is used to drive the bi directional bus bd when reading a register for the later ad 4 0 Hardware address input from branch bcout add 4 0 Output hardware address to the ALTROs 00000 if ALTROs are turned off or in debug mode card ad otherwise Enable signal for ALTRO power regulators allps error 78 Error flag signalling if output voltage has dropped 5 under nominal value for the power regulator of the digital part altrops error in Error flag signalling if output voltage has dropped 5 under the nominal value for ALTRO power re
18. d the previous read value is tested against the threshold and stored in the ADC value memory Since the difference between the previous and the current value is effectively a measurement for the current when used as in PHOS and additional register ADC DIFF INT is used to set the correct expected current direction The VTC error counter is counted up for the given position if the current flows the opposite way of what it is expected to do 5 4 9 ADC Interface ADC data Start conversion gt mscl p msd Sequencer gt 2 Master U Instruction ROM Figure 5 3 Sketch of the ADC interface that is used for monitoring of temperatures currents and voltages on the Front End Card The main purpose of the ADC interface is to read the currents voltages and temperatures on the different parts of the board There are three ADCs of type AD7417 2 placed in different areas on the board and these are controlled using a standard I2C bus protocol All the instructions for reading writing are placed in a ROM If start conversion is high when the Sequencer is in the idle state a complete readback of all values of the ADCs are initiated The sequencer is level sensitive of Start Conversion meaning that if one wants to continuously readback all the data this is done by setting this input constantly high The ADCs offer a possibility to let them verify the temperature against a prog
19. e Digital module requirement specification 17 31 5 Functional Requirements 5 1 Functional Overview The main features of the PHOS Board Controller are e Control the ALTRO bus and the GTL drivers on the FEC e Read temperatures voltages and currents on the board and verify them against locally stored thresholds Flag if an error situation has occurred on the board e Set the output of the DACs that control the bias of the high voltage section e Read Eventlength registers in ALTRO and push hitmap data to the RCU when Sparse Readout Mode is selected In addition the Board Controller is able to set the FEC in standby mode by turning off the power supplies and disabling the clock and bus transactions Hamming is per default enabled while continuously checking ADC values are not Before turning on continuously check on ADC values all threshold should be set correctly This includes adc diff and adc diff dir registers which in practice decides whether one should read current or voltage from the ADC These memory location are set correctly by default The Hamming encoding spans also over bit 10 0 in the threshold and dac registers The hamming decoding and if needed correction is done every time the values from the memories are read by internal logic When reading the ADC values they are checked against the thresholds given in the min max threshold memories if the threshold memory location value is unequal to 0 If 0 this means tha
20. e masked out as well as error status information concerning the ALTRO to the RCU If the BIAS and the SHAPER power supplies are turned off error status information concerning the ALTRO to the RCU are masked out Additionally it adds metastability filter on the strobe and acknowledge signal 5 4 4 ALTRO Interface As given by the name the ALTRO interface decoded the information coming on the ALTRO bus It listens for a positive edge on the strobe and then looks at the 20 PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 21 31 most significant bits in the ALTRO bus where it decodes the address Decoding the address essentially means e Decoding parity bit to detect any parity error gt Not valid transaction e Check the beast bit If asserted no ack should be given e Check the ALTRO_BC bit that selects either ALTRO or BC e Check the hardware address If all these are correct for the given FEC and Board Controller the 7 least significant bits are handed over to the registers module for decoding and the transaction is ack The transaction will be acked no matter if the given register addresses does exist or not Two chip select signals are being decoded one for if it is a valid board controller transaction and one if it is a valid ALTRO transaction These CS are used by the Drivers Module to control the GTL bus drivers Since the ALTRO bus has a problem with occasional timeouts d
21. ebug information was from version 3 4 made available in 4 registers This information gives a notice on how many strobes the BC has seen from the FEC and how many has actually been acked In addition the last 20 bit address being acked on the ALTRO bus is stored as well as the last 20 bit address that has not being acked is stored This can be used for debugging why the given BC does not ack on registers where it should ve done so Version 3 4 also introduced more robustness measures concerning the bus such as meta stability filters on all control signals and address information and an extra wait state to be sure that the data address are stable when the are decoded 5 4 5 Event length Manager The Event length Manager is used in Sparse Readout Mode and the purpose of the Event length Manager is to scan the Event Length register of each ALTRO channel to see if it contains data zero suppression must be enabled The module builds a hitmap register that has one bit for each channel that has event length unlike zero The hitmap register is pushed to the RCU in the same manner as the ALTRO pushes data The Event length manager listens on two commands from the register block decoded from the RCU e Scan Eventlength SCEVL e Event length Readout EVL_RDO The first command starts to read the event length register of all the ALTRO channels To do this it needs to take control over the ALTRO bus and become the bus master It then isolates the boa
22. facebus vhd drivers vhd signals driver vhd transceivers driver vhd ch counter vhd evl_man vhd evireg_trsf vhd read_evl vhd hvdac vhd hvdac_tb vhd adc_rom cmp adc_rom vhd interface adc vhd interface adc tb vhd master vhd master sm vhd ROM hex ROM mif rom vhd sequencer vhd serializer vhd interfacedec vhd adc ram cmp adc ram vhd counters vhd dac ram cmp dac ram vhd df adcval hex df adcval mif df dac hex df dac mif df thhigh hex code ref code ref docs docs docs docs graphics docs ref Quartus project vhdl vhdl vhdl altro_sw_mask_in vhdl altrobusinterface vhdl altrobusinterface vhdl altrobusinterface vhdl altrobusinterface vhdl drivers vhdl drivers vhdl drivers vhdl evl_man vhdl evl_man vhdl evl_man vhdl evl_man vhdl hvdac vhdl hvdac vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interface_adc vhdl interfacedec vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers vhdl registers Folder Description HUST PCM2 0 project HUST PCM2 0 verilog PHOS BC v3 0 spec PHOS v3 1 document Hamming encoding basis Visio file with graphics Documents that are used as reference
23. for the design The files generated used by Quartus Important files are e bc pof bc sof configuration files e bc vho Simulation model Pinning file Top level Testbench Package See chapter 5 4 3 spec this See chapter 5 4 4 obsolete v3 3 See chapter 5 4 4 See chapter 5 4 4 not updated See chapter 5 4 4 obsolete v3 3 See chapter 5 4 2 See chapter 5 4 2 See chapter 5 4 2 See chapter 5 4 5 See chapter 5 4 5 See chapter 5 4 5 See chapter 5 4 5 See chapter 5 4 10 See chapter 5 4 10 See chapter 5 4 9 See chapter 5 4 9 See chapter 5 4 9 See chapter 5 4 9 not updated See chapter 5 4 9 See chapter 5 4 9 See chapter 5 4 9 See chapter 5 4 9 Obsolete See chapter 5 4 9 See chapter 5 4 9 See chapter 5 4 7 See chapter 5 4 8 See chapter 5 4 8 obsolete See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 See chapter 5 4 8 PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 19 31 File Cd Folder sd Description df_thhigh mif df thlow hex df thlow mif dstb counter vhd hamming_decoder vhd registers vhd registers_block vhd sclk_counter vhd th_ram hex th_ram mif triggercounter vhd vtc status vhd fec address vhd sel signals vhd serializer bc vhd slave vhd slave rx vhd slave tb vhd slave tx vhd ad7417 vhd ad7417 tb vhd max5308dac vhd rcu_synthesis vhd tb_pkg vhd
24. gulator Low parity Error flag signalling if output voltage has dropped 5 under the nominal value for shaper power regulator Low parity Setting direction of GTL drivers for altro bus 0 output to RCU 1 input to FEC Setting direction of GTL drivers for altro bus 0 output to RCU 1 input to FEC Ia B LI oeab 1 E i biasps error in Error flag signalling if output voltage has iP dropped 5 under the nominal value for bias power regulator Low parity PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 8 31 200 Setting direction of GTL drivers for altro bus 1 output to RCU 0 input to FEC oeba_h out 196 Setting direction of GTL drivers for altro bus 1 output to RCU 0 input to FEC ctr_in out 198 Enabling output of GTL drivers for control bus RCU gt FEC 0 enabled 1 high Z ctr_out out 199 Enabling output of GTL drivers for control bus FEC RCU 0 enabled 1 high Z rcu sc fin 14 5 MHz Slow Clock for I2C transfers reu sda in in 119 Slow Control Serial data in from RCU Slow Control Serial data out to RCU sensor scl out 7 I2C clock for AD7417 communication x3 sensor sda inout 8 12C dataline for AD7417 communication x3 convst out 13 Convertstart signal for AD7417 x3 jio 1 l 9 Over temperature indicator Not used oti 2 In 11
25. hresholds the RCU will be notified If the severity level is considered to be potentially damaging to the board the RCU will turn off the given FEC The PHOS FEC also includes a high voltage section A very important functionality of the PHOS Board Controller is to set the bias voltage to the charge sensitive amplifiers located in the high voltage section This must be done since the amplification of the APDs that are used for readout is varying from part to part This variation is cancelled out with the setting of the DACs that are controlling the bias voltage This version of the PHOS BC is based on the TPC BC adding the extra functionality needed for PHOS and removing some features that are not needed The basis for the code is the FMD version that is a VHDL implementation of the TPC BC with some modifications Major changes have been done to this implementation to make it fit for PHOS and to make it more robust PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 3 External Interface 3 1 Signal interface 6 31 rdoclk 183 40 Mhz Readout Clock used as system clock rdock en 121 Enable for the ALTRO readout clock fecclk 40m 79 40 MHz Clock from crystal adcck in 167 7 20MHz ALTRO sampling clock adcclk en zm 122 E Sys rst bd 39 0 write Inout error Inputs Enable Reset fom RU Teomand
26. ler All error states are tested for in this module and the correct error bits are set The interface to the module is a fully synchronous interface with data address and a write enable signal The DAC value memory are hamming coded and the validity of the contents of these memories will be checked whenever the memories are read by internal logic not the interfaces The CSRO CSR2 CSR3 ADC DIFF and ADC DIFF INT registers are protected against single event upsets by the use of TMR Triple Modular Redundancy and voting logic The DAC value memory holds all the values to be written to the DAC interface The DAC interface itself has a hamming decoder performing a hamming check before the value is written to the DAC If a single bit error is found the DAC value memory is updated with the correct value If a double error is found then this is notified in the DAC hamming error register and the given DAC is not written to The VTC Status Module holds all memories related to the read out of ADC values Everytime the adc we signal is asserted from the ADC interface the comparator verifies if the value delivered by the ADC is within the thresholds The thresholds are also hamming tested every time they are read by internal logic if hamming is enabled for the BC There is a separate state machine comparator that tests whether the read back ADC value is within the threshold given in the threshold memory If the hamming decoder is enabled then the threshold va
27. lue is validated first In case of a single bit error the ADC threshold register will be updated with the correct value In case of a double bit error this is notified in the threshold hamming PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 24 31 error register This functionality is executed whenever the ADC interface writes a value to the ADC value memory The ADC threshold memory and the ADC value memory have the same addressing meaning that there is a one to one correspondence between the values in a given address If the threshold test fails the read back value exceeds the value given in threshold an error counter is counted up for the given position This counter can trigger the interrupt to go off at a configurable number of times from 1 to 3 the same error situation has occurred in a row Default value of this limit is set to 1 to match previous versions of the BC This is implemented so that it is possible to avoid that a single event upset or any other error in the reading back of ADC value will fire an interrupt that might turn off the complete board when it is false alarm The ADC DIFF and ADC DIFF INT sets the mode of which the adc value should be perceived If ADC DIFF equals 0 the value read is tested directly against the given threshold value and stored into the ADC value memory If ADC DIFF equals 1 it means that the difference between the currently returned value an
28. me Digital module requirement specification 14 31 Memory location name Adar Description Default Data Value 0x0 disabled D4VO MIN TH Minimum 4 0V Digital Voltage Threshold Default Data Value 0x1D8 3 8 V D4VOC MIN TH Minimum 4 0V Digital Current Threshold Default Value 0 0 disabled Alternatively Voltage level used for current calc D3V3 MIN Minimum 3 3V Digital Voltage Threshold Default Data Value Ox1C2 2 9 V D3V3C MIN TH Minimum 3 3V Digital Current Threshold Default Value 0x0 disabled Alternatively Voltage level used for current calc TEMP2 MIN TH Minimum Temperature Threshold for ADC IC15 Default Value 0x0 disabled A6nVO MIN TH 0x36 Minimum 6 0V Analog Voltage Threshold Default Data Value 0x170 6 4 V A6nVOC MIN TH 0x37 Minimum 6 0V Analog Current Threshold Default Value 0 0 disabled Alternatively Voltage level used for current calc A6pVO MIN TH 0x38 Minimum 6 0V Analog Voltage Threshold Default Data Value 0 1 8 5 6 V A6pVOC MIN TH 0x39 Minimum 6 0V Analog Current Threshold Default Value 0 0 disabled Alternatively Voltage level used for current calc TEMP3 MIN TH Minimum Temperature Threshold for ADC IC14 Default Value 0x0 disabled A3V3 MIN TH Minimum 3 3V Analog Voltage Threshold Default Value 0x1C2 2 9 V A3V3C MIN TH 0x3C Minimum 3 3V Analog Current Threshold Default Value 0x0 disabled Alternatively Voltage level used for current calc A13V0_MIN_TH
29. ne value in the DAC Memory in the Registers Block If hamming decoding is enabled it immediately verifies the contents of the addressed DAC Memory location If a single bit error is found it corrects the given DAC Memory location and goes on to shift the value to the addressed DAC If it is a double error this is reported in a status register and the given DAC channel is skipped When shifting in data it does it in the following sequence data to all 8 channels in one DAC NOOP command Update output command Power up Command The NOOP command is needed to verify that the last channel is correctly shifted in Only the channels that are correctly shifted in and are without double bit hamming errors are updated The Power up command is sent to all channels pulling the output of the DAC to OV for the channels that are in error PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 26 31 CSP24 1001 Table 5 4 HVDAC setup including mapping of CSP 5 4 11 Hamming Code Hamming Decoder Module The hamming decoder module is used in both the Register Block for ADC thresholds and in the DAC interface for DAC values If a single error is found it is reported and corrected If a double error is found it is just reported The hamming code is generated the following way h 0 d 0 d 1 d 3 d 4 d 6 d 8 d 10 h 1 d 0 d 2 d 3 d 5 d 6 d 9
30. nt Threshold Default value 0x014 0 858 A Alternatively Voltage level used for current calc A13V0_MAX_TH 0x4D Maximum 13 0V Analog Voltage Threshold Default Value 0x0 disabled A13V0C_MAX_TH Ox4E Maximum 13 0V Analog Current Threshold Default Value OxOOF 0 334 Alternatively Voltage level used for current calc Table 4 3 ADC Maximum Threshold Value Memory PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 16 31 Memory Addr Description Conv factor location name 0x50 Temperature for ADC IC13 0 25 C ADC counts Alternatively Voltage level used for current calc counts 3 3V Digital Voltage 6 44 mV ADC counts Alternatively Voltage level used for current calc counts TEMP2 uH LP c for ADC IC15 ADC A6nV0 0x56 6 0V Analog Voltage 4 88mV ADC counts 1000 x Alternatively Voltage level used for current calc counts Default Data Value 0x1E8 5 6 V counts Alternatively Voltage level used for current calc counts counts counts Alternatively Voltage level used for current calc counts counts Alternatively Voltage level used for current calc counts Table 4 4 ADC Value Memory Please note that the current conversion factors are only correct if current mode is set in the Threshold register for given ADC value PHOS BC specification_v3 4 doc Created by Johan Alm
31. ock Enables Sampling Clock Enables Readout Clock Power Switch for Shaper Power Regulator Power switch for Bias Power Regulator Power switch for ALTRO Power 5 Regulator ETT T si T T Ye Status and Configuration Default value 0x2220 15 This bit is set to 1 when the BC has completed the transaction with the mADC It is reset at the beginning of every transaction 14 8 5 timeout value Max num of clks for each transaction on the ALTRO bus when BC is master 7 0 sclk warning ratio 1 Value of Slow Control data line 0 Value of test mg input Latch LO L2 SCLK counters Clear LO L2 SCLK counters Clear Error Status Register Reset all the ALTROs Reset Board Controller to default values Start Conversion Readout monitor ADC SCEVL 0x1C T Yes Scan Event length registers in all ALTRO channels EVLRDO Ox1D Start readout of Event Length Hitmap register UPDATEHV UpdateHV BCVERSION 15 0 0x20 R Board Controller Version RW T T T T T T T PHOS BC specification v3 4 doc Created by Johan Alme Digital module requirement specification 12 31 Register name Addr Type Allow Description f Breast VTS_HIGH 14 0 VTS LOW 14 0 R W Voltage Temperature Status register 0 TEMP1 over th 1 DAVO over th 2 D4VOC over th 3 D3V3 over th 4 D3V3C over th 5 TEMP2 over th 6 A6nVO over th 7 A6nVOC over th
32. on 4 31 1 Document control 1 1 Revision history Document status Responsible 24 05 07 First draft 02 16 08 07 Updated after design of v3 0 1 2 References PCM 2 0 Ver 2 0 Aug PCM 2 0 8Based on PHOSS 2006 FEE board controller 0 1 HUST AD7416_AD7417_7418 pdf Rev G 2004 Analog Devices 10 Bit Digital Temperature Sensor AD7416 and Four Single Channel ADCs AD7417 AD7418 3 FEE V1 1b pdf V1 1 27 Sep 05 PHOS FEE v1 1 Schematics PHOS User Manual pdf Rev 2 1 4 PHOS Basics for the User 07 5 MAX5308 MAX5309 pdf Rev 0 8 01 Maxim Low Power Low Glitch Octal 10 Bit Voltage Output DACs with Serial Interface version 2 3 03 Programmable Logic Device Family PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 5 31 2 Motivation The Front End Electronics in PHOS is consisting of one Readout Control Unit RCU and 28 Front End Cards FECs connected to the RCU via two separate branches On each FEC an SRAM based FPGA is situated the Board Controller Since the Front End Electronics is physically unavailable when PHOS is fully commissioned it must be possible to check the status via software during operation and quickly respond to any error situation that might occur The purpose of the Board Controller is to read crucial values on the FEC such as voltages currents and temperatures If these values exceed given programmable t
33. or any reason This has a very low priority PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 28 31 6 Other requirements 6 1 Clock strategy 40 MHz System Clock 10 MHz Sampling Clock counted 6 2 Reset strategy Asynch reset negative polarity 6 3 Power strategy N A 6 4 Test strategy 6 4 1 Functional and Post Place and Route Verification p DCS RCU interface RCU fw v190606 synthesized branch_select ALTRO bus amp 2 bus slow control ALTRO bus only FEC 0 FEC ALTRO DUT FEC1 2 num_of_fecs 1 DAC 4 ADC 7417 Figure 6 1 Testbench setup for functional verification and post place and route simulation The design has been verified both functionally and post place and route with Questasim using the testbench setup as given in Figure 6 1 The process p_stimuli uses procedures to read write using the DCS interface on the RCU The RCU Module is a synthesized simulation model generated by Xilinx ISE based on RCU firmware version 190606 The Board Controller DUT also connects to simple simulation models of the ADCs a modified opensource I2C slave simulation model and the DACs that reports to the log when they are being accessed The simulation model for the ALTRO is a slightly modified simulation downloaded from the TPC FEE PHOS BC specifica
34. ounters for each byte received It takes 78 clks system clock to received and for convenience the modules times out and goes back to idle when 128 clks has passed PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 23 31 5 4 7 Interface Decoder The Interface Decoder is a state machine that decodes the information on the ALTRO bus or on the I2C bus It sets error status information for the received addresses and decodes the command trigger addresses into single command lines 5 4 8 Registers Data to from interfaces Registers Data from ADC IF 5 ADC value Memory ADC Low Comp thr Memory arator ADC High 6 SCLK counter thr Memory Register Block Hamming LO Counter gt Data to from DAC IF decoder DAC value T i e henas L2a counter VTC Status memory Figure 5 2 Registers module with all the different submodules and memories given The Registers Module consists of 3 counters a Register Block and a VTC Voltage Temperature and Current Status Module as shown in Figure 5 2 The slow clock counter counts the sampling clock for housekeeping purposes In addition there are two trigger counters that count the LO and L2a triggers received The Register Block is the important module and holds all the registers in the Board Control
35. rammable threshold set a over temperature flag OTI This is not used by the Board Controller since this functionality is kept internal in the BC firmware For the conversion factors of the different ADC values please see the adc value adress table Table 4 4 PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 25 31 Location on FEE 000 Top Between ALTRO 0 and ALTRO 2 001 Power Regulator Area 14 010 Bottom Between ALTRO 3 ALTRO 4 Table 5 3 ADCs used for monitoring in PHOS FEE 5 4 10 DAC Interface The DAC interface is responsible for setting the BIAS voltages on all the CSPs on the FEC There all together 4 DACs on the board connected with 4 separate serial buses Each DAC has 8 channels Adding it up it will be all together 32 DAC settings to be made The DAC itself has a serial interface where 16 bits needs to be shifted to the DAC to set one channel The 4 DACs have 4 separate data out data in and chip select signals and one common clock line On the data out line from the DAC the bits that was shifted in last time is directly shifted out In the DAC interface this is used to verify that the bits shifted in the last time is correctly received by the DAC The DAC interface consists of a state machine that gets out of idle state when the HV update signal is high or when the continuously updating is selected It then read one by o
36. rd from the RCU for a short while wile doing this When the hitmap register is filled it waits for the event length readout command on which it pushes the data to the RCU Please note The pushing of the data uses a gated version of the rdoclk as dstb as this is done originally This is not an ideal solution and might lead to glitches and misbehaviour of Sparse Readout Mode It would be better to let the dstb run on half the speed making a registered output as the dstb PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 22 31 5 4 6 Slow Control Slave Interface data rx HADD enable Slave RX 2 address gt Register addr ajea interface amp ctrl 4 5 Y A Signals Serializer Slave TX data data_tx Figure 5 1 Sketch of Slow Control Interface The Slow Control Interface consists of five sub modules FEC address A state machine listening for the I2C start condition and then decode the first byte transferred If this byte contains the address of this card bits 5 to 1 or is broadcast bit 6 the state machine acknowledges the request If the request is a write request bit 0 is low then the receiver is started If the request is a read request bit 0 high the transmitter is started Serializer shift register of 1 byte Serial input is the 2 bus serial data P
37. s the expected direction of the current 14 0 for the current measurements given by DIFF register 0 Current Vpreviou Veurrent 1 Current Veurrent Vpreviou Default Value 0 0080 TRANS ONTT 15 0 0x2B fia Number of acks sent to RCU Number of strobes received from RCU LAST ADDR 0x2C 7 4 MSB of last valid address 7 0 received 3 0 MSB of last not valid address received D Ire TM 15 0 FEC Mme prr ug ADD ALIS 0 the FEC Min Threshold P E Su us Threshold DW THROAT RE OEE the ADCs Memory 1 4 0 Ox3E 15 11 Hamming code 10 0 Threshold for Voltage 1 Threshold for Current 9 0 Data value ADC Max Threshold 0x40 RW Max Threshold for the ADCs Memory 14 0 Ox4E 15 11 Hamming code 10 0 Threshold for Voltage 1 Threshold for Current 9 0 Data value ADC Data 0x50 RW Yes Data values from the ADCs Memory 9 0 Ox5E 9 0 Data value HV DAC settings 0x60 RW Yes High voltage bias value for CSPs memory 0x7F 0x60 0x67 CSP 23 down to CSP 16 14 0 0x68 0x6F CSP 0 to CSP 7 0x70 0x77 CSP 8 to CSP 15 0x78 0x7F CSP 31 down to CSP 24 15 11 Hamming code 10 Don t care not used 9 0 Value to Write Table 4 1 List of registers that can be accessed externally Note The registers marked with R W and Broadcast Yes be written to when unlock bit is set PHOS BC specification_v3 4 doc Created by Johan Al
38. t the test is disabled The VTS registers and CSR1 are set after the configurable number 1 3 of times a threshold is violated for each value The number of times is set by CSR2 bit 8 7 and is default set to 1 If a given threshold is unequal to 0 this means that a violation of this threshold will trigger the interrupt line to the RCU 5 2 Main Functional Changes From PCM v2 0 HUST Removal of USB communication Removal of Board ID register Hamming encoding and TMR of static registers Some register remapping Thresholds and ADC values stored in memories Removed Testmode 5 3 Project Setup The complete design is checked into the CVS Repository of the Experimental Nuclear Physics group University of Bergen under the folder vhdlcvs phos bc File Qj Foldr Description bc cr mti Questasim project file bc mpf Questasim configuration file func do Executes functional simulation ppr do Executes post place and route simulation fmd rar code ref Fmd project http web ift uib no kjekscgi bin viewcvs cgi PHOS BC specification_v3 4 doc Created by Johan Alme Digital module requirement specification 18 31 2 0 061130 2 2 0 061130 code rar PHOS BC specification doc PHOS specification v3 1 doc conv factor xls Graphics vsd bc vhd bc tb2 vhd register config vhd altro sw mask in vhd alprotocol if vhd altrobusinterface vhd altrobusinterface tb vhd inter
39. tion_v3 4 doc Created by Johan Alme Digital module requirement specification 29 31 webpages Two generic variables makes it possible to choose between functional or post place and routes simulation as well as the number of front end cards to include The front end cards will be placed on the same branch The testbench is semi selftestable Some functions as the updating of the DACs and doing ADC readback are done by simply inspecting the log afterwards Other functionality is verified by inspection such as the setting of the interrupts etc 6 4 2 Functional Coverage Functional Coverage has not been done 6 4 3 Hardware Verification The design has been functionally verified in hardware with a setup consisting of one RCU and one FEC connected to FEC address 9 on branch A The RCU fw version 181206 and DCS board fw version 2 7 The ALTROs on the FEC is broken so it has not been possible to test if the BC affects data readout But is has been verified that register access is no problem Cases that has been functionally verified is Altro bus communication Slow Control communication DAC update on command and continuously ADC readback on command and continuously Single and double hamming error Interrupt handling from RCU Altro communication see that BC does not mingle with the data bus Trigger counters while doing data readout Broadcast In addition a stress test has been performed of the Slow Control Interface and
40. to the ADCs Ackn ALTRO bus acknowledge line Error ALTRO bus error line trsf ALTRO bus transfer line dstb ALTRO bus data strobe bcout add 4 0 Masked address to ALTRO altrops en ALTRO power supply enable biasps en BIAS power supply enable shaperps en SHAPER power supply enable oeab 1 ALTRO bus GTL driver enable oeab h ALTRO bus GTL driver enable oeba ALTRO bus GTL driver enable oeba h ALTRO bus GTL driver enable ctr in CONTROL bus GTL driver enable ctr out CONTROL bus GTL driver enable rcu sda out Slow control data out bc int Interrupt line sensor scl ADC 12C interface sensor_sda ADC 12 interface convst ADC interface convert start dac_clk_en DAC serial interface dac_sclk DAC serial interface dac ldac DAC serial interface dac sel 3 0 DAC serial interface dac din 3 0 DAC serial interface Table 5 2 Main output signals with explanations 5 4 2 Drivers Glue Logic The purpose of the Drivers Module is twofold Firstly it is in charge of driving the direction of the GTL bus drivers for the ALTRO bus and the CONTROL bus and secondly it tristates the signals on the bus since the Front End Bus is common for all FECs connected to the RCU 5 4 3 ALTRO Switch Mask In The ALTRO Switch Mask In Module is a combinatorial masking of ALTRO bus input signals and internal mask bits The internal mask bits are the power supplies enable bits from CSR3 If the ALTRO power supplies are turned off all communication with the ALTROs ar
41. very once in a while for instance this can be done every time the ADC values are read back all kinds of status registers must be read back and verified is correct PHOS BC specification v3 4 doc Created by Johan Alme
Download Pdf Manuals
Related Search