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M30201 Group USER`S MANUAL

1. L 0 4 0 6 0 8 li 1 4 x 0 13 y 0 1 0 0 10 b2 0 35 l2 1 3 Detail F MD 10 6 170 stENESAS Renesas Technology Corp Chapter 2 Peripheral Functions Usage Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Protect 2 1 Protect 2 1 1 Overview Protect is a function that causes a value held in a register to be unchanged even when a program runs away The following is an overview of the protect function 1 Registers affected by the protect function The registers affected by the protect function are a System clock control registers 0 1 addresses 000616 and 000716 b Processor mode registers 0 1 addresses 000416 and 000516 c Port P4 direction register address 03EA16 The values in registers 1 through 3 cannot be changed in write protect state To change values in the registers put the individual registers in write enabled state 2 Protect register Figure 2 1 1 shows protect register Protect register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PRCR 000A16 XXXXX0002 IEO FW i Enables writing to system clock i control registers 0 and 1 addresses 0 Write inhibited 000616 and 000716 1 Write enabled Enables writing to processor mode registers 0 and 1 addresses 000416 and 000516 Enables writing to port
2. Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 22 Operation timing of one shot mode external trigger selected 196 tENESAS Renesas Technology Corp Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting one shot timer mode and functions Timer AO mode register Address 039616 Selection of one shot timer mode Pulse output function select bit 1 Pulse is output Note 1 External trigger select bit 1 Rising edge of TAOIN pin s input signal Trigger select bit 1 Selected by event trigger select register ________________ Q Must always be 0 in one shot timer mode Count source select bit b7 b6 Count Count source period 00 f1 source f XIn 10MHz f XcIN 32 768kHz 01 fs 100ns 10 fs2 800ns 11 fce32 fcs2 3 2us 976 56us Note 1 Set the corresponding port direction register to 1 output mode S Clearing timer AO interrupt request bit Refer to Precaution for Timer A one shot timer mode b7 b0 boddxtol T Interrupt request bit Timer AO interrupt control register Address 005516 TAOIC Setting Trigger select register b7 b0 TT Tefo Trigger select register Address 038316 TRGSR Timer AO event trigger select bit 0 0 Input on TAON is selected
3. 10 Key input interrupt control register 004D16 2 46 A D control register 0 03D616 a E interrupt 004E16 i 47 A D control register 1 03D716 12 ter transmit interrupt control 005116 2 48 Port PO direction regis 03E216 O aie receive interrupt contro 005216 7 49 Port P1 direction regis 03E316 A ister transmit interrupt control 005316 i 50 Port P2 direction regis 03E616 15 UART1 receive interrupt contro 005416 2 51 Port P3 direction regis 03E716 register 16 Timer AO interrupt control regis 005516 52 Port P4 direction regis 03EA16 17 Timer XO interrupt control regis 005616 7 53 Port P5 direction regis 03EB16 18 Timer X1 interrupt control regis 005716 54 Port P6 direction registe O3EE16 19 Timer X2 interrupt control regis 005816 7 55 Port P7 direction registe 03EF16 20 Timer BO interrupt control regis 005A16 2 56 Pull up control register 0 03FC16 4 21 Timer B1 interrupt control regis 005B16 2 57 Pull up control register 1 03FD16 0016 Port P1 drive capacity control register 22 INTO interrupt control register 005D16 7 58 03FE16 0016 23 INT1 interrupt control register 005E16
4. Interrupt priority level IPL 0 Interrupt enable flag I 0 Setting interrupt except clearing wait mode Interrupt control register KUPIC Address 004D16 Address 004E16 Address 005116 005316 Address 005216 005416 Address 005516 2 Address 005616 to 005816 Address 005A16 005B16 b7 b0 0 0 0 Interrupt priority level select bit b2 b1 b0 000 Interrupt disabled uw ou Noho weno o Continued to the next page Figure 3 7 2 Set up procedure of controlling power using wait mode 1 2tENESAS 359 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications Continued from the previous page Canceling protect b7 50 Protect register Address 000A16 PEPERIT pacer Enables writing to system clock control registers 0 and 1 address 000616 and 000716 1 write enabled E Switching system clock b7 bo Syst lock control register 0 Add 0006 rT TT ETT le control register ress 16 System clock select bit 1 XCIN XCOUT Stopping main clock b7 bo System clock control register 0 Address 000616 ee ey Xo astero i Main clock XIN XOUT stop bit 1 Off Interrupt enable flag I flag 4 lt F_wity 1 WAIT instruction NOP instruction X 5 INTO interrupt request generated
5. Must be fixed to 001 Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mode _____________ Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Sleep select bit Must be 0 in clock synchronous I O mode Setting UARTO transmit receive control register 0 b7 b0 ofo a fo UARTO transmit receive control register 0 UO0CO Address 03A416 BRG count source select bit b1 b0 0 0 fi is selected 0 1 fa is selected 1 0 f32 is selected 1 1 fc is selected Must be 0 in clock synchronous I O mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed ____________ Must be 1 in clock synchronous I O mode ___________ Data output select bit Note 0 TxDi pin is CMOS output 1 TxDi pin is N channel open drain output ___ _ _ _ CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note Set the corresponding port direction register to 1 output mode Setting UART transmit receive control register 2 b7 UART transmit receive control register 2 UCON Address 03B016 UARTO tr
6. Performs count only for the period in which the TXiINouT pin is at H level Operation 1 When the count start flag is set to 1 and the TXiINOUT pin inputs at H level the counter performs a down count on the count source 2 When the TXiINOUT pin inputs at L level the counter holds its value and stops 3 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 4 Setting the count start flag to O causes the counter to hold its value and to stop Note e Make the pulse width of the signal input to the TXiINOUT pin not less than two cycles of the count source n reload register content 1 Start count 3 Underflow 2 Stop count to 4 Stop count Counter content hex Start count again i i i 0 by Time Set to 1 by software i Geared to 0 by i software N 72 1 by software Count start flag ad i TXiiNouT pin H input signal s i Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 request bit g Figure 2 4 6 Operation timing of timer mode gate function selected 226 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting timer mode and functions Timer Xi mode register
7. eeeeeee 219 24 Timer X i alse aieide el ededt dette Qe tauead tc a e dea dads dared a a haat 220 P ARONIA E E TEE EE E A E A EE 220 2 4 2 Operation of Timer X timer mode ssssssssssssessrsssstsssrsrsissirsstisssinssstnstnnntunnennnsnnnntnnnntnn ee 224 2 4 3 Operation of Timer X timer mode gate function Selected cceeeeeeeeeeeceeeeeeeeteeeeeeeees 226 2 4 4 Operation of Timer X timer mode pulse output function selected ceeeeeeeeeeeees 228 2 4 5 Operation of Timer X event counter mode reload type Selected ceceeeeeeeesteeeeeneees 230 2 4 6 Operation of Timer X event counter mode free run type selected cceceeeeeeeeerreees 232 2 4 7 Operation of Timer X one shot timer mode ceeeeeeeeeeeeeeeeeeaeeeeeeeeeeaeeseeeeeesaeeeeeneees 234 2 4 8 Operation of Timer X pulse period measurement mode ceeeeeeeeeeeeeeeeeeeeeeeteaeeeteneees 236 2 4 9 Operation of Timer X pulse width measurement MOE cceeeeeeeeeeeeeeteeeeeeeeeteaeeeteneeees 238 2 4 10 Operation of Timer X pulse width modulation mode 16 bit PWM mode selected 240 2 4 11 Operation of Timer X pulse width modulation mode 8 bit PWM mode selected 242 2 4 12 Precautions for Timer X timer mode event Counter mode ee ceeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 244 2 4 13 Precautions for Timer X one shot timer mode eee cee eeeee eee eeeeeeeeeeeeeeeeeeeeeneaeeee
8. Direction register lt Data bus Port latch z Input to respective peripheral functions Pull up selection Direction register e gt i lt Data bus Port latch Pull up selection _ Direction register e gt output Data bus 4 Port latch Input to respective peripheral functions P4o P43 P44 P45 Figure 1 90 Programmable I O ports 1 100 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up selection Pio to P17 Direction register lt q gt a bos Drive capacity control register Pull up selection Direction register m lt Data bus 4 Port latch Analog input Serial I O input Pull up selection Direction register gt q Data bus Port latch P50 P53 P54 Analog input Pull up selection Direction register D gt
9. lt Data bus Port latch Serial clock input Analog input Figure 1 91 Programmable I O ports 2 stENESAS 101 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up selection Direction register lt P60 to P67 Port latch Analog input Figure 1 92 Programmable I O ports 3 102 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Port Pi direction register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PDi i 0 to 7 03E216 03E316 03E716 03EA16 0016 03EB16 03EE16 03EF16 0016 Bit symbol ___Bitname Function RW PDi_O Port Pio direction register 0 0 Port Pit directi ist 0 Input mode BYES EEE Functions as an input port 1 Output mode Functions as an output port i 0107 except 2 POLS Port Pie direction register Note 1 Set bit 2 of protect register address 000A16 to 1 before rewriting to the port P4 direction register Note 2 Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 These bits can either be set nor reset When read its contents
10. OFFFFC16 to OFFFFF16 Reset vector Figure 1 117 ID code storage addresses 154 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version Status Register SRD The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error It can be read by writing the read status register command 7016 Also the status register is cleared by writing the clear status register command 5016 Table 1 80 gives the definition of each status register bit After clearing the reset the status register outputs 8016 Table 1 80 Status register SRD SRDO bits Status name q Definition g SR7 bit7 Status bit Ready Busy SR6 bit6 Reserved SR5 bit5 Erase bit Terminated in error Terminated normally SR4 bit4 Program bit Terminated in error Terminated normally SR3 bit3 Reserved SR2 bit2 Reserved z SR1 bit1 Reserved z SRO bit0 Reserved 7 Status bit SR7 The status bit indicates the operating status of the flash memory When power is turned on 1 ready is set for it The bit is set to O busy during an auto write or auto erase operation but it is set back to 1 when the operation ends Erase Status SR5 The erase status reports
11. 172 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Protect 1 Clearing the protect set to write enabled state bO Protect register Address 000A16 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 1 Write enabled Enables writing to port P4 direction register address 03EA16 0 Write inhibited 1 Write enabled 2 Setting system clock control register i i 0 1 3 Setting the protect set to write inhibited state Protect register Address 000A16 ox YNN PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 0 Write inhibited Enables writing to port P4 direction register address 03EA16 0 Write inhibited 1 Write enabled 4 Clearing the protect set to write enabled state b0 Protect register Address 000A16 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 0 Write inhibited 1 Write enabled Enables writing to port P4 direction register address 03EA16 1 Write enabled Changes in port P4 direction register Figure 2 1 2 Set up procedure for protect function 2 1 3 Precaution for Protect 1 The write enable bit of port P4 direction register goes to 0 when the next write instruction is executed after write enabled state is
12. 3 Canceling protect b7 bo PECETA Protect register Address 000A16 PRCR L Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 1 Write enabled ye 3 Setting operation clock after returning from stop mode When operating with XIN after returning When operating with XCIN after returning b7 0 System clock control register 0 System clock control register 0 oT Te Address 000616 CMO Address 000616 cmo Main clock X N XouT stop bit Port Xc select bit On XCIN XCOUT generation System clock select bit _____________________ System clock select bit XIN XOUT XCIN XCOUT As this register becomes setting mentioned above when As this register becomes setting mentioned above when operating with XCIN operating with XIN count source of BCLK is XIN count source of BCLK is XcIN the user does not need to set it again the user does not need to set it again When operating with XIN set port Xc select bit to 1 before setting system clock select bit to 1 The both bits cannot be set at the same time Me 3 All clocks off stop mode b7 bo System clock control register Address 000716 ofo of of4 chr All clock stop control bit 1 All clocks off stop mode Reserved bit Must be set to 0 All clocks off
13. Data present in transmit register during transmission No data present in transmit register transmission completed Data present in transmit register during transmission No data present in transmit register transmission completed TXEPT Transmit register empty Set this bit to 1 D i TXDi pin is CMOS output 0 TXDi pin is CMOS output ata output select bit TXDi pin is N channel 1 TXDi pin is N channel open drain output open drain output A Transmit data is output at M o CKPOL CLK polarity select bit falling edge of transfer clock ust alwaysibe 10 and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge UFORM Transfer format select bit 0 LSB first g Note UART1 cannot be used in clock synchronous serial I O Figure 2 6 4 UARTi related registers 2 274 2rCENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART UARTI transmit receive control register 1 b7 b6 b5 b4 b3 b2 bi b0 Address 03A516 03AD16 Symbol UiC1 i 0 1 When reset 0216 Function Note 1 During clock synchronous serial I O mode Bit name Transmission disabled Transmission enabled Transmit enable bit Transmit buffer empty flag Data present in transmit buffer register No data present in trans
14. Disable interrupts Clear TAOIC int priority level and int request bit Dummy read Enable interrupts Push Flag register onto stack Disable interrupts Clear TAOIC int priority level and int request bit Enable interrupts The reason why two NOP instructions or dummy read are inserted before FSET in Examples 1 and 2 is to prevent the interrupt enable flag from being set before the interrupt control register is rewritten due to effects of the instruction queue If changing the interrupt control register using an instruction other than the instructions listed hear and if an interrupt occurs associated with this register during execution of the instruction there can be instances in which the interrupt request bit is not set To avoid this problem use one of the instruc tions given below to change the register Following instructions AND OR BCLR or BSET 36 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt Sequence An interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here If an interrupt occurs during execution of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle
15. Interrupt enable flag I flag lt 1 3 Canceling protect b7 b0 PETEA TT Protect register Address 000A16 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 C 1 Write enabled a 3 Control of CPU clock b7 b0 System clock control register 1 b0 System clock control register 0 0 0 0 0 Address 000716 CM1 Address 000616 CMO Reserved bit WAIT peripheral function clock stop bit Note 2 Must be set to 0 0 Do not stop f1 fs f32 in wait mode Main clock division select bit Stop f1 f8 f32 in wait mode b7 b6 0 0 No division mode Port Xc select bit 0 1 Division by 2 mode 0 I O port 10 Division by 4 mode XCIN XCOUT generation 1 1 Division by 16 mode Main clock XIN XOUT stop bit 0 On Off Main clock division select bit 0 0 CM16 and CM17 valid Division by 8 mode System clock select bit Note 1 Note 2 0 XIN XOUT XCIN XCOUT Note 1 When switching the system clock it is necessary to wait for the oscillation to stabilize Me 2 Set the WAIT peripheral function clock stop bit to O when the system clock select bit is 1 C 4 WAIT instruction Wait mode Figure 2 11 6 Example of wait mode set up 328 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Po
16. 2 2 8 Operation of timer A 2 phase pulse signal process in event counter mode multiply by 4 mode selected In processing 2 phase pulse signals in event counter mode choose functions from those listed in Table 2 2 7 Operations of the circled items are described below Figure 2 2 18 shows the operation timing and Figure 2 2 19 shows the set up procedure Table 2 2 7 Choosed functions Count operation type Reload type Processing 2 phase Normal processing O Free run type pulses O 4 multiplication processing Operation 1 Setting the count start flag to 1 causes the counter to count effective edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 3 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 Note e The up count or down count conditions are as follows Table 2 2 8 The up count or down count conditions Input signal to the Input signal to the Input signal to the Input signal to the TAOOUT pin TAOIN pin TAOOUuT pin TAOIN pin H level Rising H level Falling L level Falling L level Rising Rising L level Rising H level Falling H level Falling L level 1 Start co
17. Count operation type select bit 0 Reload type 0 Must always be 0 in event counter mode Continued to the next page Figure 3 1 3 Set up procedure of long period timers 1 340 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Continued from the previous page Setting trigger select register Corer ee register Address 038316 Timer X1 event trigger select bit b5 b4 10 TXO overflow is selected Setting divide ratio b15 ue b0 Timer X1 register Address 038B16 038A16 Setting count start flag ST Od ou ean flag Address 038016 Timer X0 count start flag 1 Starts counting Timer X1 count start flag 1 Starts counting Start counting Figure 3 1 4 Set up procedure of long period timers 2 tENESAS 341 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 2 Variable Period Variable Duty PWM Output Overview In this process Timer XO and A1 are used to generate variable period variable duty PWM out put Figure 3 2 1 shows the operation timing Figure 3 2 2 shows the connection diagram and Figures 3 2 3 and 3 2 4 show the set up procedure Use the following peripheral functions e Timer mode of timer X e One shot timer mode of timer X Specifications
18. Setting trigger select register bf Trigger select register Address 038316 TRGSR Timer X0 event trigger select bit b3 b2 0 1 TB1 overflow is selected 1 0 TAO overflow is selected 1 1 TX1 overflow is selected Timer X1 event trigger select bit b5 b4 0 1 TB1 overflow is selected 1 0 TXO overflow is selected 1 1 TX2 overflow is selected Timer X1 event trigger select bit b7 b6 0 1 TB1 overflow is selected 1 0 TX1 overflow is selected 1 1 TAO overflow is selected k Setting divide ratio b15 b8 C Bo _b bO Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 o Can be set to 000016 to FFFF16 Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 11 Set up procedure of event counter mode reload type selected RENESAS 231 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 6 Operation of Timer X event counter mode free run type selected In event counter mode choose functions from those listed in Table 2 4 5 Operations of the circled items are described below Figure 2 4 12 shows the operation timing and Figure 2 4 13 shows the set up procedure Table 2 4 5 C
19. ccecceeeceeee eee enne eee teeta ee eee NARRAR ANNEN ee KE EEEREN EARNAN P186 e Event counter mode free run type Operation ccccecceeeceeeneeeeeneeeeeaeeeseeeeeesaeeseeeeeessaeeeseneees P188 Furthermore Timer A has a 2 phase pulse signal processing function which generates an up count or down count in the event counter mode depending on the phase of the two input signals Operation of the 2 phase pulse signal processing function in normal event counter mode P190 Operation of the 2 phase pulse signal processing function in 4 multiplication mode P192 c One shot timer mode In this mode the timer is started by the trigger and stops when the timer goes to O The trigger can be selected from the following 3 types an external input signal an overflow of the timer or a software trigger The pulse output function can also be selected Please refer to the timer mode explanation for details as the operation is identical e Operation in one shot timer mode effected by software ccceceeeeeeeeceeeeeeeeeeeseeeeeetsaaeeneneees P194 e Operation in one shot timer mode effected by an external trigger ccccceeseeeeeereeeetteeeeeeees P196 d Pulse width modulation PWM mode In this mode the arbitrary pulses are successively output Either a 16 bit fixed period PWM mode or 8 bit variable period mode can be selected The trigger for initiating output can also be selected Please refer to the
20. Figure 4 3 4 Operation of saving registers 2tENESAS 377 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 4 Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register FLG as it was immediately before the start of interrupt sequence and the contents of the program counter PC both of which have been saved in the stack area Then control returns to the program that was being executed before the acceptance of the interrupt request so that the suspended process resumes Return the other registers saved by software within the interrupt routine using the POPM or similar instruc tion before executing the REIT instruction 4 5 Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling checking whether interrupt requests are made the interrupt assigned a higher priority is accepted Assign an arbitrary priority to maskable interrupts peripheral I O interrupts using the interrupt priority level select bit If the same interrupt priority level is assigned however the interrupt assigned a higher hardware priority is accepted see Figure 4 5 1 Priorities of the special interrupts such as Reset dealt with as an interrupt assigned the highest priority watchdog timer interrupt etc are regulated by hardware Figure 4 5 2
21. Setting count start flag b7 bo Pe aT Sa flag Address 038016 Timer XO count start flag 1 Starts counting Timer X1 count start flag 1 Starts counting Start countin Figure 3 2 4 Set up procedure of variable period variable duty PWM output 2 RENESAS 345 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 3 Delayed One Shot Output Overview The following are steps of outputting a pulse only once after a specified elapse since an external trigger is input Figure 3 3 1 shows the operation timing Figure 3 3 2 shows the connection dia gram and Figures 3 3 3 and 3 3 4 show the set up procedure Use the following peripheral function e One shot timer mode of timer X Specifications 1 Set timer XO in one shot timer mode and set timer X1 in one shot timer mode with pulse output function 2 Set 1 ms an interval before a pulse is output in timer X0 and set 50 us a pulse width in timer X1 Both timer XO and timer X1 use f1 for the count source 3 Connect a 10 MHz oscillator to XIN Operation 1 Setting the trigger select bit to 1 and setting the count start flag to 1 enables the counter of timer XO to count 2 If an effective edge selected by use of the external trigger select bit is input to the TXOINOUT pin the counter begins a down count The counter of timer XO performs a down count on count
22. b7 b6 E E SEEE SEN TAOTGL Timer AO event trigger oo i select bit 0 0 Input on TAON is selected Note 0 1 TB2 overflow is selected Eeoa ina aaia aia e TAOTGH 1 0 TA4 overflow is selected fone 1 1 TA1 overflow is selected Note Set the corresponding port direction register to 0 This manual comprises of five chapters Use the suggested chapters as a reference for the following topics To understand hardware Specifications cccccceeeeeeeeeeeeeeeeeteeeeeeeeeeeees Chapter 1 Hardware To understand the basic way of using peripheral features and the operation timing cceeeeeeeeeees Chapter 2 Peripheral Functions Usage To observe applications of peripheral features 0ccee Chapter 3 Examples of Peripheral Functions Applications To understand interrupt timing in detail cceeceeeeeeeeeeeeeeeeteeeeeeeeeeeees Chapter 4 Interrupts To understand standard data cccceecceseeeeeeeeeeeeeeteees Chapter 5 Standard Characteristics This manual includes a quick reference immediately following the Table of Contents indicate the page of the topic to be pursued To find a page describing a specific register by the register address seeeeeeeeeeeeeees Quick Reference to Pages Classified by Address M16C Family related document list Usages Microcomputer development flow Type of document Selection of
23. stENESAS 227 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 4 Operation of Timer X timer mode pulse output function selected In timer mode choose functions from those listed in Table 2 4 3 Operations of the circled items are described below Figure 2 4 8 shows the operation timing and Figure 2 4 9 shows the set up procedure Table 2 4 3 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINOUT pin is at L level Performs count only for the period in which the TXiINOUT pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 Also the output polarity of the TXiINOUT pin reverses 3 Setting the count start flag to O causes the counter to hold its value and to stop Also the TXiINOUT pin outputs an L level n reload register content 1 Start count 2 Underflow 3 Stop count Counter content hex Cleared to 0 by et to 1 by software software Count start flag Pul
24. 1 Medium speed mode divided by 4 mode Medium speed mode divided by 16 mode CMO6 1 CMO07 1 BCLK f Xin 4 BCLK f Xin 16 Note 2 CM07 0 CMO6 0 CM07 0 CMO06 0 CM17 1 CM16 0 CM17 1 CM16 1 Ne CM05 0 CM05 1 CM04 O Main clock is oscillating CM04 1 Sub clock is stopped Main clock is stopped i N Sub clock is oscillating Medium speed mode Low power dissipation mode High speed mode divided by 2 mode BCLK f X BCLK f Xin 2 eee RA BCLK XoIn CM07 0 CMo6 0 CM07 0 CMO6 O ne CM17 0 CM16 0 CM17 0 CM16 1 GM07 1 CMO6 0 Medium speed mode Medium speed mode CMor j Nee 3 Notes 1 3 divided by 4 mode divided by 16 mode BCLK f Xin 4 BCLK f Xin 16 CM07 0 CMO06 0 CM07 0 CMO06 0 CM17 1 CM16 0 CM17 1 CM16 1 Ne S S Note 1 Switch clock after oscillation of main clock is sufficiently stable Note 2 Switch clock after oscillation of sub clock is sufficiently stable Note 3 Change CMO06 after changing CM17 and CM16 Note 4 Transit in accordance with arrow Figure 1 20 Clock transition stENESAS Renesas Technology Corp Main clock is oscillating Sub clock is oscillat
25. Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O b7 Setting count start flag b0 Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 9 Set up procedure of timer mode pulse output function selected tENESAS 229 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 5 Operation of Timer X event counter mode reload type selected In event counter mode choose functions from those listed in Table 2 4 4 Operations of the circled items are described below Figure 2 4 10 shows the operation timing and Figure 2 4 11 shows the set up procedure Table 2 4 4 Choosed functions Count source Input signal to TXiinouT counting falling edges Input signal to TXiINouT counting rising edges Timer overflow TB1 TAO TXi overflow Pulse output function No pulses output Pulses output Count operation type Reload type Free run type Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 3 Setting the count start flag to O causes
26. Figure 5 1 1 loH VOH standard characteristics of ports PO to P7 Vcc 5V voL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 2 loL VOL standard characteristics of ports PO to P7 Vcc 5V VoL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 3 lot VOL standard characteristics of port P1 Vcc 5V HIGH POWER stENESAS 387 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 4 IOH VOH standard characteristics of ports PO to P7 Vcc 3V VoL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 5 lot VoL standard characteristics of ports PO to P7 Vcc 3V 0 1 2 3 voL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 6 loL VoL standard chara
27. Internal address signal Figure 1 12 Reset sequence RENESAS 15 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Reset Processor mode register 0 000416 33 Timer BO mode register 039B16 Processor mode register 1 000516 34 Timer B1 mode register 039C16 System clock control register 0 000616 35 Par transmit receive mode 03A016 36 UARTO transmit receive control register 0 Address match interrupt a 37 UARTO transmit receive control 03A516 enable register 000916 register 1 38 UART1 transmit receive mode register 39 UART1 transmit receive control register 0 Address match interrupt 001016 40 UART1 transmit receive control 03AD16 register 0 register 1 7 41 UART transmit receive control M 001116 41 register 2 03B016 001216 42 io po control register 0 03B416 Address match interrupt 001416 43 Flash memory control register 1 03B516 register 1 Note 001516 44 Flash command register 03B616 System clock control register 1 000716 03A416 Protect register O00A16 034816 Watchdog timer control register 000F 16 03AC16 001616 45 A D control register 2 03D416
28. M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt Key Input Interrupt If the direction register of any of POo to P07 is set for input and a falling edge is input to that port a key input interrupt is generated A key input interrupt can also be used as a key on wakeup function for cancelling the wait mode or stop mode Figure 1 31 shows the block diagram of the key input interrupt Note that if an L level is input to any pin that has not been disabled for input inputs to the other pins are not detected as an interrupt Port P04 P07 pull up select bit Pull up ie Key input interrupt control register address 004D16 transistor Port P07 direction register Port P07 direction register Po7 KI7Z Pull up Port PQ6 direction transistor register Interrupt control Key input interrupt P06 Kl6 circuit request Port P01 direction Pull up register transistor POK O y Pull up register transistor PooKo O Da Port POo direction Figure 1 31 Block diagram of key input interrupt stENESAS 43 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value Two address match interrupts can be set each of which can be enabled and
29. Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 3 Operation of A D Converter in repeat mode In repeat mode choose functions from those listed in Table 2 7 3 Operations of the circled items are described below Figure 2 7 7 shows timing chart and Figure 2 7 8 shows the set up procedure Table 2 7 3 Choosed functions Operation clock AD Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit Analog input pin One of ANo pin to AN7 pin Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start operating 2 After the first conversion is completed the content of the successive comparison register conversion result is transmitted to A D register i The A D conversion interrupt request bit does not go to 1 3 The A D converter continues operating until the A D conversion start flag is set to O by software The conversion result is transmitted to A D register i every time a conversion is completed 1 Start A D conversion 2 Conversion result is transferred to the A D register 8 bit resolution 28 AD cycles 8 bit resolution 28 AD cycles 3 A D conversion 10 bit resolution 33 AD cycles 10 bit resolution 33 AD cycl
30. Note 1 Shading indicates transfer from flash memory microcomputer to peripheral unit All other data is trans Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 1 Flash Memory Version SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page 256 bytes in the flash memory sequentially one byte at a time Execute the page read command as explained here following 1 Transfer the FF16 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 From the 4th byte onward data Do D7 for the page 256 bytes specified with addresses As to A23 will be output sequentially from the smallest address first in sync with the rise of the clock RxDo M16C reception data A15 A23 data datao j data25 M16C transmit data P53 BUSY Figure 1 107 Timing for page read Read Status Register Command This command reads status information When the 7016 command code is sent with the 1st byte the contents of the status register SRD specified with the 2nd byte and the contents of status register 1 SRD1 specified with the 3rd byte are read _ RxDO 7016 M16C reception data SRD SRD1 M16C transmit data output_ _output P53 BUSY l Figure 1 108 Timing for reading the status register RENESAS 149 Renesas Technology Corp Mitsubishi microcomputers M30201 Group
31. O causes the counter to stop and to reload the content of the reload register Also the TXiINOUT pin outputs an L level At this time the timer Xi interrupt request bit goes to 1 n reload register content g 2 Stop count 1 Start count 3 Start count Start count 4 Stop count gt gt LO 7 Reload i Reload __ Reload Counter content hex Set to 1 by software Cleared to 0 by software Su Count start flag Write signal to one shot start flag k iX y One shot pulse output H H from TXiINOUT pin p LI Timer Xi interrupt T i f request bit g Pa Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 4 14 Operation timing of one shot mode 234 stENESAS Renesas Technology Corp Timer X Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting one shot timer mode and functions bi us oTo 11 Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of one shot timer mode Pulse output function select bit Note 1 Pulse is output TXiINOUT pin is a pulse output pin Invalid when the external signal is not used as a count source Trigger select bit 0 When the one shot start flag is set 1 0 Must always be 0 in one shot timer mode Count source select bit Co
32. Renesas Technology Corp Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 14 Precautions for Timer A event counter mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing shown in Figure 2 2 29 gets FFFF16 by underflow or 000016 by overflow Reading the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value 3 Please note the standards for the differences between the 2 pulses used in the 2 phase pulse signals input signals to the TAOIN pin and TAQOUT pin as shown in Figure 2 2 30 4 When free run type is selected if count is stopped set a value in the timer AO register again 1 Down count 2 Up count Reload i cameras ToT a Tole ma gare peoe ow roy Revae J 3 o jrn Revue Fero rrre rrer oooo n 1 _ Time Time n reload register content n reload register content Figure 2 2 29 Reading timer AO register Voc 5V f XIN 10MHz er Min Min TA4IN Vcc 3V f XIN 7MHz one wait TA20UT TASOUT TA40UT Figure 2 2 30 Standard of 2 phase pulses tENESAS 203
33. Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 XXKKKKEX Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Setting count start flag b7 bo Count start flag Address 038016 TABSR C Timer AO count start flag Start count Figure 2 2 27 Set up procedure of pulse width modulation mode 8 bit PWM mode selected stENESAS Renesas Technology Corp 201 Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 13 Precautions for Timer A timer mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing shown in Figure 2 2 28 gets FFFF16 Reading the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value Reload camrauevens E fe sf Read value Hex Pana ES FFFF gt Time n reload register content Figure 2 2 28 Reading timer AO register 202 stENESAS
34. Sleep select bit 0 Invalid Setting UARTIi transmit receive control register O i 0 1 b0 UARTO transmit receive control register 0 UOCO Address 03A416 UART1 transmit receive control register 0 U1C0 Address 03AC16 BRG count source select bit b1 b0 00 fi is selected 0 1 fa is selected 1 0 f32 is selected 1 1 fc is selected Must be 0 in UART mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in UART mode Data output select bit Note 0 TxDi pin is CMOS output 1 TxDi pin is N channel open drain output Must be 0 in UART mode Must be 0 in UART mode Note Set the corresponding port direction register to 1 output mode Setting UART transmit receive control register 2 b7 bo 0 UART transmit receive control register 2 UCON Address 03B016 UARTO transmit interrupt cause select bit 1 Transmission completed TXEPT 1 UART1 transmit interrupt cause select bit 1 Transmission completed TXEPT 1 Invalid in UART mode Must be 0 in UART mode Invalid in UART mode Must be 0 in UART mode Continued to the next page Figur
35. te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAOIN input LOW pulse width Table 1 60 Timer A input gating input in timer mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAO input LOW pulse width Table 1 61 Timer A input external trigger input in one shot timer mode Standard Parameter Min Max TAOIN input cycle time TAOIN input HIGH pulse width TAOIN input LOW pulse width Table 1 62 Timer A input external trigger input in pulse width modulation mode Symbol Parameter Max tw TAH TAOIN input HIGH pulse width tw TAL TAOIN input LOW pulse width Table 1 63 Timer A input up down input in event counter mode Standard Parameter Min Max tc UP TAOout input cycle time tw UPH TAOouT input HIGH pulse width tw UPL TAOouT input LOW pulse width tsu UP TIN TAOOuT input setup time th Tin UP TAOout input hold time stENESAS 121 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Timing requirements referenced to Vcc 3V Vss OV at Ta 20 to 85 C unless otherwise specified Extended operating temprature version 40 to 85 C Table 1 64 Timer B input counter input in event counter mode
36. 0 L Vref connect bit A D conversion start flag 1 Vref connected 0 A D conversion disabled Must be fixed to 0 Frequency select bit 0 0 fAD 4 is selected 1 faD 2 is selected ________________ A D input group select bit 0 Port P6 group is selected 1 Port P5 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANs4 Setting A D conversion start flag z 1 A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started na Start A D conversion Reading conversion result A D registerO Address 03C116 03C016 be A D register 1 Address 03C316 03C216 bO b7 A D register2 Address 03C516 030416 A D A D A D register 3 Address 03C716 03C616 register 4 Address 03C916 03C816 register5 Address 03CB16 03CA16 A D register6 Address 03CD16 03CC16 A D register 7 Address 03CF16 03CE16 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Setting A D conversion start flag b7 bo Fol LLLet i A D co
37. 59 Data registers RO R1 R2 R3 000016 24 Count start flag 038016 60 Address registers A0 A1 000016 25 Clock prescaler reset flag 038116 61 Frame base register FB 000016 26 One shot start flag 038216 62 Interrupt table register INTB 0000016 27 Trigger select flag 038316 63 User stack pointer USP 000016 28 Up down flag 038416 64 Interrupt stack pointer ISP 000016 29 Timer AO mode register 039616 65 Static base register SB 000016 30 Timer XO mode register 039716 66 Flag register FLG 000016 31 Timer X1 mode register 039816 32 Timer X2 mode register 039916 x Nothing is mapped to this bit Undefined The content of other registers and RAM is undefined when the microcomputer is reset The initial values must therefore be set Note This register is only exist in flash memory version Figure 1 13 Device s internal status after a reset is cleared 16 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Software Reset Software Reset Writing 1 to bit 3 of the processor mode register 0 address 000416 applies a software reset to the microcomputer A software reset has almost the same effect as a hardware reset The contents of internal RAM are preserv
38. 8 Registers related to timer X Figure 2 4 1 shows the memory map of timer X related registers Figures 2 4 2 and 2 4 3 show timer X related registers 005616 Timer XO interrupt control register TXOIC 005716 Timer X1 interrupt control register TX1IC 005816 Timer X2 interrupt control register TX2IC 038016 Count start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 Trigger select register TRGSR 038416 Up down flag UDF 038816 038916 038A16 038B16 Timer XO TX0 Timer X1 TX1 038C16 Timer X2 TX2 038D16 039716 Timer XO mode register TXOMR 039816 Timer X1 mode register TX1MR 039916 Timer X2 mode register TX2MR Figure 2 4 1 Memory map of timer X related registers RENESAS 221 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TXiMR i 0 to 2 039716 to 039916 0016 Bit symbol Bit name Function TMODO Operation mode Timer mode select bit Event counter mode 0 One shot timer mode or pulse period pulse width measurement mode Pulse width modulation PWM mode Function varies with each operation mode Count source select bit Function varies with each operation mode Note 1 Must set 00 to
39. A D Converter Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 7 A D converter and related registers Figure 2 7 1 shows the memory map of A D converter related registers and Figures 2 7 2 through 2 7 4 show A D converter related registers 004E16 A D conversion interrupt control register ADIC x a 03C016 A D register 0 ADO 03C116 03C216 A D register 1 AD1 03C316 03C416 A D register 2 AD2 03C516 03C616 A D register 3 AD3 03C716 03C816 A D register 4 AD4 03C916 03CA16 A D register 5 AD5 03CB16 E A D register 6 AD6 03CD16 register 6 03CE16 Eo PAT 03CFie register 7 a Figure 2 7 1 Memory map of A D converter related registers 286 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bt b0 Symbol Address When reset Ty fol 1 ADCONO 03D616 00000XXX2 Oio ptember ee Finan Analog input pin select bit ANo is selected AN1 is selected AN2 is selected i AN8 is selected AN4 is selected AN5 is selected AN6 is selected AN7 is selected Note 2 3 eo A D operation mode One shorimede select bit 0 Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 Note 2 A D conversion start flag 0 A D conversion disabled 1 A D conversio
40. ANo to AN5 6 pins ANo to AN7 8 pins Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo AN5o pin 2 After the A D conversion of voltage input to the ANo AN50 pin is completed the content of the successive comparison register conversion result is transmitted to A D register 0 3 The A D converter converts all pins selected by the user The conversion result is transmitted to A D register i corresponding to each pin every time A D conversion on the pin is com pleted The A D conversion interrupt request bit does not go to 1 4 The A D converter continues operating until the A D conversion start flag is set to O by software 1 Start A D conversion 2 AN1 AN51 conversion begins after 4 A F _ ANo AN50 conversion is complete 4 A D conversion l 3 Consecutive conversion is complete 8 bit reso ution 28 oAD cycles 8 bit resolution 28 aD cycles 10 bit resolution 33 aD cycles 10 bit resolution 33 oa cycles it a rari AD JLitit Set to 1 by software
41. Cleared to 0 by software A D conversion start flag A D register 0 x Result A D register 1 A D register i X Result Note When an frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 ad cycles for 8 bit resolution and 59 oAD cycles for 10 bit resolution Figure 2 7 11 Operation timing of repeat sweep 0 mode 296 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter va Selecting Sample and hold b7 b0 4 T T 1 olololi A D control register 2 Address 03D416 ADCON2 L A D conversion method select bit 1 With sample and hold Must be fixed to 0 Me zA Setting A D control register 0 and A D control register 1 b7 bo b7 0 0 1 A D control register 0 Address 03D616 ADCONO Invalid in repeat sweep mode 0 Repeat sweep mode 0 is selected Note 1 _ Must be fixed to 0 A D conversion start flag 0 A D conversion disabled Frequency select bit 0 0 faD 4 is selected 1 fap 2 is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 Set the corresponding port direction register to 0 input mode When
42. H to the L level The result of the erase operation can be known by reading the status register RxDO A716 D016 M16C reception data LAT _TxDO M16C transmit data Figure 1 124 Timing for erasing all unlocked blocks RENESAS 163 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Read Lock Bit Status Command This command reads the lock bit status of the specified block Execute the read lock bit status com mand as explained here following 1 Transfer the 7116 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 The lock bit data of the specified block is output with the 4th byte Write the highest address of the specified block for addresses As to A23 The M30201 flash memory version does not have the lock bit so the read value is always 1 block unlock As to V A16 to _ Rx M16C reception data _TxDO M16C transmit data Figure 1 125 Timing for reading lock bit status Download Command This command downloads a program to the RAM for execution Execute the download command as explained here following 1 Transfer the FA16 command code with the 1st byte 2 Transfer the program size with the 2nd and 3rd bytes 3 Transfer the check sum with the 4th byte The check sum is added
43. O The value if read turns out to be indeterminate Timer Bi overflow flag Note Count source select bit b1 b0 Oo 1 0 Pulse period pulse width measurement mode b3 b2 0 0 Pulse period measurement Interval between measurement pulse s ling edge to falling edge Pulse period measurement Interval between measurement pulse s rising edge to rising edge 1 0 Pulse width measurement Interval between measurement pulse s falling edge to rising edge and between rising edge to falling edge 1 1 Inhibited 01 0 Timer did not overflow 1 Timer has overflowed b7 b6 00 f1 01 fs 10 f32 11 fco32 Note The timer Bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Bi mode register This flag cannot be set to 1 by software Figure 1 53 Timer Bi mode register in pulse period pulse width measurement mode tENESAS 63 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse Transfer Transfer indeterminate value S measured value Reload register counter transfer timing Note 1 Timing at which counter reaches 000016 Count start flag Timer Bi interrupt request bit Cleared to 0 when interrupt request is accepted or cle
44. Pages 2 6 internal interrupt 9 gt 13 Pages 2 6 2 7 to 5 5V f XIN 7MHz with software one wait mask ROM version gt 2 7 to 5 5V f XIN 3 5MHz mask ROM version Page 6 Power consumption 18mA f XIN 7MHz with software one wait Vcc 3V gt 11mA f XIN 3 5MHz Vcc 3V Page 7 M30201M2 XXXSP FP M30201M2T XXXSP FP gt Delete M30201M4T XXXSP M30201F6T XXXSP gt Delete M30201M6 XXXFP M30201M6T XXXFP gt Addition Pages 10 11 Figures 1 7 and 1 8 are partly revised Page 15 Figure 1 11 is partly revised Page 17 Figure 1 14 is partly revised Bit 7 of the processor mode register 1 Wait bit gt Reserved bit Page 18 Seftware wait Page 21 Figure 1 18 is partly revised Note 8 is partly revised Page 22 Figure 1 19 is partly revised n 0716 approx 16 5kHz gt 19 5kHz Page 34 Figure 1 24 is partly revised Note 2 is added Page 50 Figure 1 39 is partly revised Page 78 Figure 1 72 is partly revised UARTIi transmit receive mode register Page 79 Figure 1 73 is partly revised Page 81 Figure 1 74 is partly revised Page 86 Figure 1 79 is partly revised Pages 91 to 97 Figures 1 83 to 1 89 are partly revised Pages 111 to 114 119 to 123 Tables 1 36 to 1 39 and 1 56 to 1 71 are partly revised Page 125 Table 1 74 is partly revised Boot ROM area 4 K bytes gt 3 5 K bytes Page 143 to 169 Standard serial I O mode 2 is added Revision history M30201 Group User s Manual 400 2tENESAS Renesas Technology Co
45. Standard Parameter Max tc TB TBiIN input cycle time counted on one edge tw TBH TBiIN input HIGH pulse width counted on one edge tw TBL TBiiN input LOW pulse width counted on one edge tc TB TBIIN input cycle time counted on both edges tw TBH TBiIN input HIGH pulse width counted on both edges tw TBL TBiiN input LOW pulse width counted on both edges Table 1 65 Timer B input pulse period measurement mode Standard i Max Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Table 1 66 Timer B input pulse width measurement mode Standard i Max Parameter tc TB TBiIN input cycle time tw TBH TBiIN input HIGH pulse width tw TBL TBiIN input LOW pulse width Table 1 67 Timer X input counter input in event counter mode Standard Parameter Min Max TXiINOUT input cycle time TXiinouT input HIGH pulse width TXiiNouT input LOW pulse width Table 1 68 Timer X input gate input in timer mode Standard Parameter Min Max te TX TXiINOUT input cycle time tw TXH TXiINOUT input HIGH pulse width tw TXL TXiiNouT input LOW pulse width Table 1 69 Timer X input external trigger input in one shot timer mode We ae Symbol Parameter Unit te TX TXinouT input cycle time tw TXH TXiiNouT input HIGH pulse width tw TXL TXiinouT in
46. io beeen eee e ener e eee e eee Reserved bit Must always be set to 0 o e Reserved bit Must always be set to 0 Nothing is assigned In an attempt to write these bits write 0 The value if read turns out to be indeterminate Figure 1 97 Flash memory control register Flash command register b7 b6 b5 b4 b3 b2 bi b0 Address When reset 03B616 0016 Symbol FCMD Function Writing of software command lt Software command name gt Read command Program command Program verify command Erase command Erase verify command Reset command lt Command code gt 0016 4016 C016 2016 2016 A016 FF16 FFe Figure 1 98 Flash command register tENESAS Renesas Technology Corp 127 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Flash memory version Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I O mode beforehand If the control program is written into the boot ROM area the standard serial I O mode becomes unusable See Figure 1 96 for details about the boot ROM area Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSs pin low Vss In this case the CPU starts operating using the control program in the user ROM area When the micr
47. lect bit 1 0 One shot timer mode or pulse period Tuop1 Se a mon pulse width measurement mode MRO Measurement mode 3 2 select bit 0 0 Pulse period measurement Interval between measurement pulse s falling edge to falling edge 0 1 Pulse period measurement Interval between measurement pulse s rising edge to rising edge 1 0 Pulse width measurement Interval between measurement pulse s falling edge to rising edge and between rising edge to falling edge 1 1 Inhibited Timer Xi overflow 0 Timer did not overflow 2 flag Note 1 Timer has overflowed 1 Must always be 1 in pulse period pulse width measurement mode Count source select bit Note The timer Xi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Xi mode register This flag cannot be set to 1 by software Figure 1 63 Timer Xi mode register in pulse period pulse width measurement mode RENESAS 71 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse Transfer Transfer indeterminate value Pa measured value Reload register counter transfer timing Timing at which counter reaches 000016 Count start flag Timer Xi interrupt request bit Cleared to 0 when
48. mee to o Se bi 2 o o e oo eo ooo es CM15 XIN XOUT drive capacity r LOW select bit Note 2 HIGH Main clock division No division mode select bit 1 Note 3 Division by 2 mode Division by 4 mode Division by 16 mode Note 1 Set bit 0 of the protect register address 000A16 to 1 before writing to this register Note 2 This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 3 Can be selected when bit 6 of the system clock control register 0 address 000616 is O If 1 division mode is fixed at 8 Note 4 If this bit is set to 1 XouT turns H and the built in feedback resistor is cut off XCIN and XcouT turn high impedance state Figure 1 18 Clock control registers 0 and 1 RENESAS 21 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Output The clock output function select bit allows you to choose the clock from fs fc or a divide by n clock that is output from the P54 CKOUT pin The clock divide counter is an 8 bit counter whose count source is f32 and its divide ratio can be set in the range of 0016 to FF16 Figure 1 19 shows a block diagram of clock output Clock source selection P54____4 fg o P54 CKOUT
49. peripheral function clock stop bit is O When the WAIT peripheral function clock stop bit is 1 the status immedi ately prior to entering wait mode is maintained stENESAS Renesas Technology Corp 23 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Status Transition of BCLK Status Transition of BCLK Power dissipation can be reduced and low voltage operation achieved by changing the count source for BCLK Table 1 5 shows the operating modes corresponding to the settings of system clock control regis ters 0 and 1 When reset the device starts in division by 8 mode The main clock division select bit O bit 6 at address 000616 changes to 1 when shifting from high speed medium speed to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained The following shows the operational modes of BCLK 1 Division by 2 mode The main clock is divided by 2 to obtain the BCLK 2 Division by 4 mode The main clock is divided by 4 to obtain the BCLK 3 Division by 8 mode The main clock is divided by 8 to obtain the BCLK When reset the device starts operating from this mode Before the user can go from this mode to no division mode division by 2 mode or division by 4 mode the main clock must be oscillating stably When going to low speed or lower power consumption mode make sure the sub clock i
50. Figure 2 2 13 Set up procedure of event counter mode reload type selected stENESAS 187 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 6 Operation of Timer A event counter mode free run type selected In event counter mode choose functions from those listed in Table 2 2 5 Operations of the circled items are described below Figure 2 2 14 shows the operation timing and Figure 2 2 15 shows the set up procedure Table 2 2 5 Choosed functions Count source Input signal to TAOIN Pulse output function No pulses output counting falling edges Pulses output Input signal to TAOIN Count operation type Reload type counting rising edges Free run type Timer overflow Factor for switching Content of up down flag between up and TB1 TX0 TX2 overflow down P Input signal to TAQouT Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 3 If switching from an up count to a down count or vice versa while a count is in progress the switch takes effect from the next effective edge of the count source 4 Even if an overflow occurs the content of the reload register is not reloaded but th
51. High impedance High impedance Figure 3 4 1 Operation timing of buzzer output 350 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Initialization of port P4 direction register Protect register Address 000A16 PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 0 Input mode Initialization of timer XO b7 b0 b15 b8 b7 bo A Timer XO register Timer XO mode register 1 F ojojojojo 0jo0 TXOMR Address 039716 0016 916 TXO Address 038916 038816 b7 bo Selection of timer mode Pulse output function select bit 1 Pulse is output Gate function select bit b4 b3 0 0 Gate function not available 0 Must always be 0 in timer mode Count source select bit b7 b6 b7 be Count Count source period 00 gt source Xin 10MHz_ f Xcin 32 768kHz 100ns 800ns 3 2us 976 56us Count start flag Address 038016 TABSR Timer X0 count start flag 1 Starts counting Buzzer ON Protect register Address 000A16 PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 1 Output mode Buzzer OFF b7 P
52. INTO interrupt control register INTOIC 005E16 INT1 interrupt control register INT11C Table 4 2 1 Memory map of the interrupt control registers 2tENESAS Renesas Technology Corp 369 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Interrupt control register Note 2 Symbol Address When reset KUPIC 004Di16 XXXXX0002 ADIC 004E16 XXXXX0002 SITIC i 005116 005316 XXXXX0002 SIRIC i 005216 005416 XXXXX0002 b7 b6 b5 b4 b3 b2 bi bO TAiIC 005516 XXXXX0002 TXiIC 2 005616 to 005816 XXXXX0002 TBilC 005A16 005B16 XXXXX0002 T ou b a ss t Tid ooo o Bisymbo Binare AW Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested 1 Interrupt requested Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Note 1 This bit can only be accessed for reset 0 but cannot be accessed for set 1 Note 2 To rewrite the interrupt control register do so at a point that dose not generate the interrupt request for that register For details see the precautions for interrupts b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset INTIIC i 0 1 005D16 005E16 XX00X0002 Bisymboi Bitname Interrupt priority level select bit Level 0 interrup
53. Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset Joho Hel ADCONO 03D616 00000XXxX2 Bit symbol Bit name Function Analog input pin select bit Invalid in single sweep mode b4 b3 MDo ane era mode 10 Single sweep mode MD1 Set this bit to 0 ADST A D conversion start flag A D conversion disabled A D conversion started Frequency select bit 0 fad 4 is selected Gee faD 2 is selected Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D control register 1 Note 1 b7 be b5 b4 b3 b2 bi b0 Symbol Address When reset ADCON1 03D716 0016 Bit symbol Bit name Function A D sweep pin select bit When single sweep and repeat sweep SCANO mode 0 are selected bi b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins SCAN1 1 0 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins Note 2 3 MD2 A D operation mode Set this bit to 0 in this mode select bit 1 BITS 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode CKS1 Frequency select bit 1 0 faD 2 or faD 4 is selected 1 fAD is selected VCUT Vref connect bit 1 Vref connected Set this bit to 0 ADGSELO A D input group select bit 0 Port P6 group is selected 1 Port P5 group is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to AN54 can be used in the same
54. Note 1 C210 47 pF C gt 20 47 uF C gt 3100 pF for reference Note 2 Use thick and shortest possible wiring to connect capacitors Figure 2 7 16 Use of capacitors to reduce noice 3 Set the direction register of the following ports to input the port corresponding to a pin to be used as an analog input pin and external trigger input pin 4 If using the A D converter with Vcc 2 7V to 4 0 V Use without fAD no frequency division for PAD Select without the Sample amp Hold feature Select 8 bit mode 5 Rewrite to analog input pin after changing A D operation mode The two cannot be set at the same time 6 When using the one shot or single sweep mode Confirm that A D conversion is complete before reading the A D register Note When A D conversion interrupt request bit is set it shows that A D conversion is completed 7 When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 8 Method of A D Conversion 10 bit mode 1 The A D converter compares the reference voltage Vref generated internally based on the contents of the successive comparison register with the analog input voltage VIN input from the analog input pin Each bit of the comparison result is stored in the successive comparison
55. Operation of Functional Blocks The M30201 accommodates certain units in a single chip These units include ROM and RAM to store instructions and data and the central processing unit CPU to execute arithmetic logic operations Also included are peripheral units such as timers serial I O A D converter and I O ports The following explains each unit Memory Figure 1 6 is a memory map of the M30201 The address space extends the 1M bytes from address 0000016 to FFFFF16 From FFFFF16 down is ROM For example in the M30201M4 XXXSP there is 32K bytes of internal ROM from F800016 to FFFFF16 The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to FFFFF16 The starting address of the interrupt routine is stored here The address of the vector table for timer interrupts etc can be set as desired using the internal register INTB See the section on interrupts for details From 0040016 up is RAM For example in the M30201M4 XXXSP there is 1K byte of internal RAM from 0040016 to 007FF16 In addition to storing data the RAM also stores the stack used when calling subrou tines and when interrupts are generated The SFR area is mapped to 0000016 to OO3FF16 This area accommodates the control registers for periph eral devices such as I O ports A D converter serial I O and timers etc Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes The special page vector table is mapped to FFE0
56. Selecting PWM mode and function b7 1 011 po Timer AO mode register Address 039616 l TaomA Selection of PWM mode 1 Must always be 1 in PWM mode External trigger select bit 0 Falling edge of TAOIN pin s input signal Note 1 Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 1 Functions as an 8 bit pulse width modulator Count source select bit b7 b6 i source f X n 10MHz_ f Xcin 32 768kHz 00 f1 1 01 fs be 10 f32 800ns 11 fc32 3 2us 976 56us Count Count source period Note 1 Set the corresponding port direction register which outputs the pulse to 1 output mode Clearing timer AO interrupt request bit Refer to Precaution for Timer A pulse width modulation mode b7 bo KXKXoL TL Timer AO interrupt control register Address 005516 TAOIC C Interrupt request bit Setting trigger select register b7 bo Trigger select register Address 038316 eae TRGSR Timer AO event trigger select bit b1 bO 0 0 Input on TAOIN is selected Note 2 Note 2 Set the corresponding port direction register to 0 input mode Sa a Setting PWM pulse s period and H level width a Br w Timer AO register Address 038716 038616 TAO _ Can be set to 0016 to FE16 Can be set to 0016 to FE16
57. TB1 TX0 TX2 overflow Writing 1 to the one shot start flag Operation 1 If the TAOIN pin input level changes from L to H with the count start flag set to 1 the counter performs a down count on the count source At this time the TAOOUT pin output level goes to H level 2 If the value of the counter becomes 000016 the TAOOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer AO interrupt request bit goes to 1 3 If a trigger occurs while a count is in progress the counter reloads the value of the reload register again and continues counting The reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to O causes the counter to stop and to reload the content of the reload register Also the TAOOUT pin outputs an L level At this time the timer AO interrupt request bit goes to 1 rel i n reload register content 2 Stop count 1 Start count 3 Start count Start count 4 Stop count gt Reload Reload nany Counter content hex Set to 1 by software Cleared to 0 by software Count start flag Trigger during count N 0 E l Al n la 1f X net y i One shot pulse output H i j from TAOouT pin p gt Timer AO interrupt a ba request bit g
58. This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCcIN by 32 b7 b0 Clock prescaler reset flag Address 0381 16 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Se overflow hie Timer Bi ber register i 0 1 Address 039B16 to 039D16 TTX E TBIMR i 0 1 Timer Bi overflow flag 0 Timer did not overflow Figure 2 3 9 Set up procedure of pulse period measurement mode RENESAS 215 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 5 Operation of Timer B pulse width measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 3 4 Op erations of the circled items are described below Figure 2 3 10 shows the operation timing and Figure 2 3 11 shows the set up procedure Table 2 3 4 Choosed functions Count source Internal count source f1 fs f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode i Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width meas
59. WAIT instruction CM06 0 CM17 CM16 11 CM06 1 CM06 0 CM17 CM16 10 0 d o CM06 0 O CMOi Biti ataddress 000616 CM17 CM16 01 CM1i Bit i at address 000716 CM06 0 WDCi Bit i at address 000F16 CM17 CM16 00 Details of divider Figure 1 17 Clock generating circuit RENESAS 19 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit 1 Main clock The main clock is generated by the main clock oscillation circuit After a reset the clock is divided by 8 to BCLK The clock can be stopped using the main clock stop bit bit 5 at address 000616 Stopping the clock after switching the operating clock source of CPU to the sub clock reduces the power dissipation After the oscillation of the main clock oscillation circuit has stabilized the drive capacity of the main clock oscillation circuit can be reduced using the XIN XOUT drive capacity select bit bit 5 at address 000716 Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is re tai
60. When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Table 1 3 Port status during stop mode Pin States Port Retains status before stop mode CLKOUT When fc selected H When fg clock devided Retains status before stop mode counter output selected Wait Mode When a WAIT instruction is executed BCLK stops and the microcomputer enters the wait mode In this mode oscillation continues but BCLK and watchdog timer stop Writing 1 to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions allowing power dissipation to be reduced However peripheral function clock fc32 does not stop so that the peripherals using fc32 do not contribute to the power saving When the MCU running in low speed or low power dissipation mode do not enter WAIT mode with this bit set to 1 Table 1 4 shows the status of the ports in wait mode Wait mode is cancelled by a hardware reset or interrupt If an interrupt is used to cancel wait mode the microcomputer restarts from the interrupt routine using as BCLK the clock that had been selected when the WAIT instruction was executed Table 1 4 Port status during wait mode Pin States Port Retains status before wait mode CLKOUT When fc selected Does not stop When fg clock devided Does not stop when the WAIT counter output selected
61. are indeterminate Figure 1 93 Direction register RENESAS 103 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Port Pi register 67 b BE ba b3 b2 BA bo Symbol Address When reset Pi i 0 to 7 03E016 03E116 03E516 03E816 Indeterminate ITITI 03E916 03EC16 03ED16 Indeterminate Port Pio register ar a Data is input and output to and from Port Pit register each pin by reading and writing to Port Piz register and from each corresponding bit i i 0 L level data Port Fis register 1 H level data Port Pi4 register Port Pis register PaO to except 2 Pi6 Port Pie register Port Pi7 register Note Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 This bit can either be set nor reset When read its content is indeterminate Figure 1 94 Port register 104 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up control register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PURO 03FC16 0016 Bit symbol RW PUOO P00 to POs pull up The corresponding port is pulled PUO1 P04 to P07 pull up high with a pull up resistor PU02 P10 to P13 pull up a RI PUO3 P14 to P17 pull up PUO6 P30 to P33 pull up PUO07 P34 to P35 pull up Pull up control register 1 b7 b6 b5 b4 b3 b2
62. interrupt set the software reset bit to 1 to reset software 5 Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected Table 2 8 1 The watchdog timer cycle Period Approx 52 4ms Note 10MHz Approx 419 2ms Note Approx 104 9ms Note Approx 838 8ms Note Approx 209 7ms Note Approx 1 68s Note Approx 838 8ms Note Approx 6 71s Note 0 Approx 419 2ms Note 1 Approx 3 35s Note 5MHz 2 5MHz 0 625MHz 1 Invalid Invalid 1 25MHz Invalid Invalid Invalid 32kHz Invalid Approx 2s Note Note An error due to the prescaler occurs 310 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer 6 Registers related to the watchdog timer Figure 2 8 1 shows the memory map of watchdog timer related registers and Figure 2 8 2 shows watchdog timer related registers 000E16 Watchdog timer start register WDTS 000F16 Watchdog timer control register WDC Figure 2 8 1 Memory map of watchdog timer related registers Watchdog timer control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset lojo WDC OO0F 16 000XXXXX2 High order bit of watchdog timer Reserved bit Must always be set to 0 K i Reserved bit Must always be set to 0 o 0 WDC
63. synchronous type ART 7 bi ee PAR Wee g bas UART 7 bits UARTI receive register disabled Lo PAR Co o 5 PAR i enabled VARIE biS Clock synchronous type UART 8 bits UART 9 bits j i i H H UARTI receive D7 De Ds D4 Ds D2 D1 Do buffer register MSB LSB conversion circuit Data bus high order bits Data bus low order bits MSB LSB conversion circuit LZ D7 De Ds Da Ds De D1 Do UARTI transmit buffer register UART 8 bits UART 9 bits i Clock UART 9 bits synchronous PAR type enabled T 2 HH HH HH 0 Bie UART 7 bits UART 7 bits UARTI transmit register t UART 8 bits ge Clock SP Stop bit synchronous PAR Parity bit type Note UART1 cannot be used in clock synchronous serial I O Figure 1 70 Block diagram of transmit receive unit 76 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Serial I O UARTIi transmit buffer register Note b15 b8 Symbol Address When reset b7 bO b7 UOTB 03A316 03A216 Indeterminate U1TB O3ABi6 O3AAt16 Indeterminate Transmit data Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Note Use MOV instruction to write to this register UARTI receive buffer register
64. the TXiINOUT pin outputs an H level 2 The TXIINOUT pin output level changes from H to L when a set time period elapses At this time the timer Xi interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TXiINOUT outputs an L level Note e PWM pulse cycle is 218 1 fi whereas H level duration is n fi However when 000016 is set for the timer AO register the PWM output is L level for the entire period and an interrupt request is generated for every PWM output cycle Also when FFFF 16 is set for the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f32 fc32 n Timer value Conditions Reload register 000316 when timer overflow is selected in trigger 1 1 X 2 1 comme LULL ainn Cleared to O when interrupt request is accepted or cleared by software Timer Interrupt H i request bit re ae becoming trigger Set to 1 by software Cleared to 0 by software Count start flag 1 Start count 2 Output level H to L 3 One period is complete lt 1 fiX n i 4 Stop count PWM pulse
65. the timer AO interrupt request bit goes to 1 3 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 Note e The up count or down count conditions are as follows If a rising edge is present at the TAOIN pin when the input signal level to the TAOQOUT pin is H an up count is performed If a falling edge is present at the TAOIN pin when the input signal level to the TAOOUT pin is H a down count is performed 1 Start count Input pulse FFFFi6 000016 gt x 0 f E o 2 Q 0 L o 2 5 Q O Set to 1 by software Count start flag Timer AO interrupt T request bit Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 16 Operation timing of 2 phase pulse signal process in event counter mode normal mode selected 190 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A z Selecting event counter mode and functions Selection of event counter mode 0 Must always be 0 when using two ph
66. 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Register Page Processor mode register 0 PMO Processor mode register 1 PM1 17 System clock control register 0 CM0 System clock control register 1 CM1 21 Address match interrupt enable register AIER 44 Protect register PRCR 27 Watchdog timer start register WDTS Watchdog timer control register WDC 47 Address match interrupt register 0 RMADO 44 Address match interrupt register 1 RMAD1 44 Address Register Page 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004Bi16 004C16 004D16 _ Key input interrupt control register KUPIC 004E16 A D conversion interrupt control register ADIC 004F16 005016 005116 UARTO transmit interrupt control register SOTIC 005216 UARTO receive interrupt control register SORIC 005316 UART1 transmit interrupt control register S1TIC 005416 UART1 receive interrupt control register S1RIC 34 005516 _ limer AO interrupt control register TAOIC 005616 Timer XO interrupt control register TXOIC 005716 _ Timer X1 i
67. 038716 wy AZ 039616 Timer AO mode register TAOMR Figure 2 2 1 Memory map of timer A related registers Timer AO mode register Symbol Address When reset b7 b6 b5 b4 b3 b2 bi b0 TAOMR 039616 0016 Bit symbol aw Operation mode select bit t Timer mode Event counter mode One shot timer mode Pulse width modulation PWM mode TCKO Count source select bit Function varies with each operation mode ee ie Function varies with each operation mode 0 9 o o o o elle o 9 Figure 2 2 2 Timer A related registers 1 176 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer AO register Note 1 b15 b8 ie AS De bu Address When reset Loo T O dies e Timer mode 000016 to FFFF16 Counts an internal count source e Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow One shot timer mode 000016 to FFFF16 Counts a one shot width Note 2 XO e Pulse width modulation mode 16 bit PWM 000016 to FFFE16 y fo Functions as a 16 bit pulse Tan i Note 2 e Pulse width modulation mode 8 bit PWM 0016 to FF16 Note 2 Timer low order address functions as an 8 bit Both high order prescaler and high order address functions as an 8 bit and low order pulse width modulator addresses Note 1 Read and write data in 16 bit units Note 2 Use MOV instr
68. 038916 038916 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 E Can be set to 000016 to FFFF16 d P A Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 LADD CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O i Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 5 Set up procedure of timer mode tENESAS 225 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 3 Operation of Timer X timer mode gate function selected In timer mode choose functions from those listed in Table 2 4 2 Operations of the circled items are described below Figure 2 4 6 shows the operation timing and Figure 2 4 7 shows the set up procedure Table 2 4 2 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINoOUT pin is at L level
69. 03CF16 03CE16 A D register 7 16 f Data bus high order Data bus low order YVVVVVYV Port P6 group P60 ANo CH2 CH1 CH0 000 o P61 AN1 O CH2 CH1 CH0 001_5 o P62 AN2 CH2 CH1 CH0 010_5 o ere P63 AN3 O CH2 CH1 CH0 011_5 o gt P64 AN4 O CH2 CH1 CH0 100_5 o O P6s ANs O CH2 CH1 CH0 101_ gt P66 ANe O CH2 CH1 CH0 110_5 o P67 AN7 O CH2 CH1 CH0 111_5 o Da HRH P50 AN50 O CH2 CH1 CH0 000_5 o P51 AN51 CH2 CH1 CH0 001 0 O ADGSELO 1 P52 ANs2 O CH2 CH1 CH0 010 _G 5 zo P53 ANs3 O CH2 CH1 CH0 011_5 o P54 AN54 CH2 CH1 CH0 100_5 o Figure 1 82 Block diagram of A D converter 90 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TT fol Abcone 03D616 00000XXX2 Bit symbol Bit name Function o707 0 09 ANo is selected AN1 is selected AN2 is selected AN8 is selected AN4 is selected AN5 is selected AN6 is selected AN7 is selected Note 2 3 Analog input pin select bit o A D operation mode select bit 0 One shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 Note 2 00g 000098 0
70. 05c 00 4000 Set this bit to 0 A D conversion start flag 0 A D conversion disabled ADST 1 A D conversion started CKSO Frequency select bit 0 0 fap 4 is selected 1 faD 2 is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 When changing A D operation mode set analog input pin again Note 3 ANso to ANs4 can be used in the same way as for ANo to AN4 A D control register 1 Note 1 bz b6 b5 b4 bo b2 bi b0 Symbol Address When reset ADCON1 03D716 0016 Bit symbol A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins 1 0 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins When repeat sweep mode 1 is selected b1 bO 00 ANo 1 pin 0 1 ANo AN1 2 pins 1 0 ANo to AN2 3 pins 1 1 ANo to AN3 4 pins Note 2 3 A D operation mode 0 Any mode other than repeat sweep select bit 1 mode 1 Repeat sweep mode 1 Poean bit mode select bit H 8 bit mode oms 10 bit mode CA select bit 1 0 faD 2 or faD 4 is selected CKS1 F 1 fAD is selected Vref connect bit 0 Vref not connected VCUT 1 Vref connected joo Set this bit to 0 Di a 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected joo Note 1 If the A D control register is rewritten during A D conversion the conversion res
71. 1 to A D conversion start flag Stop condition Writing 0 to A D conversion start flag Interrupt request generation timing None generated Input pin One of ANo to AN7 as selected Note Reading of result of A D converter Read A D register corresponding to selected pin at any time Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset ol 4 ADCONO 03D616 00000XXX2 Bit symbol Bit name Function CHO Analog input pin select bit 0 0 0 ANo is selected AN1 is selected AN2 is selected CH1 AN3 is selected AN4 is selected AN5 is selected CH2 AN6 is selected AN7 is selected MD1 Set this bit to 0 A D conversion start flag 0 A D conversion disabled 1 A D conversion started Frequency select bit 0 0 faD 4 is selected 1 faD 2 is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 When changing A D operation mode set analog input pin again Note 3 AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 1 Note b7 b6 b5 b4 b3 b2 bi bo Symbol Address When reset ADCON1 03D716 0016 SCANT ool mp2 A operation mode Set this bit to 0 in this mode select bit 1 BITS 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode Frequency select bit 1 0 faD 2 or fAD
72. 1 Set timer XO in timer mode and set timer X1 in one shot timer mode with pulse output function 2 Set 1 ms the PWM period to timer X0 Set 500 us the width of PWM H pulse to timer X1 Both timer XO and timer X1 use f1 for the count source 3 Connect a 10 MHz oscillator to XIN Operation 1 Setting the count start flag to 1 causes the counter of timer XO to begin counting The counter of timer XO performs a down count on count source f1 2 If the counter of timer XO underflows the counter reloads the content of the reload register and continues counting At this time the timer XO interrupt request bit gose to 1 3 An underflow in timer XO triggers the counter of timer X1 and causes it to begin counting When the counter of timer X1 begins counting the output level of the TX1INOUT pin gose to H 4 As soon as the count of the counter of timer X1 becomes 000016 the output level of TX1INOUT pin gose to L and the counter reloads the content of the reload register and stops counting At the same time the timer X1 interrupt request bit gose to 1 342 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications reload register content 1 Timer XO start count 2 Timer XO underflow Timer X0 counter content hex n reload register content 3 Timer X1 start count 4 Timer X1 sto
73. 1 118 Example circuit application for the standard serial I O mode 1 RENESAS 157 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Overview of standard serial I O mode 2 clock asynchronized In standard serial I O mode 2 software commands addresses and data are input and output between the MCU and peripheral units serial programer etc using 2 wire clock asynchronized serial I O UARTO Standard serial I O mode 2 is engaged by releasing the reset with the P53 BUSY pin L level The TxDo pin is for CMOS output Data transfer is in 8 bit units with LSB first 1 stop bit and parity OFF After the reset is released connections can be established at 9 600 bps when initial communications Fig ure 1 119 are made with a peripheral unit However this requires a main clock with a minimum 2 MHz input oscillation frequency Baud rate can also be changed from 9 600 bps to 19 200 38 400 or 57 600 bps by executing software commands However communication errors may occur because of the oscillation fre quency of the main clock If errors occur change the main clock s oscillation frequency and the baud rate After executing commands from a peripheral unit that requires time to erase and write data as with erase and program commands allow a sufficient time interval or execute the read status command and check how processing e
74. 1 Overview The address match interrupt is used for correcting a ROM or for a simplified debugging purpose monitor The following is an overview of the address match interrupt 1 Enabling disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt It is affected neither by the processor interrupt priority level IPL nor the interrupt enable flag I flag 2 Timing of the address match interrupt An interrupt occurs immediately before executing the instruction in the address indicated by the ad dress match interrupt register Set the first address of the instruction in the address match interrupt register Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt The first instruction of an interrupt routine does not generate an address match interrupt either 3 Returning from an address match interrupt The return address put in the stack when an address match interrupt occurs depends on the instruc tion not yet executed the instruction the address match interrupt register indicates The return ad dress is not put in the stack For this reason to return from an address match interrupt either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction Figure 2
75. 2 SP 4 vec vec 2 y formako J Indeterminate T elle ER a Data bus i TEA Indeterminate contents contents contents contents RD WR Stop mode Oscillation start up Interrupt sequence approximately 20 cycle 16u sec Single chip mode f Xin 10MHz Figure 2 11 2 Sequence of returning from stop mode 6 Registers related to power control Figure 2 11 3 shows the memory map of power control related registers and Figure 2 11 4 shows power control related registers stENESAS 325 Renesas Technology Corp Power Control 000616 000716 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER System clock control register 0 CMO System clock control register 1 CM1 Figure 2 11 3 Memory map of power control related registers System clock control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol CMO Bit symbol Address 000616 Bit name When reset 4816 Function CM00 Clock output function select bit WAIT peripheral function clock stop bit b1 b0 0 0 I O port P54 0 1 fc output 1 0 f8 output 1 1 Clock divide counter output 0 Do not stop peripheral function clock in wait mode 1 Stop peripheral function clock in wait mode Note 8 XCIN XCOUT drive capacity select bit Note 2 LOW HIGH Port Xc select bit I O port 0 1 0 1 XCIN XCOUT generation Main clock XIN XOUT stop bit Note
76. 2 Valid only when the TAOIN pin is selected by the event trigger select bit addresses 038316 If timer overflow is selected this bit can be 1 or 0 Note 3 Set the corresponding port direction register to O input mode Figure 1 44 Timer AO mode register in one shot timer mode 56 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 4 Pulse width modulation PWM mode In this mode the timer outputs pulses of a given width in succession See Table 1 16 In this mode the counter functions as either a 16 bit pulse width modulator or an 8 bit pulse width modulator Figure 1 45 shows the timer AO mode register in pulse width modulation mode Figure 1 46 shows the example of how a 16 bit pulse width modulator operates Figure 1 47 shows the example of how an 8 bit pulse width modulator operates Table 1 16 Timer specifications in pulse width modulation mode Specification Count source f1 f8 f32 fc32 Count operation e The timer counts down operating as an 8 bit or a 16 bit pulse width modulator e The timer reloads a new count at a rising edge of PWM pulse and continues counting e The timer is not affected by a trigger that occurs when counting 16 bit PWM e High level width n fi n Set value e Cycle time 218 1 fi fixed 8 bit PWM e High level width n X m 1 fi n values set to timer AO register s high order address e Cy
77. 2 7 9 Method of A D Conversion 8 bit mode 1 In 8 bit mode 8 higher order bits of the 10 bit successive comparison register becomes A D conversion result Hence if compared to a result obtained by using an 8 bit A D converter the voltage compared is different by 3 VREF 2048 see what are underscored in Table 2 7 9 and differences in stepping points of output codes occur as shown in Figure 2 7 18 Table 2 7 9 The comparison voltage in 8 bit mode compared to 8 bit A D converter Lee 8 bit mode 8 bit A D converter n 0 Comparison voltage 1 to 255 Vref n Optimal conversion characteristics of 8 bit A D converter VREF 5 12 V Output code Result of A D conversion 02 01 00 10 30 Analog input voltage mV Optimal conversion characteristics in 8 bit mode VREF 5 12 V Output code Result of A D conversion 8 bit 10 bit 10bit mode 8bit mode 37 5 Analog input voltage mV Note Differences in stepping points of output code for analog input voltage Figure 2 7 18 The level conversion characteristics of 8 bit mode and 8 bit A D converter stENESAS 303 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Table 2 7 10 Variation of the successive comparison register and Vref while A D conversion is in progress 8 bit mode VREF V a M VREF VREF 2 2048 IV VREF VREF VREF ngs ie te oe
78. 3 4 5 Main clock division select bit 0 Note 7 System clock select bit Note 6 0 On 1 Off 0 CM16 and CM17 valid 1 Division by 8 mode 0 XIN XOUT 1 XCIN XCOUT Set bit 0 of the protect register address 000A16 to 1 before writing to this register Changes to 1 when shifting to stop mode and at a reset No Note No re This bit is used to stop the main clock when placing the device in a low power mode If you want to operate with XIN after exiting from the stop mode set this bit to 0 When operating with a self excited oscillator set the system clock select bit CM07 to 1 before setting this bit to 1 When inputting external clock only clock oscillation buffer is stopped and clock input is acceptable If this bit is set to 1 XouT turns H The built in feedback resistor remains being connected so XIN turns pulled up to XoutT H via the feedback resistor Set port Xc select bit CM04 to 1 and stabilize the sub clock oscillating before setting to this bit from 0 to 1 Do not write to both bits at the same time And also set the main clock stop bit CM05 to 0 and stabilize the main clock oscillating before setting this bit from 1 to 0 This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the
79. 8 bits x1 channel M16C 60 series16 bit CPU core Registers Program counter Watchdog net 15 bits ROH Vector table INTB Stack pointer Multiplier C s C e Note 1 ROM size depends on MCU type Note 2 RAM size depends on MCU type Figure 1 3 Block diagram for the M30201 group tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Performance Outline Table 1 1 is performance outline of M30201 group Table 1 1 Performance outline of M30201 group ltem Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns f XIN 10MHz Memory ROM See figure 4 ROM expansion capacity RAM See figure 4 ROM expansion I O port PO to P7 43 lines Multifunction TAO 16 bits x 1 timer TBO TB1 16 bits x 2 TXO TX1 TX2 16 bits x 3 Serial I O UARTO UART or clock synchronous x 1 UART1 UART x 1 A D converter 10 bits x 8 channels Expandable up to 13 channels Watchdog timer 15 bits x 1 with prescaler Interrupt 13 internal and 3 external sources 4 software sources Clock generating circuit 2 built in clock generation circuits built in feedback resistor and external ceramic or quartz oscillator Supply voltage 4 0 to 5 5V f XIN 10MHz mask ROM version 2 7 to 5 5V f XIN 3 5MHz mask ROM version 4 0 to 5 5V
80. AO interrupt This is an interrupt that timer A generates e Timer BO interrupt and timer B1 interrupt These are interrupts that timer B generates Timer XO interrupt through timer X2 interrupt e INTO interrupt and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin 366 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 4 Interrupts and Interrupt Vector Tables If an interrupt request is accepted a program branches to the interrupt routine set in the interrupt vector table Set the first address of the interrupt routine in each vector table Two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting e Fixed vector tables The fixed vector table is a table in which addresses are fixed The vector tables are located in an area extending from FFFDC16 to FFFFF16 One vector table comprises four bytes Set the first address of interrupt routine in each vector table Table 4 1 1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables Table 4 1 1 Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Vector table addresses Address L to address H FFFDC16 to FFFDF16 Remarks Interrupt o
81. CM10 becomes 0 and clearing stop mode Starting oscillation and supplying BCLK execute the interrupt sequence as follow In the interrupt sequence the processor carries out the following in sequence given a CPU gets the interrupt information the interrupt number and interrupt request level by read ing address 0000016 The interrupt request bit of the interrupt written in address 0000016 will then be set to 0 b Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in the temporary register Note within the CPU c Sets the interrupt enable flag flag the debug flag D flag and the stack pointer assignment flag U flag to O the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed d Saves the content of the temporary register Note within the CPU in the stack area e Saves the content of the program counter PC in the stack area f Sets the interrupt priority level of the accepted instruction in the IPL Note This register cannot be utilized by the user After the interrupt sequence is completed the processor resumes executing instructions from the first address of the interrupt routine Figure 2 11 2 shows the sequence of returning from stop mode Writing 1 to CM10 na all clock stop control bit Operated by divided by 8 mode BCLK Address bus i i 00000 A Indeterminate SP
82. Counts external signal s falling edge 0 Must al ways be 0 in event counter mode 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type 0 Must always be 0 in event counter mode Count start flag Address 038016 TABSR Timer XO count start flag 1 Starts counting b7 b0 TET TT yt I b7 bo Trigger select register Address 038316 R TRGS Timer XO event trigger select bit b3 b2 0 0 Input on TXOINOUT is selected Setting interrupt priority levels in timer XO b7 w Timer XO interrupt control register Address 005616 TXOIC Interrupt control level set a value 1 to 7 Initialization of port P4 direction register SXXEEETL 1 Protect register Address 000A16 PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 0 Input mode Setting interrupt enable flag I flag Figure 3 5 1 Set up procedure of solution for a shortage of external interrupt pins stENESAS Renesas Technology Corp 353 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications 3 6 Controlling Power Using Stop Mode Overview The following are steps for controlling power using stop mode Figure 3 6 1 shows the operation timing Figure 3 6 2 show
83. Examples of sub clock Note Insert a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by the maker of the oscillator When the oscillation drive capacity is set to low check that oscillation is stable Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added external to the chip insert a feedback resistor between XIN and XouT following the instruction Insert a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by the maker of the oscillator When the oscillation drive capacity is set to low check that oscillation is stable Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added external to the chip insert a feedback resistor between XCIN and XCOUT following the instruction 18 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Control Figure 1 17 shows the block diagram of the clock generating circuit XCIN XCOUT Sub clock CM10 1 Write signal RESET Software reset lt JH Interrupt request level judgment output
84. Flash memory control register 1 FCON1 Note1 03F516 03B616 Flash command register FCMD Note 03F616 03B716 03F716 03B816 03F816 03B916 03F916 03BA16 03FA16 03BB16 03FB16 03BC16 03FC16 _Pull up control register 0 PURO 03BD16 03FD16 _Pull up control register 1 PUR1 03BE16 03FE16 _Port P1 drive control register DRR 03BF16 03FF16 Note 1 This register is only exist in flash memory version Note 2 Locations in the SFR area where nothing is allocated are reserved areas Do not access these areas for read or write Figure 1 8 Location of peripheral unit control registers 2 stENESAS 11 Renesas Technology Corp CPU Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Central Processing Unit CPU The CPU has a total of 13 registers shown in Figure 1 9 Seven of these registers RO R1 R2 R3 AO A1 and FB come in two sets therefore these have two register banks R3 Note b15 bo b15 frit b15 fsa b15 b0 b15 bo Data registers Address registers Frame base registers bo b19 bo INTB A L VHN OA DA O A O O A O A S A O S b15 b15 b15 bo i o
85. Interrupt 4 3 3 Saving Registers In the interrupt sequence only the contents of the flag register FLG and that of the program counter PC are saved in the stack area First the processor saves the four higher order bits of the program counter and 4 upper order bits and 8 lower order bits of the FLG register 16 bits in total in the stack area then saves 16 lower order bits of the program counter Figure 4 3 3 shows the state of the stack as it was before the acceptance of the interrupt request and the state the stack after the acceptance of the interrupt request Save other necessary registers at the beginning of the interrupt routine using software Using the PUSHM instruction alone can save all the registers except the stack pointer SP Address Stack area Address Stack area MSB MSB SP Program counter PC a New stack pointer value Program counter PCm Flag register FLG Flag register Program counter PCx SP Content of previous stack Ba A leaa Content of previous stack interrupt occurs Content of previous stack Content of previous stack Stack status before interrupt request Stack status after interrupt request is acknowledged is acknowledged Figure 4 3 3 State of stack before and after acceptance of interrupt request 376 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt The opera
86. Note 1 Transfer data 7 bits long Transfer data 8 bits long Transfer data 9 bits long Serial I O invalid Inhibited Inhibited Inhibited Serial I O invalid Inhibited Inhibited Inhibited 4AOCOCO 44 0 i Internal external clock 0 Internal clock Note 3 0 Internal clock Note 3 select bit Note 2 1 External clock Note 4 1 External clock Note 4 Stop bit length select bit Invalid e one ard ae Odd even parity select bit Invalid Valid when bit 6 1 Odd parity Even parity Parity enable bit Invalid Parity disabled Parity enabled Sleep select bit Must always be 0 Sleep mode deselected Sleep mode selected Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 UART1 can use only internal clock Must set this bit to 1 Note 3 Set the corresponding port direction register to 1 output mode Note 4 Set the corresponding port direction register to O input mode UARTI transmit receive control register 0 b7 b6 b5 b3 b2 bi bO Symbol Address When reset UiCO i 0 1 03A416 03AC16 0816 Function Note Bit name During clock synchronous serial I O mode Function During UART mode b1 b0 BRG count source 00 f1 is selected f1 is selected select bit 0 1 fs is selected fg is selected 1 0 f32 is selected f32 is selected 11 fc is selected fc is selected Set this bit to 0
87. P4 direction 0 Write inhibited register address 03EA16 Note 1 Write enabled 0 Write inhibited 1 Write enabled Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note Writing a value to an address after 1 is written to this bit returns the bit Figure 2 1 1 Protect register 2 1 2 Protect Operation The following explains the protect operation Figure 2 1 2 shows the set up procedure Operation 1 Setting 1 in the write enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write enabled state 2 The contents of system clock control register 0 and that of system clock control register 1 are changed 3 Setting 0 in the write enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write inhibited state 4 To change the contents of processor mode register 0 and that of processor mode register 1 follow the same steps as in dealing with system clock control registers 5 The write enable bit of port P4 direction register goes to 0 when the next write instruction is executed after write enabled state is readied Make changes in input output immediately af ter the instruction that sets 1 in the write enable bit of port P4 direction register avoid causing an interrupt
88. Pulse output function Each time the timer overflows or underflows the TAOOUT pin s polarity is reversed Note This does not apply when the free run function is selected Timer AO mode register When not using two phase pulse signal processing b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset 0j 1 TAOMR 039616 0016 Bit symbol Bit name Function TMODO Operation mode select bit 515 0 1 Event counter mode Pulse output function 0 Pulse is not output select bit TAOOUT pin is a normal port pin Pulse is output Note 1 TAOOUT pin is a pulse output pin Count polarity Counts external signal s falling edge select bit Note 2 Counts external signal s rising edge Up down switching 0 Up down flag s content cause select bit 1 TAiOUT pin s input signal Note 3 0 Must always be 0 in event counter mode Count operation type 0 Reload type select bit 1 Free run type Two phase pulse operation 0 Normal processing operation select bit Note 4 1 Multiply by 4 processing operation Note 1 Set the corresponding port direction register to 1 output mode Note 2 This bit is valid when only counting an external signal Note 3 Set the corresponding port direction register to 0 input mode Note 4 When performing two phase pulse signal processing make sure the two phase pulse signal processing operation select bit address 038416 is set t
89. Start count 2 Underflow Start count again gt Counter content hex Time Set to 1 by software Set to 1 by software Count start flag Cleared to 0 when interrupt request is accepted or cleared by software Cleared to 0 by software Timer AO interrupt 1 request bit o Figure 2 2 6 Operation timing of timer mode 180 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting timer mode and functions Selection of timer mode Pulse output function select bit 0 Pulse is not output TAQOUT pin is a normal port pin Gate function select bit i Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode perv source select bit Count Count source period 00 f1 Source XIN 10MHz f XcIN 32 768kHz 01 fs 100ns 10 f32 800ns 1 1 fc32 3 2us 976 56us Me Setting divide ratio b15 b8 b7 bO b7 bO E E ee ee oo Can be set to 000016 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 een CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the
90. Storing registers 2 Determining the interrupt address N Adress match 07 2 Yes No Address match 0 program Address match 1 Address match 1 program x 3 Rewriting the stack Restoring registers y REIT Handling an error Explanation 1 Storing the contents of the registers holding the main program status to be kept 2 Determining the interrupt address Determining which factor generated the interrupt 3 Rewriting the stack Rewriting the return address Figure 2 9 5 Overview of the address match interrupt handling routine RENESAS 317 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt 2 10 Key Input Interrupt 2 10 1 Overview Key input interrupt occurs when a falling edge is input to POo through P07 The following is an overview of the key input interrupt 1 Enabling disabling the key input interrupt The key input interrupt can be enabled and disabled using the key input interrupt register The key input interrupt is affected by the interrupt priority level IPL and the interrupt enable flag I flag 2 Occurrence timing of the key input interrupt With key input interrupt acceptance enabled pins POo through P07 which are set to input become key input interrupt pins Klo through KI7 A key input interrupt occurs
91. Symbol UiMR i 0 1 Function During clock synchronous serial I O mode Must be fixed to 001 b2 b1 bO 0 0 0 Serial I O invalid 7 Inhibited Inhibited Inhibited Bit name Serial I O mode select bit Note 1 CKDIR Internal external clock 0 Internal clock Note 3 select bit Note 2 1 External clock Note 4 STPS Stop bit length select bit Invalid PRY Odd even parity select bit Invalid PRYE Parity enable bit Invalid Sleep select bit Must always be 0 Function During UART mode N 00O a000 0Op ee Transfer data 8 bits long Transfer data 9 bits long Serial I O invalid Inhibited Inhibited Inhibited 4000440 0 Internal clock Note 3 1 External clock Note 4 0 One stop bit 1 Two stop bits Valid when bit 6 1 0 Odd parity 1 Even parity 0 Parity disabled 1 Parity enabled 0 Sleep mode deselected 1 Sleep mode selected Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 UART1 can use only internal clock Must set this bit to 1 Note 3 Set the corresponding port direction register to 1 output mode Note 4 Set the corresponding port direction register to 0 input mode UARTi transmit receive control register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiCO i 0 1 Bit symbol Bit name Address 03A416 O3AC16 When reset 0816 Function Note During clock
92. TAOIN input TAOOUT input tw UPL TAOOUT input Up down input X During event counter mode TAOIN input When count on falling th Tin UP tsu UP Tin edge is selected TAOIN input I When count on rising edge is selected TBIIN input tw TBL tc TX TXiINOUT input TxDi RxDi INTI input 124 stENESAS Renesas Technology Corp Description Flash memory version Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Outline Performance Table 1 74 shows the outline performance of the M30201 flash memory version Table 1 74 Outline Performance of the M30201 flash memory version Item Performance Power supply voltage 4 0V to 5 5 V f XIN 10MHz Program erase voltage VPP 12V 5 f XIN 10MHz Ta 25 5 C VoC 5V 10 F XIN 10MHz Ta 25 5 C Flash memory operation mode Three modes parallel I O standard serial I O CPU rewrite Erase block User ROM area See Figure 1 96 division Boot ROM area One division 3 5 Kbytes Note Program method In units of byte Erase method Collective erase Program erase control method Program erase control by software command Number of commands 6 commands Program erase count 100 times ROM code protect Parallel I O mode is supported Note The boot ROM area contains a s
93. TBiIN pin Note Note Set the corresponding port direction register to O input mode Setting divide ratio b8 Timer BO register Address 039116 039016 TBO Po Timer Bt register Address 039316 039216 TBI _ Can be set to 000016 to FFFF 16 n Setting count start flag b7 0 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Figure 2 3 7 Set up procedure of event counter mode RENESAS 213 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 4 Operation of Timer B pulse period measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 3 3 Op erations of the circled items are described below Figure 2 3 8 shows the operation timing and Figure 2 3 9 shows the set up procedure Table 2 3 3 Choosed functions Count source Internal count source f1 fa f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counte
94. The following are steps for controling power using wait mode Figure 3 7 1 shows the operation timing and Figures 3 7 2 to 3 7 4 show the set up procedure Use the following peripheral functions e Timer mode of timer B e Wait mode A flag named F WIT is used in the set up procedure The purpose of this flag is to decide whether or not to clear wait mode If F_WIT 1 in the main program the wait mode is entered if F_WIT 0 the wait mode is cleared Specifications 1 Connect a 32 768 kHz oscillator to XCIN to serve as the timer count source As interrupts occur every one second which is a count the timer reaches the controller returns from wait mode and count the clock using a program 2 Clear wait mode if a INTO interrupt request occurs Operation 1 Switch the system clock from XIN to XCIN to get low speed mode 2 Stop XIN and enter wait mode In this instance enable the timer BO interrupt and the INTO interrupt 3 When a timer BO interrupt request occurs at 1 second intervals start supplying the BCLK from XCIN At this time count the clock within the routine that handles the timer BO interrupts and enter wait mode again 4 If a INTO interrupt occurs start supplying the BCLK from Xc n Start the XIN oscillation within the INTO interrupt and switch the system clock to XIN 1 Shift to low speed mode 2 Stop XIN 3 Timer BO interrupt 4 INTo interrupt XOUT NWA XCIN Timer BO overflow Ti
95. adic ie vee Babee auction da iaaa i age ae dau daar 284 2 7 2 Operation of A D converter one shot mode eccceceeeeeeeeeeeceeeeeeeaeeseeeeeeeeaaeseeeeeessaaeeseneees 290 2 7 3 Operation of A D Converter in repeat mode ccceeeceeeseeeceeeeeeeeeeeteeeeeeeaeeseeneeesiaeeeteneees 292 2 7 4 Operation of A D Converter in single sweep mode cceeeeeeeeeeeeeeeeeeeeeeseeeeeeseaeeeeeeees 294 2 7 5 Operation of A D Converter in repeat sweep mode 0 ceceeeeeteeceeteeeetteeeeeeeeeteaaeeteeeees 296 2 7 6 Operation of A D Converter in repeat Sweep mode 1 eeceeeeeeeeeeeeeeeeteeteeeeeeteaaeeteeeees 298 2 7 7 Precautions for A D Converter cccccceeecceeceneeeeeeeeeceeaeeeeeneeceaaeeeeeaeeseaeeseeaaeseeeeeseaesteneeess 300 2 7 8 Method of A D Conversion 10 bit mode ccceeeeeeceeeeeeeeeeeeeeeeeeeeaeeseeeeeeseaeeseeeeeesaeeeteneees 301 2 7 9 Method of A D Conversion 8 bit MOE cceceeeececeeeeeeeeeeceeeeeeeaaeeseeeeeeeeaaeseeeeeetiaaeeneneees 303 2 7 10 Absolute Accuracy and Differential Non Linearity Error eee cceeeeeeeeeeeeeeeteeeeeeeenaeeeeeee 305 2 7 11 Internal Equivalent Circuit of Analog INput c ccecceeeeeeeeeceeeeeeeneee secs eeeeaeeseeeeeesaaeeeeeeees 307 2 7 12 Sensor s Output Impedance under A D Conversion cccccceeseeeeeeeeeeeteeeseeeeeeeaeeeeeneees 308 278 WatCh OG TIMET zerori ea 5 acco ecel bad E A Na aden bid ph duce desu adaee sash bauceus fasbaueantusba
96. an 8 bit I O port equivalent to PO P30 to P35 I O port P3 Input output This is a 6 bit I O port equivalent to PO P40 to P45 I O port P4 Input output This is a 6 bit I O port equivalent to PO The P40 pin is shared with timer AO input and serial I O output TxD1 The P41 pin is shared with timer AO output The P42 pin is shared with serial I O input RxD1 The P43 pin is shared with external interrupt INTO and timer XO input output TXOINOUT The P44 pin is shared with external interrupt INT1 and timer X1 input output TX1INOUT The P45 pin is shared with timer X2 input output TX2INOUT P50 to P54 I O port P5 Input output This is a 5 bit I O port equivalent to PO The P50 P51 P52 and P53 pins are shared with serial I O pins TxDo RxDo CLKo and CLKS The P54 pin is shared with clock output CLKOUT Also these pins are shared with analog input pins AN50 through AN54 P60 to P67 I O port P6 Input output This is an 8 bit I O port equivalent to PO These pins are shared with analog input pins ANo through AN7 P70 to P71 I O port P7 Input output This is a 2 bit I O port equivalent to PO These pins are used for input output to and from the oscillator circuit for the clock Connect a crystal oscillator between the XCIN and the XCOUT pins tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Memory
97. an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow i Start count again gt Counter content hex Time Set to 1 by software Set to 1 by software Count start flag f i Cleared to 0 when interrupt request is accepted or cleared by software software i Cleared to 0 by l Timer Xi interrupt request bit Figure 2 4 4 Operation timing of timer mode 224 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting timer mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of timer mode Pulse output function select bit 0 Pulse is not output TXiINOUT pin is a normal port pin Gate function select bit b4 b3 00 01 Gate function not available TXiINOUT pin is a normal port pin 0 Must always be 0 in timer mode ae source select bit Count Count source period 00 f1 Source f Xin 10MHz f Xcin 32 768kKHz 01 fe 100ns 10 f32 800ns 1 1 fc32 3 2us 976 56us Setting divide ratio gP Timer XO register Address
98. and external ceramic or quartz oscillator Applications Home appliances Audio office equipment Automobiles Central Processing Unit CPU sss 12 TIME ci sververiceeeei e E neste 48 PROS U A E E 15 Senak O erranssa eee ena 75 Clock Generating Circuit cence 18 A D Converter 00 2 ceceeeecee cece eeeeeeeeeeeeeeenaeeeeee 89 PNOLCCUOM stick secstcsyeaset Coane ttt ached tiemaeues teed 27 Programmable I O Ports c cee eee 99 MMU RUPOUS a S 28 Electric Characteristics ceeeeeeeeeeeeees 111 Watchdog Timer cccccceeceesseseeseneeeeeeeeeees 46 Flash Memory VersiOn cccccccesccesseeeeeeees 125 2 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Pin Configuration Figures 1 1 to 1 2 show the pin configurations top view PIN CONFIGURATION top view P61 AN1 P60 ANo lt gt L2 P62 AN2 P63 AN3 P64 AN4 P54 CKout ANs4 lt gt 5 P65 AN5 P53 CLKS ANs3 lt gt LS P66 AN6 P52 CLKo AN52 lt gt P67 AN7 P51 RxDo ANs1 gt Lg POo Klo P50 TxDo ANso lt gt L9 P01 Kl1 P02 Kl2 P03 KI3 P04 Kl4 POs KI5 P06 Kle P07 KI7 lt OO O D T D 0p E dSXXX XIN LOCOEW P4s5 TX2iInouT lt gt P44 INT1 TX1INouT lt gt 19 P43 INTo TXOINOUT lt gt po P42 RxDi lt gt P41 TAQout gt 22 P40 TAOIN TxD1 gt 23 Package 52P4B Figure 1 1 Pin configuration for the M302
99. avs Connect oscillator P45 TX2iNouT lt gt P44 INT1 TX1INouT gt P43 INTo TXOINouT lt gt 44 O P42 RxD1 lt p 44 P40 TAOIN TxD1 lt gt 47 P41 TAQOUT lt p gt Figure 1 106 Pin connections for serial I O mode 2 RENESAS 145 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Flash Memory Version Standard serial I O mode The standard serial I O mode inputs and outputs the software commands addresses and data needed to operate read program erase etc the internal flash memory This I O is serial There are actually two standard serial I O modes mode 1 which is clock synchronized and mode 2 which is asynchronized Both modes require a purpose specific peripheral unit The standard serial I O mode is different from the parallel I O mode in that the CPU controls flash memory rewrite uses the CPU s rewrite mode rewrite data input and so forth It is started when the reset is re leased which is done when the P52 SCLK pin is H level the CNVss pin VppH level In the ordinary command mode set CNVss pin to L level This control program is written in the boot ROM area when the product is shipped from Mitsubishi Accord ingly make note of the fact that the standard serial I O mode cannot be used if the boot ROM area is rewritten in the parallel I O mode Figures 1 105 and 1 106 show the pin connec
100. b8 Symbol Address When reset bo DL UORB 03A716 03A616 Indeterminate U1RB O3AF 16 03AE16 Indeterminate Function During clock Function Bit name synchronous serial I O During UART mode mode Receive data Receive data Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Overrun error flag 0 No overrun error 0 No overrun error Note 1 Overrun error found 1 Overrun error found Framing error flag Invalid 0 No framing error Note 1 Framing error found Parity error flag Invalid 0 No parity error Note 1 Parity error found Error sum flag Invalid 0 No error Note 1 Error found Note Bits 15 through 12 are set to 0 when the receive enable bit is set to 0 Bit 15 is set to 0 when bits 14 to 12 all are set to O Bits 14 and 13 are also set to 0 when the lower byte of the UARTi receive buffer register addresses 03A616 and O3AE16 is read out UARTi bit rate generator Note 1 2 b7 bo Address When reset 03A116 Indeterminate 03A916 Indeterminate Values that can be set Riw T Assuming that set value n BRGi divides the 0016 to FFie xO count source by n 1 Note 1 Write a value to this register while transmit receive halts Note 2 Use MOV instruction to write to this register Figure 1 71 Serial l O related registers 1 7CENESAS 77 Renesas Techno
101. bit does not becomes 1 Timer X pulse period pulse width measurement mode 1 If changing the measurement mode select bit is set after a count is started the timer Xi interrupt request bit goes to 1 2 When the first effective edge is input after a count is started an indeterminate value is transferred to the reload register At this time timer Xi interrupt request is not generated A D Converter 1 Write to each bit except bit 6 of A D control register 0 to each bit of A D control register 1 and to bit 0 of A D control register 2 when A D conversion is stopped before a trigger occurs In particular when the Vref connection bit is changed from 0 to 1 start A D conversion after an elapse of 1 us or longer 2 When changing A D operation mode select analog input pin again 3 Using one shot mode or single sweep mode Read the correspondence A D register after confirming A D conversion is finished It is known by A D conversion interrupt request bit 4 Using repeat mode repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock Stop Mode and Wait Mode 1 When returning from stop mode by hardware reset RESET pin must be set to L level until main clock oscillation is stabilized 2 When shifting to WAIT mode or STOP mode the program stops after reading 8 bytes from the WAIT instruction and the instruction that sets all clock stop bits to 1
102. bit of the certain interrupt written in address 0000016 will then be set to 0 Reading address 0000016 by software sets enabled highest priority interrupt source request bit to O Though the interrupt is generated the interrupt routine may not be executed Do not read address 0000016 by software 2 Setting the stack pointer e The value of the stack pointer immediately after reset is initialized to 000016 Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway Be sure to set a value in the stack pointer before accepting an interrupt Concerning the first instruction immediately after reset generating any interrupts is prohibited 3 External interrupt e Either an L level or an H level of at least 250 ns width is necessary for the signal input to pins INTo and INT1 regardless of the CPU operation clock e When the polarity of the INTo and INT1 pins is changed the interrupt request bit is sometimes set to 1 After changing the polarity set the interrupt request bit to 0 Figure 4 7 1 shows the procedure for changing the INT interrupt generate factor Clear the interrupt enable flag to 0 Disable interrupt Set the interrupt priority level to level 0 Disable INTi interrupt Set the polarity select bit Clear the interrupt request bit to O Set the interrupt priority level to level 1 to 7 Enable the accepting of INTI interrupt request Set the interr
103. clock generating circuits Main clock generating circuit Sub clock generating circuit e CPU s operating clock source e Internal peripheral units Use of clock operating clock source e CPU s operating clock source e Timer A B X s count clock source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator XIN XOUT XCIN XCOUT Oscillation stop restart function Available Available Oscillator status immediately after reset Oscillating Stopped Other Example of oscillator circuit Externally derived clock can be input Figure 1 15 shows some examples of the main clock circuit one using an oscillator connected to the circuit and the other one using an externally derived clock for input Figure 1 16 shows some examples of sub clock circuits one using an oscillator connected to the circuit and the other one using an externally derived clock for input Circuit constants in Figures 15 and 16 vary with each oscillator used Use the values recommended by the manufacturer of your oscillator M30201 Built in feedback resistor XIN M30201 Built in feedback resistor XIN XOuUT t Open Externally derived clock Vss Figure 1 15 Examples of main clock M30201 Built in feedback resistor XCIN XCOUT M30201 Built in feedback resistor XCIN XCOUT t Open Externally derived clock TOU E Vss Figure 1 16
104. compares this read data with the data that it previously wrote to the address using the program command If the compared data do not match the user need to execute the program and program verify operations one more time Erase command 2016 2016 The flash memory control circuit executes an erase operation by writing command code 2016 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle The erase operation requires approximately 20 ms Wait for 20 ms or more before the user go to the next processing Before this erase command can be performed all memory locations to be erased must have had data 0016 written to by using the program and program verify commands During erase operation the watchdog timer remains idle with the value 7FFF16 set in it Note 1 The erase operation is not completed immediately by writing an erase command once The user must always execute an erase verify command after each erase command executed And if verification fails the user need to execute the erase command repeatedly until the verification passes See Figure 1 99 for an example of an erase flowchart Erase verify command A016 The erase verify mode is entered by writing the command code A016 to the flash command register in the first bus cycle When the user execute an instruction to read byte data from the address to be verified e g LDE instruction
105. count start flag Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate TBOS Timer BO count start flag TB1S Timer B1 count start flag CDCS Clock devided count start flag 0 Stops counting 1 Starts counting Up down flag Note b7 b6 b5 b4 b3 b2 bi b0 When reset XXX0XXX02 Symbol Address UDF 038416 Timer AO up down flag i Down count Up count ac specification becomes valid when the up down flag content is selected for up down switching cause Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Timer AO two phase 0 two phase pulse signal pulse signal processing processing disabled select bit 1 two phase pulse signal processing enabled When not using the two phase pulse signal processing function set the select bit to 0 Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Note Use MOV instruction to write to this register Figure 1 39 Timer A related registers 2 50 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A One shot start flag Symbol Address When reset b7 b6 b5 b4 b3 b2 bi bO ONSF 038216 XXXX00002 When read the value is 0 Nothing is assigned In an attempt to w
106. cycles for 8 bit resolution No Sample amp Hold function 59 cycles for 10 bit resolution or 49 cycles for 8 bit resolution Table 2 7 1 Conversion time every operation clock Frequency selection bit 1 1 Frequency selection bit 0 Invalid A D converter s operation clock Min conversion 8 bit mode cycles Note 1 10 bit mode 33 X QAD Min conversion 8 bit mode aie atea 10 bit mode Note 1 The number of conversion cycles per one analog input pin Note 2 The conversion time per one analog input pin when fAD f XIN 10 MHz 284 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 4 Functions selection a Sample amp Hold function Sample amp Hold function samples input voltage when A D conversion starts and carries out A D conversion on the voltage sampled When A D conversion starts input voltage is sampled for 3 cycles of the operation clock When the Sample amp Hold function is selected set the operation clock for A D conversion to 1 MHz or higher b 8 bit A D to 10 bit A D switching function Either 8 bit resolution or 10 bit resolution can be selected When 8 bit resolution is selected the 8 higher order bits of the 10 bit A D are subjected to A D conversion The equations for 10 bit resolu tion and 8 bit resolution are given below 10 bit resolution Vref X n 210 Vref X0 5 210 n 1 to 1023
107. data address Duration 20 us Loop counter X X 1 Write program verify command Duration 6 us 0016 Loop counter X X 1 Write 2016 Write 2016 Write C016 Write erase verify command address Duration 6us Write A016 Read expect value FF16 FAIL Last address Next address Next address Last address Vv Vv Write read command N Write read command gt Write 0016 Write read command gt Write read command Write 0016 v y y PASS FAIL PASS FAIL Figure 1 99 Program and erase execution flowchart in the CPU rewrite mode 132 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version Description of Pin Function Flash Memory Parallel I O Mode Pin name Voc Vss Signal name Power supply input 1 0 Function Apply 5 V 10 to the Vcc pin and 0 V to the Vss pin CNVss CNVss Apply 12 V 5 to the CNVss pin RESET Reset input Connect this pin to Vss XIN Clock input XOUT Clock output Connect a ceramic or crystal resonator between the XIN and XOUT pins When entering an externally derived clock enter it from XIN and leave XOUT open AVcc AVSs Analog power supply input Conne
108. eee entre ee ee eaaeee eee eaeeeeeeetaeeeeeeeaaeeeenenea 367 A 2 Mterrupt GOMtUOl 22 assets tyscesbeves cant ate ceacttaansaeanasieuadaeasapetecaeueds a a a ASE 369 4 21 Interrupt Enable Flag s c cciiegceecevbeareetcevbirceatend Eeee EEE E EEE EEEE ERE E tuyeurtugeevbieandaced yal 371 4 2 2 Interrupt Request BIE ori ia a E RE AEA E ORARE 371 4 2 3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL 22 372 4 2 4 Rewrite the interrupt Control register ee ee eeeeeeeeeeeee cette eeeeeeeeeeeeeeeeeeeeeeeeeeseeeeaeeeeeeeeaaeees 373 4 3 NSMUPESSQUENCE A E EEEE teste leees catback Se iecdbeeset A 374 4 3 1 Interrupt RESPONSE TIME cece ikinni EA AA AEREE ERNES EAO AEE E A TEAR SE 374 4 3 2 Variation of IPL when Interrupt Request is Accepted ssssssssesresessrrssssirnsssrirnnssrinnnnsrnenn 375 4 3 3 Saving Registers ccceeeeceeeeeeceeeeeeeeaeeeeeeeeeceaaeeseaeeeceaaeeeeaaeesaaeeesaaeeseaeeesaaaeseeeeeessaeeseneees 376 4 4 Returning from an Interrupt Routine oo cece cece tence eect eeaae eee eeeaaaeeeeeeeaaeeeeeeeeaaeeeeeeeaaaeeeeeeeaas 378 42D INtSrrUpt PTO sees saciasres E a seed acting hua ceaeeeaanacea dated dicate GabLdge a ata ne ea Ma 378 4 O Multiple Interrupts reicinn teasa deceived cedeethds beet ett acct ecgenaida te dati shendee RE aaa eda E 380 4 7 Precautions for IMterrupts sessar reee E E A EEA RAE EEEN EEE EAA FEEST ORAA EEE ERE 382 Chapter 5 Standard Characterist
109. eee tain vs eases ae ee A te aes eld eae 172 PE OVERVIOW coz A cit ceed ovat aphaedevees tanh aitbiae abefads tt Gee tttes ath iene A ES 172 2 1 2 Protect Operatiivinen a canes Gad a aas 172 2 1 3 Precaution for Protect ona A edt neal eve ee eee 173 Q2TIMeR As E denen ates aacialiiiis cade Aa nae ate aha eee ae 174 22 OVEMVIOW da i dite avecth tne tease hott aeducevsith etiet Fy tase a ea a A tele 174 2 2 2 Operation of Timer A timer mode eeeeeeeeeeeeeeceeeeeee eee eaeeeeeeeeceaaeeeeeeeeseaaeeeeeeeeseeaeeeeeaeeee 180 2 2 3 Operation of Timer A timer mode gate function Selected cceceeeeeeeeeceeeeeeeeteeeeeeeeees 182 2 2 4 Operation of Timer A timer mode pulse output function selected ceeceeeeeeeeneeees 184 2 2 5 Operation of Timer A event counter mode reload type selected cceceeeeeteeeeereees 186 2 2 6 Operation of Timer A event counter mode free run type Selected ceeceeeeeeeeeneeeees 188 2 2 7 Operation of timer A 2 phase pulse signal process in event counter mod normal mode se Eie eE E EE E gies trees ayee tener E E tad hts ea tet tes stees Ses 190 2 2 8 Operation of timer A 2 phase pulse signal process in event counter mode multiply by 4 mode SClOCISG SE E laine EE E age sha tea des EE E E E E E 192 2 2 9 Operation of Timer A one shot timer mode 0 1 cc eeeeeeeeeeeeeeeeeeeeeee sees eeseaaeeteeeeeesaeeeeeeeees 194 2 2 10 Operation of Timer A one shot time
110. emi0 1 ow speed low power instruction_ __ dissipation mode N Normal mode Refer to the following for the transition of normal mode Interrupt WAIT instruction gt Interrupt ration d Wait mode Stop mode P D Interrupt Interrupt Transition of normal mode Main clock is oscillating Sub clock is stopped Medium speed mode divided by 8 mode BCLK f Xin 8 CM07 0 CMO6 1 wnt omoa oe of ae Medium speed mode CM07 0 Note 1 Main clock is oscillating ny p Sub clock is oscillating 7 High speed mode divided by 2 mode BCLK Xin CMO7 0 CMO6 o CM17 0 CM16 0 BCLK f Xin 2 CMO7 0 CMO06 0 CM17 0 CM16 1 Medium speed mode divided by 4 mode BCLK f Xin 4 CM07 0 CM06 Eio CM17 1 CM16 0 Medium speed mode divided by 16 mode BCLK f Xin 16 CM07 0 CMO6 0 CM17 1 CM16 1 Medium speed mode divided by 8 mode BCLK f Xin 8 CM07 0 CMO6 1 Main clock is oscillating Sub clock is oscillating Low speed mode CM07 0 Note 1 3 BCLK f Xcin CM07 1 CM07 1 Note 2 CMO05 O CMO05 1 Main clock is oscillating CM04 1 Sub clock
111. f XIN 10MHz flash memory version Power consumption 11mW f XIN 3 5MHz Vcc 3V mask ROM version 95mW f XIN 10MHz Vcc 5V flash memory version O I O withstand voltage 5V characteristics Output current 5mA 15mA LED drive port Device configuration CMOS silicon gate Package 52 pin plastic mold SDIP 56 pin plastic mold QFP 6 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Mitsubishi plans to release the following products in the M30201 group 1 Support for mask ROM version and flash memory version 2 ROM capacity 3 Package 52P4B Plastic molded SDIP mask ROM version and flash memory version 56P6S A Plastic molded QFP mask ROM version and flash memory version Apr 2001 M30201F6SP FP M30201F6TFP M30201M6 XXXFP M30201M6T XXXFP Figure 1 4 ROM expansion Type No M30201M4T XXX SP __ Package type SP Package 52P4B FP Package 56P6S A ROM No Omitted for flash memory version Shows difference of characteristics and usage etc Nothing Common T Automobiles ROM capacity 4 32K bytes 6 48K bytes Memory type M Mask ROM version F Flash memory version Shows pin count etc The value itself has no specific meaning M30201 Group M16C Family Figure 1 5 Type No memory size and package stENESAS 7 Rene
112. for the page 256 bytes specified with addresses As to A23 will be output sequentially from the smallest address first in sync with the fall of the clock RxDo M16C reception data A15 A23 M16C emio datao Y J datazss Figure 1 120 Timing for page read Read Status Register Command This command reads status information When the 7016 command code is sent with the 1st byte the contents of the status register SRD specified with the 2nd byte and the contents of status register 1 SRD1 specified with the 3rd byte are read _ RxDO l 7016 M16C reception data SRD SRD1 M16C transmit data output_ _output Figure 1 121 Timing for reading the status register 2tENESAS 161 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Clear Status Register Command This command clears the bits SR38 SR4 which are set when the status register operation ends in error When the 5016 command code is sent with the 1st byte the aforementioned bits are cleared When the clear status register operation ends the RTS1 BUSY signal changes from the H to the L level RxDO 5016 M16C reception data TxDO M16C transmit data Figure 1 122 Timing for clearing the status register Page Program Command This command writes the specified page 256 bytes in the flash me
113. function 0 eee eeeeeeeeetee teeters P262 stENESAS 249 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 6 Input output to the serial I O and the direction register To input an external signal to the serial I O set the direction register of the relevant port to input To output signal from the serial I O set the direction register of the relevant port to output 7 Pins related to the serial I O e CLKO pin Input output pins for the transfer clock e RxDO RxD1 pins Input pins for data e TxDO TxD1 pins Output pins for data Since TxD2 pin is N channel open drain this pin needs pull up resistor e CLKS pin Output pin for transfer clock Can be used as transfer clock output pin in the transfer clock output to multiple pins function Note UART1 cannot be used in clock synchronous serial I O mode 8 Registers related to the serial I O Figure 2 5 1 shows the memory map of serial I O related registers and Figures 2 5 2 to 2 5 4 show serial O related registers 005116 UARTO transmit interrupt control register SOTIC 005216 UARTO receive interrupt control register SORIC 005316 UART1 transmit interrupt control regster S1 TIC 005416 UART1 receive interrupt control register S1RIC 03A016 UARTO transmit receive mode register UOMR 03A116 UARTO bit rate generator UOBRG 03A216 i 03A316 UARTO transmit b
114. i i n 1 One shot pulse output SS E T E a from TAQOUT pin or Timer AO interrupt request bit g Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 20 Operation timing of one shot mode 194 stENESAS Renesas Technology Corp Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting one shot timer mode and functions b7 Selection of one shot timer mode Pulse output function select bit 1 Pulse is output Note External trigger select bit When internal is selected this bit can be 1 or 0 Trigger select bit 0 When the one shot start flag is set 1 0 Must always be 0 in one shot timer mode Count source select bit b7 bg Count Count source period b7 Pe i source f Xin 10MHz f Xcin 32 768kHz 00t fi 100ns 01 fs J 10 fs2 i fs 800ns 1 1 fc32 j fa2 3 2us i fc32 976 56us Note Set the corresponding port direction register to 1 output mode Clearing timer AO interrupt request bit Refer to Precaution for Timer A one shot timer mode b7 bo KXKKX ol TT Timer AO interrupt control register Address 005516 TAOIC Interrupt request bit Setting one shot timer s time b15 b7 bO DOSS TO E Timer AO register Address 038716 038616 TAO o Can be set to 000116 to FFFF16 Setti
115. in compli ance with any of the following procedures Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to 0 after the above listed changes have been made 3 Setting the count start flag to 0 while PWM pulses are being output causes the counter to stop counting If the TXiINOUT pin is outputting an H level in this instance the output level goes to L and the timer Xi interrupt request bit goes to 1 If the TXiINOUT pin is outputting an L level in this instance the level does not change and the timer Xi interrupt request bit does not becomes 1 4 Normal PWM output is restored according to the interrupt request generate timing both in the case of 16 bit PWM and 8 bit PWM when PWM output is either H or L level for the entire period This holds only when a value other than 000016 or FFFF 16 is set during 16 bit PWM or a value other than 0016 or FF 16 is set during 8 bit PWM l l Normal PWM restored here When PWM output is H level for the entire period Writing to the p i imer 4 fX n PWM pulse output H i from TXiINOUT pin Ee i Timer Xi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by softw
116. in the second bus cycle the content of the address is read out The CPU must sequentially erase verify memory contents one address at a time over the entire area erased If any address is encountered whose content is not FF16 not erased the CPU must stop erase verify at that point and execute erase and erase verify operations one more time Note 1 If any unerased memory location is encountered during erase verify operation be sure to execute erase and erase verify operations one more time In this case however the user does not need to write data 0016 to memory before erasing 2tENESAS 131 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Flash memory version Reset command FF16 FF16 The reset command is used to stop the program command or the erase command in the middle of operation After writing command code 4016 or 2016 twice to the flash command register write command code FF 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle The program command or erase command is disabled with the flash memory placed in read mode Program Erase Start Start Address first location All bytes 0016 Loop counter X 0 NO Write program command Write 4016 Write program data Write Program
117. interrupt Note 2 Locate an interrupt vector address in an even address if possible BCLK Address bus Cae Indeterminate SP 2 SP 4 vec vec 2 PC Data bus Interrupt l SP 2 P 4 vec vec 2 ae Indeterminate ae EA contents contents Indeterminate The indeterminate segment is dependent on the queue buffer If the queue buffer is ready to take an instruction a read cycle occurs Figure 1 26 Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL If an interrupt request that does not have an interrupt priority level is accepted one of the values shown in Table 1 11 is set in the IPL Table 1 11 Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL Watchdog timer 7 Reset 0 Other Not changed stENESAS Renesas Technology Corp Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Saving Registers In the interrupt Sequence only the contents of the flag register FLG and that of the program counter PC are saved in the stack area First th
118. is compared with the IPL The interrupt is enabled only when the priority level of the interrupt is higher than the IPL Therefore setting the interrupt priority level to O disables the interrupt Table 4 2 1 shows the settings of interrupt priority levels and Table 4 2 2 shows the interrupt levels en abled according to the consist of the IPL The following are conditions under which an interrupt is accepted interrupt enable flag I flag 1 interrupt request bit 1 interrupt priority level gt IPL The interrupt enable flag I flag the interrupt request bit the interrupt priority select bit and the IPL are independent and they are not affected by one another Table 4 2 1 Settings of interrupt priority levels Table 4 2 2 Interrupt levels enabled according to the contents of the IPL ee Interrupt priority Prionty IPL Enabled interrupt priority levels b2 bi b0 IPL2 IPL1 IPLo 000 Level 0 interrupt disabled 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Level 1 Low 0 0 1 Interrupt levels 2 and above are enabled O10 Level 2 O 1 0 Interrupt levels 3 and above are enabled O 1 1 Level 3 O 1 1 Interrupt levels 4 and above are enabled 1 0 0 Level 4 1 0 0 Interrupt levels 5 and above are enabled 101 Level 5 1 0 1 Interrupt levels 6 and above are enabled 1 1 0 Level 6 11 0 Interrupt levels 7 and above are enabled 1 1 1 Level 7 High 1 1 1 All maskable interrupts are dis
119. measurement MOE cccsecececeecsteeeeeeesseeeeeeeesteeeeeeessieeeeesesneeeeeeees P238 d Pulse width modulation PWM mode In this mode the arbitrary pulses are successively output Either a 16 bit fixed period PWM mode or 8 bit variable period mode can be selected The trigger for initiating output can also be selected 16 bit PWM mode Operation wis 2 sees cen iect evince EE ee veideaeeevntees ican eve es ee N P240 B bit PWM mode operation ensisi aa P242 2 Count source The internal count source can be selected from f1 f8 32 and fc32 Clocks f1 fs and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc32 is derived by dividing the CPU s secondary clock by 32 220 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 3 Frequency division ratio In timer mode or pulse width modulation mode the value set in the timer register 1 becomes the frequency division ratio In event counter mode the set value 1 becomes the frequency division ratio when a down count is performed or FFFF16 the set value 1 becomes the frequency division ratio when an up count is performed In one shot timer mode the value set in the timer register be comes the frequency division ratio The counter overflows or underflows when a count source equal to a frequency division ratio is input and an interrupt occurs For th
120. microcomputer Data sheet and data book Outline design Contents Hardware specifications pin assignment memory map specifications of peripheral func tions electrical characteristics timing charts Hardware Detailed description about hardware specifica tions operation and application examples connection with peripherals relationship with software Method for creating programs using assembly and C languages of system User s manual Detail design of system Programming ow manual Hard eS Soft g ware ware E Software manual devel devel 7 opment opment System evaluation M16C Family Line up M16C Family M16C 80 Series M16C 60 Series M16C 20 Series Detailed description about operation of each instruction assembly language M16C 80 Group M16C 60 Group M16C 61 Group M16C 62 Group M16C 20 Group M16C 21 Group M16C 22 Group M16C 24 Group Table of Contents Chapter 1 Hardware DSS CIID A EEE E E E A ec comand see eee home hada y dec Soe pate eae aaa to Tae bee a hese E eden 2 Memory maiie EAE ae ie ee ie a a ete ie ee ee ee een A 9 Central Processing Unit CPU 0 c ceesceceeseeeeeneeeeeeeeeeeaaeeeseneeecaaeesaaeesaaeesseaaeeseaeesseaaaesseeeeeeiaaesseneees 12 ReS6t eiia a a aii ahi E dian natal T a iae eE T TAN AA E ieee 15 SoftWare Reset nimii e a e aa e a i a a etnies 17 Clock Genera
121. ofi TANN 0to 2 e 036016 kr TMODO Operation mode select bit gt 1 5 O10 TMOD1 0 1 Event counter mode Note 1 OO Pulse output function 0 Pulse is not output select bit TXiINOUT pin is a normal port pin Pulse is output Note 2 TXiINOUT pin is a pulse output pin Invalid in event counter mode Can be 0 or 1 Count polarity r Counts external signal s falling edge select bit Note 3 Counts external signal s rising edge 0 Must always be 0 in event counter mode TCKO Count operation type X Reload type select bit Free run type TCK1 Invalid in event counter mode Can be 0 or 1 Note 1 Count source is selected by event trigger select bit address 038316 in event counter mode Note 2 Set the corresponding port direction register to 1 output mode TXiINOUT pin input is not selected as count source when pulse output function is selected Note 3 This bit is valid when only counting an external signal Figure 1 61 Timer Xi mode register in event counter mode stENESAS Renesas Technology Corp 69 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 3 One shot timer mode In this mode the timer operates only once See Table 1 22 When a trigger occurs the timer starts up and continues operating for a given period Figure 1 62 shows the timer Xi mode register in one shot timer mode Table 1 22 Timer specification
122. onward data Do D7 for the page 256 bytes specified with addresses As to A23 will be output sequentially from the smallest address first As to A16 to RxDO FC16 M16C reception data Foss hae A Sac M16C panami ders datao J faataess Figure 1 128 Timing for boot ROM area output RENESAS 165 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version ID Check This command checks the ID code Execute the boot ID check command as explained here following 1 Transfer the F516 command code with the 1st byte 2 Transfer addresses Ao to A7 As to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd 3rd and 4th bytes respectively 3 Transfer the number of data sets of the ID code with the 5th byte 4 The ID code is sent with the 6th byte onward starting with the 1st byte of the code RxDO M16C reception data TxDO M16C transmit data Figure 1 129 Timing for the ID check ID Code When the flash memory is not blank the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match If the codes do not match the command sent from the peripheral units is not accepted An ID code contains 8 bits of data Area is from the 1st byte addresses OFFFDF 16 OFFFE316 OFFFEB16 OFFFEF16 OFFFF316 OFFFF716 and OFFFFB1e Write
123. operating with XIN set port Xc select bit to 1 before setting system clock select bit to 1 The both bits cannot be set at the same time a Interrupt enable flag I flag lt 1 A clocks off stop mode bo CM1 All clock stop control bit 1 All clocks off stop mode Reserved bit Always set to 0 7 System clock control register 1 Address 000716 NOP instruction X 5 Key input interrupt request generation Pa Figure 3 6 3 Set up procedure of controlling power using stop mode 1 356 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications C Key input interrupt gt Store the registers Key matrix scan b7 bo OTH Port P3 register Address 03E516 P3 Key scan data 1110 1101 1011 0111 K Decision of key input data a b7 rT Tero con P3 register Address 03E5416 3 LIT Key scan data A Restore the registers C REIT instruction Figure 3 6 4 Set up procedure of controlling power using stop mode 2 stENESAS 357 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications 3 7 Controling Power Using Wait Mode Overview
124. output H from TXiINOUT pin q Timer Xi interrupt K request bit Note n 000016 to FFFE16 Figure 2 4 20 Operation timing of pulse width modulation mode 16 bit PWM mode selected 240 CENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting PWM mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of PWM mode 1 Must always be 1 in PWM mode Invalid in event counter mode Can be 0 or 1 o 1 1 1 1 Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 0 Functions as a 16 bit pulse width modulator Count source select bit b7 bg Count Count source period b7 b6 source f Xin 10MHz f XcIN 32 768kHz 00 f1 01 fs 0 0 fi 100ns a OE fa 800ns 1 0 Tal 10 f32 11 fc32 fa2 3 2us fc32 976 56us Note Set the corresponding port direction register which outputs the pulse to 1 output mode Clearing timer Xi interrupt request bit Refer to Precaution for Timer X pulse width modulation mode b7 bo Timer Xi interrupt control register i 0 to 2 Address 005616 to 005816 OOO TXIIC i 0 to 2 gieter m Interrupt request bit M Setting trigger select register b7 b0 Trigger select register Address 038316 TRG
125. pin is outputting an H level in this instance the output level goes to L and the timer AO interrupt request bit goes to 1 If the TAQOUT pin is outputting an L level in this instance the level does not change and the timer AO interrupt request bit does not becomes 1 4 Normal PWM output is restored according to the interrupt request generate timing both in the case of 16 bit PWM and 8 bit PWM when PWM output is either H or L level for the entire period This holds only when a value other than 000016 or FFFF 16 is set during 16 bit PWM or a value other than 0016 or FF 16 is set during 8 bit PWM When PWM output is H level for the entire period Writing to the timer AO PWM pulse output from TAQouT pin Timer AO interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software When PWM output is L level for the entire period Writing to the 1 fi X n timer AO PWM pulse output H il P from TAQouT pin pM Timer AO interrupt 1 request bit o j A Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 32 Operation timing of PWM output mode tENESAS 205 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 Timer B 2 3 1 Overview The following is an overview for timer B a 16 bi
126. program mode is entered by writing the command code 4016 to the flash command register in the first bus cycle When the user execute an instruction to write byte data to the desired address e g STE instruction in the second bus cycle the flash memory control circuit executes the program op eration The program operation requires approximately 20 us Wait for 20 us or more before the user go to the next processing During program operation the watchdog timer remains idle with the value 7FFF 16 set in it Note 1 The write operation is not completed immediately by writing a program command once The user must always execute a program verify command after each program command executed And if verification fails the user need to execute the program command repeatedly until the verification passes See Figure 1 99 for an example of a programming flowchart stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Flash memory version Program verify command C016 The program verify mode is entered by writing the command code C016 to the flash command register in the first bus cycle When the user execute an instruction e g LDE instruction to read byte data from the address to be verified the previously programmed address in the second bus cycle the content that has actually been written to the address is read out from the memory The CPU
127. registers 3 RENESAS 54 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 1 Timer mode In this mode the timer counts an internally generated count source See Table 1 12 Figure 1 41 shows the timer AO mode register in timer mode Table 1 12 Specifications of timer mode Item Specification Count source f1 f8 f32 fc32 Count operation e Down count e When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When the timer underflows TAOIN pin function Programmable I O port or gate input TAOOUT pin function Programmable I O port or pulse output Read from timer Write to timer Count value can be read out by reading timer AO register e When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time e Gate function Select function Counting can be started and stopped by the TAOIN pin s input signal e Pulse output function Each time the timer underflows the TAOOUT pin
128. requested when data transfer from UARTI receive register to UARTI receive buffer register is completed e Overrun error Note 3 This error occurs when the next data is ready before contents of UARTi receive buffer register are read out e Framing error This error occurs when the number of stop bits set is not detected e Parity error This error occurs when if parity is enabled the number of 1 s in parity and character bits does not match the number of 1 s set e Error sum flag This flag is set 1 when any of the overrun framing and parity errors is encountered e Sleep mode selection This mode is used to transfer data to and from one of multiple slave micro computers Interrupt request gen eration timing Error detection Select function Note 1 n denotes the value 0016 to FF 16 that is set to the UART bit rate generator Note 2 fEXT is input from the CLKO pin Since UART1 does not have this pin cannot select external clock Note 3 If an overrun error occurs the UARTi receive buffer will have the next data written in Note also that the UARTI receive interrupt request bit does not change stENESAS 85 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode UARTi transmit receive mode registers b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UiMR i 0 1 03A016 03A816 0016 SMDO__ Seri
129. select bit bit 6 at addresses 03A416 allows selection of the polarity of the transfer clock e When CLK polarity select bit 0 CLKo TxDo X D2 X D3 X D4 X D5 X De X D7 Note 1 The CLKO pin level when not X transferring data is H D2 X D3 X D4 X Ds X De X D7 When CLK polarity select bit 1 CLKo Note 2 The CLKO pin level when not D2 yx D3 X D4 X D5 X D6 X D7 transferring data is L X Di X D2 X D3 X D4 X Ds X De X D7 TXDO X Do Y D1 RXDo X Do X Figure 1 76 Polarity of transfer clock b LSB first MSB first select function As shown in Figure 1 77 when the transfer format select bit bit 7 at addresses 03A416 0 the transfer format is LSB first when the bit 1 the transfer format is MSB first e When transfer format select bit 0 CLKo TXDo X Do X D1 X D2 X D3 X D4 X D5 X De X D7 RXDo X Do X Di X D2 X D3 X D4 X D5 X De X D7 LSB first e When transfer format select bit 1 CLKo TXDo X D7 X De X D5 X D4 X D3 X D2 X D1 X Do RXDo X D7 X De X D5 X D4 X D3 X D2 X Di X Do MSB first Note This applies when the CLK polarity select bit 0 Figure 1 77 Transfer form
130. set to BRGi e Example of transmit timing when transfer data is 9 bits long parity disabled two stop bits Tc Transfer clock LL PLL PULL PULL PLL IL Transmit enable TG g bit TE g Data is set in UARTIi transmit buffer register Transmit buffer empty flag T1 Transferred from UARTI transmit buffer register to UARTi transmit register Stop Stop TxDi Transmit register 1 empty flag TXEPT Transmit interrupt 1 request bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc 16 n 1 fior 16 n 1 fext e Parity is disabled fi frequency of BRGi count source f1 f8 32 e Two stop bits fEXT frequency of BRGi count source external clock e Transmit interrupt cause select bit 0 n value set to BRGi Figure 1 80 Typical transmit timings in UART mode tENESAS 87 Renesas Technology Corp Mitsubishi microcomputers M30201 Group CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode ote ete e Example of receive timing when transfer data is 8 bits long parity disabled one stop bit BRGi count source aq Receive enable bit o RxDi Receive data taken in Transfer clock Reception triggered when transfer clock Transferred from UARTI receive register to Receive 1 is generated by falling edge of start bit UARTI
131. set up procedures Table 2 5 2 Choosed functions Transfer clock Internal clock f1 fs f32 fc source External clock CLKO pin CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock LSB first MSB first Transmission Transmission buffer empty interrupt factor Transmission complete Output transfer clock Not selected to multiple pins Note pee Selected Note This can be selected only when UARTO is used in combination with the internal clock Operation 1 Setting the transmit enable bit to 1 makes data transmissible status ready 2 When transmission data is written to the UARTO transmit buffer register transmission data held in the UARTO transmit buffer register is transmitted to the UARTO transmit register in synchronization with the first falling edge of the transfer clock At this time the first bit of the transmission data is transmitted from the TxDo pin Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock 3 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that the transmission is completed The transfer clock stops at H level At this time the UARTO transmit interrupt request bit goes to 1 4 Setting CLK CLKS sel
132. some differences with regard to the functions not available with the microcomputer function of read device identification code and matters related to memory capacity Table 1 76 shows pin relationship between the M30201 and M5M28F101 in parallel I O mode Table 1 76 Pin relationship in parallel I O mode Vcc M30201 flash memory version Vcc M5M28F 101 Vss Vss Address input P60 to P63 P30 to P33 P10 to P17 P50 Data I O P0o to P07 OE input P41 CE input P43 WE input P40 VRFY input Note P51 Note The VRFY input only selects read only or read write mode and does not have any pin associated with it on the M5M28F101 Microcomputer mode Parallel I O mode 0000016 0040016 YYYYY16 DF00016 Collective erasable programmable DFDFFi6 Collective User ROM erasable area programmable FFFFF16 Boot ROM area 3 5K bytes User ROM area CPU rewrite mode Standard serial I O mode Boot ROM area 3 5K bytes Collective erasable User ROM programmable area Note 1 In CPU rewrite and standard serial I O modes the user ROM is the only erasable programmable area Note 2 In parallel I O mode the area to be erased programmed can be selected by the address A17 input The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low Type No XXXXX16 YYYYY16 M30201F6 F40001
133. source f1 3 As soon as the counter of timer XO becomes 000016 the counter reloads the content of the reload register and stops counting At this time the timer XO interrupt request bit gose to 1 4 An underflow in timer XO triggers the counter of timer X1 and causes it to begin counting When timer X1 begins counting the output level of the TX1INOUT pin gose to H 5 As soon as the counter of timer X1 becomes 000016 the output level of the TX1INOUT pin gose to L the counter reloads the content of the reload register and stops counting At this time timer X1 interrupt request bit gose to 1 346 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications reload register content 1 Count enabled 2 Timer XO start count o 3 Timer XO stop count Timer XO counter content hex i n reload register content 4 Timer X1 start count i L 5 Timer X1 stop count o L c 5 Q 0 x lt a 3 E H content hex Set to 1 by software Timer XO count q start flag 9 Set to 1 by software Timer X1 count 4 start flag o Input signal from H TXOINOUT pin L PWM pulse output H from TX1INOUT pin Timer XO interrupt 1 request bit o Cleared to 0 when interrupt request i
134. start flag Timer Xi interrupt request bit 1 Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi overflow flag wv Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 4 18 Operation timing of pulse width measurement mode 238 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Va Selecting pulse period pulse width measurement mode and functions b7 b0 NZ Timer Xi mode register i 0 to 2 Address 039716 to 039916 TECE Hacer Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 1 0 Pulse width measurement Interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Timer Xi overflow flag 0 Timer did not overflow 1 Timer has overflowed 1 Must always be 1 in pulse period pulse width measurement mode Count source select bit b7 b6 00 Count Count source period source f Xin 10MHz f XcIN 32 768kHz 01 i 100ns 10 800ns 11 3 2us 976 56us Note Set the corresponding port direction register which sets the measurement pulse to O input mode o Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for ge
135. supply voltage VPPH from an external source to this pin In CPU rewrite mode only the user ROM area shown in Figure 1 96 can be rewritten the boot ROM area cannot be rewritten Make sure the program and block commands are issued for only the user ROM area The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area In the CPU rewrite mode because the flash memory cannot be read from the CPU the rewrite control program must be transferred to internal RAM before it can be executed Flash memory control register 0 Flash memory control register 1 b6 b5 b4 b3 b2 bi bd Symbol Address When reset FCON1 03B516 XXXXXX002 Bit symbol Bit name Function OP b7 b5 b4 b3 b2 b0 Symbol Address When reset lo PX 1 0 o X FCONO 03B416 001000002 it fot tot 1 i Bitsymbol Bit name Function RW roo 4 4 4 4 4 EGENOO CPU rewrite mode 0 CPU rewrite mode is invalid oio E TE ETE oo A select bit 1 CPU rewrite mode is valid i l l Doa Reserved bit This bit can not write The value if poi a os read turns out to be indeterminate 7 Booo Fcono2 CPU rewrite mode 0 CPU rewrite mode is invalid Loth Eo i E Saree res monitor flag 1 CPU rewrite mode is valid Oi Doa a Eniregorsdsins Reserved bit Must always be set to 0 o 0 E E Reserved bit Must always be set to 1 o o ro Nothing is assigned In an attempt to write this bit write 0 The value be if read turns out to be 0
136. the counter to hold its value and to stop n reload register content 2 Underflow 4 Stop count Start count again gt i 1 Asie Bees EI eee se 1 1 1 1 1 1 Counter content hex Cleared to 0 by software l Ne Set to 1 by Set to 1 by software vo Count start flag 1 af gt oe a a software Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 request bit Figure 2 4 10 Operation timing of event counter mode reload type selected 230 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting event counter mode and functions p7 20 Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXIMR i 0 to 2 Selection of event counter mode Pulse output function select bit Note 1 Pulse is output TXiINOUT pin is a pulse output pin Invalid when the external signal is not used as a count source Invalid in event counter mode Can be 0 or 1 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type Invalid in event counter mode Can be 0 or 1 Note Set the corresponding port direction register to 1 output mode a TXiINOUT pin input is not selected as count source when pulse output function is selected
137. the measurement pulse to 0 input mode s Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 e CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O XX Setting count start flag b7 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Clearing overflow flag b0 Timer Bi a register i 0 1 Address 039B16 039C16 EX TBMR ico 1 Timer Bi overflow flag 0 Timer did not overflow Figure 2 3 11 Set up procedure of pulse width measurement mode stENESAS 217 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 6 Precautions for Timer B timer mode event counter mode 1 To clear reset the count start flag is set to O Set a value in the timer Bi register then set the flag to 1 2 Reading the timer Bi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Bi register with the reload timing shown in Figure 2 3 12 gets FFFF16 Reading the timer Bi register after setting a value in the timer Bi regis ter with a count halted
138. to 0 L Vref connect bit A D conversion start flag 1 Vref connected 0 A D conversion disabled Must be fixed to 0 Frequency select bit 0 0 fAD 4 is selected 1 faD 2 is selected A D input group select bit 0 Port P6 group is selected 1 Port P5 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANs54 Setting A D conversion start flag b7 7 po A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Start A D conversion Stop A D conversion i i A D register O Address 03C116 03C016 ADO Reading eae A D register 1 Address 03C316 03C216 AD1 bO b7 A D register 2 Address 03C516 03C416 AD2 A D register 3 Address 03C716 03C616 AD3 A D register 4 Address 03C916 03C816 AD4 A D register 5 Address 03CB16 03CA16 AD5 A D register 6 Address 03CD16 03CC16 AD6 A D register 7 Address 03CF16 03CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Figure 2 7 6 Set up procedure of one shot mode RENESAS 291 Renesas Technology Corp
139. to L again the value of the counter is transferred to the reload register and the timer Xi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and the measurement is started again Note e The timer Xi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Xi is overflowed The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Xi overflow flag goes to 1 immediately after a count is performed e The timer Xi overflow flag goes to 0 if timer Xi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software Measurement of pulse time interval from falling edge to falling edge n Start count Start measurement 3 Start measurement again Count source H Measurement pulse a Transfer P Transfer Reload register counter 4 indeterminate value 4 measured value transfer timing i i aai i Note 1 Note 2 Timing at which counter ba Bi reaches 000016 Count start flag E Se to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 request bit g q Timer Xi overflow flag 0 Note 1 Counter is initialized at complet
140. to all data sent with the 5th byte onward 4 The program to execute is sent with the 5th byte onward When all data has been transmitted if the check sum matches the downloaded program is executed The size of the program will vary according to the internal RAM _ RxDO M16C reception data Data size low TxDO Data size high M16C transmit data Figure 1 126 Timing for download 164 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 2 Flash Memory Version S NOH5 OHIP 16 BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area Execute the version information output command as explained here following 1 Transfer the FB16 command code with the 1st byte 2 The version information will be output from the 2nd byte onward This data is composed of 8 ASCII code characters _ RxDO M16C reception data _TxDO M16C transmit data Figure 1 127 Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks 256 bytes Execute the boot ROM area output command as explained here following 1 Transfer the FC16 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 From the 4th byte
141. way as for ANo to AN4 Note 3 If port P5 group is selected the contents of A D registers 5 to 7 are indeterminate If port P5 group is selected do not select 8 pins sweep mode Figure 1 87 A D conversion register in single sweep mode stENESAS 95 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 4 Repeat sweep mode 0 In repeat sweep mode 0 the pins selected using the A D sweep pin select bit are used for repeat sweep A D conversion See Table 1 33 Figure 1 88 shows the A D control register in repeat sweep mode 0 Table 1 33 Repeat sweep mode 0 specifications Item Specification Function The pins selected by the A D sweep pin select bit are used for repeat sweep A D conversion Start condition Writing 1 to A D conversion start flag Stop condition Writing 0 to A D conversion start flag Interrupt request generation timing None generated Input pin ANo and AN1 2 pins ANo to ANs 4 pins ANo to AN5 6 pins or ANo to AN7 8 pins Note Reading of result of A D converter Read A D register corresponding to selected pin at any time Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note 57 206 05 BE De eee Dibo Symbol Address When reset ADCONO 03D616 00000XXX2 Bit symbol Bit name Function CHO Analog input pin select bit Invalid in repeat sweep m
142. when FF 16 is set for the significant 8 bits of the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f32 fc32 n Timer value Conditions Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 When timer overflow is selected in trigger f 1 fi X m 1 X 2 1 i i i Count source ote PPU UUU UUS UU Count start flag ip 1 n 1 1 Start count 2 Output level H to L 3 One period is ki i complete Cleared to 0 when interrupt request is accepted or cleared by software Interrupt request bit H of timer becoming m trigger 4 Stop count et 1 1X m Underflow signal of 8 H i 1 bit prescaler Note 2 a eee i 11 fX m 1 Xn TE PWM pulse output a o P eo o oh zaks TITL from TXiINOUT pin Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt request bit Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16 n 0016 to FF 16 Figure 2 4 22 Operation timing of pulse width modulation mode with 8 bit PWM mode selected 242 tENESAS Renesas Technology Corp Timer X Mitsubishi microcom
143. when a falling edge is input to a key input interrupt pin At this moment the level of other key input interrupt pins must be H No interrupt occurs when the level of other key input interrupt pins is L 3 How to determine a key input interrupt A key input interrupt occurs when a falling edge is input to one of eight pins but each pin has the same vector address Therefore read the input level of pins POo through P07 in the key input interrupt routine to determine the interrupted pin 4 Registers related to the key input interrupt Figure 2 10 1 shows the memory map of key input interrupt related registers and Figure 2 10 2 shows key input interrupt related registers 004D16 Key input interrupt control register KUPIC 03E216 Port PO direction register PDO 03FC16 Pull up control register 0 PURO Figure 2 10 1 Memory map of key input interrupt related registers 318 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt Interrupt control register Note 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset KUPIC 004D16 XXXXX0002 Bit symbol REW ILVLO Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested Oo Oo 1 Interrupt requested Note1 Nothing is assigned In an attemp
144. which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein How to Use This Manual This user s manual is written for the M30201 group The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers This manual is for the use of the models below e M30201M4 XXXSP FP e M30201M4T XXXFP e M30201M6 XXXFP e M30201M6T XXXFP e M30201F6SP FP e M30201F6TFP These products have similar features except for the memories which differ from one pro
145. with this bit set to 1 c Switching the oscillation driving capacity Set the driving capacity to LOW when oscillation is stable d External clock When using an external clock input for the CPU clock set the main clock stop bit to 1 Setting the main clock stop bit to 1 causes the XOUT pin not to operate and the power consumption goes down when using an external clock input the clock signal is input regardless of the content of the main clock stop bit stENESAS 329 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports 2 12 Programmable I O Ports 2 12 1 Overview Fourty three programmable I O ports I O pins also serve as I O pins for built in peripheral functions Each port has a direction register that defines the I O direction and also has a port register for I O data In addition each port has a pull up control register that defines pull up in terms of 4 bits Port P1 can be set to N channel output transistor drive capacity The following is an overview of the programmable I O ports 1 Writing to a port register With the direction register set to output the level of the written values from each relevant pin is output by writing to a port register The output level conforms to CMOS output Writing to the port register with the direction register set to input inputs a value to the port register but nothing is outpu
146. 0 n 0 8 bit resolution Vref X n 28 Vref X0 5 210 n 1 to 256 0 n 0 c Analog input group function The analog input pins can be switched between the port P6 group ANo to AN4 and the port P5 group AN50 to AN54 d Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A D converter To decrease the microcomputer s power consumption cut Vref To carry out A D conversion start A D conversion 1 us or longer after connecting Vref The following are exsamples in which functions a through d are selected OMG SNOt MOC suoritus intine nein ae aaae aias aiia aaaea aE a aE ea ENADE P290 Repeat Mode rrii daisies dees Eiai iiai AEAEE AEREE EARANN EEA OAAR P292 SinglesWeep MODE eakiceavecssececicsstencectcersdaced ia anaedai E aA EAEE Raa P294 Repeated Sweep mode D eacosri ninr i aan R P296 Repeated Sweep mode Tarscsisirirosoniiininiiriiiiinsiti rinia A EEEE ETEEN eee S P298 5 Input to A D converter and direction register To use the A D converter set the direction register of the relevant port to input 6 Pins related to A D converter a ANo pin through AN7 pin Input pins of the A D converter Port P6 group b AN50 pin through AN57 pin Input pins of the A D converter Port P5 group c AVcc pin Power source pin of the analog section d VREF pin Input pin of reference voltage e AVss pin GND pin of the analog section stENESAS 285 Renesas Technology Corp
147. 01 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold b7 b0 A D control register 2 Address 03D416 DDDDI 121214 Ancon A D conversion method select bit 1 With sample and hold Must be fixed to 0 N Setting A D control register 0 and A D control register 1 b7 bO b7 bo Ta er earel register 0 Address 03D616 Io ITTI Single sweep mode is selected Note 1 Invalid in single sweep mode A D sweep pin select bit Note 2 b1 bo A D control register 1 Address 03D716 ADCON1 0 0 ANo AN1 2 pins 0 1 ANo to ANs 4 pins una 1 0 ANo to AN5 6 pins Muste NxgAto g 11 ANo to AN7 8 pins A D conversion start flag Bese mode select Dit 1 Note 1 0 A D conversion disabled Must always be 0 In single sweep mace 8 10 bit mode select bit Frequency select bit 0 0 8 bit mode 0 faD 4 is selected 1 10 bit mode 1 faD 2 is selected Frequency select bit 1 0 faD 2 or fAD 4 is selected 1 fAD is selected Vref connect bit 1 Vref connected Must be fixed to 0 A D input group select bit 0 Port P6 group is selected 1 Port P5 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 t
148. 01 group shrink DIP product top view RENESAS 3 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description PIN CONFIGURATION top view lt gt P52 CLKo ANs52 lt gt P53 CLKS AN53 lt p P54 CKout ANs4 lt gt P60 ANo lt gt P61 AN1 lt gt P62 AN2 lt gt P63 AN3 lt 4 P64 AN4 lt gt P66 ANe 43 lt gt P67 AN7 N C lt gt P00 Klo lt gt P0 Kh gt 2 M30201MX XXXFP pie ers M30201MXT XXXFP lt gt POUT M30201F6FP gt POsiKis O M30201F6TFP lt gt Posikis lt gt P07 KI7 lt gt P10 LEDo amp P11 LED1 lt gt Pi2 LED2 lt gt P13 LED3 P45 TX2INOUT lt gt P44 INT1 TX1INOUT lt gt P43 INTo TXOINouT lt gt 14 O 15 16 17 P42 RxD1 lt gt P41 TAQOUT lt gt P40 TAOIN TxXD1 lt gt Package 56P6S A Figure 1 2 Pin configuration for the M30201 group QFP product top view 4 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Block Diagram Figure 1 3 is a block diagram of the M30201 group 5 2 O ports A D converter System clock generator 10 bits x 8 channels XIN XOUT Expandable up to 13 channels XCIN XCOUT Timer TAO Timer TBO 16 bits Timer TB1 16 bits UART clock synchronous SI O Timer TXO 16 bits 8 bits x 1 channel Timer TX1 16 bits i j UART Timer TX2 16 bits
149. 016 Write 2016 Write erase verify Write A016 command address oe Duration 6us Read expect value FF16 Write read command gt Write read command Write 0016 v y PASS FAIL Figure 1 103 Program and erase execution flowchart in the CPU rewrite mode 2tENESAS 141 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version Protect function In parallel I O mode the internal flash memory has the protect function available This function protects the flash memory contents from being read or rewritten easily Depending on the content at the protect control address FFFFF16 in parallel I O mode this function inhibits the flash memory contents against read or modification The protect control address FFFFF16 is shown in Figure 1 104 This address exists in the user ROM area The protect function is enabled by setting one of the two protect set bits to 0 so that the internal flash memory contents are inhibited against read or modification The protect function is disabled by setting both of the two protect reset bits to 00 so that the internal flash memory contents can be read or modified Once the protect function is set the user cannot change settings of the protect clear bits while in parallel I O mode Settings of the protect reset
150. 016 to FFFDB16 If the starting addresses of subroutines or the destination addresses of jumps are stored here subroutine call instructions and jump instructions can be used as 2 byte instructions reducing the number of program steps 0000016 SFR area For details see Figures 1 7 to 1 8 FFEO016 0040016 Internal RAM area Special page vector table A Address RAM size YYYYY 16 1K bytes 007FFi6 I EEA BRK instruction Address Address match ROM size XXXXX16 Single step 32K bytes F800016 ee timer Internal ROM area 48K bytes F400016 FFFFF16 Figure 1 6 Memory map RENESAS 9 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Memory 000016 004016 000116 004116 000216 004216 000316 004316 000416 Processor mode register 0 PMO 004416 000516 Processor mode register 1 PM1 004516 000616 System clock control register 0 CMO 004616 000716 System clock control register 1 CM1 004716 000816 004816 000916 Address match interrupt enable register AIER o00A16 Protect register PRCR 004916 000B16 000C16 004A16 000D16 004B16 000E16 Watchdog timer start register WDTS 004C16 o00F16 Watchdog timer control register WDC 004D16 Key input interrupt control register KUPIC 001016 004E16 A D conversion interrupt control register ADIC 001116 Address match interrupt register 0 RMADO 004F 16 001216 005016 00131
151. 03CC16 A D register 7 Address 03CF16 03CE16 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate k jana hann Setting A D conversion start flag b7 bo 0 A D control register 0 Address 03D616 ADCONO A D conversion start flag 0 A D conversion disabled Stop A D conversion Figure 2 7 15 Set up procedure of repeat sweep 1 mode stENESAS 299 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 7 Precautions for A D Converter 1 Write to each bit except bit 6 of A D control register 0 to each bit of A D control register 1 and to bit 0 of A D control register 2 when A D conversion is stopped before a trigger occurs In particular when the Vref connection bit is changed from 0 to 1 start A D conversion after an elapse of 1 us or longer 2 To reduce conversion error due to noise connect a voltage to the AVcc pin and to the Vref pin from an independent source It is recommended to connect a capacitor between the AVss pin and the AVcc pin between the AVss pin and the Vref pin and between the AVss pin and the analog input pin ANi ANSsi Figure 2 7 16 shows the an example of connecting the capaci tors to these pins Microcomputer
152. 03DC16 039D16 03DD16 039E16 03DE16 039F16 03DF16 03A016 UARTO transmit receive mode register UOMR 03E016 Port PO PO 03A116 UARTO bit rate generator UOBRG 03E116 Port P1 P1 03A216 A 03E216 _Port PO direction register PDO oik UARTO transmit buffer register UOTB 03 3 Port P1 direction register PD1 03A416 UARTO transmit receive control register 0 U0CO 03E416 _Port P2 P2 Reserved 03A516 UARTO transmit receive control register 1 U0C1 03E516 Port P3 P3 03A616 UARTO receive buffer register UORB 03E616 _Port P2 direction register PD2 Reserved 03A716 03E716 Port P3 direction register PD3 03A816 UART1 transmit receive mode register U1MR 03E816 Port P4 P4 03A916 UART1 bit rate generator U1BRG 03E916 Port P5 P5 03AAte UARTI transmit buffer register U1TB 03E Bort Pa direction register PDS 03AB16 03EB16 Port P5 direction register PD5 03AC16 UART1 transmit receive control register 0 U1C0 03EC16 Port P6 P6 03AD16 UART1 transmit receive control register 1 U1C1 03ED16 Port P7 P7 03AE16 F 03EE16 Port P6 direction register PD6 OSAF te UART1 receive buffer register U1RB 03EF16 Port P7 direction P PD7 03B016 UART transmit receive control register 2 UCON 03F016 03B116 03F116 03B216 03F216 03B316 03F316 03B416 Flash memory control register 0 FCONO Note1 03F416 03B516
153. 0616 and 000716 EES Enables writing to processor mode lt Writa inhihi PRC1 registers 0 and 1 addresses 000416 H e manen and 000516 Enables writing to port P4 direction 0 Write inhibited register address 03EA16 Note 1 Write enabled Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note Writing a value to an address after 1 is written to this bit returns the bit to 0 Other bits do not automatically return to 0 and they must therefore be reset by the program Figure 1 21 Protect register stENESAS 27 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Overview of Interrupt Type of Interrupts Figure 1 22 lists the types of interrupts Undefined instruction UND instruction Overflow INTO instruction Software _ BRK instruction INT instruction Interrupt P Reset DBC Special Watchdog timer Single step Hardware Address matched Peripheral 1 0 1 Peripheral I O interrupts are generated by the peripheral functions built into the microcomputer system Figure 1 22 Classification of interrupts e Maskable interrupt An interrupt which can be enabled disabled by the interrupt enable flag I flag or whose interrupt priority can be changed by priority level e Non maskable interrupt An interrupt w
154. 0bps 8MHz 7 3728MHZ 6MHz 5MHz 4 5MHZ 4 1943804MHz 4MHz 3 58MHZ 3MHz lt je 2 Je Je 2 Je 2 2 2MHz y Communications possible Communications not possible 2tENESAS Renesas Technology Corp 159 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Software Commands Table 1 83 lists software commands In the standard serial I O mode 2 erase operations programs and reading are controlled by transferring software commands via the RxDo pin Standard serial I O mode 2 adds four transmission speed commands 9 600 19 200 38 400 and 57 600 bps to the software com mands of standard serial O mode 1 Software commands are explained here below Table 1 83 Software commands Standard serial I O mode 2 1st byt When ID is ilp d Address Address Data Data Data Data Not age rea FF16 middle high acceptable o p Address Address Data Data Data Data Not age program 4116 middle high input input input input to acceptable 259th byte 3 Erase all unlocked blocks A716 D016 E 4 Read status register 7016 Seale Acesptable 5 Clear status register 5016 eee f Address Address Not 6 Read lock bit status 7116 middle high acceptable f Address Address
155. 1 Count stop condition e A new count is reloaded after the count has reached 000016 e The count start flag is reset 0 Interrupt request generation timing The count reaches 000016 TAOIN pin function Programmable I O port or trigger input TAOOUT pin function Programmable I O port or pulse output Read from timer When timer AO register is read it indicates an indeterminate value Write to timer When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Timer AO mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TEORANN TAOMR oesie Gon TMODO Operation mode select bit 7 b0 0 0 1 0 One shot timer mode TMOD1 O O Pulse output function 0 Pulse is not output select bit ioe pin is a normal port pin Pulse is output Note 1 aa pin is a pulse output pin rog External trigger select 0 Falling edge of TAOIN pin s input signal Note 3 bit Note 2 1 Rising edge of TAOIN pin s input signal Note 3 Trigger select bit i One shot start flag is valid Selected by event trigger select register 0 Must always be 0 in one shot timer mode Count source select bit Note 1 Set the corresponding port direction register to 1 output mode Note
156. 1 Address 03A516 U0C1 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled XQ Writing next transmit data b15 b8 b7 b0 b7 UARTO transmit buffer register Address 03A316 03A216 UOTB Setting transmission data F A ENENENNNNNNNENNNNENENENNNNENNNNNNNNNNNNNENNENNNNNNENNNNNNENNNNNNENEENNEENNENNNENNENNT i nunnnunnnnnunnnnnnunannununanannananann i Transmission is complete Figure 2 5 10 Set up procedure of transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected 2 RENESAS 261 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 4 Operation of Serial I O reception in clock synchronous serial I O mode In receiving data in clock synchronous serial I O mode choose functions from those listed in Table 2 5 3 Operations of the circled items are described below Figure 2 5 11 shows the operation timing and Fig ures 2 5 12 and 2 5 13 show the set up procedures Table 2 5 3 Choosed functions Transfer clock Internal clock f1 fs f32 fc source External clock CLKO pin CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer
157. 1 40 External clock input Standard Parameter Min Max External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Table 1 41 Timer A input counter input in event counter mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAOIN input LOW pulse width Table 1 42 Timer A input gating input in timer mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAO input LOW pulse width Table 1 43 Timer A input external trigger input in one shot timer mode Standard i Max Parameter TAOIN input cycle time TAOIN input HIGH pulse width TAOIN input LOW pulse width Table 1 44 Timer A input external trigger input in pulse width modulation mode Standard Symbol Parameter Min Max tw TAH TAOIN input HIGH pulse width 100 tw TAL TAOIN input LOW pulse width 100 Table 1 45 Timer A input up down input in event counter mode Standard Parameter Min Max tc UP TAOouTt input cycle time tw UPH TAOouT input HIGH pulse width tw UPL TAOout input LOW pulse width tsu UP TIN TAOout input setup time th TIN UP TAOouT input hold time tENESAS 115 Renesas Tec
158. 16 TAO _ Can be set to 000016 to FFFF16 A N N r Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XcIN by 32 b7 bO Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect k 1 Prescaler is reset When read the value is 0 Setting count start flag b7 bO Count start flag Address 038016 C1 bt TABSR Timer AO count start flag Start count Figure 2 2 9 Set up procedure of timer mode gate function selected RENESAS 183 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 4 Operation of Timer A timer mode pulse output function selected In timer mode choose functions from those listed in Table 2 2 3 Operations of the circled items are described below Figure 2 2 10 shows the operation timing and Figure 2 2 11 shows the set up proce dure Table 2 2 3 Choosed functions Count source Internal count source fi fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAOIN pin is at L level Performs count only for the period in which the TAOIN pin is at H level Operation 1 Setting the count start
159. 304g Mi mog VEE 1 VREF 4 VREF X VREF _ VREF v H i A D converter stopped 1st comparison v 2nd comparison y st comparison result 3rd comparison ns 110 010100 A 2nd comparison result 2 4 8 2048 ns 0 VREF _ VREF v 8th i ng ns ne n5 n4 n3 SREP comparison 956 DO4B v Conversion n9 n8 n7 n6 n5 n4 n3 n2 0 complete This data transfers to bit 0 to bit 7 of A D register Result of A D conversion Theoretical A D conversion characteristic of general 8 bit A D converter Theoretical A D conversion characteristic in the 8 bit mode VREF x 4 VREF y 954 VREF y 255 VREF 256 256 256 Analog input voltage Figure 2 7 19 Theoretical A D conversion characteristics 8 bit mode 304 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 10 Absolute Accuracy and Differential Non Linearity Error Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A D conversion characteristics and actual A D conversion result When measuring absolute accuracy the voltage at the middle point of the width of analog input voltage 1 LSB width that can meet the expectation of outputting an equal code based on the theoretical A D conversion characteristics
160. 35 P40 to P45 loL 1 mA 05 v voltage P50 to P54 P60 to P67 P70 P71 VoL LOW output p49 to P17 HIGHPOWER loL 3 mA 0 5 v voltage LOWPOWER loL 1 mA 05 LOW output HIGHPOWER loH 0 1 mA 0 5 VoL voltage XOUT V LOWPOWER loH 50 pA 0 5 LOW output HIGHPOWER No load 0 VoL voltage XOUT V LOWPOWER No load 0 Vt VT Hysteresis TAOIN TXOINOUT TX1 INOUT TX2INOUT TBOIN TB1IN INTo INT1 CLKo Klo to KI7 0 2 0 8 V RxDo RxD1 VT VT Hysteresis RESET 0 2 1 8 V IIH HIGH input POo to P07 P10 to P17 P30 to P35 current P40 to P45 P50 to P54 P60 to P67 Vi 3V 4 0 uA P70 P71 RESET CNVss liL LOW input P00 to P07 P10 to P17 P30 to P35 current P40 to P45 P50 to P54 P60 to P67 Vi 0V 4 0 uA P70 P71 RESET CNVss RPULLUP Pull up P00 to P07 P10 to P17 P30 to P35 Vie OV resistor P40 to P45 P50 to P54 P60 to P67 P70 P71 66 0 120 0 500 0 ka RXIN Feedback resistor XIN 3 0 MQ RXIN Feedback resistor XIN 10 0 Ma VRAM RAM retention voltage When clock is stopped 2 0 V f XIN 3 5MHz 35 7 0 mA Square wave no division f XCIN 32kHz A Square wave 40 0 p f XCIN 32kHz r When a WAIT instruction 2 8 uA a Pin is executed Icc Power supply current o Oscillation capacity HIGH Note 2 f XCIN 32kHz When a WAIT instruction 0 9 uA is executed Oscillation capacity LOW Note 2 Ta 25 when 1 0 clock is stopped uA Ta 85 when clock 20 0 is stopped Note 1 Unless otherwise noted Vcc 3V Vss OV at Ta 20 to 85 C f XIN 3 5MHz Extended operating temp
161. 4 is selected CKS1 1 faD is selected VCUT Vref connect bit 1 Vref connected o 0 Set this bit to 0 loo pi a 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected oo Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate Figure 1 86 A D conversion register in repeat mode 94 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 3 Single sweep mode In single sweep mode the pins selected using the A D sweep pin select bit are used for one by one A D conversion See Table 1 32 Figure 1 87 shows the A D control register in single sweep mode Table 1 32 Single sweep mode specifications Specification Function The pins selected by the A D sweep pin select bit are used for one by one A D conversion Start condition Writing 1 to A D converter start flag Stop condition e End of A D conversion A D conversion start flag changes to 0 e Writing 0 to A D conversion start flag Interrupt request generation timing End of A D conversion Input pin ANo and AN1 2 pins ANo to AN3 4 pins ANo to AN5 6 pins or ANo to AN7 8 pins Note Reading of result of A D converter Read A D register corresponding to selected pin Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0
162. 5 Interrupt table register INTB Interrupt table register INTB is configured with 20 bits indicating the start address of an interrupt vector table 6 Stack pointer USP ISP Stack pointer comes in two types user stack pointer USP and interrupt stack pointer ISP each config ured with 16 bits Your desired type of stack pointer USP or ISP can be selected by a stack pointer select flag U flag This flag is located at the position of bit 7 in the flag register FLG 7 Static base register SB Static base register SB is configured with 16 bits and is used for SB relative addressing 8 Flag register FLG Flag register FLG is configured with 11 bits each bit is used as a flag Figure 1 10 shows the flag register FLG The following explains the function of each flag e Bit 0 Carry flag C flag This flag retains a carry borrow or shift out bit that has occurred in the arithmetic logic unit Bit 1 Debug flag D flag This flag enables a single step interrupt Wher this flag is 1 a single step interrupt is generated after instruction execution This flag is cleared to 0 when the interrupt is acknowledged e Bit 2 Zero flag Z flag This flag is set to 1 when an arithmetic operation resulted in 0 otherwise cleared to 0 e Bit 3 Sign flag S flag This flag is set to 1 when an arithmetic operation resulted in a negative value otherwise cleared to 0 e Bit 4 Register bank select
163. 6 005116 UARTO transmit interrupt control register SOTIC 001416 005216 UARTO receive interrupt control register SORIC 001516 Address match interrupt register 1 RMAD1 005316 UART1 transmit interrupt control register S1TIC 001616 005416 UART1 receive interrupt control register S1RIC 001716 005516 Timer AO interrupt control register TAOIC 001816 005616 Timer XO interrupt control register TXOIC 001916 005716 Timer X1 interrupt control register TX1IC 001A16 005816 Timer X2 interrupt control register TX2IC 001B16 005916 001C16 o05A1s Timer BO interrupt control register TBOIC 001D16 oosBie Timer BT interrupt control register TB1IC 001E16 005C16 001F16 005D16 INTO interrupt control register INTOIC 002016 005E16 INTT interrupt control register INTTIC 002116 005F16 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Note Locations in the SFR area where nothing is allocated are reserved areas Do not access these areas for read or write Figure 1 7 Location of peripher
164. 6 OOBFF16 Figure 1 100 Block diagram of flash memory version 134 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version P61 AN1 P60 ANo lt gt 5 P62 AN2 VREF gt P63 AN3 AVcc gt lal P64 AN4 P54 CKouT AN54 lt p gt sl P65 ANs5 P53 CLKS AN53 lt gt a P66 ANe P52 CLKo ANs2 lt gt 7 P67 AN7 P51 RxDo ANs1 lt gt 3 POo Klo P50 TxDo ANs50 lt gt 9 P01 Kl1 Po2 Kl2 P03 KI3 P04 Kl4 POs Kis5 PO6 Kle Connect oscillator circuit PO7 KI7 P10 LEDo P11 LED1 P45 TX2INOUT lt gt P12 LED2 P44 INT1 TX1 INOUT lt gt Fol P13 LEDs P43 INT0 TXOINOUT lt gt 20 P14 LED4 P71 TB1IN XCIN lt gt i1 P70 TBOIN Xcout lt gt w MO T D wn U P42 RxD1 lt gt P15 LEDs P41 TAQouT 4 55 P16 LEDe P40 TAOIN TxD1 lt gt 23 P17 LED7 P30 P31 P32 Figure 1 101 Pin connection diagram in parallel I O mode 1 RENESAS 135 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version lt gt P53 CLKS ANs3 5q 4 gt P54 CKouT ANS4 5d 4 gt P52 CLKo ANs2 lt gt P60 ANo P51 RxDo ANs1 lt gt 42 lt gt P67 AN7 P50 TxDo ANso lt gt N C ad lt gt Pook CDO CNVss gt P71 TB1IN XCIN lt
165. 6FP The contents of these examples cannot be guaranteed For standardized values see Electric characteristics Vcc 5V e Measurement conditions Vcc 5V Ta 25 C f XIN square waveform input single chip mode When access to ROM and RAM without wait e Register setting condition XIN XOUT drive capacity select bit 1 HIGH Main clock XIN XOUT stop bit 0 On o XIN 1 m XIN 2 A XIN 4 gt lt XIN 8 Ke XIN 16 6 f XIN MHz Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figures 5 3 4 Standard characteristics of ICC f XIN Vcc 5V 394 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version 5 4 Standard Characteristics of Pull Up Resistor Figure 5 4 1 shows an example of the standard characteristics of the pull up resistor The standard character istics given in this section are examples of M30201F6FP The contents of these examples cannot be guaran teed For standardized values see Electric characteristics VI V Note Data described here are characteristic examples The data values are not guaranteed Figure 5 4 1 Example of the standard characteristics of the pull up resistor stENESAS 395 Renesas Tech
166. 7 Prescaler select bit 0 Divided by 16 1 Divided by 128 Watchdog timer start register b7 b0 Symbol Address When reset Loo e WDTS 000E16 Indeterminate Function The watchdog timer is initialized and starts counting after a write instruction to this register The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written Figure 2 8 2 Watchdog timer related registers stENESAS 311 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer 2 8 2 Operation of Watchdog Timer The following is an operation of the watchdog timer Figure 2 8 3 shows the operation timing and Figure 2 8 4 shows the set up procedure Operation 1 Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start a down count 2 With a count in progress writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting 3 Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting The watchdog timer resumes count ing after returning from the execution of the WAIT instruction or from the stopped state 4 If the watchdog timer underflows it is initialized to 7ZFFF16 and continues counting At this time a watchdog timer interrupt occurs 1 S
167. 8 dsp 8 FB IMM8 dsp 8 FB dsp 8 FB 0 dsp 8 FB IMM8 dsp 8 FB IMM8 dsp 8 FB IMM8 dsp 8 FB 0111 7 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S IMM8 abs16 IMM8 abs16 abs16 0 abs16 IMM8 abs16 IMM8 abs16 IMM8 abs16 1000 8 XOR B OR B G SUB B G SBB B ADD B Q MOV B Q SHL B ADJNZ B src dest src dest src dest src dest IMM dest IMM dest IMM dest IMM dest label 1001 9 XOR W OR W G SUB W G SBB W ADD W Q MOV W Q SHL W ADJNZ W src dest src dest src dest src dest IMM dest IMM dest IMM dest IMM dest label 1010 A PUSH B S POP B S MOV W S INC W PUSH W S POP W S MOV B S DEC W ROH ROH IMM A1 A1 A1 A1 IMM A1 A1 1011 B SUB B S OR B S DEC B NOT B S STZ STZX CODE_EB REIT IMM8 ROH IMM8 ROH ROH ROH IMM8 ROH IMM8 IMM8 ROH 1100 Cc SUB B S OR B S DEC B NOT B S STZ STZX PUSHM JMP A IMM8 ROL IMM8 ROL ROL ROL IMM8 ROL IMM8 IMM8 ROL src label 1101 D SUB B S OR B S DEC B NOT B S STZ STZX POPM JSR A IMM8 dsp 8 SB IMM8 dsp 8 SB dsp 8 SB dsp 8 SB IMM8 dsp 8 SB IMM8 IMM8 dsp 8 SB dest label 1110 E SUB B S OR B S DEC B NOT B S STZ STZX JMPS JMP B IMM8 dsp 8 FB IMM8 dsp 8 FB dsp 8 FB dsp 8 FB IMM8 dsp 8 FB IMM8 IMM8 dsp 8 FB IMM8 label 1111 F SUB B S OR B S DEC B NOT B S STZ STZX JSRS UND IMM8 abs16 IMM8 abs16 abs16 abs16 IMM8 abs16 IMM8 IMM8 abs16 IMM8 lt CENESAS 399 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Revision History Version Contents for change
168. 88 A D conversion register in repeat sweep mode 0 96 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 5 Repeat sweep mode 1 In repeat sweep mode 1 all pins are used for A D conversion with emphasis on the pin or pins selected using the A D sweep pin select bit See Table 1 34 Figure 1 89 shows the A D control register in repeat sweep mode 1 Table 1 34 Repeat sweep mode 1 specifications Item Specification Function All pins perform repeat sweep A D conversion with emphasis on the pin or pins selected by the A D sweep pin select bit Example ANo selected ANo AN1 gt ANo gt AN2 gt ANo gt AN3 etc Start condition Writing 1 to A D conversion start flag Stop condition Writing 0 to A D conversion start flag Interrupt request generation timing None generated Input pin ANo 1 pin ANo and AN1 2 pins ANo to AN2 3 pins ANo to AN3 4 pins Note Reading of result of A D converter Read A D register corresponding to selected pin at any time Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note b7 b6 b5 b4 b3 b2 bl bO Symbol Address When reset Joh ADCONO 03D616 00000XXX2 Bit symbol Bit name Function Analog input pin select bit Invalid in repeat sweep mode 1 A D operation mode 7 select bit 0 Set this bit to 0 A D convers
169. 9 1 shows unexecuted instructions and corresponding the stacked addresses lt Instructions whose address is added to by 2 when an address match interrupt occurs gt e 16 bit operation code instructions e 8 bit operation code instructions given below ADD B S IMM8 dest SUB B S IMM8 dest AND B S IMM8 dest OR B S IMM8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMM8 dest PUSHM src POPM dest JMPS IMM8 JSRS IMM8 MOV B S _ IMM dest However dest A0 A1 lt Instructions whose address is added to by 1 when an address match interrupt occurs gt e Instructions other than those listed above Figure 2 9 1 Unexecuted instructions and corresponding stacked addresses 4 How to determine an address match interrupt Address match interrupts can be set at two different locations However both location will have the same vector address Therefore it is necessary to determine which interrupt has occurred address match interrupt 0 or address match interrupt 1 Using the content of the stack etc determine which interrupt has occurred according to the first part of the address match interrupt routine 314 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt 5 Registers related to the address match interrupt Figure 2 9 2 shows the memory map of address match interrupt relate
170. A23 TxDO M16C transmit data P53 BUSY Figure 1 110 Timing for the page program 150 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version Erase All Unlocked Blocks Command This command erases the content of all blocks Execute the erase all unlocked blocks command as explained here following 1 Transfer the A716 command code with the 1st byte 2 Transfer the verify command code D016 with the 2nd byte With the verify command code the erase operation will start and continue for all blocks in the flash memory When block erasing ends the P53 BUSY signal changes from the H to the L level The result of the erase operation can be known by reading the status register RxDO A716 D016 M16C reception data LATS _TxDO M16C transmit data P53 BUSY Figure 1 111 Timing for erasing all unlocked blocks Read Lock Bit Status Command This command reads the lock bit status of the specified block Execute the read lock bit status com mand as explained here following 1 Transfer the 7116 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 The lock bit data of the specified block is output with the 4th byte Write the highest address of the specified block for addresses As to A23 T
171. Address 7 Code processing function F516 low middle high ID size ID1 To ID7 Acceptable 3 p load f Size To Not ownload function FA16 Size low high Data required acceptable input number of times 9 Version data output function FB46 Acceptable Address Address ta Not 10 Boot ROM area output FC16 middle high acceptable function 11 Baud rate 9600 B016 Acceptable 12 Baud rate 19200 B116 Acceptable 13 Baud rate 38400 B216 Acceptable 14 Baud rate 57600 B316 Acceptable Note 1 Shading indicates transfer from flash memory microcomputer to peripheral unit All other data is trans ferred from the peripheral unit to the flash memory microcomputer Note 2 SRD refers to status register data SRD1 refers to status register 1 data Note 3 All commands can be accepted when the flash memory is totally blank 160 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 2 Flash Memory Version SN tE CHIP 16 BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page 256 bytes in the flash memory sequentially one byte at a time Execute the page read command as explained here following 1 Transfer the FF16 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 From the 4th byte onward data Do D7
172. Address 004D16 Address 004E 16 Address 005116 005316 Address 005216 005416 Address 005516 2 Address 005616 to 005816 Address 005A16 005B16 TE i 0 ti ooo 36 Interrupt priority level select bit 0 00 Interrupt disabled Nes Canceling protect b0 addresses 000616 and 000716 1 Write enabled NS b7 2 Protect register Address 000A16 DADA 1 PRCR Enables writing to system clock control registers 0 and 1 INTiIC i 0 1 Address 005D16 005E16 Interrupt priority level select bit 000 Interrupt disabled Always set to 0 fr Setting operation clock after returning from stop mode When operating with XIN after returning m bo System clock control register 0 l 0 Address 000616 CMO Main clock XIN XOUT stop bit On System clock select bit XIN XOUT As this register becomes setting mentioned above when operating with XIN count source of BCLK is XIN the user does not need to set it again When operating with XCIN after returning bo System clock control register 0 Address 000616 CMO Port Xc select bit XCIN XCOUT generation System clock select bit XCIN XCOUT As this register becomes setting mentioned above when operating with XCIN count source of BCLK is XcIN the user does not need to set it again When
173. B s z Note These registers consist of two register banks Figure 1 9 Central processing unit register 1 Data registers RO ROH ROL R1 R1H R1L R2 and R3 Data registers RO R1 R2 and R3 are configured with 16 bits and are used primarily for transfer and arithmetic logic operations Registers RO and R1 each can be used as separate 8 bit data registers high order bits as ROH R1H and low order bits as ROL R1L In some instructions registers R2 and RO as well as R3 and R1 can use as 32 bit data registers R2RO R3R1 2 Address registers AO and A1 Address registers AO and A1 are configured with 16 bits and have functions equivalent to those of data registers These registers can also be used for address register indirect addressing and address register relative addressing In some instructions registers A1 and AO can be combined for use as a 32 bit address register A1A0 Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register 12 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU 3 Frame base register FB Frame base register FB is configured with 16 bits and is used for FB relative addressing 4 Program counter PC Program counter PC is configured with 20 bits indicating the address of an instruction to be executed
174. B16 Reset Note Interrupts used for debugging purposes only FFFFCis to FFFFFie RENESAS 31 Renesas Technology Corp Int errupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Variable vector tables The addresses in the variable vector table can be modified according to the user s settings Indicate the first address using the interrupt table register INTB The 256 byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables One vector table comprises four bytes Set the first address of the interrupt routine in each vector table Table 1 7 shows the interrupts assigned to the variable vector tables and addresses of vector tables Table 1 7 Interrupt causes variable interrupt vector addresses Software interrupt number Software interrupt number 0 Vector table address Address L to address H 0 to 3 Note Interrupt source BRK instruction Remarks Cannot be masked by flag Software interrupt number 11 44 to 47 Note Software interrupt number 12 Note Software interrupt number 13 52 to 55 Note Key input interrupt Software interrupt number 14 Note 48 to 51 Note Note Note 56 to 59 Note A D Software interrupt number 17 68 to 71 Note UARTO transmit Software interrupt number 18 72 to 75 Note UARTO receive S
175. COMPUTER A D Converter 1 One shot mode In one shot mode the pin selected using the analog input pin select bit is used for one shot A D conver sion See Table 1 30 Figure 1 85 shows the A D control register in one shot mode Table 1 30 One shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A D conversion Start condition Writing 1 to A D conversion start flag Stop condition e End of A D conversion A D conversion start flag changes to 0 e Writing 0 to A D conversion start flag Interrupt request generation timing End of A D conversion Input pin One of ANo to AN7 as selected Note Reading of result of A D converter Read A D register corresponding to selected pin Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset ololo ADCONO 03D616 00000XXX2 Bit symbol Bit name Function Analog input pin select bit ANo is selected AN1 is selected AN2 is selected CH1 AN3 is selected AN4 is selected AN5 is selected AN6 is selected Grig AN7 is selected MDO MD1 Set this bit to 0 ADST A D conversion start flag 0 A D conversion disabled 1 A D conversion started Frequency select bit 0 0 faD 4 is selected CKSO 1 faD 2 is selected Note 1 If the A D control register is rewritten
176. CON2 92 03D516 03D616 A D control register 0 ADCONO 03D716 A D control register 1 ADCON1 91 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 Port PO PO 03E116 Port P1 P1 194 03E216 Port PO direction register PDO 03E316 Port P1 direction register PD1 103 03E46 Port P2 P2 03E516 Port P3 P3 104 03E616 Port P2 direction register PD2 103 03E716 Port P3 direction register PD3 03E816 Port P4 P4 03E916 Port P5 P5 104 03EA16 Port P4 direction register PD4 03EB16 Port P5 direction register PD5 103 03EC16 Port P6 P6 03ED1e Port P7 P7 194 03EE16 Port P6 direction register PD6 03EF16 Port P7 direction register PD7 igs 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 Pull up control register 0 PURO 03FD16 Pull up control register 1 PUR1 105 03FE16 _Pull up control register 2 PUR2 03FF16 Chapter 1 Hardware Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Description The M30201 group of single chip microcomputers are built using the high performance silicon gate CMOS process using a M16C 60 Series CPU core M30201 group is packaged in a 52 pin pl
177. D conversion start flag A D register i A D conversion interrupt request Cleared to 0 when interrupt request is accepted or cleared by software Note When aD frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 oaD cycles for 8 bit resolution and 59 AD cycles for 10 bit resolution Figure 2 7 5 Operation timing of one shot mode 290 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold b7 b0 A D control register 2 Address 03D416 DDDDI 12 fo 1 ancone A D conversion method select bit 1 With sample and hold Must be fixed to 0 Setting A D conirol register 0 and A D conirol register 1 b7 bo b7 bo i Godse A D control register 0 Address 03D616 A D control register 1 Address 03D716 ADCONO ADCON1 Analog input pin select bit Note 2 Invalid in one shot mode b2 b1 b0 0 0 0 AN0 is selected A D operation mode select bit 1 Note 1 AN1 is selected 0 Must always be 0 in one shot mode AN2 is selected AN3 is selected 8 10 bit mode select bi AN4 is selected 0 8 bit mode AN5 is selected 1 10 bit mode AN6 is selected AN7 is selected 1 1 0 0 1 1 Frequency select bit 1 0 faD 2 or fAD 4 is selected 1 faD is selected One shot mode is selected Note 1 Must be fixed
178. D1 select bit 11 PWM mode MRO 1 Must always be 1 in PWM mode o o MR1 External trigger select o Falling edge of TAON pin s input signal Note 2 bit Note 1 1 Rising edge of TAO pin s input signal Note 2 Trigger select bit 0 Count start flag is valid 1 Selected by event trigger select register 16 8 bit PWM mode 0 Functions as a 16 bit pulse width modulator select bit 1 Functions as an 8 bit pulse width modulator Count source select bit Note 1 Valid only when the TAOIN pin is selected by the event trigger select bit addresses 038316 If timer overflow is selected this bit can be 1 or O Note 2 Set the corresponding port direction register to 0 input mode Note 3 Set the corresponding port direction register to 1 output mode when the pulse is output Figure 1 45 Timer AO mode register in pulse width modulation mode stENESAS 57 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Condition Reload register 000316 when external trigger rising edge of TAOIN pin input signal is selected 1 fx 216 1 Count source TAOIN pin i f input signal op a Trigger is not generated by this signal i kese 1 fiXn PWM pulse output H from TAOOouT pin p gt ee Timer AO interrupt request bit fi Frequency of count source f1 fa f32 fc32 Cleared to 0 when inte
179. E A TBO interrupt request generated Starting main clock oscillator b7 bo oh System clock control register 0 Address 000616 CMO Main clock XIN XOUT stop bit 0 On Switching system clock b7 b0 Syst lock control register 0 Add 0006 oT TT TT 7 ae clock control register ress 16 System clock select bit 0 XIN XOUT Figure 3 7 3 Set up procedure of controlling power using wait mode 2 360 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications C INTO interrupt Timer BO interrupt Store the registers Store the registers Counting clock Restore the registers Restore the registers REIT instruction REIT instruction Figure 3 7 4 Set up procedure of controlling power using wait mode 3 RENESAS 361 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications MEMO 362 stENESAS Renesas Technology Corp Chapter 4 Interrupt Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 Overview of Interrupt 4 1 1 Type of Interrupts Figure 4 1 1 lists the types of interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction I
180. H abs16 ROH abs16 A1 7 11 SB 1000 8 MOV B S OR B S SUB B S CMP B S BSET S MUL B ROH ROL ROH ROL ROH ROL ROH ROL 0 11 SB src dest 1001 9 MOV B S OR B S SUB B S CMP B S BSET S MUL W dsp 8 SB ROL dsp 8 SB ROL dsp 8 SB ROL dsp 8 SB ROL 1 11 SB src dest 1010 A MOV B S OR B S BSET S BTST S CODE_7A dsp 8 FB ROL dsp 8 FB ROL dsp 8 FB ROL dsp 8 FB ROL 2 11 SB 2 11 SB 1011 B MOV B S OR B S SUB B S CMP B S BSET S BTST S JN CODE_7B abs16 ROL abs16 ROL abs16 ROL abs16 ROL 3 11 SB 3 11 SB abel 1100 Cc MOV B S OR B S SUB B S CMP B S BSET S BTST S TU NC CODE_7C ROL ROH ROL ROH ROL ROH ROL ROH 4 11 SB 4 11 SB abel 1101 D MOV B S OR B S SUB B S CMP B S BSET S BTST S JLEU CODE_7D dsp 8 SB ROH dsp 8 SB ROH dsp 8 SB ROH dsp 8 SB ROH 5 11 SB 5 11 SB abel 1110 E MOV B S OR B S BSET S BTST S JNE JNZ CODE_7E dsp 8 FB ROH dsp 8 FB ROH dsp 8 FB ROH dsp 8 FB ROH 6 11 SB 6 11 SB abel 1111 F MOV B S OR B S SUB B S CMP B S BSET S abs16 ROH abs16 ROH abs16 ROH abs16 ROH 7 11 SB CODE_74 STE MOV PUSH NEG ROT NOT LDE POP SHL SHA CODE_75 STE MOV PUSH NEG ROT NOT LDE POP SHL SHA CODE_76 TST XOR AND OR ADD SUB ADC SBB CMP DIVX ROLC RORC DIVU DIV ADCF ABS CODE_77 TST XOR AND OR ADD SUB ADC SBB CMP DIVX ROLC RORC DIVU DIV ADCF ABS CODE_7A XCHG LDC CODE_7B XCHG STC CODE_7C MOV Dir MULU MUL EXTS STC DIVU DIV PUSH DIVX DADD DSUB DADC DSBB SMOVF SMOVB SSTR ADD LDCTX RMPA ENTER CODE_7D JMPI JSRI MULU MUL PUSHA LDIPL ADD J Cnd BMCnd DIVU DI
181. HIP 16 BIT CMOS MICROCOMPUTER Power Saving Power Saving There are three power save modes 1 Normal operating mode e High speed mode In this mode one main clock cycle forms BCLK The CPU operates on the BCLK The peripheral functions operate on the clocks specified for each respective function e Medium speed mode In this mode the main clock is divided into 2 4 8 or 16 to form BCLK The CPU operates on the BCLK The peripheral functions operated on the clocks specified for each respective function Low speed mode In this mode fc forms BCLK The CPU operates on the fc clock fc is the clock supplied by the subclock The peripheral functions operate on the clocks specified for each respective function Low power dissipation mode This mode is selected when the main clock is stopped from low speed mode The CPU operates on the fc clock fc is the clock supplied by the subclock Only the peripheral functions for which the subclock was selected as the count source continue to run 2 Wait mode CPU operation is halted in this mode The oscillator continues to run 3 Stop mode All oscillators stop in this mode The CPU and internal peripheral functions all stop Of all 3 power saving modes power savings are greatest in this mode Figure 1 20 shows the transition between each of the three modes 1 2 and 3 stENESAS Renesas Technology Corp 20 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CM
182. If an interrupt occurs during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence In the interrupt sequence the processor carries out the following in sequence given 1 CPU gets the interrupt information the interrupt number and interrupt request level by reading address 0000016 After this the corresponding interrupt request bit becomes 0 2 Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in the temporary register Note within the CPU 3 Sets the interrupt enable flag I flag the debug flag D flag and the stack pointer select flag U flag to O the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed 4 Saves the content of the temporary register Note within the CPU in the stack area 5 Saves the content of the program counter PC in the stack area 6 Sets the interrupt priority level of the accepted instruction in the IPL After the interrupt sequence is completed the processor resumes executing instructions from the first address of the interrupt routine Note This register cannot be utilized by the user Interrupt Response Time Interrupt response time is the period between the instant an interrupt occurs and the instant the first instruction within the inter
183. Indeterminate Function i The watchdog timer is initialized and starts counting after a write instruction to this register The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written Figure 1 35 Watchdog timer control and start registers stENESAS 47 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer Timer There are six 16 bit timers These timers can be classified by function into timer A one timers B two and timers X three All these timers function independently Figure 1 36 show the block diagram of timers Clock prescaler gt fi 2 i XCIN 1 32 m MO Clock prescaler reset flag bit 7 Reset f32 at address 038116 set to 1 f1 f8 f32 fc32 XIN Timer mode One shot mode PWM mode Timer AO C m eee O e Event counter mode Timer mode One shot mode PWM mode e Pulse width measuring mode Event counter mode Timer XO TXOINOUT Timer mode One shot mode PWM mode e Pulse width measuring mode e Event counter mode Timer X1 TX1INOUT Timer mode One shot mode PWM mode e Pulse width measuring mode Timer X2 TX2INOUT e Event counter mode Timer mode e e Pulse width measuring mode N J Timer BO O e Event counter mode Timer mode Pulse width mea
184. Item Specification Count source f1 f8 f32 fC32 Count operation e Down counts operating as an 8 bit or a 16 bit pulse width modulator The timer reloads a new count at a rising edge of PWM pulse and continues counting The timer is not affected by a trigger that occurs when counting 16 bit PWM H level width n fi n Set value Cycle time 218 1 fi fixed 8 bit PWM H level width nx m 1 fi n values set to timer Xi register s high order address Cycle time 28 1 m 1 fi m values set to timer Xi register s low order address Count start condition The timer overflows The count start flag is set 1 Count stop condition The count start flag is reset 0 Interrupt 8 bits PWM Set value of H level width is except FF16 0016 PWM pulse goes L request Set value of H level width is FF 16 0016 Timing that count value goes to 0116 generation 16 bits PWM Set value of H level width is except FFFF16 000016 PWM pulse goes L timing Set value of H level width is FFFF16 000016 Timing that count value goes to 000116 TXiINOUT pin function Pulse output Read from timer When timer Xi register is read it indicates an indeterminate value Write to timer e When counting stopped When a value is written to timer Xi register it is written to both reload register and counter When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload t
185. LE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 7 Operation of Timer X one shot timer mode In one shot timer mode choose functions from those listed in Table 2 4 6 Operations of the circled items are described below Figure 2 4 14 shows the operation timing and Figure 2 4 15 shows the set up procedure Table 2 4 6 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input falling edge of input signal to the TXiINOUT pin External trigger input rising edge of input signal to the TXiiINOUT pin Timer overflow TB1 TX0 TXi overflow Writing 1 to the one shot start flag Operation 1 Setting the one shot start flag to 1 with the count start flag set to 1 causes the counter to perform a down count on the count source At this time the TXiINOUT pin outputs an H level 2 The instant the value of the counter becomes 000016 the TXiINOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer Xi interrupt request bit goes to 1 3 If a trigger occurs while a count is in progress the counter reloads the value in the reload register again and continues counting The reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to
186. N channel open drain output Must always be 0 Transfer format select bit 0 LSB first ane 1 MSB first Must always be 0 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Serial I O UARTI transmit receive control register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset UiC1 i 0 1 03A516 03AD16 0216 Function Note 1 Bit Function eigenen tit min ees enable bit Transmission disabled n Transmission disabled Transmission enabled Transmission enabled ills buffer 0 Data present in 0 Data present in empty flag transmit buffer register transmit buffer register 1 No data present in 1 No data present in transmit buffer register transmit buffer register Receive complete flag 0 No data present in 0 No data present in receive buffer register receive buffer register Data present in 1 Data present in receive buffer register receive buffer register Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 If you are using clock asynchronous serial I O mode you can enable receive enable bit when RxD port input is H If RxD port input is L and you have enabled receive enable bit then receive operation starts immediately UART transmit receive control register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address
187. NGLE CHIP 16 BIT CMOS MICROCOMPUTER UART Continued from the previous page Setting UARTO bit rate generator b7 b0 TLLLILIL I UARTO bit rate generator Address 03A116 03A916 UOBRG pe E be set to 0016 to FF16 Note 1 Note 1 Write to UARTIi bit rate generator when transmission reception is halted Reception enabled b7 b0 f F UARTO transmit receive control register 1 UOC1 Address 03A516 Pit UART1 transmit receive control register 1 U1C1 Address 03AD16 Receive enable bit 1 Reception enabled Note 2 Set the corresponding port direction register to 0 input mode Start reception Checking completion of reception b7 bO aaa aan UARTO transmit receive control register 1 UOC1 Address 03A516 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register Checking error b0 UARTO receive buffer register Address 03A716 03A616 UORB Receive data Overrun error flag 0 No overrun error 1 Overrun error found Framing error flag 0 No framing error 1 Framing error found Parity error flag 0 No parity error 1 Parity error found Error sum flag 0 No error 1 Error found Processing after reading out reception data Figure 2 6 11 Set up procedure of reception in UART mode 2 2tENESAS 283 Renesas Technology Corp Mitsubishi microcomputers M30201 G
188. NT instruction Software Interrupt Reset DBC Special J Watchdog timer Single step Address matched Hardware Peripheral I O Note Note Peripheral I O interrupts are generated by the peripheral functions built into the microcomputer system Figure 4 1 1 Classification of interrupts e Maskable interrupt An interrupt which can be enabled disabled by the interrupt enable flag I flag or whose interrupt priority can be changed by priority level e Non maskable interrupt An interrupt which cannot be enabled disabled by the interrupt enable flag I flag or whose interrupt priority cannot be changed by priority level 364 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 2 Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag O flag set to 1 The following are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB BRK interrupt A BRK interrupt occurs when executing the BRK instruction INT interrupt An INT interrupt occurs when assiging one o
189. Note 2 Note 2 Set the corresponding port direction register to 0 input mode a Setting one shot timer s time b15 b8 b7 b0 b7 bo ie Ke S Can be set to 000116 to FFFF16 Timer AO register Address 038716 038616 TAO Setting clock prescaler reset flag b7 b0 L POPPP PTA Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 Setting count start flag b7 b0 LTT X LL Timer AO count start flag Count start flag Address 038016 TABSR Start count Figure 2 2 23 Set up procedure of one shot mode external trigger selected 2tENESAS Renesas Technology Corp 197 Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 11 Operation of Timer A pulse width modulation mode 16 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 2 11 Operations of the circled items are described below Figure 2 2 24 shows the operation timing and Figure 2 2 25 shows the set up procedure Table 2 2 11 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count s
190. OS MICROCOMPUTER Power Saving 26 Transition of stop mode wait mode Reset All oscillators stopped a lt WAIT CPU operation stopped CMi0 1 Medium speed mode insiruction p Stop mode ae Wait mode eee y Interrupt divided by 8 mode _ Interrupt wO ER All oscillator interru ji war CPU operation d 24 High speed medium Hnstruction Stop mode 4M0 Wait mode K SIOP MOSR speed mode _ Interrupt Neo R t WAIT C d Stop mode 4 amp Low speed iow power pinstuotion gt Wait mode Interrupt dissipation mode _ Interrupt Normal mode a Refer to the following for the transition of normal mode Transition of normal mode Main clock is oscillating Sub clock is stopped Medium speed mode divided by 8 mode CMO6 1 BCLK f Xin 8 CM07 0 CMO06 1 CM07 0 Note 1 ae gn CMO06 1 Main clock i illatin 0 CM04 1 ine ain clock is oscillating CM04 of i 9 Sub clock is oscillating Fo Medium speed mode divided by 2 mode BCLK f Xin 2 CM07 0 CM06 CM17 0 CM16 High speed mode BCLK f Xin CM07 0 CM06 CM17 0 CM16 Medium speed mode divided by 8 mode BCLK f Xin 8 CM07 0 0 0 0 CM07 0 Note 1 3 gt E _ _ _ _ _ BCLK f XciN CM07
191. OWER XCOUT No load LOWPOWER No load LOW output voltage P0o to P07 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 L 5mA LOW output voltage POo to P07 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 L 200 pA LOW output voltage HIGHPOWER P1o to P17 L 15mA LOWPOWER L 5mA LOW output voltage HIGHPOWER L 200 pA Pio to P17 LOWPOWER L 200 pA LOW output voltage Xout HIGHPOWER H 1 mA LOWPOWER H 0 5 mA LOW output voltage HIGHPOWER No load LOWPOWER No load Hysteresis TAON TXONOoUT TX1INOUT T X2INOUT TBOIN TB11N INTo INT1 CLKo KT0 to KI7 RxDo RxD1 Hysteresis RESET HIGH input current POo to P07 P 10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 RESET CNVss LOW input current POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 RESET CNVss RPULLUP Pull up resistor POo to P07 P 10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 RXIN Feedback resistor XIN RXCIN Feedback resistor XCIN VRAM RAM retention voltage When clock is stopped Note 1 Unless otherwise noted Vcc 5V Vss OV at Ta 20 to 85 C f XIN 10MHz Power supply current f Xin 10MHz Square wave no division f XCIN 32kHz VO pin Square wave has no__ f XCIN 32kHz load When a WAIT instru
192. R Address 03A016 Must be fixed to 001 Internal external clock select bit 1 External clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Sleep select bit Must be 0 in clock synchronous I O mode Setting UARTi transmit receive control register 0 i 0 to 2 b7 b0 UARTO transmit receive control register 0 aloj Lal L taco address osaaig ner BRG count source select bit Invalid when external clock is selected Must be 0 in clock synchronous I O mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in clock synchronous I O mode Data output select bit 0 TxDo pin is CMOS output 1 TxDo pin is N channel open drain output CLK polarity select bit Note 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note Set the corresponding port direction register to O input mode 7 Setting UART transmit receive control register 2 b7 b0 m UART transmit receive control register 2 ATT Jo 0 UCON Address 03B016 Must be 0 in clock synchronous I O mode UARTO continuous receive mode enable bit 0 Continuous receive mo
193. Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office
194. Renesas Technology Corp Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 15 Precautions for Timer A one shot timer mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 Setting the count start flag to 0 while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TAOOUT pin outputs L level e The interrupt request generated and the timer AO interrupt request bit goes to 1 3 The output from the one shot timer synchronizes with the count source generated internally Therefore when an external trigger has been selected a delay of one cycle of count source as a maximum occurs between the trigger input to the TAOIN pin and the one shot timer output 4 The timer AO interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode Changing operation mode from event counter mode to one shot timer mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to 0 after the above listed changes have been made 5 If a trigger occurs while a count is in progress after the counter performs one down count following the re
195. SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version Clear Status Register Command This command clears the bits SR3 SR4 which are set when the status register operation ends in error When the 5016 command code is sent with the 1st byte the aforementioned bits are cleared When the clear status register operation ends the P53 BUSY signal changes from the H to the L level CLKO RxDO 5016 M16C reception data TxDO M16C transmit data P53 BUSY Figure 1 109 Timing for clearing the status register Page Program Command This command writes the specified page 256 bytes in the flash memory sequentially one byte at a time Execute the page program command as explained here following 1 Transfer the 4116 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 From the 4th byte onward as write data Do D7 for the page 256 bytes specified with addresses As to A23 is input sequentially from the smallest address first that page is automatically written When reception setup for the next 256 bytes ends the P53 BUSY signal changes from the H to the L level The result of the page program can be known by reading the status register For more information see the section on the status register Rapo Ane his A aea hotan f datas M16C reception data A15 J
196. SR Timer X0 event trigger select bit b3 b2 TB1 overflow is selected TAO overflow is selected TX1 overflow is selected X1 event trigger select bit TB1 overflow is selected TXO overflow is selected TX2 overflow is selected X1 event trigger select bit TB1 overflow is selected TX1 overflow is selected TAO overflow is selected XN Setting PWM pulse s H level width b15 b8 b7 bO b7 Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFE16 gt Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 KKK Sire prescaler reset flag Address 038116 PSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 A Setting count starts flag b7 bo Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 21 Set up procedure of pulse width modulation mode 16 bit PWM mode selected 2tENESAS 241 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER
197. See Figure 1 103 for an example of a programming flowchart RENESAS 139 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version Program verify command C016 The program verify mode is entered by writing the command code C016 in the first bus cycle and the verify data is output from the data I O pins Do D7 in the second bus cycle Erase command 2016 2016 The flash memory control circuit executes an erase operation by writing command code 2016 in the first bus cycle and the same command code again in the second bus cycle The erase operation requires approximately 20 ms Wait for 20 ms or more before the user go to the next processing Before this erase command can be performed all memory locations to be erased must have had data 0016 written to by using the program and program verify commands Note 1 The erase operation is not completed immediately by writing an erase command once The user must always execute an erase verify command after each erase command executed And if verification fails the user need to execute the erase command repeatedly until the verification passes See Figure 1 103 for an example of an erase flowchart Erase verify command A016 The erase verify mode is entered by writing the command code A016 in the first bus cycle and the verify data is output from the data I O pins D
198. Set the CPU rewrite mode select bit to 1 4 Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled 5 Execute operation on the flash memory by writing software commands to the flash command regis ter Note 1 In addition to the above various other operations need to be performed such as for entering the data to be written to flash memory from an external source e g serial I O initializing the ports and writing to the watchdog timer lt Clearing procedure gt 1 Apply Vss to the CNVSs VPP pin 2 Set the CPU rewrite mode select bit to O 128 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Flash memory version Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode 1 Operation speed During erase program mode set BCLK to 5 MHz or less by changing the divide ratio 2 Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 3 Interrupts inhibited against use No interrupts can be used that look up the fixed vector table in the flash memory area Maskable interrupts may be used by setting the interrupt vector tab
199. Set this bit to 0 Di a 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected o0 Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 AN50 to AN54 can be used in the same way as for ANo to AN4 Note 3 If port P5 group is selected the contents of A D registers 5 to 7 are indeterminate If port P5 group is selected do not select 8 pins sweep mode Figure 2 7 3 A D converter related registers 2 288 CENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 2 Note b7 b6 b5 b4 b3 b2 bl b0 Symbol Address When reset ONN ofo of ADCON2 03D416 XXXX00002 Bi symbol AW SMP A D conversion method 0 Without sample and hold select bit 1 With sample and hold Reserved bit Always set to 0 Nothing is assigned iss i In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D register i Symbol Address When reset ADi i 0 to 7 03C016 to 03CF16 Indeterminate During 10 bit mode Two high order bits of A D conversion result e During 8 bit mode The value if read turns out to be indeterminate ee manam m os errre Nothing is assigned In an at
200. Set this bit to O CLK CLKS select bit 0 CLKMD1 CLK CLKS select bit 1 Note 2 Valid when bit 5 1 0 Clock output to CLK1 1 Clock output to CLKS1 0 Normal mode CLK output is CLKO only 1 Transfer clock output from multiple pins function selected Nothing is assigned Function During UART mode Transmit buffer empty Tl 1 Transmission completed TXEPT 1 Transmit buffer empty Tl 1 Transmission completed TXEPT 1 Must always be 0 Must always be 0 In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 When using multiple pins to output the transfer clock the following requirements must be met e UARTO internal external clock select bit bit 3 at address 03A016 0 Figure 2 6 5 UARTi related registers 3 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 6 2 Operation of Serial I O transmission in UART mode In transmitting data in UART mode choose functions from those listed in Table 2 6 4 Operations of the circled items are described below Figure 2 6 6 shows the operation timing and Figures 2 6 7 and 2 6 8 show the set up procedures Table 2 6 4 Choosed functions Transfer clock Internal clock f1 fs f32 fc source Ext
201. Timer X 2 4 11 Operation of Timer X pulse width modulation mode 8 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 4 10 Operations of the circled items are described below Figure 2 4 22 shows the operation timing and Figure 2 4 22 shows the set up procedure Table 2 4 10 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition Timer overflow TB1 TAO TXi overflow Operation 1 Selected timer overflow is generated with the count start flag set to 1 the counter performs a down count on the count source Also the TXiINOUT pin outputs an H level 2 The TXiINOUT pin output level changes from H to L when a set time period elapses At this time the timer Xi interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TXiOUT pin outputs an L level Note e PWM pulse cycle is m 1 x 28 1 fi whereas H level duration is n x m 1 fi However when 0016 is set for the significant 8 bits of the timer AO register the PWM output is L level for the entire period and an interrupt request is generated for every PWM output cycle Also
202. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry CENESAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is grant
203. UU ny AD e a Set to 1 by ca Cleared to 0 by software conversion start flag A D register 0 X Result A D register 1 X Result A D register 2 y Result Note When AD frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 AD cycles for 8 bit resolution and 59 AD cycles for 10 bit resolution Figure 2 7 14 Operation timing of repeat sweep 1 mode 298 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold b7 b0 0 oli A D control register 2 Address 03D416 OA ADconz L A D conversion method select bit 1 With sample and hold Must be fixed to 0 J S Setting A D control register 0 and A D control register 1 b7 b0 b7 bo A D control register 0 Address 03D616 A D control register 1 Address 03D716 ADCONO ADCON1 Invalid in repeat sweep mode 1 A D sweep pin select bit Note 2 b1 bo 00 ANo 1 pins 0 1 ANo AN1 2 pins j 1 0 ANo to AN2 3 pins Must be fixed to 0 1 1 ANo to AN3 4 pins Repeat sweep mode 1 is selected Note 1 A D ope
204. V PUSH DIVX DADD DSUB DADC DSBB SMOVF SMOVB SSTR STCTX RMPA EXITD WAIT CODE_7E BTSTC BM Crd BNTST BAND BNAND BOR BNOR BCLR BSET BNOT BTST BXOR BNXOR CODE_EB SHL FSET FCLR MOVA LDC SHA PUSHC POPC INT stENESAS Renesas Technology Corp 398 Appendix 2 Hexadecimal instruction CODE table Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Renesas Technology Corp D7 to D4 1000 1001 1010 1011 1100 1101 1110 1111 D3 to DO 8 9 A B Cc D E F 0000 0 TST B AND B G ADD B G ADC B CMP B G CMP B Q ROT B SHA B src dest src dest src dest src dest src dest IMM dest IMM dest IMM dest 0001 1 TST W AND W G ADD W G ADC w CMP W G CMP W Q ROT W SHA W src dest src dest src dest src dest src dest IMM dest IMM dest IMM dest 0010 2 PUSH B S POP B S MOV W S INC W PUSH W S POP W S MOV B S DEC W ROL ROL IMM AO AO AO AO IMM AO AO 0011 3 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S RTS IMM8 ROH IMM8 ROH ROH 0 ROH IMM8 ROH IMM8 ROH IMM8 ROH 0100 4 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S JMP W IMM8 ROL IMM8 ROL ROL 0 ROL IMM8 ROL IMM8 ROL IMM8 ROL label 0101 5 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S JSR W IMM8 dsp 8 SB IMM8 dsp 8 SB dsp 8 SB 0 dsp 8 SB IMM8 dsp 8 SB IMM8 dsp 8 SB IMM8 dsp 8 SB label 0110 6 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S INTO IMM
205. When reset UCON 03B016 XX0000002 Bit Function symbol Bit During clock synchronous y name serial I O mode UOIRS UARTO transmit 0 Transmit buffer empty 0 Transmit buffer empty interrupt cause select bit CM o Tl 1 1 Transmission completed 1 rison completed TXEPT 1 TXEPT 1 UART1 transmit Set this bit to 0 0 Transmit buffer empty interrupt cause select bit Tl 1 1 Transmission completed TXEPT 1 UARTO continuous Continuous receive Must always be 0 receive mode enable bit mode disabled Continuous receive mode enable Set this bit to O CLKMDO CLK CLKS select bit 0 Valid when bit 5 1 Must always be 0 0 Clock output to CLK1 1 Clock output to CLKS1 CLKMD1 CLK CLKS select 0 Normal mode Must always be 0 bit 1 Note 2 CLK output is CLKO only 1 Transfer clock output from multiple pins function selected Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 When using multiple pins to output the transfer clock the following requirements must be met UARTO internal external clock select bit bit 3 at address 03A016 0 Figure 1 73 Serial l O related registers 3 tENESAS 79 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clo
206. Writing next transmit data b8 bO b7 0 UARTO transmit buffer register Address 03A316 03A216 UOTB UART1 transmit buffer register Address 03AB16 O3AA16 U1TB Setting transmission data peceauasuseuaessrssssesaessrsssssssessrssss gg Jransmission is complete Figure 2 6 8 Set up procedure of transmission in UART mode 2 2tENESAS 279 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 6 3 Operation of Serial I O reception in UART mode In receiving data in UART mode choose functions from those listed in Table 2 6 5 Operations of the circled items are described below Figure 2 6 9 shows the operation timing and Figures 2 6 10 and 2 6 11 show the set up procedures Table 2 6 5 Choosed functions Transfer clock Internal clock f1 fs f32 fc source External clock CLKO pin Note Sleep mode Sleep mode off Sleep mode selected Note UART1 cannot be selected external clock Operation 1 Setting the receive enable bit to 1 readies data receivable status 2 When the first bit the start bit of reception data is received from the RxDi pin Then data is received bit by bit in sequence LSB MSB and stop bit s 3 When the stop bit s is are received the content of the UARTIi receive register is transmitted to the UARTIi receive buffer register At this time the receive complete flag goe
207. X One shot start flag Symbol Aiae henresei b7 b6 b5 b4 b3 b2 bi bO ONSF 038216 XXXX00002 When read the value is 0 Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Trigger select register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TRGSR 038316 0016 Timer AO event trigger oe select bit 99 Input on TAON is selected Note TB1 overflow is selected TAOTGH TX2 overflow is selected TXO overflow is selected Timer XO event trigger TXoTGL select bit a Input on TXOINOUT is selected Note TB1 overflow is selected TXOTGH TAO overflow is selected TX1 overflow is selected TXITGL ae a eventtrigger Input on TX1INouT is selected Note TB1 overflow is selected TX1TGH TXO overflow is selected TX2 overflow is selected TX2TGL Timer X2 event trigger select bit Input on TX2iNouT is selected Note TB1 overflow is selected TX2TGH TX1 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 bS b4 b3 b2 bi bo Symbol Address When reset CPSRF 038116 OXXXXXXX2 r Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate 0 No effect 1 Prescaler is reset When read the value is 0 Clock prescaler reset flag Figure 1 59 T
208. X 2 1 i i Count source e air TAOIN pin a i aa N input signal i Trigger is not generated by this signal Set to 1 by software Cleared to 0 7 l by software Count start flag 1 Start count 2 Output level H to L 3 One period is complete k 1 fiX n 4 Stop count PWM pulse output from TAOOUT pin Cleared to 0 when interrupt request is Timer AO interrupt 1 accepted or cleared by software request bit g Note n 000016 to FFFE16 Figure 2 2 24 Operation timing of pulse width modulation mode 16 bit PWM mode selected 198 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting PWM mode and functions i bo Timer AO mode register Address 039616 Selection of PWM mode 1 Must always be 1 in PWM mode External trigger select bit 1 Rising edge of TAOIN pin s input signal Note 1 Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 0 Functions as a 16 bit pulse width modulator Count source select bit Count Count source period b7 b6 3 SOUICE f Xin 10MHz f Xcin 32 768kHz 00 f 100ns 01 fat 0 f321 800ns 1 fc32 3 2us 976 56us Note 1 Set the corresponding port direction register which outputs the pulse to 1 output mode Clearing timer AO in
209. a 10 MHz oscillator to XIN Operation 1 Setting the count start flag to 1 causes the counter to begin counting The counter of timer XO performs a down count on count source f1 2 If the counter of timer XO underflows the counter reloads the content of the reload register and continues counting At this time the timer XO interrupt request bit goes to 1 The counter of timer X1 performs a down count on underflows in timer XO 3 If the counter of timer X1 underflows the counter reloads the content of the reload register and continues counting At this time the timer X1 interrupt request bit goes to 1 Timer XO counter content hex ka o 2 E Q ta x lt ks oO E H content hex Timer XO count start flag Timer X1 count start flag Timer XO interrupt 1 o request bit FFFF16 reload register content n reload register content i Start count i Set to 1 by software 1 Start count 2 Timer X0 underflow 3 Timer X1 underflow Cleard 0 by software __ Time m E Set to 1 by software p wN A Cleared to 0 when interrupt request is accepted or cleared by software pans Timer X1 interrupt 1 o request bit Figure 3 1 1 Operation timing of long period timers a 338 stENESAS Renesas Technology Corp Mits
210. a program into the flash memory which already has the ID code set for these addresses neces SE a eel ees OFFFDC16 to OFFFDF 16 ID1 Undefined instruction vector OFFFEO16 to OFFFE316 ID2 Overflow vector OFFFE416 to OFFFE716 i BRK instruction vector OFFFE816 to OFFFEB16 ID3 Address match vector OFFFEC16 to OFFFEF16 ID4 Single step vector OFFFF016 to OFFFF316 ID5 Watchdog timer vector OFFFF416 to OFFFF716 ID6 DBC vector OFFFF816 to OFFFFB16 ID7 OFFFFC16 to OFFFFF16 Reset vector Figure 1 130 ID code storage addresses 166 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Baud Rate 9600 This command changes baud rate to 9 600 bps Execute it as follows 1 Transfer the B016 command code with the 1st byte 2 After the B016 check code is output with the 2nd byte change the baud rate to 9 600 bps RxDO M16C reception data TxDO M16C transmit data Figure 1 131 Timing of baud rate 9600 RENESAS 167 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Baud Rate 19200 This command changes baud rate to 19 200 bps Execute it as follows 1 Transfer the B116 command code with the 1st byte 2 After the B116 ch
211. abled When either the IPL or the interrupt priority level is changed the new level is reflected to the interrupt in the following timing e When changing the IPL using the REIT instruction the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction e When changing the IPL using either the POPC LDC or LDIPL instruction the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used e When changing the interrupt priority level using the MOV or similar instruction the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used 372 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 2 4 Rewrite the interrupt control register To rewrite the interrupt control register do so at a point that does not generate the interrupt request for that register If there is possibility of the interrupt request occur rewrite the interrupt control register after the interrupt is disabled The program examples are described as follow Example 1 INT_SWITCH1 FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit NOP Four NOP instructions are required when using HOLD
212. acity select bit 1 HIGH Main clock XIN XOUT stop bit 0 On e XIN 1 m XIN 2 A XIN 4 XIN 8 e XIN 16 5 6 f XIN MHz Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figures 5 1 8 Standard characteristics of ICC f XIN Vcc 3V 390 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics 5 2 Standard Characteristics of Pull Up Resistor Figure 5 2 1 shows an example of the standard characteristics of the pull up resistor The standard character istics given in this section are examples of M30201M4 XXXFP The contents of these examples cannot be guaranteed For standardized values see Electric characteristics 2 VI V Note Data described here are characteristic examples The data values are not guaranteed Figure 5 2 1 Example of the standard characteristics of the pull up resistor RENESAS 391 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version 5 3 Standard DC Characteristics Flash memory version The standard characteristics given in this section are examples of M30201F6FP The contents of these examples cannot be guaranteed Fo
213. acteristics Table 2 7 7 Relationship of the successive comparison register contents and Vref Successive approximation register n Vref V 0 1 t01023 RENESAS 301 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Table 2 7 8 Variation of the successive comparison register and Vref while A D conversion is in progress 10 bit mode VRE v VREF VREF 1st comparison gt 9048 V no 1 v VREF VREF _ VREF jy A D converter stopped 2nd comparison 0 0 2 t 74 2048 ng y st comparison result 3rd comparison nsl1lololololo VREF VREF VREF _ VREF 2 4 7 204 A ond comparison result 9 uaa VREF VREF VREF VREF VREF i n4 n3 t7024 5048 10th cu 2 4 2048 Conversion complete ng n7 n6 nd n4 n3 n2 n1 no This data transfers to the bit 0 to bit 9 of A D register Result of A D conversion Theoretical A D conversion characteristic Ideal A D conversion characteristic t VREF VREF VREF VREF V 1024 3 1024 1021 1024 1022 1024 X 1028 REF Analog input voltage Figure 2 7 17 Theoretical A D conversion characteristics 10 bit mode 302 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter
214. address 03A416 0 CLKO input level H CLKO polarity select bit bit 6 at address 03A416 1 CLKO input level L Interrupt request e When transmitting generation timing Transmit interrupt cause select bit bit O at address 03B016 0 Interrupts re quested when data transfer from UARTO transfer buffer register to VARTO transmit register is completed Transmit interrupt cause select bit bit O at address 03B016 1 Interrupts re quested when data transmission from UARTO transfer register is completed e When receiving Interrupts requested when data transfer from UARTO receive register to UARTO receive buffer register is completed Error detection e Overrun error Note 2 This error occurs when the next data is ready before contents of UARTO receive buffer register are read out Select function e CLK polarity selection Whether transmit data is output input at the rising edge or falling edge of the trans fer clock can be selected e LSB first MSB first selection Whether transmission reception begins with bit 0 or bit 7 can be selected e Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register e Transfer clock output from multiple pins selection UARTO transfer clock can be chosen by software to be output from one of the two pins set Note 1 n denotes the value 0016 to FF 16 that is set to the UART bit rate generato
215. aeas E 310 2181 OVEIVIOW AE etcetera O E E Ee le a A Ne et a 310 2 8 2 Operation of Watchdog TimMer eccccceeceeeeeeeeeeeeeeeeeeeeeeeaeeeceeeeeceaeeseeeeeesaeeegeaeeeeneeeeeeeeee 312 2 9 Address Mateh MEUPE i sccsezcshectenbe coved eats avin te decteghleteeeethols eeblawslercuieeoescceevenieh rovteetheriedanastuederees 314 Z9 AVOVEIVIOW ects cas cet a pathic ated naatata gaat caayues tae aaaea aa ea a a aa aaa 314 2 9 2 Operation of Address Match Interrupt eccccceseeeeeeeeeeeeeeeeeeeeeaeeeeeeeeesaeeeeeneeeeeeeeseeeeee 316 2 10 Key Input Interrupt 22 22 cccesccceceeeeseceeeeeeeeeeeeeeesaeceeeeesaaeceeeeeaseceeeeessaeeeeeessageceeeessseceaensnseeeeenentiaes 318 21034 OVGRVIGW paceenk cad ieeka ti cebesd be ceectbe beware sentipies tend decades EE A 318 2 10 2 Operation of Key Input Interrupt 20 2 cceceeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeaeeeeeeeeesaeeeseneeeseaeeeeeaeeeee 320 Ar POwWer CONTO n seen tee Meehan ees eee Maat eA eae eh bd ce le ue due 322 PAEO TEA AE Perea E ec orcerescorne tr acrecen reer a T 322 22412 Stop Mode Set U D a e re aTa dacat te sede gh aaa r E aa aa E aE Aa EEE AOE EEE Aa EEEE yeas 327 2 11 3 Wait Mode Set Up essssssssssssesssnsssnessnnessnsosnnsssnsssnnsstessensssteseensconaccsnaconnnotnnorenstnnnstensseene 328 2 11 4 Precautions in Power Control ccccccecceeeeeeeeeeceeeeeeeeeceaaeseceeeeseaaeeeseeeeseeaeeeseaeeseeeeeseaaeeee 329 2 12 Programmable I O Pons c cccsceeeeeeeeeeeeeeeeeeeeeeaeee
216. ain clock becomes the BCLK The CPU operates according to the BCLK selected Each peripheral function operates according to its assigned clock Low speed mode fc becomes the BCLK The CPU operates according to the fc clock The fc clock is supplied by the secondary clock Each peripheral function operates according to its assigned clock e Low power consumption mode The main clock operating in low speed mode is stopped The CPU operates according to the fc clock The fc clock is supplied by the secondary clock The only peripheral functions that operate are those with the sub clock selected as the count source b Wait mode The CPU operation is stopped The oscillators do not stop c Stop mode All oscillators stop The CPU and all built in peripheral functions stop This mode among the three modes listed here is the most effective in decreasing power consumption Figure 2 11 1 is the state transition diagram of the above modes 322 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control Transition of stop mode wait mode Reset All oscillators stopped gt WAIT opu operation stopped CM10 1 instruction lt Medium speed mode gt Wai rap tM Ne ay moue Interrupt N divided by 8 T Ne ait made Inorg t CP ration Alloscillators stopped 7 CM10 1 Wen Wait mode speed mode J t WAIT CP lt
217. al I O mode select bit P bt 5 lo o SMD1 100 Transfer data 7 bits long loo 10 1 Transfer data 8 bits long SMD2 110 Transfer data 9 bits long CKDIR Internal external clock 0 Internal clock Note 2 select bit Note 1 1 External clock Note 3 STPS Stop bit length select bit 0 One stop bit 1 Two stop bits PRY Odd even parity Valid when bit 6 1 ed select bit 0 Odd parity 1 Even parity PRYE Parity enable bit 0 Parity disabled 1 Parity enabled SLEP Sleep select bit 0 Sleep mode deselected 1 Sleep mode selected Note 1 UART1 can use only internal clock Must set this bit to 1 Note 2 Set the corresponding port direction register to 1 output mode Note 3 Set the corresponding port direction register to O input mode Figure 1 79 UARTi transmit receive mode register in UART mode Table 1 28 lists the functions of the input output pins during UART mode Note that for a period from when the UARTIi operation mode is selected to when transfer starts the TxDi pin outputs a H If the N channel open drain is selected this pin is in floating state Table 1 28 Input output pin functions in UART mode Pin name Function Method of selection TxDi Serial data output Port P51 and P42 direction register bit 0 at address 03EB16 bit 0 at P50 P40 address 03EA16 1 Can be used as an input port when performing reception only RxDi Serial data input Port P51 and P42 di
218. al clock is input to the CLKO pin 3 In receiving data in succession an overrun error occurs when the next reception data is made ready in the UARTO receive register with the receive complete flag set to 1 before the content of the UARTO receive buffer register is read and overrun error flag is set to 1 In this instance the next data is written to the UARTO receive buffer register so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again If an overrun error occurs the UARTO receive interrupt request bit does not go to 1 4 To receive data in succession set dummy data in the lower order byte of the UARTO transmit buffer register every time reception is made 5 With an external clock selected perform the following set up procedure with the CLKO pin input level H if the CLK polarity select bit 0 or with the CLKO pin input level L if the CLK polarity select bit 1 1 Set receive enable bit to 1 2 Set transmit enable bit to 1 3 Write dummy data to the UARTO transmit buffer register tENESAS 267 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 6 Clock Asynchronous Serial I O UART 2 6 1 Overview UART handles communications by means of character by character synchronization The transmission side and the recep
219. al unit control registers 1 10 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Memory 038016 Count start flag TABSR 03C016 038116 Clock prescaler reset flag CPSRF 03C116 038216 One shot start flag ONSF 03C216 038316 Trigger select register TRGSR 030316 038416 Up down flag UDF 03C416 038516 03C516 038616 i 03C616 038716 Timer AO TAQ 03C716 038816 i 03C816 o3s916 Timer XO TX0 03C916 038A16 03CA16 038B16 Timer X1 TX1 03CB16 038C16 03CC16 038D16 Timer X2 TX2 03CD16 038E16 Clock divided counter CDC 03CE16 038F16 03CF16 039016 R 03D016 039116 Timer BO TBO 03D116 039216 Timer B1 TB1 bevels 039316 03D316 039416 03D416 A D control register 2 ADCON2 039516 03D516 039616 Timer AO mode register TAOMR 03D616 A D control register 0 ADCONO 039716 Timer XO mode register TXOMR 03D716 A D control register 1 ADCON1 A D register 0 ADO A D register 1 AD1 A D register 2 AD2 A D register 3 AD3 A D register 4 AD4 A D register 5 AD5 A D register 6 AD6 A D register 7 AD7 039816 Timer X1 mode register TX1MR 03D816 039916 Timer X2 mode register TX2MR 03D916 039A16 03DA16 039B16 Timer BO mode register TBOMR 03DB16 039C16 Timer B1 mode register TB1MR
220. alling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Writing 1 to the one shot start flag Operation 1 Setting the one shot start flag to 1 with the count start flag set to 1 causes the counter to perform a down count on the count source At this time the TAOOUT pin outputs an H level 2 The instant the value of the counter becomes 000016 the TAOOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer AO interrupt request bit goes to 1 3 If a trigger occurs while a count is in progress the counter reloads the value in the reload register again and continues counting The reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to O causes the counter to stop and to reload the content of the reload register Also the TAOOUT pin outputs an L level At this time the timer AO interrupt request bit goes to 1 n reload register content g 2 Stop count 1 Start count 3 Start count Start count 4 Stop count F gt e gt gt Reload a Reload Reload Counter content hex Set to 1 by software l i Cleared to 0 by software Sa Count start flag Write signal to H one shot start flag 1 fiX o i
221. alue gt measured value transfer timing Se o eaters Note 1 Note 1 Note 2 Timing at which counter reaches 000016 Count start flag Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi interrupt 1 request bit o 4 Timer Bi overflow flag g cao a aoo o eee ee Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 3 8 Operation timing of pulse period measurement mode 214 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting pulse period pulse width measurement mode and functions Timer Bi mode register i 0 1 Address 039B16 039C 16 TBiMR i 0 1 Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 0 0 Pulse period measurement Interval between measurement pulse falling edge to falling edge Timer Bi overflow flag 0 Timer did not overflow 1 Timer has overflowed Count source select bit i b7 b6 l Count Count source period 00 f1 source Xin 10MHz_ f Xcin 32 768kHz i he 100ns 1132 1 fc32 800ns 3 2us 976 56us Note Set the corresponding port direction register which sets the measurement pulse to 0 input mode F Setting clock prescaler reset flag
222. alue of the stack pointer SP when interrupt request is acknowledged After registers are saved the SP content is SP minus 4 28 Operation of saving registers 40 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register FLG as it was immediately before the start of interrupt sequence and the contents of the program counter PC both of which have been saved in the stack area Then control returns to the program that was being executed before the acceptance of the interrupt request so that the suspended process re sumes Return the other registers saved by software within the interrupt routine using the POPM or similar in struction before executing the REIT instruction Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling checking whether interrupt requests are made the interrupt assigned a higher priority is accepted Assign an arbitrary priority to maskable interrupts peripheral I O interrupts using the interrupt priority level select bit If the same interrupt priority level is assigned however the interrupt assigned a higher hardware priority is accepted Priorities of the special interrupts such as Reset dealt with as an interrupt a
223. and a clock asynchronous serial O mode UART mode The contents of the serial I O mode select bits bits 0 to 2 at addresses 03A016 and 03A816 determine whether UARTO is used as a clock synchronous serial I O or as a UART UART1 is used as a UART only Figures 1 71 through 1 73 show the registers related to UARTIi UARTO RxDo UART reception Receive Q H Clock source selection S acta i clock Transmit Bit rate generator Clock synchronous type coniro circul receive unit UART transmission Transmit Clock synchronous type o control circuit Clock synchronous type when internal clock is selected O Clock synchronous type Clock synchronous type when internal clock is selected when external clock is A selected CLK o o polarity reversing circuit Clock output pin select switch External UART1 RDI Q Receive Clock source selection Reception clock Transmit f o Bit rate generator control circuit receive unit fg No 1 n 1 fg2 o Transmit issi clock fc o 1 16 Transmission control circuit m Values set to UARTO bit rate generator BRGO n Values set to UART1 bit rate generator BRG1 Figure 1 69 Block diagram of UARTI i 0 1 stENESAS 75 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Serial I O Clock
224. and transfer data format See Table 1 27 Figure 1 79 shows the UARTIi transmit receive mode register Table 1 27 Specifications of UART Mode Item Transfer data format Specification e Character bit transfer data 7 bits 8 bits or 9 bits as selected e Start bit 1 bit e Parity bit Odd even or nothing as selected e Stop bit 1 bit or 2 bits as selected Transfer clock e When internal clock is selected bit 3 at addresses 03A016 03A816 O fi 16 n 1 Note 1 fi f1 fs f32 fc e When external clock is selected bit 3 at addresses 03A016 1 fExT 16 n 1 Note 1 Note 2 Transmission start condition e To start transmission the following requirements must be met Transmit enable bit bit 0 at addresses 03A516 O3AD16 1 Transmit buffer empty flag bit 1 at addresses 03A516 O3AD16 0 Reception start condi tion e To start reception the following requirements must be met Receive enable bit bit 2 at addresses 03A516 03AD16 1 Start bit detection e When transmitting Transmit interrupt cause select bits bits 0 1 at address 03B016 0 Interrupts requested when data transfer from UARTI transfer buffer register to UARTIi transmit register is completed Transmit interrupt cause select bits bits 0 1 at address 03B016 1 Interrupts requested when data transmission from UARTI transfer register is completed e When receiving Interrupts
225. anges from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f XIN 10 MHz T 0 3 us in the A D conversion mode with sample amp hold Output impedance RO for sufficiently charging capacitor C within time T is determined as follows T 0 3 us R 7 8 KQ C 3 pF X 0 1 and Y 1024 Hence 0 3 X 10 R0 7 8 X10834 3 0 X 108 3 0 X 10 In ae 1024 Thus the allowable output impedance of the sensor circuit capable of thoroughly driving the A D con verter turns out to be approximately 3 0 kQ Tables 2 7 11 and 2 7 12 show output impedance values based on the LSB values Microprocessor s inside R 7 8kQ C 3 0pF Figure 2 7 23 A circuit equivalent to the A D conversion terminal 308 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Tables 2 7 11 Relation between output impedance and precision satel of A D converter 10 bit mode Reference value f Xin Cycle Sampling time Resolution e oF 3x o Sample amp hold bit is enabled oh b ol Go N ho NIOJ Go CO NI 2 x cycle Sample amp hold bit is disabled er al 3x ae Sample amp hold bit is enabled Sample a
226. ansmission in clock synchronous serial I O mode In transmitting data in clock synchronous serial I O mode choose functions from those listed in Table 2 5 1 Operations of the circled items are described below Figure 2 5 5 shows the operation timing and Figures 2 5 6 and 2 5 7 show the set up procedures Table 2 5 1 Choosed functions Transfer clock Internal clock f1 fa f32 fc source External clock CLKO pin CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock LSB first MSB first Transmission Transmission buffer empty interrupt factor Transmission complete Output transfer clock Not selected to multiple pins Note PeR Selected Note This can be selected only when UARTO is used in combination with the internal clock Operation 1 Setting the transmit enable bit to 1 and writing transmission data to the UARTO transmit buffer register makes data transmissible status ready 2 In synchronization with the first falling edge of the transfer clock transmission data held in the UARTO transmit buffer register is transmitted to the UARTO transmit register At this time the UARTO transmit interrupt request bit goes to 1 Also the first bit of the transmission data is transmitted from the TxDo pin Then the data is transmitted bit by bit from the lower order in synch
227. ansmit interrupt cause select bit 1 Transmission completed TXEPT 1 Must be 0 in clock synchronous I O mode Must be 0 in clock synchronous I O mode CLK CLKS select bit 0 0 Clock output to CLKO 1 Clock output to CLKS CLK CLKS select bit 1 1 Transfer clock output from multiple pins finction selected Continued to the next page Figure 2 5 9 Set up procedure of transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected 1 260 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Continued from the previous page Setting UARTO bit rate generator b7 bo UARTO bit rate generator Address 03A116 UOBRG DE Can be set to 0016 to FF16 Note Note Write to UARTO bit rate generator when transmission reception is halted Me r Transmission enabled b7 bo EXIDE UARTO transmit receive control register 1 Address 03A516 U0C1 Transmit enable bit 1 Transmission enabled T Writing transmit data b8 b0 b7 UARTO transmit buffer register Address 03A316 03A216 UOTB Setting transmission data A m LLLLLLLLLLLLLLLELTECLLEETTTTELEEETTTETETEETETETEEETETTETTEE Start transmission Checking the status of UARTO transmit buffer register b7 b0 ECX UARTO transmit receive control register
228. are When PWM output is L level for the entire period Writing to the 1 fi X n timer Xi PWM pulse output ees from TXiINOUT pin L i i Timer Xi interrupt request bit Oia Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 4 25 Operation timing of PWM output mode RENESAS 247 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 Clock Synchronous Serial I O 2 5 1 Overview Clock synchronous serial I O carries out 8 bit data communications in synchronization with the clock The following is an overview of the clock synchronous serial I O 1 Transmission reception format 8 bit data 2 Transfer rate If the internal clock is selected as the transfer clock the divide by 2 frequency resulting from the bit rate generator division becomes the transfer rate The bit rate generator count source can be se lected from the following f1 f8 82 and fc Clocks f1 fg and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc is derived by dividing the CPU s sub clock by 1 respec tively Furthermore if an external clock is selected as the transfer clock the clock frequency input to the CLK pin becomes the transfer rate 3 Error detection Only overrun error can be detected Overrun error is an error that occurs when the next data is made rea
229. ared by software Timer Bi overflow flag Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 54 Operation timing when measuring a pulse period Count source Measurement pulse 7 Transfer 4 Transfer Transfer indeterminate measured value measured g measured value f Va A value Pel Reload register counter transfer timing l za A Note 1 A Note 1 Timing at which counter reaches 000016 Count start flag Timer Bi interrupt request bit lt A Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi overflow flag 1 Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 55 Operation timing when measuring a pulse width 64 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Timer X Figure 1 56 shows the block diagram of timer X Figures 1 57 to 1 59 show the timer X related registers Use the timer Xi mode register bits 0 and 1 to choose the desired mode Timer X has the five operation modes listed as follows e Timer mode The timer counts an internal count source e Event counter mode The timer counts pulses from an external source or a timer overflow e One shot timer mode The timer stops counting when the count reaches 000016 e Pulse period pulse width measuring
230. art flag b7 b0 Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Clearing overflow flag a 00 Timer Xi mode register i 0 to 2 Address 039716 to 039916 TT lof txime eo to 2 Timer Xi overflow flag 0 Timer did not overflow Figure 2 4 17 Set up procedure of pulse period measurement mode tENESAS 237 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 9 Operation of Timer X pulse width measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 4 8 Op erations of the circled items are described below Figure 2 4 18 shows the operation timing and Figure 2 4 19 shows the set up procedure Table 2 4 8 Choosed functions Count source Internal count source f1 fs f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to start counting the count source 2 If an effective edge of a pulse to be measured is
231. as Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications P33 I O port P0o Klo Po1 Kh P02 Kl2 P03 KI3 P04 Kl4 POs KI5 P06 Kl6 Hmo Hmo PWD pmo rmo pmo emo Hmo P07 KI7 Figure 3 6 2 Example of circuit of controling power using stop mode tENESAS 355 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications b Initial condition b7 bo Pull up control register 0 7 Address 03FC16 PURO P00 to POs pulled high P04 to P07 pulled high bo Port P3 register 0 Address 03E516 P3 Key scan data Interrupt enable level IPL 0 Interrupt enable flag I 0 Port PO direction register Address 03E216 PDO Key scan input port b7 bo oJofofofofof oo Port P3 direction register Address 03E716 PD3 Key scan output port bo Lh b7 bo Key input interrupt control register WANs Addi 004D DODDI lolol kipe n Interrupt priority level select bit Set higher value than the present IPL Setting interrupt except stop mode cancel Interrupt control register KUPIC ADIC SITIC i SiRIC i TAIIC b7 bo TXiIC
232. ase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing 1 Must always be 1 when using two phase pulse signal processing ________________ Q Must always be 0 when using two phase pulse signal processing Count operation type select bit 1 Free run type Two phase pulse signal processing operation select bit 0 Normal processing operation Note Set the corresponding port direction register which inputs the pulse to O input mode A Two phase pulse signal processing select bit gt bo b7 Up d fl Add 0384 DOE XXL Uptown aa Adress asso Timer AO two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled b7 bO f TT I lool Trigger select register Address 038316 H TRIGGER 00 Must always be 00 when using two phase pulse signal processing Setting divide ratio b8 b0 b7 bO DOOS DO o o OE Timer AO register Address 038716 038616 TAO oo Can be set to 000016 to FFFF16 3 l Z Setting count start flag b7 b0 Count start flag Address 038016 HEBT TABSR Timer AO count start flag Start count Figure 2 2 17 Set up procedure of 2 phase pulse signal process in event counter mode normal mode selected 2tENESAS 191 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A
233. ash version Vcc 4 0V to 5 5V Vss OV Ta 20 to 85 C Extended operating temperature version 40 to 85 C Note 2 The average output current is an average value measured over 100ms Note 3 Keep output current as follows The sum of port P3 and P4 IOL peak is under 40 mA The sum of port P1 IOL peak is under 60 mA The sum of port P1 P3 and P4 IOH peak is under 40 mA The sum of port PO P5 P6 and P7 IOL peak is under 80 mA The sum of port PO P5 P6 and P7 IOH peak is under 80 mA Note 4 Relationship between main clock oscillation frequency and supply voltage Highest operation frequency MHz Main clock input oscillation frequency Without wait 10 0 5 x Vcc 10 000MHz 3 5 0 0 2 7 4 0 5 5 Power supply voltage V Main clock no division 112 stENESAS Renesas Technology Corp Electrical characteristics Vcc 5V Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 38 Electrical characteristics Note1 HIGH ou voltage Parameter POo to P07 P 10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 Measuring condition loH 5mA Vcc 5V Standard Min Typ Max HIGH ou voltage POo to P07 P 10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 loH 200 uA HIGH ou voltage HIGHPOWER XOUT loH 1 mA LOWPOWER loH 0 5 mA HIGH outpu voltage HIGHP
234. assigned a priority higher than the IPL to be accepted Figure 4 6 1 shows the scheme of multiple interrupts An interrupt request that is not accepted because of low priority will be held If the condition following is met when the REIT instruction returns the IPL and the interrupt priority is determined then the interrupt request being held is accepted Interrupt priority level of the interrupt request being held gt Returned the IPL 380 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Interrupt request generated Nesting Reset Wain ouine Interrupt 1 Interrupt priority level 3 Interrupt 2 Multiple interrupts Interrupt priority level 5 Interrupt 3 Interrupt priority level 2 Not acknowledged because of low interrupt priority Main routine instructions are not executed Interrupt enable flag Processor interrupt priority level Automatically executed Be sure to set in software Figure 4 6 1 Multiple interrupts RENESAS 381 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 7 Precautions for Interrupts 1 Reading address 0000016 e When maskable interrupt is occurred CPU read the interrupt information the interrupt number and interrupt request level in the interrupt sequence The interrupt request
235. astic molded SDIP or 56 pin plastic molded QFP These single chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency With 1M bytes of address space they are capable of execut ing instructions at high speed The M30201 group includes a wide range of products with different internal memory types and sizes and various package types Features e Basic machine instructions 4 Compatible with the M16C 60 series e Memory Capacity ceeeeeeseeeeeenes ROM RAM See figure 1 4 ROM expansion e Shortest instruction execution time 100ns f XIN 10MHz e Supply Voltage ccceeeseeeeseeeeeseeeeeees 4 0 to 5 5V f XIN 10MHz mask ROM version 2 7 to 5 5V f XIN 3 5MHz mask ROM version 4 0 to 5 5V f XIN 10MHz flash memory version MtOMrUPt 2 2 2 eee eeeeeeeeeeeeeeeeeeeneeeeeeeeneeees 13 internal and 3 external interrupt sources 4 software including key input interrupt e Multifunction 16 bit timer 00 Timer A x 1 timer B x 2 timer Xx 3 e Clock output Seral LO niseni nnna 1 channel for UART or clock synchronous 1 for UART A D CONVEO corcissciesnin 10 bits X 8 channels Expandable up to 13 channels s Watchdog mMel serisi 1 line e Programmable W O ceeeeeeeeeeteees 43 lines LED drive ports asscciriccirareniia 8 ports e Clock generating Circuit ee 2 built in clock generation circuits built in feedback resistor
236. asuring a pulse period Figure 1 65 shows the operation timing when measuring a pulse width Table 1 23 Timer specifications in pulse period pulse width measurement mode Count source f1 f8 f32 fc32 Count operation e Up count e Counter value 000016 is transferred to reload register at measurement pulse s effective edge and the timer continues counting Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When measurement pulse s effective edge is input Note 1 e When an overflow occurs Simultaneously the timer Xi overflow flag changes to 1 The timer Xi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Xi mode register TXiINOUT pin function Measurement pulse input Read from timer When timer Xi register is read it indicates the reload register s content measurement result Note 2 Write to timer Cannot be written to Note 1 An interrupt request is not generated when the first effective edge is input after the timer has started counting Note 2 The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset I Ja ilo TXMR 0t02 039716t0 039916 002 Bit symbol Function l TMODO Operation mode ee
237. at stENESAS 83 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous serial I O mode c Transfer clock output from multiple pins function This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit bits 4 and 5 at address 03B016 See Figure 1 78 The multiple pins function is valid only when the internal clock is selected for UARTO Microcomputer TxDo P50 CLKS P53 CLKo P52 Note This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I O mode Figure 1 78 The transfer clock output from the multiple pins function usage d Continuous receive mode If the continuous receive mode enable bit bits 2 and 3 at address 03B016 is set to 1 the unit is placed in continuous receive mode In this mode when the receive buffer register is read out the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again 84 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode 2 Clock asynchronous serial I O UART mode The UART mode allows transmitting and receiving data after setting the desired transfer rate
238. bits can only be changed in CPU rewrite mode Protect control address b7 b6 b5 b4 b3 b2 bi bO Symbol Address When shipping FF16 IJ lalah ROMCP FFFFF16 1 1 i tsm Birame Funcion Ey o Reserved bit Always set to 1 oon bs ba Lo ae ee ere ROMCR Protect reset bit 00 Protect removed tat 01 Protect set bit effective it 10 Protect set bit effective i 11 Protect set bit effective b7 b6 1 ROMCP Protect set bit 00 Protect enabled 01 Protect enabled 10 Protect enabled 11 Protect disabled Note 1 When protect is turned on the flash memory version is protected against readout or modification in parallel I O mode Note 2 The protect reset bits can be used to turn off protect However since these bits cannot be changed in parallel I O mode they need to be rewritten in CPU rewrite mode Figure 1 104 Protect control address 142 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode Flash Memory Version SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Pin functions Flash memory standard serial I O mode Description Vcc Vss Power input Apply 5V 10 to Vcc pin and 0 V to Vss pin CNVss CNVss Mode entry pin Apply 12V 5 to this pin RESET Reset input Reset input pin While reset is L level a 20 cycle or longer clock must be input to XIN pin XIN Clock input Connect a ceramic resonator or crysta
239. bl b0 Symbol Address When reset PUR1 03FD16 0016 PU10 P40 to P43 pull up The corresponding port is pulled high with a pull up resistor 1 Pulled high S f S i i Port P1 drive capacity control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset DRR 03FE16 0016 Set P1 N channel output DRRI Port P11 drive capacuty transistor drive capacity 0 LOW 1 HIGH Figure 1 95 Pull up control register tENESAS 105 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Example connection of unused pins Table 1 36 Example connection of unused pins Pin name Connection Ports PO P1 P3 to P7 After setting for input mode connect every pin to Vss pull down or after setting for output mode leave these pins open XouT Note Open AVCC Connect to Vcc AVSss VREF Connect to Vss Note With external clock input to XIN pin 106 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Usage Precaution Timer A timer mode 1 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing gets FFFF16 Reading the timer AO register after setting a value in the timer AO register with a count halted but before t
240. but before the counter starts counting gets a proper value Reload ee oe el Read value Hex f 2 1 oo FFFF p Time n reload register content Figure 2 3 12 Reading timer Bi register 218 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 7 Precautions for Timer B pulse period pulse width measurement mode 1 The timer Bi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Bi is overflowed The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine 2 If the timer overflow occurs simultaneously with the input of a measurement pulse and if the interrupt factor cannot be determined from the timer Bi overflow flag connect the timers and count the number of overflows 3 When reset the timer Bi overflow flag goes to 1 This flag can be set to 0 by writing to the timer Bi mode register when the count start flag is 1 4 Use the timer Bi interrupt request bit to detect only overflows Use the timer Bi overflow flag only to determine the interrupt factor within the interrupt routine 5 When the first effective edge is input after a count is started an indeterminate value is trans ferred to the reload register At this time timer Bi interrupt request is not generated 6 The value of the counte
241. c n 32 768kHz 00 f1 01 f8 1 0 f32 g00ns 1 1 fc32 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Setting divide ratio b8 b0 b7 bO OoOo DO E Timer AO register Address 038716 038616 TAO E Can be set to 000016 to FFFF16 k i P N Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 bO Count start flag Address 038016 EE TABSR Timer AO count start flag Start count Figure 2 2 11 Set up procedure of timer mode pulse output function selected RENESAS 185 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 5 Operation of Timer A event counter mode reload type selected In event counter mode choose functions from those listed in Table 2 2 4 Operations of the circled items are described below Figure 2 2 12 shows the operation timing and Figure 2 2 13 shows the set up procedure Table 2 2 4 Choosed functions Count source Input signal to TAOIN Pulse output function No pulses output counting
242. ccessed for set 1 Note 2 To rewrite the interrupt control register do so at a point that dose not generate the interrupt request for that register For details see the precautions for interrupts b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset INTiIC i 0 1 005D16 005E XX00X000 XX o TT ilC i 16 16 2 3 Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 oc Level 6 Level 7 Interrupt request bit O Interrupt not requested 0 0 1 Interrupt requested Note 1 POL Polarity select bit 0 Selects falling edge 1 Selects rising edge Reserved bit Always set to 0 o o Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 This bit can only be accessed for reset 0 but cannot be accessed for set 1 Note 2 To rewrite the interrupt control register do so at a point that dose not generate the interrupt request for that register For details see the precautions for interrupts Figure 1 24 Interrupt control register 34 RENESAS Renesas Technology Corp Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Enable Flag The interrupt enable flag I flag controls the enabling and disabling of maskable interrupts Setting this flag to 1 enables all maskable interrupts setting it
243. cece eecneeeeeeeeeeeeeeeeeeeeeeaaeeeeeeeesaaeeeseaeeesaeeeseaaeeseeeeeeenaaeseenees P346 3 4 BUZZ QUU naana telat since cen debe peed deen ete ene P350 e 3 5 Solution for external interrupt pins shortage eeceeceeeceeeseeeeeeeeeeeeeeeeeeeeeeseaeeseeeeeesaeeeneneees P352 e 3 6 Controlling power USING stop MOE ccccceceeceeeeeeeeeeeeeeeeeeseaaeeesaaeeseeaeeesaaaeseceeesaaeeneeees P354 e 3 7 Controlling power USING Wait MOE ceeeecececeeeeeeeeeceeeeeeeeeeceaaeeeseeeeseaeeeseaaesecneeestaeenennees P358 336 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Applications MEMO tENESAS 337 Renesas Technology Corp Timer X Applications Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 3 1 Long Period Timers Overview In this process Timer XO and Timer X1 are connected to make a 16 bit timer with a 16 bit prescaler Figure 3 1 1 shows the operation timing Figure 3 1 2 shows the connection dia gram and Figures 3 1 3 and 3 1 4 show the set up procedure Use the following peripheral functions e Timer mode of timer X e Event counter mode of timer X Specifications 1 Set timer XO to timer mode and set timer X1 to event counter mode 2 Perform a count on count source f1 using timer XO to count for 1 ms and perform a count on timer XO using timer X1 to count for 1 second 3 Connect
244. ception in clock synchronous serial I O mode 2 tENESAS 265 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 5 Precautions for Serial I O in clock synchronous serial I O Transmission 1 With an external clock selected perform the following set up procedure with the CLKO pin input level H if the CLK polarity select bit O or with the CLKO pin input level L if the CLK polarity select bit 1 1 Set the transmit enable bit to 1 2 Write transmission data to the UARTO transmit buffer register 266 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Reception 1 In operating the clock synchronous serial I O operating a transmitter generates a shift clock Fix settings for transmission even when using the device only for reception Dummy data is output to the outside from the TxDo pin transmission pin when receiving data 2 With the internal clock selected setting the transmit enable bit to 1 transmission enabled status and setting dummy data in the UARTO transmission buffer register generates a shift clock With the external clock selected a shift clock is generated when the transmit enable bit is set to 1 dummy data is set in the UARTO transmit buffer register and the extern
245. ciedoat 1 Output mode Functions as an output port 0107 except 2 Poi 6 Pon Pie direction register Note 1 Set bit 2 of protect register address 000A16 to 1 before rewriting to the port P4 direction register Note 2 Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 These bits can either be set nor reset When read its contents are indeterminate Port Pi register Symbol Address When reset Pi i 0 to 7 03E016 03E116 03E516 03E816 Indeterminate 03E916 03EC16 03ED16 Indeterminate Bit symbol Port Pio regi Maier E Port Pi1 register each pin by reading and writing to Port Pi2 register and from each corresponding bit z 0 L level data Port Pis register 1 H level data Port Pi4 register Port Pis register i Oto 7 except 2 Pie Port Pie register Port Pi7 register Note Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 This bit can either be set nor reset When read its content is indeterminate b7 b6 b5 b4 b3 b2 bi bO Figure 2 12 2 Programmable I O ports related registers 1 tENESAS 333 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports Pull up control register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PURO 03FC16 0016 Bit symbol oom eds The corresponding port is pulled PUO1 P04 to P07 pul
246. ck synchronous serial I O mode 1 Clock synchronous serial I O mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data See Table 1 25 Figure 1 65 shows the UARTO transmit receive mode register Table 1 25 Specifications of clock synchronous serial I O mode Transfer data format e Transfer data length 8 bits Transfer clock e When internal clock is selected bit 3 at address 03A016 O fi 2 n 1 Note 1 fi f1 f8 f32 fc e When external clock is selected bit 3 at address 03A016 1 Input from CLKO pin Transmission start e To start transmission the following requirements must be met condition Transmit enable bit bit O at address 03A516 1 Transmit buffer empty flag bit 1 at addresses 03A516 0 e Furthermore if external clock is selected the following requirements must also be met CLKO polarity select bit bit 6 at address 03A416 0 CLKO input level H CLKO polarity select bit bit 6 at address 03A416 1 CLKO input level L Reception start e To start reception the following requirements must be met conditio Receive enable bit bit 2 at address 03A516 1 Transmit enable bit bit 0 at address 03A516 1 Transmit buffer empty flag bit 1 at address 03A516 0 e Furthermore if external clock is selected the following requirements must also be met CLKO polarity select bit bit 6 at
247. cle time 28 1 x m 1 fi m values set to timer AO register s low order address Count start condition External trigger is input e The timer overflows The count start flag is set 1 Count stop condition e The count start flag is reset 0 Interrupt 8 bits PWM _ Set value of H level width is except FF 16 0016 PWM pulse goes L request e Set value of H level width is FF16 0016 Timing that count value goes to 0116 generation 16 bits PWM Set value of H level width is except FFFF16 000016 PWM pulse goes L timing e Set value of H level width is FFFF16 000016 Timing that count value goes to 000116 TAOIN pin function Programmable I O port or trigger input TAOOUT pin function Pulse output Read from timer When timer AO register is read it indicates an indeterminate value Write to timer When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Note When set value of H level width is 0016 or 000016 pulse outputs L level and inversion value FF16 or FFFF 16 is set to timer Timer AO mode register b7 D6 BS bt BS De pT bo Symbol Address When reset 1 1 1 TAOMR 039616 0016 _Bit symbol 4 TMODO _ Operation mode bt bo teen TMO
248. clock Transfer clock LSB first MSB first Continuous receive Disabled d ies Enabled Output transfer clock Not selected to multiple pins Note ER Selected Note This can be selected only when UARTO is used in combination with the internal clock Operation 1 Writing dummy data to the UARTO transmit buffer register setting the receive enable bit to 1 and the transmit enable bit to 1 makes the data receivable status ready 2 In synchronization with the first rising edge of the transfer clock the input signal to the RxDO pin is stored in the highest bit of the UARTO receive register Then data is taken in by shifting right the content of the UARTO reception data in synchronization with the rising edges of the transfer clock 3 When 1 byte data lines up in the UARTO receive register the content of the UARTO receive register is transmitted to the UARTO receive buffer register The transfer clock stops at H level At this time the receive complete flag and the UARTO receive interrupt request bit goes to 1 4 The receive complete flag goes to 0 when the lower order byte of the UARTO buffer register is read 262 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Example of wiring Microcomputer Transmitter side IC CLKO CLK RxDO TxD Example of operatio
249. come 1 Clear the interrupt request bit after changing the polarity 4 Changing interrupt control register See Changing Interrupt Control Register 110 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Electrical characteristics Table 1 36 Absolute maximum ratings Parameter Condition Rated value Supply voltage 0 3 to 6 5 Note 1 Analog supply voltage 0 3 to 6 5 Note 1 Input voltage RESET CNVss POo to P07 P10 to P17 P30 to P35 0 3 to Vec 0 3 P40 to P45 P50 to P54 P60 to P67 Note 2 P70 P71 VREF XIN Output voltage P0Oo to P07 P10 to P17 P30 to P35 P40 to P45 V P50 to P54 P60 to P67 P70 P71 VREF XIN 0 3 to Vcc 0 3 Power dissipation 1000 Note 3 Operating ambient temperature 20 to 85 Note 4 Storage temperature 40 to 150 Note 5 Note 1 Flash memory version 0 3 to 7 V Note 2 When writing to flash MCU CNVss is 0 3 to 13 V Note 3 Flat package 56P6S A is 300 mW Note 4 Extended operating temperature version 40 to 85 C When flash memory version is program erase mode 25 5 C Note 5 Extended operating temperature version 65 to 150 C tENESAS 111 Renesas Technology Corp Electrical characteristics Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 37 Recommended
250. ct AVss to Vss and AVcc to Vcc respectively VREF Reference voltage input Connect this pin to Vss POo to P07 Data I O Do to D7 These are data Do D7 input output pins P10 to P17 Address input As to A15 These are address As A15 input pins P30 to P33 Address input A4 to A7 Input port P3 These are address A4 A7 input pins Enter low signals to these pins WE input Input port P4 This is a WE input pin Enter high signals or low signals to these pins Address input A17 Input port P5 This is address A17 input pin Apply VIH 5 V to this pin when VPP VPPH 12 V or ViL 0 V when VPP VPPL 5 V Enter high signals or low signals to these pins P64 to P67 Address input Ao to A3 Input port P6 These are address Ao A3 input pins Enter high signals or low signals to these pins P70 to P71 Input port P7 Enter high signals or low signals to these pins 2tENESAS Renesas Technology Corp 133 Appendix Parallel I O Mode Flash memory version Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Parallel I O Mode The parallel I O mode is entered by making connections shown in Figures 1 101 and 1 102 and then turning the VPPH power supply on In this mode the M30201 flash memory version operates in a manner similar to the NOR flash memory M5M28F101 from Mitsubishi Note however that there are
251. cteristics of port P1 Vcc 3V HIGH POWER 388 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics 5 1 2 Standard Characteristics of ICc f XIN Figures 5 1 7 and 5 1 8 show the standard characteristics of ICC f XIN The standard characteristics given in this section are examples of M30201M4 XXXFP The contents of these examples cannot be guaranteed For standardized values see Electric characteristics e Measurement conditions Vcc 5V Ta 25 C f XIN square waveform input single chip mode When access to ROM and RAM without wait e Register setting condition XIN XOUT drive capacity select bit 1 HIGH Main clock XIN XQUT stop bit 0 On g XIN 2 a Xin 4 x XIN 8 x XIN 16 6 f XIN MHz Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figures 5 1 7 Standard characteristics of ICC f XIN VCC 5V stENESAS 389 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Vcc 3V e Measurement conditions Vcc 3V Ta 25 C f XIN square waveform input single chip mode When access to ROM and RAM without wait e Register setting condition XIN XOUT drive cap
252. ction is executed Note 2 Ta 25T when clock is stopped Ta 85T when clock is stopped Extended operating temprature version 40 to 85 C Note 2 With one timer operated using fC32 tENESAS Renesas Technology Corp 113 Electrical characteristics Vcc 5V Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 39 A D conversion characteristics Note Parameter Resolution Measuring condition Vrer Vcc Vcc 5V Standard Min Typ Max Absolute Sample amp hold function not available VREF Vcc 5V accuracy Sample amp hold function available 10bit VREF Vcc 5V Sample amp hold function available 8bit VREF Vcc 5V RLADDER Ladder resistance Vrer Vcc tconv Conversion time 1 Obit tconv Conversion time 8bit tsamP Sampling time VREF Reference voltage Via Analog input voltage Note Unless otherwise noted Vcc AVcc VREF 5V Vss AVSs OV at Ta 25 C f XIN 10MHz 114 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Timing requirements referenced to Vcc 5V Vss OV at Ta 20 to 85 C unless otherwise specified Extended operating temprature version 40 to 85 C Table
253. d 186 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting event counter mode and functions BOO0OCOOE Dyn AO mode register Address 039616 TAOMR Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge Up down switching cause select bit 0 Up down flag s content 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type Invalid when not using two phase pulse signal processing Setting up down flag b7 bo Up d fl Add 0384 iOS ESSN Eo lr a Timer AO up down flag 0 Down count Timer AO two phase pulse signal processing select bit 0 Two phase pulse signal processing disabled N Setting trigger select register b7 bo Trigger select register Address 038316 ALLE TRGSR Timer AO event trigger select bit b1 bO 0 0 Input on TAOIN is selected Note Note Set the corresponding port direction register to 0 input mode Setting divide ratio b15 b8 b7 b0 b7 Timer AO register Address 038716 038616 TAO E Can be set to 000016 to FFFF16 Setting count start flag b7 bo Count start flag Address 038016 TABSR Timer AO count start flag Start count
254. d See the software manual for details b15 bO TPT EERE Feros re Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1 10 Flag register FLG 14 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Reset Reset There are two kinds of resets hardware and software In both cases operation is the same after the reset See Software Reset for details of software resets This section explains on hardware resets When the supply voltage is in the range where operation is guaranteed a reset is effected by holding the reset pin level L 0 2Vcc max for at least 20 cycles When the reset pin level is then returned to the H level while main clock is stable the reset status is cancelled and program execution resumes from the address in the reset vector table Figure 1 11 shows the example reset circuit Figure 1 12 shows the reset sequence Vcc Power source voltage detection circuit Example when Vcc 5V Figure 1 11 Example reset circuit More than 20 cycles are needed RESET BCLK 24cycles e Hs o Internal clock Content of reset vector Address FFFFCie Y FFFFE16
255. d lected lected low is sel low is sel low is sel Timer X1 lect bit b7 b6 0 1 TB1 ove 10 TX1 overfl 11 TAO overfl event trigger sel ected ected ected low is sel low is sel low is sel Setting PWM pulse s H level width b15 b8 b0 b7 b7 bO Timer X0 register Address 038916 038816 TXO Loo T E Timer X1 register Address 038B16 038A16 TX1 n Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFE16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XcIN by 32 b7 bo DDDDDDDI a Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O a b7 b0 LTT TTT Setting count starts flag Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 23 Set up procedure of pulse width modulation mode 8 bit PWM mode selected 243 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 12 Precautions for Timer X timer mode event counter mode 1 To clear reset the count start flag is set to O Set a value
256. d the content of the succes sive comparison register conversion result is transmitted to A D register 0 3 Every time the A D converter carries out A D conversion on a selected analog input pin the A D converter carries out A D conversion on only one unselected pin and then the A D converter carries out A D conver sion from the ANO pin again See Figure 2 7 13 The conversion result is transmitted to A D register i every time conversion on a pin is completed The A D conversion interrupt request bit does not go to 1 4 The A D converter continues operating until software goes the A D conversion start flag to O When AN0 is selected When ANo AN1 are selected When ANo to AN2 are selected When ANo to AN3 are selected Time ame gt xo i ees Converted analog input pin Converted analog input pin Converted analog input pin Converted analog input pin Figure 2 7 13 ANi pin s sweep sequence in repeat sweep mode 2 Conversion result is 1 Start ANo AN5o pin transfered to A D 3 Consecutive conversion conversion conversion register gt r i i i 4 A D 8 bit resolution i 8 bit resolution amp bit resolution 8 bit resolution conversion 28 wav cycles 28 AD cycles 28 eaD cycles 28 aD cycles is complete 10 bit resolution 10 bit resolution 10 bit resolution 10 bit resolution 33 AD cycles 33 AD cycles 33 ead cycles 33 aD cycles o UUW UUW
257. d registers and Figure 2 9 3 shows address match interrupt related registers 000916 Address match interrupt enable register AIER 000A16 000B16 000E16 000F16 001016 001116 Address match interrupt register 0 RMADO 001216 001316 001416 001516 Address match interrupt register 1 RMAD1 001616 Figure 2 9 2 Memory map of address match interrupt related registers Address match interrupt enable register or eS ee ee Symbol Address When reset AIER 000916 XXXXXX002 Bit symbol Bit name Function i AIERO Address match interrupt 0 0 Interrupt disabled enable bit 4 Interrupt enabled AIER1 Address match interrupt 1 0 Interrupt disabled enable bit 1 Interrupt enabled Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Address match interrupt register i i 0 1 19 b16Xb15 b8 Address When reset 20 b7 a 001216 to 001016 X0000016 001616 to 001416 X0000016 Address setting register for address match interrupt 0000016 to FFFFF16 pe Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Figure 2 9 3 Address match interrupt related registers RENESAS 315 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt 2 9 2 Operation of Address Matc
258. de disabled Must be 0 in clock synchronous I O mode Valid when bit 5 1 CLK CLKS select bit 1 0 Normal mode Continued to the next page Figure 2 5 12 Set up procedure of reception in clock synchronous serial I O mode 1 264 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Continued from the previous page ee Reception enabled b7 bo KKKE FID UARTO transmit receive control register 1 Address 03A516 UOC1 Transmit enable bit 1 Transmission enabled Receive enable bit Note 1 Reception enabled Note Set the corresponding port direction register to O input mode Writing dummy data b15 b8 b7 b0 b7 bo KKKKKEKKEX id UARTO transmit buffer register Address 03A316 03A216 UOTB Setting dummy data Start reception Checking completion of reception b7 b0 BPPP TH UARTO transmit receive control register 1 Address 03A516 U0C1 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register Checking error b15 b7 bo UARTO receive buffer register Address 03A716 0O3A616JUORB Receive data Overrun error flag 0 No overrun error 1 Overrun error found Processing after reading out reception data Figure 2 5 13 Set up procedure of re
259. disabled by an address match interrupt enable bit Address match interrupts are not affected by the inter rupt enable flag I flag and processor interrupt priority level IPL For an address match interrupt the value of the program counter PC that is saved to the stack area varies depending on the instruction being executed Figure 1 32 shows the address match interrupt related registers Address match interrupt enable register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset AIER 000916 XXXXXX002 Bina am AIERO Address match interruptO Q Interrupt disabled enable bit 4 Interrupt enabled AIER1 Address match interrupt 1 O Interrupt disabled enable bit 1 Interrupt enabled Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Address match interrupt register i i 0 1 b19 b16 b15 b8 Address When reset bo be b0 b7 001216 to 001016 X0000016 001616 to 001416 X0000016 Address setting register for address match interrupt 0000016 to FFFFF16 Jo o Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Figure 1 32 Address match interrupt related registers 44 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Precautions for Interrupts 1 Reading address 0000016 e Whe
260. dress 038316 aun BG TRGSR Timer AO event trigger select bit b1 b0 0 0 Input on TAOIN is selected Note Note Set the corresponding port direction register to 0 input mode Setting divide ratio b8 b0 b7 b0 Timer AO register Address 038716 038616 TAO o Can be set to 000016 to FFFF16 Setting count start flag b7 bo Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 15 Set up procedure of event counter mode free run type selected RENESAS 189 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 7 Operation of timer A 2 phase pulse signal process in event counter mode normal mode selected In processing 2 phase pulse signals in event counter mode choose functions from those listed in Table 2 2 6 Operations of the circled items are described below Figure 2 2 16 shows the operation timing and Figure 2 2 17 shows the set up procedure Table 2 2 6 Choosed functions Count operation type Reload type Free run type 2 phase pulses Normal processing process 4 multiplication processing Operation 1 Setting the count start flag to 1 causes the counter to count effective edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time
261. duct to another This manual gives descriptions of M30201M4 XXXSP Memories built in are as shown below Be careful when writing a program as the memories have different capacities The figure of each register configuration describes its functions contents at reset and attributes as follows pate M30201F6SP FP yi M30201F6TFP AREE E A I N E AS A E ES S M30201M6 XXXFP M30201M6T XXXFP M30201M4 XXXSP FP Kpa aan M30201M4T XXXFP 0 frrrn rrr tree ae a cc a CG ala ea posceraee tte 16K 32K 48K ROM Size Byte This manual comprises of eight chapters Use the suggested chapters as a reference for the following topics e Bit attribute R Read W Write O Possible to read O Possible to write X lmpossible to read X lmpossible to write Bit attribute One shot start flag Symbol Address When reset b7 be 09 DA b3 b2 bi bo ONSF 038216 00x000002 i Bit symbol Bit name Function i i to tt tt 54 TA0OS Timer AO one shot start flag 4 Timer start te eit ea TA10S_ Timer A1 one shot start flag When read the value is 0 OO PER TA2OS Timer A2 one shot start flag OO Le Sh io enee Seas TA3O0S Timer A3 one shot start flag oO eee ae TA40S__ Timer A4 one shot start flag 0ko Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate
262. during A D conversion the conversion result is indeterminate Note 2 When changing A D operation mode set analog input pin again Note 3 AN50 to ANs4 can be used in the same way as for ANo to AN4 A D control register 1 Note b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset ADCON1 03D716 0016 Bit symbol Bit name Function A D sweep pin select bit Invalid in one shot mode A D operation mode Set this bit to 0 in this mode select bit 1 8 10 bit mode select bit 8 bit mode 10 bit mode Frequency select bit 1 faD 2 or fAD 4 is selected faD is selected Vref connect bit Vref connected Set this bit to 0 O O A D input group select bit 0 Port P6 group is selected ADGSELO 1 Port P5 group is selected Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate Figure 1 85 A D conversion register in one shot mode stENESAS 93 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 Repeat mode In repeat mode the pin selected using the analog input pin select bit is used for repeated A D conversion See Table 1 31 Figure 1 86 shows the A D control register in repeat mode Table 1 31 Repeat mode specifications Specification Function The pin selected by the analog input pin select bit is used for repeated A D conversion Start condition Writing
263. dy before the reception buffer register is read 4 How to deal with an error When receiving data read an error flag and reception data simultaneously to determine which error has occurred If the data read is erroneous initialize the error flag and the UARTO receive buffer register then receive the data again To initialize the UARTO receive buffer register 1 Set the receive enable bit to O disable reception 2 Set the serial I O mode select bit to 0002 invalid serial I O 3 Set the serial I O mode select bit 4 Set the receive enable bit to 1 again enable reception To transmit data again due to an error on the reception side when external clock is selected clear the UARTO transmit buffer register then transmit the data again To clear the UARTO transmit buffer register 1 Set the port P52 CLKo pin direction register to 0 input mode 2 Set the port P50 TxDo pin direction register to 0 input mode 3 Set the internal external clock select bit to O internal clock 4 Checking complection of transmission no data present in transmit register 5 Set the internal external clock select bit to 1 external clock 6 Set the port P50 TxDo pin direction register to 1 output mode then set transmission data in the UARTO transmit buffer register 248 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Cloc
264. e Standard Parameter Min Max te Tx TXiINOUT input cycle time tw TXH TXiINOUT input HIGH pulse width tw TXL TXiiNouT input LOW pulse width Table 1 51 Timer X input external trigger input in one shot timer mode Standard Parameter Min Max to TX TXiiNOUT input cycle time tw TXH TXinout input HIGH pulse width tw TXL TXiINouT input LOW pulse width 116 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Timing requirements referenced to Vcc 5V Vss OV at Ta 20 to 85 C unless otherwise specified Extended operating temprature version 40 to 85 C Table 1 52 Timer X input pulse period measurement mode Standard Parameter Min Max TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width Table 1 53 Timer X input pulse width measurement mode Standard Parameter Min Max te TX TXiiNouT input cycle time tw TXH TXitnouT input HIGH pulse width tw TXL TXiINOUT input LOW pulse width Table 1 54 Serial I O Standard Parameter Min Max te CK CLKO input cycle time tw CKH CLKO input HIGH pulse width tw CKL CLKO input LOW pulse width ta C Q TxDi output delay time th C Q TxDi hold time tsu D C RxDi input setup time th C D RxDi inpu
265. e Table 2 3 1 Choosed functions Count source Internal count source f1 fs f32 fc32 Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the counter contin ues counting At this time the timer Bi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow i 3 Stop count Start count again gan oO g Z a 2 a O is ne 2 5 O oO Time Set to 1 by software Cleared to 0 by Set to 1 by software P software i 2 Count start flag ne i i Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi interrupt 1 a request bit o Figure 2 3 4 Operation timing of timer mode 210 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B r Selecting timer mode and functions b7 b0 Timer Bi mode register i 0 1 Address 039B16 039C16 I o0 TBiMR 0 to 2 Selection of timer mode Invalid in timer mode Can be 0 or 1 Fixed to 0 in timer mode i n poures asec Dl f Count Count source period 00 f1 SOUICe
266. e In this mode the timer counts an external signal or an internal timer s overflow See Table 1 18 Figure 1 52 shows the timer Bi mode register in event counter mode Table 1 18 Timer specifications in event counter mode Count source e External signals input to TBIIN pin e Effective edge of count source can be a rising edge a falling edge or falling and rising edges as selected by software Count operation e Counts down e When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer underflows TBIIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer When counting stopped When a value is written to timer Bi register it is written to both reload register and counter When counting in progress When a value is written to timer Bi register it is written to only reload register Transferred to counter at next reload time Timer Bi mode register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset IIX foli TBiMR i 0 1 039B16 to 039C16 00XX00002 Biteymbo 7 TMODO Operation mode select bit ce Event i j Event counter mode TMOD1 MRO Count polarity select Rave bit Note 1 y 0 0 Counts external s
267. e UARTI receive buffer register e The UARTI receive interrupt request bit does not change Framing error e This error occurs when the stop bit falls short of the set number of stop bits Parity error e With parity enabled this error occurs when the total number of 1 s in character bits and the parity bit is different from the specified number Error sum flag e This flag turns on when any error overrun framing or parity is detected When the flag turns on How to clear the flag The error is detected when data is transferred from the UARTI receive register to the UARTi receive buffer register e Set the receive enable bit to g e Set the receive enable bit to 0 e Read the lower order byte of the UARTi receive buffer register e When all error overrun framing and parity are removed the flag is cleared stENESAS Renesas Technology Corp 270 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 4 Functions selection In operating UART the following functions can be used a Sleep mode Sleep mode is a mode in which data is transferred to a particular microcomputer among those con nected by use of clock asynchronous serial I O devices The following are examples in which functions a to e are chosen e Transmission WITHOUT other functions 0 ceeeeeeeeeeeeeeeeeeeeeeeeceaeeeeeaaeeseeeeeesaaaeseeeeees
268. e 1 9 Interrupt levels enabled according to the contents of the IPL Interrupt priority Interrupt priority Priority level select bit level order b2 bi b0 Level 0 0 0 0 interrupt disabled 0 0 1 Level 1 Low O 1 0 Level 2 O 1 1 Level 3 1 0 0 Level 4 1 0 1 Level 5 1 1 0 Level 6 1 1 1 Level 7 High IPL Enabled interrupt priority levels IPL2 IPL1 IPLo 0 0 Interrupt levels 1 and above are enabled O O 1 Interrupt levels 2 and above are enabled O 1 0 Interrupt levels 3 and above are enabled O 1 1 Interrupt levels 4 and above are enabled 1 0 0 Interrupt levels 5 and above are enabled 1 0 1 Interrupt levels 6 and above are enabled 1 1 0 Interrupt levels 7 and above are enabled All maskable interrupts are disabled stENESAS Renesas Technology Corp 35 Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Changing the Interrupt Control Register lt Program examples gt The program examples are described as follow Example 1 INT_SWITCH1 FCLR AND B 00h 0055h NOP NOP FSET Example 2 INT_SWITCH2 FCLR AND B 00h 0055h MOV W MEM RO FSET Example 3 INT_SWITCH3 PUSHC FLG FCLR AND B 00h 0055h POPC FLG Disable interrupts Clear TAOIC int priority level and int request bit Four NOP instructions are required when using HOLD function Enable interrupts
269. e 2 6 7 Set up procedure of transmission in UART mode 1 278 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART Continued from the previous page Setting UARTI bit rate generator i 0 1 b7 b0 UARTi bit rate generator i 0 1 Address 03A116 03A916 UiBRG i 0 1 Can be set to 0016 to FF16 Note Note Write to UARTi bit rate generator when transmission reception is halted Transmission enabled b7 bo EVANTA TANTA UARTO transmit receive control register 1 UOC1 Address 03A516 Xxx ET UART1 transmit receive control register 1 U1C1 Address 03AD16 Transmit enable bit 1 Transmission enabled Writing transmit data b15 b8 b7 b0 b7 b0 XXKKKKE d UARTO transmit buffer register Address 03A316 03A216 UOTB UART1 transmit buffer register Address 03AB16 O3AA16 U1TB Setting transmission data Ne BNSNNSNNNASNNANNANENANANNNNANENAENNGNNANEANENNENNAEEANEENENN Start transmission Checking the status of UARTi transmit buffer register i 0 1 b7 po UARTO transmit receive control register 1 UOC1 Address 03A516 eee gee UART1 transmit receive control register 1 U1C1 Address 03AD16 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled
270. e count continues At this time the timer AO interrupt request bit goes to 1 n reload register content 2 Underflow 3 Switch count 4 Overflow Counter content hex Count start flag A Set to 1 by software q Up down flag 0 i i i i Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 4 ma x Ss request bit un l Figure 2 2 14 Operation timing of event counter mode free run type selected 188 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting event counter mode and functions Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge Up down switching cause select bit 0 Up down flag s content 0 Must always be 0 in event counter mode Count operation type select bit 1 Free run type Invalid when not using two phase pulse signal processing K Setting up down flag b7 0 0 0 Up down flag Address 038416 UDF Timer AO up down flag 0 Down count Timer AO two phase pulse signal processing select bit 0 Two phase pulse signal processing disabled r Setting trigger select register By Bo Trigger select register Ad
271. e processor saves the 4 high order bits of the program counter and 4 high order bits and 8 low order bits of the FLG register 16 bits in total in the stack area then saves 16 low order bits of the program counter Figure 1 27 shows the state of the stack as it was before the acceptance of the interrupt request and the state the stack after the acceptance of the interrupt request Save other necessary registers at PUSHM instruction alone can save Address Stack area MSB Content of previous stack _ Content of previous stack Stack status before interrupt request is acknowledged the beginning of the interrupt routine using software Using the all the registers except the stack pointer SP Address Stack area MSB SP a New stack Program counter PC A pointer value Program counter PCm Flag register FLG gt Flag register FLGu Program SP counter PCx Stack pointer value before interrupt occurs Content of previous stack Content of previous stack Stack status after interrupt request is acknowledged Figure 1 27 State of stack before and after acceptance of interrupt request 39 stENESAS Renesas Technology Corp Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer Note at the ti
272. e pulse output function the output from the port varies the value in the port register does not vary 4 Reading the timer Either in timer mode or in event counter mode reading the timer register takes out the count at that moment Read it in 16 bit units The data either in one shot timer mode or in pulse width modulation mode is indeterminate In both the pulse period measurement mode and pulse width measurement mode an indeterminate value is read until the second effective edge is input after a count is started otherwise the measurement results are read 5 Writing to the timer When writing to the timer register while a count is in progress the value is written only to the reload register When writing to the timer register while a count has stopped the value is written both to the reload register and the count Write the value in 16 bit increments The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode 6 Relation between the input output to from the timer and the direction register With the output function of the timer set the direction register of the relevant port to input To input an external signal to the timer set the direction register of the relevant port to input However pulse output cannot be selected when inputting an external signal to the timer and vice versa 7 Pins related to timer X a TXOINOUT TX1INOUT TX2INOUT Input output pins to timer X
273. eceive mode register UOMR Address 03A016 Serial I O mode select bit b2 b1 b0 1 0 1 Transfer data 8 bits long Internal external clock select bit 1 External clock Note Stop bit length select bit 0 One stop bit Valid when bit 6 1 Parity enable bit 0 Parity diabled Sleep select bit 0 Sleep mode diabled Note UATRT1 cannot be selected external clock n Setting UARTO transmit receive control register 0 b7 b0 0 0 UARTO transmit receive control register 0 UOCO Address 03A416 BRG count source select bit Invalid when external clock is selected Must be 0 in UART mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in UART mode Data output select bit 0 TxDO pin is CMOS output 1 TxDO pin is N channel open drain output Must be 0 in UART mode Must be 0 in UART mode Setting UART transmit receive control register 2 BOLT 4 UART transmit receive control register 2 UCON Address 03B016 Invalid in UART mode Must be 0 in UART mode Invalid in UART mode Must be 0 in UART mode Continued to the next page Figure 2 6 10 Set up procedure of reception in UART mode 1 282 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SI
274. eck code is output with the 2nd byte change the baud rate to 19 200 bps RxDO M16C reception data TxDO M16C transmit data Figure 1 132 Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38 400 bps Execute it as follows 1 Transfer the B216 command code with the 1st byte 2 After the B216 check code is output with the 2nd byte change the baud rate to 38 400 bps RxDO M16C reception data TxDO M16C transmit data Figure 1 133 Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57 600 bps Execute it as follows 1 Transfer the B316 command code with the 1st byte 2 After the B316 check code is output with the 2nd byte change the baud rate to 57 600 bps RxDO M16C reception data TxDO M16C transmit data Figure 1 134 Timing of baud rate 57600 168 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 2 Flash Memory Version Example Circuit Application for The Standard Serial I O Mode 2 The below figure shows a circuit application for the standard serial I O mode 2 CLKO P53 BUSY M30201 Flash memory version CNVss 1 Control pins and external circuitry will vary according to peripheral unit For more information see the peripheral unit manual 2 In this example the microprocessor mode and sta
275. ect bit 1 to 1 and setting CLK CLKS select bit 0 to 1 causes the CLKS pin to go to the transfer clock output pin Change the transfer clock output pin when transmission is halted 258 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Example of wiring Microcomputer TxDo P50 CLKS P53 CLKo P52 Note This applies when performing only transmission with an internal clock selected in the clock synchronous serial I O mode Example of operation 1 Transmission enabled 3 Transmission is complete 2 Start transmission 4 Clock switched Transfer clock LJUUUUUUUUUUULUN i Transmit enable bit Transmit buffer empty flag CLK CLKS select bit 1 CLK CLKS select bit 0 ao innn noo 702000 O C C OCOC Transmit interrupt k request bit 0 a Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 5 8 Operation timing of transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected stENESAS 259 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Setting UARTO transmit receive mode register b7 bo UARTO transmit receive mode register o o ofi UOMR Address 03A016
276. ed Figure 1 14 shows the processor mode register 0 and 1 Processor mode register 0 Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset XXXI Jofolo PMO 000416 XXXX00002 Reserved bit Must always be set to 0 PMO3 Software reset bit The device is reset when this bit is set to 1 The value of this bit is O when read Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note Set bit 1 of the protect register address 000A16 to 1 when writing new values to this register Processor mode register 1 Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PM1 000516 OXXXXXX02 Bit symbol Reserved bit Must always be set to 0 loio Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Reserved bit Must always be set to 0 o o Note Set bit 1 of the protect register address 000A16 to 1 when writing new values to this register Figure 1 14 Processor mode register 0 and 1 RENESAS 17 Renesas Technology Corp Clock Generating Circuit Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units Table 1 2 Main clock and sub
277. ed hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but
278. eeeeeeceaeeeseaaeeeeeeeeesaaeeseeeeeesaeeseeaeeesiaeeeneaeeeee 330 2512 1 OVGIVIGW piisisid TE A A E bisa AE E E A E 330 Chapter 3 Examples of Peripheral functions Applications 821 Eong Period TIMES ro arara o aa e AEE A E AA AAAA EEA E TE A EA ees hate 338 3 2 Variable Period Variable Duty PWM Output 0 cccceceeeeeeeeeeeeeneeeeeeaeeseeeeeesaaeeeeeeeeesaeeeteeeeeaas 342 3 3 Delayed One Shot Output cc eeeeee cece eeeeeeeeee cece ae eeeeeeeeceaeeeeeaeeeeeeeeeeeaaeeseeeeeesaeeseeeeeessaeeeseeeeee 346 3 4 Buzzer Output cai ical ea eet ed a ie eb dee Si eae 350 3 5 Solution for External Interrupt Pins Shortage ccccceceecceeeeeeeeeeeeeeaeeeeeeeeeeaeeseeneeessaeeeseeeeeaas 352 3 6 Controlling Power Using Stop Mode cccccceceeeeeeeeeeeceeeeeeeeeeeeeaeeeeeaaeeseeeeeesaaaeseeeeeesaaeeseeeeeaas 354 3 7 Controling Power Using Wait Mode cccccccececeeeeeeeee cece eeeeaeeeeeeeesaaaeeeceeeesaaeseeeeeeseeaeeeeeaeeeed 358 Chapter 4 Interrupt 4 1 Overview of Interrupt cece ceenceececeeeeeeeeeeeeeeeecaaeesseeeeecaaeesdeaaeecaaeeeseaaeeseeeeeeaaaeseeeeeeseaeesseaaeeee 364 44 1 Type of IMterru pts iv cicccedeeencceevie eee deve ected eee die esa devel dished dh eee eddie eee EN EEA TN ee 364 4 1 2 S0ttware Interrupts mene iene i ate ede Le de teat aat 365 4 1 3 Hardware Interrupts sicie ia eena Aia AREAN ATEENA AA ANE ANNE ETEA 366 4 1 4 Interrupts and Interrupt Vector Tables 2 0 0 2 eee eee eecneee
279. equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under ce
280. er e Single step interrupt This interrupt is exclusively for the debugger do not use it in other circumstances With the debug flag D flag set to 1 a single step interrupt occurs after one instruction is executed Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1 If an address other than the first address of the instruction in the address match interrupt register is set no address match interrupt occurs For address match interrupt see 2 9 Address match Interrupt 2 Peripheral I O interrupts A peripheral I O interrupt is generated by one of built in peripheral functions Built in peripheral func tions are dependent on classes of products so the interrupt factors too are dependent on classes of products The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INI instruction uses Peripheral I O interrupts are maskable interrupts e Key input interrupt A key input interrupt occurs if an L is input to the KI pin A D conversion interrupt This is an interrupt that the A D converter generates e UARTO and UART1 transmission interrupt These are interrupts that the serial I O transmission generates UARTO and UART1 reception interrupt These are interrupts that the serial I O reception generates Timer
281. er to O input mode UARTI transmit receive control register 0 b7 b6 b5 b4 b3 b2 bi b0 tT td Jol YT Symbol UiCO i 0 1 Address 03A416 O83AC16 When reset 0816 0 Parity disabled 1 Parity enabled Bit P symbol Bit name CLKO BRG count source select bit CLK1 Function Note During clock synchronous serial I O mode bi b0 0 0 f1 is selected 0 1 f8 is selected 1 0 f32 is selected 1 fc is selected Function During UART mode b1 b0 00 f1 is selected 01 fs is selected 10 f32 is selected 1 fc is selected Set this bit to 0 TXEPT Transmit register empty Set this bit to 1 NCH Data output select bit CLK polarity select bit Data present in transmit register during transmission No data present in transmit register transmission completed TXDi pin is CMOS output 1 TXDi pin is N channel open drain output Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Note UART1 cannot be used in clock synchronous serial I O Figure 1 72 Serial l O related registers 2 78 7rtENESAS Renesas Technology Corp Data present in transmit register during transmission No data present in transmit register transmission completed TXDi pin is CMOS output TXDi pin is
282. er underflows when a count source equal to a frequency division ratio is input and an interrupt request occurs 4 Reading the timer In timer mode or event counter mode the count value at the time of reading the timer register will be read Read the register in 16 bit increments In both the pulse period measurement mode and pulse width measurement mode an indeterminate value is read until the second effective edge is input after a count is started otherwise the measurement results are read 5 Writing to the timer When writing to the timer register while a count is in progress the value is written only to the reload register When writing to the timer register while a count has stopped the value is written both to the reload register and the count Write the value in 16 bit increments The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode 206 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 6 Input to the timer and the direction register To input an external signal to the timer set the direction register of the relevant port to input 7 Pins related to timer B a TBOIN TB1IN Input pins to timer B 8 Registers related to timer B Figure 2 3 1 shows the memory map of timer B related registers Figures 2 3 2 and 2 3 3 show timer B related registers 005A16 Timer BO interrup
283. ernal clock CLKO pin Note Transmission Transmission buffer empty interrupt factor Transmission complete Sleep mode Sleep mode off Sleep mode selected Note UART1 cannot be selected external clock Operation 1 Setting the transmit enable bit to 1 and writing transmission data to the UARTi transmit buffer register readies the data transmissible status 2 Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register At this time the first bit the start bit of the transmission data is transmitted from the TxDi pin Then data is transmitted bit by bit in sequence LSB MSB parity bit and stop bit s 3 When the stop bit s is are transmitted the transmit register empty flag goes to 1 which indicates that transmission is completed At this time the UARTi transmit interrupt request bit goes to 1 The transfer clock stops at H level 4 If the transmission condition of the next data is ready when transmission is completed a start bit is generated following to stop bit s and the next data is transmitted 276 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART Example of wiring Microcomputer Receiver side IC Example of operation Transfer clock oo 1 Transmission enabled 3 Confirme stop bit pojo 4 Start transmission 2 Start
284. es i is complete ANNARA Set to 1 by software Cleared to 0 by software A D conversion T start flag A D register i Result Result i A D conversion Stop Convert Convert Convert Stop Note When ap frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 AD cycles for 8 bit resolution and 59 AD cycles for 10 bit resolution Figure 2 7 7 Operation timing of repeat mode 292 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold b7 b0 olololi A D control register 2 Address 03D416 ADCON2 A D conversion method select bit 1 With sample and hold Must be fixed to 0 Setting A D control register 0 and A D control register 1 bo b7 b7 o A D control register 0 Address 03D616 A D control register 1 Address 03D716 ADCONO oe Analog input pin select bit Note 2 Invalid in repeat mode b2 b1 b0 0 0 0 ANd is selected A D operation mode select bit 1 Note 1 AN1 is selected 0 Must always be 0 in repeat mode AN2 is selected AN3 is selected 8 10 bit mode select bit AN4 is selected 0 8 bit mode ANs is selected 1 10 bit mode AN6 is selected AN7 is selected Frequency select bit 1 Repeat mode is selected Note 1 i ie pek selected Must be fixed to
285. esponse time is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment a and the time required for executing the interrupt sequence b Figure 4 3 1 shows the interrupt response time Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine Interrupt response time a Time from interrupt request is generated to when the instruction then under execution is completed b Time in which the instruction sequence is executed Figure 4 3 1 Interrupt response time 374 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Time a is dependent on the instruction under execution Thirty cycles is the maximum required for the DIVX instruction without wait Time b is as shown in Table 4 3 1 Table 4 3 1 Time required for executing the interrupt sequence Interrupt vector address Stack pointer SP value 16 Bit bus without wait 8 Bit bus without wait Even 18 cycles Note 1 20 cycles Note 1 Even 19 cycles Note 1 20 cycles Note 1 Odd Note 2 19 cycles Note 1 20 cycles Note 1 Odd Note 2 20 cycles Note 1 20 cycles Note 1 N
286. eteneaeeees 245 2 4 14 Precautions for Timer X pulse period pulse width measurement mode eeeeeee 246 2 4 15 Precautions for Timer X pulse width Modulation mode ee eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeees 247 2 5 Clock Synchronous Serial O a rar aa ra a aaraa aa ar aa A p aaraa desea aaaea ieee aa aaa 248 PAEONIA A E AEE ceca E ET E E 248 2 5 2 Operation of Serial I O transmission in clock synchronous serial I O mode 068 254 2 5 3 Operation of the Serial I O transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected 0 0 eee ec eeeeeeeeeeeeeeeeeeeeaeeeeeeeeaaeeeeeeeaaeeeeeeeaas 258 2 5 4 Operation of Serial I O reception in clock synchronous serial I O Mode cscceeee 262 2 5 5 Precautions for Serial I O in clock synchronous Serial I O cceeeceeeeeeeeeeeeeeeetaeeeeeeees 266 2 6 Clock Asynchronous Serial I O UART c cccceeeeeeeeeeeeeeeeeeeeaee scene eeseaaeeteaeeesaaeseeaaeesecaeeesaaeeeed 268 2 61 OVEIVICW oa ei aaa eii de tae Ravn eect vel de hd Oa eines Ol hae ee 268 2 6 2 Operation of Serial I O transmission in UART mode ccccceeeeeeeeeeeeeeeeaeeeeeeeeeseaeeeeeneees 276 2 6 3 Operation of Serial I O reception in UART mode ccccceeeeeeeeeeeeeeeeeeeeeaeeeeeeeeessaeeeeeneees 280 27 AD CONVEMER sity ii cce stoi cthstin e aa a whan be eh adie ate ia 284 2A QVCIVICW niia aaah heehee E van Oo dag
287. etting the WAIT peripheral function clock stop bit bit 2 at 000616 to 1 and then executing a WAIT instruction 5 fc32 This clock is derived by dividing the sub clock by 32 It is used for the timer A timer B and timer X counts 6 fc This clock has the same frequency as the sub clock It is used for BCLK and for the watchdog timer 20 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit Figure 1 18 shows the system clock control registers 0 and 1 System clock control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset CMO 000616 4816 Bil symbol b1 b0 Clock output function 1 O port P54 select bit Q 1 fc output f fg output Clock divide counter output CMo2 WAIT peripheral function He os not stop peripheral function clock in wait mode clock stop bit Stop peripheral function clock in wait mode Note 8 CM03 XCIN XCOUT drive capacity 2 LOW select bit Note 2 HIGH Port Xc select bit I O port CMo4 Peer ae XCIN XCOUT generation CM05 Main clock XIN XOUT 0 On stop bit Note 3 4 5 1 Off CM06 Main clock division select o CM16 and CM17 valid bit 0 Note 7 Division by 8 mode hep clock select bit 0 XIN XOUT Set bit 0 of the protect register address 000A16 to 1 before writing to this register Changes to 1 when shifting to stop mode and at a reset This bit i
288. event counter mode to one shot timer mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to 0 after the above listed changes have been made 4 If a trigger occurs while a count is in progress after the counter performs one down count following the reoccurrence of a trigger the reload register contents are reloaded and the count continues To generate a trigger while a count is in progress generate the second trigger after an elapse longer than one cycle of the timer s count source after the previous trigger occurred stENESAS 245 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 14 Precautions for Timer X pulse period pulse width measurement mode 1 The timer Xi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Xi is overflowed The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine 2 If the timer overflow occurs simultaneously with the input of a measurement pulse and if the interrupt factor cannot be determined from the timer Xi overflow flag connect the timers and count the number of overflows 3 When reset the timer Xi overflow flag goes to 1 This flag cannot be set to O by writing to the timer Xi mode register when the count start flag is 1 4 Use the ti
289. f XIN 10MHz f XcIN 32 768kHz 01 fs 100ns 10 f32 800ns 11 fc32 i 3 2us 976 56us Setting divide ratio b15 b8 b7 bO Doo O OE Timer BO register Address 039116 039016 TBO Timer B1 register Address 039316 039216 TB1 Oo Can be set to 000016 to FFFF16 A k Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O x Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Figure 2 3 5 Set up procedure of timer mode stENESAS 211 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 3 Operation of Timer B event counter mode In event counter mode choose functions from those listed in Table 2 3 2 Operations of the circled items are described below Figure 2 3 6 shows the operation timing and Figure 2 3 7 shows the set up procedure Table 2 3 2 Choosed functions Count source Input signal to the TBiIN pin counting falling edges Input signal to the TBiIN pin counting rising edges In
290. f software interrupt numbers 0 through 63 and executing the INT instruction Software interrupt numbers 0 through 31 are assigned to peripheral I O interrupts so executing the INT instruction allows executing the same interrupt routine that a peripheral I O interrupt does The stack pointer SP used for the INT interrupt is dependent on which software interrupt number is involved So far as software interrupt numbers 0 through 31 are concerned the microcomputer saves the stack pointer assignment flag U flag when it accepts an interrupt request If change the U flag to 0 and select the interrupt stack pointer ISP and then execute an interrupt sequence When returning from the interrupt routine the U flag is returned to the state it was before the acceptance of interrupt re quest So far as software numbers 32 through 63 are concerned the stack pointer does not make a shift 2tENESAS 365 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 3 Hardware Interrupts Hardware interrupts are classified into two types special interrupts and peripheral I O interrupts 1 Special interrupts Special interrupts are non maskable interrupts Reset Reset occurs if an L is input to the RESET pin e DBC interrupt This interrupt is exclusively for the debugger do not use it in other circumstances e Watchdog timer interrupt Generated by the watchdog tim
291. falling edges Pulses output Input signal to TAOIN Count operation type Reload type counting rising edges Free run type Timer overflow Factor for switching Content of up down flag between up and TB1 TX0 TX2 overflow down P Input signal to TAQout Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 3 If switching from an up count to a down count or vice versa while a count is in progress the switch takes effect from the next effective edge of the count source 4 Setting the count start flag to O causes the counter to hold its value and to stop 5 If an overflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 n reload register content 5 Overflow 1 Start count 2 Underflow 4 Stop count i p Start count again Counter content hex 000016 i Set to 1 by software Cleared to 0 i i software Count start flag Up down flag leared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 1 request bit Figure 2 2 12 Operation timing of event counter mode reload type selecte
292. fc o Clock divided couter 8 Division n 1 n 0016 to FF16 Example i When f Xin 10MHz ae Adaress 038E T6 n 0716 approx 19 5kHz Low order 8 bits n 2616 approx 4 0kHz n 4D16 approx 2 0kHz Data bus low order bits n 9B16 approx 1 0kHz Figure 1 19 Block diagram of clock output 22 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Stop Mode Wait Mode Stop Mode Writing 1 to the all clock stop control bit bit 0 at address 000716 stops all oscillation and the microcom puter enters stop mode In stop mode the content of the internal RAM is retained provided that Vcc remains above 2V Because the oscillation of BCLK f1 to f32 fc fc32 and fAD stops in stop mode peripheral functions such as the A D converter and watchdog timer do not function However timer A timer B and timer X operate provided that the event counter mode is set to an external pulse and UARTO functions provided an external clock is selected Table 1 3 shows the status of the ports in stop mode Stop mode is cancelled by a hardware reset or an interrupt If an interrupt is to be used to cancel stop mode that interrupt must first have been enabled If returning by an interrupt that interrupt routine is executed When shifting from high speed medium speed mode to stop mode and at a reset the main clock division select bit 0 bit 6 at address 000616 is set to 1
293. fc e CLK polarity select bit 0 n value set to BRGO e Transmit interrupt cause select bit 0 e Example of receive timing when external clock is selected Receive enable bit RE oy Transmit enable f bit TE o Dummy data is set in UARTO transmit buffer register oy Transmit buffer empty flag TI Transferred from UARTO transmit buffer register to UARTO transmit register CLKO Receive data is taken in RxDO aay Transferred from UARTO receive register Read out from UARTO receive buffer register Receive complete 1 to UARTO receive buffer register flag RI Receive interrupt 1 request bit IR o DA Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Meet the following conditions are met when the CLK External clock is selected input before data reception H e CLK polarity select bit 0 Transmit enable bit gt 1 e Receive enable bit 1 Dummy data write to UARTO transmit buffer register fEXT frequency of external clock Figure 1 75 Typical transmit receive timings in clock synchronous serial I O mode 82 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous serial I O mode a Polarity select function As shown in Figure 1 76 the CLK polarity
294. fective only when selecting the internal clock Switching among pins for outputting the transfer clock allows data trans mission to two external ICs in a time sharing manner e Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from the following the instant the transmission buffer is emptied or the instant the transmission register is emptied When transmis sion buffer empty timing is selected an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register Therefore data can be transmitted in succession When transmission register empty timing is selected an interrupt occurs when data transmission is complete Following are some examples in which various functions a through e are selected e Transmission Operation WITH transmission at falling edge of transfer clock LSB First interrupt at instant transmission buffer is emptied WITHOUT transfer clock output to multiple pins function e Transmission Operation WITH transmission at falling edge of transfer clock LSB First interrupt at instant transmission is completed WITH transfer clock output to multiple pins function UARTO SCISCUON AV AINADIC epsa fagdecchetagiendlareaedey cht anteeehtlaadech ager ented ieee P258 e Reception WITH reception at falling edge of transfer clock LSB First successive reception mode disabled WITHOUT transfer clock output to multiple pins
295. flag B flag This flag chooses a register bank Register bank 0 is selected when this flag is 0 register bank 1 is selected when this flag is 1 e Bit 5 Overflow flag O flag This flag is set to 1 when an arithmetic operation resulted in overflow otherwise cleared to 0 e Bit 6 Interrupt enable flag I flag This flag enables a maskable interrupt An interrupt is disabled when this flag is O and is enabled when this flag is 1 This flag is cleared to 0 when the interrupt is acknowledged RENESAS 13 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU e Bit 7 Stack pointer select flag U flag Interrupt stack pointer ISP is selected when this flag is O user stack pointer USP is selected when this flag is 1 This flag is cleared to 0 when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos 0 to 31 is executed e Bits 8 to 11 Reserved area e Bits 12 to 14 Processor interrupt priority level IPL Processor interrupt priority level IPL is configured with three bits for specification of up to eight processor interrupt priority levels from level 0 to level 7 If a requested interrupt has priority greater than the processor interrupt priority level IPL the interrupt is enabled Bit 15 Reserved area The C Z S and O flags are changed when instructions are execute
296. flag indicates whether the control program was downloaded to the RAM or not using the down load function Check Sum Consistency Bit SR12 This flag indicates whether the check sum matches or not when a program is downloaded for execu tion using the download function ID Check Completed Bits SR11 and SR10 These flags indicate the result of ID checks Some commands cannot be accepted without an ID check Data Reception Time Out SR9 This flag indicates when a time out error is generated during data reception If this flag is attached during data reception the received data is discarded and the microcomputer returns to the command wait state 156 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 1 Flash Memory Version SINGLE CHIP 1 BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I O Mode 1 The below figure shows a circuit application for the standard serial I O mode 1 Control pins will vary according to programmer therefore see the peripheral unit manual for more information Clock input CLKO P53 output P53 BUSY Data input RxDO Data output TxDO M30201 Flash memory version CNVss 1 Control pins and external circuitry will vary according to peripheral unit For more information see the peripheral unit manual 2 In this example the microprocessor mode and standard serial I O mode are switched via a switch Figure
297. flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 Also the output polarity of the TAOOUT pin reverses 3 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAOOUT pin outputs an L level n reload register content 2 Underflow 1 Start count 3 Stop count Start count again a Counter content hex Cleared to 0 by Set to 1 by software _ Software Set to 1 by software Count start flag Pulse output from H TAOOUT pin Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt ee ee request bit ink Figure 2 2 10 Operation timing of timer mode pulse output function selected 184 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting timer mode and functions Selection of timer mode Pulse output function select bit Note 1 Pulse is output TAOOUT pin is a pulse output pin Gate function select bit b4b3 i i l Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period b7 b6 Source XIN 10MHz f X
298. function NOP FSET Enable interrupts Example 2 INT_SWITCH2 FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit MOV W MEM RO Dummy read FSET Enable interrupts Example 3 INT_SWITCHS PUSHC FLG Push Flag register onto stack FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit POPC FLG Enable interrupts The reason why two NOP instructions four when using the HOLD function or dummy read are inserted before FSET in Examples 1 and 2 is to prevent the interrupt enable flag from being set before the interrupt control register is rewritten due to effects of the instruction queue When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener ated This will depend on the instruction If this creates problems use the below instructions to change the register Instructions AND OR BCLR BSET stENESAS 373 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 3 Interrupt Sequence An interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here If an interrupt occurs during executio
299. g a two phase external signal Figure 1 43 shows the timer AO mode register in event counter mode Table 1 13 Timer specifications in event counter mode when not processing two phase pulse signal Item Specification Count source External signals input to TAOIN pin effective edge can be selected by software TB1 overflow TXO overflow TX2 overflow Count operation Up count or down count can be selected by external signal or software When the timer overflows or underflows it reloads the reload register con tents before continuing counting Note Divide ratio 1 FFFF16 n 1 for up count 1 n 1 for down count n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer overflows or underflows TAOIN pin function Programmable I O port or count source input TAOOUT pin function Programmable I O port pulse output or up down count select input Read from timer Count value can be read out by reading timer AO register Write to timer e When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Select function e Free run count function Even when the timer overflows or underflows the reload register content is not reloaded to it e
300. gt A lt gt P01 Kl1 _ lt GD P70 TBOIN XcOUT lt gt 38 lt gt Po2 Kiz RESET gt 6 lt gt Pos Kis N C 550i M30201F6FP POs Kle Connect oscillator Xout lt gt Posikis 5 circuit Vss gt M30201F6TFP lt gt Posikle XIN gt lt gt Po7 KI7 Vcc gt 39 lt gt P10 LEDo P45 TX2INOUT lt gt 13 P44 INT1 TX1 inout lt gt LED2 P43 INTo TXOINouT lt gt P42 RxD1 lt p gt EE Figure 1 102 Pin connection diagram in parallel I O mode 2 136 tENESAS Renesas Technology Corp Appendix Parallel I O Mode Flash memory version Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER User ROM and Boot ROM Areas In parallel I O mode the user ROM and boot ROM areas shown in Figure 1 100 can be rewritten In the boot ROM area an erase block operation is applied to only one 3 5 K byte block The boot ROM area has had a standard serial I O mode control program stored in it when shipped from the Mitsubishi factory Therefore using the device in standard serial input output mode the user does not need to write to the boot ROM area Functional Outline Parallel I O Mode In parallel I O mode bus operation modes Read Output Disable Standby and Write are selected by the status of the CE OE WE VAFY and CNVSs input pins The contents of erase program and other operations are selected by writing a softwa
301. h Interrupt The following is an operation of address match interrupt Figure 2 9 4 shows the set up procedure of address match interrupt and Figure 2 9 5 shows the overview of the address match interrupt handling routine Operation 1 The address match interrupt handling routine sets an address to be used to cause the ad dress match interrupt register to generate an interrupt 2 Setting the address match enable flag to 1 enables an interrupt to occur 3 An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed Setting address match interrupt register gt Address match interrupt register 0 Address 001216 to 001016 RMADO Address match interrupt register 1 Address 001616 to 001416 RMAD1 b23 b20 b19 b16 b15 b8 b7 b4 b3 b0 b7 b0 b7 bo E Can be set to 0000016 to FFFFF16 Setting address match interrupt enable register b7 b0 Address match interrupt enable register Address 000916 AIER Address match interrupt 0 enable bit 1 Interrupt enabled Address match interrupt 1 enable bit 1 Interrupt enabled Figure 2 9 4 Set up procedure of address match interrupt 316 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt C Address match interrupt routine 1
302. he counter starts counting gets a proper value Timer A event counter mode 1 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing gets FFFF16 by under flow or 000016 by overflow Reading the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value 2 When stop counting in free run type set timer again Timer A one shot timer mode 1 Setting the count start flag to O while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TAQOUT pin outputs L level e The interrupt request generated and the timer AO interrupt request bit goes to 1 2 The timer AO interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to one shot timer mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to O after the above listed changes have been made Timer A pulse width modulation mode 1 The timer AO interrupt request bit becomes 1 if setting operation mode of the timer in co
303. he M30201 flash memory version does not have the lock bit so the read value is always 1 block unlock As to V Ai to DQ6 _ Rx M16C reception data _TxDO M16C transmit data P53 BUSY Figure 1 112 Timing for reading lock bit status tENESAS 151 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version Download Command This command downloads a program to the RAM for execution Execute the download command as explained here following 1 Transfer the FA16 command code with the 1st byte 2 Transfer the program size with the 2nd and 3rd bytes 3 Transfer the check sum with the 4th byte The check sum is added to all data sent with the 5th byte onward 4 The program to execute is sent with the 5th byte onward When all data has been transmitted if the check sum matches the downloaded program is executed The size of the program will vary according to the internal RAM Check fogram V Program mpg rae A Aan festa se M16C reception data Fa N sum data ae Data size low TxDO Data size high M16C transmit data P53 BUSY Figure 1 113 Timing for download 152 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 1 Flash Memory Version SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Ver
304. hen the CE and OE pins are low In Read mode the data corresponding to each software command entered is output from the data I O pins Do D7 Output Disable The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high Also the data I O pins are placed in the high impedance state Standby The Standby mode is entered by driving the CE pin high Also the data I O pins are placed in the high impedance state Write The Write mode is entered by applying VPPH to the CNVSs pin and a high voltage to the VRFY pin and then pulling the WE pin low when the CE pin is low and OE pin is high In this mode the device accepts the software commands or write data entered from the data I O pins A program erase or some other operation is initiated depending on the content of the software command entered here The input data such as address is latched at the falling edge of WE pin The input data such as software command is latched at the rising edge of WE pin 138 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version Software Commands Table 1 78 lists the software commands available with the M30201 flash memory version By entering a software command from the data I O pins Do D7 in Write mode specify the content of the operation such as erase or program operation to be performed The following ex
305. hich cannot be enabled disabled by the interrupt enable flag I flag or whose interrupt priority cannot be changed by priority level 28 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts e Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction e Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag O flag set to 1 The following are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB BRK interrupt A BRK interrupt occurs when executing the BRK instruction INT interrupt An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction Software interrupt numbers 0 through 31 are assigned to peripheral I O interrupts so executing the INT instruction allows executing the same interrupt routine that a peripheral I O interrupt does The stack pointer SP used for the INT interrupt is dependent on which software interrupt number is involved So far as software interrupt numbers 0 through 31 are concerned the microcomputer saves the stack pointer assignment flag U flag when it accepts an inte
306. hnology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Timing requirements referenced to Vcc 5V Vss OV at Ta 20 to 85 C unless otherwise specified Extended operating temprature version 40 to 85 C Table 1 46 Timer B input counter input in event counter mode Standard Parameter Min Max tc TB TBiIN input cycle time counted on one edge tw TBH TBiIN input HIGH pulse width counted on one edge tw TBL TBiIN input LOW pulse width counted on one edge tc TB TBIIN input cycle time counted on both edges tw TBH TBiIN input HIGH pulse width counted on both edges tw TBL TBiin input LOW pulse width counted on both edges Table 1 47 Timer B input pulse period measurement mode Standard Parameter Min Max TBIIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Table 1 48 Timer B input pulse width measurement mode Standard Parameter Min Max tc TB TBiIN input cycle time tw TBH TBiIN input HIGH pulse width tw TBL TBiIN input LOW pulse width Table 1 49 Timer X input counter input in event counter mode Standard Parameter Min Max TXiINOUT input cycle time TXiiNOUT input HIGH pulse width TXiiNouT input LOW pulse width Table 1 50 Timer X input gate input in timer mod
307. hoosed functions Count source Input signal to TXiinouT counting falling edges Input signal to TXiINouT counting rising edges Timer overflow TB1 TAO TXi overflow Pulse output function No pulses output Pulses output Count operation type Reload type Free run type Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer Xi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count i i 4 Stop count i p 2 Underflow FFFF16 4 Lanna en ennnnee Start count again gt BR Counter content hex Cleared to 0 by 1 Set to 1 software software Count start flag he Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 4 request bit Q Figure 2 4 12 Operation timing of event counter mode free run type selected 232 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting event counter mode and functions p7 po Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of e
308. i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of timer mode Pulse output function select bit 0 Pulse is not output Set to O when gate function selected Gate function select bit b4 b3 1 1 Timer counts only when TXiINOUT pin is held H Note _________________Q Must always be 0 in timer mode oa source select bit Count Count source period 00 fi 5 SOUICE XIN 10MHz t Xc n 32 768kHz 01 f8 100ns 10 f32 800ns 1 1 fc32 3 2us 976 56us eee Set the corresponding port direction register to 0 input mode Setting divide ratio bs poe Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038c16 TX2 _ Can be set to 000016 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 LP CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Y a Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 7 Set up procedure of timer mode gate function selected
309. ics 5 1 Standard DC Characteristics 0 cccccceceeceeeeeeeeceeeeeeeeeeeeeeeeeeeaeeeeeeeeeeaaeseeeeeeecaeeeseaeeeseeeeseaeeneaes 386 5 1 1 Standard Ports Characteristics 00 c cccceccceeeeeeceeeeeeeeeeeeeeeeeeeaaeeeeeeeesecaeeeeaeeseeeeesiaaeeneeeees 386 5 1 2 Standard Characteristics Of ICC f XIN ccccceeeeeeceeeeeeeeeeeeaeeeeeeeeceaeeeeaeeeseeaeeeeaaeeseeeeeeaaeeee 389 5 2 Standard Characteristics of Pull Up Resistor 0 cccccecceceeeeeeeeeeeeeeeaeeeeeeeeeeaeeeseaeeseeeeeeeaeeneaes 391 5 3 Standard DC Characteristics Flash memory version ceeeeeeeeeeeeeeeeeeeeeeeeeaeeteeeeeeseaaeenenes 392 5 3 1 Standard Ports Characteristics cccccceccceeesceceeeeeeeeaeeeeeeeeeceaaeeseaaeeseaaeeseaaeeseeeeesiaaeeneneees 392 5 3 2 Standard Characteristics Of ICC f XIN cceeeceeeeeeeeeeeeeeeceaeeeeeeeeseaaeeeeaaeeseeaeeeeaaeeseeeeeeaeeeee 394 5 4 Standard Characteristics of Pull Up Resistor Flash memory Version ccccceeeeeeeseeeeeees 395 Quick Reference to Pages Classified by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002Bi16 002Ci6 002D16 002E16 002F16 003016 003116 003216 003316
310. ics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMSs etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 tENESAS Renesas Techno
311. ide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer underflows TBIIN pin function Programmable I O port Read from timer Count value is read out by reading timer Bi register Write to timer e When counting stopped When a value is written to timer Bi register it is written to both reload register and counter e When counting in progress When a value is written to timer Bi register it is written to only reload register Transferred to counter at next reload time Timer Bi mode register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset b X lol TBIMR i 0 1 039B16 to 039C16 00XX00002 Bit symbol Bitname Function R w TMOD b1 bO Operation mode select bit 0 0 Timer mode TMOD1 Invalid in timer mode M Can be 0 or 1 Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate Invalid in timer mode In an attempt to write to this bit write O The value if read in timer mode turns out to be indeterminate Count source select bit b7 b6 00 f1 01 fs 10 f32 1 1 fc32 Figure 1 51 Timer Bi mode register in timer mode RENESAS 61 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 Event counter mod
312. idth measurement mode Item Specification Count source f1 f8 f32 fc32 Count operation e Up count e Counter value 00001 6 is transferred to reload register at measurement pulse s effective edge and the timer continues counting Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing e When measurement pulse s effective edge is input Note 1 e When an overflow occurs Simultaneously the timer Bi overflow flag changes to 1 The ti start flag is 1 anda mer Bi overflow flag changes to 0 when the count value is written to the timer Bi mode register TBIIN pin function Measurement pulse input Read from timer When timer Bi register is read it indicates the reload register s content measurement result Note 2 Write to timer Cannot be written to Note 1 An interrupt request is not generated when the first effective edge is input after the timer has started counting Note 2 The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer Timer Bi mode register b7 b6 b5 b4 b3 b2 bi b0 Sam RRH TBiMR i 0 1 Symbol Address 039B16 039C16 When reset 00XX00002 Operation mode select bit Measurement mode select bit Nothing is assigned In an attempt to write to this bit write
313. ignal s falling edges Counts external signal s MR1 rising edges Counts external signal s falling and rising edges Inhibited Nothing is assigned In an attempt to write to this bit write O The value if read turns out to be indeterminate Invalid in event counter mode In an attempt to write to this bit write 0 The value if read in event counter mode turns out to be indeterminate MR3 TCKO Invalid in event counter mode Can be 0 or 1 TCK1 Event clock select 0 Input from TBiIN pin Note 2 1 TBj overflow j 1 wheni 0 j 0 wheni 1 Note 1 Valid only when input from the TBiIN pin is selected as the event clock If timer s overflow is selected this bit can be O or 1 Note 2 Set the corresponding port direction register to 0 input mode Figure 1 52 Timer Bi mode register in event counter mode 62 stENESAS Renesas Technology Corp Timer B Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 3 Pulse period pulse width measurement mode In this mode the timer measures the pulse period or pulse width of an external signal See Table 1 19 Figure 1 53 shows the timer Bi mode register in pulse period pulse width measurement mode Figure 1 54 shows the operation timing when measuring a pulse period Figure 1 55 shows the operation timing when measuring a pulse width Table 1 19 Timer specifications in pulse period pulse w
314. ime Note When set value of H level width is 0016 or 000016 pulse outputs L level and inversion value FF16 or FFFF 16 is set to timer Timer Xi mode register D7 b6 p3 ba b3 b2 bT bO Address When reset III bhii TAIME 0t02 039716 to 039916 0016 iiid eoma Seme on N 7 TMODO Operation mode b1 bo TMOD1 select bit 1 1 PWM mode MRO 1 Must always be 1 in PWM mode MRI Invalid in PWM mode Can be 0 or 1 MR 16 8 bit PWM mode 0 Functions as a 16 bit pulse width modulator select bit 1 Functions as an 8 bit pulse width modulator TCKO Count source select bit TCK1 MR2 Trigger select bit 0 Count start flag is valid Note 1 1 Selected by event trigger select register eo Note 1 TXiINOUT pin inout cannot be selected by the event trigger select bit addresses 038316 Note 2 Set the corresponding port direction register to 1 output mode Figure 1 66 Timer Xi mode register in pulse width modulation mode stENESAS 73 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Condition Reload register 000316 when trigger timer overflow is selected 1 f x 216 1 a 1 1 1 Count source Trigger signal PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit fi Frequency of count source f1 f8 f32 fc32 Cleared to 0 when
315. imer X related registers 3 tENESAS 67 Renesas Technology Corp Timer X 68 1 Timer mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER In this mode the timer counts an internally generated count source See Table 1 20 Figure 1 60 shows the timer Xi mode register in timer mode Table 1 20 Specifications of timer mode Item Specification Count source f1 f8 f32 fC32 Count operation e Down count When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When the timer underflows TXiINOUT pin function Programmable I O port gate input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer e When counting stopped When a value is written to timer Xi register it is written to both reload register and counter e When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Select function e Gate function Counting can be started and stopped by the TXiINOUT pin s input signal e Pulse output function Each time the timer underflows the TXiINOUT pin s polar
316. in the instruction queue Therefore insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits to 1 3 When the MCU running in low speed or low power dissipation mode do not enter WAIT mode with WAIT peripheral function clock stop bit set to 1 RENESAS 109 Renesas Technology Corp Mitsubishi microcomputers M30201 Group 3 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Interrupts 1 Reading address 0000016 e When maskable interrupt is occurred CPU read the interrupt information the interrupt number and interrupt request level in the interrupt sequence The interrupt request bit of the certain interrupt written in address 0000016 will then be set to 0 Reading address 0000016 by software sets enabled highest priority interrupt source request bit to 0 Though the interrupt is generated the interrupt routine may not be executed Do not read address 0000016 by software 2 Setting the stack pointer e The value of the stack pointer immediately after reset is initialized to 000016 Accepting an inter rupt before setting a value in the stack pointer may become a factor of runaway Be sure to seta value in the stack pointer before accepting an interrupt Concerning the first instruction immediately after reset generating any interrupt is prohibited 3 External interrupt When changing a polarity of pins INTO and INT1 the interrupt request bit may be
317. in the timer Xi register then set the flag to 1 2 Reading the timer Xi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Xi register with the reload timing shown in Figure 2 4 24 gets FFFF16 Reading the timer Xi register after setting a value in the timer Xi regis ter with a count halted but before the counter starts counting gets a proper value Reload Read value Hex GEJ FFFF Time n reload register content Figure 2 4 24 Reading timer Xi register 244 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 13 Precautions for Timer X one shot timer mode 1 To clear reset the count start flag is set to O Set a value in the timer Xi register then set the flag to 1 2 Setting the count start flag to 0 while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TXiINOUT pin outputs L level e The interrupt request generated and the timer Xi interrupt request bit goes to 1 3 The timer Xi interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from
318. ing Low speed mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control Figure 1 21 shows the protect register The values in the processor mode register 0 address 000416 processor mode register 1 address 000516 system clock control reg ister O address 000616 system clock control register 1 address 000716 and port P4 direction register address 03EA16 can only be changed when the respective bit in the protect register is set to 1 There fore important outputs can be allocated to port P4 If after 1 write enabled has been written to the port P4 direction register write enable bit bit 2 at address 000A16 a value is written to any address the bit automatically reverts to 0 write inhibited However the system clock control registers 0 and 1 write enable bit bit O at 000A16 and processor mode register 0 and 1 write enable bit bit 1 at 000A16 do not automatically return to 0 after a value has been written to an address The program must therefore be written to return these bits to 0 Protect register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PRCR 000A16 XXXXX0002 Biemba rot Enables writing to system clock i PRCO control registers 0 and 1 addresses bes ae l 00
319. input the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is transferred to the reload register The timer Xi interrupt request does not generate 3 If an effective edge of a pulse to be measured is input again the value of the counter is transferred to the reload register and the timer Xi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and measurement is started again Note e The timer Xi interrupt request bit goes to 1 when an effective edge of a pulse to be measured is input or timer Xi is overflows The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Xi overflow flag goes to 1 immediately after a count is performed e The timer Xi overflow flag goes to 0 if timer Xi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software 1 Start count 3 Start measurement again 2 Start measurement Count source TULL U UUN H Measurement pulse indeterminate Reload register counter value transfer timing L 7 Transfer us _Transfer measured value Note 1 A Note 1 A Note 1 4 Note 1 A Note 2 Timing at which counter a reaches 000016 Count
320. interrupt number 63 128 to 131 to 252 to 255 Note Note Software interrupt Note Address relative to address in interrupt table register INTB 368 tENESAS Renesas Technology Corp Cannot be masked by flag Interrupt Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 4 2 Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted What is described here does not apply to non maskable interrupts Enable or disable a non maskable interrupt using the interrupt enable flag I flag interrupt priority level selection bit or processor interrupt priority level IPL Whether an interrupt request is present or absent is indicated by the interrupt request bit The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt Also the interrupt enable flag flag and the IPL are located in the flag register FLG Table 4 2 1 shows the memory map of the interrupt control registers and Table 4 2 2 shows the interrupt control registers 004D16 Key input interrupt control register KUPIC 004E16 A D conversion interrupt control register ADIC 005016 i 005216 UARTO receive interrupt control register SORIC 005B16 Timer B1 interrupt control register TB1IC oo5Cs O S O 005D16
321. interrupt request is accepted or cleared by software Timer Xi overflow flag ai Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 64 Operation timing when measuring a pulse period Count source Measurement pulse Transfer Transfer Transfer indeterminate measured measured value value value t Reload register counter transfer timing Timing at which counter reaches 000016 Count start flag Timer Xi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi overflow flag a q __ Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 65 Operation timing when measuring a pulse width 72 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 5 Pulse width modulation PWM mode In this mode the timer outputs pulses of a given width in succession See Table 1 24 In this mode the counter functions as either a 16 bit pulse width modulator or an 8 bit pulse width modulator Figure 1 66 shows the timer Xi mode register in pulse width modulation mode Figure 1 67 shows the example of how a 16 bit pulse width modulator operates Figure 1 68 shows the example of how an 8 bit pulse width modulator operates Table 1 24 Timer specifications in pulse width modulation mode
322. interrupt request is accepted or cleared by software Note1 n 000016 to FFFF 16 Figure 1 67 Example of how a 16 bit pulse width modulator operates Condition Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 Trigger timer overflow is selected 1 fi X m 1 X 28 1 in i Count source Note1 Trigger signal 4 E K l4 1 f X m 1 Underflow signal of 8 bit prescaler Note2 1 fX m 1 Xn 1 1 1 i a 1 1 PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit fi Frequency of count source ft fa 32 fC32 Cleared to 0 when interrupt request is accepted or cleaerd by software Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16 n 0016 to FF16 Figure 1 68 Example of how an 8 bit pulse width modulator operates 74 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Serial I O Serial I O Serial I O is configured as two channels UARTO and UART1 UARTO and UART1 each have an exclusive timer to generate a transfer clock so they operate indepen dently of each other Figure 1 69 shows the block diagram of UARTO and UART1 Figure 1 70 shows the block diagram of the transmit receive unit UARTO has two operation modes a clock synchronous serial I O mode
323. ion of measurement Note 2 Timer has overflowed Figure 2 4 16 Operation timing of pulse period measurement mode 236 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting pulse period pulse width measurement mode and functions b7 b0 7 Timer Xi mode register i 0 to 2 Address 039716 to 039916 TERE trio Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 0 0 Pulse period measurement Interval between measurement pulse falling edge to falling edge Timer Xi overflow flag 0 Timer did not overflow 1 Timer has overflowed 1 Must always be 1 in pulse period pulse width measurement mode N Source selectbit Count Count source period 00 f1 source f Xin 10MHz_ f Xcin 32 768kHz 01 fs 100ns 10 f32 800ns 1 1 fc32 3 295 976 56us Note Set the corresponding port direction register which sets the measurement pulse to 0 input mode F C E Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCcIN by 32 b7 b0 Clock prescaler reset flag Address 0381 16 LADD CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Setting count st
324. ion start flag 0 A D conversion disabled 1 A D conversion started Frequency select bit 0 O fap 4 is selected 1 fAD 2 is selected b3 1 Repeat sweep mode 1 Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D control register 1 Note 1 b7 b6 bS b4 ba be bt bo Symbol Address When reset 0 1 1 ADCON1 03D716 0016 Bit symbol Bit name Function A D sweep pin select bit When single sweep and repeat sweep SCANO mode 1 are selected b1 b0 00 ANo 1 pins 01 ANo AN1 2 pins 1 0 ANo to AN2 3 pins 1 1 ANo to ANs 4 pins Note 2 A D operation mode Set 1 in this mode select bit 1 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode Frequency select bit 1 0 fAD 2 or fAD 4 is selected CKS1 F 1 faD is selected VCUT Vref connect bit 1 Vref connected Set this bit to 0 Di x 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to ANs54 can be used in the same way as for ANo to AN4 Figure 1 89 A D conversion register in repeat sweep mode 1 stENESAS Renesas Technology Corp 97 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter e Sample and hold Samp
325. is selected TX2TGH TX1 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset L KXKXxKKXK TX CPSRF 038116 OXXXXXXX2 Breme __Bitname Fran JEW Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate 0 No effect 1 Prescaler is reset When read the value is O Clock prescaler reset flag Figure 2 4 3 Timer X related registers 2 2CENESAS 223 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 2 Operation of Timer X timer mode In timer mode choose functions from those listed in Table 2 4 1 Operations of the circled items are described below Figure 2 4 4 shows the operation timing and Figure 2 4 5 shows the set up procedure Table 2 4 1 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINOUT pin is at L level Performs count only for the period in which the TXiINOUT pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If
326. is stopped Va NS CMO6 0 Notes 1 3 K High speed mode BCLK Xin CMO7 0 CMO06 0 CM17 0 CM16 0 Medium speed mode divided by 2 mode BCLK f Xin 2 CMO7 0 CMO06 g CM17 0 CM16 1 Medium speed mode divided by 4 mode Medium speed mode divided by 16 mode BCLK f Xin 4 CMO7 0 CMO06 0 CM17 1 CM16 0 BCLK f Xin 16 CMO07 0 CMO6 0 CM17 1 CM16 1 J CM07 CM06 CM04 Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 1 Note 2 CMO05 1 BCLK f XciN CM07 1 Note 1 Note 3 g g q Note 1 Switch clock after oscillation of main clock is sufficiently stable Note 2 Switch clock after oscillation of sub clock is sufficiently stable Note 3 Change CMO06 after changing CM17 and CM16 Note 4 Transit in accordance with arrow Figure 2 11 1 State transition diagram of power control mode 323 2tENESAS Renesas Technology Corp Power Control Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity Reducing the driving capacity after the oscillation stabilizes allow
327. is used as an ana log input voltage For example if 10 bit resolution is used and if VREF reference voltage 5 12 V then 1 LSB width becomes 5 mV and 0 mV 5 mV 10 mV 15 mV 20 mV are used as analog input voltages If analog input voltage is 25 mV absolute accuracy 3LSB refers to the fact that actual A D conversion falls on a range from 00216 to 00816 though an output code 00516 can be ex pected from the theoretical A D conversion characteristics Zero error and full scale error are included in absolute accuracy Also all the output codes for analog input voltage between VREF and AVcc becomes 3FF 16 Output code result of A D conversion Theoretical A D conversion characteristic 10 15 20 25 30 35 Analog input voltage mV Figure 2 7 20 Absolute accuracy 10 bit resolution stENESAS 305 Renesas Technology Corp A D Converter Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Differential non linearity error Differential non linearity error refers to the difference between 1 LSB width based on the theoretical A D conversion characteristics an analog input width that can meet the expectation of outputting an equal code and an actually measured 1 LSB width analog input voltage width that outputs an equal code If 10 bit resolution is used and if VREF reference voltage 5 12 V differential non linearity error 1LSB refers t
328. ister Note 1 Address When reset 038916 038816 Indeterminate 038B16 038A16 Indeterminate 038D16 038C16 Indeterminate Function Values that can be set e Timer mode 000016 to FFFF16 Counts an internal count source Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow e One shot timer mode 000016 to FFFF16 x lo Counts a one shot width Note 2 Pulse period pulse width measurement mode o x Measures a pulse period or width e Pulse width modulation mode 16 bit PWM 000016 to FFFE16 x fe Functions as a 16 bit pulse ca i Note 2 b15 b7 Pulse width modulation mode 8 bit PWM oipo Elenoa Timer low order address functions as an 8 bit a prescaler and high order address functions as an 8 bit 0016 to FFi6 Note 2 pulse width modulator Low order addresses Note 1 Read and write data in 16 bit units Note 2 Use MOV instruction to write to this register Count start flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TABSR 038016 000X00002 r 1 Starts counting Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate TBOS Timer BO count start flag 0 Stops counting TB1S Timer B1 count start flag Tectarercouniing Figure 1 58 Timer X related registers 2 66 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer
329. ity error flag Invalid Note Error sum flag Invalid Note 0 No overrun error 1 Overrun error found 0 No overrun error 1 Overrun error found 0 No framing error 1 Framing error found 0 No parity error 1 Parity error found 0 No error 1 Error found Note Bits 15 through 12 are set to 0 when the receive enable bit is set to 0 Bit 15 is set to O when bits 14 to 12 all are set to O Bits 14 and 13 are also set to O when the lower byte of the UARTi receive buffer register addresses 03A616 and 03AE16 is read out UARTI bit rate generator Note 1 2 b7 bo Address 03A1 16 03A916 When reset Indeterminate Indeterminate Values that can be set Assuming that set value n BRGi divides the count source by n 1 0016 to FF16 Note 1 Write a value to this register while transmit receive halts Note 2 Use MOV instruction to write to this register Figure 2 6 3 UARTi related registers 1 CENESAS Renesas Technology Corp 273 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART UARTI transmit receive mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UiMR i 0 1 03A016 03A816 0016 Function Bit name During clock synchronous serial I O mode Must be fixed to 001 Function During UART mode N 4440 005 32000 05 6 Serial I O mode select bit
330. ity is reversed Timer Xi mode register b7 b6 bd b4 b3 b2 bi bO Symbol Address When reset fol Jofo TXIMR i 0 to 2 039716 to 039916 0016 Errno RW TMODO Operation mode bibo TMOD1 select bit 00 Timer mode MRO Pulse output function 0 Pulse is not output select bit TXiINOUT pin is a normal port pin 1 Pulse is output Note 1 TXiINOUT pin is a pulse output pin i i b4 b3 Gate function select bit 0 X Note 2 Gate function not available eo TXiINOUT pin is a normal port pin 1 0 Timer counts only when TXiINOUT MR2 pin is held L Note 3 1 1 Timer counts only when TXiINOUT pin is held H Note 3 R3 fr M 0 Must always be fixed to 0 in timer mode TCKO Count source select bit TCK1 Note 1 Set the corresponding port direction register to 1 output mode Gate function cannot be selected when pulse output function is selected Note 2 The bit can be 0 or 1 Note 3 Set the corresponding port direction register to 0 input mode Pulse output function cannot be selected when gate function is selected Figure 1 60 Timer Xi mode register in timer mode stENESAS Renesas Technology Corp Timer X Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 Event counter mode In this mode the timer counts an external signal or an internal timer s overflow See Table 1 21 Figure 1 61 shows the timer Xi mode register in event cou
331. k Synchronous Serial I O 5 Function selection For clock synchronous serial I O the following functions can be selected a Function for choosing polarity This function switches the polarity of the transfer clock The following operations are available e Data is input at the falling edge of the transfer clock and is output at the rising edge e Data is input at the rising edge of the transfer clock and is output at the falling edge b Function for choosing which bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7 Choose either of the following e LSB first Data is transmitted from bit 0 e MSB first Data is transmitted from bit 7 c Function for choosing successive reception mode Successive reception mode is a mode in which reading the receive buffer register makes the recep tion enabled status ready In this mode there is no need to write dummy data to the transmit buffer register so as to make the reception enabled status ready But at the time of starting reception read the receive buffer register into a dummy manner Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready e Successive reception mode Reading the reception buffer register makes the reception enabled status ready d Function for outputting transfer clock to multiple pins This function is to switch among pins to output the transfer clock This function is ef
332. l oscillator between XIN and XOUT pins To input an externally generated clock input it to XIN pin XOUT Clock output and open XOUuT pin AVcc AVss Analog power supply input Connect AVss to Vss and AVcc to Vcc respectively VREF Reference voltage input Enter the reference voltage for AD from this pin POo to P07 Input port PO Input H or L level signal or open Pio to P17 Input port P1 Input H or L level signal or open P30 to P35 Input port P3 Input H or L level signal or open P4o to P45 Input port P4 Input H or L level signal or open Input port P5 Input H or L level signal or open Mode entry pin Supply H level when powering on MCU When startup is completed this pin serves the serial input clock This pin sets the type of serial flash programming mode An H level input mode 1 sets the mode to clock synchronous An L level input mode 2 sets the mode to clock asynchronous This pin changes to output after entry into standard serial I O mode P60 to P67 Input port P6 Input H or L level signal or open P70 to P71 Input port P7 Input H or L level signal or open RENESAS 143 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Flash Memory Version Mode setup method CNVss VpPH RESET Vss gt Vcc SCLK Vcc Note Note Apply Vcc when powe
333. l up high with a pull up resistor oio F 0 Not pulled high PU02 P10 to P13 pull up 1 Pulled high O 0 PU03 P14 to P17 pull up o o PU06 P30 to P33 pull up oio PU07 P34 to P35 pull up oio Pull up control register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PUR1 03FD16 0016 RW The corresponding port is pulled oio high with a pull up resistor oio 1 Pulled high joo o o oo oo aa e Port P1 drive capacity control register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset DRR 03FE16 0016 KW Sot P1 N channel output O O transistor drive capaciy O O eee o0 oo oo oo oio oio Figure 2 12 3 Programmable I O ports related registers 2 334 tENESAS Renesas Technology Corp Chapter 3 Examples of Peripheral functions Applications Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Applications This chapter presents applications in which peripheral functions built in the M16C 20 are used They are shown here as examples In practical use make suitable changes and perform sufficient evaluation For basic use see Chapter 2 How to Use Peripheral Functions Here follows the list of applications that appear in this chapter BV LONG PEMOd TIM SIS emisa T S Nad eaeraae P338 e 3 2 Variable period variable duty PWM output eee eee eee eente cette enna e ee ee eaaeeeeeetaaeeeeeeeeaeeeeenena P342 e 3 3 Delayed one shot output eec
334. le and hold is selected by setting bit 0 of the A D control register 2 address 03D416 to 1 When sample and hold is selected the rate of conversion of each pin increases As a result a 28 AD cycle is achieved with 8 bit resolution and 33 oAD with 10 bit resolution Sample and hold can be selected in all modes However in all modes be sure to specify before starting A D conversion whether sample and hold is to be used 98 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Programmable I O Ports There are 43 programmable I O ports PO to P7 Each port can be set independently for input or output using the direction register A pull up resistance for each block of 4 ports can be set The port P1 allows the drive capacity of its N channel output transistor to be set as necessary Figures 1 90 to 1 92 show the programmable I O ports Each pin functions as a programmable I O port and as the I O for the built in peripheral devices To use the pins as the inputs for the built in peripheral devices set the direction register of each pin to input mode When the pins are used as the outputs for the built in peripheral devices they function as outputs regardless of the contents of the direction registers See the descriptions of the respective functions for how to set up the built in peripheral devices 1 Direction registers Figure 1 93 shows the di
335. le in a location outside the flash memory area RENESAS 129 Renesas Technology Corp CPU Rewrite Mode Flash memory version Software Commands Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 75 lists the software commands available with the M30201 flash memory version When CPU rewrite mode is enabled write software commands to the flash command register to specify the operation to erase or program The content of each software command is explained below Table 1 75 List of Software Commands CPU Rewrite Mode First bus cycle Command Read Second bus cycle Address 03B616 Data Do to D7 Mode Address Data Do to D7 Program 03B616 Program address Program data Program verify 03B616 Verify address Verify data Erase 03B616 03B616 2016 Erase verify 03B616 Verify address Verify data Reset 03B616 FF16 Read Command 0016 The read mode is entered by writing the command code 0016 to the flash command register in the first bus cycle When an address to be read is input in one of the bus cycles that follow the content of the specified address is read out at the data bus Do D7 8 bits at a time The read mode is retained intact until another command is written After reset and after the reset command is executed the read mode is set Program Command 4016 The
336. logy Corp tENESAS O D Re T S 5 C Di W M30201 Group User s Manual MITSUBISHI 16 BIT SINGLE CHIP MICROCOMPUTER M16C FAMILY Renesas Electronics REV C 2001 06 www renesas com Keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including produc
337. logy Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Serial I O UARTi transmit receive mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol UiMR i 0 1 Bit name SMDO Serial I O mode select bit Note 1 SMD1 SMD2 CKDIR Internal external clock select bit Note 2 STPS Stop bit length select bit Address 03A016 03A816 When reset 0016 Function During clock synchronous serial I O mode Must be fixed to 001 b2 b1 bO 000 Serial I O invalid 7 01 0 Inhibited 0 1 1 Inhibited 111 Inhibited Internal clock Note 3 External a Note i Invalid Function During UART mode N 4424204006 4400040 Z Transfer data 7 bits long Transfer data 8 bits long Transfer data 9 bits long Serial I O invalid Inhibited Inhibited Inhibited Internal clock Note 3 External clock Note 4 0 One stop bit 1 Two stop bits 40004445 PRY Odd even parity select bit Invalid Valid when bit 6 1 0 Odd parity 1 Even parity PRYE Parity enable bit SLEP Sleep select bit Must always be 0 0 Sleep mode deselected 1 Sleep mode selected Invalid Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 UART1 can use only internal clock Must set this bit to 1 Note 3 Set the corresponding port direction register to 1 output mode Note 4 Set the corresponding port direction regist
338. mands addresses and data are input and output between the MCU and peripheral units serial programer etc using clock synchronized serial I O UARTO and P53 BUSY Standard serial I O mode 1 is engaged by releasing the reset with the P53 BUSY pin H level In reception software commands addresses and program data are synchronized with the rise of the transfer clock that is input to the CLKo pin and are then input to the MCU via the RxDo pin In transmis sion the read data and status are synchronized with the fall of the transfer clock and output from the TxDo pin The TxDo pin is for CMOS output Transfer is in 8 bit units with LSB first When busy such as during transmission reception erasing or program execution the P53 BUSY pin is H level Accordingly always start the next transfer after the P53 BUSY pin is L level Also data and status registers in memory can be read after inputting software commands Status such as the operating state of the flash memory or whether a program or erase operation ended successfully or not can be checked by reading the status register Here following are explained software commands status registers etc RENESAS 147 Renesas Technology Corp Appendix Standard Serial I O Mode 1 Flash Memory Version Software Commands Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 79 lists software commands In the standard serial I O mode 1 erase
339. me of acceptance of an interrupt request is even or odd Ifthe content of the stack pointer Note is even the content of the flag register FLG and the content of the program counter PC are saved 16 bits at atime If odd their contents are saved in two steps 8 bits at atime Figure 1 28 shows the operation of the saving registers Note When any INT instruction in software numbers 32 to 63 has been executed this is the stack pointer Figure 1 indicated by the U flag Otherwise it is the interrupt stack pointer ISP 1 Stack pointer SP contains even number Address SP 5 Odd SP 4 Even SP 3 Odd SP 2 Even SP 1 Odd SP Even Sequence in which order registers are saved Stack area Program counter PCL 2 Saved simultaneously Program counter PCm all 16 bits Flag register FLG 1 Saved simultaneously Flag register Program all 16 bits FLGu counter PCx Finished saving registers in two operations 2 Stack pointer SP contains odd number Address SP 5 Even SP 4 Odd SP 3 Even SP 2 Odd SP 1 Even SP Odd Stack area Sequence in which order registers are saved Program counter PCL Program counter PCm Saved simultaneously Il 8 bi Flag register FLG all 8 bits Flag register Program FLGu counter PCx Finished saving registers in four operations Note SP denotes the initial v
340. mer BO interrupt processing High speed oo High speed re r gt O e a Low speed Low speed Low speed i Low speed Figure 3 7 1 Operation timing of controling power using wait mode 358 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications Initial condition b7 b0 Syst lock trol register 0 Add 000616 o Jolt fol on clock control register ress WAIT peripheral function clock stop bit 0 Do not stop peripheral function clock in wait mode XCIN XCOUT drive capacity select bit Port Xc select bit 1 Functions as XcIN XCOUT oscillator Main clock XIN XOUT stop bit 0 Oscillating Main clock divide ratio select bit 0 System clock select bit 0 XIN XOUT 0 T Timer BO mode register Address 039B16 TBOMR Operation mode select bit b1 b0 0 0 Timer mode Count source select bit b7 b6 1 1 fc32 f XCIN divided by 32 b15 b8 b7 0316 FFie Toe BO register Address 039116 039016 b7 bO Clock t flag Add 0381 rt DIXXDIKIXD Clock ere er reset flag Address 16 Rrescaler is reset b7 bo 1 Count start flag Address 038016 LP rasee TBO start counting b7 b0 PPPPI PPH U ai interrupt control register Address 005A16 TBO interrupt priority level INTO interrupt control register Address 005D16 INTOIC INTO interrupt priority level
341. mer Bi interrupt request bit goes to 1 2 When the first effective edge is input after a count is started an indeterminate value is transferred to the reload register At this time timer Bi interrupt request is not generated Timer X timer mode 1 Reading the timer Xi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Xi register with the reload timing gets FFFF16 Reading the timer AO register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value Timer X event counter mode 1 Reading the timer Xi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Xi register with the reload timing gets FFFF16 by underflow or 000016 by overflow Reading the timer Xi register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value 2 When stop counting in free run type set timer again Timer X one shot timer mode 1 Setting the count start flag to 0 while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TXiINOUT pin outputs L level e The interrupt request generated and the timer Xi interrupt request bit goes to 1 2 The timer Xi interrupt request bit g
342. mer Xi interrupt request bit to detect only overflows Use the timer Xi overflow flag only to determine the interrupt factor within the interrupt routine 5 When the first effective edge is input after a count is started an indeterminate value is trans ferred to the reload register At this time timer Xi interrupt request is not generated 6 The value of the counter is indeterminate at the beginning of a count Therefore the timer Xi overflow flag may go to 1 immediately after a count is started 7 If changing the measurement mode select bit is set after a count is started the timer Xi interrupt request bit goes to 1 8 If the input signal to the TXiINOUT pin is affected by noise precise measurement may not be performed in some cases It is recommended to see that measurements fall within a specific range by use of software 9 For pulse width measurement pulse widths are successively measured Use software to check whether the measurement result is an H level width or an L level width 246 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 15 Precautions for Timer X pulse width modulation mode 1 To clear reset the count start flag is set to O Set a value in the timer Xi register then set the flag to 1 2 The timer Xi interrupt request bit becomes 1 if setting operation mode of the timer
343. mer mode pulse output FUNCTION operation 2 2 eee cece eeeee cette eee eee ee eeaeeeeeeeaaeeeeeeeaeeeeeeeaea P228 b Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers The free run type in which nothing is reloaded from the reload register can be selected when an underflow occurs The pulse output function can also be selected Event counter MODS OPSlAUlON ipone pnei enS A ENAERE KEEA ARES P230 e Event counter mode free run type operation cceceeceeeceeeseeeeeeeeeeeeeeseeeeeeeaeeseeneeessaeeeneneees P232 c One shot timer mode In this mode the timer is started by the trigger and stops when the timer goes to 0 The trigger can be selected from the following 3 types an external input signal an overflow of the timer or a software trigger e One shot timer mode operation ececeeeececeeeeeeeeeeeeeeeeeeecaeeeeeaeeeceaeeeesaaeeseeeeesaaaeseneeeessaaeeseaaees P234 d Pulse period measurement pulse width measurement mode External pulse period or external pulse widths are measured If pulse period measurement mode is selected the periods of input pulses are continuously measured If pulse width measurement mode is selected widths of H level pulses and those of L level pulses are continuously measured e Operation in pulse period measurement MOE eceeececesesteeeeeesenteeeeeesseeeeeeeeseeeeeeesseeeeeeees P236 e Operation in pulse width
344. mit buffer register Receive enable bit Note 2 Reception disabled Reception enabled Receive complete flag No data present in receive buffer register Data present in receive buffer register Nothing is assigned Function During UART mode Transmission disabled Transmission enabled Data present in transmit buffer register No data present in transmit buffer register Reception disabled Reception enabled No data present in receive buffer register Data present in receive buffer register In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 If you are using clock asynchronous serial I O mode you can enable receive enable bit when RxD port input is H If RxD port input is L and you have enabled receive enable bit then receive operation starts immediately UART transmit receive control register 2 b7 b6 b5 b4 b3 b2 bi b0 Address 03B016 Symbol UCON When reset XX0000002 Function During clock synchronous serial I O mode UARTO transmit interrupt cause select bit 0 Transmit buffer empty Tl 1 1 Transmission completed TXEPT 1 UART1 transmit interrupt cause select bit Set this bit to 0 Continuous receive mode disabled Continuous receive mode enable UARTO continuous receive mode enable bit
345. mode The timer measures an external signal s pulse period or pulse width e Pulse width modulation PWM mode The timer outputs pulses of a given width Data bus high order bits Clock source selection Timer One shot fi o PWM Low order High order fg O Pulse period pulse width measurement 8 bits 8 bits O O f32 O Timer Reload register 16 functi a to i TXiINOUT Event counter O i 0 to 2 Polarity Counter 16 O switching and edge pulse Clock selection Count start flag Counter reset circuit O o TB1 overflow External 4 O trigger 1 TAO 2 TX1 when TXO 2 _O 1 TXO 2 TX2 when TX1 1 TX1 2 TAO when TX2 Pulse output lt Toggle flip flop Figure 1 56 Block diagram of timer X Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TXiMR i 0 to 2 039716 to 039916 0016 Bit symbol A mone Operation mode 00 Timer mode select bit 01 Event counter mode TMOD1 1 0 One shot timer mode or pulse period pulse width measurement mode 1 1 Pulse width modulation PWM mode MR1 MR2 MR3 TCKO Count source select bit TCK1 Function varies with each operation mode Function varies with each operation mode Eze Figure 1 57 Timer X related registers 1 stENESAS 65 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Timer Xi reg
346. modulation mode 8 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 2 12 Operations of the circled items are described below Figure 2 2 26 shows the operation timing and Figure 2 2 27 shows the set up procedure Table 2 2 12 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Operation 1 If the TAOIN pin input level changes from H to L with the count start flag set to 1 the counter performs a down count on the count source Also the TAQOUT pin outputs an H level 2 The TAQOUT pin output level changes from H to L when a set time period elapses At this time the timer AO interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAOOUT pin outputs an L level Note e PWM pulse cycle is m 1 x 28 1 fi whereas H level duration is n x m 1 fi However when 0016 is set for the significant 8 bits of the timer AO register the PWM outp
347. mory sequentially one byte at a time Execute the page program command as explained here following 1 Transfer the 4116 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 From the 4th byte onward as write data Do D7 for the page 256 bytes specified with addresses As to A23 is input sequentially from the smallest address first that page is automatically written When reception setup for the next 256 bytes ends the RTS1 BUSY signal changes from the H to the L level The result of the page program can be known by reading the status register For more information see the section on the status register RxDO data255 M16C reception data _TxDO M16C transmit data Figure 1 123 Timing for the page program 162 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 2 Flash Memory Version S NOH5 OHIP 16 BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks Execute the erase all unlocked blocks command as explained here following 1 Transfer the A716 command code with the 1st byte 2 Transfer the verify command code D016 with the 2nd byte With the verify command code the erase operation will start and continue for all blocks in the flash memory When block erasing ends the RTS1 BUSY signal changes from the
348. mp hold bit is disabled stENESAS 309 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer 2 8 Watchdog Timer 2 8 1 Overview The watchdog timer can detect a runaway program using its 15 bit timer prescaler The following is an overview of the watchdog timer 1 Watchdog timer start procedure When reset the watchdog timer is in stopped state Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start performing a down count The watchdog timer once started operating cannot be stopped by any means other than stopping conditions 2 Watchdog timer stop conditions The watchdog timer stops in any one of the following states a Period in which the CPU is in stopped state b Period in which the CPU is in waiting state 3 Watchdog timer initialization The watchdog timer is initialized to 7FFF16 in the cases given below and begins a down count a When the watchdog timer writes to the watchdog timer start register while a count is in progress b When the watchdog timer underflows 4 Runaway detection When the watchdog timer underflows a watchdog timer interrupt occurs In writing a program write to the watchdog timer start register before the watchdog timer underflows The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag I flag In processing a watchdog timer
349. mple amp hold function when using the A D converter at Vcc 2 7 4 0V L Have you selected 8 bit mode when using the A D converter at Vcc 2 7 4 0V tENESAS 397 Renesas Technology Corp Appendix 2 Hexadecimal instruction CODE table Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER The next instruction is arranged in each CODE D7 to D4 0000 0001 0010 0011 0100 0101 0110 0111 D3 to DO 0 1 2 3 4 5 6 7 0000 0 BRK AND B S ADD B S MOV B S BCLR S BNOT S JMP S MULU B ROH ROL ROH ROL ROH AO 0 11 SB 0 11 SB abel src dest 0001 1 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S JMP S MULU W ROL dsp 8 SB dsp 8 SB ROL dsp 8 SB ROL dsp 8 SB A0 1 11 SB 1 11 SB abel src dest 0010 2 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S JMP S MOV B G ROL dsp 8 FB dsp 8 FB ROL dsp 8 FB ROL dsp 8 FB A0 2 11 SB 2 11 SB abel src dest 0011 3 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S JMP S MOV W G ROL abs16 abs16 ROL abs16 ROL abs16 A0 3 11 SB 3 11 SB abel src dest 0100 4 NOP AND B S ADD B S MOV B S BCLR S BNOT S JMP S CODE_74 ROL ROH ROL ROH ROGk A1 4 11 SB 4 11 SB abel 0101 5 MOV B S AND B S BCLR S ROH dsp 8 SB dsp 8 SB ROH dsp 8 SB ROH dsp 8 SB A1 5 11 SB 0110 6 MOV B S AND B S BCLR S ROH dsp 8 FB dsp 8 FB ROH dsp 8 FB ROH dsp 8 FB A1 6 11 SB 0111 7 MOV B S AND B S ADD B S MOV B S BCLR S ROH abs16 abs16 RO
350. mpliance with any of the following procedures e Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to O after the above listed changes have been made 2 Setting the count start flag to O while PWM pulses are being output causes the counter to stop counting If the TAOOUT pin is outputting an H level in this instance the output level goes to L and the timer AO interrupt request bit goes to 1 If the TAOOUT pin is outputting an L level in this instance the level does not change and the timer AO interrupt request bit does not becomes 1 RENESAS 107 Renesas Technology Corp Mitsubishi microcomputers M30201 Group 3 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Timer B timer mode event counter mode 1 Reading the timer Bi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Bi register with the reload timing gets FFFF16 Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value Timer B pulse period pulse width measurement mode 1 If changing the measurement mode select bit is set after a count is started the ti
351. ms The watchdog timer is initialized by writing to the watchdog timer start register address OOOE16 and when a watchdog timer interrupt request is generated The prescaler is initialized only when the microcomputer is reset After a reset is cancelled the watchdog timer and prescaler are both stopped The count is started by writing to the watchdog timer start register address 000E16 In stop mode and wait mode the watchdog timer and prescaler are stopped Counting is resumed from the held value when the modes are released Figure 1 34 shows the block diagram of the watchdog timer Figure 1 35 shows the watchdog timer related registers Prescaler Watchdog timer interrupt request Watchdog timer e gt Write to the watchdog timer start register address 000E16 RESET o Figure 1 34 Block diagram of watchdog timer 46 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog timer control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset lojo WDC 000F16 000XXXXX2 Bit symbol High order bit of watchdog timer Reserved bit Must always be set to 0 a Reserved bit Must always be set to 0 o0 WDC7 Prescaler select bit 0 Divided by 16 1 Divided by 128 Watchdog timer start register br bo Symbol Address When reset LY WDTS 000E16
352. n Normal processing operation The timer counts up rising edges or counts down falling edges on the TAOIN pin when input signal on the TAQOUT pin is H TAQOUT TAOIN A i A B 1 Up Up Up Down Down Down count count count count count count Multiply by 4 processing operation If the phase relationship is such that the TAOIN pin goes H when the input signal on the TAOQOUT pin is H the timer counts up rising and falling edges on the TAQOUT and TAOIN pins If the phase relationship is such that the TAOIN pin goes L when the input signal on the TAOQOUT pin is H the timer counts down rising and falling edges on the TAOOUT and TAOIN pins TaoouT fy dy f vaviy as ee Count up all edges Count down all edges s a Count up all edges Count down all edges Note This does not apply when the free run function is selected 54 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer AO mode register When using two phase pulse signal processing b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TAOMR 039616 0016 of tfofojols O J meee on fol TMODO Operation mode select bit o n a r oO TMOD vent counter mode OO 0 Must Aa be 0 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processo Must always be 1 when using two phase
353. n 1 Reception enabled 3 Reception is complete 1 2 Start reception 4 Read of reception data 1 i Receive enable bit RE Transmit enable bit TE Dummy data is set in UARTO transmit buffer register Transmit buffer empty flag TI Transferred from UARTO transmit buffer register to UARTO transmit register 1 fext QD Reception data is taken in RxDO Transferred from UARTO receive register Read out from UARTO receive buffer register Receive complete q to UARTO receive buffer register DN flag RI _ Receive interrupt request bit IR Pad Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Make sure that the following conditions are met when e External clock is selected the CLKO pin input H before data reception e CLK polarity select bit 0 e Transmit enable bit 1 e Receive enable bit gt 1 e Dummy data write to UARTO transmit buffer register fEXT frequency of external clock Figure 2 5 11 Operation timing of reception in clock synchronous serial I O mode tENESAS Renesas Technology Corp 263 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Setting UARTO transmit receive mode register b7 b0 0 7 of oy 1 oli UARTO transmit receive mode register UOM
354. n Microcomputer mode 0000016 0040016 YYYYY16 DF00016 Collective erasable programmable DFDFF16 XXXXX16 Collective User ROM erasable area programmable FFFFF16 Parallel I O mode Boot ROM area 3 5K bytes User ROM area Collective erasable programmable CPU rewrite mode Standard serial I O mode Boot ROM area 3 5K bytes User ROM area Note 1 In CPU rewrite and standard serial I O modes the user ROM is the only erasable programmable area Note 2 In parallel I O mode the area to be erased programmed can be selected by the address A17 input The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low Type No XXXXX16 YYYYY16 M30201F6 F400016 00BFF16 126 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Flash memory version CPU Rewrite Mode In CPU rewrite mode the on chip flash memory can be operated on read program or erase under control of the Central Processing Unit CPU In CPU rewrite mode the flash memory can be operated on by reading or writing to the flash memory control register and flash command register Figure 1 97 Figure 1 98 show the flash memory control register and flash command register respectively Also in CPU rewrite mode the CNVSs pin is used as the VPP power supply pin Apply the power
355. n UND instruction Overflow FFFE016 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716 If the vector contains FF 16 program execution starts from the address shown by the vector in the variable vector table Address match FFFE816 to FFFEBi6 There is an address matching interrupt enable bit Single step Note FFFEC16 to FFFEF 16 Do not use Watchdog timer FFFFO16 to FFFF316 DBC Note FFFF416 to FFFF716 Do not use FFFF816 to FFFFB16 Reset Note Interrupts used for debugging purposes only FFFFC16 to FFFFF 16 2tENESAS Renesas Technology Corp 367 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt e Variable vector tables The addresses in the variable vector table can be modified according to the user s settings Indicate the first address using the interrupt table register INTB The 256 byte area subsequent to the ad dress the INTB indicates becomes the area for the variable vector tables One vector table comprises four bytes Set the first address of the interrupt routine in each vector table Table 4 1 2 shows the interrupts assigned to the variable vector tables and addresses of vector tables Table 4 1 2 Interrupts assigned to the variable vector tables and addresses of vector tables Vector table address Address L to address H Software interrupt number Interrupt sou
356. n maskable interrupt is occurred CPU read the interrupt information the interrupt number and interrupt request level in the interrupt sequence The interrupt request bit of the certain interrupt written in address 0000016 will then be set to 0 Reading address 0000016 by software sets enabled highest priority interrupt source request bit to 0 Though the interrupt is generated the interrupt routine may not be executed Do not read address 0000016 by software 2 Setting the stack pointer e The value of the stack pointer immediately after reset is initialized to 000016 Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway Be sure to set a value in the stack pointer before accepting an interrupt Concerning the first instruction immediately after reset generating any interrupts is prohibited 3 External interrupt e Either an L level or an H level of at least 250 ns width is necessary for the signal input to pins INTO and INT1 regardless of the CPU operation clock e When changing a polarity of pins INTO and INT1 the interrupt request bit may become 1 Clear the interrupt request bit after changing the polarity Figure 1 33 shows the switching condition of INT inter rupt request Clear the interrupt enable flag to 0 Disable interrupt Set the interrupt priority level to level 0 Disable INTi interrupt Set the polarity select bit Clear the interrupt request bit
357. n of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle If an interrupt occurs during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence In the interrupt sequence the processor carries out the following in sequence given 1 CPU gets the interrupt information the interrupt number and interrupt request level by reading ad dress 0000016 2 Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in the temporary register Note within the CPU 3 Sets the interrupt enable flag I flag the debug flag D flag and the stack pointer select flag U flag to 0 the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed 4 Saves the content of the temporary register Note 1 within the CPU in the stack area 5 Saves the content of the program counter PC in the stack area 6 Sets the interrupt priority level of the accepted instruction in the IPL After the interrupt sequence is completed the processor resumes executing instructions from the first address of the interrupt routine Note This register cannot be utilized by the user 4 3 1 Interrupt Response Time Interrupt r
358. n register which inputs the pulse to 0 input mode d Two phase pulse signal processing select bit bO b7 Up d fl Add 0384 ODDI DDD ube Address 038416 Timer AO two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled b7 b0 Trigger select register Address 038316 olo trigcer E 00 Must always be 00 when using two phase pulse signal processing S Setting divide ratio b15 b8 b7 bO b7 b0 re ns Timer AO register Address 038716 038616 TAO _ Can be set to 000016 to FFFF16 a J Setting count start flag b7 b0 Count start flag Address 038016 UT TABSR Timer AO count start flag Start count Figure 2 2 19 Set up procedure of2 phase pulse signal process in event counter mode multiply by 4 mode selected stENESAS 193 Renesas Technology Corp Mitsubishi microcomputers M30201 Group LY SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 9 Operation of Timer A one shot timer mode In one shot timer mode choose functions from those listed in Table 2 2 9 Operations of the circled items are described below Figure 2 2 20 shows the operation timing and Figure 2 2 21 shows the set up procedure Table 2 2 9 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input f
359. n started Frequency select bit 0 0 fap 4 is selected 1 fAD 2 is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 When changing A D operation mode set analog input pin again Note 3 AN50 to AN54 can be used in the same way as for ANo to AN4 Figure 2 7 2 A D converter related registers 1 RENESAS 287 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Note 3 ANso to ANs4 can be used in the same way as for ANo to ANa A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset To TL TTT Atan 03D716 0016 Bitsymbol ___Bitname Function RWI A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins 1 0 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins 1 1 1 1 1 1 1 1 1 1 L When repeat sweep mode 1 is selected e b1 b0 00 ANo 1 pin 0 1 ANo AN1 2 pins 1 0 ANo to AN2 3 pins 11 ANo to AN8 4 pins Note 2 3 i amp A D operation mode 0 Any Mode other than repeat sweep select bit 1 mode 1 Repeat sweep mode 1 BITS 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode CKS1 Frequency select bit 1 0 fap 2 or fAD 4 is selected 1 faD is selected Vref connect bit 0 Vref not connected VCUT 1 Vref connected joo
360. ndard serial I O mode are switched via a switch Figure 1 135 Example circuit application for the standard serial I O mode 2 RENESAS 169 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 52P4B MMP Plastic 52pin 600mil SDIP EIAJ Package Code JEDEC Code Weight g Lead Material SDIP52 P 600 1 78 5 1 Alloy 42 Cu Alloy AANAAANANANAAAANANANANANA Q i EE eee A i oE D Dimension in Millimeters Symbol Min Nom Max A 5 5 i A1 0 51 j A2 3 8 lt b 0 4 0 5 0 59 b1 0 9 1 0 1 3 VARVARA b2 0 65 0 75 1 05 UU UU c 0 22 0 27 0 34 D 45 65 45 85 46 05 E 12 85 13 0 13 15 e 1 778 SEATING PLANE 15 24 L 3 0 0 0 15 56P6S A Plastic 56pin 10X10mm body QFP EIAJ Package Code JEDEC Code Weight g Lead Material Mp QFP56 P 1010 0 65 0 59 Alloy 42 a Id Recommended Mount Pad Dimension in Millimeters Symbol Min Nom Max A 3 05 Ai 0 0 1 0 2 A2 2 8 b 0 25 0 3 0 4 c 0 13 0 15 0 2 D 9 8 10 0 10 2 E e 9 8 10 0 10 2 0 65 HD 12 5 12 8 13 1 HE 12 5 12 8 13 1
361. nded before executing the next command Data and status registers in memory can be read after transmitting software commands Status such as the operating state of the flash memory or whether a program or erase operation ended successfully or not can be checked by reading the status register Here following are explained initial communications with peripheral units how frequency is identified and software commands Initial communications with peripheral units After the reset is released the bit rate generator is adjusted to 9 600 bps to match the oscillation fre quency of the main clock by sending the code as prescribed by the protocol for initial communications with peripheral units Figure 1 119 1 Transmit B016 from a peripheral unit If the oscillation frequency input by the main clock is 10 MHz the MCU with internal flash memory outputs the B016 check code If the oscillation frequency is anything other than 10 MHz the MCU does not output anything 2 Transmit 0016 from a peripheral unit 16 times The MCU with internal flash memory sets the bit rate generator so that 0016 can be successfully received 3 The MCU with internal flash memory outputs the B016 check code and initial communications end successfully 1 Initial communications must be transmitted at a speed of 9 600 bps and a transfer interval of a minimum 15 ms Also the baud rate at the end of initial communications is 9 600 bps 1 If the peripheral unit ca
362. ned 2 Sub clock The sub clock is generated by the sub clock oscillation circuit No sub clock is generated after a reset After oscillation is started using the port Xc select bit bit 4 at address 000616 the sub clock can be selected as BCLK by using the system clock select bit bit 7 at address 000616 However be sure that the sub clock oscillation has fully stabilized before switching After the oscillation of the sub clock oscillation circuit has stabilized the drive capacity of the sub clock oscillation circuit can be reduced using the XCIN XCOUT drive capacity select bit bit 3 at address 000616 Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation This bit changes to 1 when shifting to stop mode and at a reset 3 BCLK The BCLK is the clock that drives the CPU and is fc or the clock is derived by dividing the main clock by 1 2 4 8 or 16 The BCLK is derived by dividing the main clock by 8 after a reset The main clock division select bit O bit 6 at address 000616 changes to 1 when shifting from high speed medium speed to stop mode and at reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained 4 Peripheral function clock f1 f8 32 fAD The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32 The peripheral function clock is stopped by stopping the main clock or by s
363. nerating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 L PPPOP CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 0 Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Clearing overflow flag E PO Timer Xi mode register i 0 to 2 Address 039716 to 039916 T o txime 0 to 2 Timer Xi overflow flag 0 Timer did not overflow Figure 2 4 19 Set up procedure of pulse width measurement mode stENESAS 239 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 10 Operation of Timer X pulse width modulation mode 16 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 4 9 Operations of the circled items are described below Figure 2 4 20 shows the operation timing and Figure 2 4 21 shows the set up procedure Table 2 4 9 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition Timer overflow TB1 TAO TXi overflow Operation 1 Selected timer overflow is generated with the count start flag set to 1 the counter performs a down count on the count source Also
364. ng clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 Me b0 AAAA ATA Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 bo Count start flag Address 038016 CTA E TABSR Timer AO count start flag Setting one shot start flag b7 bo KKK LLL 1 One shot start flag Address 038216 ONSF L Timer AO one shot start flag Start count Figure 2 2 21 Set up procedure of one shot mode RENESAS 195 Renesas Technology Corp Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 10 Operation of Timer A one shot timer mode external trigger selected In one shot timer mode choose functions from those listed in Table 2 2 10 Operations of the circled items are described below Figure 2 2 22 shows the operation timing and Figure 2 2 23 shows the set up procedure Table 2 2 10 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow
365. nnot receive B016 successfully change the oscillation frequency of the main clock Peripheral unit MCU with internal flash memory a ae ee Reset r If the oscillation frequency input PEE i by the main clock is 10 MHz the eemransfer 0016F 6times r ae T MCU outputs B016 If other than 1 Transfer B016 10 MHz the MCU does not output anything At least 15ms transfer interval 3 Transfer check code B016 The bit rate generator setting completes 9600bps Figure 1 119 Peripheral unit and initial communication 158 stENESAS Renesas Technology Corp How frequency is identified Mitsubishi microcomputers M30201 Group Appendix Standard Serial I O Mode 2 Flash Memory Version SN tE CHIP 16 BIT CMOS MICROCOMPUTER When 0016 data is received 16 times from a peripheral unit at a baud rate of 9 600 bps the value of the bit rate generator is set to match the operating frequency 2 10 MHz The highest speed is taken from the first 8 transmissions and the lowest from the last 8 These values are then used to calculate the bit rate generator value for a baud rate of 9 600 bps Baud rate cannot be attained with some operating frequencies Table 1 82 gives the operation frequency and the baud rate that can be attained for Table 1 82 Operation frequency and the baud rate Operation frequency Baud rate MHz 9 600bps 10MHz Baud rate 19 200bps a Baud rate 38 400bps Baud rate 57 60
366. nology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix 1 Check Sheet Appendix 1 Check Sheet The following check sheet was created based on items which had been the source of problems in the past We recommend you refer to the check sheet when troubleshooting Checks regarding register initial settings L Has the initial setting been made in the interrupt stack pointer ISP at the top of the program L Has the initial setting been made in the user stack pointer USP Only if using the USP LI Does the USP overlap the ISP area Only if using the USP O Is interrupt enabled after setting the ISP and USP L Is the top address of the variable interrupt vector table set in the interrupt table register INTB O Is interrupt enabled after setting the INTB L Has the initial setting been made in the frame base register FB Only if using the FB LC Has the initial setting been made in the stack base register SB Only if using the SB Checks regarding the internal memory L Does the RAM capacity used in the program exceed the RAM capacity of the microcomputer LI Does the ROM capacity used in the program exceed the ROM capacity of the microcomputer Checks regarding the protect register L Is writing enabled in the protect register address 000A16 before writing in the system clock control register addresses 000616 and 000716 L Is writing enabled in the protect register bef
367. nter mode Table 1 21 Timer specifications in event counter mode when not processing two phase pulse signal Item Specification Count source External signals input to TXiINOUT pin effective edge can be selected by software TB1 overflow TAO overflow TXi overflow Count operation Down count When the timer underflows it reloads the reload register contents before continuing counting Note Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer underflows TXiINOUT pin function Programmable I O port count source input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer e When counting stopped When a value is written to timer Xi register it is written to both reload register and counter e When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Select function e Free run count function Even when the timer underflows the reload register content is not reloaded to it e Pulse output function Each time the timer underflows the TXiINOUT pin s polarity is reversed Note This does not apply when the free run function is selected Timer Xi mode register b7 b6 b5 b4 b3 b2 bi bO o
368. nterrupt control register TX1IC 005816 _ Timer X2 interrupt control register TX2IC 005916 oo5a16 _ Timer BO interrupt control register TBOIC 005Bie _ Timer B1 interrupt control register TB1IC 34 005C16 005D16 INTO interrupt control register INTOIC 005E16 INT1 interrupt control register INT11C of 005F16 Quick Reference to Pages Classified by Address Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 O3AA16 03AB16 03AC16 03AD16 O3AE16 O3AF 16 Register Page Count start flag TABSR 50 Clock prescaler reset flag CPSRF One shot start flag ONSF Trigger select register TRGSR 51 Up down flag UDF 50 Timer AO TAO 50 Timer XO TX0 Timer X1 TX1 Timer X2 TX2 66 Clock divided counter CDC Timer BO TBO Timer B1 TB1 60 Timer AO mode register TAOMR 49 Timer XO mode register TXOMR Timer X1 mode register ea e a TX1MR Timer X2 mode register TX2MR 65 Timer BO mode register TBOMR Timer B1 mode register TB1MR 59 UARTO transmit receive mode registe
369. ntrol register 0 Address 03D616 ADCONO L A D conversion start flag 0 A D conversion disabled Ke Stop A D conversion Figure 2 7 8 Set up procedure of repeat mode stENESAS 293 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 4 Operation of A D Converter in single sweep mode In single sweep mode choose functions from those listed in Table 2 7 4 Operations of the circled items are described below Figure 2 7 9 shows timing chart and Figure 2 7 10 shows the set up procedure Table 2 7 4 Choosed functions Operation clock AD Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit Analog input pin ae AN1 2 pins ANo to AN8 4 pins ANo to AN5 6 pins ANo to AN7 8 pins Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo AN50 pin 2 After the A D conversion of voltage input to the ANo AN50 pin is completed the content of the successive comparison register conversion result is transmitted to A D register 0 The A D converter converts all analog input pins selected by the user The conversion result is trans mitted to A D register i corres
370. o 1 and event trigger select bits addresses 038316 to 00 Figure 1 42 Timer AO mode register in event counter mode stENESAS 53 Renesas Technology Corp Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 14 Timer specifications in event counter mode when processing two phase pulse signal Specification Count source Two phase pulse signals input to TAOIN or TAQOUT pin Count operation Up count or down count can be selected by two phase pulse signal When the timer overflows or underflows the reload register content is reloaded and the timer starts over again Note Divide ratio e 1 FFFFie n 1 for up count e 1 n 1 for down count n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing Timer overflows or underflows TAOIN pin function Two phase pulse input TAOOUT pin function Two phase pulse input Read from timer Count value can be read out by reading timer AO register Write to timer When counting stopped When a value is written to timer AO register it is written to both reload regis ter and counter When counting in progress When a value is written to timer AO register it is written to only reload regis ter Transferred to counter at next reload time Select functio
371. o D7 in the second bus cycle Note 1 If any unerased memory location is encountered during erase verify operation be sure to execute erase and erase verify operations one more time In this case however the user does not need to write data 0016 to memory before erasing 140 stENESAS Renesas Technology Corp Reset command FF16 FF16 Appendix Parallel I O Mode Flash memory version Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER The reset command is used to stop the program command or the erase command in the middle of operation After writing command code 4016 or 2016 twice write command code FF 16 in the first bus cycle and the same command code again in the second bus cycle The program command or erase command is disabled with the flash memory placed in read mode Program Address first location Loop counter X 0 Write program command Write 4016 Write program data Write Program data address Duration 20 us Loop counter X X 1 Write program verify write C016 command a Duration 6 us Last address Next address Vv C Write read command N Write read command Write 0016 A PASS FAIL Erase Next address Start All bytes 0016 NO Program all bytes 0016 Loop counter X X 1 Write 2
372. o AN54 Setting A D conversion start flag o A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Start A D conversion Stop A D onversion nssss O 1011 imunu i i A D registerO Address 03C116 03C016 ADO Reading Bela aen A D register 1 Address 03C316 03C216 AD1 b0 b7 A D register 2 Address 03C516 03C416 AD2 A D register 3 Address 03C716 03C616 AD3 A D register 4 Address 03C916 03C816 AD4 A D register5 Address 03CB16 O3CA16 AD5 A D register6 Address 03CD16 03CC16 AD6 A D register 7 Address 03CF16 03CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Figure 2 7 10 Set up procedure of single sweep mode stENESAS 295 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 5 Operation of A D Converter in repeat sweep mode 0 In repeat sweep 0 mode choose functions from those listed in Table 2 7 5 Operations of the circled items are described below Figure 2 7 11 shows timing chart and Figure 2 7 12 shows the set up procedure Table 2 7 5 Choosed functions Operation clock AD Divided by 4 fab divided by 2 fab faD Resolution 8 bit 10 bit Analog input pin Di AN1 2 pins ANo to AN8 4 pins
373. o the fact that 1 LSB width actually measured falls on a range from 0 mV to 10 mV though 1 LSB width based on the theoretical A D conversion characteristics is 5 mV see 5 2 A D converter s standard characteristics Output code result of A D conversion 1LSB width for theoretical A D conversion characteristic Differential non linear error 15 20 25 30 35 40 45 Analog input voltage mV Figure 2 7 21 Differential non linearity error 10 bit resolution 306 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 11 Internal Equivalent Circuit of Analog Input Figure 2 7 22 shows the internal equivalent circuit of analog input 7 AVcc Parasitic ON resistor diode ON resistor approx 0 6k Q approx 2k 2 Wiring resistor I C Approx 3 0pF A ANO l approx 0 2k Q Analog input voltage O O sw Sampling control signal i ladder type l switches i ladder type wiring i 10 resistors i 10 ON resistor Parasitic approx 5k Q diode Chopper type amplifier swi A D successive conversion b2 b1 bo register A D control register 0 Resistor Comparison voltage ladder ON resistor approx 0 6k Q ADT A D conversion interrupt request Comparison reference voltage Vref generator Sampling Comparison Connect to O SW1 conducts only on the ports selected for analog input Cont
374. occurrence of a trigger the reload register contents are reloaded and the count continues To generate a trigger while a count is in progress generate the second trigger after an elapse longer than one cycle of the timer s count source after the previous trigger occurred TAOIN pin input signal el Trigger input Count source One shot pulse output from TAOOUT pin Start one shot pulse output Note The above applies when an external trigger falling edge of TAOIN pin input signal is selected Figure 2 2 31 One shot timer delay 204 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 16 Precautions for Timer A pulse width modulation mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 The timer AO interrupt request bit becomes 1 if setting operation mode of the timer in com pliance with any of the following procedures Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to 0 after the above listed changes have been made 3 Setting the count start flag to 0 while PWM pulses are being output causes the counter to stop counting If the TAOOUT
375. ock Synchronous Serial I O UARTI transmit receive control register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UiC1 i 0 1 03A516 03AD16 0216 Function Note 1 Bit _ Function Bit name During clock syre ronous R i enable bit 0 Transmission disabled 0 Transmission disabled 1 Transmission enabled 1 Transmission enabled 90 faa li buffer 0 Data present in 0 Data present in i empty flag transmit buffer register transmit buffer register i 1 No data present in 1 No data present in transmit buffer register transmit buffer register _ Receive enable bit s Reception disabled z Reception disabled Note 2 Reception enabled Reception enabled a Receive complete flag 0 No data present in 0 No data present in receive buffer register receive buffer register Data present in 1 Data present in receive buffer register receive buffer register Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 If you are using clock asynchronous serial I O mode you can enable receive enable bit when RxD port input is H If RxD port input is L and you have enabled receive enable bit then receive operation starts immediately UART transmit receive control register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UCON 03B016 XX0000002 Function Func
376. ocomputer is reset by pulling the P52 pin high Vcc the CNVss pin high VPPH the CPU starts operating using the control program in the boot ROM area This mode is called the boot mode The control program in the boot ROM area can also be used to rewrite the user ROM area CPU rewrite mode operation procedure The internal flash memory can be operated on to program read verify or erase it while being placed on board by writing commands from the CPU to the flash memory control register addresses 03B416 03B516 and flash command register address 03B616 Note that when in CPU rewrite mode the boot ROM area cannot be accessed for program read verify or erase operations Before this can be accom plished a CPU write control program must be written into the boot ROM area in parallel input output mode The following shows a CPU rewrite mode operation procedure lt Start procedure Note 1 gt 1 Apply VPPH to the CNVss VPP pin and Vcc to the port P52 pin for reset release Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program In this case set the CPU write mode select bit of the flash memory control register to 1 before applying VPPH to the CNVSs VPP pin 2 After transferring the CPU write control program from the boot ROM area to the internal RAM jump to this control program in RAM The operations described below are controlled by this program 3
377. ode 0 CH1 A D operation mode select bit 0 Set this bit to 0 b4 b3 11 Repeat sweep mode 0 A D conversion start flag 0 A D conversion disabled 1 A D conversion started Frequency select bit 0 0 fAaD 4 is selected 1 faD 2 is selected Note If the A D control register is rewritten during A D conversion the conversion result i indeterminate A D control register 1 Note 1 yee Symbol Address When reset ADCON1 03D716 0016 Bit symbol Bit name Function A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins 1 0 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins Note 2 3 A D operation mode Set this bit to 0 in this mode select bit 1 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode Frequency select bit 1 faD 2 or faD 4 is selected fan is selected Vref connect bit Vref connected Set this bit to 0 A D input group select bit Port P6 group is selected ADGSELO put group 1 Port P5 group is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 AN50 to AN54 can be used in the same way as for ANo to AN4 Note 3 If port P5 group is selected the contents of A D registers 5 to 7 are indeterminate If port P5 group is selected do not select 8 pins sweep mode Figure 1
378. ode register U1MR 03A916 UART1 bit rate generator U1BRG O3AA16 03AB16 03AC16 UART1 transmit receive control register 0 U1C0 03AD16 UART1 transmit receive control register 1 U1C1 03AE16 03AF16 03B016 UART transmit receive control register 2 UCON UARTO receive buffer register VORB UART1 transmit buffer register U1TB UART1 receive buffer register U1RB Figure 2 6 2 Memory map of UARTi related registers 272 stENESAS Renesas Technology Corp UART Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UARTI transmit buffer register Note b15 b8 b7 bO b7 Address 03A316 03A216 UARTi receive buffer register b15 b8 b7 bO b7 03AB16 03AA16 When reset Indeterminate Indeterminate Transmit data Nothing is assigned indeterminate In an attempt to write to these bits write 0 The value if read turns out to be Note Use MOV instruction to write to this register Address 03A716 03A616 Symbol UORB U1RB O3AFi6 03AE16 Bit name Function During clock synchronous serial I O mode When reset Indeterminate Indeterminate Function During UART mode Receive data Receive data Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Overrun error flag Note FER Framing error flag Invalid Note PER Par
379. oe eae r Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate 0 No effect 1 Prescaler is reset When read the value is 0 Clock prescaler reset flag Figure 2 2 5 Timer A related registers 4 RENESAS 179 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 2 Operation of Timer A timer mode In timer mode choose functions from those listed in Table 2 2 1 Operations of the circled items are described below Figure 2 2 6 shows the operation timing and Figure 2 2 7 shows the set up procedure Table 2 2 1 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAOIN pin is at L level Performs count only for the period in which the TAOIN pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1
380. oes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to one shot timer mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to O after the above listed changes have been made 108 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Timer X pulse width modulation mode 1 The timer Xi interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures e Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to O after the above listed changes have been made 2 Setting the count start flag to 0 while PWM pulses are being output causes the counter to stop counting If the TXiINOUT pin is outputting an H level in this instance the output level goes to L and the timer Xi interrupt request bit goes to 1 If the TXiINOUT pin is outputting an L level in this instance the level does not change and the timer Xi interrupt request
381. oftware interrupt number 19 76 to 79 Note UART1 transmit Software interrupt number 20 80 to 83 Note UART1 receive Software interrupt number 21 84 to 87 Note Timer AO Software interrupt number 22 88 to 91 Note Timer XO Software interrupt number 23 92 to 95 Note Timer X1 Software interrupt number 24 96 to 99 Note Timer X2 Software interrupt number 25 100 to 103 Note Software interrupt number 26 104 to 107 Note Timer BO Software interrupt number 27 108 to 111 Note Timer B1 Software interrupt number 28 112 to 115 Note Software interrupt number 29 116 to 119 Note INTO Software interrupt number 30 120 to 123 Note INT1 Software interrupt number 31 124 to 127 Note Software interrupt number 32 to Software interrupt number 63 Note Note Note Note Note Note Note Note 128 to 131 to 252 to 255 Note Note Software interrupt Note Address relative to address in interrupt table register INTB Cannot be masked by flag 32 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priorit
382. ommand checks the ID code Execute the boot ID check command as explained here following 1 Transfer the F516 command code with the 1st byte 2 Transfer addresses Ao to A7 As to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd 3rd and 4th bytes respectively 3 Transfer the number of data sets of the ID code with the 5th byte 4 The ID code is sent with the 6th byte onward starting with the 1st byte of the code ngs Rare ral ore oma OI M16C reception data _TxDO M16C transmit data P53 BUSY Figure 1 116 Timing for the ID check ID Code When the flash memory is not blank the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match If the codes do not match the command sent from the peripheral units is not accepted An ID code contains 8 bits of data Area is from the 1st byte addresses OFFFDF 16 OFFFE316 OFFFEB16 OFFFEF16 OFFFF316 OFFFF716 and OFFFFB1e Write a program into the flash memory which already has the ID code set for these addresses ides Ae ikea OFFFDCi 6 to OFFFDF16 ID1 Undefined instruction vector OFFFE016 to OFFFE316 ID2 Overflow vector OFFFE416 to OFFFE716 i BRK instruction vector OFFFE816 to OFFFEB16 ID3 Address match vector OFFFEC16 to OFFFEF 16 ID4 Single step vector OFFFF016 to OFFFF316 ID5 Watchdog timer vector OFFFF416 to OFFFF716 ID6 DBC vector OFFFF816 to OFFFFB16 ID7
383. one of the FCLR FSET POPC and LDC instructions the acceptance of the interrupt is effective as the next instruction is executed When changed by REIT instruction Determination whether or not to Interrupt request generated accept interrupt request Previous REIT Interrupt sequence instruction If flag is changed from 0 to 1 by REIT instruction When changed by FCLR FSET POPC or LDC instruction Determination whether or not to Interrupt request generated accept ii request Previous instruction FSET Next instruction Interrupt sequence If flag is changed from 0 to 1 by FSET instruction Figure 4 2 3 The timing of reflecting the change in the flag to the interrupt 4 2 2 Interrupt Request Bit The interrupt request bit is set to 1 by hardware when an interrupt is requested After the interrupt is accepted and jumps to the corresponding interrupt vector the request bit is set to 0 by hardware The interrupt request bit can also be set to 0 by software Do not set this bit to 1 stENESAS 371 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 2 3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL Set the interrupt priority level using the interrupt priority level select bit which is one of the component bits of the interrupt control register When an interrupt request occurs the interrupt priority level
384. one shot timer mode explanation for details as the operation is identical 16 bit PWM mode Operations ji escadceeit iE Ea dave naan eh AA AEEA ARRS P198 8 bit PWM mode operation cee eeeeeeeee ence cette enna e ee ee deian in eaaa ENERE EARNE EaR P200 174 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 Count source The internal count source can be selected from f1 f8 f32 and fc32 Clocks f1 f8 and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc32 is derived by dividing the CPU s secondary clock by 32 3 Frequency division ratio In timer mode or pulse width modulation mode the value set in the timer register 1 becomes the frequency division ratio In event counter mode the set value 1 becomes the frequency division ratio when a down count is performed or FFFF16 the set value 1 becomes the frequency division ratio when an up count is performed In one shot timer mode the value set in the timer register be comes the frequency division ratio The counter overflows or underflows when a count source equal to a frequency division ratio is input and an interrupt occurs For the pulse output function the output from the port varies the value in the port register does not vary 4 Reading the timer Either in timer mode or in event counter mode reading the timer register takes o
385. operating conditions Note 1 Vcc Parameter Supply voltage Mask ROM version Standard Typ Flash memory version AVcc Analog supply voltage Vss Supply voltage AVss Analog supply voltage VIH HIGH input voltage P90 to P07 P10 to P17 P30 to P35 P4o to P4s P50 to P54 P60 to P67 P70 P71 XIN RESET CNVss ViL LOW input voltage P00 to P07 P10 to P17 P30 to P35 P4o to P4s P50 to P54 P60 to P67 P70 P71 XIN RESET CNVss 1 OH peak HIGH peak output P00 to P07 P10 to P17 P30 to P35 P40 to P4s current P50 to P54 P60 to P67 P70 P71 TOL peak LOW peak output 00 to P07 P30 to P3s P40 to P4s current P50 to P54 P60 to P67 P7o P71 OL peak LOW peak output Pio to P17 HIGHPOWER current LOWPOWER lOH avg HIGH average output P00 to P07 P10 to P17 P30 to P35 P4o to P45 current P50 to P54 P60 to P67 P70 P71 IOL avg LOW average output P00 to P07 P30 to P35 P40 to P4s current P50 to P54 P60 to P67 P70 P71 low avg LOW average output Po to P17 HIGHPOWER curent LOWPOWER f XIN Main clock input oscillation Mask ROM version Vcc 4 0V to 5 5V frequency Vcc 2 7V to 4 0V Flash memory version Vcc 4 0V to 5 5V Subclock oscillation frequency Note 1 Unless otherwise noted Vcc 2 7V to 5 5V Vss OV Ta 20 to 85 C Extended operating temperature version 40 to 85 C Fl
386. operation mode select bit when using timer X2 of M30200 Timer Xi register Note 1 b15 b8 Address When reset b7 b0 b7 bO 038916 038816 Indeterminate Loo T 0880161088016 Indeterminate 038D16 038C16 Indeterminate Function Values that can be set e Timer mode 000016 to FFFF16 Counts an internal count source e Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow One shot timer mode 000016 to FFFF16 x0 Counts a one shot width Note 2 Pulse period pulse width measurement mode o x Measures a pulse period or width Pulse width modulation mode 16 bit PWM 000016 to FFFE16 Functions as a 16 bit pulse mts eel Note 2 Pulse width modulation mode 8 bit PWM eae se 2 Timer low order address functions as an 8 bit Sn lod prescaler and high order address functions as an 8 bit 0016 to FF 16 Note 2 pulse width modulator Low order addresses Note 1 Read and write data in 16 bit units Note 2 Use MOV instruction to write to this register Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 TAOS Timer AO count start flag 0 Stops counting TXOS Timer X0 count start flag 1 Starts counting Timer X1 count start flag Timer X2 count start flag Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate TBOS Timer BO count start flag 0 Stops counting TB1S Time
387. operations programs and reading are controlled by transferring software commands via the RxDo pin Software commands are explained here below Table 1 79 Software commands Standard serial I O mode 1 When ID is Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte Aci verificate 1 Page read FFig Address Address Dat ata Not middle high acceptable 2 Page program 4116 Address Address Data Not middle high input input input input to acceptable 259th byte 3 Erase all unlocked blocks A716 D016 Not acceptable 4 Read status register 7016 Acceptable 5 Clear status register 5016 Not acceptable 6 Read lockbit status 7116 Address Address Not middle high acceptable 7 ID check function F516 Address Address Address ID size ID1 To ID7 Acceptable low middle high 8 Download function FAi6 Size Size Check Data To Not low high sum input required acceptable number of times 9 Version data output function FB16 Boot area output function FCi6 Address middle ferred from the peripheral unit to the flash memory microcomputer Note 2 SRD refers to status register data SRD1 refers to status register 1 data Note 3 All commands can be accepted when the flash memory is totally blank 148 tENESAS Renesas Technology Corp Acceptable Not acceptable
388. ore writing in the processor mode register addresses 000416 and 000516 L Is writing enabled in the protect register before writing in the port P4 direction register address O3EA16 L Is writing effectuated in the port P4 direction register by the next instruction after writing is enabled in the protect register _ Does not an interrupt generate between the instruction writing is enabled in the protect register and the instruction writing in the port P4 direction register 396 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix 1 Check Sheet Checks regarding the timer _ Is the timer started after a value is set in the timer register Checks regarding low power consumption _ In the low power consumption mode does not current flow from Vref when the Vref connection bit bit 5 in address 03D716 is set L Is not voltage level of port floating in the low power consumption mode Checks regarding Interrupt LI When rewrite the interrupt register do so at a point that does not generate the interruput request Checks regarding low voltage LI When using at low voltage have you checked recommended operating conditions and changed the wait bit address 000516 bit 7 to 1 Checks regarding A D converter L Have you selected other than fap no dividing for AD when using the A D converter at Vcc 2 7 4 0V LI Have you selected no sa
389. ote 1 Add 2 cycles in the case of a DBC interrupt add 1 cycle in the case either of an address coincidence interrupt or of a single step interrupt Note 2 Locate an interrupt vector address in an even address if possible BCLK Address bus Address y Indeterminate SP 2 SP 4 vec vec 2 PC Data bus Interrupt ETT Indeterminate SP 2 i SP 4 vec vec 2 contents contents contents contents Indeterminate The indeterminate segment is dependent on the queue buffer If the queue buffer is ready to take an instruction a read cycle occurs Figure 4 3 2 Time required for executing the interrupt sequence 4 3 2 Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL If an interrupt request that does not have an interrupt priority level is accepted one of the values shown in Table 4 3 2 is set in the IPL Table 4 3 2 Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL Watchdog timer 7 Reset 0 Other Not changed stENESAS 375 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER
390. ow e Pulse period pulse width measuring mode The timer measures an external signal s pulse period or pulse width Data bus high order bits A Data bus low order bits Clock source selection f Low order 8 bits ii High order 8 bits i o Timer fa o Pulse period pulse width measurement Reload register 16 f32 o fc32___o Event counter Polarity switching and edge pulse Can be selected in only event counter mode TBj overflow O j 1 when i 0 j 0 wheni 1 Figure 1 48 Block diagram of timer B Timer Bi mode register Symbol Address When reset EE ee TBIMR i 0 1 039B16 039C16 OOXX00002 Bit symbol 0 TMODO Operation mode select bit 9 9 Timer mode Event counter mode TMOD1 Pulse period pulse width measurement mode Inhibited Function varies with each operation mode MR1 TCK1 Function varies with each operation mode MR2 MR3 TCKO Count source select bit Note 1 Timer BO Note 2 Timer B1 Figure 1 49 Timer B related registers 1 stENESAS 59 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Timer Bi register Note Address When reset 039116 039016 Indeterminate b15 039316 039216 Indeterminate Function Timer mode 000016 to FFFF16 Counts the timer s period e Event counter mode 000016 to FFFF16 Counts external pulses input or a timer overflow Note1 Read and
391. p count n H 000016 oO 2 Z 3 Q 8 T x lt a E H content hex Set to 1 by software Timer XO count qr i i start flag 0 Set to 1 by software Timer X1 count q start flag 0 PWM pulse output H from TX1INOUT pin 4 Timer XO interrupt 1 request bit g Cleared to 0 when interrupt request is accepted or cleared by software Timer X1 interrupt 1 request bit o Cleared to 0 when interrupt request is accepted or cleared by software Figure 3 2 1 Operation timing of variable period variable duty PWM output Used for timer mode Set to period Timer XO interrupt request bit Timer X1 interrupt request bit Used for one shot timer mode Set to H width Figure 3 2 2 Connection diagram of variable period variable duty PWM output RENESAS 343 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Setting timer XO Selecting timer mode and functions ropop ey epop opel o TA mode register Address 039716 Selection of timer mode Pulse output function select bit 0 Pulse is not output TXOINOUT pin is a normal port pin Gate function select bit b4 b3 00 Gate function not available TXOINOUT pin is a normal port pin _ Q Must always be 0 in timer mode Count source select bit Count Count source
392. period b7 bs SOUICE f X n 10MHz_ f XcIN 32 768kHz 00 f1 gt Toons 800ns 3 2us 976 56us Setting divide ratio b15 b8 i oe b0 Timer XO register Address 038916 038816 Setting timer X1 fr Selecting one shot timer mode and functions Selection of one shot timer mode Pulse output function select bit Note 1 Pulse is output External trigger select bit Invalid when choosing timer s overflow as trigger Trigger select bit 1 Selected by event trigger select register Q Must always be 0 in one shot timer mode Sount Source select bit Count Count source period 00 fi gt i SOUICE f X n 10MHz f XcIN 32 768kHz i 100ns 800ns 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Continued to the next page Figure 3 2 3 Set up procedure of variable period variable duty PWM output 1 344 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Continued from the previous page Setting trigger select register b7 bo Trigger select register Address 038316 I iio tr se E Timer X1 event trigger select bit b5 b4 1 0 TXO overflow is selected Setting one shot timer s time b15 b8 ld b0 7 b0 Timer X1 register Address 038B16 038A16
393. pin 1 Pulse is output Note 1 TXiINOOUT pin is a pulse output pin MR1 External trigger select 0 Falling edge of TXiINOOUT pin s input signal Note 3 joo bit Note 2 1 Rising edge of TXiINOOUT pin s input signal Note 3 MR2 Trigger select bit 0 One shot start flag is valid 1 Selected by event trigger select register Note 4 MR3 0 Must always be 0 in one shot timer mode TCKO Count source select bit Set the corresponding port direction register to 1 output mode External trigger cannot be selected as count start condition when pulse output function is selected Valid only when the TXiiNOUT pin is selected by the event trigger select bit addresses 038316 If timer overflow is selected this bit can be 1 or 0 Set the corresponding port direction register to O input mode Pulse output function cannot be selected when TXiINOUT pin is selected by the event trigger select bit addresses 038316 Figure 1 62 Timer Xi mode register in one shot timer mode 70 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 4 Pulse period pulse width measurement mode In this mode the timer measures the pulse period or pulse width of an external signal See Table 1 23 Figure 1 63 shows the timer Xi mode register in pulse period pulse width measurement mode Figure 1 64 shows the operation timing when me
394. plains the content of each software command Table 1 78 Software command list parallel I O mode First bus cycle Second bus cycle Command Data Data Mode Address Do to D7 Mode Address Do to D7 Read Program Program Program address data Program verify Verify data Erase x 2016 Erase verify Verify Verify address data Reset FFi6 Read Command 0016 The read mode is entered by writing the command code 0016 in the first bus cycle When an address to be read is input in one of the bus cycles that follow the content of the specified address is read out at the data I O pins Do D7 The read mode is retained intact until another command is written After reset and after the reset command is executed the read mode is set Program Command 4016 The program mode is entered by writing the command code 4016 in the first bus cycle When an address and data to be program is write in the second bus cycle the flash memory control circuit executes the program operation The program operation requires approximately 20 us Wait for 20 us or more before the user go to the next processing Note 1 The write operation is not completed immediately by writing a program command once The user must always execute a program verify command after each program command executed And if verification fails the user need to execute the program command repeatedly until the verification passes
395. ponding to each pin every time conversion on one pin is com pleted 3 When the A D conversion on all the analog input pins selected is completed the A D conver sion interrupt request bit goes to 1 At this time the A D conversion start flag goes to 0 The A D converter stops operating E 2 After A D conversion on ANo AN50 pin is complete 1Start A D conversion A D converter begins converting all pins selected 3 A D conversion is complete 8 bit resolution 28 oapcycles 8 bit resolution 28 yap cycles 10 bit resolution 33 aD cycles 10 bit resolution 33 aD cycles m a gt lt m a Wu Set to 1 by software A D conversion 4 start flag A D register 0 X Result A D register 1 Y Result A D register i x Result A D conversion 1 interrupt request g bit A Cleared to 0 when interrupt request is accepted or cleared by software Note When ap frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 aD cycles for 8 bit resolution and 59 ab cycles for 10 bit resolution Figure 2 7 9 Operation timing of single sweep mode 294 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M302
396. pt control register is rewritten due to effects of the instruction queue e When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener ated This will depend on the instruction If this creates problems use the below instructions to change the register Instructions AND OR BCLR BSET tENESAS Renesas Technology Corp 383 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt MEMO 384 stENESAS Renesas Technology Corp Chapter 5 Standard Characteristics Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics 5 1 Standard DC Characteristics The standard characteristics given in this section are examples of M30201M4 XXXFP The contents of these examples cannot be guaranteed For standardized values see Electric characteristics 5 1 1 Standard Ports Characteristics Figures 5 1 1 through 5 1 6 show the standard ports characteristics 386 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Von V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values
397. pulse signal Bua hien MR3 0 Must always be 0 when using two phase pulse signal processing TCKO Count operation type 0 Reload type select bit 1 Free run type Two phase pulse processing operation 0 Normal processing operation select bit Note 1 Multiply by 4 processing operation Note When performing two phase pulse signal processing make sure the two phase pulse signal processing operation select bit address 038416 is set to 1 Also always be sure to set the event trigger select bit addresses 038316 to 00 Figure 1 43 Timer AO mode register in event counter mode stENESAS 55 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 3 One shot timer mode In this mode the timer operates only once See Table 1 15 When a trigger occurs the timer starts up and continues operating for a given period Figure 1 44 shows the timer AO mode register in one shot timer mode Table 1 15 Timer specifications in one shot timer mode Item Specification Count source f1 f8 f32 fC32 Count operation The timer counts down e When the count reaches 000016 the timer stops counting after reloading a new count e Ifa trigger occurs when counting the timer reloads a new count and restarts counting Divide ratio n n Set value Count start condition e An external trigger is input e The timer overflows e The one shot start flag is set
398. put LOW pulse width 122 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group g ey ue SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Timing requirements referenced to Vcc 3V Vss OV at Ta 20 to 85 C unless otherwise specified Extended operating temprature version 40 to 85 C Table 1 70 Timer X input pulse period measurement mode Standard Parameter Min Max TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width Table 1 71 Timer X input pulse width measurement mode Standard Parameter Min Max te TX TXiinout input cycle time tw TXH TXitNouT input HIGH pulse width tw TXL TXiINOUT input LOW pulse width Table 1 72 Serial I O Standard Parameter Min Max te Ck CLKO input cycle time tw CKH CLKO input HIGH pulse width tw CKL CLKO input LOW pulse width ta C Q TxDi output delay time th C Q TxDi hold time tsu D C RxDi input setup time th C D RxDi input hold time Table 1 73 External interrupt INTi inputs We ae Symbol Parameter Unit tw INH INTI input HIGH pulse width tw INL INTi input LOW pulse width RENESAS 123 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V
399. put signal to the TBiIN pin counting rising edges and falling edges Timer overflow TBj overflow Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Bi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow 3 Stop count lt gt Start count again a Counter content hex Time Set to 1 by software TA Set to 1 by softwar VA software Count start flag 7 i i Cleared to 0 by Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi interrupt 4 Ta T aw request bit o Figure 2 3 6 Operation timing of event counter mode 212 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting event counter mode and functions b0 i 7 Timer Bi mode register i 0 1 Address 039B16 039C16 lt Te elo teime i 0 1 Selection of event counter mode Count polarity select bit b3 b2 0 0 Counts external signal falling edges Fixed to 0 in event counter mode Event clock select 0 Input from
400. puters M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A Selecting PWM mode and functions LI CHI Note Set the corresponding port direction register which outputs the pulse to 1 output mode Selection of PWM mode 1 Must always be 1 in PWM mode Invalid in event counter mode Can be 0 or 1 Trigger select bit 16 8 bit PWM mode select bit Count source select bit Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 1 Selected by event trigger select register 1 Functions as a 8 bit pulse width modulator b7 be Count Count source period i SOUICE Xin 10MHZ f Xcin 32 768kKHz fi 100ns fs 800ns 3 2us 976 56us b7 b6 00 fi 01 f8 10 fs2 11 fce32 Oo f2 0 1 0 1 fos2 Clearing timer Xi interrupt request bit b7 ESPI b0 i Refer to Precaution for Timer X pulse width modulation mode Timer Xi interrupt control register i 0 to 2 Address 005616 to 005816 TXiIC i 0 to 2 Interrupt request bit Setting trigger select register b7 b0 Me Trigger select register Address 038316 TRGSR Timer X0 event trigger select bit b3 b2 0 1 TB1 ove 10 TAO overfl 11 TX1 ove lected lected lected low is sel low is sel low is sel Timer X1 lect bit b5 b4 0 1 TB1 ove 10 TXO overfl 11 TX2 overfl event trigger se lecte
401. r Note 2 If an overrun error occurs the UARTO receive buffer will have the next data written in Note also that the UARTO receive interrupt request bit does not change 80 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous serial I O mode UARTO transmit receive mode registers b7 b6 b5 b4 b3 b2 bi b0 oT TTT fofoys tmr oaae 0016 __SMDO__ Serial I O mode select bit 2 21 bO 0 0 1 Clock synchronous serial SMD1 1 0 mode SMD2 CKDIR Internal external clock 0 Internal clock Note 1 select bit 1 External clock Note 2 STPS PRY Invalid in clock synchronous serial I O mode PRYE SLEP 0 Must always be 0 in clock synchronous serial I O mode loi Note 1 Set the corresponding port direction register to 1 output mode Note 2 Set the corresponding port direction register to 0 input mode Figure 1 74 UARTO transmit receive mode register in clock synchronous serial I O mode Table 1 26 lists the functions of the input output pins during clock synchronous serial I O mode Note that for a period from when the UARTO operation mode is selected to when transfer starts the TxDO pin outputs a H If the N channel open drain is selected this pin is in floating state Table 1 26 Input output pin functions in clock synchronous serial I O mode Serial data output Port P5o direction register bit 0 at add
402. r Address 03E216 PDO 0 Input mode Functions as an input port 1 Output mode Functions as an output port W Setting pull up control register 0 b7 bO Pull up control register 0 Address 03FC16 PURO 1 Pulled high POo to P083 1 Pulled high P04 to P07 Setting interrupt control register eee ae te interrupt control register Address 004D16 Interrupt priority level select bit b2 b1 bO 0 0 0 Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested Figure 2 10 5 Set up procedure of key input interrupt stENESAS 321 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 Power Control 2 11 1 Overview Power Control refers to the reduction of CPU power consumption by stopping the CPU and oscillators or decreasing the operation clock The following is a description of the three available power control modes 1 Modes Power control is available in three modes a Normal operation mode e High speed mode Divide by 1 frequency of the main clock becomes the BCLK The CPU operates with the BCLK selected Each peripheral function operates according to its assigned clock Medium speed mode Divide by 2 divide by 4 divide by 8 or divide by 16 frequency of the m
403. r UOMR 78 UARTO bit rate generator UOBRG UARTO transmit buffer register UOTB 77 UARTO transmit receive control register 0 UOCO 78 UARTO transmit receive control register 1 U0C1 79 UARTO receive buffer register UORB 77 UART1 transmit receive mode register U1MR 78 UART1 bit rate generator U1BRG UART1 transmit buffer register U1TB 77 UART1 transmit receive control register 0 U1C0 78 UART1 transmit receive control register 1 U1C1 79 UART1 receive buffer register U1RB 77 03B016 UART transmit receive control register 2 UCON 79 03B116 03B216 03B316 03B416 Flash memory control register 0 FCONO Note 03B516 Flash memory control register 1 FCON1 Note 03B616 Flash command register FCMD Note 127 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 O3BE16 O3BF16 Note This register is only exist in flash memory version Address Register Page 03C016 j at ike A D register 0 ADO 03021 A D register 1 AD1 030316 030416 paces A D register 2 AD2 030618 A D register 3 AD3 030716 92 03C816 Hesg A D register 4 AD4 osCA1e A D register 5 AD5 03CB16 030018 A D register 6 AD6 03CD16 03CE16 7 esc A D register 7 AD7 03D016 03D116 03D216 03D316 03D416 A D control register 2 AD
404. r B1 count start flag T rstarts counting Clock devided count start flag Figure 2 4 2 Timer X related registers 1 222 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X One shot start flag Symbol Address When reset b7 b6 b5 b4 b3 b2 bi b0 ONSF 038216 XXXX00002 TA0OS Timer AO one shot start flag 4 Timer start When read the value is 0 1 TX0OS Timer XO one shot start flag TX10S Timer X1 one shot start flag TX20S Timer X2 one shot start flag Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Trigger select register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TRGSR 038316 0016 Bit symbol R Timer AO event trigger TAOTGE select bit 2 Input on TAON is selected Note TB1 overflow is selected TAOTGH TX2 overflow is selected TXO overflow is selected TXOTGL Timer XO event trigger select bit g N Input on TXOINOUT is selected Note TB1 overflow is selected TAO overflow is selected TX1 overflow is selected TXOTGH TX1TGL_ Timer X1 event trigger select bit Input on TX1INouT is selected Note TB1 overflow is selected TXO overflow is selected TX2 overflow is selected TX1TGH 30098 77 00 TX2TGL Timer X2 event trigger select bit Input on TX2iNouT is selected Note TB1 overflow
405. r is indeterminate at the beginning of a count Therefore the timer Bi overflow flag may go to 1 immediately after a count is started 7 If changing the measurement mode select bit is set after a count is started the timer Bi interrupt request bit goes to 1 8 If the input signal to the TBiIN pin is affected by noise precise measurement may not be performed in some cases It is recommended to see that measurements fall within a specific range by use of software 9 For pulse width measurement pulse widths are successively measured Use software to check whether the measurement result is an H level width or an L level width RENESAS 219 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 Timer X 2 4 1 Overview The following is an overview for timer X a 16 bit timer 1 Mode Timer X operates in one of the four modes a Timer mode In this mode the internal count source is counted Two functions can be selected the pulse output function that reverses output from a port every time an overflow occurs or the gate function which controls the count start stop according to the input signal from a port lt Timer mode operaio etessnskiaas anaa ENEKE tei naan in aadaeidae eee aes nea edd P224 Timer mode gate function operation 0 eee ceeeee cece eee ette eee eee ee eset eee aeee ee etaaeeeeeeeaaeeeeeeeaeeeeeneeaa P226 e Ti
406. r mode external trigger selected eeeeeee 196 2 2 11 Operation of Timer A pulse width modulation mode 16 bit PWM mode selected 198 2 2 12 Operation of Timer A pulse width modulation mode 8 bit PWM mode selected 200 2 2 13 Precautions for Timer A timer mode 0 eee ee eeee cette eter ee eee eee ae ee eee taaeeeeeetaaeeeeeetaeeeeenenea 202 2 2 14 Precautions for Timer A event counter mode eeeeeteeeeeeeeneeeeeeeeeaeeeeeeeaeeeeeeeaaeeeeeneaas 203 2 2 15 Precautions for Timer A one shot timer mode eee eeeeeeeeennneeeeeeeeeeeeeeeeaeeeeeeeaaeeeeeeeaas 204 2 2 16 Precautions for Timer A pulse width Modulation mode cece eeseeeeeeeenteeeeeeeenaeeeeeeeaas 205 2 3 THMON Bes E E E LEE ATEA E EE A A 206 PAE ONETAN E EEA A EA E A TAA 206 2 3 2 Operation of Timer B timer mode cece cece ee ceneeeeeee cece ae eeeeeee ce aaeeeceeeeseeaeeegeeeeseeaeeeeeaeeeee 210 2 3 3 Operation of Timer B event Counter mode ccceeeeeeeeeeeeeeceeeeeeeeeeeaeeeeaaeeseeeeestaaeeeeeeees 212 2 3 4 Operation of Timer B pulse period Measurement MOE cccceceseceeeesseeeeeseseseeeeeseaes 214 2 3 5 Operation of Timer B pulse width measurement mode ccecceceeesseeeeeesesteeeeeesntaeeeeeeeaas 216 2 3 6 Precautions for Timer B timer mode event Counter mode eeeeeeeeeeeenteeeeeeentaeeeeeeeaas 218 2 3 7 Precautions for Timer B pulse period pulse width measurement mode
407. r standardized values see Electric characteristics 5 3 1 Standard Ports Characteristics Figures 5 3 1 through 5 3 3 show the standard ports characteristics 392 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version Von V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Flectrical characteristics for rated values Figure 5 3 1 loH VOH standard characteristics of ports PO to P7 Vcc 5V VoL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 3 2 loL VOL standard characteristics of ports PO to P7 Vcc 5V VoL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 3 3 lot VOL standard characteristics of port P1 Vcc 5V HIGH POWER stENESAS 393 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version 5 3 2 Standard Characteristics of ICc f XIN Figure 5 3 4 shows the Characteristics of ICC f XIN The standard characteristics given in this section are examples of M30201F
408. r to start counting the count source 2 If a measurement pulse changes from H to L the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is transferred to the reload register The timer Bi interrupt request does not generate 3 If a measurement pulse changes from H to L again the value of the counter is transferred to the reload register and the timer Bi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and the measurement is started again Note e The timer Bi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Bi is overflowed The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Bi overflow flag goes to 1 immediately after a count is performed e The timer Bi overflow flag goes to 0 if timer Bi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software Measurement of pulse time interval from falling edge to falling edge 1 Start count 2 Start measurement 3 Start measurement again Count source 5 HW i Measurement pulse LaTransfer 1 4 Transfer Reload register counter i indeterminate v
409. ration mode select bit 1 Note 1 1 Must always be 1 in repeat sweep mode 1 8 10 bit mode select bit Frequency select bit 0 0 8 bit mode 0 fap 4 is selected 1 10 bit mode 1 fAD 2 is selected A D conversion start flag 0 A D conversion disabled Frequency select bit 1 0 faD 2 or fAD 4 is selected 1 fab is selected Vref connect bit 1 Vref connected ____________ Must be fixed to 0 A D input group select bit 0 Port P6 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode 1 Port P5 group is selected Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to AN54 Setting A D conversion start flag b7 bO A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started a Converts non selected pin after converting pins selected through the A D sweep pin select bit Orie oe Start A D conversion Reading conversion result A D registerO Address 03C116 03C016 b15 b8 A D register 1 Address 03C316 03C216 b7 bO b7 A D register 2 Address 03C516 03C416 AAA AAI A D register 3 Address 03C716 03C616 A D register 4 Address 03C916 03C816 A D register 5 Address 03CB16 03CA16 A D register 6 Address 03CD16
410. rature version 40 to 85 C Note 2 With one timer operated using C32 lt CENESAS 119 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Table 1 57 A D conversion characteristics Note Paramet M diti Standard arameter easuring condition Min Typ Max Resolution Vrer Vcc Absolute Sample amp hold function not available VREF Vcc 3V accuracy 8bit AD AD Riapper Ladder resistance VREF VcC tconv Conversion time 8bit VREF Reference voltage VIA Analog input voltage Note Unless otherwise noted Vcc AVcc VREF 3V VSS AVSsS OV at Ta 25 C f XIN 3 5MHz 120 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Timing requirements referenced to Vcc 3V Vss OV at Ta 20 to 85 C unless otherwise specified Extended operating temprature version 40 to 85 C Table 1 58 External clock input Standard Parameter Min Max External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Table 1 59 Timer A input counter input in event counter mode Standard Parameter Min Max
411. rce Remarks Software interrupt number 0 0 to 3 Note BRK instruction Cannot be masked by flag Software interrupt number 11 44 to 47 Note Software interrupt number 12 Note Software interrupt number 13 52 to 55 Note Key input interrupt Software interrupt number 14 Note 48 to 51 Note Note Note 56 to 59 Note A D Software interrupt number 17 68 to 71 Note UARTO transmit Software interrupt number 18 72 to 75 Note UARTO receive Software interrupt number 19 76 to 79 Note UART1 transmit Software interrupt number 20 80 to 83 Note UART1 receive Software interrupt number 21 84 to 87 Note Timer AO Software interrupt number 22 88 to 91 Note Timer XO Software interrupt number 23 92 to 95 Note Timer X1 Software interrupt number 24 96 to 99 Note Timer X2 Software interrupt number 25 100 to 103 Note Software interrupt number 26 104 to 107 Note Timer BO Software interrupt number 27 108 to 111 Note Timer B1 Software interrupt number 28 112 to 115 Note Software interrupt number 29 116 to 119 Note INTO Software interrupt number 30 120 to 123 Note INT1 Software interrupt number 31 124 to 127 Note Software interrupt number 32 to Software
412. re command The data in memory can only be read out by a read after software command input Program and erase operations are controlled using software commands Table 1 77 Relationship between control signals and bus operation modes Mode Enamel TE OE WE VRFY VPP Do to D7 Read VIL VIL VIH VIL VppH Data output i Output disabled VIL VIH VIH VIL VPPH Hi Z Stand by VIH xX x VIL VpPH Hi Z Read VIL VIL VIH VH VppH Data output Pea Output disabled VIL Vin vig ie Vesa HiZ Standby VIH X X VIH VppH Hi Z Write VIL VIH VIL VIH VPPH Data input Note X can be VIL or VIH 2tENESAS Renesas Technology Corp 137 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Flash memory version The following explains about bus operation modes software commands and status register Bus Operation Modes Read only mode is entered by applying VPPH to the CNVSs pin and a low voltage to the VRFY pin Read only mode has three states Read Output Disable and Standby which are selected by setting the CE OE and WE pins high or low Read write mode is entered by applying VPPH to the CNVSs pin and a high voltage to the VRFY pin Read write mode has four states Read Output Disable Standby and Write which are selected by setting the CE OE and WE pins high or low Read The Read mode is entered by pulling the WE pin high w
413. readied Make changes in input output immediately af ter the instruction that sets 1 in the write enable bit of port P4 direction register avoid causing an interrupt RENESAS 173 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 Timer A 2 2 1 Overview The following is an overview for timer A a 16 bit timer 1 Mode Timer A operates in one of the four modes a Timer mode In this mode the internal count source is counted Two functions can be selected the pulse output function that reverses output from a port every time an overflow occurs or the gate function which controls the count start stop according to the input signal from a port lt Timer mode operaio enessnskiaas anaa NEKE ARAA ENEE eee nee ede P180 Timer mode gate function operation 00 0 eee ee cece eee enne eee eee eeee eee taaaeee ee AA EENEN SENEN aA KANRA NNE P182 e Timer mode pulse output FUNCTION operation 2 0 ee cece eect eee eeeeee eee eeeeaeeeeeeeaaeeeeeeeaeeeeeeeaaa P184 b Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers The free run type in which nothing is reloaded from the reload register can be selected when an underflow occurs The pulse output function can also be selected Please refer to the timer mode explanation for details as the operation is identical Event counter mode Operation
414. receive buffer register complete flag Receive interrupt 4 i request bit g eee a Cleared to 0 when interrupt request is accepted or cleared by software The above timing applies to the following settings Parity is disabled One stop bit Figure 1 81 Typical receive timing in UART mode a Sleep mode This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi The sleep mode is selected when the sleep select bit bit 7 at addresses 03A016 03A816 is set to 1 during reception In this mode the unit performs receive operation when the MSB of the received data 1 and does not perform receive operation when the MSB 0 88 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D Converter The A D converter consists of one 10 bit successive approximation A D converter circuit with a capacitive coupling amplifier Pins P60 to P67 and P50 to P54 also function as the analog signal input pins The direction registers of these pins for A D conversion must therefore be set to input The Vref connect bit bit 5 at address 03D716 can be used to isolate the resistance ladder of the A D converter from the reference voltage input pin VREF when the A D converter is not used Doing so stops any current flowing into the resistance ladder from VREF reducing
415. rection register bit 1 at address 03EB16 bit 2 at P51 P42 address 03EA16 0 Can be used as an input port when performing transmission only CLKO Programmable I O port Internal external clock select bit bit 3 at address 03A016 0 P52 Transfer clock input Internal external clock select bit bit 3 at address 03A016 1 86 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode e Example of transmit timing when transfer data is 8 bits long parity enabled one stop bit Transfer clock Transmit enable i bit TE Data is set in UARTi transmit buffer register Transmit buffer empty flag T1 Transferred from UARTIi transmit buffer register to UARTIi transmit register oe Pany e Stopped pulsing because transmit enable bit 0 I I I 10 SOB XOXEMEXEXONEKEY amp sABXENEXEXEMEKENEXEY siABX0 Transmit register 1 e cee ed TXEPT Transmit interrupt ae request bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc 16 n 1 fi or 16 n 1 fext Parity is enabled fi frequency of BRGi count source f1 f8 32 fc One stop bit fEXT frequency of BRGi count source external clock e Transmit interrupt cause select bit 1 n value
416. rection registers These registers are used to choose the direction of the programmable I O ports Each bit in these regis ters corresponds one for one to each I O pin 2 Port registers Figure 1 94 shows the port registers These registers are used to write and read data for input and output to and from an external device A port register consists of a port latch to hold output data and a circuit to read the status of a pin Each bit in port registers corresponds one for one to each I O pin 3 Pull up control registers Figure 1 95 shows the pull up control registers The pull up control register can be set to apply a pull up resistance to each block of 4 ports When ports are set to have a pull up resistance the pull up resistance is connected only when the direction register is set for input 4 Port P1 drive capacity control register Figure 1 95 shows a structure of the port P1 drive capacity control register This register is used to control the drive capacity of the port P1 s N channel output transistor Each bit in this register corresponds one for one to the port pins stENESAS 99 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up selection Direction register lt P30 to P35 Data bus Port latch Pull up selection POo to P07 P42 P71
417. register until analog to digital conversion Successive comparison method is complete If a trigger occurs the A D converter carries out the following 1 Fixes bit 9 of the successive comparison register Compares Vref with VIN In this instance the contents of the successive comparison register are 10000000002 default Bit 9 of the successive comparison register varies depending on the comparison re sult as follows If Vref lt VIN then 1 is assigned to bit 9 If Vref gt VIN then 0 is assigned to bit 9 2 Fixes bit 8 of the successive comparison register Sets bit 8 of the successive comparison register to 1 then compares Vref with VIN Bit 8 of the successive comparison register varies depending on the comparison result as follows If Vref lt VIN then 1 is assigned to bit 8 If Vref gt VIN then 0 is assigned to bit 8 3 Fixes bit 7 through bit 0 of the successive comparison register Carries out step 2 above on bit 7 through bit 0 After bit 0 is fixed the contents of the successive comparison register conversion result are transmitted to A D register i Vref is generated based on the latest content of the successive comparison register Table 2 7 7 shows the relationship of the successive comparison register contents and Vref Table 2 7 8 shows how the successive comparison register and Vref vary while A D conversion is in progress Figure 2 7 17 shows theoretical A D conversion char
418. ress 03EB16 1 Outputs dummy data when performing reception only Serial data input Port P51 direction register bit 1 at address 03EB16 0 Can be used as an input port when performing transmission only Transfer clock output Internal external clock select bit bit 3 at address 03A016 0 Internal external clock select bit bit 3 at address 03A016 1 Transfer clock input Port P52 direction register bit 2 at address 03EB16 0 RENESAS 81 Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous serial I O mode Example of transmit timing when internal clock is selected Tc Transfer clock LULL LULU LLU aq Transmit enable Data is set in UARTO transmit buffer Q bit TE 0 register Transmit buffer i empty flag TI Transferred from UARTO transmit buffer register to UARTO transmit register TCLK I Stopped pulsing because transfer enable bit 0 1300 POOHOOOAOOOHOGOE_LOOBOOABE Transmit igo register empty uy o io mMm r flag TXEPT r Transmit interrupt 1 Mm Ji a request bit IR g lt F Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc TceLk 2 n 1 fi e Internal clock is selected fi frequency of BRGO count source f1 f8 f32
419. ring on MCU P61 A P60 ANo lt p P62 A P63 A P64 A P54 CKOUT AN54 lt p gt g P65 A P53 CLKS AN53 gt 6 P66 A P52 CLKo ANs2 lt gt 7 P67 AN7 P51 RxDo ANs1 gt 8 POo Klo P50 TxDo ANs0 lt gt PoW K P02 Kl2 PO3 KI3 P04 Kl4 P05 KI5 POs Kle PO7 Ki7 Pio P11 _P48 TX2inouT lt gt 49 P12 P44 INT1 TX1INouT lt gt 19 P13 P43 INTo TXOINOUT lt gt 20 P14 P42 RxD1 lt gt 54 P15 P41 TAOouT lt gt Pte P40 TAOIN TXD1 lt gt P17 P30 P31 P32 P71 TB1IN XcIN lt gt P70 TBOIN XcouT gt 49 Connect oscillator circuit vss gt dS94 LOcOEW Figure 1 105 Pin connections for standard serial I O mode 1 144 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Flash Memory Version Mode setup method CNVss VpPH RESET Vss gt Vcc SCLK Vcc Note Note Apply Vcc when powering on MCU lt gt P62 AN2 lt gt P63 AN3 lt P P64 AN4 lt gt P66 ANe lt gt P54 CKouT AN54 lt gt P60 ANo lt gt P61 AN1 d lt gt P52 CLKo AN52 lt p P53 CLKS ANs3 54 a7 44 4d lt gt P67 AN7 N C gt P0o0 Klo gt Po Ki 8 lt gt Po2 Kl2 RESET lt gt P03 Ki3 M30201F6FP 4 gt PosiKla lt gt P05 KI5 M30201F6TFP a lt gt Po7 KI7 lt gt P10 LEDo gt P1i LED gt P12 LED2 gt P13 LEDs P51 RxDo ANs1 lt gt P50 TxDo AN50 lt gt O
420. ripheral devices Port Internal peripheral device I O pins PO key input interrupt function input pins P40 I O pin for serial I O communication Timer A input pin P41 Timer A output pin P42 Serial I O input pin P43 P44 Input pins for external interrupt Timer X I O pins P45 Timer X I O pin P50 to P54 I O pins for serial I O communication A D converter input pins P6 A D converter input pins P70 P71 Timer B input pins 7 Examples of working on non used pins Table 2 12 2 contains examples of working on non used pins There are shown here for mere ex amples In practical use make suitable changes and perform sufficient evaluation in compliance with you application Table 2 12 2 Examples of working on unused pins in single chip mode Pin name Connection Ports PO P1 P3 to P7 After setting for input mode connect every pin to Vss or Vcc via a resistor or after setting for output mode leave these pins open Note 1 XouT Note 2 Open AVcc Connect to Vcc AVss VREF BYTE Connect to Vss Note 1 If setting these pins in output mode and opening them ports are in input mode until switched into output mode by use of software after reset Thus the voltage levels of the pins become unstable and there can be instances in which the power source current increases while the ports are in input mode In view of an instance in which the con
421. rite to these bits write 0 The value if read turns out to be indeterminate Trigger select register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TRGSR 038316 0016 Bit symbol R TAOTGL Timer AO event trigger select bit TXOTGL Timer X0 event trigger select bit Input on TAOIN is selected Note TB1 overflow is selected TX2 overflow is selected TXO overflow is selected N Input on TXOmourT is selected Note TB1 overflow is selected TAO overflow is selected TX1 overflow is selected TXOTGH ojl 0 Og BR TX1TGL Timer X1 event trigger select bit Input on TX1INOUT is selected Note TB1 overflow is selected TXO overflow is selected TX2 overflow is selected TX1TGH 00g 00g 00g o O0O TX2TGL Timer X2 event trigger select bit Input on TX2 mourT is selected Note TB1 overflow is selected TX2TGH TX1 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi b0 Address When reset Symbol OAA CPSRF 038116 0XXXXXXX2 Bit symbol Bitname Function RW out to be indeterminate 0 No effect 1 Prescaler is reset When read the value is 0 Clock prescaler reset flag Nothing is assigned In an attempt to write to these bits write 0 The value if read turns Figure 1 40 Timer A related
422. rol related registers 326 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 2 Stop Mode Set Up Settings and operation for entering stop mode are described here Operation 1 Enables the interrupt used for returning from stop mode 2 Sets the interrupt enable flag I flag to 1 3 Clearing the protection and setting every clock stop bit to 1 stops oscillation and causes the processor to go into stop mode 1 Setting interrupt to cancel stop mode Interrupt control register KUPIC Address 004D16 ADIC Address 004E16 Address 005116 005316 Address 005216 005416 Address 005516 Address 005616 to 005816 Address 005A16 005Bie INTiIC i 0 1 Address 005D16 005E16 b7 bO nn Interrupt priority level select bit Interrupt priority level select bit Make sure that the interrupt priority Make sure that the interrupt priority level of the level of the interrupt which is used to interrupt which is used to cancel the wait mode is cancel the wait mode is higher than higher than the processor interrupt priority IPL of the processor interrupt priority IPL of the routine where the WAIT instruction is executed the routine where the WAIT k igh Reserved bit instruction is executed Must be set to 0 T oo ac tt TW om A 2 Interrupt enable flag I flag lt 1
423. rol signal SW2 and SW3 are open when A D conversion is not in for SW2 progress their status varies as shown by the waveforms in Connect to the diagrams on the left Connect to O SW4 conducts only when A D conversion is not in progress Control signal for SW3 Connect to Warning Use only as a standard for designing this data Mass production may cause some changes in device characteristics Figure 2 7 22 Internal equivalent circuit to analog input tENESAS 307 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 12 Sensor s Output Impedance under A D Conversion To carry out A D conversion properly charging the internal capacitor C shown in Figure 2 7 23 has to be completed within a specified period of time With T as the specified time time T is the time that switches SW2 and SW3 are connected to O in Figure 2 7 22 Let output impedance of sensor equivalent circuit be RO microcomputer s internal resistance be R precision error of the A D converter be X and the A D converter s resolution be Y Y is 1024 in the 10 bit mode and 256 in the 8 bit mode t Vc is generally Vc VIN 1 e C RO R Andwhent T Vc VIN SVINeviN t Hence RO R Cen X Y With the model shown in Figure 2 7 29 as an example when the difference between VIN and Vc becomes 0 1LSB we find impedance RO when voltage between pins Vc ch
424. ronization with the falling edges 3 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that transmission is completed The transfer clock stops at H level 4 If the next transmission data is set in the UARTO transmit buffer register while transmission is in progress before the eighth bit has been transmitted the data is transmitted in succession 254 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Example of wiring Microcomputer Receiver side IC CLKO CLK TxDO RxD Example of operation 1 Transmission enabled 3 Transmission is complete 4 Transmit next data 2 Start transmission To Transfer clock Transmit enable bit TE Data is set to UARTi transmit buffer register Transmit buffer empty flag TI H i ag T Transferred from UARTI transmit buffer register to UARTi transmit register TOK Stopped pulsing because transfer enable bit 0 noo 202000 am 0200o a 00O Oa Transmit register 4 i i i empty flag g o Ld TXEPT f r t Transmit e interrupt request 0 bit IR T e X A Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols Tc TCLK 2 n 1 fi The above timing applies to the following settings fi frequency of BRGi count
425. rotect register Address 000A16 EONA PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 0 Input mode Figure 3 4 2 Set up procedure of buzzer output stENESAS 351 Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 5 Solution for External Interrupt Pins Shortage Overview The following are solution for external interrupt pins shortage Figure 3 5 1 shows the set up procedure Use the following peripheral function e Event counter mode of timer X Specifications 1 Inputting a falling edge to the TXOINOUT pin generates a timer XO interrupt Operation 1 Set timer XO to event counter mode set timer to 0 and set interrupt priority levels in timer XO 2 Inputting a falling edge to the TXOINOUT pin generates a timer XO interrupt 352 2tENESAS Renesas Technology Corp Timer X Applications 7 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Initialization of timer XO b7 b0 20 Timer XO register TXO Address 038916 038816 Timer X0 mode register 0 0 0 0 Of ojo 1 TXoMR Address 039716 Selection of event counter mode Pulse output function select bit 0 Pulse is not output TXOINOUT pin is a normal port pin Count polarity select bit 0
426. roup SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 A D Converter 2 7 1 Overview The A D converter used in the M16C 60 group operates on a successive conversion basis The following is an overview of the A D converter 1 Mode The A D converter operates in one of five modes a One shot mode Carries out A D conversion on input level of one specified pin only once b Repetition mode Repeatedly carries out A D conversion on input level of one specified pin c Single sweep mode Carries out A D conversion on input level of two or more specified pins only once d Repeated sweep mode 0 Repeatedly carries out A D conversion on input level of two or more pins e Repeated sweep mode 1 Repeatedly carries out A D conversion on input level of two or more pins This mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times 2 Operation clock The operation clock in 5 V operation can be selected from the following fAD divide by 2 fAD and divide by 4 fAD In 3 V operation the selection is divide by 2 fAD or divide by 4 The fAD frequency is equal to that of the CPU s main clock 3 Conversion time Number of conversion for A D convertor varies depending on resolution as given Table 2 7 1 shows relation between the A D converter operation clock and conversion time Sample amp Hold function selected 33 cycles for 10 bit resolution or 28
427. rp Revision date Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Version Revision Contents for change date Page 204 2 2 15 Precaution for Timer A one shot timer mode 3 is partly revised Page 219 2 3 7 Precautions for Timer B pulse period pulse width measurement mode 3 is partly revised Page 309 Table 2 7 11 and Table 2 7 12 are partly revised Page 320 Figure 2 10 3 is partly revised Page 324 Table 2 11 1 is partly revised Page 328 Figure 2 11 6 is partly revised Page 329 2 11 4 Precautions in Power Control b is partly revised Page 355 Figure 3 6 2 is partly revised Page 359 Figure 3 7 2 is partly revised Revision history M30201 Group User s Manual stENESAS 401 Renesas Technology Corp M30201 Group User s Manual 2tENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan
428. rrupt request If change the U flag to O and select the interrupt stack pointer ISP and then execute an interrupt sequence When returning from the interrupt routine the U flag is returned to the state it was before the acceptance of interrupt request So far as software numbers 32 through 63 are concerned the stack pointer does not make a shift stENESAS 29 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Hardware Interrupts Hardware interrupts are classified into two types special interrupts and peripheral I O interrupts 1 Special interrupts Special interrupts are non maskable interrupts e Reset Reset occurs if an L is input to the RESET pin DBC interrupt This interrupt is exclusively for the debugger do not use it in other circumstances e Watchdog timer interrupt Generated by the watchdog timer e Single step interrupt This interrupt is exclusively for the debugger do not use it in other circumstances With the debug flag D flag set to 1 a single step interrupt occurs after one instruction is executed Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1 If an address other than the first address of the instruction in the address match interrupt regi
429. rrupt request is accepted or cleared by software Note n 000016 to FFFF 16 Figure 1 46 Example of how a 16 bit pulse width modulator operates Condition Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 External trigger falling edge of TAOIN pin input signal is selected 1 fi X m 1 X 2 1 run red Count source Note1 TAOIN pin input signal Underflow signal of H TE 8 bit prescaler Note2 q PWM pulse output from TAQOUT pin Timer AO interrupt request bit fi Frequency of count source Cleared to 0 when interrupt request is accepted or cleaerd by software f1 fa f32 fc32 Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16 n 0016 to FF 16 Figure 1 47 Example of how an 8 bit pulse width modulator operates 58 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Timer B Figure 1 48 shows the block diagram of timer B Figures 1 49 and 1 50 show the timer B related registers Use the timer Bi mode register i 0 1 bits 0 and 1 to choose the desired mode Timer B has three operation modes listed as follows e Timer mode The timer counts an internal count source Event counter mode The timer counts pulses from an external source or a timer overfl
430. rtain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electron
431. rupt routine has been executed This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment a and the time required for executing the interrupt sequence b Figure 1 25 shows the interrupt response time Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine Interrupt response time a Time from interrupt request is generated to when the instruction then under execution is completed b Time in which the instruction sequence is executed Figure 1 25 Interrupt response time stENESAS 37 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Time a is dependent on the instruction under execution Thirty cycles is the maximum required for the DIVX instruction without wait Time b is as shown in Table 1 10 Table 1 10 Time required for executing the interrupt sequence Interrupt vector address Stack pointer SP value 16 bit bus without wait 8 bit bus without wait Even 18 cycles Note 1 20 cycles Note 1 Even 19 cycles Note 1 20 cycles Note 1 Odd Note 2 19 cycles Note 1 20 cycles Note 1 Odd Note 2 20 cycles Note 1 20 cycles Note 1 Note 1 Add 2 cycles in the case of a DBC interrupt add 1 cycle in the case either of an address match interrupt or of a single step
432. s accepted or cleared by software Timer X1 interrupt 4 request bit o or Cleared to 0 when interrupt request is accepted or cleared by software Figure 3 3 1 Operation timing of delayed one shot output TXOINOUT pin input fi fs O Used for one shot timer mode ao Timer XO interrupt request bit Timer X1 interrupt request bit Used for one shot timer mode Figure 3 3 2 Connection diagram of delayed one shot output stENESAS 347 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Setting timer X0 Selecting one shot timer mode and functions Selection of one shot timer mode Pulse output function select bit 0 Pulse is not output External trigger select bit 0 Falling edge of TXOINOUT pin s input signal Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode Count source select bit Count Count source period b7 b6 source f Xin 10MHz f Xc n 32 768kHz 00 f1 Toons 800ns 3 2us 976 56us N Setting trigger select register Select TXOINOUT pin to input TXO trigger TTT Trt 4 Li a select register Address 038316 E Timer X0 event trigger select bit b3 b2 0 0 Input on TXOINOUT is selected Note Note Set the corresponding port direction register to 0 inpu
433. s an example of circuit and Figures 3 6 3 and 3 6 4 show the set up procedure Use the following peripheral functions e Key input interrupts Stop mode e Pull up function Specifications 1 Use P30 through P33 for the scan output pins of a key matrix Use the input pins Klo through KI7 of the key input interrupt function for the key input reading pins The pull up function is also used 2 If a key input interrupt request occurs clear the stop mode and read a key Operation 1 Enable a key input interrupt and set the pull up function to pins Klo through KI7 Change the output of P30 through P33 to L and enter stop mode 2 If a key is pressed L is input to one of pins Klo through KI7 to clear stop mode A key input interrupt occurs to execute the key input interrupt handling routine 3 Sequentially set P30 through P33 to L to determine which key was pressed 4 When the process to determine the key pressed is completed change the output from P30 through P33 to L again and enter stop mode 1 Shift to stop mode 2 Cancel a stop mode 3 Key scan Key matrix scan 4 Shift to stop mode ra P30 output P31 output P32 output P33 output POo to P07 input Key input Key OFF Key ON Key OFF Key ON Key input L o interrupt processing CPU clock _ __ D Stop mode Stop mode Figure 3 6 1 Operation timing of controlling power using stop mode 354 tENESAS Renes
434. s becomes even or odd depending on which parity is chosen even or odd SP stop bit Either 1 bit or 2 bit H signal to be added immediately after character bits after the parity bit if parity is checked This they signals the end of data transmission 268 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 Transfer rate The divide by 16 frequency resulting from division in the bit rate generator BRG becomes the trans fer rate The count source for the transfer rate register can be selected from f1 f8 32 and the input from the CLK pin Clocks f1 f8 f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Table 2 6 2 Example of baud rate setting BRG s System clock 10MHz System clock 7 3728MHz Baud rate bps countsource BRG s set value n Actual time bps BRG s set value n Actual time bps tENESAS 269 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 3 An error detection In clock asynchronous serial I O mode detect errors are shown in Table 2 6 3 Table 2 6 3 Error detection Type of error Description Overrun error e This error occurs when the next data lines up before the content of the UARTIi receive buffer register is read The next data is written to th
435. s for further reduction in power consumption 3 Clearing stop mode and wait mode The stop mode and wait mode can be cleared by generating an interrupt request or by resetting hardware Set the priority level of the interrupt to be used for clearing higher than the processor interrupt priority level IPL and enable the interrupt enable flag I flag When an interrupt clears a mode that interrupt is processed Table 2 11 1 shows the interrupts that can be used for clearing a stop mode and wait mode 4 BCLK in returning from wait mode or stop mode a Returning from wait mode The processor immediately returns to the BCLK which was in use before entering wait mode b Returning from stop mode If operation was performed in the high speed mode or medium speed mode prior to engaging the stop mode CMO6 will change to 1 when operation shifts to the stop mode CM17 CM16 and CM07 do not change Accordingly when operation is restored from the stop mode operation starts in the 8 division mode Also if operation was performed in the low speed mode prior to engaging the stop mode CMO06 CM17 CM16 and CM07 do not change When operation is restored from the stop mode operation starts in the low speed mode Table 2 11 1 Interrupts available for clearing stop mode and wait mode Interrupt for clearing Key input interrupt Wait mode CM02 0 Possible CM02 1 Note 4 CM07 0 CM05 0 Possible Stop mode Po
436. s in one shot timer mode Specification Count source f1 fa f32 fC32 Count operation The timer counts down When the count reaches 000016 the timer stops counting after reloading a new count If a trigger occurs when counting the timer reloads a new count and restarts counting Divide ratio 1 n n Set value Count start condition An external trigger is input e The timer overflows e The one shot start flag is set 1 Count stop condition A new count is reloaded after the count has reached 000016 e The count start flag is reset 0 Interrupt request generation timing The count reaches 000016 TXiINOUT pin function Programmable I O port trigger input or pulse output Read from timer When timer Xi register is read it indicates an indeterminate value Write to timer When counting stopped When a value is written to timer Xi register it is written to both reload register and counter e When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Timer Xi mode register b7 b6 b5 b4 b3 b2 bi bd Address When reset o ifo TXIMR Oto 2 039716 to 039916 0016 iz R TMODO Operation mode b1 bo One select bit 1 0 One shot timer mode or pulse period TMOD1 pulse width measurement mode Pulse output function 0 Pulse is not output 1 select bit TXiINOOUT pin is a normal port
437. s oscillating stably 4 Division by 16 mode The main clock is divided by 16 to obtain the BCLK 5 No division mode The main clock is divided by 1 to obtain the BCLK 6 Low speed mode fc is used as BCLK Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa At least 2 to 3 seconds are required after the sub clock starts Therefore the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled 7 Low power dissipation mode fc is the BCLK and the main clock is stopped Note Before the count source for BCLK can be changed from XIN to XCIN or vice versa the clock to which the count source is going to be switched must be oscillating stably Allow a wait time in software for the oscillation to stabilize before switching over the clock Table 1 5 Operating modes dictated by settings of system clock control registers 0 and 1 Operating mode of BCLK Invalid Division by 2 mode Invalid Division by 4 mode Invalid Invalid Invalid Division by 8 mode 1 1 Invalid Division by 16 mode 0 0 Invalid No division mode Invalid Invalid Invalid 1 Low speed mode Invalid 24 Invalid Invalid 1 Low power dissipation mode tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE C
438. s polarity is reversed Timer AO mode register b7 b6 b5 b4 b3 b2 bi bO Symbol TAOMR Address 039616 When reset 0016 Bit symbol TMODO TMOD1 MRO RW Operation mode b1 b0 p 0 0 Timer mode select bit 0 Pulse is not output TAQouT pin is a normal port pin 1 Pulse is output Note 1 TAOQOUT pin is a pulse output pin b4 b3 0 X Note 2 Gate function not available TAOIN pin is a normal port pin Timer counts only when TAOIN pin is held L Note 3 Timer counts only when TAOIN pin is held H Note 3 Pulse output function select bit Gate function select bit 0 Must always be 0 in timer mode Count source select bit Note 1 Set the corresponding port direction register to 1 output mode Note 2 The bit can be 0 or 1 Note 3 Set the corresponding port direction register to 0 input mode Figure 1 41 Timer AO mode register in timer mode stENESAS Renesas Technology Corp 52 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 Event counter mode In this mode the timer counts an external signal or an internal timer s overflow Timer AO can count a single phase and a two phase external signal Table 1 13 lists timer specifications when counting a single phase external signal Figure 1 42 shows the timer AO mode register in event counter mode Table 1 14 lists timer specifications when countin
439. s to 1 to indicate that the reception is completed the UARTI receive interrupt request bit goes to 1 4 The receive complete flag goes to 0 when the lower order byte of the UARTi buffer register is read 280 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART Example of wiring Microcomputer Transmitter side IC CLKO CLK RxDO TxD Example of operation 4 Data is read 1 Reception enabled 3 Receiving is i 2 Start reception completed source k Receive enable bit rd PDO R D7 Stop bit E Receive data taken in l Transfer clock 7 i as F oo Reception started when transfer Transferred from UARTO receive register Clock is generated by falling edge to UARTO receive buffer register Receive 4 of start bit complete flag ot A ease Read to UARTO receive buffer register Receive interrupt 1 maae apie SE NH Cleared to 0 when interrupt request is accepted or cleared by software Timing of transfer data 8 bits long applies to the following settings Transfer data length is 8 bits Parity is disabled One stop bit Figure 2 6 9 Operation timing of reception in UART mode RENESAS 281 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART Setting UARTO transmit receive mode register b0 0 1 1 0 1 UARTO transmit r
440. s used to stop the main clock when placing the device in a low power mode If you want to operate with XIN after exiting from the stop mode set this bit to O When operating with a self excited oscillator set the system clock select bit CM07 to 1 before setting this bit to 1 When inputting external clock only clock oscillation buffer is stopped and clock input is acceptable If this bit is set to 1 XouT turns H The built in feedback resistor remains being connected so XIN turns pulled up to XouT H via the feedback resistor Set port Xc select bit CM04 to 1 and stabilize the sub clock oscillating before setting to this bit from 0 to 1 Do not write to both bits at the same time And also set the main clock stop bit CM05 to 0 and stabilize the main clock oscillating before setting this bit from 1 to O This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 8 fc32 is not included Do not set to 1 when using low speed or low power dissipation mode System clock control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 TT Jefetefer Symbol Address When reset CM1 000716 2016 Bit symbol Bit name Function L CM10 All clock stop control bit 0 Clock on Note 4 1 All clocks off stop mode
441. s when the A D conversion start flag changes to 1 Conversion speed per pin Without sample and hold function 8 bit resolution 49 oAD cycles 10 bit resolution 59 OAD cycles e With sample and hold function 8 bit resolution 28 AD cycles 10 bit resolution 33 OAD cycles Note 1 Does not depend on use of sample and hold function Note 2 Without sample and hold function set the oAD frequency to 250kHz min With the sample and hold function set the oAD frequency to 1MHz min stENESAS 89 Renesas Technology Corp A D Converter Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CKS1 1 Resistor ladder O o AD cksi o A D conversion rate selection Pree try Successive conversion register A D control register 1 address 03D716 Addresses A D control register 0 address 03D616 03C116 03C016 A D register 0 re 030316 03C216 A D register 1 03C516 030416 03C716 03C616 A D register 3 030916 03C816 A D register 4 16 16 A D register 2 16 16 16 Decoder 03CB16 03CA16 A D register 5 VIN Comparator AAAAAAA A 16 03CD16 03CC16 A D register 6 16
442. sas Technology Corp es S S S O Pin Description Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Pin Description Pin name Vcc Vss Signal name Power supply input I O type Function Supply 2 7 to 5 5 V to the Vcc pin Supply O V to the Vss pin CNVss CNVss Input Connect it to the Vss pin RESET Reset input Input A L on this input resets the microcomputer XIN XOUT Clock input Clock output Input Output These pins are provided for the main clock generating circuit Connect a ceramic resonator or crystal between the XIN and the XOUT pins To use an externally derived clock input it to the XIN pin and leave the XOUT pin open AVcc Analog power supply input This pin is a power supply input for the A D converter Connect it to VCC AVSS Analog power supply input This pin is a power supply input for the A D converter Connect it to Vss VREF Reference voltage input Input This pin is a reference voltage input for the A D converter POo to P07 I O port PO Input output This is an 8 bit CMOS I O port It has an input output port direction register that allows the user to set each pin for input or output individually When set for input the user can specify in units of four bits via software whether or not they are tied to a pull up resistor P10 to P17 I O port P1 Input output This is
443. se output from 4 TXiINOUT pin Timer Xi interrupt request bit Figure 2 4 8 Operation timing of timer mode pulse output function selected 228 stENESAS Renesas Technology Corp Timer X Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting timer mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of timer mode Pulse output function select bit 1 Pulse is output Note TXiINOUT pin is a pulse output pin Gate function select bit b4 b3 o l Gate function not available Set to 0X when pulse output function selected 0 Must always be 0 in timer mode Note Set the corresponding port direction register to 1 output mode Count source select bit Count Count source period b7 b6 i source f XN 10MHz f Xcin 32 768kHz 00 fi i 100ns 01 f8 10 f32 800ns 11 fc32 3 2us 976 56us Setting divide ratio b0 Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFF16 b7 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 Clock prescaler reset flag Address 0381 16 CPSRF bo XN
444. shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine 378 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt zZ Timer BO Timer X2 Timer X0 Timer B1 Timer X1 Priority of peripheral I O interrupts if priority levels are same UART1 reception UARTO reception A D conversion Timer AO UART1 transmission UARTO transmission oO Key input interrupt Figure 4 5 1 Maskable interrupts priorities peripheral I O interrupts Reset gt DBC gt Watchdog timer gt Peripheral I O gt Single step gt Address match Figure 4 5 2 Hardware interrupts priorities stENESAS 379 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 6 Multiple Interrupts The state when control branched to an interrupt routine is described below The interrupt enable flag I flag is set to 0 the interrupt is disabled The interrupt request bit of the accepted interrupt is set to 0 The processor interrupt priority level IPL is assigned to the same interrupt priority level as assigned to the accepted interrupt Setting the interrupt enable flag I flag to 1 within an interrupt routine allows an interrupt request
445. sion Information Output Command This command outputs the version information of the control program stored in the boot area Execute the version information output command as explained here following 1 Transfer the FB16 command code with the 1st byte 2 The version information will be output from the 2nd byte onward This data is composed of 8 ASCII code characters M16C reception data M16C transmit Gata vi fe kor ft AX P53 BUSY Figure 1 114 Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks 256 bytes Execute the boot ROM area output command as explained here following 1 Transfer the FC16 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively 3 From the 4th byte onward data Do D7 for the page 256 bytes specified with addresses As to A23 will be output sequentially from the smallest address first in sync with the fall of the clock As to V A16 to RxDO FC16 M16C reception data LECI J Tae faa TxDO data0 data255 M16C transmit data Ldatao A J Joata259 P53 BUSY Figure 1 115 Timing for boot ROM area output RENESAS 153 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version ID Check This c
446. source f1 f8 f32 fC Internal clock is selected n value set to BRGi e CLK polarity select bit 0 e Transmit interrupt cause select bit 0 Figure 2 5 5 Operation timing of transmission in clock synchronous serial I O mode tENESAS 255 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Setting UARTO transmit receive mode register b7 UARTO transmit receive mode register of I JoJo UOMR Address 03A016 Must be fixed to 001 Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Sleep select bit Must be 0 in clock synchronous I O mode Setting UARTO transmit receive control register 0 UARTO transmit receive control register 0 U0CO Address 03A416 q BRG count source select bit b1 b0 00 fi is selected 0 1 fg is selected 1 0 f32 is selected 11 fc is selected Must be 0 in clock synchronous I O mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in clock synchronous I O mode Data output select bit Note 0 TxDi pin is CMOS o
447. ss When reset b7 b6 b5 b4 b3 b2 bi bO ONSF 038216 XXXX00002 1 Timer ste ool When read the value is 0 ie col oo proces Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Figure 2 2 4 Timer A related registers 3 178 CENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Trigger select register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TRGSR 038316 0016 Timer AO event trigger select bit 99 Input on TAOIN is selected Note TB1 overflow is selected TAOTGH TX2 overflow is selected TXO overflow is selected Timer XO event trigger TXOTGL select bit eo Input on TXOINOUT is selected Note TB1 overflow is selected TXOTGH TAO overflow is selected TX1 overflow is selected Timer X1 event tri r TXITGL Eerie bit eventitrigge Input on TX1INOUT is selected Note TB1 overflow is selected TX1TGH TXO overflow is selected TX2 overflow is selected TX2TGL Timer X2 event trigger select bit Input on TX2INOUT is selected Note TB1 overflow is selected TX2TGH TX1 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset CPSRF 038116 OXXXXXXX2 Bitaymbol Brame Funan RW Nite sata a
448. ssible A D interrupt Note 3 Impossible Impossible UARTO transmit interrupt Possible Note 1 Note 1 UARTO receive interrupt Possible Note 1 Note 1 UART1 transmit interrupt Possible Impossible Impossible UART1 receive interrupt Possible Impossible Impossible Timer AO interrupt Possible Note 2 Note 2 Timer BO interrupt Possible Note 2 Note 2 Timer B1 interrupt Possible Note 2 Note 2 Timer XO interrupt Possible Note 2 Note 2 Timer X1 interrupt Possible Note 2 Note 2 Timer X2 interrupt Possible Note 2 Note 2 INTO interrupt Possible Possible Possible INT1 interrupt Possible Possible Note 1 Can be used when an external clock in clock synchronous serial I O mode is selected Note 2 Can be used when the external signal is being counted in event counter mode Note 3 Can be used in one shot mode and one shot sweep mode Note 4 When the MCU running in low speed or low power dissipation mode do not enter WAIT mode with CM02 set to 1 Possible 324 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 5 Sequence of returning from stop mode Sequence of returning from stop mode is oscillation start up time and interrupt sequence When interrupt is generated in stop mode
449. ssigned the highest priority watchdog timer interrupt etc are regulated by hardware Figure 1 29 shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine Interrupt Priority Level Judge Circuit This circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously Figure 1 30 shows the interrupt resolution circuit stENESAS Renesas Technology Corp 41 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Reset gt DBC gt Watchdog timer gt Peripheral I O gt Single step gt Address match Figure 1 29 Hardware interrupts priorities Priority level of each interrupt oe Level 0 initial value INT1 Timer BO High Timer X2 Timer XO Timer B1 Timer X1 UART1 reception UARTO reception A D conversion Timer AO Priority of peripheral I O interrupts a if priority levels are same UART1 transmission UARTO transmission Oo KEKE KEK EKER ERK ER ERK ERR ERR ERR Key input interrupt Processor interrupt priority level IPL Interrupt request level judgment output Interrupt enable flag I flag pilates reques Address match accepted Watchdog timer Figure 1 30 Interrupt resolution circuit 42 RENESAS Renesas Technology Corp Mitsubishi microcomputers
450. start flag Timer X1 one shot start flag Timer X2 one shot start flag Start count Figure 2 4 15 Set up procedure of one shot mode tENESAS Renesas Technology Corp 235 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 8 Operation of Timer X pulse period measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 4 7 Op erations of the circled items are described below Figure 2 4 16 shows the operation timing and Figure 2 4 17 shows the set up procedure Table 2 4 7 Choosed functions Count source Internal count source f1 fs f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to start counting the count source 2 If a measurement pulse changes from H to L the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is transferred to the reload register The timer Xi interrupt request does not generate 3 If a measurement pulse changes from H
451. start flag 1 Starts counting Timer X1 count start flag 1 Starts counting Start countin Figure 3 3 4 Set up procedure of delayed one shot output 2 RENESAS 349 Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 4 Buzzer Output Overview The timer mode is used to make the buzzer ring Figure 3 4 1 shows the operation timing and Figure 3 4 2 shows the set up procedure Use the following peripheral function e The pulse outputting function in timer mode of timer X Specifications 1 Sound a 2 kHz buzz beep by use of timer XO 2 Effect pull up in the relevant port by use of a pull up resistor When the buzzer is off set the port high impedance and stabilize the potential resulting from pulling up 3 Connect a 10 MHz oscillator to XIN Operation 1 The microcomputer begins performing a count on timer X0 Timer XO has disabled interrupts 2 P43 is TXOINOUT pin Setting the port P43 direction register to 1 output mode and outputs 2 kHz pulses 3 The microcomputer stops outputting pulses by setting the port P43 direction register to 0 input mode P43 goes to an input pin and the output from the pin becomes high impedance 1 Start count 2 Buzzer output ON 3 Buzzer output OFF Timer X0 overflow timing i Count start flag o f Port P43 direction 1 register w P43 output l
452. ster is set no address match interrupt occurs 2 Peripheral I O interrupts A peripheral I O interrupt is generated by one of built in peripheral functions The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses Peripheral I O interrupts are maskable interrupts e Key input interrupt A key input interrupt occurs if an L is input to the KI pin A D conversion interrupt This is an interrupt that the A D converter generates e UARTO and UART1 transmission interrupt These are interrupts that the serial I O transmission generates UARTO and UART1 reception interrupt These are interrupts that the serial I O reception generates Timer AO interrupt This is an interrupts that timer AO generates Timer BO and timer B2 interrupt These are interrupts that timer B generates e Timer XO to timer X2 interrupt These are interrupts that timer X generates e INTO and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin 30 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupts and Interrupt Vector Tables If an interrupt request is accepted a program branches to the interrupt routine set in the interrupt vector table Set the first address of the interrupt routine in each vector table Figure 1 23 shows format for specifying interrupt vec
453. stop mode Figure 2 11 5 Example of stop mode set up stENESAS 327 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 3 Wait Mode Set Up Settings and operation for entering wait mode are described here 1 2 3 4 Enables the interrupt used for returning from wait mode Sets the interrupt enable flag I flag to 1 Clears the protection and changes the content of the system clock control register Executes the WAIT instruction Operation _ eS HS YH WH 1 Setting interrupt to cancel wait mode Interrupt control register KUPIC Address 004D16 Address 004E16 Address 005116 005316 Address 005216 005416 Address 005516 Address 005616 to 005816 Address 005A16 005B16 INTIIC i 0 1 Address 005D16 005E16 m SS are LEI OOS a6 w b7 bo ne Interrupt priority level select bit Interrupt priority level select bit Make sure that the interrupt priority Make sure that the interrupt priority level of the level of the interrupt which is used interrupt which is used to cancel the wait mode is to cancel the wait mode is higher higher than the processor interrupt priority IPL of than the processor interrupt priority the routine where the WAIT instruction is executed IPL of the routine where the WAIT instruction is executed Reserved bit Must be set to 0 Xe
454. suring mode x a Timer B1 e Event counter mode Figure 1 36 Timer block diagram 48 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer A Figure 1 37 shows the block diagram of timer A Figures 1 38 to 1 40 show the timer A related registers Use the timer AO mode register bits 0 and 1 to choose the desired mode Timer A has the four operation modes listed as follows e Timer mode The timer counts an internal count source e Event counter mode The timer counts pulses from an external source or a timer over flow e One shot timer mode The timer stops counting when the count reaches 000016 e Pulse width modulation PWM mode The timer outputs pulses of a given width Data bus high order o Clock source selection Data bus low order i fi o High order f8 o 5 8 bits f32 O e Timer gate function e Event counter Counter 16 Clock selection Up count down count Count start flag fo down count in event counter mode TB1 overflow _ O Down count O External TXO overflow 0O trigger Up down flag O O TX2 overflow O Pulse output TAOOUT O Toggle flip flop Figure 1 37 Block diagram of timer A Timer AO mode register Symbol Address When reset b7 b6 b5 b4 b3 b2 bi b0 TAOMR 039616 0016 Bit symbol RW Timer mode E
455. synchronous serial 1 O mode Function During UART mode CLKO BRG count source select bit CLK1 fi is selected fs is selected fs2 is selected fc is selected b 0 Ws 0 iz b1 b0 f1 is selected fe is selected f32 is selected 0 0 1 11 fc is selected 0 1 0 1 Set this bit to 0 TXEPT Transmit register empty flag Data present in transmit register during transmission No data present in transmit register transmission completed 0 Data present in transmit register during transmission No data present in transmit register transmission completed Set this bit to 1 Data output select bit CKPOL CLK polarity select bit UFORM Transfer format select bit TXDi pin is CMOS output 0 1 TXDi pin is N channel open drain output Transmit data is output at alling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at alling edge 0 LSB first 1 MSB first TXDi pin is CMOS output TXDi pin is N channel open drain output Must always be 0 Must always be 0 Note UART1 cannot be used in clock synchronous serial I O Figure 2 5 3 Serial l O related registers 2 252 2CENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Cl
456. t control register TBOIC 005B16 Timer B1 interrupt control register TB1IC RY 038016 Count start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 Trigger select register TRGSR 038416 Up down flag UDF 039016 039116 039216 039316 Timer BO TBO Timer B1 TB1 Ry 039B16 Timer BO mode register TBOMR 039C16 Timer B1 mode register TB1MR Figure 2 3 1 Memory map of timer B related registers tENESAS 207 Renesas Technology Corp Timer B Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer Bi mode register Symbol Address When reset pi IR eck ease ct TBIMR i 0 1 039B16 039C16 00XX00002 Bit symbol TMODO Operation mode select bit Timer mode Event counter mode Pulse period pulse width measurement mode Inhibited OD1 Function varies with each operation mode MR1 MR2 MR3 TCKO Count source select bit TCK1 Function varies with each operation mode Note 1 Timer BO Note 2 Timer B1 Figure 2 3 2 Timer B related registers 1 208 tENESAS Renesas Technology Corp Timer B Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer Bi register Note Address When reset 039116 039016 Indeterminate b15 039316 039216 Indeterminate Function Timer mode 000016 to FFFF16 Counts the timer s period e E
457. t data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Mitsubishi Electric Corporation by various means including the Mitsubishi Semiconductor home page hittp www mitsubishichips com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss resulting from the information contained herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in
458. t disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested 1 Interrupt requested Note 1 O 1 Selects rising edge O Reserved bit Always set to 0 oio Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Polarity select bit 0 Selects falling edge Note 1 This bit can only be accessed for reset 0 but cannot be accessed for set 1 Note 2 To rewrite the interrupt control register do so at a point that dose not generate the interrupt request for that register For details see the precautions for interrupts Figure 4 2 2 Interrupt control registers 370 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 2 1 Interrupt Enable Flag The interrupt enable flag I flag controls the enabling and disabling of maskable interrupts Setting this flag to 1 enables all maskable interrupts setting it to O disables all maskable interrupts This flag is set to 0 after reset The content is changed when the flag is changed causes the acceptance of the interrupt request in the following timing e When changing the flag using the REIT instruction the acceptance of the interrupt takes effect as the REIT instruction is executed e When changing the flag using
459. t hold time Table 1 55 External interrupt INTi inputs Wi a Symbol Parameter Unit tw INH INTi input HIGH pulse width tw INL INTI input LOW pulse width ma stENESAS 117 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V TAOIN input TAOOUT input tw UPL TAOOUT input Up down input X During event counter mode TAOIN input When count on falling th Tin UP tsu UP Tin edge is selected TAOIN input I When count on rising edge is selected TBIIN input tw TBL tc TX TXiINOUT input TxDi RxDi INTI input 118 2tENESAS Renesas Technology Corp Electrical characteristics Vcc 3V Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 56 Electrical characteristics Note 1 Vcc 3V e Standard Symbol Parameter Measuring condition Min Typ Max Unit VoH HIGH output P0Oo to P07 P10 to P17 P30 to P35 iis na 25 v voltage P4o to P45 P50 to P54 P60 to P67 P70 P71 HIGHPOWER loH 1mA 2 5 vor age x0 9 LOWPOWER lon 50pA 25 HIGHPOWER No load 3 0 VOH fered a XCOUT V 9 LOWPOWER No load 16 VoL LOW output P0o to P07 P30 to P
460. t mode Mes Setting delay time b15 b7 Timer X0 register Address 038916 038816 TXO Continued to the next page Figure 3 3 3 Set up procedure of delayed one shot output 1 348 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Continued from the previous page Setting timer X1 Selecting one shot timer mode and functions Selection of one shot timer mode Pulse output function select bit Note 1 Pulse is output TX1INOUT pin is pulse output pin External trigger select bit Invalid when choosing timer s overflow Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode Count source select bit r Sount Count source pared 00 f1 p source Xin 10MHz_ f Xci n 32 768kHz 100ns 800ns 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Setting trigger select register Set timer XO to trigger timer X1 aero Trigger select register Address 038316 Timer X1 event trigger select bit b5 b4 1 0 TXO overflow is selected Setting one shot timer s time b15 b8 x bo 67 b0 Timer X1 register Address 038B16 038A16 la Setting count start flag bo De aay Count stari flag Address 038016 Timer XO count
461. t timer 1 Mode Timer B operates in one of three modes a Timer mode The internal count source is counted Operation in mer MOUS se sie cecee ccc desacencdecedseascavenautsstuccaawaasdecautadaceuecasdgetuacuusteedodvabeacedeentidaceecaties P210 b Event counter mode The number of pulses coming from outside and the number of the timer overflows are counted e Operation in event counter MOE eeeeeececeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeseaeeeseneeeseaeeeseaaeeseeeeeetaeeseenes P212 c Pulse period measurement pulse width measurement mode External pulse period or external pulse widths are measured If pulse period measurement mode is selected the periods of input pulses are continuously measured If pulse width measurement mode is selected widths of H level pulses and those of L level pulses are continuously measured e Operation in pulse period measurement mode ceceececeeesseeeeeeseceeeeeeeesneeeeeeseseeeeesenseeeeeeees P214 Operation in pulse width measurement mode ccceecceeceecsteeeeeesseeeeeeesesneeeeeeesseeeeeessieeeeeeees P216 2 Count source An internal count source can be selected from f1 fs f32 and fc32 f1 f8 and f32 are clocks obtained by dividing the CPU main clock by 1 8 and 32 respectively fc32 is the clock obtained by dividing the CPU secondary clock by 32 3 Frequency division ratio The frequency division ratio equals the value set in the timer register 1 The count
462. t to the relevant pins The output level remains floating 2 Reading a port register With the direction register set to output reading a port register takes out the content of the port regis ter not the content of the pin With the direction register set to input reading the port register takes out the content of the pin 3 Effect of the protection register Data written to the direction register of P4 is affected by the protection register The direction register of P4 cannot be easily rewritten 4 Setting pull up The pull up control bit allows setting of the pull up in terms of 4 bits either in use or not in use For the four bits chosen pull up is effective only in the ports whose direction register is set to input Pull up is not effective in ports whose direction register is set to output Do not set pull up of corresponding pin when XCIN XCOUT is set or a port is used as A D input 5 Drive capacity control The drive capacity of the N channel output transistor on P1 can be set between LOW and HIGH in units of 1 bit One bit corresponds to one pin 330 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports 6 I O functions of built in peripheral devices Table 2 12 1 shows relation between ports and I O functions of built in peripheral devices Table 2 12 1 Relation between ports and I O functions of built in pe
463. t to write to these bits write O The value if read turns out to be indeterminate Note 1 This bit can only be accessed for reset 0 but cannot be accessed for set 1 Note 2 To rewrite the interrupt control register do so at a point that dose not generate the interrupt request for that register For details see the precautions for interrupts Port PO direction register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PDO 03E216 0016 RIW L P00_0 T Por Poo drecion reser oo Port P01 direction register 0 ER an input port O 0 Port P02 direction register 1 Output mode o0 Port P03 direction register Functions as an output port o o Port P04 direction register O10 Port PO5 direction register O10 Port P06 direction register oio Port P07 direction register O O Pull up control register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PURO 03FC16 0016 Bit symbol RW ee pote Eis pale The corresponding port is pulled 0 0 PUO1 P04 to P07 pull up high with a pull up resistor O 0 PU02 P10 to P13 pull up B e i 0 0 PU03 P14 to P17 pull up O O PU06 P30 to P33 pull up 10 0 PU07 P34 to P35 pull up 10 0 Figure 2 10 2 key input interrupt related registers stENESAS 319 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt 2 10 2 Operation of Key Input Interrupt The following is an opera
464. taaeeneaeees e Reception WITHOUT other functions 0 2 cece cece eeeeeeeeeeeeeeeeneeeceaeeeeeaaeeeeaeeessaaeeseeeeeesaeesteneees 5 Input output to the serial I O and the direction register To input an external signal to the serial I O set the direction register of the relevant port to input To output a signal from the serial I O set the direction register of the relevant port to output 6 Pins related to the serial I O e CLKo pins Input pins for the transfer clock e RxDo RxD1 pins Input pins for data e TxDo TxD1 pins Output pins for data tENESAS Renesas Technology Corp 271 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 8 Registers related to the serial I O Figure 2 6 2 shows the memory map of serial I O related registers and Figures 2 6 3 to 2 6 7 show UARTIi related registers 005116 UARTO transmit interrupt control register SOTIC 005216 UARTO receive interrupt control register SORIC 005316 UART1 transmit interrupt control regster S1 TIC 005416 UART1 receive interrupt control register S1RIC m 7 03A016 UARTO transmit receive mode register UOMR 03A116 UARTO bit rate generator UOBRG ace UARTO t t buff ter UOTB 03A316 ransmit buffer register i 03A416 UARTO transmit receive control register 0 UOCO i i 03A516 UARTO transmit receive control register 1 U0C1 03A616 03A716 03A816 UART1 transmit receive m
465. tandard serial I O mode control program which is stored in it when shipped from the factory This area can be erased and programmed in only parallel I O mode RENESAS 125 Renesas Technology Corp Description Flash memory version Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Flash Memory The M30201 flash memory version contains the NOR type of flash memory that requires a high voltage VPP power supply for program erase operations in addition to the Vcc power supply for device operation For this flash memory three flash memory modes are available in which to read program and erase parallel I O and standard serial I O modes in which the flash memory can be manipulated using a program mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit CPU Each mode is detailed in the pages to follow In addition to the ordinary user ROM area to store a microcomputer operation control program the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I O modes This boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory However the user can write a rewrite control program in this area that suits the user s application system This boot ROM area can be rewritten in only parallel I O mode Figure 1 96 Block diagram of flash memory versio
466. tart condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Operation 1 If the TAOIN pin input level changes from L to H with the count start flag set to 1 the counter performs a down count on the count source Also the TAOOUT pin outputs an H level 2 The TAOQOUT pin output level changes from H to L when a set time period elapses At this time the timer AO interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAOOUT outputs an L level Note e PWM pulse cycle is 2 6 1 fi whereas H level duration is n fi However when 000016 is set for the timer AO register the PWM output is L level for the entire period and an interrupt request is generated for every PWM output cycle Also when FFFF 16 is set for the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f82 f 32 n Timer value Conditions Reload register 000316 external trigger rising edge of TAOIN pin input signal is selected 1 fi
467. tart count 3 In stopped state or WAIT 4 Generate i 1 instruction is executing etc watchdog timer 2 Write operation interrupt 000016 Write signal to the H watchdog timer start register L Figure 2 8 3 Operation timing of watchdog timer 312 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer Va Setting watchdog timer control register Watchdog timer control register Address 000F 16 Reserved bit Must always be 0 Prescaler select bit 0 Divided by 16 1 Divided by 128 Setting watchdog timer start register b7 bo ooo Watchdog timer start register Address 000E16 WDTS Loo The watchdog timer is initialized and starts counting with a write instruction to this register The watchdog timer value is always initialized to 7FFF16 regardless of the value written Generating watchdog timer interrupt Va Software reset aac Processor mode register 0 Address 000416 PMO Software reset bit The device is reset when this bit is set to 1 The value of this bit is O when read XX Figure 2 8 4 Set up procedure of watchdog timer stENESAS 313 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt 2 9 Address Match Interrupt 2 9
468. tempt to write to these bits write 0 The value if read turns out to be indeterminate Figure 2 7 4 A D converter related registers 3 stENESAS 289 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 2 Operation of A D converter one shot mode In one shot mode choose functions from those listed in Table 2 7 2 Operations of the circled items are described below Figure 2 7 5 shows the operation timing and Figure 2 7 6 shows the set up procedure Table 2 7 2 Choosed functions Operation clock AD Divided by 4 fab divided by 2 fab fap Resolution 8 bit 10 bit Analog input pin One of ANo pin to AN7 pin Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to begin operating 2 After A D conversion is completed the content of the successive comparison register con version result is transmitted to A D register i At this time the A D conversion interrupt re quest bit goes to 1 Also the A D conversion start flag goes to 0 and the A D converter stops operating 1 Start A D conversion 2 A D conversion is complete 8 bit resolution 28 aD cycles 10 bit resolution 33 aD cycles A
469. tents of the direction registers change due to a runaway generated by noise or other causes setting the contents of the direction registers periodically by use of software increases program reliability Note 2 When an external clock is input to the XIN pin RENESAS 331 Renesas Technology Corp Programmable I O Ports Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 8 Registers related to the programmable I O ports Figure 2 12 1 shows the memory map of programmable I O ports related registers and Figures 2 12 2 to 2 12 4 show programmable I O ports related registers 03E016 Port PO PO S pate PPPO OOO OOOO 03E216 Port PO direction register PDO 03E316 Port P1 direction register PD1 o OSESt6 PortP3 P3 a 03E716 Port P3 direction register PD3 03E816 Port PA PA S 03E916 Port P5 P5 S oaEc1e Pon P6 PE mS rw O3FCi6 Pull up control register O PURO 03FD16 Pull up control register 1 PUR1 03FE16 Port P1 drive control register DRR Figure 2 12 1 Memory map of programmable I O ports related registers 332 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports Port Pi direction register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PDi i 0 to 7 03E216 03E316 03E716 03EA16 0016 03EB16 03EE16 03EF16 Poo Port Fio direction register a s
470. ter 7 Address 03CF16 03CE16 Eight low order bits of A D conversion result When read the content is indeterminate ar Setting A D conversion start flag b7 bO 0 A D control register 0 Address 03D616 A D conversion start flag 0 A D conversion disabled Me Stop A D conversion Figure 2 7 12 Set up procedure of repeat sweep 0 mode tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 6 Operation of A D Converter in repeat sweep mode 1 In repeat sweep 1 mode choose functions from those listed in Table 2 7 6 Operations of the circled items are described below Figure 2 7 13 shows ANi pin s sweep sequence Figure 2 7 14 shows timing chart and Figure 2 7 15 shows the set up procedure Table 2 7 6 Choosed functions Operation clock AD Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit Analog input pin ANo 1 pins ANo to AN1 2 pins ANo to AN2 3 pins ANo to ANs 4 pins Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo ANB50 pin 2 After the A D conversion on voltage input to the ANo AN50 pin is complete
471. terrupt request bit Refer to Precaution for Timer A pulse width modulation mode b7 bo SSNS Timer AO interrupt control register Address 005516 DODA racic E gister l Interrupt request bit Setting trigger select register b7 bd Trigger select register Address 038316 TRGSR L Timer AO event trigger select bit b1 bO 0 0 Input on TAOIN is selected Note 2 Note 2 Set the corresponding port direction register to 0 input mode Setting PWM pulse s H level width b15 b8 b7 b0 b7 b0 re T O OE Timer AO register Address 038716 038616 TAO Ke Can be set to 000016 to FFFE16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 AAAA TATATA Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count starts flag b7 b0 Count start flag Address 038016 Uta Trt TABSR Timer AO count start flag Start count Figure 2 2 25 Set up procedure of pulse width modulation mode 16 bit PWM mode selected stENESAS 199 Renesas Technology Corp Mitsubishi microcomputers M30201 Group f SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 12 Operation of Timer A pulse width
472. the operating status of the auto erase operation If an erase error occurs it is set to 1 When the erase status is cleared it is set to O Program Status SR4 The program status reports the operating status of the auto write operation If a write error occurs it is set to 1 When the program status is cleared it is set to 0 RENESAS 155 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version Status Register 1 SRD1 Status register 1 indicates the status of serial communications results from ID checks and results from check sum comparisons It can be read after the SRD by writing the read status register command 7016 Also status register 1 is cleared by writing the clear status register command 5016 Table 1 81 gives the definition of each status register 1 bit 0016 is output when power is turned ON and the flag status is maintained even after the reset Table 1 81 Status register 1 SRD1 f Definition SRD1 bits Status name O Boot update completed bit Update completed Not update Reserved Reserved Checksum match bit Mismatch ID check completed bits Not verified Verification mismatch Reserved Verified SR9 bit1 Data receive time out Time out Normal operation SR8 bit Reserved z Boot Update Completed Bit SR15 This
473. the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANs4 Frequency select bit 1 Vref connect bit Must be fixed to 0 A D input group select bit N A D control register 1 Address 03D716 ADCON1 A D sweep pin select bit Note 2 b1 bo 0 0 ANo AN1 2 pins 0 1 ANo to AN8 4 pins 1 0 ANo to ANs 6 pins 1 1 ANo to AN7 8 pins A D operation mode select bit 1 Note 1 0 Must always be 0 in repeat sweep mode 0 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode 0 fAD 2 or fAD 4 is selected 1 faD is selected 1 Vref connected 0 Port P6 group is selected 1 Port P5 group is selected Setting A D conversion start flag b7 b0 CCILL A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Repeatedly carries out A D conversion on pins selected through the A D sweep pin select bit Start A D conversion Reading conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode NS A D registerO Address 03C 116 03C016 ba A D register 1 Address 03C316 03C216 bO b7 bo A D register2 Address 03C516 030416 A D register 3 Address 03C716 03C616 A D register 4 Address 03C916 03C816 A D register 5 Address 03CB16 03CA16 A D register 6 Address 03CD16 03CC16 A D regis
474. the power dissipation When using the A D converter start A D conversion only after setting bit 5 of 03D716 to connect VREF The result of A D conversion is stored in the A D registers of the selected pins When set to 10 bit precision the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses When set to 8 bit precision the low 8 bits are stored in the even addresses Table 1 29 shows the performance of the A D converter Figure 1 82 shows the block diagram of the A D converter and Figures 1 83 and 1 84 show the A D converter related registers Table 1 29 Performance of A D converter Item Performance Method of A D conversion Successive approximation capacitive coupling amplifier Analog input voltage Note 1 OV to AVcc Vcc Operating clock oAD Note 2 Vcc 5V __fAD divide by 2 of fAD divide by 4 of fAD fAD f XIN Voc 3V divide by 2 of fAD divide by 4 of fAD fAD f XIN Resolution 8 bit or 10 bit selectable Absolute precision Vcc 5V Without sample and hold function 3LSB e With sample and hold function 8 bit resolution 2LSB e With sample and hold function 10 bit resolution 3LSB Vcc 3V e Without sample and hold function 8 bit resolution 2LSB Operating modes One shot mode repeat mode single sweep mode repeat sweep mode 0 and repeat sweep mode 1 Analog input pins 8 pins ANo to AN7 5 pins AN50 to AN54 A D conversion start condition e Software trigger A D conversion start
475. ting Circuit sius ai ia i i aia d ii ia aa a ea ai 18 GlOCK CONTON iaa eared aa ee th ee casi a a AAE shi aaa A a E A aa te oh ease hed te 19 Clock Output an aada adele iin iaa a Mandal hata dai 22 SLOP MOGE sx sev vertes evs E oth a apa nto A et escent dead A tanks otha ace 23 Wait MOU vac aaiae oeiee ALENE EEA ANTA EDAC EAEN AAE vee esdev yee ce eee 23 POWEP SAVING eia anaa aeaa e ea ea Aa aa rete ahaa aie A aa AmE aae T a SE aa dled Ea GAE gee ee ee 25 POLO CUI raas Ea EENE E E A EAEN 27 iiernupi raei a antes a a a leh ea E a E tae Settee ad 28 Watchdog Time ers esea a E E a aN 46 THIMG EE E AE E E EA EEE E E EE E E TE ET 48 aE a E E A E E E 49 TIMOR Beere a a a a ee eed Seen bei tay 59 TINOLA aera A ack Gpbeeeti sah hivtaciacudtecs A E 65 SOMali O E EE ETETE AAE E A A AE EEE 75 A D Converterin aa a a a a a a a a E a 89 Programmable VO PORNS miiia e aa ate a ea td aaa ee a a At a 99 Usage Precaution 22224 eE E RAA E ARER E TE E R E aeons die 107 Electrical CharacteriStiCs ssccscclezcteseesteccuphbrecucevbirenetethbeauced EE EAE TEA REEERE EOE TNE REESE 111 Outline Performance Flash Memory ccccceseeceeeeeeeeeeeeseceeeceaaeeeeeeeeseaaeeeeeeeeseeaeeeseaeeseeeeeseaeeneaes 125 Rash Memo ooreen a e a a a e a aE a a ee 126 O AB REANO CA TE T E 127 Parallel O MOTE ea a a ar e a a a a aA a a T a leva eect bated a a aa aae i anana 134 Standard Serial I O 010 146 Chapter 2 Peripheral Functions Usage 221 Protect ane ie Mast
476. tion During clock synchronous During UART mode R W serial I O mode H UOIRS UARTO transmit 0 Transmit buffer empty Transmit buffer empty interrupt cause select bit 1 Tl 1 1 Transmission completed eaoh completed TXEPT 1 TXEPT 1 UART1 transmit Set this bit to 0 a buffer empty interrupt cause select bit Ile Transmission completed TXEPT 1 UARTO continuous Continuous receive receive mode enable bit mode disabled Continuous receive mode enable Set this bit to O OO CLKMDO CLK CLKS select bit 0 Valid when bit 5 1 Must always be 0 i Clock output to CLK1 Clock output to CLKS1 CLKMD1 CLK CLKS select 0 Normal mode Must always be 0 bit 1 Note 2 CLK output is CLKO only 1 Transfer clock output from multiple pins function selected Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 When using multiple pins to output the transfer clock the following requirements must be met e UARTO internal external clock select bit bit 3 at address 03A016 0 Figure 2 5 4 Serial I O related registers 3 stENESAS 253 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 2 Operation of Serial I O tr
477. tion of key input interrupt Figure 2 10 3 shows an example of a circuit that uses the key input interrupt Figure 2 10 4 shows an example of operation of key input interrupt and Figure 2 10 5 shows the setting procedure of key input interrupt Operation 1 Set the direction register of the ports to be changed to key input interrupt pins to input and set the pull up function 2 Setting the key input interrupt control register and setting the interrupt enable flag makes the interrupt enabled state ready 3 If a falling edge is input to either Klo through KI7 the key input interrupt request bit goes to 1 P30 P31 P32 P33 V O port P00 Klo Po1 Kit P02 Kl2 Pos Kis Po4 Kl4 POs KI5 POs Kle Hmo Hmo Hmo Hmo Hmo pme pme Hamp P07 KI7 Figure 2 10 3 Example of circuit using the key input interrupt 1 Enter to stop mode 2 Cancel stop mode 3 Key scan oi Key matrix scan 4 Enter to stop mode P30 output P31 output P32 output P33 output P04 to P07 input y y y Key input Key OFF Key ON Key OFF Key ON Key input interrupt processing r Figure 2 10 4 Example of operation of key input interrupt 320 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt a Setting port P10 direction register b7 bO a Port PO direction registe
478. tion of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer at the time of acceptance of an interrupt request is even or odd If the content of the stack pointer Note is even the content of the flag register FLG and the content of the program counter PC are saved 16 bits at a time If odd their contents are saved in two steps 8 bits at atime Figure 4 3 4 shows the operation of the saving registers Note Stack pointer indicated by U flag 1 Stack pointer SP contains even number Address Stack area Sequence in which order registers are saved SP 4 Even Program counter PC 2 Saved simultaneously SP 3 Odd Program counter PCw all 16 bits SP 2 Even Flag register FLG 1 Saved simultaneously z Flag register Program all 16 bits SP 1 Odo FLGH counter PCu in two operations Finished saving registers 2 Stack pointer SP contains odd number Address Stack area Sequence in which order registers are saved SP 4 Odd Program counter PCL ISP Program counter PCm ll 8 bi SP 2 Odd Flag register FLG al 8 bits B Flag register Program SP 1 Even FLG counter PCH SP Odd Finished saving registers in four operations Note SP denotes the initial value of the stack pointer SP when interrupt request is acknowledged After registers are saved the SP content is SP minus 4
479. tion side are independent of each other so full duplex communication is possible The following is an overview of the clock asynchronous serial I O 1 Transmission reception format Figure 2 6 1 shows the transmission reception format and Table 2 6 1 shows the names and func tions of transmission data Transfer data length 7 bits _ _ 1ST 7DATA __ 1SP m 1ST 7DATA 2SP m 1ST 7DATA 1PAR 1SP __ 1ST 7DATA 1PAR 2SP Transfer data length 8 bits _ 1ST 8DATA 1SP m 1ST 8DATA 2SP m 1ST 8DATA 1PAR 1SP 1ST 8DATA 1PAR 2SP Transfer data length 9 bits _ 1ST 9DATA __ 1SP m 1ST 9IDATA _ 2SP m 1ST 9DATA 1PAR 1SP 1ST 9DATA 1PAR 2SP ST Start bit Character bit Transfer data Parity bit Stop bit Figure 2 6 1 Transmission reception format Table 2 6 1 Transmission data names and functions ST start bit A 1 bit L signal to be added immediately before character bits This bit signals the start of data transmission DATA character bits Transmission data set in the UARTIi transmit buffer register PAR parity bit A signal to be added immediately after character bits so as to increase data reliability The level of this signal so varies that the total number of 1 s in character bits and this bit alway
480. tions for the standard serial I O mode Serial data I O uses UARTO and transfers the data serially in 8 bit units Standard serial I O switches between mode 1 clock synchronized and mode 2 clock asynchronized according to the level of P53 BUSY pin when the reset is released To use standard serial I O mode 1 clock synchronized set the P53 BUSY pin to H level and release the reset The operation uses the four UARTO pins CLKo RxDo TxDo and P53 BUSY The CLKo pin is the transfer clock input pin through which an external transfer clock is input The TxDo pin is for CMOS output The P53 BUSY pin outputs an L level when ready for reception and an H level when reception starts To use standard serial I O mode 2 clock asynchronized set the P53 BUSY pin to L level and release the reset The operation uses the two UARTO pins RxDo and TxDo In the standard serial I O mode only the user ROM area indicated in Figure 1 96 can be rewritten The boot ROM cannot In the standard serial I O mode a 7 byte ID code is used When there is data in the flash memory com mands sent from the peripheral unit are not accepted unless the ID code matches 146 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode 1 Flash Memory Version Overview of standard serial I O mode 1 clock synchronized In standard serial I O mode 1 software com
481. to 0 Set the interrupt priority level to level 1 to 7 Enable the accepting of INTi interrupt request Set the interrupt enable flag to 1 Enable interrupt i Figure 1 33 Switching condition of INT interrupt request 4 Changing interrupt control register See Changing Interrupt Control Register stENESAS 45 Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control The watchdog timer is a 15 bit counter which down counts the clock derived by dividing the BCLK using the prescaler A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer When XIN is selected for the BCLK bit 7 of the watchdog timer control register address 000F16 selects the prescaler division ratio by 16 or by 128 When XCIN is selected as the BCLK the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register address OOOF 16 When XIN is selected in BCLK Prescaler division ratio 16 or 128 x watchdog timer count 82768 BCLK Watchdog timer cycle When XCIN is selected in BCLK Prescaler division ratio 2 x watchdog timer count 82768 BCLK Watchdog timer cycle For example when BCLK is 10MHz and the prescaler division ratio is set to 16 the watchdog timer cycle is approximately 52 4
482. to O disables all maskable interrupts This flag is set to 0 after reset Interrupt Request Bit The interrupt request bit is set to 1 by hardware when an interrupt is requested After the interrupt is accepted and jumps to the corresponding interrupt vector the request bit is set to 0 by hardware The interrupt request bit can also be set to 0 by software Do not set this bit to 1 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL Set the interrupt priority level using the interrupt priority level select bit which is one of the component bits of the interrupt control register When an interrupt request occurs the interrupt priority level is compared with the IPL The interrupt is enabled only when the priority level of the interrupt is higher than the IPL Therefore setting the interrupt priority level to O disables the interrupt Table 1 8 shows the settings of interrupt priority levels and Table 1 9 shows the interrupt levels enabled according to the contents of the IPL The following are conditions under which an interrupt is accepted interrupt enable flag I flag 1 interrupt request bit 1 interrupt priority level gt IPL The interrupt enable flag I flag the interrupt request bit the interrupt priority select bit and the IPL are independent and they are not affected by one another Table 1 8 Settings of interrupt priority levels Tabl
483. tor addresses Two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting Vector address 0 Mid address Vector address 2 Bao High address 0000 Figure 1 23 Format for specifying interrupt vector addresses Vector address 1 Vector address 3 0000 e Fixed vector tables The fixed vector table is a table in which addresses are fixed The vector tables are located in an area extending from FFFDC16 to FFFFF16 One vector table comprises four bytes Set the first address of interrupt routine in each vector table Table 1 6 shows the interrupts assigned to the fixed vector tables and addresses of vector tables Table 1 6 Interrupt and fixed vector address Interrupt source Undefined instruction Vector table addresses Address L to address H FFFDCie to FFFDFi6 Remarks Interrupt on UND instruction Overflow FFFEOt16 to FFFES3i6 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716 If the vector is filled with FF16 program execution starts from the address shown by the vector in the variable vector table Address match FFFE816 to FFFEBis There is an address matching interrupt enable bit Single step Note FFFECie to FFFEF 16 Do not use Watchdog timer FFFFO016 to FFFF316 DBC Note FFFF416 to FFFF 16 Do not use FFFF816 to FFFF
484. transmission Transmit enable bit TE Data is set in UARTi transmit buffer register Transmit buffer empty flag TI Transferred from UARTI transmit buffer register to UARTi transmit register Parity Stop Stopped pulsing because transfer enable bit 0 bit to TxDi Transmit register empty flag TXEPT Transmit interrupt request g bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc 16 n 1 fi or 16 n 1 fEXT e Parity is enabled fi frequency of BRGi count source f1 fs 32 fC One stop bit fEXT frequency of BRGi count source external clock e Transmit interrupt cause select bit 1 n value set to BRGi Figure 2 6 6 Operation timing of transmission in UART mode stENESAS 277 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART Setting UARTIi transmit receive mode register i 0 1 b a 110 7 UARTO transmit receive mode register UOMR Address 03A016 UART1 transmit receive mode register U1MR Address 03A816 Hi Serial I O mode select bit b2 b1 b0 1 0 1 Transfer data 8 bits long Internal external clock select bit 0 Internal clock Stop bit length select bit 0 One stop bit Odd even parity select bit Valid when bit 6 1 0 Odd parity Parity enable bit 1 Parity enabled
485. transmit data A b15 b8 b7 b0 b7 UARTO transmit buffer register Address 03A316 03A216 UOTB Setting transmission data S EELELELEELLLELLLELLLLLLELLLELLELLLLLLLETELLLLELELELTELLLELI a Start transmission a s Checking the status of UARTO transmit buffer register b7 b0 UARTO transmit receive control register 1 Address 03A516 U0C1 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled Xe Writing next transmit data b15 b8 b7 b0 b7 AAAA AAAI UARTO transmit buffer register Address 03A316 03A216 UOTB Setting transmission data C of nunnnnunnnnnnnnnnunnnnnanannnannananan n Transmission is complete Figure 2 5 7 Set up procedure of transmission in clock synchronous serial I O mode 2 stENESAS 257 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 3 Operation of the Serial I O transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected In transmitting data in clock synchronous serial I O mode choose functions from those listed in Table 2 5 2 Operations of the circled items are described below Figure 2 5 8 shows the operation timing and Figures 2 5 9 and 2 5 10 show the
486. ts value and to stop Note e Make the pulse width of the signal input to the TAOIN pin not less than two cycles of the count source n reload register content 1 Start count 3 Underflow 2 Stop count 2 7 4 Stop count Counter content hex Start count again Cleared to 0 by Time Set to 1 by software i i i software Set to 1 by software Count start flag TAOIN pin H cr ws input signal jB Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 1 request bit g Figure 2 2 8 Operation timing of timer mode gate function selected 182 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A a Selecting timer mode and functions Selection of timer mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Gate function select bit b4 b3 1 1 Timer counts only when TAOIN pin is held H Note 0 Must always be 0 in timer mode om source select bit Count Count source period 00 f1 SOUICE f XIN 10MHz f XcIN 32 768kHz 01 fs 100ns 10 f32 800ns 11 fc32 i 3 2us 976 56us Note Set the corresponding port direction register to 0 input mode Setting divide ratio b8 b0 b7 Timer AO register Address 038716 0386
487. ubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Used for timer mode Timer XO interrupt request bit Timer X1 interrupt request bit Used for event counter mode Figure 3 1 2 Connection diagram of long period timers tENESAS 339 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Setting timer X0 Selecting timer mode and functions roTop op oo of eyo TORE mode register Address 039716 Selection of timer mode Pulse output function select bit 0 Pulse is not output TXOINOUT pin is a normal port pin Gate function select bit b4 b3 0 0 Gate function not available TXOINOUT pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period ae FA SOUICE Xin 10MHZ f XcIN 32 768kKHz 100ns 800ns 3 2us 976 56us Setting divide ratio b15 b8 b7 bO b7 bO eee Setting timer X1 Selecting event counter mode and each function uli 0 Timer X1 mode register Address 039816 fofofofofofofols txime Selection of event counter mode Pulse output function select bit 0 Pulse is not output TX1INOUT pin is a normal port pin Count polarity select bit 0 Must always be 0 in event counter mode 0 Must always be 0 in event counter mode
488. uction to write to this register Count start flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TABSR 038016 000X00002 r 1 Starts counting Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate TBOS Timer BO count start flag 0 Stops counting TB1S Timer B1 count start flag ieStarts counting CDCS Clock devided count start flag Figure 2 2 3 Timer A related registers 2 RENESAS 177 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A UP AQOWT Hag INOLE b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset UDF 038416 XXX0XXX02 Timer AO up down flag 0 Down count 1 Up count This specification becomes valid when the up down flag content is selected for up down switching cause Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Timer AO two phase 0 two phase pulse signal pulse signal processing processing disabled select bit 1 two phase pulse signal processing enabled When not using the two phase pulse signal processing function set the select bit to 0 Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Note Use MOV instruction to write to this reqister ne sh rt fl One shot start flag Symbol Addre
489. uffer register UOTB 03A416 UARTO transmit receive control register 0 U0CO 03A516 UARTO transmit receive control register 1 U0C1 03A616 03A716 034816 UART1 transmit receive mode register U1MR 03A916 UART1 bit rate generator U1BRG 03AA16 l O3ABig UART1 transmit buffer register U1TB 03AC16 UART1 transmit receive control register 0 U1C0 03AD16 UART1 transmit receive control register 1 U1C1 03AE16 O3AF e UART1 receive buffer register U1 RB 03B016 UART transmit receive control register 2 UCON 03B116 UARTO receive buffer register UORB Figure 2 5 1 Memory map of serial I O related registers 250 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O UARTIi transmit buffer register Note bs Symbol Address When reset b0 b7 UOTB 03A316 03A216 Indeterminate U1TB 03AB16 03AA16 Indeterminate Transmit data Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note Use MOV instruction to write to this register UARTi receive buffer register b15 b8 Symbol Address When reset b7 bo b7 UORB 03A716 03A616 Indeterminate U1RB 03AF16 03AE168 Indeterminate 5 Function During clock Function Bit name synchronous serial I O During UART mode mode Receive data Recei
490. ult is indeterminate Note 2 AN50 to AN54 can be used in the same way as for ANo to AN4 Note 3 If port P5 group is selected the contents of A D registers 5 to 7 are indeterminate If port P5 group is selected do not select 8 pins sweep mode Figure 1 83 A D converter related registers 1 RENESAS 91 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 2 Note b7 b6 b5 b4 b3 b2 bl bO Symbol Address When reset OAN of 0 of ADCON2 03D416 XXXX00002 R iar foo 1 With sample and hold masao foo Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D register i Symbol Address When reset ADi i 0 to 7 03C016 to 03CF16 Indeterminate bo Eight low order bits of A D conversion result e During 10 bit mode Two high order bits of A D conversion result e During 8 bit mode The value if read turns out to be indeterminate ee ee eee eee eens Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Figure 1 84 A D converter related registers 2 92 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICRO
491. unt H morge AE A LA CL OEFEN TAL EP Input pulse TAON FFFF16 x 2 E Q Ss i g E 3 Q oO 000016 Set to 1 by software a os Time 2 Underflow 3 Overflow Count start flag l g Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 4 request bit o Figure 2 2 18 Operation timing of 2 phase pulse signal process in event counter mode multiply by 4 mode selected 192 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting event counter mode and functions Selection of event counter mode 0 Must always be 0 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing 1 Must always be 1 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing Count operation type select bit 1 Free run type Two phase pulse signal processing operation select bit 1 Multiply by 4 processing operation Note Set the corresponding port directio
492. unt Count source period y Be ft SOUICE Xin 10MHZz f Xcin 32 768kHz 01 f8 i 100ns 10 f32 i 800ns 11 fcs2 3 24s 976 56us Note Set the corresponding port direction register to 1 output mode TXiINOUT pin is not selected as count source when pulse output function selected X Clearing timer Xi interrupt request bit Refer to Precaution for Timer X one shot timer mode b7 b0 0 Timer Xi interrupt control register Address 005516 TXiIC i 0 to 2 Interrupt request bit Setting one shot timer s time b15 b8 b7 0 b7 Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX1 lo Can be set to 000116 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XcIN by 32 b7 b0 Clock prescaler reset flag Address 038116 LADD CPSRE Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Z Setting count start flag b7 bo x T Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Setting one shot start flag b7 b0 XXX CCT 1 One shot start flag Address 038216 ONSF ___ Timer X0 one shot
493. upt enable flag to 1 Enable interrupt Figure 4 7 1 Switching condition of INT interrupt request 382 2tENESAS Renesas Technology Corp Interrupt Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 4 Rewrite the interrupt control register e To rewrite the interrupt control register do so at a point that does not generate the interrupt request for that register If there is possibility of the interrupt request occur rewrite the interrupt control register after the interrupt is disabled The program examples are described as follow Example 1 INT_SWITCH1 FCLR AND B 00h 0055h NOP NOP FSET Example 2 INT_SWITCH2 FCLR AND B 00h 0055h MOV W MEM RO FSET Example 3 INT_SWITCHS PUSHC FLG FCLR AND B 00h 0055h POPC FLG Disable interrupts Clear TAOIC int priority level and int request bit Four NOP instructions are required when using HOLD function Enable interrupts Disable interrupts Clear TAOIC int priority level and int request bit Dummy read Enable interrupts Push Flag register onto stack Disable interrupts Clear TAOIC int priority level and int request bit Enable interrupts The reason why two NOP instructions four when using the HOLD function or dummy read are inserted before FSET in Examples 1 and 2 is to prevent the interrupt enable flag from being set before the interru
494. urce COU H Measurement pulse o 1 i i be Transfer Ka Transfer measured value f indeterminate Bn yy i pi Reload register counter value transfer timing g Note 1 A Note 1 A Note Va Timing at which counter a reaches 000016 Count start flag Timer Bi interrupt request bit T Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi overflow flag T Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 3 10 Operation timing of pulse width measurement mode 216 RENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting pulse period pulse width measurement mode and functions bO Timer Bi mode register i 0 1 Address 039B16 039C16 PTLD ALLA TBiMR i 0 1 Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 1 0 Pulse width measurement Interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Timer Bi overflow flag 0 Timer did not overflow 1 Timer has overflowed au Sones evel Count Count source period O0 f1 i source f XIN 10MHz_ f XcIN 32 768kHz 01 fe 100ns 10 f32 800ns 1 fc32 7 3 2us 976 56us Note Set the corresponding port direction register which sets
495. urement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to start counting the count source 2 If an effective edge of a pulse to be measured is input the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is transferred to the reload register The timer Bi interrupt request does not generate 3 If an effective edge of a pulse to be measured is input again the value of the counter is transferred to the reload register and the timer Bi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and measurement is started again Note e The timer Bi interrupt request bit goes to 1 when an effective edge of a pulse to be measured is input or timer Bi is overflows The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Bi overflow flag goes to 1 immediately after a count is performed e The timer Bi overflow flag goes to 0 if timer Bi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software 1 Start count 3 Start measurement again 2 Start measurement Count so
496. ut is L level for the entire period and an interrupt request is generated for every PWM output cycle Also when FF 16 is set for the significant 8 bits of the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fa f32 fc32 n Timer value Conditions Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 External trigger falling sage of TAOIN pin input signal is selected 1 fi X m 1 X 2 1 ada Count source Note 1 Count start flag 1 Start count n 2 Output level H to L 3 One period is TAOIN pin input 1 Li i complete gt 1 81 X m prescaler Note 2 7 i gt eae i 1 fX m 1 Xn r f Cleared to 0 when interrupt request i is accepted or cleared by software Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF 16 n 0016 to FF 16 PWM pulse output from TAOOUT pin Timer AO interrupt request bit 1 0 H L Underflow signal of 8 bit H jid H L je 0 Figure 2 2 26 Operation timing of pulse width modulation mode with 8 bit PWM mode selected 200 tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A
497. ut the count at that moment Read it in 16 bit units The data either in one shot timer mode or in pulse width modulation mode is indeterminate 5 Writing to the timer To write to the timer register when a count is in progress the value is written only to the reload register When writing to the timer register when a count is stopped the value is written both to the reload register and to the counter Write a value in 16 bit units 6 Relation between the input output to from the timer and the direction register With the output function of the timer set the direction register of the relevant port to input To input an external signal to the timer set the direction register of the relevant port to input 7 Pins related to timer A a TAOIN Input pins to timer A b TAQOUT Output pins from timer A They become input pins to timer A when event counter mode is active RENESAS 175 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 8 Registers related to timer A Figure 2 2 1 shows the memory map of timer A related registers Figures 2 2 2 through 2 2 5 show timer A related registers 005516 Timer AO interrupt control register TAOIC EN X 038016 Count start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 Trigger select register TRGSR 038416 Up down flag UDF 038616 Timer AO TAO
498. utput 1 TxDi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note Set the corresponding port direction register to 1 output mode Va Setting UART transmit receive control register 2 b7 D UART transmit receive control register 2 Pdr ol To UCON Address 03B016 UARTO transmit interrupt cause select bit 0 Transmit buffer empty TI 1 Must be 0 in clock synchronous I O mode Must be 0 in clock synchronous I O mode Valid when bit 5 1 CLK CLKS select bit 1 0 Normal mode Continued to the next page Figure 2 5 6 Set up procedure of transmission in clock synchronous serial I O mode 1 256 stENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Continued from the previous page Setting UARTO bit rate generator b7 b0 UARTO bit rate generator Address 03A116 UOBRG Can be set to 0016 to FF16 Note Note Write to UARTO bit rate generator when transmission reception is halted Transmission enabled b7 b0 KEKE IIDE UARTO transmit receive control register 1 Address 03A516 UOC1 Transmit enable bit 1 Transmission enabled C Writing
499. value before stop mode is retained e 8 fc32 is not included Do not set to 1 when using low speed or low power dissipation mode System clock control register 1 Note 1 b6 b5 b4 b3 b2 bi b0 Symbol CM1 Address 000716 When reset 2016 0 0 0 0 Bit symbol Bit name Function All clock stop control bit Note 4 0 Clock on 1 All clocks off stop mode CM10 Reserved bit Always set to 0 Reserved bit Always set to 0 Reserved bit Always set to 0 Reserved bit Always set to 0 XIN XOUT drive capacity select bit Note 2 0 LOW 1 HIGH CM15 b7 b6 0 0 No division mode 0 1 Division by 2 mode 1 0 Division by 4 mode 1 1 Division by 16 mode Main clock division select bit 1 Note 3 CM16 CM17 Note 1 Set bit 0 of the protect register address 000A16 to 1 before writing to this register Note 2 This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 3 Can be selected when bit 6 of the system clock control register 0 address 000616 is 0 If 1 division mode is fixed at 8 Note 4 If this bit is set to 1 XouT turns H and the built in feedback resistor is cut off XcIN and XcoutT turn high impedance state Figure 2 11 4 Power cont
500. value is 0 e Setting count start flag b7 bO Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 7 Set up procedure of timer mode stENESAS 181 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 3 Operation of Timer A timer mode gate function selected In timer mode choose functions from those listed in Table 2 2 2 Operations of the circled items are described below Figure 2 2 8 shows the operation timing and Figure 2 2 9 shows the set up procedure Table 2 2 2 Choosed functions Count source Internal count source fi fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAOIN pin is at L level Performs count only for the period in which the TAOIN pin is at H level Operation 1 When the count start flag is set to 1 and the TAOIN pin inputs at H level the counter performs a down count on the count source 2 When the TAOIN pin inputs at L level the counter holds its value and stops 3 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 4 Setting the count start flag to O causes the counter to hold i
501. ve data Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate OER Overrun error flag 0 No overrun error No overrun error Note 1 Overrun error found Overrun error found Framing error flag Invalid No framing error Note Framing error found Parity error flag Invalid No parity error Note Parity error found Error sum flag Invalid No error Note Error found Note Bits 15 through 12 are set to O when the receive enable bit is set to O Bit 15 is set to 0 when bits 14 to 12 all are set to O Bits 14 and 13 are also set to 0 when the lower byte of the UARTIi receive buffer register addresses 03A616 and 03AE16 is read out UARTIi bit rate generator Note 1 2 b7 bo Address When reset 03A116 Indeterminate 03A916 Indeterminate Values that can be set Assuming that set value n BRGi divides the 0016 to FFie x o count source by n 1 Note 1 Write a value to this register while transmit receive halts Note 2 Use MOV instruction to write to this register Figure 2 5 2 Serial I O related registers 1 RENESAS 251 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O UARTIi transmit receive mode register Address 03A016 03A816 When reset 0016 b7 b6 b5 b4 b3 b2 bi bO
502. vent counter mode One shot timer mode Pulse width modulation PWM mode TCKO Count source select bit Function varies with each operation mode Figure 1 38 Timer A related registers 1 stENESAS 49 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer AO register Note 1 b8 Address b0b7 038716 038616 Function Timer mode Counts an internal count source e Event counter mode Counts pulses from an external source or timer overflow One shot timer mode Counts a one shot width Pulse width modulation mode 16 bit PWM Functions as a 16 bit pulse with fede e Pulse width modulation mode 8 bit PWM Timer low order address functions as an 8 bit prescaler and high order address functions as an 8 bit When reset Indeterminate Values that can be set 000016 to FFFF16 000016 to FFFF16 000016 to FFFF16 Note 2 000016 to FFFE16 Note 2 0016 to FF16 Note 2 Both high order and low order addresses pulse width modulator Note 1 Read and write data in 16 bit units Note 2 Use MOV instruction to write to this register Count start flag b7 b6 b5 b4 b3 b2 bi b0 When reset 000X00002 Address 038016 Symbol TABSR Bit symbol Bit name Function TAOS Timer AO count start flag 0 Stops counting TXOS Timer X0 count start flag 1 Starts counting TX1S Timer X1 count start flag TX2S Timer X2
503. vent counter mode Pulse output function select bit 0 Pulse is not output Count polarity select bit 0 Counts external signal s falling edge Invalid in event counter mode Can be 0 or 1 0 Must always be 0 in event counter mode Count operation type select bit 1 Free run type Invalid in event counter mode Can be 0 or 1 Setting trigger select register br bo Trigger select register Address 038316 TRGSR Timer X0 event trigger select bit b3 b2 0 0 Input on TXOINOUT is selected Note Timer X1 event trigger select bit b5 b4 0 0 Input on TX1INOUT is selected Note Timer X1 event trigger select bit b7 b6 0 0 Input on TX2INOUT is selected Note Note Set the corresponding port direction register to 0 input mode a Setting divide ratio b15 b8 Be b0 b7 b0 Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 o Can be set to 000016 to FFFF16 k Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 13 Set up procedure of event counter mode free run type selected stENESAS 233 Renesas Technology Corp Mitsubishi microcomputers M30201 Group SING
504. vent counter mode 000016 to FFFF16 Counts external pulses input or a timer overflow Note1 Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 1 1 1 1 1 1 TAOS Timer AO count start flag 0 Stops counting TXOS Timer XO count start flag 1 Starts counting TX1S Timer X1 count start flag TX2S Timer X2 count start flag Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate TBOS Timer BO count start flag 0 Stops counting TB1IS Timer B1 count start flag plans counting CDCS Clock devided count start flag Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset CPSRF 038116 OXXXXXXX2 Bit symbol Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Clock prescaler reset flag 0 No effect P g 1 Prescaler is reset When read the value is O Figure 2 3 3 Timer B related registers 2 tENESAS Renesas Technology Corp 209 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 2 Operation of Timer B timer mode In timer mode choose functions from those listed in Table 2 3 1 Operations of the circled items are described below Figure 2 3 4 shows the operation timing and Figure 2 3 5 shows the set up procedur
505. wer Control 2 11 4 Precautions in Power Control 1 When returning from stop mode by hardware reset RESET pin must be set to L level until main clock oscillation is stabilized 2 When switching to either wait mode or stop mode instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every clock stop bit to 1 within the instruction queue are prefetched and then the program stops So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every clock stop bit to 1 3 Suggestions to reduce power consumption e Ports The processor retains the state of each programmable I O port even when it goes to wait mode or to stop mode A current flows in active I O ports A pass current flows in input ports that float When entering wait mode or stop mode set non used ports to input and stabilize the potential a A D converter A current always flows in the VREF pin When entering wait mode or stop mode set the Vref connection bit to 0 so that no current flows into the VREF pin b Stopping peripheral functions In wait mode stop non used wait peripheral functions using the peripheral function clock stop bit However peripheral function clock fc32 does not stop so that the pe ripherals using fc32 do not contribute to the power saving When the MCU running in low speed or low power dissipation mode do not enter WAIT mode
506. write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 TAOS Timer AO count start flag 0 Stops counting TXOS Timer XO count start flag 1 Starts counting TX1S Timer X1 count start flag TX2S Timer X2 count start flag Nothing is assigned In an attempt to write to this bit write O The value if read turns out to be indeterminate TBOS Timer BO count start flag 0 Stops counting TB1S Timer B1 count start flag L ystarts counting CDCS Clock devided count start flag Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset L XDKIXIKIXIKIX CPSRF 038116 0XXXXXXX2 Nothing is assigned In an attempt to write to these bits write 0 The value if read turns out to be indeterminate Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Figure 1 50 Timer B related registers 2 60 2tENESAS Renesas Technology Corp Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 1 Timer mode In this mode the timer counts an internally generated count source See Table 1 17 Figure 1 51 shows the timer Bi mode register in timer mode Table 1 17 Timer specifications in timer mode Count source f1 f8 f32 fC32 Count operation Counts down e When the timer underflows it reloads the reload register contents before continuing counting Div
507. y to be accepted What is described here does not apply to non maskable interrupts Enable or disable a maskable interrupt using the interrupt enable flag I flag interrupt priority level select bit and processor interrupt priority level IPL Whether an interrupt request is present or absent is indi cated by the interrupt request bit The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt Also the interrupt enable flag I flag and the IPL are located in the flag register FLG Figure 1 24 shows the interrupt control registers tENESAS Renesas Technology Corp 33 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt control register Note 2 Symbol Address When reset KUPIC 004Di6 XXXXX0002 ADIC 004E16 XXXXX0002 005116 005316 XXXXX0002 005216 005416 XXXXX0002 005516 XXXXX0002 005616 to 005816 XXXXX0002 005A16 005B16 XXXXX0002 ie oo b7 b6 b5 b4 b3 b2 bi b0 LI ooo Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested 1 Interrupt requested Nothing is assigned In an attempt to write to these bits write O The value if read turns out to be indeterminate Note 1 This bit can only be accessed for reset 0 but cannot be a

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