ISP1763A PCI evaluation board
Contents
1. B frequency 12MHz 19 2MHz 24MHz i 2 NEA FREQSEL2 0 0 1 5 6 7 8 9 10 1 0 1 0 32 13 14 15 16 HEADER2X8 LF 1 BUS interface NAND Multiplex NOR DACK ALE 0 0 1 CLE 0 1 0 HEADER2X8 LF HEADER2XS8 LF SRAM ISP1763A Figure 14 19 29 ISP1763A 2013 10 16 CD00257207 Copyright ST All rights reserved User manual Schematics ISP1 763A PCI evaluation board y life qugmented UM0865 52 R125 560R 0603 1 16W 1 LF C115 100NF 50V 0603 10 LF OUTI Pot2 wd V3 V3 5 05 Chip E jam g USB RECEPTACLE A oo c me N N en U8 E ox x U7 45V usb Chip 8 1 DNM PSWIN S Z USBULC6 2F3 7 21 RD3 0R VBUSI e VIN FIGA BOE M RI4 OR C116 5 4 YU PSW2_N OUTB ENB 100 50 0603 10 LF 2026 2 5 z s DNM V3V3 5V_usb_Chip a 19 amp USBULC62F3 R132 OR RI38 0R VBUSI R137 560R 0603 1 16W 1 LF M cis C119 DNM LED3 S LEDRED3MM LF FB 5 68 4 7uEB5V 100nF 100uF 16V BLM31A2608 2 Socket Chassis Chassis Chassis Chassis USB_AB MICRO DNM ma U10 m m USBULC6 2F3 m m fm USBULC6 2F3 LED2 LED RED2. a vcco L19 18001 4 TDO mM x TK 6 rk 5 NC Lak OERST CEO 19 NC NC CENE 1 Z S ac SS SQ 50 2 8 85 88 V3V3 m 92 94 195 96 97 98 199 00 01 202 203 04 05 206 207 208 GND EJ als en 8 A DNM R100 V3 V3 BS zsa 386 aR gt V2y5 R101 A R99 4 7K V3 OR 2 amp a n E 8 lt LD 15 0 gt V2V5 hswap during configuration HSWAP 0 user io pull up enable HSWAP 1 user io pull up disable PROG B When connect can be loaded WNhen disconnect can t be loaded 21 29 ISP1763A FPGA 2013 10 16 16 CD00257207 Rev 3 Copyright ST All rights reserved Figure Lv ISP1 763A PCI evaluation board User manual Schematics y life qdugmented UM0865 d Dd Dd Dd A A sav zsa NH99N orav ciav vidv gs iav sed sav sav Lva 199 0 _ cag PATO I SASA Zrd ANS AS AS t9X0V OIA lav anp 8s8 av sav EAE Lav WIS EAE wid ATAL GND EAE 91qv slav GND ozay ccav 9911 vcav GND 9cav zay otav Wd GND IND OIA AS AS 120254 OIA Iv GND tv ago GND clav EAE Slav Wd GND Ga DIS GND M ov sv 0
3. 103 a 103 ap A ane NETTE 7 5 IO1 L05P A12 vCCO3 7 XD V3V3 T 5 R103 Tor LOSN AI1 GND s AIS T 4 RI04 TOR DO GND 103 LI2N z 50 3 8105 MTOR 101 L06P 103 12 34 LGI I PRESE i os IO1 LO6N VREF 103 FAS 1 IP IO3 vccol IP T 101_L07P A1 O RHCLK IO3 LION LHCIK7 5 525 IO1_LO7N A9 RHCLK1 IO3 LIOP LHCLK6 z IO1 L08P A8 RHCLK2 103_LO9N LHCLK5 4 177 LO8N A7 RHCLK3 LO9P LHCLK4 7 ND NEM IP GND GND p 26 142 IO1 L09P AG RHCLK4 103 L08N LHCLK3 24 LA30 IO1 LO9N AS5 RHCIK5 L08P LHCLK2 IO1 L10P A4 RHCLK6 103_LO7N LHCLK1 101_L10N A3 RHCLK7 103_L07P LHCLKO T Vi peer IP VREF VCCO3 ae svi 1 1 2 IPVREF T gt IO1 LIIN A1 103 106 gt IO1 LI2P 103_LO6P IO1 LI2N A0 GND T GND 103_LOSN 5 IP 103_ ME VCCOI p lt 101_L13P VCONT Cui v LI3N 103 LMN 101 4 103 104 LIN GND 0 103 LON oem 103 103P 7 VV IO1 LI5P HDC VCCAUX zy 4 V2vs IO1 LISN IDCO on 2 140 LI6P LDCI 50 9 99 5 103 LIBN VREF E IO1 LI6N IDC2 8 3 8 3 8 3 8 a 103 102P TDI a2ea2Z AZAZ 2 2 2 22 2 10 a ais ggss 552 SG m2 aD 2S m 2 220 zl 38 lis 220 435 She ROGE HEADERI X2 LF Pee 828 888886888982688288458586885288485886 LED ORANGE 0603 LF 045 V2V5 DO
4. 5 ee 55 HOHd O SV sv LW GND i dOLS StV epo ogx a Dd 0ASA R EAEA TED OL CCS 63 USERi D ACKO LLOC Ki Xe USERo DREQo LLOC Ko eg 18 MODED S Lato TEST 261 LAN UNT 52 lan MDREQ DMPAF EOT sie a T xh LA13 BB BREQi 5 B LAIS ne HANO LA16 74 LA16 VDD 147 V3V3 LAI 75 E 146LSERR BRR gt amp LA18 76 LA18 TS ADS 145 ADS ADS LAD 11 LA19 BG 144LHOLDA LHOLDA LA21 79 LA20 BR LHOLD 142 LCLK LHOLD LA2 80 141V3V3 Cake 15 81 453 vss 140GND 8 LA24 82 LA24 DP3 139 R14 1K 84 MB DP2 C 7 LA27 85 ee 136 17 1K LA28 86 135 LREADY LAB 31 A29 saps ie Guss GND 88 VSS VDD 133 V3V3 3 lt lt 4 E E 355555 jas H El IL ESIEBBEBHSEBEREEE s m M SEE I I Ei lt iu D z 5 5 8 8 5170 R27 lt Wk 5 1 52 180 RM g mm Ro 15 10K 5 8 1 R23 LHOLDA IwR R3 15 10K E n E m gt 5 2 g od a SELLE 5 4 3 E e I ui E eg E to 5 iar ma sisisistsisiststs sLsisizi 1 oi E S 5 BE 9404 W
5. C71 ISP1 763A PCI evaluation Yy ife augmented b Oa rd UM0665 User manual Abstract This document describes board level operations of the ISP1763A PCI evaluation board Two version of the board are available one for the TFBGA package and the other for the VFQFPN package The ISP1763A PCI evaluation board allows engineers and software developers to create USB host device and OTG features for customer applications Keywords isp1 63a usb universal serial bus host controller otg on the go CD00257207 Rev3 2013 10 16 ISP1763A Copyright ST All rights reserved lt 7 ISP1 763A PCI evaluation board User manual Legal information y life qdugmented UM0865 Legal information Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document
6. 129 115 10uF 25V LEDS LED GREEN 0603 SML312ECT LD1086D2T25TR LED RED 0603 LF C133 10uF25V Super Pure Green 5 22UF 25V 20 TAN D LF VSVO V2V5 m R154 C131 R147 33R 0603 1 16W 1 LF 10uF 25V LED6 3R 0603 1 10W 1 LF 240R 0603 1 8W 1 _LF R152 51R 0603 1 16W 1 LF LED YELLOW 0603_LF Figure 18 Power 23 29 ISP1763A 2013 10 16 CD00257207 Rev 3 Copyright ST All rights reserved Lv ISP1 763A PCI evaluation board y life qdugmented 2K 0603 1 10W 1 ALE 1 OR 93 DREQ R156 R1 3K 0603 1 16W 1 LF Figure 19 CD00257207 0 0865 1 4 3V3 3 po Bur DL T DI BUF pi D3 BUF DA 13 ps is MPUr D5 BUF 17 9 D9 BUF pg 21 ee D8 BUF D9 23 pe BUF D10 25 Dil 27 D12 29 DI3 31 D14 33 DI5 35 ADDRO 37 ADDR 39 ADDR2 41 ADDR3 43 45 47 49 51 ADDR4 753 ADDR5 55 ADDR6 57 ADDR7 59 61 63 65 67 69 71 SB 75 77 S79 81 83 S85 87 89 DNM 291 95 97 SFM 150 02 S D A User manual BSQUARE PXA320 SRAM INTERFACE GND 4 G2 G2 G2 G2 G2 IN i i O oo JO O oo No O 00 IG FLASH HDR RDY GND GND VCC IO Chip FLASH HDR nCS2 ies Ris FLASH HDR_nCS3 63MB NM S 44 R160 OR nLLA DNM TP26 DNM DNM R161 OR ALE 1 R162 OR ALE DNM NOR Flash R163 OR 66 R164 OR 68 DNM 70 72 WE 74 76
7. All rights reserved Lv ISP1763A PCI evaluation board User manual Physical description y life augmented UM0865 Table 6 ISP1763A chip package information Product Package _ Package description TFBGA64 64 balls body 4 x 4 x 0 8 mm VFQFPN64 64 terminals body 9 x 9 x 1 0 mm For the schematic design there is no difference except the chip footprint For the PCB layout TFBGA is six layered design whereas VFQFPN is only four layered design All the components are same on both the boards except the ISP1763A IC package 3 4 2 PLX9054 and 93LC56C EEPROM PLX9054 is a PCI to local bus accelerator The ISP1763A is always a PCI target during initialization as well as during the data transfer phase to or from the ISP1763A memory n gu Tram Y r GJ TT NS JOD CO QC ed BS bet entm NN 2171 517 amp OW Figure 10 9054 When powering on or asserting the PCI RESET signal PLX9054 attempts to read the serial EEPROM to check its presence The 93LC56C EEPROM is required for the correct initialization of PLX9054 The serial EEPROM contains information required to initialize PLX9054 registers For details refer to Chapter 11 of PLX PCI 9054 Data Sheet The initial programming of 93C56 must be done in a serial EEPROM programmer Displaying and adjusting of certain parameters can be done using
8. C107 C99 C105 C123 C116 C113 C109 100 pF C32 C0603 Capacitor SMD 0603 100 pF 50 V 5 NPO 100 Q R103 R102 R105 R104 C0603 Resistor SMD 0603 1 10W 1 100 lead free 100 UF C114 ELE SMD D Capacitor Ele SMD D 100 yF 16 V 20 lead free 120 Q R108 C0603 Resistor SMD 0603 1 10W 1 120 lead free 200 Q R144 C0603 Resistor SMD 0603 1 16W 1 200 Q lead free 220 UF C124 ELE SMD E Capacitor Ele SMD 220 uF 10 V FK series low ESR 20 lead free 240 Q R151 C0603 Resistor SMD 0603 1 8W 1 240 Q lead free Capacitor SMD 0603 100 nF 50 V 10 lead free O gt Co CD00257207 Rev3 2013 10 16 ISP1763A 26 29 Copyright ST All rights reserved ISP1 763A PCI evaluation board User manual List of materials 4 y life augmented UM0865 5100 R13 C0603 Resistor SMD 0603 1 10W 1 510 O lead free 560 Q R125 R137 C0603 Resistor SMD 0603 1 16W 1 560 O lead free 767130 1 J1 767130 1 Connector 38Pos 0 025CL 767130 1 B3S 1000 SW 1 B3S 1000 Switch tact SMD 6 mm x 6 mm white BLM31A260S FB1 FB2 R1206 Murata ferrite bead 1206 case 0 05 DC resistance CDRH104RNP L1 CDRH104RNP Inductor SMD 7 uH 4 5 A 7RONC DR1040 7RO R 510 12 000MABJ X2 CS10 Crystal 12 MHz 6 x 3 5 mm CS10 12 000MABJ UT DC power socket DC power socket Socket DC jack 2 5 mm PCB 2 5 mm DIA DPOAPR Power disk drive RA 4 way FD2X20 LF J2 FD2X20 Connector PCB Mt 0 100 2 x 20 way FDS8958A SOIC 8 4x5mm Transistor FDS89
9. USB ports Figure 15 20 29 ISP1763A 2013 10 16 CD00257207 Rev 3 Copyright ST All rights reserved Schematics User manual UM0865 ISP1 763A PCI evaluation board y life qugmented 8 46 FD2X20 IF Female IDE connector pin orientation of the header as seen from the top view top layer 2 ttt l ll l l 100NF 50V 0603 Y5V LF V3V3 5 018044 1 1 3 C93 OSC 100NF 50V 2 204 0603 5 50MHz 44421 15PF 50V 0608 5 L 05 For Debug For Debug For Debug Dou 2 PIN MALE HEADER FOR CRO PROBE EE 2 T EE V2 V5 3 VIO H M x HEADER1X2 LF m 2 slo P 2 2 955528291 Z5 6 oH HEADERI 2 LF XC3S500E 5 9 gag YETTEFEPECEEEEEPELEEEEEEREE S n o GND gus 555526 did 48244051655555151442152 GND 22 E li nn 101 6 25 55444 SSSS OG OQ ZR SSSOSSSSBer ERAS L3 gt B a 5 IO1 LOIN AI5 aS ag l 8 a 3 2 Q Au 103 LI6N 101 2 14 5 da QS 2452 2A x Ry 2 8 g 103 116 101_LO2N A13 ley 88 B amp B IO3 LISN ue P 8 88 AJ 103 Lisp 2 5 ta VCCAUX SSE ss 838 8g vecos V vav3 101_L03P g IONREF 2v5 101_L03N VREF a vccol IO1
10. 1 TP11 TP12 TP13 TP18 Test point TP10 TP7 TP6 TP9 TP4 TP1 TP2 TP3 TP8 TP5 TFM 135 32 S D A DC1 TFM 135 32 S D A Samtec connector SMT vertical plug 35 x 2 TFM 135 32 S D A USB con type A 52 USB type 4 way 87520 receptacle 0010B USBULC6 2F3 U7 U9 U10 U11 USBULC6 2F3 ESD protection diode USB AB MICRO 53 USB micro type Micro USB type SMD ZX62 AB 5P XC3S500E U3 PQ208 IC Spartan XC3S500E 4PQG208C PQFP XCF04S U5 TSSOP20 4 4 x 6 5 IC programmable mm XCF04SVOG20C 20 TSSOP u93LC56C U1 DIP8 93LC56C I P EEPROM DIP 8 lead free CD00257207 Rev3 2013 10 16 ISP1763A 28 29 Copyright ST All rights reserved Lv ISP1763A PCI evaluation board y life qdugmented UMOS865 Glossary EEPROM Electrically Erasable Programmable Read Only Memory FPGA Field Programmable Gate Array NAND Not AND NOR Nor OR OS Operating System OTG On The Go PCI Peripheral Component Interconnect PIO Parallel Input Output RAM Random Access Memory SRAM Static Random Access Memory USB Universal Serial Bus CD00257207 Rev3 2013 10 16 Copyright ST All rights reserved ISP1763A Glossary 29 29
11. 8 3 Physical description 9 3 1 Board layout 3 2 Connectors 9 3 2 1 J1 PLX signals probe connector 10 3 2 2 2 ISP1763A bus interface 10 3 2 3 J3 J4 J5 and J6 bus test headers 11 3 2 4 USB ports 11 3 2 5 JP1 Xilinx 3 state input 11 3 2 6 JP2 Xilinx PROG input 11 3 2 7 JP3 Xilinx JTAG connector 11 3 2 8 JP4 GND connector 12 3 2 9 JP5 GND connector 12 3 2 10 JP6 5 V power select 12 3 2 11 JP7 Vccuo select 12 3 2 12 PS1 PC power connector 12 3 2 13 PS2 DC power socket 12 3 2 14 CON 1 PCI connector 12 3 2 15 CN1 PXA320 platform connector 12 3 2 16 DC1 DM357platform connector 13 3 2 17 Conf1 butterfly configuration 13 CD00257207 Rev3 20133026 I SP73A 8Q9 Copyright ST All rights reserved lt 7 ISP1 763A PCI evaluation board User manual y life qdugmented UMO865 3 3 LEDs 3 4 Board components 3 4 1 ISP1763A chip 3 4 2 PLX9054 and 93LC56C EEPROM 3 4 3 Xilinx XC3S500E 4 Schematics 5 List of materials Glossary CD00257207 Rev3 2013 10 16 Copyright ST All rights reserved ISP1763A Contents 14 15 15 16 17 18 25 29 4 29 Lv ISP1 763A PCI evaluation board User manual About this document y life qdugmented UMOS65 About this document 1 1 Purpose This document provides description on how to use the evaluation module to develop software for customers 1 2 Revision information Table 1 Revision history De Re comes o 2010 04 05 2 Updated the last paragraph of Secti
12. A 7 0 signals 3 2 4 USB ports The ISP1763A has two ports e Port 1 can be configured as either the host controller or the peripheral controller Has a micro AB USB connector on board e Port 2 is configured as the host controller Has a standard A USB host connector on board 3 2 5 JP1 Xilinx 3 state input This is the 3 state input to Xilinx Connect pin 1 pin 2 The Xilinx pins connected to the ISP1763A not 3 stated Connect pin pin 2 The Xilinx pins connected to the ISP1763A are 3 stated 3 2 6 JP2 Xilinx PROG input This is the Xilinx PROG input When this jumper is connected the FPGA code will be loaded to Xilinx from U5 3 2 7 JP3 Xilinx JTAG connector Figure 6 JTAG connector Through the JTAG interface download program into Xilinx 35500 Use the Xilinx USB blaster to connect the JTAG interface on board LED1 turns on when FPGA successfully completes configuration CD00257207 Rev3 2013 10 16 ISP1763A 11 29 Copyright ST All rights reserved y life augmented 3 2 9 3 2 10 3 2 11 3 2 12 3 2 13 3 2 14 3 2 15 000257207 ISP1 763A PCI evaluation board User manual Physical description UM0865 JP4 GND connector The GND connector is to connect the oscilloscope or logic analyzer probe 5 GND connector The GND connector is to connect the oscilloscope or logic analyzer probe JP6 5 V power select This is the 5 V power sup
13. C6 C16 C18 10 Q R147 C0603 Resistor SMD 0603 1 16W 1 10 O lead free CD00257207 Rev3 2013 10 16 ISP1763A 25 29 C0603 Capacitor SMD 0603 10 nF 50 V 10 X7R Copyright ST All rights reserved ISP1 763A PCI evaluation board User manual List of materials 4 y life augmented UM0865 10 uF C128 C130 C120 C127 C129 C134 ELE SMD B Capacitor Ele SMD B C132 C131 10uF 25 V 20 lead free 12 R115 R116 C0603 Resistor SMD 0603 1 16W 1 12 kQ lead free 15 pF C94 C0603 Capacitor SMD 0603 15 pF 50 V 5 lead free 18 pF C110 C111 C0603 Capacitor SMD 0603 18 pF 50 V 5 R86 R87 C0603 Resistor SMD 0603 1 16W 1 22 lead free 22 UF C133 TAN SMD D Capacitor tan SMD D 22 uF 25 V 20 lead free 33 kO R141 C0603 Resistor SMD 0603 1 16W 1 33 kQ lead free R154 C0603 Resistor SMD 0603 1 16W 1 33 lead free 51 Q R152 C0603 Resistor SMD 0603 1 16W 1 51 O lead free R100 C0603 Resistor SMD 0603 1 16W 1 68 0 100 kQ R136 C0603 Resistor SMD 0603 1 10W 1 100 lead free 100 nF C61 C23 C51 C21 C15 C56 C66 C49 C0603 Capacitor SMD 0603 C59 C76 C58 C71 C68 C63 C46 C19 100 nF 50 V 80 20 lead C34 C44 C36 C64 C41 C39 C11 C73 free C69 C74 C13 C78 C79 C33 C38 C5 C7 C48 C53 C9 C43 C17 C54 C25 C31 C29 C3 C1 C27 C95 C81 C87 NO NO Q2 Qo O C88 C83 C85 C86 C92 C84 C93 C89 C90 C91 100 nF C126 C125 C121 C122 C115 C118 C0603 C101 C103
14. VCC IO Chip GND VCC 3V3 Chip R115 12 1 10 5 0603 10 A cal S an Ww wal U6 ISP1763A VFQFPN VCC IO Chip 3V3 i lt E 5 VCC 3V3 Chip e E 5 35 104 56 gt lt ES n for 3 S 105 S 2 3 e S e e gt 5 S E S 5 GND gt uv z 121812158 122 J 2 A 2 E Z E E Decoupling capacitor VCC IO Chi OUD 10K 0603 1 16W 196 LF R112 R117 10K 10K 0603 1 16W 1 LF RESET R118 TP3 10K 10K 0603 1 16W 196 LF R122 10K 0603 1 16W 196 0 Ea foal E oen 8622 5658 5555455 lt ae lt 5 5 lt gm GND 1 m 5 2 AGND E S VCC IO Chip 21 5 ADO z ADI 5 6 7 8 Zi E a2 aZ AR e min Oo Ne 1 lp C ira Donantne lt lt lt gt 0 5464 gt 55442 lt 5 109 100nF 10 12 000MABJ UT 18PF 50V 0603 5 123 OR 42 FREQSEL2 110 4 FREQSEL1 18PF 50V 0603 5 LF 40 RESE 39 38 ALE 37 DACKE 36 DREQ T 34___ADDR7 33 ADDR6 DNM VCC IO _Chip C113 4 70F 10V 100NF 50V 0603 10 LF PLACE SUFFICIENT SPACE BETWEEN THE HEADERS FOR LA PROBE CONNECTION DACK 15 16 Ro 13 14 j 1 CLE 9140 WE 5 6 RD 4 CSH A
15. the PLXmon utility CD00257207 Rev3 2013 10 16 ISP1763A 16 29 Copyright ST All rights reserved C77 ISP1763A PCI evaluation board User manual Physical description y life qaugmented UM0865 NY 418 M d jg oq 1 Figure 11 EEPROM 93 56 3 4 3 Xilinx XC3S500E FPGA ensures adaptation between the ISP1763A generic bus interface and the PLX9054 local bus interface The FPGA programming can be downloaded through the JTAG interface UU WW OS ION IO OF Qai LO TA ILL ID a 5 R R 4 i 4 pesti Sih 3253531735 753253334 i _ A _ a _ I I _ ES a Eg _ i sich AA A ITALIA Figure 12 Xilinx XC3S500E For detail description of the FPGA programming refer to ISP1763A PCI evaluation board FPGA design UM0887 CD00257207 Rev3 2013 10 16 ISP1763A 17 29 Copyright ST All rights reserved C77 ISP1 763A PCI evaluation board User manual Schematics y life qdugmented UM0865 4 Schematics ISP1763A PCI EVALUATION BOARD ISP1763A USB PORTS FPGA PCI POWER CONNECTORS Figure 13 Main CD00257207 Rev3 2013 10 16 ISP1763A 18 29 Copyright ST All rights reserved User manual Schematics ISP1 763A PCI evaluation board y life qugmented UM0865
16. 58A NP SO 8 Header1 x 2 LF JP2 JP4 JP5 Header1 x 2 Header pin 0 100 1 x 2 way gold lead free Header1 x 3 LF JP1 JP6 JP7 Header1 x Header pin 0 100 1 x 3 way gold lead free Header1 x 6 LF JP3 Header1 x 6 Header pin 0 100 1 x 6 way gold lead free Header2 x 8 LF J3 J4 J5 J6 Header2 x 8 Header pin 0 100 2 x 8 way gold lead free ISP1763 VFQFPN VFQFPN 64 LD1086D2T18TR U16 D2PAK IC reg LDO POS 1 8V 1 5A D2PAK LD1086D2T25TR U15 D2PAK IC reg LDO POS 2 5V 1 5A D2PAK LD1086D2T33TR U17 D2PAK IC reg LDO positive 3 3 V D2PAK LD1117S12TR SOT 223 IC reg LDO POS 800MA 1 2 V SOT223 LED blue 0603 LF LED4 LEDO0603 LED blue 0603 LED green 0603 LEDO0603 Chip LED green SMD 0603 SML312ECT package 0 8 x 1 6 x 0 8 mm LED orange LED1 LEDO603 LED orange 0603 0603 LF LED red 3MM_LF LED2 LED3 LED3mm LED 3 mm red diffused LED red 0603 LF LEDS LEDO0603 LED red 0603 LED yellow LED6 LED0603 LED yellow 0603 0603 LF CD00257207 Rev3 2013 10 16 ISP1763A 27 29 Copyright ST All rights reserved Log ISP1763A PCI evaluation board User manual List of materials y life qdugmented UM0865 F QFP176 P 5N SFM 150 02 S D A CN1 SFM 150 02 S D A Connector SMT 0 5 2x50 SFM 150 02 S D A SN74LVT244BPW TSSOP20 4 4x6 5 IC 74LVT244BPW 20 TSSOP mm U12 U8 U2 51 1 SMB PCB VERT SMB SMB jack 50 O PCB Mt ST 5 018044 X 5 018044 Oscillator 50 000 MHz HCMOS 3 3 V 1 2 size Test point 1 8 TPREQ 1 TPGNT
17. 78 RD n 80 RO FLASH HDR nRQ FLASH HDR RESET R165 RESET GPIO OUT5 Bo DNM GPIO IN5 SE DC SCL on Ru 92 R166 OR RESET nRESET_OUT R167 ww OR RESET CONN 0 50 SQ Shrouded Header SMT 100pin 0 465 BTB DAVINCI DM357 NAND INTERFACE 1 I lt lt 2 5 zs x11 11 lt 13 5613 15 E a 21 ALE 5 25 27 2 27 lt 2 29 WE 3 TEE 15 39 7 D13 4 E Dll 43 45 D9 41 45 D7 49 47 D5 s e s a D3 ss ee DI s eee 39 2 RESET R168 _ OR 61 61 63 9 63 67 25 7 82 69 gt 4 x a s 6 Nam 7 1M x 14 46 16 182 lt 18 49 20 755 2 24 CLE 28 32 34 RD 34 j34 RD _ 36 R 36 36 RQ __ 38 38 40 D14 20 4 D12 44 DIO 44 447746 RI 4s D8 E 50 D6 22 D4 54 54 54 56 D2 58 DO 58 28 60 62 642 lt 64 70 19 Tes TFM 135 32 S D A Samtec connector CONN SMT VERTICAL PLUG 35X2 TFM 135 32 S D A Connectors 2013 10 16 Copyright ST All rights reserved ISP1763A Schematics 24 29 ISP1 763A PCI evaluation board User manual List of materials 4 y life augmented UM0865 List of materials D List of materials 00 R80 R81 R83 R82 R77 R76 R79 R78 R93 R92 R95 R94 R85 R84 R91 R90 R75 R64 R63 R66 R65 R39 R38 R62 R61 R72 R71
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19. PCI slot 32 bit 33 MHz running with Linux Red Hat kernel can be used The type of Linux Red Hat installation determines minimum system requirements The minimum recommended system configuration is a Pentium class processor 1 GHz with 128 MB RAM 2 2 2 Working with Windows CE OS An x86 based computer that has an available PCI slot 32 bit 33 MHz running Windows CE ver 5 0 or ver 6 0 OS can be used For STMicroelectronics set up example use Gigabyte GA 945GZM S2 motherboard on board Ethernet controller disabled with RealTek PCI Ethernet card PCI vendor ID is 10ECh and device ID is 8139h and a standard 1 44 MB floppy disk drive for system boot up Follow this hardware configuration as much as possible especially the motherboard and the Ethernet card CD00257207 Rev3 2013 10 16 ISP1763A 8 29 Copyright ST All rights reserved CTI ISP1 763A PCI evaluation board User manual Physical description y life augmented UM0865 3 Physical description This section describer the physical layout of the ISP1763A PCI evaluation board and its interface 3 1 Board layout The ISP1763A PCI evaluation board is 150 x 101 6 mm six layer or four layer VFQFPN printed circuit board that is powered by the PCI slot power Figure 4 shows the layout of the top view of the ISP1763A PCI evaluation board P Figure 4 ISP1763A PCI evaluation board top view 3 2 Connectors These connectors and jumpers are d
20. QSEL2 to LOW mount R111 and remove R113 e Toconnect FREQSEL2 to HIGH mount R113 and remove R111 e Toconnect FREQSEL1 to LOW mount R112 and remove R114 o connect FREQSEL1 to HIGH mount R114 and remove R112 The PIO mode selection is needed only for the actual platform validation On the x86 platform PIO mode selection is done using the Xilinx FPGA code The mounting of resistors R119 to R122 do not affect the mode selection done by Xilinx To configure in various modes refer to ISP1763A PCI evaluation board FPGA design 0 0887 When the ISP1763A is connected to customer platform mode selection is done using pins CLE and ALE ADV_N The corresponding resistors are mounted to connect CLE and ALE ADV_N to GND or connect CLE to LOW mount R120 and remove R122 Toconnect CLE to HIGH mount R122 and remove R120 e Toconnect ALE ADV_N to LOW mount R119 and remove R121 connect ALE ADV N to HIGH mount R121 and remove R119 CD00257207 Rev3 2013 10 16 ISP1 763A 13 29 Copyright ST All rights reserved C77 ISP1763A PCI evaluation board User manual Physical description y life qugmented UM0865 O ER 4 os IN gt oo lt wn L S i E 3 DES Figure 7 Butterfly configuration Table 4 Clock frequency and bus interface configuration Clock 12 MHz Reserved Comment fre
21. QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com CD00257207 Rev3 2013 10 16 ISP1763A Copyright ST All rights reserved 2 29 Lv ISP1 763A PCI evaluation board User manual Contents y life qdugmented UMOS65 Contents 1 About this document 5 1 1 Purpose 5 1 2 Revision information 5 1 3 Board history 5 1 4 Reference list 5 2 Introduction 6 2 1 Key features 6 2 2 Basic operation 8 2 2 1 Working with Linux OS 8 2 2 2 Working with Windows CE OS
22. R74 R73 R68 R67 R70 R69 R155 R148 R162 R158 R149 R0603 Resistor SMD 0603 1 16W 1 0 Q lead free R146 R153 R150 R167 R166 R160 R168 R164 R161 R165 R163 R145 R89 R88 R123 R109 R97 R96 R98 R99 R138 R126 R140 R139 R133 R124 R132 R134 R3 R2 R1 R45 R46 R24 1 R25 R37 R26 R9 R8 R14 R15 R16 R0603 Resistor SMD 0603 1 10W R36 R17 1 1 KQ lead free 2 R156 R0603 Resistor SMD 0603 1 10W 1 2 KQ lead free R157 R0603 Resistor SMD 0603 1 16W 1 3 kO lead free R147 R0603 Resistor SMD 0603 1 10W 1 3 Q lead free 4 7 KQ R107 R110 R106 R101 R0603 Resistor SMD 0603 1 10W 1 4K7 lead free 4 7 uF C108 C112 TAN SMD A Capacitor tan SMD A 4u7F 10 V 20 lead free 4 7 uF C96 C97 C0603 Capacitor SMD 0603 4u7F 10 V Y5V 80 20 lead free uF C117 ELE SMD B Capacitor Ele SMD B 4u7F 35 V 20 lead free 10 kO R59 R60 R57 R56 R58 R43 R118 C0603 Resistor SMD 0603 1 16W R44 R130 R49 R47 R117 R55 R111 1 10 lead free R42 R121 R113 R50 R114 R112 R52 R53 R54 R51 R119 R122 R120 R6 R7 R143 R5 R12 R135 R10 R11 R41 R40 R34 R35 R159 R48 R4 R22 R32 R27 R28 R29 R131 R33 R127 R30 R18 R19 R129 R128 R23 R31 R20 Q2 O R21 10 nF C80 C75 C70 C104 C42 C37 C65 C45 C40 C35 C60 C55 C50 C102 C82 C77 C72 C106 C98 100 52 C47 C57 C67 C62 C24 C12 C14 C26 C10 C30 C28 C8 C4 C2 C22 C20
23. SSSSSSSQQ282833838 55 elg ci g ac e SHEH e dE PEEB 4 15 g c 3E 28 50 duds o Se Ji sisi ds Suae SSRS Sgu Figure 17 PCI CD00257207 Rev3 2013 10 16 ISP1763A 22 29 Copyright ST All rights reserved User manual Schematics ISP1 763A PCI evaluation board y life qugmented UM0865 TP6 12 0 ext m Take care the orientation 100nF 50V U13 B of this connector 1 GND 1 C120 112 gt DLP 2 PS1 DNM V5V0 10 3 N TP7 x D RIS oR VL DH E LF 1 8 HE e FDS8958A Ed SHDN DL VCC IO Chi OUT GND PCIpower Chip VSVO0 PCI HOME CDRHI O4RNP 7RONC alala V3V3 VCC 3V3 Chip C124 R141 z 220uF 10V 33K 2 DL P C125 26 Vref 1 25v 6 R149 OR 1 1 HEADERIX3 LF SS 5 5 8 8 12V IN THE CENTRE 5 AND GND ON THE SHEILD 5 0 5 usb Chip Eu E 150 OR DC POWER SOCKET2 5MM DIA 2 2 52 DNM T T o 1 2 z YD LED4 LED BLUE 0603 LF TP9 TP10 R144 U14 200R 0603 1 16W 1 LF LD1117S12TR VSVOL A L vin Vout V1V2 Tab GND V3V3 PCI TP12 R148 U16 OR LD1086D2TI8TR 017 V5V0 3 w OUT V1V8 LD 108602133 TR TP11 p V5V0 N _OUT V3V3
24. croprocessors The PCI bridge board allows you to demonstrate the functionality of the ISP1763A on a standard PC with at least one PCI slot ISP1763A POWER b d JTAG XILINX 4 EEPROM PLX9054 Figure 1 Block diagram of the ISP1763A PCI evaluation board Key features include 12 MHz crystal clock input e One OTG port one host only port e Four types of bus interfaces e FPGA configuration e PCI connection e Multiple voltage power supply CD00257207 Rev3 2013 10 16 ISP1763A 6 29 Copyright ST All rights reserved C77 ISP1 763A PCI evaluation board User manual Introduction s life augmented UM0865 All local bus signals are easily accessible on test headers designed for direct connection of a standard Tektronix logic analyzer Figure 2 ISP1763A PCI evaluation board VFQFPN T ERICSSON TFBGA wile SP 1763 gt oE pecas Y Figure 3 ISP1763A PCI evaluation board TFBGA CD00257207 Rev3 2013 10 16 ISP1763A 7 29 Copyright ST rights reserved Lv ISP1 763A PCI evaluation board User manual Introduction y life qdugmented UMOS865 2 2 Basic operation 2 2 1 Working with Linux OS Any x86 based computer that has a
25. escribed in the following sections Table 3 Connectors PLX signals probe connector 1 CD00257207 Rev3 2013 10 16 ISP1763A 9 29 Copyright ST All rights reserved C77 ISP1763A PCI evaluation board User manual Physical description y life qdugmented 3 2 1 3 2 2 CD00257207 UM0865 JP1 Xilinx Tristate input Tristate input to Xilinx to 3 state signals to the ISP1763A JP2 Xilinx PROG input When this jumper is connected the FPGA code will be loaded to Xilinx from U5 Conf1 Butterfly configuration 1 PLX signals probe connector This is only for using the logic analyzer Probe debug signals between FPGA and PLX9054 communication The default setting is not mounted on board J2 ISP1763A bus interface This header has all the address bus data bus and control signals of the ISP17634A 2013 10 16 ISP1763A Copyright ST All rights reserved 10 29 Lv ISP1763A PCI evaluation board User manual Physical description y life qugmented UM0865 Figure 5 J2 bus interface 3 2 3 J3 J4 J5 and 6 bus test headers These headers are only used to probe bus interface signals Only for testing The J3 male header is for lower 8 bit AD 7 0 signals The J5 male header is for upper 8 bit AD 15 8 signals The J4 male header is for the DACK DREQ IRQ CLE ALE ADV_N WR_N RW_N WE_N RD_N DS_N RE_N OE_N and CS_N CE_N control signals The J6 male header is for 8 bit
26. on 3 2 3 and Section 3 2 7 Changed the package name from HVQFN to VFQFPN 2013 10 16 Applied ST branding No other change in the content 1 3 Board history Table 2 Board history m 2009 10 30 09283 1 ISP1763 PCI evaluation board first release 2009 10 30 09282 1 ISP1763 PCI evaluation board VFQFPN first release 1 4 Reference list 1 Universal Serial Bus Specification Rev 2 0 www usb org 2 PCI Local Bus Specification Version 2 2 3 PLX PCI 9054 Data Sheet 4 5 1763 PCI evaluation board FPGA design CD00259895 0 0887 5 SP1763A Hi Speed USB OTG controller data sheet 000264885 6 SP1763A programming guide 0070 CD00265095 CD00257207 Rev3 2013 10 16 ISP1763A 5 29 Copyright ST All rights reserved C77 ISP1 763A PCI evaluation board User manual Introduction y life qdugmented UM0865 2 Introduction This section provides a description of the ISP1763A PCI evaluation board along with the key features and a block diagram of the circuit board 2 Key features The ISP1763A is a Hi Speed Universal Serial Bus USB On The Go OTG dual role controller with two USB ports Port 1 is configurable as a host controller an OTG controller or a peripheral controller while port 2 is always assigned to the host controller The ISP1763A bus interface provides SRAM general multiplex NOR NAND modes to communicate with most types of microcontrollers and mi
27. ply select Connect pin 1 and pin 2 5 V is supplied by external power supply PS1 or PS2 Connect pin 2 and pin 3 5 V is supplied by the PCI slot default JP7 select This is the power supply select Connect 1 and pin 2 is powered by 3 3 V default Connect 2 pin is powered by 1 8 V PS1 PC power connector Used for external supply of 12 V from the PC power supply Connect pin 1 and pin 2 of JP6 5 V is supplied by external power supply 51 This is not used when the ISP1763A is inserted into the PCI slot PS2 DC power socket Used for the external supply of 12 V 3 A from the DC power supply Connect 1 and pin 2 of JP6 5 V is supplied by external power supply PS2 This is not used when the ISP1763A is inserted into the PCI slot CONI PCI connector This is the standard PCI bus interface that is compliant with PC Local Bus Specification Ver 2 2 All PCI signals are connected to PLX9054 PCI to local bus I O accelerator chip CN1 PXA320 platform connector By default this connector is not mounted Only for the BSQUARE PXA320 platform use While using this connector with the PXA320 platform the ISP1763A PCI evaluation board is powered by external DC 12 V 3 A power supply PS2 1 Connect pin 1 and pin 2 of jumper JP6 The evaluation board is powered by the external power supply 2013 10 16 ISP1763A 12 29 Copyright ST All
28. quency default FREQSEL2 LOW LOW HIGH HIGH Through R111 to GND Through R113 to FREQSEL1 LOW HIGH LOW HIGH Through R112 to GND Through R114 to Bus interface SRAM General Comment default multiplex CLE HIGH LOW LOW HIGH Through R120 to GND Through R122 to Vecio ALE ADV_N HIGH LOW HIGH LOW Through R119 to GND Through R121 to 3 3 LEDs The ISP1763A PCI evaluation board has seven LEDs that are located on the top side of the board Information regarding these LEDs is given in Table 5 Table 5 LED LED1 JTAG download or program done indicator Orange LED3 Vpus1 Volts indicator After loading the host software the light will be turned on LED2 Vpus2 volts indicator After loading the host software the light will be turned on Ra CD00257207 Rev3 2013 10 16 ISP1763A 14 29 Copyright ST All rights reserved ISP1763A PCI evaluation board User manual Physical description y life qaugmented UM0865 epee LED4 5 V indicator LED5 1 8 V indicator Reo LED6 2 5 V indicator LED7 3 3 V indicator 3 4 Board components This describes the operation of the major board components on the ISP1763A PCI evaluation board 3 4 1 ISP1763A chip The ISP1763A PCI evaluation board is available in two packages TFBGA and VFQFPN d 3 HRY ye EL Figure 8 ISP1763A VEQFPN Figure 9 ISP1763A TFBGA CD00257207 Rev3 2013 10 16 ISP1763A 15 29 Copyright ST
29. rights reserved Lv ISP1763A PCI evaluation board User manual Physical description y life qdugmented UM0865 2 Connect pin 1 and 2 of jumper JP7 The I O voltage of the ISP1763A is set at 3 3 V The PXA320 platform does not provide 1 8 V 3 Connect pin 2 and pin of jumper JP1 It 3 states all I O pins from the FPGA connected to the ISP1763A IC 4 Connect pin 1 and pin 2 of jumper JP2 The FPGA program is loaded from U5 The program has the logic for the 3 state of the pins 3 2 16 DC1 DM357platform connector By default this connector is not mounted Only for the DAVINCI DM35 platform use While using this connector with the DM35 platform the ISP1763A PCI evaluation board is powered by external DC 12 V 3 A power supply PS2 1 Connect pin 1 and pin 2 of jumper JP6 The evaluation board is powered by the external power supply 2 Connect pin 2 and pin of jumper JP7 The I O voltage of the ISP1763A is set at 1 8 V The DM35 platform does not provide V 3 Connect pin 2 and pin of jumper 1 It 3 states all I O pins from the FPGA connected to the ISP1763A IC 4 Connect pin 1 and pin 2 of jumper JP2 The FPGA program is loaded from U5 The program has the logic for the 3 state of pins 3 2 17 Conf1 butterfly configuration Frequency selection is done using pins FREQSEL1 and FREQSEL2 The corresponding resistors are mounted to connect FREQSEL1 and FRESEL2 to GND or Vcciro Toconnect FRE
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