PCADADIO - Farnell
Contents
1. ADHI CLRINT i TPL e CLK4M E ass IROZ 100K 100K LKZ fiare ADINT O ses de Dees IRO3 Ici8 TRE LK4 1 T22U10 CTCBINT IRGE ZRCONU I CLK ADRY 23 ppg E B Ira BRES H ADEN Eco serey 22 ED Sud e REEN gt Zeen ira lEt 1023 El 4 STAT INTC eos 14 174 15 RPS BUE T Ed ina SE sts ace HE TP BO4 Lon ois x Deen pour HE T 1c20 BD3 11 16 MAD3 al 16 BOS lap o4 42 MEDS RCEN Lap EAT AD abi 18 374 18 807 3n ga Seren Busy HE SD 20 BOI 4 S MADI ia 14 ADLO 17 op 15 BDE 2D D OUTE ADHI pe BDO 3 2 MaDe 11 13 ADS 14 55 I iD Qi A 4 4 MRES CIMT En Lk11 LKLG Lks ADS 13 bp satte BD4 Le cren f RCEN f SWEH T TP amp AD Blan 4a E03 LA De ADB 7 B BOS E S ap 30 as ebs 4 55 Een MUXAD le apa alio o2 808 tea sIP2 a alas CK o IK SIP4 102 bg 103 ER 1 jt KS i ebene P Je 1 ciee2. 0 7 Function ADC ready 0 conversion completed since last read of ADC Data High Byte Counter Timer ready 0 OUTB has transitioned low high since Clear CTC Ready last accessed Writing any data starts conversion ADO 3 ADC data from last conversion AD4 11 ADC data from last conversion Multiplexer channel address 0 15 for PCADADIOCS 0 7 for PCADADIOCD DAO 3 DACA low data DA4 11 DACA high data DBO 3 DACH low data DB4 11 DACB high data See Intel 8254 data sheet See Intel 8254 data sheet See Intel 8254 data sheet See Intel 8254 data sheet Writing any data sets Status Flag CTC to 1 and clears CTC interrupt if enabled NBENO 3 0 nibble configured as output 1 nibble configured as input PL7 Digital I O DigO 7 PL7 Digital UO Dig8 15 Green User LED Control 0 LED off 1 LED on Reads as 2Dh Installing Multiple PCADADIOs This is just like installing a single PCADADIO except that each must be installed at a different address The base address must be set in 4 byte boundaries rcom CONTROL SYSTEMS Page 7 2192 09061 000 000 J489 PCADADIO ADC Sequence The PCADADIO is shipped calibrated for the 5V range and requires re calibration if used on other ranges The ADC may be triggered from three alternative sources selected by a jumper Software trigger from writing the register Hardware trigger from an external TTL input approximately 1 2usec low pulse Periodic timer
3. 17 Installation for CE Compliance oocccococon hh hh hh hr 19 Reference 2 2 a eae a a a Rar Gee D c mE RR TR eee RL EUR TR 20 Circuit Diagrams cer Mann a ka De ee 22 rcom Page 3 CONTROL SYSTEMS 2192 09061 000 000 J489 PCADADIO Page 4 rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 Introduction The PCADADIO is a low cost multi purpose UO board for PC compatibles It has eight differential PCADADIOCD or 16 single ended PCADADIOCS multiplexed analogue inputs two analogue outputs 16 digital I Os and three counter timer channels The operation of each of these functions is controlled using the PC XT bus and link options Features CE compliant design 8 differential or 16 single ended multiplexed 12 bit ADC channels 10kHz channel to channel acquisition rate buffered input 100kHz repeat rate back to back single channel conversion 10us typical conversion rate 5V 10V 0 5V 0 10V selectable input ranges Two 12 bit 1 bit accuracy analogue output channels 5V 0 5V 0 10V channel by channel selectable output ranges 10us settling time to 12 bit accuracy Intel 8254 compatible 3 channel counter timer 1 ADC timer 1 interrupt timer 1 general purpose timer 1MHz master operating frequency 16 TTL nibble configurable digital UO lines Input 1K pulled to 0 8V resistor input low Output 24mA at 0 45V sources from 1K resistor at 5V Selectable power up states Compact I O addressing scheme 4 b
4. BCLK1M rcom Title PCRDRDIO ANALOGUE AND DIGITAL 140 BOARD Sheet our jpessine Me ago CONTROL SYSTEMS LTD drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent C LAST ACCESSED 9 Jan 1995 Arcom Page 24 2192 09061 000 000 J489 PCADADIO VAPO R26 ESOR GRINOR UR VAPOS TPZ 2G0R R25 zu R24 UREF aser T 1K2 AB 5URER A Bug TR3 REF BIP UNI YRZ RE cag BE 10 1013 jaa 5 csq AD7547 gra L Ree 20 Weg cad 18 CSB 33 Ic1 AGND UR outa L ep 2 as i les b D11 teg TS Die YRA 4 RT T DACA WDACA ps 21 VANEG L 10K DS VDD OFFOA SR D AGND URS WDACB UE Soe 3 10k DS R13 cag BDa 7 D4 RFB UANEG 53 20K D2 OUTB w D1 8 Lez Da URB 5 me l DACE ES Tak Loan SE varos HIR Ril URE Er Ra 10K AB m A BLKS A Gene yea BIP UNI cag UANEG POOR Bo 14 n174 i15 L ps BDE 13 EB oe 12 LBDG aos til o4 19 LEDS ED4 Elo as 7 LED4 Zen E 1D oi E cL sh DACLATCH ZBRES VAPOS 12 k E LM31 viaa 1024 ces 53 TRE pTysLes R30 E 100 on NK Ltn our in out H 5UA 13 ADJ SER GND UB R23 s
5. E cu tens Sr 248 es ZC TEE TRF1 S R31 18u y NE REF a2 T N 2K4 CT E i AGND T al B Filo ante E R27 SE CATHAL ES R100 R42 eet C44 4 T6R 4 TOR Ral 1004 Teu rcom CONTROL SYSTEMS LTD PCADADIO This drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent C ANALOGUE AND DIGITAL 170 Drawing No 1994 LAST ACCESSED 9 Jan 1995 Page 25 Arcom J489 PCADADIO 2192 09061 000 000 ela PLE THE RIBBON CABLE WIRE NUMBERS START WITH RC 18 aoe a Bar Ae BCLKB A 38 3e THE D CONNECTOR PIN NUMBERS ON THE BCLK1M 3 Al 5g za CLK14 PCB MOUNTED D CONNECTOR START WITH D BOUTC A se 68 BGATEE t Si 7 BGATEC s GE ES ES BOUTB 3 ae 250 325 IRQ3 L4 BCLkIR A 24 24 5 3 AT mw LI PL1 BCLKC As 23 23 al Rpse De 5 _ ae SS 22 R o 4 goa RC4S DI CAD En 21 Beas D33 ES 20 12h BEAT pas ig Eu RC46 DIE ig is Mi em Han D32 gy CMT Re44 D48 16 16 DACA RC43 D15 15 15 D31 14 14 D47 197 3 e LORD D14 IS Er SE pae 11 AEN m l D46 1g 18 Dia lie eg GND D6 en wire pes D1 Ben D45 E 7
6. always unpack and install the board in an anti static working area Please ensure that should a board need to be returned to Arcom it is adequately packed and if a battery is fitted that it is isolated Revision History Manual PCB Comments Issue A V1 Iss 2 960731 First released in this format Issue B V1 Iss 2 980115 ECO2684 rcom CONTROL SYSTEMS Page 2 J489 PCADADIO 2192 09061 000 000 Contents Preface Sia A LA Sie eio AA fair e tes a a erm ee AAA EE 2 Packing List Utility Disk Handling ESD Packaging ssl 2 Revision History 2 2 d ni rg ua ERR ERR GE RE ee 2 INTFOGUCTION ees cM e UE 5 OU ti DIE SR E RT EE PP UTERE TM M 5 Getting Started vo docu O 5 Operati EE 6 Reading from or Writing to the Board Base Address Selection The I O Pointer Scheme 6 Pointer Value amp Register Function Installing Multiple PCADADIOs 2 7 ADC Sequence DAC Sequence Digital I Os Counter Timers llle 8 ADG Trggetitg tee e EE 9 Links and Options e tt lb REM ER Rem d TRE EE a AA Behr RYE 10 Default Link Position Diagram 00 e 10 Board Functions secas a onu e oa e re RR e ede ee AA A 11 User Configuration Record Sheet o ocooccccco nennen 13 Calibration 2 52 2i nix eae is a Ee Se o a peg nta Dus cate ee 14 Galibratingithe ADG s nume ser Ph aestus ae ba 14 Calibrating the DAGS ob other tI I E Hai ome need 15 Utility DISK ELTE 16 CONNEC O S cC PE Pm
7. maximum flexibility the connections have been arranged to allow clock inputs to be linked to the standard 1MHz clock or other channel outputs using jumper links The pinout of the 10 way header and connections are shown below BCLKB 10 BOUTC 8 BGATEC 6 BCLK1M 4 45V 2 C9 O1 BCLK1M BGATEB BOUTB BCLKC GND J489 PCADADIO rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 Installation for CE Compliance To maintain compliance with the requirements of the EMC Directive 89 336 EEC this product must be correctly installed The PC in which the board is housed must be CE compliant as declared by the PC manufacturer The external I O cable should be the Arcom CAB50CE or a fully screened cable to the same pattern 1 Remove the cover of the PC observing any additional instructions of the PC manufacturer 2 Locate the board in a spare ISA slot and press gently but firmly into place 3 Ensure that the metal bracket attached to the board is fully seated 4 Fitthe bracket clamping screw and firmly tighten this on the bracket NOTE Good contact of the bracket to chassis is essential 5 Fit the screened I O cable to the 50 way board connector 6 Ensure that the jack screws for the cable connector are tightened use a screw driver 7 Replace the cover of the PC observing any additional instructions of the PC manufacturer The following standards have been applied to this product BS EN50081 1
8. 1992 Generic Emissions Standard Residential Commercial Light Industry BS EN50082 1 1992 Generic Immunity Standard Residential Commercial Light Industry BS EN55022 1995 ITE Emissions Class B Limits and Methods rcom Page 19 CONTROL SYSTEMS 2192 09061 000 000 Reference Test Point Locations J489 PCADADIO Test Description Point TP1 PCbus IRQ2 TP2 DAC Voltage Reference TP3 45V Analogue TP4 PCbus IRQ3 TP5 Analogue Supply Approx 15V TP6 Analogue Supply Approx 15V TP7 ADC Chip Enable TP8 ADC Status Line TP9 Analogue Ground TP10 Digital Ground TP11 Buffered Reset Active Low TP12 I O Address Match TP13 5V Digital TP14 Device Write Active Low TP15 Device Read Active Low Page 20 rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 Trimmer Locations Function ADC Gain DAC Reference Voltage DAC Ch A Gain DAC Ch B Gain DAC Ch A Zero Offset DAC Ch B Zero Offset ADC Zero Offset Trimmer N NK N N MN ARAN gt N Na T rcom Page 21 CONTROL SYSTEMS J489 PCADADIO iagrams t Di rcu
9. 3 if necessary Repeat for DAC channel B replacing VR5 with VR6 and VR3 with VR4 Bipolar Calibration For DAC channel A Zero Offset Adjust 1 Set DAC A output to 000 hex 2 Measure between the DAC A output on PL1 and analogue ground and adjust VR5 to give full scale negative i e 5 000V Full Scale Gain Adjust 1 Set the DAC A output to 800 hex 2 Measure between the DAC A output on PL1 and adjust VR3 to give half scale output 0 000V 3 Set DAC A to FFF hex and check full scale is 4 9975V Repeat for DAC channel B replacing VR5 and VR6 and VR3 and VRA rcom Page 15 CONTROL SYSTEMS 2192 09061 000 000 J489 PCADADIO Page 16 Utility Disk A Utility Disk containing example software is supplied with the PCADADIO to help you get started README TXT File The file README TXT is the first one you should look at It contains up to date information on the whole disk PCADADIO INI The demonstration program uses a file PCADADIO INI which allows the user to initialise the base address ADC and DAC ranges etc This file may be edited to reflect changes in the board settings PCADADIO EXE This program displays the ADC inputs scrolls an active bit along the digital I O and allows setting of the DACs These will all run with the standard link settings Decrementing CTC data and incrementing interrupt counts are also shown In order for these to run it is necessary to add a link to LK2A between pins 9 and 10 on PL3
10. 7 D12 A D Ben D28 5 5 Dien m D44 4 IRQZ Dii Ds En D27 ps gt a8 DAS D Le RESET De tet AGD D26 RHS COMPONENT SIDE SOLDER SIDE D42 pa pes D4i D ayo LP RCL D24 HEES UAPOS CHT CH1S e mis Cool ciel cid CzE cae casal cad cel ed cial ces Hrs Rela D23 TRS SUA Is E y CHB CH149 B t 15 pss BGN 1 44 I H AGND SUA CH8 Ge in cal cesl ced ced cag csg ceg csalo cagicag CH5 4CH134 2s a 58 REIS D22 CHET amp TPB ERE Zei poe VANES VANES EE u R 12 Del PDIFF E amp RELL D37 AGND 2 CH3 CHiie ste D4 TP13 RCI nea TSU Atos D36 CH2 CH1 04 BS m CH 4 Bu Dis 5 e e e e e e CH1 7CH93 s a d T Cu BCE D35 cealcralcsel cad cem ciel ced cel cvelesal cel ceg cen ce cv4 oval c7 cael cval C E C34b ceal csal carl C HDL CI de C92 c38 Cal CH CHE B E CHO 8 D34 E PDIFE Bei ni fm amp GND 5 TP18 4 DGND rcom Title PCADADIO ANALOGUE AND DIGITAL 1 0 BOARD Seen Bap o rssins Mes daga CONTROL SYSTEMS LTD This drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent LAST ACCESSED 9 Jan 1995 Arcom Page 26
11. DIDA 1 o 3 TAB 103 ign T S Ar cis 13 ns m To lelals az IE GAS 19 128 S 5 vaPos ECZ 0 T gy er CHB _ E EA 128 EN IU GAIN 5c 5 26 CHS CHIH I A 138 2 INAL11 URL LE CIE 21 14 18 DS CHE 14 E 134 A3 Yat REF I 24 Cd 091244 148 pela E i 100R 3 Ic ES ieee cHe t F E 1a a1 HE E Si REF 76 M REFO an sra Hits ADS 18 553 op 15 BD CH3 CH11 4 7 Isp ao ir 48 8K a un REL 12 lop OR DES Abe 17T 5 pp 16 BEDE cH E E 154 ll Lk SIR 13 ee ADL Aen gg 19 EDS CHZ CH194 C IC ouTal A Are TOVIN Dia AD len oi BD4 E tea 5 TS MANE DEL eur Gage D Sjap 4q 3 B03 CHI CH84 RLC E 178 OUTE x De MADE jsp so 802 C10 E Ae en VAPOS D Di elis le F 14 z Bo y u Ps MaD 4 zus EDI CHO cH8 M 198 yo IET B sk OFFSET Rid LEE PGND N A A Da MADE 3 2 EDO Ce ES y UR Aa NA B 10 10 CHAR HER Isa OU A 10k PKA e 12 H RE E UNI i 1 1 CK oE E LKL 10R Par 6 xs vanes cs2 I 1 ft IK sIP3 T SUA t 1K in 1033 PDIFF M8254 5 ZADLO E eus SE Oe VAPOS VANES BDE 2 18 10K le sie a ned BCLKC send Era ac Zou out eue BGATEC H zes eva GATS Per Sinz EO BCLKB jene 2v2 z mE ape Spe oct BOUTB BGATEB Heer evi BDL Zo catei H4 164 1Y4 Le e our SUTB D Ellas iya 14 LKIE 103 182 12 m RIO EE RD cko A ero 8 lal 1Y1 te UR carpe il A BINE l RP ese maint oe Ica 10K EE TE SE 1 1a D i3 ETLS 55
12. J489 PCADADIO 2192 09061 000 000 PCADADIO Multi Function Digital Analogue O Board Technical Manual Product Information Full information about other Arcom products is available via the Fax on Demand System Telephone Numbers are listed below or by contacting our WebSite in the UK at www arcom co uk or in the US at www arcomcontrols com Useful Contact Information Customer Support Sales Tel 44 0 1223 412 428 Tel 44 0 1223 411 200 Fax 44 0 1223 403 400 Fax 44 0 1223 410 457 E mail support arcom co uk E mail sales arcom co uk or for the US E mail icpsales arcomcontrols com United Kingdom United States France Germany Belgium Arcom Control Systems Ltd Arcom Control Systems Inc Arcom Control Systems Kostenlose Infoline Groen Nummer Clifton Road 13510 South Oak Street Centre d affaires SCALDY Tel 0130 824 511 Tel 0800 7 3192 Cambridge CB1 4WH UK Kansas City MO 64145 USA 23 rue Colbert Fax 0130 824 512 Fax 0800 7 3191 Tel 01223 411 200 Tel 816 941 7025 7885 SAINT QUENTIN FoD 0130 860 449 Fax 01223 410 457 Fax 816 941 0343 Cedex FRANCE Netherlands FoD 01223 240 600 FoD 800 747 1097 Tel 800 90 84 06 Italy Gratis o6 Nummer Fax 800 90 84 12 NumeroVerde Tel 06022 11 36 FoD 800 90 23 80 FoD 1678 73600 Fax 06022 11 48 The choice of boards or systems is the responsibility of the buyer and the use to which they are put cannot be the liability of Arcom Control Systems Ltd However Arcom s sales team
13. LK4B Sends an interrupt from the counter timer OUTB to IRQ3 CTC OUTB strobing high is also indicated by the status flag register whether or not a link is fitted Links LK5 LK6 DAC Output Range Links LK5 and LK6 selects the output range for DAC1 and DACO respectively The range settings are as below LKA 5V to 5V LKB OV to 5V None OV to 10V Links LK7 LK8 and R15 ADC Input Ranges Links LK7 LK8 and R15 select the input range to the ADC The range settings are as below rcom CONTROL SYSTEMS LK7 Range A 5V to 5V A OV to 10V B 10V to 10V A OV to 5V Under no circumstances should both links be fitted to position B Page 11 2192 09061 000 000 Page 12 Link LK9 LK10 and LK11 ADC Trigger Sources These three links enable the three different ADC trigger sources Each trigger source is enabled when a link is fitted J489 PCADADIO Please note that only one link should be fitted for reliable operation LKO9 fitted LK10 fitted LK11 fitted Enable software triggering Enable hardware triggering Enable counter timer channel A triggering Links LK12 LK13 LK14 LK15 Digital UO Reset State Thee links select the state of the digital I O lines at reset in nibble 4 bit groups each nibble is shown below Reset high should be used when the digital l Os are to be used as inputs otherwise the lines will be driven low as out
14. as shown 10 car 9 8 7 6 an 5 4 aa 3 2 a 1 rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 Connectors PL1 Front Panel 50 way D type The PCADADIO has two user connectors PL1 and PL3 PL2 is the edge connector on the PCB used to connect to the PC bus PL1 is located on the board front panel and the pinout is compatible with the Arcom Signal Conditioning System SCS For this reason the pinout is listed both for the 50 way D type and a 50 way ribbon cable The pin locations for these connectors are shown below Ribbon Cable No D 50 Pin No Signal Title 1 f o 3 18 emos 4 2 Ch0 CH8 5 3 o 6 19 Cht Ch9 7 SCH 8 36 Ch2JChi0 3 Ca hw 10 4 Ch3 Chti i VA 12 pa o PDIFF E s MIT 14 38 Ch4 Ch12 15 CS c 16 6 Ch5 Chi3 17 SCH 18 23 Ch6 Ch14 19 SC 20 40 Ch7 Ch15 21 Ca 22 E PDIFF 23 a Di 24 2 Dis 25 be 26 e De 27 CS na 28 o ns 29 e Die 30 Dig g m em 32 44 Not Used 33 e Dis 34 12 f De 35 5 Dep 36 2 f bie 37 Pig 38 45 iss 39 3 Den 40 CL iss ai VA 42 Reserved E ps DS 44 Ca acs 45 Not Used 46 mp o e Not Used a8 HN E El 50 50 5V rcom Page 17 CONTROL SYSTEMS 2192 09061 000 000 Page 18 PL3 10 way IDC Header PL3 is used for connecting external signals to buffered versions of the CTC inputs and outputs for channels B and C For
15. ase 1 The ADC and DAC data are accessed using the low and high access registers located at Base 2 and Base 3 This feature can be used to optimise data acquisition using software word access since this results in two contiguous bus cycles Base 2 followed by Base 3 There is no need to write a new pointer value before access is made to read ADC data Base Pointer Register Write Only Base 1 Diagnostic and Control Access Byte Read Write Base 2 DAC and ADC Low Access Byte Read Write Base 3 DAC and ADC High Access Byte Read Write Page 6 rcom CONTROL SYSTEMS J489 PCADADIO Pointer Values and Register Function 2192 09061 000 000 Pointer Value hex 00 00 00 00 00 01 Read Write Read Base 1 Read Base 1 Write Base 1 Read Base 2 Read Base 3 Write Base 1 Write Base 2 Write Base 3 Write Base 2 Write Base 3 R W Base 1 R W Base 1 R W Base 1 R W Base 1 Write Base 1 Write Base 1 R W Base 1 R W Base 1 Write Base 1 Read Base 1 Function Register Name Status Flag ADC Status Flag CTC ADC Start Conversion ADC Data Low Byte ADC Data High Byte Multiplexer Channel Select DACA Register DACA Register DACB Register DACB Register CTC Counter A CTC Counter B CTC Counter C CTC Counter Control Word Clear CTC Ready Digital UO Configuration Digital VO Group 2 Digital VO Group 3 Not Used User LED Board ID Data Bit
16. ating the DACs In order to calibrate the DACs it is necessary to have a DVM with at least 5 digit resolution On the demonstration disk there is a facility useful for calibrating the DACs This allows each DAC to be set to the required value for calibration A single trim VR2 is provided to trim the reference voltage used by the DACs Additionally two trimmers are provided for adjusting the zero offset and gain of each DAC channel VR5 and VR3 trim the zero offset and gain of DAC channel A and VR6 and VR4 DAC channel B respectively These trims are for fine adjust only within standard ranges Set the necessary links for the required mode and voltage ranges Run the screen display software Put the DVM on the AGND and VREF test point and adjust VR2 to read 5 02V Note If the gain adjust trimmers VR3 amp 4 have insufficient range adjust VR2 to read 5 01V and repeat the calibration procedure Unipolar Calibration For DAC channel A Zero Offset Adjust 1 Set DAC A output to 000 hex 2 Measure between the DAC A output on PL1 and analogue ground and adjust VR5 to give 0 000V Full Scale Gain Adjust 1 Set the DAC A output to 800 hex 2 Measure between the DAC A output on PL1 and adjust VR3 to exactly give half scale output 2 500V for the OV to 5V output and 5 000V for the OV to 10V output 3 Set DAC A to FFF hex and check full scale is 9 9975 for OV to 10V range 4 9985 for the OV to 5V range 4 Adjust VR
17. e ADC In order to calibrate the ADC it is necessary to have a precision digital voltmeter DVM with at least 5 digit resolution and a high stability low noise DC signal source To monitor adjustments it is necessary to continually read and display the ADC data There is a program on the Utility Disk which provides this facility PCADADIO EXE Two trim adjusters VR7 and VR1 are provided for trimming the zero offset and gain respectively These trims are for fine adjusting the standard ranges Unipolar Calibration Set the necessary links for unipolar mode and the required voltage range Run the screen display software Zero Offset Adjust 1 Set the input voltage to exactly zero 2 Adjust VH7 to give 000 to 001 hex Full Scale Gain Adjust 1 Setthe input voltage to full scale positive minus 1 LSB 44 9985 for the 5V range 9 9975 for the 10V range 2 Adjust VR1 to give FFE to FFF Bipolar Calibration Set the necessary links for bipolar mode and the required voltage range Run the screen display software Bipolar Offset Adjust 1 Set the input voltage to full scale negative plus 1 LSB 4 9975 for the 5V range 9 995 for the 10V range 2 Adjust VR7 to give 000 to 001 hex Full Scale Gain Adjust 1 Set the input voltage to full scale positive minus 1 LSB 44 9975 for the 5V range 49 995 for the 10V range 2 Adjust VR1 to give FFE to FFF rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 Calibr
18. is always available to assist you in making your decision La Pen HM A O 1996 Arcom Control Systems Ltd Acom conrei SCH d Arcom Control Systems is a subsidiary of Fairey Group Plc quality management Ip P system which has been Specifications are subject to change without notice and do not form part of any contract certified by the British All d k ised Standards Institution BSI trademarks recognised as compliant with 1509001 1994 rcom Page 1 CONTROL SYSTEMS 2192 09061 000 000 J489 PCADADIO WindowsNT FREE Windows NT4 0 Drivers Visit the PC ISA bus Boards page on the Arcom Website www arcom co uk ntdrv10 AR exe to download Preface Packing List This product is shipped as follows Board User Manual Utility Disk If any of the above appear to be missing please telephone Arcom 01223 411200 Throughout this document denotes that a signal is active low All address and data values are in hexadecimal Utility Disk This product is shipped with a utility disk which contains PCbus Library Source code written in C and sample executable files to aid in calibrating the board Also supplied is a programming resistor which is required for the 0 5V range of the ADC Handling ESD Packaging This board contains CMOS devices which could be damaged in the event of static electricity being discharged through them At all times please observe anti static precautions when handling the board and
19. l 2192 0906 1 000 000 Ci 12 11 MS NIBBLE 3 BCLK1M BOARD ID 20 5 LS NIBBLE A AE EA AA Ae Ices T22V1a ER cre Re Fe AL RES CLRINT DCONF DIGZWR DIGZRD DIGLUR DIG1RD WIO RIO STi sra Bae eo oo 2 jm Jen 4 oa ru 5 BAL BRES OFF BIORD DEN BIOWR RAT ss en I cn on Io ru bl STAT MUXAD ADGO ADHI ADLO DACLATCH WDACA WDACB w oo u ln jen 4s oa ra Se pe GREEN F2 USER LED ESOR m fe 4s on In foo an OFFREG re fee ee 53 7 rcom PCADADIO ANALOGUE AND DIGITAL I O BOARD Drawing No J489 CONTROL SYSTEMS LTD This drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent C 1994 LAST ACCESSED 9 Jan 1995 Arco
20. last conversion they must be read within 6uS of triggering a new conversion RCONV or OUTA 6us max 250ns min rcom Page 9 CONTROL SYSTEMS 2192 09061 000 000 J489 PCADADIO Links amp Options Default Link Position Diagram PL1 PL2 PL3 LZ AR i Lie S ll Default Link Page 10 rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 Board Functions Throughout this section indicates a factory set default link Link LK1 Pseudo Differential Ground Connection Fit PCADADIOCS Fit only if inputs are isolated from OVA Omit PCADADIOCD differential inputs Link LK2 ADC Interrupt Selection Link LK2 selects an interrupt source for the ADC which generates an interrupt signal after conversion is complete and indicates ADC data is ready for reading LK2A Sends an interrupt at conversion complete to IRQ2 LK2B Sends an interrupt at conversion complete to IRQ3 ADC conversion compete is also indicated by the status flag register whether or not a link is fitted Link LK3 Differential Single Ended Input Selection A PCADADIOCD B PCADADIOCS Link LK4 Counter Timer Interrupt Selection Link LK4 selects an interrupt source for the counter timer channel B An interrupt will be generated whenever the OUTB pin of the counter timer 8254 strobes low to high LK4A Sends an interrupt to the counter timer OUTB to IRQ2
21. m Page 22 2192 09061 000 000 J489 PCADADIO DIGIWR DIGOEL DIGIRD DIGOEg Ic4 244 2Y4284 eva ZAA evesna gYlzni 1141484 1Y3143 1Yr2 142 lY1181 16 26 1 DIGEWR DIGOE3 LDIG1 amp 5 1 3 LDIG14 LDIGi3 LDIGie LDIGi1 LDIG1 amp LDIGS LDIG8 amp DCONF DIGOE4 DIGERD ICS 244 24424 2Y32A3 eve 2 2z 2Y1ZA1 L 144 1Y3143 1Yr2 142 1r11A1 16 26 1 BDO 7 rcom CONTROL SYSTEMS LTD Title PCADADIO This drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent ANALOGUE AND DIGITAL 140 BOARD 1 3 Sheet 2 of 5 i c H DIGO 15 Drawing No LAST ACCESSED 9 Jan 1995 Page 23 Arcom J489 PCADADIO 2192 09061 000 000
22. programmed from the on board CTC In the second two cases an interrupt should be used to signal that a new value is ready With a software trigger all timing can be done from the program using this sequence Select channel register and write channel value Delay for input settling about 50usec Select software trigger register and write to trigger value not defined Delay for ADC conversion about 20usec Select status register and read to check that new value is ready Read ADC data registers DAC Sequence Before writing a 12 bit DAC value to the data registers at Base 2 and Base 3 the DAC channel must be selected Write value 02 to the Pointer register for DAC A and value 03 for DAC B Digital Os Before connecting any inputs to the digital l Os check that the links LK12 15 which control the reset state of the individual nibbles are correctly configured as inputs otherwise damage may occur either to the PCADADIO or external equipment The direction of individual nibbles can be switched by writing to the digital configuration register Access to the individual outputs and inputs is via the digital I O group 2 and 3 registers If a nibble is configured as an input a write to the output register will have no effect on the input unless the state of the configuration register is changed to an output In this case the last value written to the nibble will be transferred to the output It is therefore importan
23. puts which may cause damage The link associated with LK15 Digital 1 O lines DIGO 3 LK14 Digital 1 O lines DIG4 7 LK13 Digital 1 O lines DIG8 11 LK12 Digital 1 O lines DIG12 15 LKxxxA fitted Sets the nibble low LKxxxB fitted Sets the nibble high Link LK16 Counter Timer Channel A Clock Source Link LK16 selects the clock source for counter timer channel A LK16A Clocked by the output of counter timer channel C output LK16B 1MHz Clock Link LK17 Digital UO Reset Test Link Used for automated board testing of the digital l Os to ensure they reset into the correct states and should be left in position A rcom CONTROL SYSTEMS J489 PCADADIO User Configuration Record Sheet This sheet may be duplicated Links Pseudo Differential Ground ADC Interrupt LK1 DAC Output Differential LK1 Single Ended Input Counter Timer Interrupt LK2 LK6 ADC Input ADC Trigger Sources LK7 LK8 LK10 LK11 Digital UO Reset State Counter Timer Channel A Clock LK12 LK13 LK14 LK15 Digital UO Reset Test LK17 Base Address Switches SW1 sw2 SW3 rcom CONTROL SYSTEMS all sp A LK14 LK172 Ee Oe LK1653 ds AB 2192 09061 000 000 PL2 Page 13 2192 09061 000 000 J489 PCADADIO Calibration Page 14 Calibrating th
24. t to ensure that the correct value is written to the output register before switching from an input to an output Counter Timers The PCADADIO contains three 16 bit counter timers in an Intel 8254 compatible Counter Timer Chip CTC To offer maximum flexibility the PCADADIO has a 10 way connector PL3 with the facility to link the inputs to external and internal clock sources including the outputs of other counter timer channels Additionally channel A can be used to start ADC conversion and channel B to generate interrupts on IRQ2 or 3 when links LK10 and LK4 are selected respectively Counter A should always be programmed in mode 2 which ensures that OUTA is only active for a single clock cycle i e 1us when connected to the 1MHz clock When OUTC is connected to CLKA the time between rising edges on OUTC must not exceed 6us or be less than 250ns Page 8 rcom CONTROL SYSTEMS J489 PCADADIO 2192 09061 000 000 ADC Triggering The counter timer trigger uses channel A and the hardware strobe the RCONV pin on PL1 Conversion is started from these sources when OUTA signal or RCONV are low To ensure that the ADC does not perform multiple conversions it must be ensured that hardware and CTC trigger pulses are greater than 250nS but less than 6uS Maximum data throughput can be obtained by triggering a new conversion before data from the last conversion is read and processed To ensure that the ADC data registers contain data from the
25. writing to a pointer register and then accessing a data register to read or write the required function The pointer register need only be written with a new value if a different data register is next to be accessed ADC and DAC data is handled by a dedicated pair of registers The board occupies only four bytes of PCbus I O space Each time the board is accessed the Red LED will flash momentarily Base Address Selection The switches set the address of the lowest of the four bytes of the board control registers the base address and the three remaining bytes occupy sequential addresses above this location in PCbus I O space Therefore the base address must be set up on four byte boundaries i e SW3 should be set to 0 4 8 or C The address switches should be set to read from left to right SW1 to SW3 to correspond with the hex switches For example for address 180hex the deepest PCbus I O base address SW1 is set to 1 SW2 to 8 and SWS to 0 The I O Pointer Scheme To access a function on the PCADADIO you must set up the pointer register to point to it This is achieved by writing a pointer value byte to the I O base address Once a particular device is pointed at it can be accessed by writing reading the relevant access register The pointer value need not be re written for every access to the same access register All control and diagnostic functions including ADC control are accessed using the byte 8 bit access register located at B
26. ytes 8 bit ISA bus interface Board access user LEDs ID byte 2Dh IO connector conforms to Arcom Signal Conditioning System SCS Operating temperature range 0 C to 55 C Power required 5V 330mA 5 typical 12V 200mA 10 typical MTBF 172 706 hours using generic figures from MIL HDBK 217F at ground benign Dimensions 289 x 120 x 25mm Weight 266g Getting Started Switch off PC Install board in supplied configuration Switch on PC and observe the LEDs while it powers up You may see the red LED flash once This simply means that the BIOS start up program in your PC is checking through UO space to see if any boards are there It is nothing to worry about On the other hand if your PC fails to boot or the red LED flashes continuously you will need to change the PCADADIO base address e Run EXAMP 01 utility disk The Green User LED should flash The utility disk supplied with PCADADIO contains example software to help get you started PCADADIO EXE will run with the standard link settings and displays the ADC inputs scrolls an active bit along the digital I O and allows setting of the DACs Decrementing CTC data and incrementing interrupt counts are also shown In order for these to run it is necessary to add a link to LK2A between pins 9 and 10 on PL3 rcom Page 5 CONTROL SYSTEMS 2192 09061 000 000 J489 PCADADIO Operation Reading from or Writing to the Board Control of the PCADADIO is achieved by
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