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UM10349 - NXP Semiconductors

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1. SX 9 285 7845 eo e EIE I ES 39 JE 1V8 ARM 8 lt E 8 8 VDD S M vov M lt Y vv vvv v v v v 59g NELI 8445 eRe eee ees Du us Geese esse 88495 oa Yo oa 14430 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 24 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx J11 RX1 gt TX1 P2 8 P2 9 SDA gt SCL P2 10 P2 11 0 15 gt 0 18 P2 12 P2 13 0 19 gt lt P0 20 P2 14 P2 15 0 21 P0 29 P2 16 P2 17 P0 23 lt P0 27 P2 18 P2 19 P0 25 gt 0 24 P2 20 P2 21 P0 28 P0 22 P2 22 P2 23 P0 30 P3 28 P2 24 P2 25 P3 29 4 P3 30 P2 28 2 29 VIN 28 1 8 ARM C33 i C28 Lcx C34 Jp VDD ST7 Los npm i C28 l C42 M DM VDD VDD R25 R26 4 7 KQ 4 7 KQ NRESET pu ISP B fon nF ym VDD VDD VIN VDD a 2 IH TP26 sre
2. 14 serial time 14 power up 15 power up BV iti ed ete cedes ecd 15 power 3V sairib erranari seise teiaa 16 power up 18 16 power 16 card command 0 16 negotiate niit Ifsd 2 1 set clock card card take off and card insertion 17 Sel card baud rate usns 18 19 TDA write 126 cereus 19 write 2 8 1 19 Start 19 Embedded firmware 20 COMPIE tees 20 E 21 Special 22 Remarks for CAKE8037T CAKE8037TT SUPPO E S 22 5 Schematic and 23 5 1 Schematic 5 2 EV 5 3 6 Legal information eene 29 6 1 29 6 2 Disclaimers ssss 29 6 3 Trademarks eese 29 7 lj q 30 8 List of figures cessere 31 9 List of tables eerie rhone conos
3. Selected Sectors r Esecute Code Use Baud Rate pload to Flas vlr ar eae 1 15200 v after Upload 4 Start Sector 0 115200 rase Compare Flash Manual Reset End Sector 14 Time Dut sec 2 Device Use DTR RTS Device for Reset and LPc2212 zd Part ip ATAL Freq kHz fi 4745 Device ID Boot Loader 10 Selection Fig 12 LPC200 Flash Utility Configuration The COM port must be adapted to the one used to connect the Cake80xx MBA board The filename is the built hex file By default after source code installation the path is C Program Files NXP Semiconductors Cake80xxMBAFirmware obj ArmT DA hex To load the software follow the steps e Supply the Cake80xxMBA board and connect the serial port to the PC COM port e Click on the Upload to Flash button under the Flash Utility tool e When the tool asks to reset the board press and hold the ISP switch of the Cake80xxMBA then press and release the RST switch and finally release ISP e Click on OK in the message box of Flash Utility e The load starts After the load is completed reset the board by pressing the RST switch only the board restarts with the new FW UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 21 of 33 NXP Semiconductors U M1 0349 Contact sm
4. d Bar j EN 2 39 SHON R5 sn 2 8 To c 5 eno 2e 6 5o gt SCL d Lew 4 3ol 220 nF 2 1o gt SDA j BadFD Fig 14 CAKE80xx MBA 01 D Schematic part 1 888 014420 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 23 of 33 NXP Semiconductors UM10349 Contact smart card reader chips evaluation with CAKE80xx Fig 15 80 MBA 01 D Schematic part 2 E ggfpgssus NENNT AR ttyttt ttt T 1 ARM_DATA O 7 ls e 6188 8 lt tt ERR 5 228 1V8 ARM 5 E VD 8a g Y2 sz ELE 14 7458 MHz zzz 3 Bd 89 2 lt lt lt lt m zp TOO yy 2 5 2 i Ssdsaf na ssseigssszzkie25 s 222222 VDD gt H gt gt 0 o Oo oO o aj o gt oj gt d do d d A gt gt gt A Dx m m x P2224 mj 833888888388SERBBRESSRSERHEHRPP
5. 7 Capacite COG 0603 SOV 2 0603 Cap UPRISTISD 4 NATIONAL SEMICONDUCTOR AP 38693SD 1 8 Low drop CMOS regulator 00 13V i we 173269350 3 3 NATIONS SONDUCTOR1I3868350 3 3 Low drop CMOS PDD 10 2222 1 es 110144 500486 1 2212 80144 NXP LPC22 12 80144 Microcontroleur 16 32bits 1288 Flash 10 bit ADC packagr lafpld pn x max3241c 1 0 28 sot3 3241 241 c 15232 3 0 to 5 5V ESD protected 1Mbps Package ssop prix 0603 10k 3 i k Resistance Package CMS 0603 1 0 IW 821102 R23 RJA arco eee 70603 4k7 a 5 R26 449 Resistance 0603 1 0 1W pn x 70603 nc 4 RM RIS R16 RIT r003 __ NC Resistance CMS 0603 1 0 1W NON CABLE ipn x subd 09 i 1 734348 1 1 1 5450 9 points femelle coude serie AMPLIMITE ret ae vite x co _ 320x160x160 1008 Capacite Tantalium Package TAJA AVX TAJATOSKO10R 10 10V 85 7V 125 degres 2 cs Capote Tantalum Pakage 10 VS depres 1V125 dps pnsx tajb 3 1 v 125 pnsx 33 3 prex tial 1 Fig 19 Bill of materials UM10349 All information provided in this docume
6. 8 Fig 10 power up 5V frame exchange 15 Fig 11 Build mak Compiler path 20 Fig 12 LPC200 Flash Utility Configuration 21 Fig 13 Cake80xx MBA 22 Fig 14 CAKE80xx MBA 01 D Schematic part 1 23 Fig 15 CAKE80xx MBA 01 D Schematic part 2 24 Fig 16 CAKE80xx MBA 01 D Schematic part 3 25 Fig 17 Layout Top La ayef cirip 26 Fig 18 Layout Bottom 27 Fig 19 Bill 22 222 28 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 31 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx 9 List of tables Table 1 Command 9 Table 2 Outgoing commands only 10 Table 6 Supported baudrates 18 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 32 of 33 NXP Semiconductors UM10349 Contact smart card reader chips evaluation with CAKE80xx 10 Contents 1 2 2 1 2 3 2 2 1 2 1 1 2 1 1 1 2 1
7. The 4 header bytes include the following bytes 1 byte 2 byte 3 byte 4 byte A 1 1 0 0 0 0 0 Data length to transmit excluding Command byte header and LRC A 0 Acknowledge of the frame 1 byte 60 1 Nack of the frame message with a status error 1 byte EO Fig 6 Frame structure The LRC Longitudinal Redundancy Check byte is such that the exclusive oring of all bytes including LRC is null General dialog structure The host controller is the master for the transmission each command from the master is followed by an answer from TDACake80xx_MBA including the same command byte as the input command However in some cases card insertion or extraction a time out detection on Rx line or an automatic emergency deactivation of the card the Cake80xx_MBA is able to initiate an exchange All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 7 of 33 UM10349 NXP Semiconductors Contact smart card reader chips evaluation with CAKE80xx 2 1 1 1 Successful command System to TDA8029 60 XX XX YY nnnnnnnnnnnnnnnnnnnn 27 ACK length code Data C APDU LRC TDA8029 to System 60 UU UU YY 1 mmmmmmmmmmmmmm TT ACK length code Data R APDU LRC 1 The same command byte YY is returned in the answer from TDA
8. R3 47 BRMCADOR UM lt 8007 ioi Re 102 4 888 0 4 103 gt 14 7456 MHz 1 Um Re Cab 625 02 i on 22pF R7 105 eise 79 5 SOWN C18 E ETE ET ETE 107 T 100 nF 108 23 R11 oa z 3 3 x RIO olsa al lt o kik 8991224815 __ 48 47 46 45 44 43 42 41 40 39 38 37 RD ARM_DATA 0 7 TP22 LOAUX 07 5 ARM 07 m a 10K ots Lot 06 8 ARM DATA 06 m 3 12 es D5 ARM DATA 05 T T PRESI D4 TPB ARM 04 ms 5 4 ii TDABDU7BHL ARM ATA 7 8 0 au CONDI 02 TRIO ARM 02 4 Es ek gg Di DATA 01 ib Vect 00 ARM DATA 00 Hs RSTI T Ria R1 amp R17 102 10 27 SAM ne Li 28 ci2 12 1 13 14 15 16 17 18 19 20 21 22 23 24 2 3 E g 3 a 8 A 5 5 F m m MAX3241CAI TL t ea Fe AEN oq em ues T oa VDD E LSU R12 1 1 thos 2 1 vn S C4 R15 2 2 3 A d mE 2201 ze TP2 TIN TOUT Lr 210017 lt 14 T2N t gt qu T20UT VDD 7 RIQUTB os R2OUTB Taper 22 rne TP25 RIOUT RIIN 4 20 19 4 R20UT 5 Er RSOUT 6 5 TP20 R40UT 46 7 RAIN TREE REQUT 5
9. 2 4 1 6 Contact smart card reader chips evaluation with CAKE80xx_MBA get_reader_status This command is used to check the status of the reader System to CAKE80XX 60 0000 AA CA CAKE80XX to System 60 0001 AA EMV PRO FIDI UX CS VER MTH YR LRC Where e EMV emv state e PRO protocol type e FIDI current FiDi e UX UX parameter e CS Cards 1 to 4 state High nibble Presence low nibble activation e VER Actual version number e MTH Month of the actual version e YR Year of the actual version set_serial_baud_rate This command is used for changing the baud rate onto the serial link between the host and the interface card The default value is set to 38400 baud A parameter has to be transmitted in order to choose the baud rate System to CAKE80XX 60 0001 OD PAR LRC CAKE80XX to System 60 0000 00 6D Table 4 Baud rate parameter Baud rate Baud Parameter 4800 00 9600 01 19200 02 38400 03 57600 04 76800 05 115200 06 After a baud rate change the new value takes place for the next command sent by the host serial time out This command is sent from CAKE80XxX to the host controller if during a transmission from the host controller to CAKE80XX the time interval between 2 characters exceeds 10ms This timing is calculated between each character of a frame starts after the first character and is disabled after the last character of the frame This feature has been implemented in order to avoid any blocki
10. set card baud rate Sets the baudrate of the activated smart card ifsd request OCh Request an IFSD change for the activated smart card communication Set_serial_baud_rate Changes the baudrate for host communication show fidi Displays the current FiDi set serial timeout Sets the timeout for the serial connexion negotiate PPS 10u Initiates a parameter change for t 0 set clock card 11 Selects the division for the smart card clock tda write i2c 2 Write to a TDA connected to the CPU through I C interface tda read i2c 2 Reads from a TDA connected to the CPU through I C interface start EMV loopback 2Fu Launch the EMV loopback process Blocking function that does not return power_off 4Du Deactivates the current smart card select_device 67H Selects the connected TDA daughter board power up 1 8V 68H Activates the card with VCC 1 8V select_card Selects the smart card to access power up 3V 6Du Activates the card with VCC 3V power up 5V 6Du Activates the card with VCC 5V set nad Abu Sets the NAD parameter for T21 communication idle mode 9 Sets the smart in idle mode activated with lower consumption get reader status Displays information about the current state of the reader UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 rights reserved User manual Rev 1 0 1 October 2014 9 of 33 NXP Semiconductors UM1 0349 Conta
11. 0xB4 128 0xD5 128 0x23 139 5 0x52 744 0 93 128 OxB5 64 0 06 64 0 28 46 5 0 53 372 0 94 64 0xB6 32 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 18 of 33 NXP Semiconductors UM1 0349 UM10349 2 4 10 2 4 11 2 4 12 2 4 13 Contact smart card reader chips evaluation with CAKE80xx_MBA set_nad This command is used from the application layer in order to specify a SAD source address and a DAD destination address for a logical connection using T 1 protocol as defined in ISO7816 3 The default value is 00 and will be kept until the send NAD command has been notified to the CAKE80XX Any NAD submission where SAD and DAD are identical except 00 will be rejected If bits b4 or b8 of the NAD required are set to 1 VPP programming the NAD will be rejected The NAD shall be initialized before any information exchange with the card using T 1 protocol otherwise and error message will be generated System to CAKE80XX 60 0001 A5 NAD LRC to System 60 0000 A5 LRC Where is the new value of NAD immediately taken into account TDA write i2c This command writes a value on an I C address if a TDA with interface is connected on the board e g TDA8026 The answer from the board is an acknowledge Example System to CAKE80XX 60 0002 2B ADD VAL LRC to System 60 00
12. E M V IFSC 10H or IFSC FFH Wrong TDi TB2 is present in the ATR TC1 is not compatible with CWT IFSD not accepted Procedure byte error Card absent Checksum error All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 11 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx Status code Meaning ATR not supported E0u Card error bad card selected Card clock frequency not accepted after a set clock card command 2 UART overflow Supply voltage drop off 4 Temperature alarm E94 Framing error Serial LRC error At least one command frame has been lost Serial time out UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 12 of 33 NXP Semiconductors UM1 0349 UM10349 Contact smart card reader chips evaluation with CAKE80xx_MBA 2 4 Commands description 2 4 1 2 4 1 1 2 4 1 2 2 4 1 3 General commands send_num_mask This command is used to identify the software version which is flashed in the Cake80xx_MBA CPU For example the current software can be coded as ARMTDA 1 0 TDA8026 The first string represents the firmware name then the version is given and finally the nam
13. TRST gt T 100 nF c32 th C26 TDI gt 4 27 100 nF 33 uF m FH TMS t 1 TCK RTCK TDO gt NRESET gt 1V8 ARM eta LPC2212 R20 R24 R23 R22 R21 R18 10 kQ 10 kQ 10 10 kQ 10 10 kQ 636 038 N2520 6002RB 77 je il VDD VDD LPC2212 mn C49 C50 c51 Js Jm d ipm paces 100 nF I 100 nF I 100 nF nF I 100 nF nF nF Tt nF nF I 100nF 7 014454 Fig 16 CAKE80xx_MBA_01_D Schematic part 3 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 25 of 33 NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx 5 2 Layout x E BSX0087 1 Cuivre Top Fig 17 Layout Top Layer NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx jejejeje 0000 910 910 910 910 910 lem fN 47 BSX008 7 1 Cuivre Bottom Fig 18 Layout Bottom Layer UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 27 of 33 NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx PART T E
14. 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose 6 3 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 29 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx 7 Commands tete Entire E 9 E zug M 10 T TDA8037 22 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 30 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx 8 List of figures Fig 1 Cake80xx MBA 3 Fig 2 Cake80xxMBA evaluation architecture 4 Fig 3 Daughter board Card connector position 5 Fig 4 Daughter boards position 6 Fig 5 Frame 2 7 Fig 6 Frame 2 7 Fig 7 Successful command frame description 8 Fig 8 Unsuccessful command frames 8 Fig 9 Acknowledge
15. 00 2B LRC Where ADD is the address and VAL is the value to write TDA write i2c This command reads a value on an 2 address if a TDA with interface is connected on the board e g TDA8026 The answer from the board is the read value Example System to CAKE80XX 60 0001 2C ADD LRC to System 60 0001 2C VAL LRC Where ADD is the address and VAL is the read value returned Start EMV Loopback These commands launch the EMV Loopback mechanism This is a loop which tries to activate the smart card slot 1 every second If the card activation is success then the EMV loopback starts and the full test is performed automatically At the end the loop restarts trying to activate again the smart card This commands never returns and works by itself It allows passing a full EMV protocol certification without any action from the user But it can display data on the serial link System to CAKE80XX 60 0001 2FLRC to System ASCII DATA All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 19 of 33 NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx 3 Embedded firmware 3 1 The mother board Cake80xxMBA is supplied with a loaded firmware with a protocol interface described in the communication chapter The loaded firmwar
16. 1 2 2 1 1 8 2 2 2 2 1 2 3 2 4 2 4 1 2 4 1 1 2 4 1 2 2 4 1 8 2 4 1 4 2 4 1 5 2 4 1 6 2 4 2 2 4 2 1 2 4 2 2 2 4 2 3 2 4 3 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 4 9 2 4 10 2 4 11 2 4 12 2 4 13 3 3 1 3 2 4 4 1 Board presentation 3 Board 4 Board 5 Power Supply cemeterio 5 Computer connection 5 Daughter boards connections 5 Communication 7 ALPAR Protocol 7 General dialog 7 Successful command 8 Unsuccessful 8 Answer with an acknowledge power off idle mode power down mode 8 05 2 9 General 9 iu 10 Commands description 13 General 13 send num 002 13 Select device ssessssssssssessss 13 check card 13 get reader 14 set serial baud
17. 8029 Fig 7 Successful command frame description 2 1 1 2 Unsuccessful command System to TDA8029 60 XX XX YY nnnnnnnnnnnnnnnnnnnn ZZ ACK length code Data C APDU LRC TDA8029 to System UUUU SS 1 TT NACK length code Status LRC 1 In that case the status contains the error code information see error list Fig 8 Unsuccessful command frames 2 1 1 3 Answer with an acknowledge power off idle mode power down mode System to TDA8029 example power off 60 0000 4D ACK Length code LRC TDA8029 to System 60 0000 4D ACK Length code LRC 1 In the case where the answer is an acknowledge of the command the TDA8029 sends back a frame with the same content of the command Fig 9 Acknowledge frame NXP B V 2014 All rights reserved 8 of 33 All information provided in this document is subject to legal disclaimers Rev 1 0 1 October 2014 UM10349 User manual NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx 2 2 Commands 2 2 1 General commands The following command bytes are available listed in numerical order Table 1 Command summary Command Code Description card_command APDU 00H Sends an APDU to the activated smart card check_pres_card 09H Check the selected card presence send_num_mask Reads the firmware version
18. EPPETPREP S ARM DATA 03 A vail 107 VSS 10 Vss 1 22 ARM DATA 2 Eois 1 3 105 21 DATAQI A P022 CAPO 0 0 104 Mu bes miei P149 7 102 P1 20 P0 24 PO 24 491 2ISCK1 2 S vss 2 100 CAPO_2IMATO_2 EINTO 2 23 D231 10 gg EINTZ RH gt 045 YDP P224 E 11 EN 53 o P2254 D28 15 P3 30 P2 26 D26 BOOTO 1 8150 BLSO PIPESTATO strio VDD 14 95 1 21 RI Plies TRAGEPKT2 5 a4 V7 po 227 D27 BOOTA 16 98 8 2 28 m 17 92 ENTI DODI isp D30 JAIN4 18 LPC2212FBD144 STE can ARM_ADDR 0 3 P2 30 19 90 Bala 031 AINS 44 aol A0 ADDR P0 25 P025 4 t ARM ADDR 1 NC1155 a A2 ADDR AIND CAPO MATO 53 PA TRACEPKT 34 ag 1 DTRI gt gg AIN1 CAPO 2IMATO 2 MAT 0f DSR1 vss a 2 CAP etsi 07 5 26 83 106 P3 29 lt BLS2 AIN6 47 82 PIPESTAT2 za P328 BLS3 AIN7 ai _ADDR 3 WE WE 26 80 Ves P34 50 79 0 8791 2131 105 po 29 AN2 SIMATO 3 7 8 5 Pisia AINS EINTA CAPO O 55 EINTSPWME RXD1 pres 34 75 PWMAITXDI MERO 82 56 74 45 P3 5 P3 24 4 C83 55 73 48 P3 6 5898999139 979955053555995799235959g8RrRB 475 2 e s xr 2112 92
19. Example System to CAKE80XX 60 0002 10 PPFD LRC to System 60 0000 10 70 Where FD is the ratio Fi Di given by TA1 parameter of the ATR and PP is the protocol to be used If the command is acknowledged any subsequent exchanges between the card and CAKE80XX will be made by using the new parameters All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 16 of 33 NXP Semiconductors UM1 0349 UM10349 2 4 6 2 4 7 2 4 8 Contact smart card reader chips evaluation with CAKE80xx_MBA Ifsd request This command is used to send a S IFS request block to the card indicating the maximum length of information field of blocks which can be received by the interface device in T21 protocol The initial size following the answer to reset is 32 bytes and this size shall be used throughout the rest of the card session or until a new value is negotiated by the terminal by sending a S IFS request block to the card In E M V mode the IFSD size is automatically negotiated to 254 just after the ATR has been received System to CAKE80XX 60 0001 0C PAR LRC to System 60 0000 OC 6C Where PAR is the IFSD size set clock card This command is used for changing the card clock frequency The default value is set to FXTAL 4 which is 3 68625 MHz A parameter has to be transmitted in order to choose the card cl
20. FERENC EOMETRY 73757217 35 1000 2 873 872 sw b s 7 836 1000 83 1000 Bouton poussoir CMS 66 __ _ pnsx bar 1 sts 254 bor2md R2 Barrette male droite pas 2 4mm h7mm 2 points cavalier pnsx bar2x10mdi 2 noni con bar 254 2x10 md NC NON rette male droite double rangee 2x10 points Pa 2 m Ms7mm 3 pnis bardatid i Sen ba 254 24 0 Bar2sAFD Barrette femelle droite double ranges 254 points Pas 2 54mm H E Sem exKONTEKA773541109470 prex barzxim i con bar 254 24 Barrette male droite double rangee 298 points Pas 2 Samm Herm prix bar2xSfd 1 4 ton bor 254 2x5 ld Bar2x5FD Barrette femelle droite double rangee 2x5 points Pas 2 54men HB Sem ex KONTEKA773541110470 pns bar2vsmdNC 2 tom bar 254 2x5 md CABLE Barrette male droite double rangee 2x5 points Pac S4mm 7 pnsx bari cav 2 573 574 254 barimd Barrette male droite 2 54mm h 7mm 3 points cavalier D x ICM 3003 8847 NXP 847 Transistor NPN general purpose 4SV 100mA nex 0603 100nf SOV 26 caciscisconcat 0603 1000F Capacite X7R 0603 SOV 10 32 C33 C34 C35 C36 C37 C38 C41 C42 Im scm pnsx_ lt 0603_220nf_25V cia cis 50003 2202 Copacite 0603 25V 10 16 17 pne 0603 22pl 50 4 222305366541
21. UM10349 Contact smart card reader chips evaluation with CAKE80xx Rev 1 0 1 October 2014 User manual Document information Info Content Keywords Abstract TDA Eval board Smart card reader This document describes the way to use the Cake80xx MBA mother board power supply protocols plug of the daughter boards firmware NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx Revision history Rev Date Description 1 0 20141001 First official release 0 3 20131008 Add TDA8037 0 2 20101116 Add EMV Loopback mechanism 0 20090313 Draft Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 2 of 33 NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx 1 Board presentation The Cake80xx MBA is a mother board dedicated to the evaluation of the NXP smart card reader front end devices The following devices are compliant with the mother board TDA8025 with the Cake8025 01 D daughter board TDA8026 with the Cake8026 02 D daughter board TDA8034 with the Cake8034 0X D daughter boards one for each package e TDA8024 with the Cake8024 11 D TDA8024TT
22. and Cake8024 12 D TDA8024T daughter boards TDA8020 with the Cake8020 07 D daughter board TDA8023 with the Cake8023 06 D daughter board TDA8035 with the Cake8035 01 D daughter board e TDA8037 with the Cake8037T and Cake8037TT daughter board VAL Yet EE 01 0 Ji Fig 1 80 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 3 of 33 NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx 1 1 Board architecture The following figure shows how the Cake80xxMBA drives TDA daughter boards Configuration 1507816 management Cake80xxMBA Mother Board Cake TDA Daugher board Fig 2 80 evaluation architecture The TDA8007 on the mother board is used as an ISO7816 UART interface Then the host CPU drives the evaluated TDA directly for the configuration and activation management and through the TDA8007 for the smart card communication data over IO line UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 4 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx 1 2 Board connect
23. art card reader chips evaluation with CAKE80xx 4 Special comments 4 1 Remarks for CAKE8037T and CAKE8037TT Support If you get the Motherboard is not marked CAKE80xx MBA 01 v2 or has a blue sticker on it the quartz Y1 needs to be changed in order to be able to use the CAKE8037T or the CAKE8037TT This is because the TDA8037 can only divide the frequency by 1 or 2 The new quartz Y1 needs to be between 4 and 5 MHz um m Leur m 4 TW ad s ie MAD 1 48 01 0 77 8SX0087 1 Fig 13 Cake80xx MBA UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 22 of 33 NXP Semiconductors UM10349 Contact smart card reader chips evaluation with CAKE80xx 5 Schematic and layout 5 1 Schematic 2 3 TxD 4 2DTR 5 GND 6 DSR 7 RTS
24. co 32 10 lt 33 Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2014 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 1 October 2014 Document identifier UM10349
25. ct smart card reader chips evaluation with CAKE80xx Table 2 X Outgoing commands only Command Code Parameter Description Card extraction AOH These commands are sent as soon as card is inserted or extracted without any command coming from the system These commands use the same operating Card insertion 0 code but the extra parameter gives the additional information The X in the parameter high nibble is the number of the card that has been inserted or extracted Card deactivated XXn 40 The card is deactivated due a hardware problem short on Vcc overcurrent Time out XXH Time out problem on Cake80xx MBA Rx line This command is used in order to warn the host controller that the last communication has broken down time out problem so that the Rx line of Cake80xx MBA does not remain blocked The time out condition is a silence greater than 10 ms in the host command frame Frame lost An unexpected host controller command frame has been received by the Cake80xx MBA while it was busy to process a previous command frame In the last three commands the code value is the previous code value used during a normal exchange 2 3 Error list The error list gives the status code identification and a brief signification of the status error code Table3 List of error codes Status code Meaning 08H Length of the data buffer too short 20H Wrong APDU 21H T
26. de but they do not give TA2 parameter in their answer to reset So the UART has to be set to the right baud rate by means of this specific command which programs the baud rate For non ISO baud rates there is a possibility to increase the capability of the reader by setting the bit CKU which divides by 2 the number of clock cycles of the etu and thus doubles the baud rate of the ISO UART Example System to CAKE80XX 60 0002 0B XXCKU LRC to System 60 0000 OB LRC Where is the value of FiDi if CKU 0 the baud rate is defined by FiDi if CKU 1 the baud rate is 2 the baud rate is defined by FiDi For an etu of 372 clock cycles XX FiDi 0x11 prescaler 31 divider 12 31 12 372 0 Table 6 Supported baudrates As the baud rates in dark boxes are using CKU bit they are not reachable when fxra 1 TA1 CLK ETU TA1 CLK ETU TA1 CLK ETU TA1 CLK ETU TA1 CLK ETU 0x01 372 0x31 744 0x54 186 0x95 32 OxC1 1536 0x02 186 0 32 372 0 55 93 0x96 16 OxC2 768 0x03 93 0x33 186 0x56 46 5 OxA1 768 OxC3 384 0 04 46 5 0x34 93 0x58 124 OxA2 384 4 192 0x08 31 0x35 46 5 0x61 1860 0 192 0xC5 96 0x11 372 0x38 62 0x62 930 OxA4 96 0xC6 48 0x12 186 0x41 1116 Ox63 465 OxA5 48 0xC8 128 0x13 93 0 42 558 0x64 232 5 OxA8 64 OxD1 2948 0 14 46 5 Ox43 279 0x68 155 0xB1 1024 0xD2 1024 0x18 31 0x44 139 5 0x69 93 0xB2 512 0xD3 512 0x21 558 0x48 93 0x91 512 0xB3 256 0xD4 256 0x22 279 0x51 1488 0x92 256
27. e may not be the one described in this file but a previous version If the latest one is required it must be compiled and loaded using the following description The source code of this mother board is available as a MSVC solution provided with an installer Cake80xxMBAFW_setup exe This solution is based on MSVC 20093 for the text editor but as it s an ARM embedded software it uses GNUARM compiler and linker Compiler The GNUARM Compiler can be downloaded from the GNUARM website www nxp com redirect gnuarm com The package that has been used to build the Firmware is the GCC 4 1 toolchain for cygwin http www gnuarm com bu 2 17_gcc 4 1 1 c c _nl 1 14 0_gi 6 5 exe For the project to be built the GNUARM compilers must be installed in the CAGNUARM folder If another folder is chosen then the GNUARM dir in the Build mak file must be updated ArmTDA Microsoft Visual C design Build mak m ni xj Fichier Edition Affichage Projet G n rer D boguer Outils Fen tre 1G SAAS RR AV eS e ip sel suspend Stet 3 Explorateur de solutions ArmTDA X EMWLb c genlib c lib h Serial c Config c Config h Serial h decode c decode h Prot 0 Build mak 4 List of obj to compile d j Uart c a OBJLIST O activate o O Asynclib o 0 buffer o 0 Config o 0 decode o 0 gen 2 Ei Header Files O main o O Prot TO o O Prot Ti o O Serial o 0
28. e of the current used daughter board is displayed System to CAKE80XX 60 0000 OA 6A to System 60 0001 OA 41 52 4D 54 44 41 20 31 2E 30 20 54 4D 41 38 303236 LRC Select_device This command selects the device type plugged with the daughter board When executed this command changes the device to the one chosen and performs an initialization of the microcontroller and the TDA plugged The result of the device switch can be seen in the mask version After the firmware version the used device is displayed The following parameters are used by this command 004 Selects the TDA8026 01 Selects the TDA8025 024 Selects the TDA8034T 5016 package 03 4 Selects the TDA8034HN HVQFN24 package 044 Selects the TDA8020 05 Selects the TDA8023 064 Selects the TDA8024 074 Selects the TDA8035 08 Selects the TDA8037 System to CAKE80XX 60 00 01 67 01 06 to System 60 00 00 67 07 check card presence This command is used to check the presence of a card System to CAKE80XX 60 0000 09 69 to System 60 00 01 09 PRES LRC Where PRES indicates the presence of the selected slot 00 if there is no card 01 if a card is present All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 13 of 33 NXP Semiconductors UM1 0349 UM10349 2 4 1 4 2 4 1 5
29. hips evaluation with CAKE80xx_MBA power_up 3V This command allows activating the card at a VCC of 3V Every signal going to the card will be referenced to this VCC See power up 5V for the other characteristics power up 1 8V This command allows activating the card at a VCC of 1 8V Every signal going to the card will be referenced to this VCC See power up 5V for the other characteristics power off This command is used to deactivate the card whatever it has been activated for or 5V operation A deactivation sequence is processed following the ISO 7816 3 normalization in about 100us System to CAKE80XX 60 0000 4D 2D to System 60 00 00 4D 2D card command APDU This command is used to transmit card commands under APDU format from system to CAKE80XX whatever 0 or 1 protocol are used Short or extended commands see limitations in 8 1 can be used An answer to such a command is also made in APDU format from CAKE80XxX to the system Example System to CAKE80XX 60 0007 00 00A40000024F 00 8E to System 60 0002 00 9000 F2 negotiate This command is used to make a PPS Protocol and Parameter Selection to the card if in its ATR the card proposes a different Fi Di or 2 different protocols By using this command a PPS will be made to the card with the Fi or Di and protocol type entered as a parameter PP It is up to the host to make the correct Fi Di submission to the card
30. ions The Mother board must be supplied and connected to the host to be used 1 2 1 Power supply The power is supplied through the Jack connector J12 This board must be supplied with 5V On the Jack connector the 5V must be inside the connector while the ground is on the external connection 1 2 2 Computer connection The connection to the computer is made through an RS232 straight serial cable connected on J5 1 2 3 Daughter boards connections The daughter boards must be plugged on the HE10 connectors J1 to J4 The daughter boards must always be placed so that the main smart card connector is available from the side opposed to the RS232 connector as shown in the next figure Power Supply RS232 Cake80xx MBA Main card insertion Fig 3 Daughter board Card connector position With respect to this card connector position the following figures give the position of the different daughter boards UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 5 of 33 NXP Semiconductors UM10349 Contact smart card reader chips evaluation with CAKE80xx Power Supply RS232 Cake8026 Cake8023 Cake8020 Cake80xx MBA Main card insertion a Cake8026 connection Fig 4 Daughter boards position Power Sup
31. ng of the transmission line between the host controller and CAKE80XX CAKE80XX to System 0001 6F FF 71 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 14 of 33 NXP Semiconductors UM1 0349 UM10349 Contact smart card reader chips evaluation with CAKE80xx_MBA 2 4 2 power up commands 2 4 2 1 There are three different power up commands 5V 3V 1 8V Two of them power up 3V and power up 5V have to be followed by a parameter 00g indicates that all the parameters of the ATR of the card compliant with 1507816 3 will be taken into account 01 indicates that only the ATR of cards whose parameters are inside the E M V 4 2 specification scope will be taken into account cards having an ATR which does not comply with E M V 4 2 requirements will be rejected power up 5V This command allows activating the card at a VCC of 5V All the signals going to the card will be referenced to this VCC An activation sequence is processed following the 507816 3 normalization VCC is rising I O is enabled CLK is started and RST is processed If the card answers to this command the answer will content all the ATR parameters these parameters are memorized in CAKE80XX and will be taken into account during the whole card session till the card is deactivated or till warm reset is processed The structure of the ans
32. nt is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 28 of 33 NXP Semiconductors UM10349 Contact smart card reader chips evaluation with CAKE80xx 6 Legal information 6 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 6 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might inc
33. ock frequency System to CAKE80XX 60 0001 11 PAR LRC Table 5 set clock card parameter Based on a crystal with a frequency equal to 14 745MHz Frequency Parameter Fxtal 14 745MHz 00 Fxtal 2 7 37MHz 02 Fxtal 4 3 68MHz 04 Fxtal 8 1 84MHz 06 After a card clock frequency change all the waiting times are internally set to the new value Before applying the requested clock the compatibility of the frequency with the current Fi used by the card is checked as described in 507816 3 For example if the card has answered in its ATR a Fi parameter of 372 or 558 fmax lt 6MHz a change of the card clock frequency to Fxtal 14 745MHz or Fxtal 2 7 37MHz will not be processed and an error status will be sent to the application card take off and card insertion These two commands are sent directly to the system processor as soon as a card extraction or insertion has occurred CAKE80XX to System 60 0001 AO 10 Ci for a card 1 extraction 60 0001 0 11 CO for a card 1 insertion All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 17 of 33 NXP Semiconductors UM10349 Contact smart card reader chips evaluation with CAKE80xx 2 4 9 set card baud rate This command is used mainly for cards which are not fully ISO 7816 3 compliant with specific and negotiable modes As a matter of fact some cards are in specific mo
34. of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or UM10349 All information provided in this document is subject to legal disclaimers customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an a
35. oo short APDU 22H Card mute now during T 1 exchange 24u Bad NAD 25H Bad LRC 26H Resynchronized 27H Chain aborted 29H Overflow from card 30H Non negotiable mode TA2 present 31H Protocol is neither T 0 nor T 1 negotiate command 32H T 1 is not accepted negotiate command UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 10 of 33 NXP Semiconductors UM10349 UM10349 Contact smart card reader chips evaluation with CAKE80xx_MBA Status code 33H 34H 35H 38 39H 404 55H 80H 81H 83H 844 864 884 894 8Bu 8 924 934 944 954 964 974 984 994 C3u Meaning PPS answer is different from PPS request Error on PCK negotiate command Bad parameter in command absent PPS not accepted no answer from card Early answer of the card during the activation Card Deactivated Unknown command Card mute after power on Time out waiting time exceeded 4 parity errors in reception 4 parity errors in transmission Bad FiDi ATR duration greater than 19200 etus E M V CWI not supported E M V BWI not supported E M V WI Work waiting time not supported E M V TC3 not accepted E M V Parity error during ATR Specific mode byte TA2 with b5 byte 1 TB1 absent during a cold reset E M V TB1different from 00 during a cold reset
36. ply RS232 Cake8034 Cake8025 Cake8024 Cake8035 Cake8037 Cake80xx MBA Aa Main card insertion b Cake8034 or Cake8025 connection The Cake8034 and Cake8024 use only two connectors J2 is a 10 pins connector while the other J1 to J3 are only 8 pins e Cake8025 Cake8035 and Cake8037 use J2 and J4 as well but only the 8 lower pins of J4 are needed Cake8026 Cake8023 and Cake8020 must be plugged on the 4 connectors J1 to J4 UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 6 of 33 NXP Semiconductors UM1 0349 Contact smart card reader chips evaluation with CAKE80xx 2 Communication UM10349 2 1 ALPAR Protocol 2 1 1 The communication between the host controller and the Cake80xx_MBA obeys to a protocol named ALPAR This protocol encapsulates the useful data of a message in an invariant frame structure and defines a dialog structure of messages exchanges Data is exchanged between the host controller and the mother board in blocks each made up of binary characters on one byte 4 header characters 0 to 506 data characters C APDU or R APDU 1 LRC character 4 bytes 0 to 506 bytes 1 byte Header C APDU or R APDU LRC Information field Fig 5 Frame structure
37. s is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5
38. startup o 0 Uart E 2104i2c h 50 8026 0 2104i2c o 0 T8023 0 0 8020 0 O EMVl1b o EN types h E common h Tools PATH E Config h GNUARM DIR C GNUARY E decode h GNUARM VER 4 1 1 E EMVIb h E ib h Files PATH 2 2 8 Serial h O obj Ha startup s 5 BINDIR iGNUARM DIR Yibin T8026 h CC BINDIR Varm elf gcc m tdalib h CL BINDIR 3arm elf 1d E Uart h OC BINDIR Narm elf objcopy Ej 3 Resource Files s arm In OUTFILE ArmTDA E x Build mak 11 gt Fig 11 Build mak Compiler path UM10349 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 20 of 33 NXP Semiconductors U M1 0349 Contact smart card reader chips evaluation with CAKE80xx 3 2 Loader Once the Firmware has been built it can be loaded using LPC2000 Flash Utility which can be downloaded from the NXP website http www nxp com documents other Ipc2000 flash isp utility zip The loader must be configured as follows 5 LPC2000 Flash Utility 15 xl File Buffer Help PHILIPS LPC2000 Flash Utility V2 2 0 r Flash Programming Erase Blank Communication Filename Connected To Port rs Cake80xxMBAF itmware obj AmT DA Hex c Blank Check Entire Device
39. ur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation
40. wer is the following System to CAKE80XX 60 00 01 6E 01 OF AC Length code E M V LRC K to System 60 XX XX 6 nnnnnnnnnnnnnnnnnnnn 27 AC Length code ATR parameters LRC K Fig 10 power up 5V frame exchange If the card is in specific mode CAKE80XX will process the next command directly using the new interface parameters of this specific mode If the card proposes a different Fi Di in the ATR than the default value Fi Di 372 it is up to the application to make a PPS command by using the negotiate command If the card proposes 2 different protocols in its ATR it is up to the application to make a PPS command by using the negotiate command If the card does not answer to the reset a status giving an error code is returned to the application In the case of E M V compliant power up if the card is using 1 protocol just after having received the ATR sends an IFSD request to the card indicating that the reader can manage a data buffer of 254 bytes FEH The power up 5V command can be used to generate a warm reset if the card is already activated All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 0 1 October 2014 15 of 33 NXP Semiconductors UM1 0349 UM10349 2 4 2 2 2 4 2 3 2 4 3 2 4 4 2 4 5 Contact smart card reader c

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