EVBUM2159 - NCP3120-23 2 A/3 A HF Buck Evaluation
Contents
1. I Protection SEQ1 1 SHDN 1 Power AVIN Sequencing 1 STAR TU P ref 0 8V UVLO Reference l TH ER MAL 0 8V SH U TD OWN pu SHDN1 SHDN2 L GND 2 SHDN 2 SS 2 id Soft Start amp Tracking Control MIX j Nee A e om ot A or uo e ce et In rtt icm m I TRAGK 2 HS protection 2 FB2 E d 0 5V Overload Protection 180 COMP 2 L END S Error Amplifier e CON TR OL bes LOGIC 2 I FB2 SW2 PG2 pg 2 Delay 0 9 re OS yaq Falling comp SHDN 2 Figure 10 NCP 3120 Block Diagram http onsemi com 6 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB Table 2 PIN DESCRIPTION Symbol 1 31 32 Swi VIN N N 8 10 SW2 GND2 SS2 COMP2 AGND FB2 109 H 00 TRACK 2 N TRACK 1 cO SEQ2 N O EN2 SEQ1 N N m N1 PG2 N Co N BA PG1 N al z N O FB1 AGND COMP1 N N NI N N wech wech l A CH O O N 00 cO Se 2 GND1 Exposed Pad GND C NCP3123QPBCKGEVB Description Switch node of Channel 1 Connect an inductor between SW1 and the regulator output Input power supply voltage pins These pins should be connected together to the input signal supply voltage pin Switch node of Channel 2 Connect an inductor between SW2 and the regulator output Power ground for Channel 2 Soft start control input for Channel 2 An internal current source charges a2. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 K f Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2159 D
3. 000 Y ofst 6 000 Y ofst 1 00MS S0MSisfEdge Negative LeC LeC roy 2 13 2008 5 06 38 PM roy 2 13 2008 5 11 11 PM Figure 18 Ratiometric Startup of Voutij2 with Power Good Outputs CH1 Vouti CH2 Vouto CH3 PG1 CHA PG2 File Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help C4 Setup i i i i L H i i i imebase 0 00 us 10 0 Vidiv 10 0 Vidiv 500 mAfdiv 500 mA div ALIIS LUI Stop BIM 21 00 offset 30 80 V ofst 310 mA ofst 510 mA ofst 100k5 5 0GSisfEdge Positive LeCroy 2 15 2008 9 25 05 AM Figure 19 Switching Waveforms Showing 180 Phase Shift Operation CH1 Vsy4 CH2 Vswo CH3 1 4 CH4 IL http onsemi com 10 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB PERFORMANCE INFORMATION Continued Hiccup Overload Protection When the NCP312x detects an overload condition FB The NCP312x uses hiccup mode protection to protect the voltage falls to 0 5 V switching stops the soft start power supply from damage during overload conditions capacitor is discharged to 0 1 V and again charged to 1 V During normal operation the external soft start capacitor is The output of the error amplifier is also tied to ground pulled up by a current source that delivers 10 uA to the SS output transistor is closed during the soft start capacitor pin capacitor This current source continues to charge the discharge If the output voltage is s
4. ees JP16 Soft start 2 capacitor enable JP7 Tracking 1 ref level must connect pins 2 3 for normal operation JP8 Tracking 2 ref level must connect pins 2 3 for normal operation connect 1 2 for Tracking function see the configuration table Table 4 CONFIGURATION OF JUMPERS Normal Operation Enable from Vin Enables are Driven from an External Sources pz qoe qne Enable 1 is Driven from Vin Channel 2 is Disabled Sequential Sequencing Enable from Vin Enable 1 is Driven from an External Source Enable 2 is a SLAVE of Enable 1 la a res Lo alitas a Le Le T Y r Esa Internal Tracking CH1 is MASTER CH2 SLAVE Enable from Vin Enable1 is Driven from External Source Enable2 is Connected with Enable1 EA j E A i LL ON Semiconductor and ON are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all l
5. B NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB PERFORMANCE INFORMATION Continued Vertical Timebase Trigger splay Cursors easure Math Analysis Utilities Help C4 ase Trigger splay Cursors easure Math Analysis Utilities Help Vo ee AH 5 p 4 Timebase Oys Trigger KITO Stop 880 mA ETE d Stop 880 mA 200 mV div 1 00 Aldiv 200 midi 1 00 Ardiv 390 0 my 2 990 A ofst 100MS SOOMS sfEdge Positive 390 0 mv 2 990 A ofst 1 00MS 500 MSisfEdge Negative LeCroy 2 12 2008 11 35 34 AM LeCroy 2 12 2008 11 35 47 AM Figure 15 Load Transient Vouti Vin 12 V lout 200 mA to 2 A to 200 mA CH1 Vouti CH4 lout imebase 0 us Trigger vertical Trigger Display Cursors Measure Math Analysis Utilities Help Ga File Vertical Trigger Display Cursors Measure Math Analysis Utilities Help AA tp tp tt tt tt ttt tt KA KA F s andante A rigger rigger 200 mV div 1 00 Afdiv EN 880 mA 200 mV div 1 00 Afdiv 200ps div Stop 880 mA 270 0 mV 2 990 A ofst 1 00MS SOOMS sfEdge Positive 270 0 mV 2 990 A ofst 1 00MS SOO MS sfEdge Negative LeCroy 2 12 2008 1 12 17 PM LeCroy 2 12 2008 1 12 08 PM Figure 16 Load Transient Voute Vin 12 V lout 200 mA to 2 A to 200 mA CH1 Vous CH4 loui Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help 52 File Ve
6. BRS360 IC1 1 Dual 2 A S A NCP312x QFN32 Switching Regulator Note 2 5x5 mm 200 750 kHz 200 2 200 kHz JP1 JP2 4 3 Pin 3 Pin 2 54 JP7 JP8 JP3 JP4 12 RM 2 54 mm PCB Jumper 2 54 JP5 JP6 pin s PCB pin s JP9 JP10 JP11 JP12 JP13 JP14 JP15 JP16 Jumper Jumper RM Jumper 2 54 2 54 mm H3 R4 2 Resistor 1 1206 Note 5 M BE B Plastic Plastic distance L 5 mm Distance Connecting 17 Connecting external Ext Points points 2 x 0 1 2 3 Manufacturer Substitution Lead Part Number a an VISHAY RCAT206240KFKEA 206240KFKEA ER AN RCA1206100ROFKEA E SES ven EGO je wee reren ee ON Semiconductor MBRS240LT3G MBRS340LT3G MBRS360LT3G Z o NCP312xMNTXG Note 2 o O 5 o ON Semiconductor 5 o 5 o 5 o 3 2A40 V NCP3120 amp NCP3122 3 A 60 V NCP3121 3 A 40 V NCP3123 4 SMB NCP3120 amp NCP3122 SMC NCP3121 amp NCP3123 5 Not used positions http onsemi com 12 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB TEST PROCEDURE FOR THE NCP312x EVALUATION BOARD SS a ON Semicanmductor NCP312x v2 14 Evaluation Boerd geep Lef ae e CN SHA GENE EN AGND n JILDE NEE REE w Si ue E ml wa a pis ED pio cas P1 Er Ij cd P id u sEG1 1 H ANI a N A kad e KA EE 3 ERD OO d Zu ONO 9 AGND P Figure 22 Test Setup The following steps detail the test procedure for all th
7. NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB NCP3120 23 2 A 3 A HF Buck Evaluation Board User s Manual Circuit Description The NCP312x operates as a voltage mode pulse width modulated PWM asynchronous buck converter Its operating frequency is adjustable with an external resistor to ground from 220kHz to 750 2 200 kHz minimum switching frequency of 220kHz and a maximum Table 1 EVALUATION BOARD SPECIFICATION Characteristic Input Voltage Output Voltage Oscillator Frequency Enable Threshold High EN Tied to SEQ Sequence Threshold Low EN Tied to SEQ Voltage Ripple Voutt Vout2 V Load Regulation out1 Vin 10 8 13 2 V lout 2 A Thermal Shutdown Dual 2 A 3 A DC DC Converter Dimensions Line Regulation 1 Operation down to 4 5 V requires selecting a lower voltage for Man Semiconductor Components Industries LLC 2012 November 2012 Rev 1 ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL 750 2 200 kHz Also an onboard operational transconductance amplifier OTA integrates the error signal to provide high DC accuracy The NCP312x also includes an enable and disable function with externally controlled soft start and stop Outlined Area Publication Order Number EVBUM2159 D NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB We Semiconductor Eo A NCP3121 v2 di Tq ch KM MG ors d e Lummr y CF SE
8. Q2 x 94 fe TRACK2 AGND e f TRACK 4 Pi E e E i ad ds o pim a H POS ue ra Figure 3 NCP3122 2A HF Buck Evaluation Board Figure 4 NCP3123 3A HF Buck Evaluation Board http onsemi com 2 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB BOARD DETAILS Figure 5 Top Layer Figure 6 Bottom Layer C15 C16 P ON Semiconductor TUE L JR3 Ho Lio CICI E E a C19 Cn NCP3120 Ver 1 0 Dual Output 2A Regulator Reference Design Figure 7 Silkscreen Layer http onsemi com NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB QNO DCH STI L sy E gdf q pide i j c Zar _ n C t QN9V sm A DovaL CHOVYL cdf Figure 8 Schematic for the NCP3120 Buck Evaluation Board http onsemi com NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB LONS ONE LdNOD ONDY g 3 NIAY GIN9V UN9V OND lt ON lt Figure 9 Schematic for the NCP3121 NCP3122 and NCP3123 Buck Evaluation Boards http onsemi com NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB 0 1 ref Falling comp SHDN 1 PGI HS protection 1 lt a VIN COMP 1 L Ea Ir CON TR OL He LOGIC 1 SW 1 GND 1 NY ss1 L Soft Start amp Tracking Control TRACK 1 LJ FB1 1 AVIN We Signal 0 5V Voltage RTL Overload CT AGND
9. d to an external pull up resistor Input signal supply voltage pin Feedback Pin Used to set the output voltage of Channel 1 with a resistive divider from the output Analog ground Connect to GND1 and GND2 Compensation pin of Channel 1 This is the output of the error amplifier and inverting input of the PWM comparator Soft start stop control input for Channel 1 An internal current source charges an external capacitor connected to this pin to set the soft start time Power ground for Channel 1 The exposed pad at the bottom of the package is the electrical ground connection of the NCP312x This node must be tied to ground http onsemi com 7 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB PERFORMANCE INFORMATION The following Figures show typical performance of the NCP312x in this evaluation board 90 10 NEN Vin A Y CS 85 Z ZN gt 80 gt Z Z f O O LL LL LLI LLI 70 0 02 04 06 08 10 12 14 16 1 8 2 0 0 02 04 06 08 1 0 1 2 14 16 1 8 2 0 lout A lout A Figure 11 Efficiency for Voy 3 3 V Figure 12 Efficiency O Vouto 5 V j lt gt ll O N lt qe VERNE MANE EEE ij Er AEEA FACIE COREE LENIE VIL IRR nr III EE EO III OEI eegen el l 3 B bee In lout A lout A Figure 13 Load Regulation vs Vin for Vouti 3 3 V Figure 14 Load Regulation vs Vj for Vout 3 3 V http onsemi com 8 NCP3120QPBCKGEV
10. ese boards NCP3120 NCP3121 NCP3122 and NCP3123 Required Equipment Current limited DC Power Supply e g AGILENT 6653A Ipc DC Volt Meter able to measure up to 15 V DC e g KEITHLEY 2000 3pcs DC Amp Meter able to measure up to 2 A DC e g KEITHLEY 2000 3pcs DC Electronic Load e g AGILENT 6060B 2pcs Test Procedure 1 Make sure if the red ringed jumpers are placed Figure 22 Connect the test setup as shown in Figure 22 Disable loads 0 A Apply an input voltage ViN 12 V DC Check if Vouri 5 V DC Vout 3 3 V DC Enable loads up to 2 A 3 A for the NCP3121 NCP3123 Buck Evaluation Boards Z Check if Vouri 5 V DC VOUT2 3 3 V DC 8 If yes test passed successfully 9 Power down the load 0 1 DU BW WN Power down Vin End of test http onsemi com 13 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB CONFIGURATION OF JUMPERS JP1 Enable Disable 1 st Channel pins 2 3 enabling 1 2 JP9 Internal Tracking 2 Enable disabling the channel 1 JP10 Internal enable 1 of Master voltage Soft start 2 JP2 Enable Disable 2 nd Channel pins 2 3 enabling JP11 Internal enable 2 of Master voltage Soft start 2 1 2 disabling the channel 2 JP12 External enable of Master voltage Soft start 1 JP5 SEQ1 EN2 JP13 External enable of Master voltage Soft start 2 JP4 EN2 SEQ2 JP14 Track1 Track2 JP5 EN1 SEQ1 JP15 Soft start 1 capacitor enable Hn iret
11. iability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner
12. n external capacitor connected to this pin to set the soft start time Compensation pin of Channel 2 This is the output of the error amplifier and inverting input of the PWM comparator Analog ground connect to GND1 and GND2 Feedback Pin Used to set the output voltage of Channel 2 with a resistive divider from the output Resistor select for the oscillator frequency Connect a resistor from the RT pin to AGND to set the frequency of the master oscillator Tracking input for Channel 2 This pin allows the user to control the rise time of the second output This pin must be tied high in the normal operation except in the tracking mode Tracking input for Channel 1 This pin allows the user to control the rise time of the first output This pin must be tied high in the normal operation except in the tracking mode Sequence pin for Channel 2 I O used in power sequencing Connect SEQ to EN for normal operation of a standalone device Enable input for Channel 2 Sequence pin for Channel 1 I O used in power sequencing Connect SEQ to EN for normal operation of a standalone device Enable input for Channel 1 Power good open drain output of Channel 2 Output logic is pulled to ground when the output is less than 9096 of the desired output voltage Tied to an external pull up resistor Power good open drain output of Channel 1 Output logic is pulled to ground when the output is less than 9096 of the desired output voltage Tie
13. rtical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help P1 C1 vs n A 9 SN A q AAA 4 Measure P1 freq C4 P2 freq C3 Measure P1 freq C4 P2freq C3 value 301 7680 kHz 301 9086 kHz value 302 0283 kHz 302 0087 kHz status A status Y Y rigger rigger 50 0 mVidiv 50 0 mVidiv 20 0 Vidiv 20 0 Vidiv 2 00 usidiv Stop 8 8 v 5 00 Vidiv 5 00 Vidiv 2 00 usidiv Stop 8 70V 150 0 mv 70 0 mv ofst 8 00 V offset 72 00 V ofst 100kS 5 0GS s Edge Positive 3 00 V offset 17 60 V ofst 100kS 5 0GSisfEdge Positive LeCroy 2 8 2008 12 43 29 PM LeCroy 2 8 2008 11 30 12 4M Figure 17 Switching Waveforms Vout1 Vout2 New Vswo CH1 Vouti CH2 Mou CH3 Vsw1 CHA Vswo http onsemi com 9 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB PERFORMANCE INFORMATION Continued File Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help C4 Setup File Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help C4 Setup mi Ir ca i i i x i i i i i i i i i i i i i i imebase 3 12 ms imebase 3 12 ms 2 00 Vidiv 2 00 Vidiv 2 00 Vidiv 2 00 Vidiv 2 00 mid Stop 1 44 V 2 00 Vidiv 2 00 Vidiv 2 00 Vidiv 2 00 Vidiv 2 00 msidiv Stop 242 V 2 000 V offset 2 000 Y ofst 6 000 Y ofst 6 000 Y ofst 1 00MS S0MSisfEdge Negative 2 000 V offset 2 000 Y ofst 6
14. till below the overload soft start capacitor until it reaches the saturation voltage of condition voltage 0 5 V the cycle repeats as shown in the current source typically 4 V Figure 20 load or SS1 fout l drv Load Control Voltage Output Voltage Output FET Driver Figure 20 Hiccup Overload Protection Description Vin 12 V File Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help c3 Setup E 2 s t e m ee ee sss kas w mmm D i21 I cd 1 imebase 600 ys 2 00 Vidiv 2 00 Vidiv 2 00 A div 2 00 A7div 10 0 ms div Stop 960 mV 4 200 V offset 4 000 V ofst 1 500 A offset 8 000 A ofst 1 00MS 10MS s Edge Negative 4 94 Y 2 24 A 726A LeCroy 2 15 2008 10 45 54 AM Figure 21 Switching Waveforms Showing Hiccup Overload Protection CH1 Vsw1 CH2 Vsw2 CH3 TET CH4 l 2 http onsemi com 11 NCP3120QPBCKGEVB NCP3121QPBCKGEVB NCP3122QPBCKGEVB NCP3123QPBCKGEVB Table 3 BILL OF MATERIAL FOR THE NCP312x EVALUATION BOARD Note 2 JON R14 Resistor 100 Q 1 1206 R24 ME OO C1 C15 Ceramic Capacitor 22 uF 10 1210 C25 C2 C3 4 Ceramic Capacitor 100 uF 10 1206 C11 C21 LD1 LD2 LED Diode Green LED 3 mm NA 3 mm D11 D21 2 Low Vf Schottky MBRS240 SMB SMC Rectifier Note 3 MBRS340 Note 4 M
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