USB3FPGA
Contents
1. o 82 3 oe a we cee RESERVED BB E 5 22 z 3 s 8 1 On x RT n P51 e ay pata ca PWR P 109 P108 P48 ca l7 0 ug O r12 0 Orno 0 C p450 Ors T r115 0 Gers reon T P118 0 Opie r400 ps3 USB2 0 T USB2 0 Pi2O Ons 560 D rss Controller P123 P122 m zie r340 DJ P33 T P126 P124 O 621 n T D 28 Gre d r300 Ore O3 1 ug e r12 0 piso SPARTAN 3E 28 i 38 P132 FPGA c rzBpngsslr 30 DUD T P1340 OP135 um P20 Ors En O P136 DO E Dens O r138 0 xx C ro Ors CONFIG P1400 B P140 Oris LED P140 2 P146 DJ OOFr9 hiai 000 ak onse Da a P151 fj zoeb5 s255zg 00 D STERRE FERRIE o0000 o D Lesanoonscososancaoco eo ee MM f a E n CC E c rr gt J4 m C du LEDA PWR Figure 2 USB3FPGA connector diagram Attention2. USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 B8 preliminary FPGA lt gt Memory interface SRAM signal name FPGA pin number RAM_A4 FPGA Pin 202 RAM A5 FPGA Pin 200 RAM A6 FPGA I O Pin 197 RAM A7 FPGA I O Pin 193 RAM A8 FPGA Pin 190 RAM A9 FPGA I O Pin 187 RAM A10 FPGA I O Pin 171 RAM A11 FPGA I O Pin 167 RAM A12 FPGA I O Pin 164 RAM A13 FPGA I O Pin 162 RAM A14 FPGA I O Pin 160 RAM A15 FPGA I O Pin 161 RAM_A16 FPGA I O Pin 163 RAM_A17 FPGA I O Pin 165 RAM_A18 FPGA I O Pin 168 RAM A19 FPGA I O Pin 172 RAM DO FPGA I O Pin 150 RAM D1 FPGA I O Pin 151 RAM_D2 FPGA Pin 152 RAM_D3 FPGA I O Pin 153 RAM_D4 FPGA I O Pin 144 RAM_D5 FPGA I O Pin 145 RAM_D6 FPGA Pin 146 RAM_D7 FPGA I O Pin 147 RAM_D8 FPGA Pin 203 RAM_D9 FPGA I O Pin 5 RAM_D10 FPGA I O Pin 8 RAM_D11 FPGA I O Pin 9 RAM_D12 FPGA I O Pin 2 RAM_D13 FPGA I O Pin 3 RAM_D14 FPGA I O Pin 4 RAM_D15 FPGA I O Pin 205 RAM_WE FPGA I O Pin 178 USB3FPGA C 1030 2805 User Manual V 1 41 B9 www cesys com preliminary FPGA lt gt Memory interface SRAM signal name FPGA pin number RAM_OE FPGA I O Pin 179 RAM_CE FPGA Pin 180 RAM_BLE FPGA I O Pin 177 RAM_BHE FPGA I O Pin 181 Undocumented FPGA IO pins that are not documented are reserved for USB communicat
3. Install from a list or specific location Advanced press Next In the second dialog select the first option Search for the best driver in these location and include only the second option there Include this location in the search Then press Browse and select the drivers folder which is included in the source package that ships with our board press Next Windows will try to install the driver now for security reasons it will ask the user to allow this via another dialog box you have to select Continue Anyway here Finish the installation by pressing Finish in the next dialog box the loader driver is installed now Because the used USB chip needs a two step driver loading mechanism Windows will now pop up another dialog which informs the user about a new hardware detection To install this second driver follow the installation instructions for first driver step by step this will be exactly the same After finishing the installation for the second driver the device should work correctly To verify the installation have a look in the device manager expand the Universal Serial Bus controllers tree and look for a device named Cesys USB3FPGA compatible device In addition start the diagnostic tool which is located in the bin folder in our source USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C 1 preliminary package and try the memory test and benchmark options there How this works is describ
4. until the software has called SetConfiguration Most PC s ignore this restriction but some USB hubs measure the current flow and will report a shortcut condition when a USB device draws more than 100 mA immediately after it has been plugged The option software controlled keeps the FPGA the SRAM and the Pins on CON1 A3 B3 C3 powered off until SetConfiguration was called As long as the FPGA is not powered its I O pins must be held low 0 3 Volt Attention When you use software controlled power on behaviour make sure no FPGA I O pin is driven as long as the FPGA is not powered J4 Optional power sequencing Pin 1 2 All power supplies will ramp up as soon as 5 Volt are attached Pin 2 3 Software controlled power on At startup only FX2LP power supply will ramp up Only after the attached USB host grants more than 100mA 2 will enable power up of other onboard power supplies USB 2 0 interface The USB 2 0 interface of the board is implemented using an USB controller outside the FPGA Therefore FPGA designs do not need to include USB specific code Developers do not need to know details about the USB bus To enable communication between the FPGA and a program running on the PC a easy to use API and VHDL sample code come with the board If your design works stand alone and does not require any communication with the PC you may ignore the USB interface details and use it on
5. Int32 ceFPGA SaveBin String sFileName Info Save design in bin format smaller and faster loading via LoadBin Returns Error Code Errors 2 OF no error E OPEN can t open file E PAD no design to save call one of the Load methods first C HRESULT ceFPGA SetBin uchar pucData uint uiSize NET Int32 ceFPGA SetBin Byiel pucData wink uwisize Info Set design based on the binary equivalent given by pucData with size uiSize Returns Error Code Errors o DE no error E OUTOFMEMORY not enough memory available class ceAsyncHandle This class is a helper class for async operations It holds all necessary informations about an active transfer in background and is needed for completion The methods of this class are designed to help to detect transfer finishing C ceAsyncHandle ceAsyncHandle NET ceAsyncHandle ceAsyncHandle Info Class constructor Returns Errors C ceAsyncHandle ceAsyncHandle NET ES Info Class destructor Returns Errors USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C18 preliminary C HRESULT ceAsyncHandle IsComplete bool pbComplete NET Tats ceAsynoHandle TsComplete ret Boolean bComplete Info Check if the attached operation is completed pbComplete bComplete will be true if this is done Returns Error Code E
6. The Testpin numbering printed on the PCB v1 0 is not correct in the area marked above This error has been fixed in PCB v1 1 This document is correct USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 B2 preliminary Board dimensions 100 94 42 5 58 mm ames RAE LEA P ale e Figure 3 USB3FPGA board dimensions Power supply The USB3FPGA can be configured to be self powered or bus powered The default setting is bus powered This means power is provided by the USB bus If the USB3FPGA is the only device on the USB bus most computers should allow a maximum current of about 500 mA This may not be true for notebooks J1 Power source select Pin 1 2 Self powered External 5 Volt power supply must be attached to connector CON1 Pin 2 3 Bus powered USB power supply USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 B3 preliminary The option self powered requires an external power supply connected to Use this method if your design draws more current than your USB bus can deliver Attention Be careful when using the external power connector If you apply more than 5 5 Volts or if you reverse the polarity the board will permanently fail and may not be reparable Directly after the USB3FPGA board is connected to the USB bus it must not consume more then 100mA This is the current limit defined by the USB standard
7. rel i gt apo Tiro re epo Tiro Cete gt app tirto data apo tito emoty gt yep Firo emoty apo tito rel COUME gt apo Liro _wel_CouMeE aga talb sort kg iaa al gt aga wislo short keo tan debug gt open regio rerireadi process app adr gp reg begin app datai lt others gt 0 for i in 0 to 3 loop if i TO INTEGER unsigned app adr 1 downto 0 then app datai lt gp seg 1 F end if end loop end process USBS3FPGA C 1030 2805 www cesys com User Manual V 1 41 D5 preliminary USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 preliminary USB3FPGA 1030 2805 www cesys com User Manual V 1 41 D7 preliminary E Additional information Newsgroups There are several newsgroups that discuss FPGA and VHDL related themes Two of them are comp arch fpga comp lang vhdl Links For further information about FPGA and VHDL may be found through links located on CESYS website www cesys com Books VHDL Design Representation and Synthesis James R Armstrong F Gail Gray Prentice Hall ISBN 0 13 021670 4 USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 E 1 preliminary F Table of contents ARE WU MTA pta vane es Summary f LESESEETS oa ey ae 1 FeattreliSt ose ence coat
8. start again with one or more Init calls This forces a reenumeration of all devices Attention This invalidates all pointers you get from the API How to communicate with devices If the API is initialized correctly you can retrieve the count of available devices by calling the static member function GetDeviceCount from class ceDevice To access one of the devices call function GetDevice from the same class and use an index in range of 0 lt index lt GetDeviceCount to specify one of the devices The pointer returned by this function is constant and valid until you call Delnit the same call will return the same pointer so you do not have to store this pointer anywhere All communication with the device is done using this class pointer Before any data can be sent or received the device must be opened To do this call method Open which internally opens the device set default parameters and retrieves some information about the device After a successful call to this function you can do those things descriptions below Configure device SetGPIFSpeed Retrieve information Getlnfo Download FPGA designs ProgramFPGA Read and write FPGA registers ReadRegister WriteRegister Read and write huge blocks of data ReadBulk WriteBulk Read and write parts of the EEPROM ReadEeprom WriteEeprom To properly finish the use of the device call Close Function description method
9. the last error occurred in the firmware This may help to find out unexpected errors Returns Firmware error code Errors C HRESULT ceDevice Open NET Int32 ceDevice Open Info Opens the device Returns Error code Errors SOIN no error S FALSE device already open E FAIL error retrieving information from driver E OPEN failed to open device C HRESULT ceDevice ProgramFPGA ceFPGA pFPGA NET Int32 ceDevice ProgramFPGA ceFPGA pFPGA Info Downloads a FPGA design to the device This should be the first step after opening the device Without a running design the hardware won t do anything Returns Error code Errors 2 DES no error E OPEN device not open E FAIL call to driver falls E INVALIDARG invalid design B MOPIPE no matching pipe found E FPGA INTTS init pin doesn t switch E FPGA NC fpga not configured USB3FPGA C 1030 2805 User Manual V 1 41 www cesys com 10 preliminary Goren HRESULT ceDevice ReadBulk uchar pucData uint uiSize uint amp uiTransfered ceAsyncHandle pH Mint ULPipe uine nicimeout NET Int32 ceDevice ReadBulk Byte pucData UInt32 uiSize ref UInt32 uiTransfered ref ceAsyncHandle pH UInE32 naPipe UImnt3S2 uiTimecut Info This function should be used to transfer huge blocks of data from device to host It is able to work in sync or async mode depending on the given parameters Parameter pucData s
10. the test either success or failure The Benchmark button shows a list of 3 different benchmark options Read Write Read and Write After choosing one of these options the log window disappears and the benchmark graph pops up The blue graph line shows the unchanged value of bytes per second transferred between PC and device while the purple line shows an averaged value Benchmarking can be stopped by pressing the Stop button on the left USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C3 preliminary Ceusb3 Diagnostics t CES S Figure 6 Ceusb3 Diagnostics Benchmark API General Language compatibility The CEUSB3 API is designed to work with C native code to ensure best performance Due to the wide popularity the library is compatible with Visual C 7 1 and higher versions In addition to this a wrapper for the NET Framework 1 1 is also available so applications written in C NET C and Visual Basic have access to the API too The NET wrapper consists of the same classes and methods as the C API but global functions macros and constants are encapsulated in an additional class ceUSB3API based on the fact that NET doesn t support this Furthermore some data types are not available in all languages so a few of the parameters have a different value type in the C and NET API The best place to analyze the differences are the sample sources that ship with the API The test appl
11. with 8 bit address 2 FIFO read write Entity gpif interface This entity encapsulates all functionality which is needed for USB transfers over FX 2 USB Controller s GPIF It is strongly recommended not to modify neither this module nor any other underlying entity There are two groups of port signals One group contains the system input signals IFCLK i RESET i and the GPIF control signals which are labeled with the prefix GPIF_ These signals must be connected directly to the appropriate FPGA Pins in the top level entity The other group contains the system output signals clk o rst o and the user control signals which are labeled with the prefix app Only this one is needed for USB transfers in user applications All user control signals are synchronous to clk o For every interface in this group you will find an appropriate function in the C C API port s function s notes rst_o ResetFPGA pulses rst_o clk_o SetGPIFSpeed changes clk_o frequency between 30 MHz and 48 MHz USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 D2 preliminary port s function s notes app_we_o ReadRegister single read write with 8 bit app_adr_o 7 downto 0 WriteRegister address the LSBs of the app_data_o 15 downto 0 address are used app_data_i 15 downto 0 app_fifo_wr_i ReadBulk FIFO transfer FPGA gt app_fifo_data_i 15 downto 0 HOST app_fifo_full_o app_fifo_wr_co
12. 48 FPGA Pin 147 13 FPGA I O Pin 146 FPGA Pin 145 FPGA I O Pin 144 14 V FPGA IN Pin 142 FPGA I O Pin 9 FPGA I O Pin 139 15 FPGA I O Pin 138 FPGA I O Pin 137 V FPGAIN Pin 136 16 FPGA I O Pin 135 FPGA I O Pin 134 FPGA I O Pin 133 17 FPGA I O Pin 132 V FPGAIN Pin 130 FPGA I O Pin 129 18 FPGA I O Pin 128 FPGA I O Pin 127 FPGA I O Pin 126 19 V FPGA IN Pin 124 FPGA I O Pin 123 FPGA I O Pin 122 20 FPGA I O Pin 120 FPGA I O Pin 119 V FPGA IN Pin 118 21 FPGA I O Pin 116 FPGA I O Pin 115 FPGA I O Pin 113 22 GND GND GND 23 FPGA I O Pin 112 V FPGAIN Pin 110 FPGA Pin 109 24 FPGA I O Pin 108 FPGA I O Pin 107 FPGA Pin 106 25 FPGA I O Pin 55 FPGA I O Pin 61 FPGA Pin 62 26 FPGA I O Pin 63 FPGA I O Pin 64 FPGA I O Pin 65 27 FPGA I O Pin 68 FPGA I O Pin 69 V FPGA I O Pin 28 VY FPGA I O Pin 72 FPGA I O Pin 90 FPGA I O Pin 91 29 FPGA I O Pin 93 FPGA I O Pin 94 FPGA Pin 96 30 FPGA I O Pin 97 FPGA I O Pin 98 VY FPGA I O Pin 101 31 FPGA I O Pin 99 FPGA I O Pin 100 FPGA I O Pin 102 32 GND GND GND USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 B6 preliminary V5EXT If Jumper J1 is set to Position 1 2 self powered mode a 5 VDC power supply must be connected here For bus powered applications this pins can be left unconnected V3 This pin is connected to the 3 3 Volt power supply of the board Depending on the loaded FPGA design it can source up to 200 mA Attention This pin is also connected to the on boar
13. 6 or 0 pucData C HRESULT ceDevice WriteRegister ushort usAddress ushort amp usValue NET Int32 ceDevice WriteRegister UInt16 usAddress ref UInt16 usValue Info Write value usValue to FPGA register usAddress Returns Error code Errors amp DR no error E OPEN device not open E RAIL call to driver fails class celnfo C const char ceInfo GetDeviceName NET String ceInfo GetDeviceName Info Returns the name of the device Same name as listed in the device manager Returns Requested information Errors USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 C14 preliminary C const char ceInfo GetDevicePath NET String ceInfo GetDevicePath Info Returns the internal name of windows path to the device For informational purposes only Returns Requested information Errors C const char ceInfo GetDriverInfo NET String ceInfo GetDriverInfo Info Returns the description and version of the used driver For informational purposes only Returns Requested information Errors C const char ceInfo GetFirmwareInfo NET String ceInfo GetFirmwareInfo Info Returns the description and version of the used firmware For informational purposes only Returns Requested information Errors C const char
14. CES S USB3FPGA V 1 41 February 26 2008 User Manual C 1030 2805 SPARTAN 3E FPGA board with USB 2 0 interface Order number C 1030 2805 1 E _ oo USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 preliminary Copyright information Copyright 2007 CESYS GmbH All Rights Reserved The information in this document is proprietary to CESYS GmbH No part of this document may be reproduced in any form or by any means or used to make derivative work such as translation transformation or adaptation without written permission from CESYS GmbH CESYS GmbH provides this documentation without warranty term or condition of any kind either express or implied including but not limited to express and implied warranties of merchantability fitness for a particular purpose and non infringement While the information contained herein is believed to be accurate such information is preliminary and no representations or warranties of accuracy or completeness are made In no event will CESYS GmbH be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document CESYS GmbH will make improvements or changes in the product s and or program s described in this documentation at any time CESYS GmbH retains the right to make changes to this product at any time without notice Products may have mino
15. IR OR CORRECTION IN NO EVENT WILL THE COPYRIGHT HOLDER BE LIABLE TO YOU FOR DAMAGES INCLUDING ANY GENERAL SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THIS SOURCECODE INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THIS SOURCECODE TO OPERATE WITH ANY OTHER SOFTWARE PROGRAMS HARDWARE CIRCUITS OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN EVEN IF THE COPYRIGHT HOLDER HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 D 1 preliminary Files src gpif_interface vhd module with application interface port src sync fifo 1Kx16 vhd synchronous FIFO used within gpif interface vhd src demo application vhd example for using gpif interface vhd demo application ucf pinout and timing constraints needed for the GPIF gpif interface ise project file for ISE vers 9 1 03i demo application bin binary configuration file of demo application vhd after synthesis check ISE gt process Generate Programming File Properties General Options gt Create Binary Configuration File for using bin files Modules For user applications with USB transfer only the modules gpif interface vhd sync fifo 1Kx16 vhd and the constraints from demo application ucf are needed Two types of transfers are supported 1 Single read write
16. SB3FPGA driver via Windows XP installation guide from included driver and utilities CD 3 With Windows XP USB3FPGA device driver has to be installed twice 4 Locate folder bin on shipped CD and double click diag exe By pressing the Memory Test button on the left a first device test can be started USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 A2 preliminary B Hardware 2 Mbyte Fast SRAM 1M x 16 10ns N USB 2 0 conncetor High Speed USB 2 0 Peripheral controller 8 o ce ac FPGA Wo 2 D gt Clock Reset and Power Figure 1 USB3FPGA block diagram SPARTAN 3E FPGA Device System Gates CLB Rows CLB Columns Total CLBs Total Slices Distributed RAM bits Block RAM bits Dedicated Multipliers DCMs XC3S500E 4PQ208C 500k 46 34 1164 4 656 73 360 k 20 For details on SPARTAN 3E FPGA please refer to data sheet at http www xilinx com support documentation data_sheets ds312 pdf USB3FPGA C 1030 2805 User Manual V 1 41 www cesys com B 1 preliminary Connector diagram
17. as 1023 entries for 16 bit words The FIFO levels are reported by the signals app wr count o and app fifo rd count o Entity demo application This entity connects the external ports of the module gpif interface to the top level ports of the FPGA design Register read write bulk read write and simple operations LED on off are demonstrated here There is a switch between data loopback and infinite data source sink for bulk transfers The bulk transfer from and to onboard SRAM over USB is demonstrated as well Start and stop SRAM addresses and data direction are defined by register writes Then a finite state machine copies the data from FIFOs to SRAM and vice versa USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 D3 preliminary Waveforms ee app_we_o app adr o TTX S HH S app data X_D_XLL LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL app data i L LLLLLLLLLLLLLLLLLLLLLLX_ WIU Figure 7 Single Read Write clk o app fifo wr i app fifo data i app full o app fifo wr count o This waveform demonstrates the behavior of app fifo full and app wr count o when there is no transaction on the USB controller side of the FIFO During simultaneous FIFO read and FIFO write transactions the signals do not change The signal app fifo full o will be cleared and app wr count o will decrease if there are read transactions on the USB controller side but no write tran
18. ase contact CESYS if you need this clock USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 7 preliminary RESET The RESET signal can be used as an active high input to reset the whole design It is active during FPGA configuration and for a few milliseconds after configuration has finished It also can get activated by the Host software FPGA JTAG port The JTAG port of the SPARTAN 3E FPGA is accessible through connector CON2 This 14 pin connector can be used with XILINX download cables Although configuration of the FPGA can be made via USB many other tools i e ChipScope require JTAG CON2 JTAG connector Pin 1 3 5 7 9 11 13 GND Pin 2 2 5 Volt Pin 4 TMS Pin 6 TCK Pin 8 TDO Pin 10 TDI Pin 12 14 Not connected Attention Don t connect JTAG adapters that use 3 3 Volt signaling The FPGA only accepts 2 5 Volt signal levels Memory interface CESYS USB3FPGA is equipped with 2MByte of FAST SRAM 1M x 16 10ns CYPRESS CY7C1061AV33 10ZC This type of memory is static This means it can be used very easily because it does not need refresh bank management address multiplexing or other techniques known from dynamic memories The access time is 10ns The maximum data rate is 200 MByte s FPGA lt gt Memory interface SRAM signal name FPGA pin number RAM 0 FPGA I O Pin 189 RAM_A1 FPGA Pin 192 RAM_A2 FPGA I O Pin 196 RAM_A3 FPGA I O Pin 199
19. async I O will be used Using synced I O uiTransfered will return the count of bytes transferred which can be unequal to the requested transfer count otherwise this return value is undefined To specify a special pipe for the transfer uiPipe can be used but in most cases a value of Oxffffffff let the API decide the best pipe The last parameter uiTimeOut is only valid using synced I O a timeout for transfer completion in milliseconds can be specified here Returns Error code Errors ELTE no error E OPEN device not open E FAIL call to driver fails E INVALIDARG invalid data ptr uiSize 0 or uiSize not dividable by 512 E NOPIPE no matching pipe found uiPipe USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C13 preliminary invaligd E TIMEOUT call is tamed out eme E PENDING device is in pending mode async C HRESULT ceDevice WriteEeprom uint uiAddress uchar puchata Urne Uode NET Int32 ceDevice WriteEeprom uint uiAddress Byte pucData UINtS2 Wisize Info Writes data to on board EEPROM 7 KB are free for use starting at address 0 Maximum transfer size is 4 KB uiAddress sets the base offset pucData must hold the data while uiSize sets the count of bytes that should be transferred Returns Error code Errors S OK no error E OPEN device not open E BATE call to driver fails E INVALIDARG uiAddresstuiSize gt 7k uiSize gt 409
20. cernto GetHostController NET String ceInfo GetHostController Info Returns the description of the host controller this device is connected to For informational purposes only Returns Requested information Errors USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C15 preliminary C uint ceInfo GetPipeBufferSize NET UInt32 ceInfo GetPipeBufferSize Info Returns the buffer size of each pipe inside the driver This is the maximum count of bytes usable by block transfers via ReadBulk WriteBulk Returns Requested information Errors C uint ceInfo GetPipeCount NET UInt32 ceInfo GetPipeCount Info Count of pipes supported by the current host device interface For informational purposes only Returns Requested information Errors Cre const char celnfo GetUSBPath NET String ceInfo GetUSBPath Info Returns the connection path from device to host controller including any hub in between Used ports are enclosed in squared brackets in back of any hub Returns Requested information Errors C bool ceInfo GetUSBPath NET Boolean ceInfo GetUSBPath Info Returns true if the transfer between host and device is in highspeed mode 480MBit s false otherwise 15MBit s Returns Requested information E
21. d RAM It can only be used when the RAM is not needed and disabled by pulling RAM_CE high v Attention This pin can only be used as an Input to the FPGA Clock signals and RESET Clock signals FX2CLK FPGA IN GCLK9 Pin 184 FPGA Pin 103 IFCLK FPGA IN GCLK8 Pin 183 CLK50 FPGA I O GCLK10 Pin 185 CLK_optional FPGA I O GCLK11 Pin 186 RESET FPGA I O Pin 28 There are 4 clock sources on the USB3FPGA evaluation board No matter which of them you use as the main clock for your design you should synchronize all incoming asynchronous signals to it with at least one FlipFlop before using them internally If you fail to do so your design may work sometimes but not every time One hot state machines might lose their hot state and become inoperable Encoded state machines might enter wrong or illegal states FX2CLK This is the clock the USB controller FX2 uses internally and for its Program Data memory interface IFCLK This is the interface clock of the USB controller FX2 GPIF If you want to transmit or receive data using the USB interface it is the easiest way to choose this clock as the main clock source for your design It defaults to 48 MHz Its frequency can be switched to 30 MHz by the software See API documentation CLK50 The CLK50 clock signal is connected to a on board oscillator running at 50 MHz CLK optional The CLK optional clock signal is connected to an empty oscillator position Ple
22. eDevice SetGPIFSpeed ceGPIFSpeed Speed NET Int32 ceDevice SetGPIFSpeed ceDevice ceGPIFSpeed USB3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C12 preliminary Speed Info Allows the adjustment of the GPIF speed between 30 and 48 MHz Default value is 48 MHz It is not necessary to change this value except for some special cases Possible enumerators are CeGPIFS 30MHz eceGPIFS 48MHz Returns Error code Errors S OK no error E OPEN device not open E RAI call to driver fails E INVALIDARG uiPipeNumber out of range C HRESULT ceDevice WriteBulk uchar pucData uint E e uiSize uint amp uiTransfered ceAsyncHandle pH urne UNE Mi qe Cute NET Int32 ceDevice WriteBulk Byte pucData UInt32 uiSize ref UInt32 uiTransfered ref ceAsyncHandle pH UImnt32 ulPipe Ulnis2 uiruimeOut Info This function should be used to transfer huge blocks of data from host to device It is able to work in sync or async mode depending on the given parameters Parameter pucData should point to the buffer which contains the data to send while uiSize must be data count of bytes that should be transfered The maximum allowed count of bytes in one call can be retrieved by method GetPipeBufferSize from attached class celnfo use GetInfo to get it Furthermore this count must be even If pH is NULL than synced I O is active if pH is a valid async handle
23. ed in the following chapter Diagnostics Ceusb3 Diagnostics c C E WPlusb vid_10F88pid_c381 58f635d31 amp 085 53b029df bbc6 4db8 841e 69ce4F1 E3588 ReEnum Device List Device Info Download Design Dump EEPROM RBT to BIN Register I O Memory Test Benchmark Figure 4 Ceusb3 Diagnostics The list box on top of the window lists all available devices All device specific operations are bound to the device selected in this box After a change in the hardware configuration device plug unplug replug this list has to be re enumerated to ensure stability and functionality This can be done by simply pressing the ReEnum Device List button To get detailed information about a selected device a click on Device Info will print all known information to the log window below the device list box This includes information about the driver firmware hardware composition plus some software details The devices main functionality is given by the on board FPGA which must be configured to work which is not case after power on The configuration process is quite simply after clicking the Download Design button a file selection dialog will pop up the chosen file will be used to configure the FPGA after the selection Two file types are supported at the moment RBT raw bit streams and FPGA binary equivalents for raw bit streams creation described below The Dump EEPROM button will pop up a file se
24. hould point to a buffer that is able to hold the requested data while uiSize must be data count of bytes that should be received The maximum allowed count of bytes in one call can be retrieved by method GetPipeBufferSize from attached class celnfo use GetInfo to get it Furthermore this count must be dividable by 512 If pH is NULL than synced is active if pH is a valid async handle async I O will be used Using synced I O uiTransfered will return the count of bytes transferred which can be unequal to the requested transfer count otherwise this return value is undefined To specify a special pipe for the transfer uiPipe can be used but in most cases a value of Oxffffffff let the API decide the best pipe The last parameter uiTimeOut is only valid using synced I O a timeout for transfer completion in milliseconds can be specified here Returns Error code Errors S OK no error E OPEN device not open E EATE call po driver fails E INVALIDARG invalid data ptt Hisize 0 Or urogize mot dividable by 512 E NOPIPE no matching pipe found uiPipe invalid E TIMEOUT call if timed our sync E PENDING device is in pending mode async C HRESULT ceDevice ReadEeprom uint uiAddress uchar pu ucData uint 8 NET Int32 ceDevice ReadEeprom uint uiAddress Byte 55 udoixe Info Reads data from on board EEPROM 7 KB are free for use start
25. ication shows many parts from the API and is available in C native cntest C NET cnettest C cstest and VB vbtest Backward compatibility The CEUSB3 API is newly designed so there s no compatibility with API s from USB2FPGA or other devices USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 C4 preliminary ceUSB3 C API specs Basics The API contains the necessary library and include files To use the API you have to follow the steps below Include the main header file ceusb3api h Link the executable with the main library ceusb3api lib The whole API is located in namespace ceUSB3 so either tell the compiler to use this namespace using namespace ceUSB3 or scope all elements with this namespace separately e g ceUSB3 ceDevice pDev ceUSB3 ceDevice GetDevice 0 Pointers retrieved by the API must NOT be deleted this is done by the internally Affected classes are ceDevice and celnfo Error handling Most functions return a HRESULT code so you can use the SUCCEEDED and FAILED macros defined in the windows To retrieve a printable error string from a failed call use GetHRESULTMessage which returns the description string of a given error code Only error codes used by the ceUSB3 NET API specs Basics The API can be used by adding a new reference to the project choose the file browser there and select ceusb3apinet dll To be able to use the classes na
26. ing at address 0 Maximum transfer size is 4 KB uiAddress sets the base offset pucData should be huge enough to hold the requested data while uiSize sets the count of bytes that should be transferred Returns Error code USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 C11 preliminary Errors S_OK no error E_OPEN device not open E FAIL call to driver fails E INVALIDARG uiAddresstuiSize gt 7k uiSize gt 4096 or 0 pucData C HRESULT ceDevice ReadRegister ushort usAddress ushort amp usValue NET Int32 ceDevice ReadRegister UInt16 usAddress ref UInt16 usValue Info Read the value of FPGA register usAddress the result will be stored in usValue Returns Error code Errors o OR no error E OPEN device not open E FAIL call to driver fails C HRESULT ceDevice ResetFPGA NET Int32 ceDevice ResetFPGA Info Pulses the FPGA reset pin Returns Error code Errors 2 OR no error E OPEN device not open E FRI call to driver fails C HRESULT ceDevice ResetPipe uint uiPipeNumber NET Int32 ceDevice ResetPipe UInt32 uiPipeNumber Info Forces the USB bus driver to reset pipe number uiPipeNumber Returns Error code Errors S OK no error E OPEN device not open EPEAT call to driver fails E INVALIDARG uiPipeNumber out of range C HRESULT c
27. ion and should not be connected in user designs USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 B10 preliminary C Software Files The files which ships with our source package are sorted in subdirectories the structure is described below Folder Contains bin Compiled sample applications including the diagnostic tool diag exe which is can be used for simple tasks like device testing and FPGA configuration How to use it can be found later in this document designs Holds the generated design which is used for all of our sample applications including the diagnostic tool Source code can be found in the source folder doc All documentation including this document can be found here drivers System drivers for our device is located in this folder if the operating system asks for a driver point it to this folder source Source files for the FPGA and the host system mainly sample applications can be found in this folder in addition the API is located in subfolders lib and include Driver installation After plugging the device to a PC the first time the operating system in this case Windows XP will pop up an information about the detection of a new hardware As Windows doesn t know the USB3FPGA board it asks the user several questions to install the correct drivers for the device The steps are shortly described below In the first Dialog select the second option
28. lection dialog where users can choose a file where all EEPROM contents will be stored in a hexadecimal like text format As described above the design importer is able to use RBT and FPGA files The FPGA format is simply a binary representation for RBT files which are smaller than there RBT equivalents and they will be parsed much faster To create a FPGA out of a RBT a click on RBT to BIN will pop up a source selection dialog Afterwards a USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C2 preliminary destination file must be chosen in a second file selection dialog thats all the conversion should be done The Register button hides the log window and pops up additional controls to test the register read and write functionality based on the underlying FPGA design a compatible design must be downloaded The Write button writes the given value to the selected register just as the Read button reads the value from the selected register and displays the value in the Value field The Return button on the left return to normal functionality Ceusb3 Diagnostics C VPlusb vid_10F8 amp pid_c381 58 635d318085 53b029df bbc6 4db8 841e 69ce4f163588 Register 0x0000 Value 0x0000 Write Read Figure 5 Ceusb3 Diagnostics Register I O The 2 MB on board memory can be tested by pressing the Memory Test button A message box will pop up afterwards showing the results of
29. ly for downloading your design USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 B4 preliminary FPGA pin connections All FPGA VCCO Pins on the USB3FPGA board are connected to 3 3 Volt The I O pins of the SPARTAN 3E FPGA do NOT accept 5 Volt Input signals When 5 Volt signals are connected without proper level shifters or series resistors the FPGA will immediately become damaged When 3 3 Volt signals are used with long traces or cables in conjunction with improper termination the resulting overshoot and undershoot can damage the FPGA as well Please read Xilinx application note http direct xilinx com bvdocs appnotes xapp659 pdf for details Don t apply any voltage outside the interval 0 5V 3 8V not even for a few Nanoseconds Take care of overshoot undershoot conditions LEDs LEDs USER LED FPGA I O pin 140 Power LED FPGA is powered ON Config LED FPGA is configured PWR2 LED USB controller is powered ON Power LED lights up when the FPGA gets power PWR2 LED lights up when the board gets power from the USB bus Config LED lights up when the FPGA is configured successfully User LED light up when there is a low level at the corresponding FPGA Pin The meaning of this LEDs is defined by the user s FPGA design FPGA Testpins All FPGA pins are routed to testpoints to ease the connection of measurement equipment like Logic Analyzers The relationship between FPGA pins and Test
30. mespace cesys ceUSB3NET must be used the syntax is based on the NET language that is used Error handling Most functions return a System Int32 code the C macros for error checking are encapsulated in two static methods ceUSB3API ceSUCCEEDED and ceUSB3API ceFAILED In addition all possible error codes used by the API are defined as constants in that class ceUSBAPI ceS ceUSBAPI ceE To retrieve a printable error string from a failed call use ceUSB3API GetHRESULTMessage which returns the description string of a given error code Only error codes used by the API Additional differences to the C API Because NET doesn t support global functions Init and Delnit are encapsulated in class ceUSB3API too Furthermore Init doens t expect a GUID but a value from the ceUSB3API ceDeviceType enumeration USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C5 preliminary How to use the API Initialization Deinitialization To use the API it must be initialized this is done by a call to Init NET ceUSB3API Init This function searches for all devices plugged to the computer which matches the given GUID NET ceUSB3API ceDeviceType You can call this function with different GUID s which builds an internal list of all of them After using the API it must be freed this is done by calling Delnit NET ceUSB3API Delnit To detect any changes in the list of connected devices you have to call Delnit and
31. nector of the USB3FPGA allows connections to I O pins of the FPGA as well as to 3 3 V and GND Many extensions can be attached directly without the need of an additional external power supply Feature list XILINX XC3S500E 4PQ208C FPGA CYPRESS FX2LP USB controller 2MByte FAST SRAM 1M x 16 10ns connected to FPGA 64 kByte SRAM connected to USB 2 0 controller optional USB 2 0 compliant device Selectable self powered or bus powered Up to three individual onboard clock oscillators Expansion port 44 pins 15 INPUT pins 22 auxiliary pins 3 LEDS All FPGA Pins routed to test connectors Driver for Windows XP Firmware and Benchmark program included Sample code C Source of test program included Minimum requirements PC with USB 2 0 interface running Windows XP M 10 MByte free harddisk space M USB3FPGA board with USB2 0 compliant cable M CESYS USB 2 0 drivers USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 A 1 preliminary FPGA Design Tools To simulate and synthesize FPGA designs appropriate tools are needed Xilinx offers a toolset called ISE WebPack free of charge on their website http www xilinx com The ISE WebPack fully supports the XC3S500E Spartan3E FPGA There are also other commercial tools available from Xilinx and various other vendors Windows XP Quick start installation guide 1 Connect USB3FPGA to one free USB2 0 port with shipped USB2 0 compliant cable 2 Install U
32. points is printed on the USB3FPGA board and shown in the Connector Diagram above Expansion port CON1 The 96 pin VG96 abc reverse external expansion connector DIN 41612 is of type female Please use the connector diagram to indicate pin 1 On some connectors the numbers are printed upside down Mating connectors among others are RS Components 476 025 or Farnell 104 986 or HARTING order number 0903 196 7921 Most pins of the FPGA can be configured as input IN output OUT or bi directional I O Make sure your FPGA design does not drive pins that are already driven by external connected logic This is also important for bi directional signals USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 B5 preliminary CON1 96 pin VG Expansion connector Pin A B 1 V5EXT V5EXT V5EXT 2 GND GND GND 3 V3 V3 V3 4 FPGA I O Pin 199 FPGA I O Pin 197 FPGA I O Pin 196 5 V FPGA IN Pin 194 FPGA I O Pin 193 FPGA I O Pin 192 6 FPGA I O Pin 190 FPGA I O Pin 189 FPGA Pin 187 7 V FPGAIN Pin 175 V FPGAIN Pin 174 FPGA Pin 172 8 V FPGA IN Pin 169 FPGA Pin 168 FPGA Pin 167 9 FPGA Pin 161 FPGA Pin 160 V FPGAIN Pin 159 10 V FPGAIN Pin 6 V FPGA IN Pin 204 V FPGAIN Pin 154 11 FPGA Pin 153 FPGA Pin 152 FPGA Pin 151 12 FPGA Pin 150 V FPGAIN Pin 1
33. r variations to this publication known as errata CESYS GmbH assumes no liability whatsoever including infringement of any patent or copyright for sale and use of CESYS GmbH products CESYS GmbH and the CESYS logo are registered trademarks All product names are trademarks registered trademarks or service marks of their respective owner Please check www cesys com to get the latest version of this document CESYS Gesellschaft f r angewandte Mikroelektronik mbH Zeppelinstrasse 6a D 91074 Herzogenaurach Germany USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 preliminary A Overview Summary of USB3FPGA USB3FPGA can be used as a development platform for designs with Xilinx SPARTAN 3E FPGAs as well as a OEM component for job lot production A 96 pin VG connector allows the attachment of external hardware to the FPGA The board is equipped with a XC3S500E 4PQ208C XILINX FPGA a member of the Spartan 3E family This programmable logic device receives its internal functions after it has been configured by downloading a bitstream that represents the design The change of logic functions reconfiguration is possible at any time The bistream is loaded from the PC via USB to the FPGA The software that comes with the board permits to load new configurations anytime Two clock oscillators supply basic clocks that can be used by the FPGA A third clock oszillator can be populated on request The 96 pin VG expansion con
34. reb eee ee 17 class ceAsyncHandle oeiia eaea ai Ue aaa E a EE E EEE EEEE 18 DE a a ETAL EN E E A E 1 USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 F 1 preliminary FPGA source code copyright 1 FPGA source code nennen aa Dis laimer of AOT N E P M 2 DM es UE 2 Entity gpit AN MA ad EGA 2 Entity syne ne TEST uei obs 3 niece ITUR n 3 LLLI LaL M EU ME 4 Gode SAN NETTE 5 E Additional NeEwSgrOUpS eso CM PR cM qr DENN e TO 1 LII C NR aie sw nec ase cee es E Table GU DE DUI NI fe USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 F2 preliminary
35. roa ce pean Minimum TAN NETTE FPGA Design WOON agrees on acters eae bau E PE 2 Windows Quick start installation guide eeeeseseeeeeereennnnn 2 CEN GC ITE ORE 1 SFARTIANESE PPOR trc HII pr FEEDER Ion p pERU Rte pr IE EFE Sn I Ux ReE CP Pte Matemsaisiacionebenades 1 ConnecHrdidgrani NU UU 2 Board ayer DIE osse n urbe esed epp OC cR Oei CEU Eu RR MR REB 3 Power I e eicere Eee 3 4 FPGA DID GOBIHOO assets tt deca sends bap aede xta r ouem raa s an Ra NY ia ai 5 E LA 5 FPGA TESIPINS m mes 5 Ee dealt E RU Y TTE A i 5 Clock signals ang RESET er S Gal CES DN Duaci 7 RH 8 Memory IIIS LES 19 iere aa aain ee EGEE iea E EEE TO 0T 8 Undocumented RTT 10 a Nie mE Driver Iste aita iniaa eiea snc aaa eaaa a lei 1 DAMOS TTE E 2 BEL 4x M LIUM E E 4 ETC ENTE 4 CFt APLSPECS nee ee dumm 5 COLISBS MELBPISDBUS ipti oir eee rere ba E EE EA tees pus oup e Peters 5 How to use IDEAE pr eno a cite teda E dm eL i pne dpcd is 6 class COD OUS eue n t a aite nte e enn 8 SEES SEN 14 caet BI POE eos eter QU ird cenko E netu t Es pe
36. rrors USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C16 preliminary class ceFPGA This class is able to import and export different formats of FPGA designs This time rawbit RBT and binary streams FPGA cesys internally used format are supported Except ceDevice and celInfo this class has an public constructor and destructor so you have to take care about the lifetime of this object C CeFPGA ceFPGA NET CeFPGA ceFPGA Info Class constructor Returns Errors C ceFPGA ceFPGA NET Info Class destructor Returns Errors C HRESULT ceFPGA LoadBin const char pszFileName NET Int32 ceFPGA LoadBin String sFileName Info Load design from pszFileName sFileName using bin format importer created via SaveBin Returns Error Code Errors OR no error E OPEN can t open file E OUTOFMEMORY not enough memory available C HRESULT ceFPGA LoadRBT const char pszFileName NET Int32 ceFPGA LoadRBT String sFileName Info Load design from pszFileName sFileName using RBT format importer Returns Error Code Errors S OK no error E OPEN can t open file E FALL unknown format E OUTOFMEMORY not enough memory available USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C17 preliminary C HRESULT ceFPGA SaveBin const char pszFileName NET
37. rrors S_OK error E FAD general error E INVALIDARG pbComplete is NULL C HRESULT ceAsyncHandle Wait uint uiTimeOutMs NET Int32 ceAsyncHandle Wait uint uiTimeOutMs Info Wait uiTimeOutMs milliseconds for transfer completion Returns Error Code Errors S DE no error E FAIL genera Error E TIMEOUT operation has timed out USB3FPGA C 1030 2805 User Manual V 1 41 C 19 www cesys com preliminary D FPGA design FPGA source code copyright information This source code is copyrighted by CESYS GmbH GERMANY unless otherwise noted FPGA source code license THIS SOURCECODE IS NOT FREE IT IS FOR USE TOGETHER WITH THE CESYS USB3FPGA USB CARD ARTICLE NR C 1030 2805 ONLY YOU ARE NOT ALLOWED TO MODIFY AND DISTRIBUTE OR USE IT WITH ANY OTHER HARDWARE SOFTWARE OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT HOLDER Disclaimer of warranty THIS SOURCECODE IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL BUT THERE IS NO WARRANTY OR SUPPORT FOR THIS SOURCECODE THE COPYRIGHT HOLDER PROVIDES THIS SOURCECODE AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FORA PARTICULAR PURPOSE THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THIS SOURCECODE IS WITH YOU SHOULD THIS SOURCECODE PROVE DEFECTIVE YOU ASSUME THE COST OF ALL NECESSARY SERVICING REPA
38. s in alphabetic order All methods are listed twice the first one is the C native notation the other one is the NET counterpart in CZ notation USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C6 preliminary Global functions NET class ceUSB3API Crt void DeInit NET void ceUSB3API DeInit Info Frees all resources allocated by Init this must be called after using the Returns Errors C const char GetHRESULTMessage HRESULT hr NET String ceUSB3API GetHRESULTMessage System Int32 Nr Info Returns the error string bound to the given error code hr Returns Error string Errors C HRESULT Init const GUID amp Guid NET Int32 ceUSBAPI Init ceUSB3API DeviceType T Info Initializes the API and searches for devices with the given type via GUID or device type The function can be called multiple times with different types to enumerate and use different devices Resources allocated by that call must be freed by calling DeInit after use Possible GUID s C GUID INTERPACE CEUGE3 GUID INTERFACE PSAA4096V2 Possible Types NET ceDT CRUSE3 ceDT PSAA4096V2 Returns Error code Errors DR no error B error searching devices USBS3FPGA C 1030 2805 www cesys com User Manual V 1 41 C7 preliminary class ceDevice C HRESULT ceDevice AbortPipe uint uiPipeNumber NET In
39. sactions on the application side app fifo rd i app dat o 7 ZZZX 95 VZZLLLIX US X92 X e Koo 7777777 app fifo empty o app fifo rd count o Figure 9 FIFO Transfer HOST gt FPGA This waveform demonstrates the behavior of app fifo empty o and app fifo rd count o when there is no transaction on the USB controller side of the FIFO During simultaneous FIFO read and FIFO write transactions the signals do not change The signal app empty will be cleared and USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 D4 preliminary app_fifo_rd_count_o will increase if there are write transactions on the USB controller side but no read transactions on the application side Please note the one clock cycle delay between app_fifo_rd_i and app_fifo_data_o Code samples The following extracts of VHDL code shows you some possible implementations of single read write and FIFO transfer data communication type arr stdl6 is array natural range lt gt of std logic vector 15 downto 0 signal gp reg arr stdl6 3 downto 0 others gt others gt 0 inst goi intertace 3 pur imexiece port map ESE BE elk gt Elk app we o gt app we upper app data o gt app datao app data ii gt app datai apo Tito Wie L gt apo Fir wie apo tirto Cata i gt app tito atai appe tire cull aE o apo tito we COUME gt apo Firo _ wie CONE apo Tiro
40. t32 ceDevice AbortPipe UInt32 uiPipeNumber Info Forces the USB bus driver to abort the transfer on a given pipe uiPipeNumber Returns Error code Errors 5 no error E OPEN device not open E FAIL call to driver fails E INVALIDARG uiPipeNumber is out of range C void ceDevice Close NET void ceDevice Close Info Closes the device Returns Errors C HRESULT ceDevice GetAsyncResult ceAsyncHandle pH uint uiTransfered NET Int32 ceDevice GetAsyncResult ref ceAsyncHandle pH ref UInt32 uiTransfered This method is needed when using any of the following functions using the async call convention ReadBulk WriteBulk Usage After starting an async operation use the async handle pH to check if the transfer is complete Afterwards you have to call GetAsyncResult to cleanup the call and retrieve the count of bytes transferred via this operation uiTransfered A good example on how to use this can be found in the test application that ships with the API which is available in all supported languages Returns Error code Errors no error E FAILS the function fails E INVALIDARG pH is NULL USBS3FPGA C 1030 2805 WWW Cesys com User Manual V 1 41 C8 preliminary C ceDevice ceDevice GetDevice uint uildx NET ceDevice ceDevice GetDevice UInt32 uildx Info Returns a poin
41. ter to a device which is selected by a zero based index uiIdx This pointer is valid until DeInit is called Never try to delete this object this is done automatically Returns Pointer to device with the given index NULL otherwise Errors C uint ceDevice GetDeviceCount NET UInt32 ceDevice GetDeviceCount Info Returns the count of devices find during the call of Init if Init is called multiple times the total number is returned Returns Count of devices found in the system Errors C ceInfo ceDevice GetInfo NET ceInfo ceDevice GetInfo Info Returns a static pointer to a ceInfo class instance bound to the device This holds additional information about the device Never try to delete the returned object this is done by DeInit automatically Returns Pointer to info class Errors C uint ceDevice GetLastError NET UInt32 ceDevice GetLastError Info Returns the last error occurred in the driver This may help to find out unexpected errors Returns Driver error code Errors USB3FPGA C 1030 2805 www cesys com User Manual V 1 41 C9 preliminary C uint ceDevice GetLastFirmwareError NET UInt32 ceDevice GetLastFirmwareError Info Returns
42. unt_o 9 downto 0 app_fifo_rd_i WriteBulk FIFO trnasfer HOST gt app_fifo_data_o 15 downto 0 FPGA app_fifo_empty_o app fifo rd count o 9 downto 0 There is something special about the signal app usb short pkg inh i USB short package inhibit and the FIFO transfer from the FPGA to the HOST USB transfers are always package oriented If the FPGA design fills the FIFO slower than the USB controller reads out the data the maximum USB package size is not reached and the USB controller sends a short package to the HOST So in datastreaming applications a lot of short packages could be send which leads to a protocol overhead You can set the signal app usb short pkg inh i to logic 1 to avoid this effect and increase the transferrate If app usb short pkg inh i7 1 then the USB controller waits until the maximum USB package size is reached before sending the data to the HOST This feature should only be used for datastreams which never end Otherwise you could get a timeout in your ReadBulk function because the USB controller waits until the next package is complete which possibly never happens Please take a look at the waveforms and the sourcecode examples at the end of this document to find out how the other user control signals have to be used Entity sync fifo 1Kx16 This entity is a synchronous FIFO internally used in the module gpif interface Two of these FIFOs are used One for each direction Each FIFO h
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